2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
16 #include <mono/metadata/abi-details.h>
17 #include <mono/metadata/appdomain.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/utils/mono-mmap.h>
21 #include <mono/utils/mono-hwcap-arm.h>
22 #include <mono/utils/mono-memory-model.h>
25 #include "mini-arm-tls.h"
29 #include "debugger-agent.h"
31 #include "mono/arch/arm/arm-vfp-codegen.h"
33 #if (defined(HAVE_KW_THREAD) && defined(__linux__) && defined(__ARM_EABI__)) \
34 || defined(TARGET_ANDROID) \
35 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
39 /* Sanity check: This makes no sense */
40 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
41 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
45 * IS_SOFT_FLOAT: Is full software floating point used?
46 * IS_HARD_FLOAT: Is full hardware floating point used?
47 * IS_VFP: Is hardware floating point with software ABI used?
49 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
50 * IS_VFP may delegate to mono_arch_is_soft_float ().
53 #if defined(ARM_FPU_VFP_HARD)
54 #define IS_SOFT_FLOAT (FALSE)
55 #define IS_HARD_FLOAT (TRUE)
57 #elif defined(ARM_FPU_NONE)
58 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
59 #define IS_HARD_FLOAT (FALSE)
60 #define IS_VFP (!mono_arch_is_soft_float ())
62 #define IS_SOFT_FLOAT (FALSE)
63 #define IS_HARD_FLOAT (FALSE)
67 #define THUNK_SIZE (3 * 4)
69 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
72 void sys_icache_invalidate (void *start, size_t len);
75 /* This mutex protects architecture specific caches */
76 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
77 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
78 static mono_mutex_t mini_arch_mutex;
80 static gboolean v5_supported = FALSE;
81 static gboolean v6_supported = FALSE;
82 static gboolean v7_supported = FALSE;
83 static gboolean v7s_supported = FALSE;
84 static gboolean v7k_supported = FALSE;
85 static gboolean thumb_supported = FALSE;
86 static gboolean thumb2_supported = FALSE;
88 * Whenever to use the ARM EABI
90 static gboolean eabi_supported = FALSE;
93 * Whenever to use the iphone ABI extensions:
94 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
95 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
96 * This is required for debugging/profiling tools to work, but it has some overhead so it should
97 * only be turned on in debug builds.
99 static gboolean iphone_abi = FALSE;
102 * The FPU we are generating code for. This is NOT runtime configurable right now,
103 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
105 static MonoArmFPU arm_fpu;
107 #if defined(ARM_FPU_VFP_HARD)
109 * On armhf, d0-d7 are used for argument passing and d8-d15
110 * must be preserved across calls, which leaves us no room
111 * for scratch registers. So we use d14-d15 but back up their
112 * previous contents to a stack slot before using them - see
113 * mono_arm_emit_vfp_scratch_save/_restore ().
115 static int vfp_scratch1 = ARM_VFP_D14;
116 static int vfp_scratch2 = ARM_VFP_D15;
119 * On armel, d0-d7 do not need to be preserved, so we can
120 * freely make use of them as scratch registers.
122 static int vfp_scratch1 = ARM_VFP_D0;
123 static int vfp_scratch2 = ARM_VFP_D1;
128 static gpointer single_step_tramp, breakpoint_tramp;
131 * The code generated for sequence points reads from this location, which is
132 * made read-only when single stepping is enabled.
134 static gpointer ss_trigger_page;
136 /* Enabled breakpoints read from this trigger page */
137 static gpointer bp_trigger_page;
141 * floating point support: on ARM it is a mess, there are at least 3
142 * different setups, each of which binary incompat with the other.
143 * 1) FPA: old and ugly, but unfortunately what current distros use
144 * the double binary format has the two words swapped. 8 double registers.
145 * Implemented usually by kernel emulation.
146 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
147 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
148 * 3) VFP: the new and actually sensible and useful FP support. Implemented
149 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
151 * We do not care about FPA. We will support soft float and VFP.
153 int mono_exc_esp_offset = 0;
155 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
156 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
157 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
159 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
160 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
161 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
163 //#define DEBUG_IMT 0
166 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
170 mono_arch_regname (int reg)
172 static const char * rnames[] = {
173 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
174 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
175 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
178 if (reg >= 0 && reg < 16)
184 mono_arch_fregname (int reg)
186 static const char * rnames[] = {
187 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
188 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
189 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
190 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
191 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
192 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
195 if (reg >= 0 && reg < 32)
203 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
205 int imm8, rot_amount;
206 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
207 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
211 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
212 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
214 code = mono_arm_emit_load_imm (code, dreg, imm);
215 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
220 /* If dreg == sreg, this clobbers IP */
222 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
224 int imm8, rot_amount;
225 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
226 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
230 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
231 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
233 code = mono_arm_emit_load_imm (code, dreg, imm);
234 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
240 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
242 /* we can use r0-r3, since this is called only for incoming args on the stack */
243 if (size > sizeof (gpointer) * 4) {
245 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
246 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
247 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
248 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
249 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
250 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
251 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
252 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
253 ARM_B_COND (code, ARMCOND_NE, 0);
254 arm_patch (code - 4, start_loop);
257 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
258 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
260 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
261 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
267 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
268 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
269 doffset = soffset = 0;
271 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
272 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
278 g_assert (size == 0);
283 emit_call_reg (guint8 *code, int reg)
286 ARM_BLX_REG (code, reg);
288 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
292 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
298 emit_call_seq (MonoCompile *cfg, guint8 *code)
300 if (cfg->method->dynamic) {
301 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
303 *(gpointer*)code = NULL;
305 code = emit_call_reg (code, ARMREG_IP);
309 cfg->thunk_area += THUNK_SIZE;
314 mono_arm_patchable_b (guint8 *code, int cond)
316 ARM_B_COND (code, cond, 0);
321 mono_arm_patchable_bl (guint8 *code, int cond)
323 ARM_BL_COND (code, cond, 0);
328 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
331 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
332 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
334 code = emit_call_seq (cfg, code);
335 if (dreg != ARMREG_R0)
336 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
338 g_assert_not_reached ();
344 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
347 if (tls_offset_reg != ARMREG_R0)
348 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
349 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
351 code = emit_call_seq (cfg, code);
352 if (dreg != ARMREG_R0)
353 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
355 g_assert_not_reached ();
361 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
364 if (sreg != ARMREG_R1)
365 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
366 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
367 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
369 code = emit_call_seq (cfg, code);
371 g_assert_not_reached ();
377 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
380 /* Get sreg in R1 and tls_offset_reg in R0 */
381 if (tls_offset_reg == ARMREG_R1) {
382 if (sreg == ARMREG_R0) {
383 /* swap sreg and tls_offset_reg */
384 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
385 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
386 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
388 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
389 if (sreg != ARMREG_R1)
390 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
393 if (sreg != ARMREG_R1)
394 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
395 if (tls_offset_reg != ARMREG_R0)
396 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
398 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
400 code = emit_call_seq (cfg, code);
402 g_assert_not_reached ();
410 * Emit code to push an LMF structure on the LMF stack.
411 * On arm, this is intermixed with the initialization of other fields of the structure.
414 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
416 gboolean get_lmf_fast = FALSE;
419 if (mono_arm_have_tls_get ()) {
421 if (cfg->compile_aot) {
423 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
424 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
426 *(gpointer*)code = NULL;
428 /* Load the value from the GOT */
429 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
430 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
432 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
433 g_assert (lmf_addr_tls_offset != -1);
434 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
439 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
440 (gpointer)"mono_get_lmf_addr");
441 code = emit_call_seq (cfg, code);
443 /* we build the MonoLMF structure on the stack - see mini-arm.h */
444 /* lmf_offset is the offset from the previous stack pointer,
445 * alloc_size is the total stack space allocated, so the offset
446 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
447 * The pointer to the struct is put in r1 (new_lmf).
448 * ip is used as scratch
449 * The callee-saved registers are already in the MonoLMF structure
451 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
452 /* r0 is the result from mono_get_lmf_addr () */
453 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
454 /* new_lmf->previous_lmf = *lmf_addr */
455 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
456 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
457 /* *(lmf_addr) = r1 */
458 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
459 /* Skip method (only needed for trampoline LMF frames) */
460 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
461 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
462 /* save the current IP */
463 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
464 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
466 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
467 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
478 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
482 for (list = inst->float_args; list; list = list->next) {
483 FloatArgData *fad = list->data;
484 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
485 gboolean imm = arm_is_fpimm8 (var->inst_offset);
487 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
493 if (*offset + *max_len > cfg->code_size) {
494 cfg->code_size += *max_len;
495 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
497 code = cfg->native_code + *offset;
501 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
502 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
504 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
506 *offset = code - cfg->native_code;
513 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
517 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
519 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
522 if (!arm_is_fpimm8 (inst->inst_offset)) {
523 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
524 ARM_FSTD (code, reg, ARMREG_LR, 0);
526 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
533 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
537 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
539 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
542 if (!arm_is_fpimm8 (inst->inst_offset)) {
543 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
544 ARM_FLDD (code, reg, ARMREG_LR, 0);
546 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
555 * Emit code to pop an LMF structure from the LMF stack.
558 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
562 if (lmf_offset < 32) {
563 basereg = cfg->frame_reg;
568 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
571 /* ip = previous_lmf */
572 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
574 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
575 /* *(lmf_addr) = previous_lmf */
576 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
581 #endif /* #ifndef DISABLE_JIT */
584 * mono_arm_have_tls_get:
586 * Returns whether we have tls access implemented on the current
590 mono_arm_have_tls_get (void)
600 * mono_arch_get_argument_info:
601 * @csig: a method signature
602 * @param_count: the number of parameters to consider
603 * @arg_info: an array to store the result infos
605 * Gathers information on parameters such as size, alignment and
606 * padding. arg_info should be large enought to hold param_count + 1 entries.
608 * Returns the size of the activation frame.
611 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
613 int k, frame_size = 0;
614 guint32 size, align, pad;
618 t = mini_get_underlying_type (csig->ret);
619 if (MONO_TYPE_ISSTRUCT (t)) {
620 frame_size += sizeof (gpointer);
624 arg_info [0].offset = offset;
627 frame_size += sizeof (gpointer);
631 arg_info [0].size = frame_size;
633 for (k = 0; k < param_count; k++) {
634 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
636 /* ignore alignment for now */
639 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
640 arg_info [k].pad = pad;
642 arg_info [k + 1].pad = 0;
643 arg_info [k + 1].size = size;
645 arg_info [k + 1].offset = offset;
649 align = MONO_ARCH_FRAME_ALIGNMENT;
650 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
651 arg_info [k].pad = pad;
656 #define MAX_ARCH_DELEGATE_PARAMS 3
659 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
661 guint8 *code, *start;
662 GSList *unwind_ops = mono_arch_get_cie_program ();
665 start = code = mono_global_codeman_reserve (12);
667 /* Replace the this argument with the target */
668 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
669 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
670 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
672 g_assert ((code - start) <= 12);
674 mono_arch_flush_icache (start, 12);
678 size = 8 + param_count * 4;
679 start = code = mono_global_codeman_reserve (size);
681 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
682 /* slide down the arguments */
683 for (i = 0; i < param_count; ++i) {
684 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
686 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
688 g_assert ((code - start) <= size);
690 mono_arch_flush_icache (start, size);
694 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
696 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
697 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
701 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
707 * mono_arch_get_delegate_invoke_impls:
709 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
713 mono_arch_get_delegate_invoke_impls (void)
719 get_delegate_invoke_impl (&info, TRUE, 0);
720 res = g_slist_prepend (res, info);
722 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
723 get_delegate_invoke_impl (&info, FALSE, i);
724 res = g_slist_prepend (res, info);
731 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
733 guint8 *code, *start;
736 /* FIXME: Support more cases */
737 sig_ret = mini_get_underlying_type (sig->ret);
738 if (MONO_TYPE_ISSTRUCT (sig_ret))
742 static guint8* cached = NULL;
743 mono_mini_arch_lock ();
745 mono_mini_arch_unlock ();
750 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
753 start = get_delegate_invoke_impl (&info, TRUE, 0);
754 mono_tramp_info_register (info, NULL);
757 mono_mini_arch_unlock ();
760 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
763 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
765 for (i = 0; i < sig->param_count; ++i)
766 if (!mono_is_regsize_var (sig->params [i]))
769 mono_mini_arch_lock ();
770 code = cache [sig->param_count];
772 mono_mini_arch_unlock ();
777 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
778 start = mono_aot_get_trampoline (name);
782 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
783 mono_tramp_info_register (info, NULL);
785 cache [sig->param_count] = start;
786 mono_mini_arch_unlock ();
794 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
800 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
802 return (gpointer)regs [ARMREG_R0];
806 * Initialize the cpu to execute managed code.
809 mono_arch_cpu_init (void)
811 i8_align = MONO_ABI_ALIGNOF (gint64);
812 #ifdef MONO_CROSS_COMPILE
813 /* Need to set the alignment of i8 since it can different on the target */
814 #ifdef TARGET_ANDROID
816 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
822 * Initialize architecture specific code.
825 mono_arch_init (void)
827 const char *cpu_arch;
829 mono_os_mutex_init_recursive (&mini_arch_mutex);
830 if (mini_get_debug_options ()->soft_breakpoints) {
831 breakpoint_tramp = mini_get_breakpoint_trampoline ();
833 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
834 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
835 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
838 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
839 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
840 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
841 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
842 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
844 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
846 #if defined(__ARM_EABI__)
847 eabi_supported = TRUE;
850 #if defined(ARM_FPU_VFP_HARD)
851 arm_fpu = MONO_ARM_FPU_VFP_HARD;
853 arm_fpu = MONO_ARM_FPU_VFP;
855 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
857 * If we're compiling with a soft float fallback and it
858 * turns out that no VFP unit is available, we need to
859 * switch to soft float. We don't do this for iOS, since
860 * iOS devices always have a VFP unit.
862 if (!mono_hwcap_arm_has_vfp)
863 arm_fpu = MONO_ARM_FPU_NONE;
866 * This environment variable can be useful in testing
867 * environments to make sure the soft float fallback
868 * works. Most ARM devices have VFP units these days, so
869 * normally soft float code would not be exercised much.
871 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
873 if (soft && !strncmp (soft, "1", 1))
874 arm_fpu = MONO_ARM_FPU_NONE;
878 v5_supported = mono_hwcap_arm_is_v5;
879 v6_supported = mono_hwcap_arm_is_v6;
880 v7_supported = mono_hwcap_arm_is_v7;
882 #if defined(__APPLE__)
883 /* iOS is special-cased here because we don't yet
884 have a way to properly detect CPU features on it. */
885 thumb_supported = TRUE;
888 thumb_supported = mono_hwcap_arm_has_thumb;
889 thumb2_supported = mono_hwcap_arm_has_thumb2;
892 /* Format: armv(5|6|7[s])[-thumb[2]] */
893 cpu_arch = g_getenv ("MONO_CPU_ARCH");
895 /* Do this here so it overrides any detection. */
897 if (strncmp (cpu_arch, "armv", 4) == 0) {
898 v5_supported = cpu_arch [4] >= '5';
899 v6_supported = cpu_arch [4] >= '6';
900 v7_supported = cpu_arch [4] >= '7';
901 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
902 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
905 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
906 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
911 * Cleanup architecture specific code.
914 mono_arch_cleanup (void)
919 * This function returns the optimizations supported on this cpu.
922 mono_arch_cpu_optimizations (guint32 *exclude_mask)
924 /* no arm-specific optimizations yet */
930 * This function test for all SIMD functions supported.
932 * Returns a bitmask corresponding to all supported versions.
936 mono_arch_cpu_enumerate_simd_versions (void)
938 /* SIMD is currently unimplemented */
943 mono_arm_is_hard_float (void)
945 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
951 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
953 if (v7s_supported || v7k_supported) {
967 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
969 mono_arch_is_soft_float (void)
971 return arm_fpu == MONO_ARM_FPU_NONE;
976 is_regsize_var (MonoType *t)
980 t = mini_get_underlying_type (t);
987 case MONO_TYPE_FNPTR:
989 case MONO_TYPE_OBJECT:
990 case MONO_TYPE_STRING:
991 case MONO_TYPE_CLASS:
992 case MONO_TYPE_SZARRAY:
993 case MONO_TYPE_ARRAY:
995 case MONO_TYPE_GENERICINST:
996 if (!mono_type_generic_inst_is_valuetype (t))
999 case MONO_TYPE_VALUETYPE:
1006 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1011 for (i = 0; i < cfg->num_varinfo; i++) {
1012 MonoInst *ins = cfg->varinfo [i];
1013 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1016 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1019 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1022 /* we can only allocate 32 bit values */
1023 if (is_regsize_var (ins->inst_vtype)) {
1024 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1025 g_assert (i == vmv->idx);
1026 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1034 mono_arch_get_global_int_regs (MonoCompile *cfg)
1038 mono_arch_compute_omit_fp (cfg);
1041 * FIXME: Interface calls might go through a static rgctx trampoline which
1042 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1045 if (cfg->flags & MONO_CFG_HAS_CALLS)
1046 cfg->uses_rgctx_reg = TRUE;
1048 if (cfg->arch.omit_fp)
1049 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1050 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1051 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1052 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1054 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1055 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1057 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1058 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1059 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1060 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1061 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1062 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1068 * mono_arch_regalloc_cost:
1070 * Return the cost, in number of memory references, of the action of
1071 * allocating the variable VMV into a register during global register
1075 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1081 #endif /* #ifndef DISABLE_JIT */
1084 mono_arch_flush_icache (guint8 *code, gint size)
1086 #if defined(MONO_CROSS_COMPILE)
1088 sys_icache_invalidate (code, size);
1090 __builtin___clear_cache (code, code + size);
1097 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1100 if (*gr > ARMREG_R3) {
1102 ainfo->offset = *stack_size;
1103 ainfo->reg = ARMREG_SP; /* in the caller */
1104 ainfo->storage = RegTypeBase;
1107 ainfo->storage = RegTypeGeneral;
1114 split = i8_align == 4;
1119 if (*gr == ARMREG_R3 && split) {
1120 /* first word in r3 and the second on the stack */
1121 ainfo->offset = *stack_size;
1122 ainfo->reg = ARMREG_SP; /* in the caller */
1123 ainfo->storage = RegTypeBaseGen;
1125 } else if (*gr >= ARMREG_R3) {
1126 if (eabi_supported) {
1127 /* darwin aligns longs to 4 byte only */
1128 if (i8_align == 8) {
1133 ainfo->offset = *stack_size;
1134 ainfo->reg = ARMREG_SP; /* in the caller */
1135 ainfo->storage = RegTypeBase;
1138 if (eabi_supported) {
1139 if (i8_align == 8 && ((*gr) & 1))
1142 ainfo->storage = RegTypeIRegPair;
1151 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1154 * If we're calling a function like this:
1156 * void foo(float a, double b, float c)
1158 * We pass a in s0 and b in d1. That leaves us
1159 * with s1 being unused. The armhf ABI recognizes
1160 * this and requires register assignment to then
1161 * use that for the next single-precision arg,
1162 * i.e. c in this example. So float_spare either
1163 * tells us which reg to use for the next single-
1164 * precision arg, or it's -1, meaning use *fpr.
1166 * Note that even though most of the JIT speaks
1167 * double-precision, fpr represents single-
1168 * precision registers.
1170 * See parts 5.5 and 6.1.2 of the AAPCS for how
1174 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1175 ainfo->storage = RegTypeFP;
1179 * If we're passing a double-precision value
1180 * and *fpr is odd (e.g. it's s1, s3, ...)
1181 * we need to use the next even register. So
1182 * we mark the current *fpr as a spare that
1183 * can be used for the next single-precision
1187 *float_spare = *fpr;
1192 * At this point, we have an even register
1193 * so we assign that and move along.
1197 } else if (*float_spare >= 0) {
1199 * We're passing a single-precision value
1200 * and it looks like a spare single-
1201 * precision register is available. Let's
1205 ainfo->reg = *float_spare;
1209 * If we hit this branch, we're passing a
1210 * single-precision value and we can simply
1211 * use the next available register.
1219 * We've exhausted available floating point
1220 * regs, so pass the rest on the stack.
1228 ainfo->offset = *stack_size;
1229 ainfo->reg = ARMREG_SP;
1230 ainfo->storage = RegTypeBase;
1237 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1241 MonoClassField *field;
1242 MonoType *ftype, *prev_ftype = NULL;
1245 klass = mono_class_from_mono_type (t);
1247 while ((field = mono_class_get_fields (klass, &iter))) {
1248 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1250 ftype = mono_field_get_type (field);
1251 ftype = mini_get_underlying_type (ftype);
1253 if (MONO_TYPE_ISSTRUCT (ftype)) {
1254 int nested_nfields, nested_esize;
1256 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1258 if (nested_esize == 4)
1259 ftype = &mono_defaults.single_class->byval_arg;
1261 ftype = &mono_defaults.double_class->byval_arg;
1262 if (prev_ftype && prev_ftype->type != ftype->type)
1265 nfields += nested_nfields;
1267 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1269 if (prev_ftype && prev_ftype->type != ftype->type)
1275 if (nfields == 0 || nfields > 4)
1277 *out_nfields = nfields;
1278 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1283 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1285 guint i, gr, fpr, pstart;
1287 int n = sig->hasthis + sig->param_count;
1291 guint32 stack_size = 0;
1293 gboolean is_pinvoke = sig->pinvoke;
1294 gboolean vtype_retaddr = FALSE;
1297 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1299 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1306 t = mini_get_underlying_type (sig->ret);
1317 case MONO_TYPE_FNPTR:
1318 case MONO_TYPE_CLASS:
1319 case MONO_TYPE_OBJECT:
1320 case MONO_TYPE_SZARRAY:
1321 case MONO_TYPE_ARRAY:
1322 case MONO_TYPE_STRING:
1323 cinfo->ret.storage = RegTypeGeneral;
1324 cinfo->ret.reg = ARMREG_R0;
1328 cinfo->ret.storage = RegTypeIRegPair;
1329 cinfo->ret.reg = ARMREG_R0;
1333 cinfo->ret.storage = RegTypeFP;
1335 if (t->type == MONO_TYPE_R4)
1336 cinfo->ret.size = 4;
1338 cinfo->ret.size = 8;
1340 if (IS_HARD_FLOAT) {
1341 cinfo->ret.reg = ARM_VFP_F0;
1343 cinfo->ret.reg = ARMREG_R0;
1346 case MONO_TYPE_GENERICINST:
1347 if (!mono_type_generic_inst_is_valuetype (t)) {
1348 cinfo->ret.storage = RegTypeGeneral;
1349 cinfo->ret.reg = ARMREG_R0;
1352 if (mini_is_gsharedvt_variable_type (t)) {
1353 cinfo->ret.storage = RegTypeStructByAddr;
1357 case MONO_TYPE_VALUETYPE:
1358 case MONO_TYPE_TYPEDBYREF:
1359 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1360 cinfo->ret.storage = RegTypeHFA;
1362 cinfo->ret.nregs = nfields;
1363 cinfo->ret.esize = esize;
1366 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1369 #ifdef TARGET_WATCHOS
1374 if (native_size <= max_size) {
1375 cinfo->ret.storage = RegTypeStructByVal;
1376 cinfo->ret.struct_size = native_size;
1377 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1379 cinfo->ret.storage = RegTypeStructByAddr;
1382 cinfo->ret.storage = RegTypeStructByAddr;
1387 case MONO_TYPE_MVAR:
1388 g_assert (mini_is_gsharedvt_type (t));
1389 cinfo->ret.storage = RegTypeStructByAddr;
1391 case MONO_TYPE_VOID:
1394 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1397 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1402 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1403 * the first argument, allowing 'this' to be always passed in the first arg reg.
1404 * Also do this if the first argument is a reference type, since virtual calls
1405 * are sometimes made using calli without sig->hasthis set, like in the delegate
1408 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1410 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1412 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1416 cinfo->ret.reg = gr;
1418 cinfo->vret_arg_index = 1;
1422 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1425 if (vtype_retaddr) {
1426 cinfo->ret.reg = gr;
1431 DEBUG(g_print("params: %d\n", sig->param_count));
1432 for (i = pstart; i < sig->param_count; ++i) {
1433 ArgInfo *ainfo = &cinfo->args [n];
1435 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1436 /* Prevent implicit arguments and sig_cookie from
1437 being passed in registers */
1440 /* Emit the signature cookie just before the implicit arguments */
1441 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1443 DEBUG(g_print("param %d: ", i));
1444 if (sig->params [i]->byref) {
1445 DEBUG(g_print("byref\n"));
1446 add_general (&gr, &stack_size, ainfo, TRUE);
1450 t = mini_get_underlying_type (sig->params [i]);
1454 cinfo->args [n].size = 1;
1455 add_general (&gr, &stack_size, ainfo, TRUE);
1459 cinfo->args [n].size = 2;
1460 add_general (&gr, &stack_size, ainfo, TRUE);
1464 cinfo->args [n].size = 4;
1465 add_general (&gr, &stack_size, ainfo, TRUE);
1470 case MONO_TYPE_FNPTR:
1471 case MONO_TYPE_CLASS:
1472 case MONO_TYPE_OBJECT:
1473 case MONO_TYPE_STRING:
1474 case MONO_TYPE_SZARRAY:
1475 case MONO_TYPE_ARRAY:
1476 cinfo->args [n].size = sizeof (gpointer);
1477 add_general (&gr, &stack_size, ainfo, TRUE);
1479 case MONO_TYPE_GENERICINST:
1480 if (!mono_type_generic_inst_is_valuetype (t)) {
1481 cinfo->args [n].size = sizeof (gpointer);
1482 add_general (&gr, &stack_size, ainfo, TRUE);
1485 if (mini_is_gsharedvt_variable_type (t)) {
1486 /* gsharedvt arguments are passed by ref */
1487 g_assert (mini_is_gsharedvt_type (t));
1488 add_general (&gr, &stack_size, ainfo, TRUE);
1489 switch (ainfo->storage) {
1490 case RegTypeGeneral:
1491 ainfo->storage = RegTypeGSharedVtInReg;
1494 ainfo->storage = RegTypeGSharedVtOnStack;
1497 g_assert_not_reached ();
1502 case MONO_TYPE_TYPEDBYREF:
1503 case MONO_TYPE_VALUETYPE: {
1506 int nwords, nfields, esize;
1509 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1510 if (fpr + nfields < ARM_VFP_F16) {
1511 ainfo->storage = RegTypeHFA;
1513 ainfo->nregs = nfields;
1514 ainfo->esize = esize;
1525 if (t->type == MONO_TYPE_TYPEDBYREF) {
1526 size = sizeof (MonoTypedRef);
1527 align = sizeof (gpointer);
1529 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1531 size = mono_class_native_size (klass, &align);
1533 size = mini_type_stack_size_full (t, &align, FALSE);
1535 DEBUG(g_print ("load %d bytes struct\n", size));
1537 #ifdef TARGET_WATCHOS
1538 /* Watchos pass large structures by ref */
1539 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1540 if (sig->pinvoke && size > 16) {
1541 add_general (&gr, &stack_size, ainfo, TRUE);
1542 switch (ainfo->storage) {
1543 case RegTypeGeneral:
1544 ainfo->storage = RegTypeStructByAddr;
1547 ainfo->storage = RegTypeStructByAddrOnStack;
1550 g_assert_not_reached ();
1559 align_size += (sizeof (gpointer) - 1);
1560 align_size &= ~(sizeof (gpointer) - 1);
1561 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1562 ainfo->storage = RegTypeStructByVal;
1563 ainfo->struct_size = size;
1564 /* FIXME: align stack_size if needed */
1565 if (eabi_supported) {
1566 if (align >= 8 && (gr & 1))
1569 if (gr > ARMREG_R3) {
1571 ainfo->vtsize = nwords;
1573 int rest = ARMREG_R3 - gr + 1;
1574 int n_in_regs = rest >= nwords? nwords: rest;
1576 ainfo->size = n_in_regs;
1577 ainfo->vtsize = nwords - n_in_regs;
1580 nwords -= n_in_regs;
1582 if (sig->call_convention == MONO_CALL_VARARG)
1583 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1584 stack_size = ALIGN_TO (stack_size, align);
1585 ainfo->offset = stack_size;
1586 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1587 stack_size += nwords * sizeof (gpointer);
1593 add_general (&gr, &stack_size, ainfo, FALSE);
1599 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1601 add_general (&gr, &stack_size, ainfo, TRUE);
1607 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1609 add_general (&gr, &stack_size, ainfo, FALSE);
1612 case MONO_TYPE_MVAR:
1613 /* gsharedvt arguments are passed by ref */
1614 g_assert (mini_is_gsharedvt_type (t));
1615 add_general (&gr, &stack_size, ainfo, TRUE);
1616 switch (ainfo->storage) {
1617 case RegTypeGeneral:
1618 ainfo->storage = RegTypeGSharedVtInReg;
1621 ainfo->storage = RegTypeGSharedVtOnStack;
1624 g_assert_not_reached ();
1628 g_error ("Can't handle 0x%x", sig->params [i]->type);
1633 /* Handle the case where there are no implicit arguments */
1634 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1635 /* Prevent implicit arguments and sig_cookie from
1636 being passed in registers */
1639 /* Emit the signature cookie just before the implicit arguments */
1640 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1643 /* align stack size to 8 */
1644 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1645 stack_size = (stack_size + 7) & ~7;
1647 cinfo->stack_usage = stack_size;
1653 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1655 MonoType *callee_ret;
1659 c1 = get_call_info (NULL, caller_sig);
1660 c2 = get_call_info (NULL, callee_sig);
1663 * Tail calls with more callee stack usage than the caller cannot be supported, since
1664 * the extra stack space would be left on the stack after the tail call.
1666 res = c1->stack_usage >= c2->stack_usage;
1667 callee_ret = mini_get_underlying_type (callee_sig->ret);
1668 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1669 /* An address on the callee's stack is passed as the first argument */
1672 if (c2->stack_usage > 16 * 4)
1684 debug_omit_fp (void)
1687 return mono_debug_count ();
1694 * mono_arch_compute_omit_fp:
1696 * Determine whenever the frame pointer can be eliminated.
1699 mono_arch_compute_omit_fp (MonoCompile *cfg)
1701 MonoMethodSignature *sig;
1702 MonoMethodHeader *header;
1706 if (cfg->arch.omit_fp_computed)
1709 header = cfg->header;
1711 sig = mono_method_signature (cfg->method);
1713 if (!cfg->arch.cinfo)
1714 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1715 cinfo = cfg->arch.cinfo;
1718 * FIXME: Remove some of the restrictions.
1720 cfg->arch.omit_fp = TRUE;
1721 cfg->arch.omit_fp_computed = TRUE;
1723 if (cfg->disable_omit_fp)
1724 cfg->arch.omit_fp = FALSE;
1725 if (!debug_omit_fp ())
1726 cfg->arch.omit_fp = FALSE;
1728 if (cfg->method->save_lmf)
1729 cfg->arch.omit_fp = FALSE;
1731 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1732 cfg->arch.omit_fp = FALSE;
1733 if (header->num_clauses)
1734 cfg->arch.omit_fp = FALSE;
1735 if (cfg->param_area)
1736 cfg->arch.omit_fp = FALSE;
1737 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1738 cfg->arch.omit_fp = FALSE;
1739 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1740 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1741 cfg->arch.omit_fp = FALSE;
1742 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1743 ArgInfo *ainfo = &cinfo->args [i];
1745 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1747 * The stack offset can only be determined when the frame
1750 cfg->arch.omit_fp = FALSE;
1755 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1756 MonoInst *ins = cfg->varinfo [i];
1759 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1764 * Set var information according to the calling convention. arm version.
1765 * The locals var stuff should most likely be split in another method.
1768 mono_arch_allocate_vars (MonoCompile *cfg)
1770 MonoMethodSignature *sig;
1771 MonoMethodHeader *header;
1774 int i, offset, size, align, curinst;
1779 sig = mono_method_signature (cfg->method);
1781 if (!cfg->arch.cinfo)
1782 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1783 cinfo = cfg->arch.cinfo;
1784 sig_ret = mini_get_underlying_type (sig->ret);
1786 mono_arch_compute_omit_fp (cfg);
1788 if (cfg->arch.omit_fp)
1789 cfg->frame_reg = ARMREG_SP;
1791 cfg->frame_reg = ARMREG_FP;
1793 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1795 /* allow room for the vararg method args: void* and long/double */
1796 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1797 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1799 header = cfg->header;
1801 /* See mono_arch_get_global_int_regs () */
1802 if (cfg->flags & MONO_CFG_HAS_CALLS)
1803 cfg->uses_rgctx_reg = TRUE;
1805 if (cfg->frame_reg != ARMREG_SP)
1806 cfg->used_int_regs |= 1 << cfg->frame_reg;
1808 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1809 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1810 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1814 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1815 if (sig_ret->type != MONO_TYPE_VOID) {
1816 cfg->ret->opcode = OP_REGVAR;
1817 cfg->ret->inst_c0 = ARMREG_R0;
1820 /* local vars are at a positive offset from the stack pointer */
1822 * also note that if the function uses alloca, we use FP
1823 * to point at the local variables.
1825 offset = 0; /* linkage area */
1826 /* align the offset to 16 bytes: not sure this is needed here */
1828 //offset &= ~(8 - 1);
1830 /* add parameter area size for called functions */
1831 offset += cfg->param_area;
1834 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1837 /* allow room to save the return value */
1838 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1841 switch (cinfo->ret.storage) {
1842 case RegTypeStructByVal:
1844 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1845 offset = ALIGN_TO (offset, 8);
1846 cfg->ret->opcode = OP_REGOFFSET;
1847 cfg->ret->inst_basereg = cfg->frame_reg;
1848 cfg->ret->inst_offset = offset;
1849 if (cinfo->ret.storage == RegTypeStructByVal)
1850 offset += cinfo->ret.nregs * sizeof (gpointer);
1854 case RegTypeStructByAddr:
1855 ins = cfg->vret_addr;
1856 offset += sizeof(gpointer) - 1;
1857 offset &= ~(sizeof(gpointer) - 1);
1858 ins->inst_offset = offset;
1859 ins->opcode = OP_REGOFFSET;
1860 ins->inst_basereg = cfg->frame_reg;
1861 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1862 g_print ("vret_addr =");
1863 mono_print_ins (cfg->vret_addr);
1865 offset += sizeof(gpointer);
1871 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1872 if (cfg->arch.seq_point_info_var) {
1875 ins = cfg->arch.seq_point_info_var;
1879 offset += align - 1;
1880 offset &= ~(align - 1);
1881 ins->opcode = OP_REGOFFSET;
1882 ins->inst_basereg = cfg->frame_reg;
1883 ins->inst_offset = offset;
1886 ins = cfg->arch.ss_trigger_page_var;
1889 offset += align - 1;
1890 offset &= ~(align - 1);
1891 ins->opcode = OP_REGOFFSET;
1892 ins->inst_basereg = cfg->frame_reg;
1893 ins->inst_offset = offset;
1897 if (cfg->arch.seq_point_ss_method_var) {
1900 ins = cfg->arch.seq_point_ss_method_var;
1903 offset += align - 1;
1904 offset &= ~(align - 1);
1905 ins->opcode = OP_REGOFFSET;
1906 ins->inst_basereg = cfg->frame_reg;
1907 ins->inst_offset = offset;
1910 ins = cfg->arch.seq_point_bp_method_var;
1913 offset += align - 1;
1914 offset &= ~(align - 1);
1915 ins->opcode = OP_REGOFFSET;
1916 ins->inst_basereg = cfg->frame_reg;
1917 ins->inst_offset = offset;
1921 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1922 /* Allocate a temporary used by the atomic ops */
1926 /* Allocate a local slot to hold the sig cookie address */
1927 offset += align - 1;
1928 offset &= ~(align - 1);
1929 cfg->arch.atomic_tmp_offset = offset;
1932 cfg->arch.atomic_tmp_offset = -1;
1935 cfg->locals_min_stack_offset = offset;
1937 curinst = cfg->locals_start;
1938 for (i = curinst; i < cfg->num_varinfo; ++i) {
1941 ins = cfg->varinfo [i];
1942 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1945 t = ins->inst_vtype;
1946 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1949 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1950 * pinvoke wrappers when they call functions returning structure */
1951 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1952 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1956 size = mono_type_size (t, &align);
1958 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1959 * since it loads/stores misaligned words, which don't do the right thing.
1961 if (align < 4 && size >= 4)
1963 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1964 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1965 offset += align - 1;
1966 offset &= ~(align - 1);
1967 ins->opcode = OP_REGOFFSET;
1968 ins->inst_offset = offset;
1969 ins->inst_basereg = cfg->frame_reg;
1971 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1974 cfg->locals_max_stack_offset = offset;
1978 ins = cfg->args [curinst];
1979 if (ins->opcode != OP_REGVAR) {
1980 ins->opcode = OP_REGOFFSET;
1981 ins->inst_basereg = cfg->frame_reg;
1982 offset += sizeof (gpointer) - 1;
1983 offset &= ~(sizeof (gpointer) - 1);
1984 ins->inst_offset = offset;
1985 offset += sizeof (gpointer);
1990 if (sig->call_convention == MONO_CALL_VARARG) {
1994 /* Allocate a local slot to hold the sig cookie address */
1995 offset += align - 1;
1996 offset &= ~(align - 1);
1997 cfg->sig_cookie = offset;
2001 for (i = 0; i < sig->param_count; ++i) {
2002 ainfo = cinfo->args + i;
2004 ins = cfg->args [curinst];
2006 switch (ainfo->storage) {
2008 offset = ALIGN_TO (offset, 8);
2009 ins->opcode = OP_REGOFFSET;
2010 ins->inst_basereg = cfg->frame_reg;
2011 /* These arguments are saved to the stack in the prolog */
2012 ins->inst_offset = offset;
2013 if (cfg->verbose_level >= 2)
2014 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2022 if (ins->opcode != OP_REGVAR) {
2023 ins->opcode = OP_REGOFFSET;
2024 ins->inst_basereg = cfg->frame_reg;
2025 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2027 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2028 * since it loads/stores misaligned words, which don't do the right thing.
2030 if (align < 4 && size >= 4)
2032 /* The code in the prolog () stores words when storing vtypes received in a register */
2033 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2035 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2036 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2037 offset += align - 1;
2038 offset &= ~(align - 1);
2039 ins->inst_offset = offset;
2045 /* align the offset to 8 bytes */
2046 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2047 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2052 cfg->stack_offset = offset;
2056 mono_arch_create_vars (MonoCompile *cfg)
2058 MonoMethodSignature *sig;
2062 sig = mono_method_signature (cfg->method);
2064 if (!cfg->arch.cinfo)
2065 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2066 cinfo = cfg->arch.cinfo;
2068 if (IS_HARD_FLOAT) {
2069 for (i = 0; i < 2; i++) {
2070 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2071 inst->flags |= MONO_INST_VOLATILE;
2073 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2077 if (cinfo->ret.storage == RegTypeStructByVal)
2078 cfg->ret_var_is_local = TRUE;
2080 if (cinfo->ret.storage == RegTypeStructByAddr) {
2081 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2082 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2083 g_print ("vret_addr = ");
2084 mono_print_ins (cfg->vret_addr);
2088 if (cfg->gen_sdb_seq_points) {
2089 if (cfg->soft_breakpoints) {
2092 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2093 ins->flags |= MONO_INST_VOLATILE;
2094 cfg->arch.seq_point_ss_method_var = ins;
2096 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2097 ins->flags |= MONO_INST_VOLATILE;
2098 cfg->arch.seq_point_bp_method_var = ins;
2100 g_assert (!cfg->compile_aot);
2101 } else if (cfg->compile_aot) {
2102 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2103 ins->flags |= MONO_INST_VOLATILE;
2104 cfg->arch.seq_point_info_var = ins;
2106 /* Allocate a separate variable for this to save 1 load per seq point */
2107 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2108 ins->flags |= MONO_INST_VOLATILE;
2109 cfg->arch.ss_trigger_page_var = ins;
2115 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2117 MonoMethodSignature *tmp_sig;
2120 if (call->tail_call)
2123 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2126 * mono_ArgIterator_Setup assumes the signature cookie is
2127 * passed first and all the arguments which were before it are
2128 * passed on the stack after the signature. So compensate by
2129 * passing a different signature.
2131 tmp_sig = mono_metadata_signature_dup (call->signature);
2132 tmp_sig->param_count -= call->signature->sentinelpos;
2133 tmp_sig->sentinelpos = 0;
2134 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2136 sig_reg = mono_alloc_ireg (cfg);
2137 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2139 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2144 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2149 LLVMCallInfo *linfo;
2151 n = sig->param_count + sig->hasthis;
2153 cinfo = get_call_info (cfg->mempool, sig);
2155 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2158 * LLVM always uses the native ABI while we use our own ABI, the
2159 * only difference is the handling of vtypes:
2160 * - we only pass/receive them in registers in some cases, and only
2161 * in 1 or 2 integer registers.
2163 switch (cinfo->ret.storage) {
2164 case RegTypeGeneral:
2167 case RegTypeIRegPair:
2169 case RegTypeStructByAddr:
2170 /* Vtype returned using a hidden argument */
2171 linfo->ret.storage = LLVMArgVtypeRetAddr;
2172 linfo->vret_arg_index = cinfo->vret_arg_index;
2175 case RegTypeStructByVal:
2176 /* LLVM models this by returning an int array */
2177 linfo->ret.storage = LLVMArgAsIArgs;
2178 linfo->ret.nslots = cinfo->ret.nregs;
2182 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2183 cfg->disable_llvm = TRUE;
2187 for (i = 0; i < n; ++i) {
2188 LLVMArgInfo *lainfo = &linfo->args [i];
2189 ainfo = cinfo->args + i;
2191 lainfo->storage = LLVMArgNone;
2193 switch (ainfo->storage) {
2194 case RegTypeGeneral:
2195 case RegTypeIRegPair:
2197 case RegTypeBaseGen:
2199 lainfo->storage = LLVMArgNormal;
2201 case RegTypeStructByVal:
2202 lainfo->storage = LLVMArgAsIArgs;
2203 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2205 case RegTypeStructByAddr:
2206 case RegTypeStructByAddrOnStack:
2207 lainfo->storage = LLVMArgVtypeByRef;
2210 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2211 cfg->disable_llvm = TRUE;
2221 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2224 MonoMethodSignature *sig;
2228 sig = call->signature;
2229 n = sig->param_count + sig->hasthis;
2231 cinfo = get_call_info (cfg->mempool, sig);
2233 switch (cinfo->ret.storage) {
2234 case RegTypeStructByVal:
2236 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2237 /* The JIT will transform this into a normal call */
2238 call->vret_in_reg = TRUE;
2241 if (call->inst.opcode == OP_TAILCALL)
2244 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2245 * the location pointed to by it after call in emit_move_return_value ().
2247 if (!cfg->arch.vret_addr_loc) {
2248 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2249 /* Prevent it from being register allocated or optimized away */
2250 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2253 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2255 case RegTypeStructByAddr: {
2257 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2258 vtarg->sreg1 = call->vret_var->dreg;
2259 vtarg->dreg = mono_alloc_preg (cfg);
2260 MONO_ADD_INS (cfg->cbb, vtarg);
2262 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2269 for (i = 0; i < n; ++i) {
2270 ArgInfo *ainfo = cinfo->args + i;
2273 if (i >= sig->hasthis)
2274 t = sig->params [i - sig->hasthis];
2276 t = &mono_defaults.int_class->byval_arg;
2277 t = mini_get_underlying_type (t);
2279 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2280 /* Emit the signature cookie just before the implicit arguments */
2281 emit_sig_cookie (cfg, call, cinfo);
2284 in = call->args [i];
2286 switch (ainfo->storage) {
2287 case RegTypeGeneral:
2288 case RegTypeIRegPair:
2289 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2290 MONO_INST_NEW (cfg, ins, OP_MOVE);
2291 ins->dreg = mono_alloc_ireg (cfg);
2292 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2293 MONO_ADD_INS (cfg->cbb, ins);
2294 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2296 MONO_INST_NEW (cfg, ins, OP_MOVE);
2297 ins->dreg = mono_alloc_ireg (cfg);
2298 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2299 MONO_ADD_INS (cfg->cbb, ins);
2300 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2301 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2302 if (ainfo->size == 4) {
2303 if (IS_SOFT_FLOAT) {
2304 /* mono_emit_call_args () have already done the r8->r4 conversion */
2305 /* The converted value is in an int vreg */
2306 MONO_INST_NEW (cfg, ins, OP_MOVE);
2307 ins->dreg = mono_alloc_ireg (cfg);
2308 ins->sreg1 = in->dreg;
2309 MONO_ADD_INS (cfg->cbb, ins);
2310 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2314 cfg->param_area = MAX (cfg->param_area, 8);
2315 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2316 creg = mono_alloc_ireg (cfg);
2317 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2318 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2321 if (IS_SOFT_FLOAT) {
2322 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2323 ins->dreg = mono_alloc_ireg (cfg);
2324 ins->sreg1 = in->dreg;
2325 MONO_ADD_INS (cfg->cbb, ins);
2326 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2328 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2329 ins->dreg = mono_alloc_ireg (cfg);
2330 ins->sreg1 = in->dreg;
2331 MONO_ADD_INS (cfg->cbb, ins);
2332 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2336 cfg->param_area = MAX (cfg->param_area, 8);
2337 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2338 creg = mono_alloc_ireg (cfg);
2339 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2340 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2341 creg = mono_alloc_ireg (cfg);
2342 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2343 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2346 cfg->flags |= MONO_CFG_HAS_FPOUT;
2348 MONO_INST_NEW (cfg, ins, OP_MOVE);
2349 ins->dreg = mono_alloc_ireg (cfg);
2350 ins->sreg1 = in->dreg;
2351 MONO_ADD_INS (cfg->cbb, ins);
2353 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2356 case RegTypeStructByVal:
2357 case RegTypeGSharedVtInReg:
2358 case RegTypeGSharedVtOnStack:
2360 case RegTypeStructByAddr:
2361 case RegTypeStructByAddrOnStack:
2362 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2363 ins->opcode = OP_OUTARG_VT;
2364 ins->sreg1 = in->dreg;
2365 ins->klass = in->klass;
2366 ins->inst_p0 = call;
2367 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2368 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2369 mono_call_inst_add_outarg_vt (cfg, call, ins);
2370 MONO_ADD_INS (cfg->cbb, ins);
2373 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2374 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2375 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2376 if (t->type == MONO_TYPE_R8) {
2377 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2380 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2382 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2385 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2388 case RegTypeBaseGen:
2389 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2390 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2391 MONO_INST_NEW (cfg, ins, OP_MOVE);
2392 ins->dreg = mono_alloc_ireg (cfg);
2393 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2394 MONO_ADD_INS (cfg->cbb, ins);
2395 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2396 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2399 /* This should work for soft-float as well */
2401 cfg->param_area = MAX (cfg->param_area, 8);
2402 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2403 creg = mono_alloc_ireg (cfg);
2404 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2405 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2406 creg = mono_alloc_ireg (cfg);
2407 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2408 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2409 cfg->flags |= MONO_CFG_HAS_FPOUT;
2411 g_assert_not_reached ();
2415 int fdreg = mono_alloc_freg (cfg);
2417 if (ainfo->size == 8) {
2418 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2419 ins->sreg1 = in->dreg;
2421 MONO_ADD_INS (cfg->cbb, ins);
2423 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2428 * Mono's register allocator doesn't speak single-precision registers that
2429 * overlap double-precision registers (i.e. armhf). So we have to work around
2430 * the register allocator and load the value from memory manually.
2432 * So we create a variable for the float argument and an instruction to store
2433 * the argument into the variable. We then store the list of these arguments
2434 * in call->float_args. This list is then used by emit_float_args later to
2435 * pass the arguments in the various call opcodes.
2437 * This is not very nice, and we should really try to fix the allocator.
2440 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2442 /* Make sure the instruction isn't seen as pointless and removed.
2444 float_arg->flags |= MONO_INST_VOLATILE;
2446 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2448 /* We use the dreg to look up the instruction later. The hreg is used to
2449 * emit the instruction that loads the value into the FP reg.
2451 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2452 fad->vreg = float_arg->dreg;
2453 fad->hreg = ainfo->reg;
2455 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2458 call->used_iregs |= 1 << ainfo->reg;
2459 cfg->flags |= MONO_CFG_HAS_FPOUT;
2463 g_assert_not_reached ();
2467 /* Handle the case where there are no implicit arguments */
2468 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2469 emit_sig_cookie (cfg, call, cinfo);
2471 call->call_info = cinfo;
2472 call->stack_usage = cinfo->stack_usage;
2476 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2482 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2483 ins->dreg = mono_alloc_freg (cfg);
2484 ins->sreg1 = arg->dreg;
2485 MONO_ADD_INS (cfg->cbb, ins);
2486 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2489 g_assert_not_reached ();
2495 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2497 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2499 ArgInfo *ainfo = ins->inst_p1;
2500 int ovf_size = ainfo->vtsize;
2501 int doffset = ainfo->offset;
2502 int struct_size = ainfo->struct_size;
2503 int i, soffset, dreg, tmpreg;
2505 switch (ainfo->storage) {
2506 case RegTypeGSharedVtInReg:
2507 case RegTypeStructByAddr:
2509 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2511 case RegTypeGSharedVtOnStack:
2512 case RegTypeStructByAddrOnStack:
2513 /* Pass by addr on stack */
2514 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2517 for (i = 0; i < ainfo->nregs; ++i) {
2518 if (ainfo->esize == 4)
2519 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2521 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2522 load->dreg = mono_alloc_freg (cfg);
2523 load->inst_basereg = src->dreg;
2524 load->inst_offset = i * ainfo->esize;
2525 MONO_ADD_INS (cfg->cbb, load);
2527 if (ainfo->esize == 4) {
2530 /* See RegTypeFP in mono_arch_emit_call () */
2531 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2532 float_arg->flags |= MONO_INST_VOLATILE;
2533 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2535 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2536 fad->vreg = float_arg->dreg;
2537 fad->hreg = ainfo->reg + i;
2539 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2541 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2547 for (i = 0; i < ainfo->size; ++i) {
2548 dreg = mono_alloc_ireg (cfg);
2549 switch (struct_size) {
2551 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2554 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2557 tmpreg = mono_alloc_ireg (cfg);
2558 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2559 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2560 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2561 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2562 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2563 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2564 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2567 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2570 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2571 soffset += sizeof (gpointer);
2572 struct_size -= sizeof (gpointer);
2574 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2576 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2582 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2584 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2587 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2590 if (COMPILE_LLVM (cfg)) {
2591 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2593 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2594 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2595 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2596 MONO_ADD_INS (cfg->cbb, ins);
2601 case MONO_ARM_FPU_NONE:
2602 if (ret->type == MONO_TYPE_R8) {
2605 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2606 ins->dreg = cfg->ret->dreg;
2607 ins->sreg1 = val->dreg;
2608 MONO_ADD_INS (cfg->cbb, ins);
2611 if (ret->type == MONO_TYPE_R4) {
2612 /* Already converted to an int in method_to_ir () */
2613 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2617 case MONO_ARM_FPU_VFP:
2618 case MONO_ARM_FPU_VFP_HARD:
2619 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2622 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2623 ins->dreg = cfg->ret->dreg;
2624 ins->sreg1 = val->dreg;
2625 MONO_ADD_INS (cfg->cbb, ins);
2630 g_assert_not_reached ();
2634 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2637 #endif /* #ifndef DISABLE_JIT */
2640 mono_arch_is_inst_imm (gint64 imm)
2646 MonoMethodSignature *sig;
2649 MonoType **param_types;
2653 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2657 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2660 switch (cinfo->ret.storage) {
2662 case RegTypeGeneral:
2663 case RegTypeIRegPair:
2664 case RegTypeStructByAddr:
2675 for (i = 0; i < cinfo->nargs; ++i) {
2676 ArgInfo *ainfo = &cinfo->args [i];
2679 switch (ainfo->storage) {
2680 case RegTypeGeneral:
2681 case RegTypeIRegPair:
2682 case RegTypeBaseGen:
2686 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2689 case RegTypeStructByVal:
2690 if (ainfo->size == 0)
2691 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2693 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2694 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2702 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2703 for (i = 0; i < sig->param_count; ++i) {
2704 MonoType *t = sig->params [i];
2709 t = mini_get_underlying_type (t);
2732 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2734 ArchDynCallInfo *info;
2738 cinfo = get_call_info (NULL, sig);
2740 if (!dyn_call_supported (cinfo, sig)) {
2745 info = g_new0 (ArchDynCallInfo, 1);
2746 // FIXME: Preprocess the info to speed up start_dyn_call ()
2748 info->cinfo = cinfo;
2749 info->rtype = mini_get_underlying_type (sig->ret);
2750 info->param_types = g_new0 (MonoType*, sig->param_count);
2751 for (i = 0; i < sig->param_count; ++i)
2752 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2754 return (MonoDynCallInfo*)info;
2758 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2760 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2762 g_free (ainfo->cinfo);
2767 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2769 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2770 DynCallArgs *p = (DynCallArgs*)buf;
2771 int arg_index, greg, i, j, pindex;
2772 MonoMethodSignature *sig = dinfo->sig;
2774 g_assert (buf_len >= sizeof (DynCallArgs));
2784 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2785 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2790 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2791 p->regs [greg ++] = (mgreg_t)ret;
2793 for (i = pindex; i < sig->param_count; i++) {
2794 MonoType *t = dinfo->param_types [i];
2795 gpointer *arg = args [arg_index ++];
2796 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2799 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2801 } else if (ainfo->storage == RegTypeFP) {
2802 } else if (ainfo->storage == RegTypeBase) {
2803 slot = PARAM_REGS + (ainfo->offset / 4);
2804 } else if (ainfo->storage == RegTypeBaseGen) {
2805 /* slot + 1 is the first stack slot, so the code below will work */
2808 g_assert_not_reached ();
2812 p->regs [slot] = (mgreg_t)*arg;
2817 case MONO_TYPE_STRING:
2818 case MONO_TYPE_CLASS:
2819 case MONO_TYPE_ARRAY:
2820 case MONO_TYPE_SZARRAY:
2821 case MONO_TYPE_OBJECT:
2825 p->regs [slot] = (mgreg_t)*arg;
2828 p->regs [slot] = *(guint8*)arg;
2831 p->regs [slot] = *(gint8*)arg;
2834 p->regs [slot] = *(gint16*)arg;
2837 p->regs [slot] = *(guint16*)arg;
2840 p->regs [slot] = *(gint32*)arg;
2843 p->regs [slot] = *(guint32*)arg;
2847 p->regs [slot ++] = (mgreg_t)arg [0];
2848 p->regs [slot] = (mgreg_t)arg [1];
2851 if (ainfo->storage == RegTypeFP) {
2852 float f = *(float*)arg;
2853 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2856 p->regs [slot] = *(mgreg_t*)arg;
2860 if (ainfo->storage == RegTypeFP) {
2861 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2864 p->regs [slot ++] = (mgreg_t)arg [0];
2865 p->regs [slot] = (mgreg_t)arg [1];
2868 case MONO_TYPE_GENERICINST:
2869 if (MONO_TYPE_IS_REFERENCE (t)) {
2870 p->regs [slot] = (mgreg_t)*arg;
2873 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2874 MonoClass *klass = mono_class_from_mono_type (t);
2875 guint8 *nullable_buf;
2878 size = mono_class_value_size (klass, NULL);
2879 nullable_buf = g_alloca (size);
2880 g_assert (nullable_buf);
2882 /* The argument pointed to by arg is either a boxed vtype or null */
2883 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2885 arg = (gpointer*)nullable_buf;
2891 case MONO_TYPE_VALUETYPE:
2892 g_assert (ainfo->storage == RegTypeStructByVal);
2894 if (ainfo->size == 0)
2895 slot = PARAM_REGS + (ainfo->offset / 4);
2899 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2900 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2903 g_assert_not_reached ();
2909 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2911 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2912 DynCallArgs *p = (DynCallArgs*)buf;
2913 MonoType *ptype = ainfo->rtype;
2914 guint8 *ret = p->ret;
2915 mgreg_t res = p->res;
2916 mgreg_t res2 = p->res2;
2918 switch (ptype->type) {
2919 case MONO_TYPE_VOID:
2920 *(gpointer*)ret = NULL;
2922 case MONO_TYPE_STRING:
2923 case MONO_TYPE_CLASS:
2924 case MONO_TYPE_ARRAY:
2925 case MONO_TYPE_SZARRAY:
2926 case MONO_TYPE_OBJECT:
2930 *(gpointer*)ret = (gpointer)res;
2936 *(guint8*)ret = res;
2939 *(gint16*)ret = res;
2942 *(guint16*)ret = res;
2945 *(gint32*)ret = res;
2948 *(guint32*)ret = res;
2952 /* This handles endianness as well */
2953 ((gint32*)ret) [0] = res;
2954 ((gint32*)ret) [1] = res2;
2956 case MONO_TYPE_GENERICINST:
2957 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2958 *(gpointer*)ret = (gpointer)res;
2963 case MONO_TYPE_VALUETYPE:
2964 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2970 *(float*)ret = *(float*)&p->fpregs [0];
2972 *(float*)ret = *(float*)&res;
2974 case MONO_TYPE_R8: {
2978 if (IS_HARD_FLOAT) {
2979 *(double*)ret = p->fpregs [0];
2984 *(double*)ret = *(double*)®s;
2989 g_assert_not_reached ();
2996 * Allow tracing to work with this interface (with an optional argument)
3000 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3004 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3005 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3006 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3007 code = emit_call_reg (code, ARMREG_R2);
3021 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3024 int save_mode = SAVE_NONE;
3026 MonoMethod *method = cfg->method;
3027 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3028 int rtype = ret_type->type;
3029 int save_offset = cfg->param_area;
3033 offset = code - cfg->native_code;
3034 /* we need about 16 instructions */
3035 if (offset > (cfg->code_size - 16 * 4)) {
3036 cfg->code_size *= 2;
3037 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3038 code = cfg->native_code + offset;
3041 case MONO_TYPE_VOID:
3042 /* special case string .ctor icall */
3043 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3044 save_mode = SAVE_ONE;
3046 save_mode = SAVE_NONE;
3050 save_mode = SAVE_TWO;
3054 save_mode = SAVE_ONE_FP;
3056 save_mode = SAVE_ONE;
3060 save_mode = SAVE_TWO_FP;
3062 save_mode = SAVE_TWO;
3064 case MONO_TYPE_GENERICINST:
3065 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3066 save_mode = SAVE_ONE;
3070 case MONO_TYPE_VALUETYPE:
3071 save_mode = SAVE_STRUCT;
3074 save_mode = SAVE_ONE;
3078 switch (save_mode) {
3080 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3081 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3082 if (enable_arguments) {
3083 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3084 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3088 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3089 if (enable_arguments) {
3090 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3094 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3095 if (enable_arguments) {
3096 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3100 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3101 if (enable_arguments) {
3102 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3106 if (enable_arguments) {
3107 /* FIXME: get the actual address */
3108 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3116 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3117 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3118 code = emit_call_reg (code, ARMREG_IP);
3120 switch (save_mode) {
3122 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3123 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3126 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3129 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3132 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3143 * The immediate field for cond branches is big enough for all reasonable methods
3145 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3146 if (0 && ins->inst_true_bb->native_offset) { \
3147 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3149 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3150 ARM_B_COND (code, (condcode), 0); \
3153 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3155 /* emit an exception if condition is fail
3157 * We assign the extra code used to throw the implicit exceptions
3158 * to cfg->bb_exit as far as the big branch handling is concerned
3160 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3162 mono_add_patch_info (cfg, code - cfg->native_code, \
3163 MONO_PATCH_INFO_EXC, exc_name); \
3164 ARM_BL_COND (code, (condcode), 0); \
3167 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3170 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3175 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3179 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3180 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3182 switch (ins->opcode) {
3185 /* Already done by an arch-independent pass */
3187 case OP_LOAD_MEMBASE:
3188 case OP_LOADI4_MEMBASE:
3190 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3191 * OP_LOAD_MEMBASE offset(basereg), reg
3193 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3194 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3195 ins->inst_basereg == last_ins->inst_destbasereg &&
3196 ins->inst_offset == last_ins->inst_offset) {
3197 if (ins->dreg == last_ins->sreg1) {
3198 MONO_DELETE_INS (bb, ins);
3201 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3202 ins->opcode = OP_MOVE;
3203 ins->sreg1 = last_ins->sreg1;
3207 * Note: reg1 must be different from the basereg in the second load
3208 * OP_LOAD_MEMBASE offset(basereg), reg1
3209 * OP_LOAD_MEMBASE offset(basereg), reg2
3211 * OP_LOAD_MEMBASE offset(basereg), reg1
3212 * OP_MOVE reg1, reg2
3214 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3215 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3216 ins->inst_basereg != last_ins->dreg &&
3217 ins->inst_basereg == last_ins->inst_basereg &&
3218 ins->inst_offset == last_ins->inst_offset) {
3220 if (ins->dreg == last_ins->dreg) {
3221 MONO_DELETE_INS (bb, ins);
3224 ins->opcode = OP_MOVE;
3225 ins->sreg1 = last_ins->dreg;
3228 //g_assert_not_reached ();
3232 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3233 * OP_LOAD_MEMBASE offset(basereg), reg
3235 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3236 * OP_ICONST reg, imm
3238 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3239 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3240 ins->inst_basereg == last_ins->inst_destbasereg &&
3241 ins->inst_offset == last_ins->inst_offset) {
3242 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3243 ins->opcode = OP_ICONST;
3244 ins->inst_c0 = last_ins->inst_imm;
3245 g_assert_not_reached (); // check this rule
3249 case OP_LOADU1_MEMBASE:
3250 case OP_LOADI1_MEMBASE:
3251 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3252 ins->inst_basereg == last_ins->inst_destbasereg &&
3253 ins->inst_offset == last_ins->inst_offset) {
3254 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3255 ins->sreg1 = last_ins->sreg1;
3258 case OP_LOADU2_MEMBASE:
3259 case OP_LOADI2_MEMBASE:
3260 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3261 ins->inst_basereg == last_ins->inst_destbasereg &&
3262 ins->inst_offset == last_ins->inst_offset) {
3263 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3264 ins->sreg1 = last_ins->sreg1;
3268 ins->opcode = OP_MOVE;
3272 if (ins->dreg == ins->sreg1) {
3273 MONO_DELETE_INS (bb, ins);
3277 * OP_MOVE sreg, dreg
3278 * OP_MOVE dreg, sreg
3280 if (last_ins && last_ins->opcode == OP_MOVE &&
3281 ins->sreg1 == last_ins->dreg &&
3282 ins->dreg == last_ins->sreg1) {
3283 MONO_DELETE_INS (bb, ins);
3292 * the branch_cc_table should maintain the order of these
3306 branch_cc_table [] = {
3320 #define ADD_NEW_INS(cfg,dest,op) do { \
3321 MONO_INST_NEW ((cfg), (dest), (op)); \
3322 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3326 map_to_reg_reg_op (int op)
3335 case OP_COMPARE_IMM:
3337 case OP_ICOMPARE_IMM:
3351 case OP_LOAD_MEMBASE:
3352 return OP_LOAD_MEMINDEX;
3353 case OP_LOADI4_MEMBASE:
3354 return OP_LOADI4_MEMINDEX;
3355 case OP_LOADU4_MEMBASE:
3356 return OP_LOADU4_MEMINDEX;
3357 case OP_LOADU1_MEMBASE:
3358 return OP_LOADU1_MEMINDEX;
3359 case OP_LOADI2_MEMBASE:
3360 return OP_LOADI2_MEMINDEX;
3361 case OP_LOADU2_MEMBASE:
3362 return OP_LOADU2_MEMINDEX;
3363 case OP_LOADI1_MEMBASE:
3364 return OP_LOADI1_MEMINDEX;
3365 case OP_STOREI1_MEMBASE_REG:
3366 return OP_STOREI1_MEMINDEX;
3367 case OP_STOREI2_MEMBASE_REG:
3368 return OP_STOREI2_MEMINDEX;
3369 case OP_STOREI4_MEMBASE_REG:
3370 return OP_STOREI4_MEMINDEX;
3371 case OP_STORE_MEMBASE_REG:
3372 return OP_STORE_MEMINDEX;
3373 case OP_STORER4_MEMBASE_REG:
3374 return OP_STORER4_MEMINDEX;
3375 case OP_STORER8_MEMBASE_REG:
3376 return OP_STORER8_MEMINDEX;
3377 case OP_STORE_MEMBASE_IMM:
3378 return OP_STORE_MEMBASE_REG;
3379 case OP_STOREI1_MEMBASE_IMM:
3380 return OP_STOREI1_MEMBASE_REG;
3381 case OP_STOREI2_MEMBASE_IMM:
3382 return OP_STOREI2_MEMBASE_REG;
3383 case OP_STOREI4_MEMBASE_IMM:
3384 return OP_STOREI4_MEMBASE_REG;
3386 g_assert_not_reached ();
3390 * Remove from the instruction list the instructions that can't be
3391 * represented with very simple instructions with no register
3395 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3397 MonoInst *ins, *temp, *last_ins = NULL;
3398 int rot_amount, imm8, low_imm;
3400 MONO_BB_FOR_EACH_INS (bb, ins) {
3402 switch (ins->opcode) {
3406 case OP_COMPARE_IMM:
3407 case OP_ICOMPARE_IMM:
3421 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3422 int opcode2 = mono_op_imm_to_op (ins->opcode);
3423 ADD_NEW_INS (cfg, temp, OP_ICONST);
3424 temp->inst_c0 = ins->inst_imm;
3425 temp->dreg = mono_alloc_ireg (cfg);
3426 ins->sreg2 = temp->dreg;
3428 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3429 ins->opcode = opcode2;
3431 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3437 if (ins->inst_imm == 1) {
3438 ins->opcode = OP_MOVE;
3441 if (ins->inst_imm == 0) {
3442 ins->opcode = OP_ICONST;
3446 imm8 = mono_is_power_of_two (ins->inst_imm);
3448 ins->opcode = OP_SHL_IMM;
3449 ins->inst_imm = imm8;
3452 ADD_NEW_INS (cfg, temp, OP_ICONST);
3453 temp->inst_c0 = ins->inst_imm;
3454 temp->dreg = mono_alloc_ireg (cfg);
3455 ins->sreg2 = temp->dreg;
3456 ins->opcode = OP_IMUL;
3462 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3463 /* ARM sets the C flag to 1 if there was _no_ overflow */
3464 ins->next->opcode = OP_COND_EXC_NC;
3467 case OP_IDIV_UN_IMM:
3469 case OP_IREM_UN_IMM: {
3470 int opcode2 = mono_op_imm_to_op (ins->opcode);
3471 ADD_NEW_INS (cfg, temp, OP_ICONST);
3472 temp->inst_c0 = ins->inst_imm;
3473 temp->dreg = mono_alloc_ireg (cfg);
3474 ins->sreg2 = temp->dreg;
3476 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3477 ins->opcode = opcode2;
3480 case OP_LOCALLOC_IMM:
3481 ADD_NEW_INS (cfg, temp, OP_ICONST);
3482 temp->inst_c0 = ins->inst_imm;
3483 temp->dreg = mono_alloc_ireg (cfg);
3484 ins->sreg1 = temp->dreg;
3485 ins->opcode = OP_LOCALLOC;
3487 case OP_LOAD_MEMBASE:
3488 case OP_LOADI4_MEMBASE:
3489 case OP_LOADU4_MEMBASE:
3490 case OP_LOADU1_MEMBASE:
3491 /* we can do two things: load the immed in a register
3492 * and use an indexed load, or see if the immed can be
3493 * represented as an ad_imm + a load with a smaller offset
3494 * that fits. We just do the first for now, optimize later.
3496 if (arm_is_imm12 (ins->inst_offset))
3498 ADD_NEW_INS (cfg, temp, OP_ICONST);
3499 temp->inst_c0 = ins->inst_offset;
3500 temp->dreg = mono_alloc_ireg (cfg);
3501 ins->sreg2 = temp->dreg;
3502 ins->opcode = map_to_reg_reg_op (ins->opcode);
3504 case OP_LOADI2_MEMBASE:
3505 case OP_LOADU2_MEMBASE:
3506 case OP_LOADI1_MEMBASE:
3507 if (arm_is_imm8 (ins->inst_offset))
3509 ADD_NEW_INS (cfg, temp, OP_ICONST);
3510 temp->inst_c0 = ins->inst_offset;
3511 temp->dreg = mono_alloc_ireg (cfg);
3512 ins->sreg2 = temp->dreg;
3513 ins->opcode = map_to_reg_reg_op (ins->opcode);
3515 case OP_LOADR4_MEMBASE:
3516 case OP_LOADR8_MEMBASE:
3517 if (arm_is_fpimm8 (ins->inst_offset))
3519 low_imm = ins->inst_offset & 0x1ff;
3520 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3521 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3522 temp->inst_imm = ins->inst_offset & ~0x1ff;
3523 temp->sreg1 = ins->inst_basereg;
3524 temp->dreg = mono_alloc_ireg (cfg);
3525 ins->inst_basereg = temp->dreg;
3526 ins->inst_offset = low_imm;
3530 ADD_NEW_INS (cfg, temp, OP_ICONST);
3531 temp->inst_c0 = ins->inst_offset;
3532 temp->dreg = mono_alloc_ireg (cfg);
3534 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3535 add_ins->sreg1 = ins->inst_basereg;
3536 add_ins->sreg2 = temp->dreg;
3537 add_ins->dreg = mono_alloc_ireg (cfg);
3539 ins->inst_basereg = add_ins->dreg;
3540 ins->inst_offset = 0;
3543 case OP_STORE_MEMBASE_REG:
3544 case OP_STOREI4_MEMBASE_REG:
3545 case OP_STOREI1_MEMBASE_REG:
3546 if (arm_is_imm12 (ins->inst_offset))
3548 ADD_NEW_INS (cfg, temp, OP_ICONST);
3549 temp->inst_c0 = ins->inst_offset;
3550 temp->dreg = mono_alloc_ireg (cfg);
3551 ins->sreg2 = temp->dreg;
3552 ins->opcode = map_to_reg_reg_op (ins->opcode);
3554 case OP_STOREI2_MEMBASE_REG:
3555 if (arm_is_imm8 (ins->inst_offset))
3557 ADD_NEW_INS (cfg, temp, OP_ICONST);
3558 temp->inst_c0 = ins->inst_offset;
3559 temp->dreg = mono_alloc_ireg (cfg);
3560 ins->sreg2 = temp->dreg;
3561 ins->opcode = map_to_reg_reg_op (ins->opcode);
3563 case OP_STORER4_MEMBASE_REG:
3564 case OP_STORER8_MEMBASE_REG:
3565 if (arm_is_fpimm8 (ins->inst_offset))
3567 low_imm = ins->inst_offset & 0x1ff;
3568 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3569 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3570 temp->inst_imm = ins->inst_offset & ~0x1ff;
3571 temp->sreg1 = ins->inst_destbasereg;
3572 temp->dreg = mono_alloc_ireg (cfg);
3573 ins->inst_destbasereg = temp->dreg;
3574 ins->inst_offset = low_imm;
3578 ADD_NEW_INS (cfg, temp, OP_ICONST);
3579 temp->inst_c0 = ins->inst_offset;
3580 temp->dreg = mono_alloc_ireg (cfg);
3582 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3583 add_ins->sreg1 = ins->inst_destbasereg;
3584 add_ins->sreg2 = temp->dreg;
3585 add_ins->dreg = mono_alloc_ireg (cfg);
3587 ins->inst_destbasereg = add_ins->dreg;
3588 ins->inst_offset = 0;
3591 case OP_STORE_MEMBASE_IMM:
3592 case OP_STOREI1_MEMBASE_IMM:
3593 case OP_STOREI2_MEMBASE_IMM:
3594 case OP_STOREI4_MEMBASE_IMM:
3595 ADD_NEW_INS (cfg, temp, OP_ICONST);
3596 temp->inst_c0 = ins->inst_imm;
3597 temp->dreg = mono_alloc_ireg (cfg);
3598 ins->sreg1 = temp->dreg;
3599 ins->opcode = map_to_reg_reg_op (ins->opcode);
3601 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3604 gboolean swap = FALSE;
3608 /* Optimized away */
3613 /* Some fp compares require swapped operands */
3614 switch (ins->next->opcode) {
3616 ins->next->opcode = OP_FBLT;
3620 ins->next->opcode = OP_FBLT_UN;
3624 ins->next->opcode = OP_FBGE;
3628 ins->next->opcode = OP_FBGE_UN;
3636 ins->sreg1 = ins->sreg2;
3645 bb->last_ins = last_ins;
3646 bb->max_vreg = cfg->next_vreg;
3650 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3654 if (long_ins->opcode == OP_LNEG) {
3656 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3657 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3663 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3665 /* sreg is a float, dreg is an integer reg */
3667 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3669 ARM_TOSIZD (code, vfp_scratch1, sreg);
3671 ARM_TOUIZD (code, vfp_scratch1, sreg);
3672 ARM_FMRS (code, dreg, vfp_scratch1);
3673 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3677 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3678 else if (size == 2) {
3679 ARM_SHL_IMM (code, dreg, dreg, 16);
3680 ARM_SHR_IMM (code, dreg, dreg, 16);
3684 ARM_SHL_IMM (code, dreg, dreg, 24);
3685 ARM_SAR_IMM (code, dreg, dreg, 24);
3686 } else if (size == 2) {
3687 ARM_SHL_IMM (code, dreg, dreg, 16);
3688 ARM_SAR_IMM (code, dreg, dreg, 16);
3695 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3697 /* sreg is a float, dreg is an integer reg */
3699 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3701 ARM_TOSIZS (code, vfp_scratch1, sreg);
3703 ARM_TOUIZS (code, vfp_scratch1, sreg);
3704 ARM_FMRS (code, dreg, vfp_scratch1);
3705 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3709 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3710 else if (size == 2) {
3711 ARM_SHL_IMM (code, dreg, dreg, 16);
3712 ARM_SHR_IMM (code, dreg, dreg, 16);
3716 ARM_SHL_IMM (code, dreg, dreg, 24);
3717 ARM_SAR_IMM (code, dreg, dreg, 24);
3718 } else if (size == 2) {
3719 ARM_SHL_IMM (code, dreg, dreg, 16);
3720 ARM_SAR_IMM (code, dreg, dreg, 16);
3726 #endif /* #ifndef DISABLE_JIT */
3728 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3731 emit_thunk (guint8 *code, gconstpointer target)
3735 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3736 if (thumb_supported)
3737 ARM_BX (code, ARMREG_IP);
3739 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3740 *(guint32*)code = (guint32)target;
3742 mono_arch_flush_icache (p, code - p);
3746 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3748 MonoJitInfo *ji = NULL;
3749 MonoThunkJitInfo *info;
3752 guint8 *orig_target;
3753 guint8 *target_thunk;
3756 domain = mono_domain_get ();
3760 * This can be called multiple times during JITting,
3761 * save the current position in cfg->arch to avoid
3762 * doing a O(n^2) search.
3764 if (!cfg->arch.thunks) {
3765 cfg->arch.thunks = cfg->thunks;
3766 cfg->arch.thunks_size = cfg->thunk_area;
3768 thunks = cfg->arch.thunks;
3769 thunks_size = cfg->arch.thunks_size;
3771 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3772 g_assert_not_reached ();
3775 g_assert (*(guint32*)thunks == 0);
3776 emit_thunk (thunks, target);
3777 arm_patch (code, thunks);
3779 cfg->arch.thunks += THUNK_SIZE;
3780 cfg->arch.thunks_size -= THUNK_SIZE;
3782 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3784 info = mono_jit_info_get_thunk_info (ji);
3787 thunks = (guint8*)ji->code_start + info->thunks_offset;
3788 thunks_size = info->thunks_size;
3790 orig_target = mono_arch_get_call_target (code + 4);
3792 mono_mini_arch_lock ();
3794 target_thunk = NULL;
3795 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3796 /* The call already points to a thunk, because of trampolines etc. */
3797 target_thunk = orig_target;
3799 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3800 if (((guint32*)p) [0] == 0) {
3804 } else if (((guint32*)p) [2] == (guint32)target) {
3805 /* Thunk already points to target */
3812 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3814 if (!target_thunk) {
3815 mono_mini_arch_unlock ();
3816 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3817 g_assert_not_reached ();
3820 emit_thunk (target_thunk, target);
3821 arm_patch (code, target_thunk);
3822 mono_arch_flush_icache (code, 4);
3824 mono_mini_arch_unlock ();
3829 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3831 guint32 *code32 = (void*)code;
3832 guint32 ins = *code32;
3833 guint32 prim = (ins >> 25) & 7;
3834 guint32 tval = GPOINTER_TO_UINT (target);
3836 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3837 if (prim == 5) { /* 101b */
3838 /* the diff starts 8 bytes from the branch opcode */
3839 gint diff = target - code - 8;
3841 gint tmask = 0xffffffff;
3842 if (tval & 1) { /* entering thumb mode */
3843 diff = target - 1 - code - 8;
3844 g_assert (thumb_supported);
3845 tbits = 0xf << 28; /* bl->blx bit pattern */
3846 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3847 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3851 tmask = ~(1 << 24); /* clear the link bit */
3852 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3857 if (diff <= 33554431) {
3859 ins = (ins & 0xff000000) | diff;
3861 *code32 = ins | tbits;
3865 /* diff between 0 and -33554432 */
3866 if (diff >= -33554432) {
3868 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3870 *code32 = ins | tbits;
3875 handle_thunk (cfg, domain, code, target);
3880 * The alternative call sequences looks like this:
3882 * ldr ip, [pc] // loads the address constant
3883 * b 1f // jumps around the constant
3884 * address constant embedded in the code
3889 * There are two cases for patching:
3890 * a) at the end of method emission: in this case code points to the start
3891 * of the call sequence
3892 * b) during runtime patching of the call site: in this case code points
3893 * to the mov pc, ip instruction
3895 * We have to handle also the thunk jump code sequence:
3899 * address constant // execution never reaches here
3901 if ((ins & 0x0ffffff0) == 0x12fff10) {
3902 /* Branch and exchange: the address is constructed in a reg
3903 * We can patch BX when the code sequence is the following:
3904 * ldr ip, [pc, #0] ; 0x8
3911 guint8 *emit = (guint8*)ccode;
3912 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3914 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3915 ARM_BX (emit, ARMREG_IP);
3917 /*patching from magic trampoline*/
3918 if (ins == ccode [3]) {
3919 g_assert (code32 [-4] == ccode [0]);
3920 g_assert (code32 [-3] == ccode [1]);
3921 g_assert (code32 [-1] == ccode [2]);
3922 code32 [-2] = (guint32)target;
3925 /*patching from JIT*/
3926 if (ins == ccode [0]) {
3927 g_assert (code32 [1] == ccode [1]);
3928 g_assert (code32 [3] == ccode [2]);
3929 g_assert (code32 [4] == ccode [3]);
3930 code32 [2] = (guint32)target;
3933 g_assert_not_reached ();
3934 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3942 guint8 *emit = (guint8*)ccode;
3943 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3945 ARM_BLX_REG (emit, ARMREG_IP);
3947 g_assert (code32 [-3] == ccode [0]);
3948 g_assert (code32 [-2] == ccode [1]);
3949 g_assert (code32 [0] == ccode [2]);
3951 code32 [-1] = (guint32)target;
3954 guint32 *tmp = ccode;
3955 guint8 *emit = (guint8*)tmp;
3956 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3957 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3958 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3959 ARM_BX (emit, ARMREG_IP);
3960 if (ins == ccode [2]) {
3961 g_assert_not_reached (); // should be -2 ...
3962 code32 [-1] = (guint32)target;
3965 if (ins == ccode [0]) {
3966 /* handles both thunk jump code and the far call sequence */
3967 code32 [2] = (guint32)target;
3970 g_assert_not_reached ();
3972 // g_print ("patched with 0x%08x\n", ins);
3976 arm_patch (guchar *code, const guchar *target)
3978 arm_patch_general (NULL, NULL, code, target);
3982 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3983 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3984 * to be used with the emit macros.
3985 * Return -1 otherwise.
3988 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3991 for (i = 0; i < 31; i+= 2) {
3992 res = (val << (32 - i)) | (val >> i);
3995 *rot_amount = i? 32 - i: 0;
4002 * Emits in code a sequence of instructions that load the value 'val'
4003 * into the dreg register. Uses at most 4 instructions.
4006 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4008 int imm8, rot_amount;
4010 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4011 /* skip the constant pool */
4017 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4018 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4019 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4023 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4024 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4025 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4026 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4029 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4031 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4035 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4037 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4039 if (val & 0xFF0000) {
4040 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4042 if (val & 0xFF000000) {
4043 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4045 } else if (val & 0xFF00) {
4046 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4047 if (val & 0xFF0000) {
4048 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4050 if (val & 0xFF000000) {
4051 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4053 } else if (val & 0xFF0000) {
4054 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4055 if (val & 0xFF000000) {
4056 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4059 //g_assert_not_reached ();
4065 mono_arm_thumb_supported (void)
4067 return thumb_supported;
4073 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4078 call = (MonoCallInst*)ins;
4079 cinfo = call->call_info;
4081 switch (cinfo->ret.storage) {
4082 case RegTypeStructByVal:
4084 MonoInst *loc = cfg->arch.vret_addr_loc;
4087 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4088 /* The JIT treats this as a normal call */
4092 /* Load the destination address */
4093 g_assert (loc && loc->opcode == OP_REGOFFSET);
4095 if (arm_is_imm12 (loc->inst_offset)) {
4096 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4098 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4099 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4102 if (cinfo->ret.storage == RegTypeStructByVal) {
4103 int rsize = cinfo->ret.struct_size;
4105 for (i = 0; i < cinfo->ret.nregs; ++i) {
4106 g_assert (rsize >= 0);
4111 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4114 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4117 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4123 for (i = 0; i < cinfo->ret.nregs; ++i) {
4124 if (cinfo->ret.esize == 4)
4125 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4127 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4136 switch (ins->opcode) {
4139 case OP_FCALL_MEMBASE:
4141 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4142 if (sig_ret->type == MONO_TYPE_R4) {
4143 if (IS_HARD_FLOAT) {
4144 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4146 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4147 ARM_CVTS (code, ins->dreg, ins->dreg);
4150 if (IS_HARD_FLOAT) {
4151 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4153 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4160 case OP_RCALL_MEMBASE: {
4165 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4166 g_assert (sig_ret->type == MONO_TYPE_R4);
4167 if (IS_HARD_FLOAT) {
4168 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4170 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4171 ARM_CPYS (code, ins->dreg, ins->dreg);
4183 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4188 guint8 *code = cfg->native_code + cfg->code_len;
4189 MonoInst *last_ins = NULL;
4190 guint last_offset = 0;
4192 int imm8, rot_amount;
4194 /* we don't align basic blocks of loops on arm */
4196 if (cfg->verbose_level > 2)
4197 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4199 cpos = bb->max_offset;
4201 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4202 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4203 //g_assert (!mono_compile_aot);
4206 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4207 /* this is not thread save, but good enough */
4208 /* fixme: howto handle overflows? */
4209 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4212 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4213 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4214 (gpointer)"mono_break");
4215 code = emit_call_seq (cfg, code);
4218 MONO_BB_FOR_EACH_INS (bb, ins) {
4219 offset = code - cfg->native_code;
4221 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4223 if (offset > (cfg->code_size - max_len - 16)) {
4224 cfg->code_size *= 2;
4225 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4226 code = cfg->native_code + offset;
4228 // if (ins->cil_code)
4229 // g_print ("cil code\n");
4230 mono_debug_record_line_number (cfg, ins, offset);
4232 switch (ins->opcode) {
4233 case OP_MEMORY_BARRIER:
4235 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4236 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4240 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4242 case OP_TLS_GET_REG:
4243 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4246 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4248 case OP_TLS_SET_REG:
4249 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4251 case OP_ATOMIC_EXCHANGE_I4:
4252 case OP_ATOMIC_CAS_I4:
4253 case OP_ATOMIC_ADD_I4: {
4257 g_assert (v7_supported);
4260 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4262 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4264 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4268 g_assert (cfg->arch.atomic_tmp_offset != -1);
4269 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4271 switch (ins->opcode) {
4272 case OP_ATOMIC_EXCHANGE_I4:
4274 ARM_DMB (code, ARM_DMB_SY);
4275 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4276 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4277 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4279 ARM_B_COND (code, ARMCOND_NE, 0);
4280 arm_patch (buf [1], buf [0]);
4282 case OP_ATOMIC_CAS_I4:
4283 ARM_DMB (code, ARM_DMB_SY);
4285 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4286 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4288 ARM_B_COND (code, ARMCOND_NE, 0);
4289 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4290 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4292 ARM_B_COND (code, ARMCOND_NE, 0);
4293 arm_patch (buf [2], buf [0]);
4294 arm_patch (buf [1], code);
4296 case OP_ATOMIC_ADD_I4:
4298 ARM_DMB (code, ARM_DMB_SY);
4299 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4300 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4301 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4302 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4304 ARM_B_COND (code, ARMCOND_NE, 0);
4305 arm_patch (buf [1], buf [0]);
4308 g_assert_not_reached ();
4311 ARM_DMB (code, ARM_DMB_SY);
4312 if (tmpreg != ins->dreg)
4313 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4314 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4317 case OP_ATOMIC_LOAD_I1:
4318 case OP_ATOMIC_LOAD_U1:
4319 case OP_ATOMIC_LOAD_I2:
4320 case OP_ATOMIC_LOAD_U2:
4321 case OP_ATOMIC_LOAD_I4:
4322 case OP_ATOMIC_LOAD_U4:
4323 case OP_ATOMIC_LOAD_R4:
4324 case OP_ATOMIC_LOAD_R8: {
4325 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4326 ARM_DMB (code, ARM_DMB_SY);
4328 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4330 switch (ins->opcode) {
4331 case OP_ATOMIC_LOAD_I1:
4332 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4334 case OP_ATOMIC_LOAD_U1:
4335 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4337 case OP_ATOMIC_LOAD_I2:
4338 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4340 case OP_ATOMIC_LOAD_U2:
4341 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4343 case OP_ATOMIC_LOAD_I4:
4344 case OP_ATOMIC_LOAD_U4:
4345 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4347 case OP_ATOMIC_LOAD_R4:
4349 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4350 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4352 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4353 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4354 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4355 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4356 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4359 case OP_ATOMIC_LOAD_R8:
4360 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4361 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4365 ARM_DMB (code, ARM_DMB_SY);
4368 case OP_ATOMIC_STORE_I1:
4369 case OP_ATOMIC_STORE_U1:
4370 case OP_ATOMIC_STORE_I2:
4371 case OP_ATOMIC_STORE_U2:
4372 case OP_ATOMIC_STORE_I4:
4373 case OP_ATOMIC_STORE_U4:
4374 case OP_ATOMIC_STORE_R4:
4375 case OP_ATOMIC_STORE_R8: {
4376 ARM_DMB (code, ARM_DMB_SY);
4378 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4380 switch (ins->opcode) {
4381 case OP_ATOMIC_STORE_I1:
4382 case OP_ATOMIC_STORE_U1:
4383 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4385 case OP_ATOMIC_STORE_I2:
4386 case OP_ATOMIC_STORE_U2:
4387 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4389 case OP_ATOMIC_STORE_I4:
4390 case OP_ATOMIC_STORE_U4:
4391 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4393 case OP_ATOMIC_STORE_R4:
4395 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4396 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4398 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4399 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4400 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4401 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4402 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4405 case OP_ATOMIC_STORE_R8:
4406 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4407 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4411 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4412 ARM_DMB (code, ARM_DMB_SY);
4416 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4417 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4420 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4421 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4423 case OP_STOREI1_MEMBASE_IMM:
4424 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4425 g_assert (arm_is_imm12 (ins->inst_offset));
4426 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4428 case OP_STOREI2_MEMBASE_IMM:
4429 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4430 g_assert (arm_is_imm8 (ins->inst_offset));
4431 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4433 case OP_STORE_MEMBASE_IMM:
4434 case OP_STOREI4_MEMBASE_IMM:
4435 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4436 g_assert (arm_is_imm12 (ins->inst_offset));
4437 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4439 case OP_STOREI1_MEMBASE_REG:
4440 g_assert (arm_is_imm12 (ins->inst_offset));
4441 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4443 case OP_STOREI2_MEMBASE_REG:
4444 g_assert (arm_is_imm8 (ins->inst_offset));
4445 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4447 case OP_STORE_MEMBASE_REG:
4448 case OP_STOREI4_MEMBASE_REG:
4449 /* this case is special, since it happens for spill code after lowering has been called */
4450 if (arm_is_imm12 (ins->inst_offset)) {
4451 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4453 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4454 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4457 case OP_STOREI1_MEMINDEX:
4458 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4460 case OP_STOREI2_MEMINDEX:
4461 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4463 case OP_STORE_MEMINDEX:
4464 case OP_STOREI4_MEMINDEX:
4465 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4468 g_assert_not_reached ();
4470 case OP_LOAD_MEMINDEX:
4471 case OP_LOADI4_MEMINDEX:
4472 case OP_LOADU4_MEMINDEX:
4473 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4475 case OP_LOADI1_MEMINDEX:
4476 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4478 case OP_LOADU1_MEMINDEX:
4479 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4481 case OP_LOADI2_MEMINDEX:
4482 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4484 case OP_LOADU2_MEMINDEX:
4485 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4487 case OP_LOAD_MEMBASE:
4488 case OP_LOADI4_MEMBASE:
4489 case OP_LOADU4_MEMBASE:
4490 /* this case is special, since it happens for spill code after lowering has been called */
4491 if (arm_is_imm12 (ins->inst_offset)) {
4492 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4494 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4495 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4498 case OP_LOADI1_MEMBASE:
4499 g_assert (arm_is_imm8 (ins->inst_offset));
4500 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4502 case OP_LOADU1_MEMBASE:
4503 g_assert (arm_is_imm12 (ins->inst_offset));
4504 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4506 case OP_LOADU2_MEMBASE:
4507 g_assert (arm_is_imm8 (ins->inst_offset));
4508 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4510 case OP_LOADI2_MEMBASE:
4511 g_assert (arm_is_imm8 (ins->inst_offset));
4512 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4514 case OP_ICONV_TO_I1:
4515 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4516 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4518 case OP_ICONV_TO_I2:
4519 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4520 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4522 case OP_ICONV_TO_U1:
4523 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4525 case OP_ICONV_TO_U2:
4526 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4527 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4531 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4533 case OP_COMPARE_IMM:
4534 case OP_ICOMPARE_IMM:
4535 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4536 g_assert (imm8 >= 0);
4537 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4541 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4542 * So instead of emitting a trap, we emit a call a C function and place a
4545 //*(int*)code = 0xef9f0001;
4548 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4549 (gpointer)"mono_break");
4550 code = emit_call_seq (cfg, code);
4552 case OP_RELAXED_NOP:
4557 case OP_DUMMY_STORE:
4558 case OP_DUMMY_ICONST:
4559 case OP_DUMMY_R8CONST:
4560 case OP_NOT_REACHED:
4563 case OP_IL_SEQ_POINT:
4564 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4566 case OP_SEQ_POINT: {
4568 MonoInst *info_var = cfg->arch.seq_point_info_var;
4569 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4570 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4571 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4573 int dreg = ARMREG_LR;
4575 if (cfg->soft_breakpoints) {
4576 g_assert (!cfg->compile_aot);
4580 * For AOT, we use one got slot per method, which will point to a
4581 * SeqPointInfo structure, containing all the information required
4582 * by the code below.
4584 if (cfg->compile_aot) {
4585 g_assert (info_var);
4586 g_assert (info_var->opcode == OP_REGOFFSET);
4587 g_assert (arm_is_imm12 (info_var->inst_offset));
4590 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4592 * Read from the single stepping trigger page. This will cause a
4593 * SIGSEGV when single stepping is enabled.
4594 * We do this _before_ the breakpoint, so single stepping after
4595 * a breakpoint is hit will step to the next IL offset.
4597 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4600 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4601 if (cfg->soft_breakpoints) {
4602 /* Load the address of the sequence point method variable. */
4603 var = ss_method_var;
4605 g_assert (var->opcode == OP_REGOFFSET);
4606 g_assert (arm_is_imm12 (var->inst_offset));
4607 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4609 /* Read the value and check whether it is non-zero. */
4610 ARM_LDR_IMM (code, dreg, dreg, 0);
4611 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4612 /* Call it conditionally. */
4613 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4615 if (cfg->compile_aot) {
4616 /* Load the trigger page addr from the variable initialized in the prolog */
4617 var = ss_trigger_page_var;
4619 g_assert (var->opcode == OP_REGOFFSET);
4620 g_assert (arm_is_imm12 (var->inst_offset));
4621 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4623 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4625 *(int*)code = (int)ss_trigger_page;
4628 ARM_LDR_IMM (code, dreg, dreg, 0);
4632 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4634 if (cfg->soft_breakpoints) {
4635 /* Load the address of the breakpoint method into ip. */
4636 var = bp_method_var;
4638 g_assert (var->opcode == OP_REGOFFSET);
4639 g_assert (arm_is_imm12 (var->inst_offset));
4640 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4643 * A placeholder for a possible breakpoint inserted by
4644 * mono_arch_set_breakpoint ().
4647 } else if (cfg->compile_aot) {
4648 guint32 offset = code - cfg->native_code;
4651 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4652 /* Add the offset */
4653 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4654 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4655 if (arm_is_imm12 ((int)val)) {
4656 ARM_LDR_IMM (code, dreg, dreg, val);
4658 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4660 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4662 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4663 g_assert (!(val & 0xFF000000));
4665 ARM_LDR_IMM (code, dreg, dreg, 0);
4667 /* What is faster, a branch or a load ? */
4668 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4669 /* The breakpoint instruction */
4670 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4673 * A placeholder for a possible breakpoint inserted by
4674 * mono_arch_set_breakpoint ().
4676 for (i = 0; i < 4; ++i)
4681 * Add an additional nop so skipping the bp doesn't cause the ip to point
4682 * to another IL offset.
4690 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4693 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4697 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4700 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4701 g_assert (imm8 >= 0);
4702 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4706 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4707 g_assert (imm8 >= 0);
4708 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4712 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4713 g_assert (imm8 >= 0);
4714 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4717 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4718 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4720 case OP_IADD_OVF_UN:
4721 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4722 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4725 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4726 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4728 case OP_ISUB_OVF_UN:
4729 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4730 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4732 case OP_ADD_OVF_CARRY:
4733 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4734 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4736 case OP_ADD_OVF_UN_CARRY:
4737 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4738 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4740 case OP_SUB_OVF_CARRY:
4741 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4742 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4744 case OP_SUB_OVF_UN_CARRY:
4745 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4746 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4750 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4753 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4754 g_assert (imm8 >= 0);
4755 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4758 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4762 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4766 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4767 g_assert (imm8 >= 0);
4768 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4772 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4773 g_assert (imm8 >= 0);
4774 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4776 case OP_ARM_RSBS_IMM:
4777 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4778 g_assert (imm8 >= 0);
4779 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4781 case OP_ARM_RSC_IMM:
4782 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4783 g_assert (imm8 >= 0);
4784 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4787 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4791 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4792 g_assert (imm8 >= 0);
4793 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4796 g_assert (v7s_supported || v7k_supported);
4797 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4800 g_assert (v7s_supported || v7k_supported);
4801 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4804 g_assert (v7s_supported || v7k_supported);
4805 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4806 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4809 g_assert (v7s_supported || v7k_supported);
4810 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4811 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4815 g_assert_not_reached ();
4817 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4821 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4822 g_assert (imm8 >= 0);
4823 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4826 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4830 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4831 g_assert (imm8 >= 0);
4832 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4835 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4840 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4841 else if (ins->dreg != ins->sreg1)
4842 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4845 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4850 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4851 else if (ins->dreg != ins->sreg1)
4852 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4855 case OP_ISHR_UN_IMM:
4857 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4858 else if (ins->dreg != ins->sreg1)
4859 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4862 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4865 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4868 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4871 if (ins->dreg == ins->sreg2)
4872 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4874 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4877 g_assert_not_reached ();
4880 /* FIXME: handle ovf/ sreg2 != dreg */
4881 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4882 /* FIXME: MUL doesn't set the C/O flags on ARM */
4884 case OP_IMUL_OVF_UN:
4885 /* FIXME: handle ovf/ sreg2 != dreg */
4886 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4887 /* FIXME: MUL doesn't set the C/O flags on ARM */
4890 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4893 /* Load the GOT offset */
4894 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4895 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4897 *(gpointer*)code = NULL;
4899 /* Load the value from the GOT */
4900 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4902 case OP_OBJC_GET_SELECTOR:
4903 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4904 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4906 *(gpointer*)code = NULL;
4908 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4910 case OP_ICONV_TO_I4:
4911 case OP_ICONV_TO_U4:
4913 if (ins->dreg != ins->sreg1)
4914 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4917 int saved = ins->sreg2;
4918 if (ins->sreg2 == ARM_LSW_REG) {
4919 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4922 if (ins->sreg1 != ARM_LSW_REG)
4923 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4924 if (saved != ARM_MSW_REG)
4925 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4929 if (IS_VFP && ins->dreg != ins->sreg1)
4930 ARM_CPYD (code, ins->dreg, ins->sreg1);
4933 if (IS_VFP && ins->dreg != ins->sreg1)
4934 ARM_CPYS (code, ins->dreg, ins->sreg1);
4936 case OP_MOVE_F_TO_I4:
4938 ARM_FMRS (code, ins->dreg, ins->sreg1);
4940 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4941 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4942 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4943 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4946 case OP_MOVE_I4_TO_F:
4948 ARM_FMSR (code, ins->dreg, ins->sreg1);
4950 ARM_FMSR (code, ins->dreg, ins->sreg1);
4951 ARM_CVTS (code, ins->dreg, ins->dreg);
4954 case OP_FCONV_TO_R4:
4957 ARM_CVTD (code, ins->dreg, ins->sreg1);
4959 ARM_CVTD (code, ins->dreg, ins->sreg1);
4960 ARM_CVTS (code, ins->dreg, ins->dreg);
4965 MonoCallInst *call = (MonoCallInst*)ins;
4968 * The stack looks like the following:
4969 * <caller argument area>
4972 * <callee argument area>
4973 * Need to copy the arguments from the callee argument area to
4974 * the caller argument area, and pop the frame.
4976 if (call->stack_usage) {
4977 int i, prev_sp_offset = 0;
4979 /* Compute size of saved registers restored below */
4981 prev_sp_offset = 2 * 4;
4983 prev_sp_offset = 1 * 4;
4984 for (i = 0; i < 16; ++i) {
4985 if (cfg->used_int_regs & (1 << i))
4986 prev_sp_offset += 4;
4989 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4991 /* Copy arguments on the stack to our argument area */
4992 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4993 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4994 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4999 * Keep in sync with mono_arch_emit_epilog
5001 g_assert (!cfg->method->save_lmf);
5003 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5005 if (cfg->used_int_regs)
5006 ARM_POP (code, cfg->used_int_regs);
5007 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5009 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5012 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5013 if (cfg->compile_aot) {
5014 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5016 *(gpointer*)code = NULL;
5018 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5020 code = mono_arm_patchable_b (code, ARMCOND_AL);
5021 cfg->thunk_area += THUNK_SIZE;
5026 /* ensure ins->sreg1 is not NULL */
5027 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5030 g_assert (cfg->sig_cookie < 128);
5031 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5032 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5042 call = (MonoCallInst*)ins;
5045 code = emit_float_args (cfg, call, code, &max_len, &offset);
5047 if (ins->flags & MONO_INST_HAS_METHOD)
5048 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5050 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5051 code = emit_call_seq (cfg, code);
5052 ins->flags |= MONO_INST_GC_CALLSITE;
5053 ins->backend.pc_offset = code - cfg->native_code;
5054 code = emit_move_return_value (cfg, ins, code);
5061 case OP_VOIDCALL_REG:
5064 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5066 code = emit_call_reg (code, ins->sreg1);
5067 ins->flags |= MONO_INST_GC_CALLSITE;
5068 ins->backend.pc_offset = code - cfg->native_code;
5069 code = emit_move_return_value (cfg, ins, code);
5071 case OP_FCALL_MEMBASE:
5072 case OP_RCALL_MEMBASE:
5073 case OP_LCALL_MEMBASE:
5074 case OP_VCALL_MEMBASE:
5075 case OP_VCALL2_MEMBASE:
5076 case OP_VOIDCALL_MEMBASE:
5077 case OP_CALL_MEMBASE: {
5078 g_assert (ins->sreg1 != ARMREG_LR);
5079 call = (MonoCallInst*)ins;
5082 code = emit_float_args (cfg, call, code, &max_len, &offset);
5083 if (!arm_is_imm12 (ins->inst_offset)) {
5084 /* sreg1 might be IP */
5085 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5086 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5087 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5088 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5089 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5091 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5092 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5094 ins->flags |= MONO_INST_GC_CALLSITE;
5095 ins->backend.pc_offset = code - cfg->native_code;
5096 code = emit_move_return_value (cfg, ins, code);
5099 case OP_GENERIC_CLASS_INIT: {
5100 static int byte_offset = -1;
5101 static guint8 bitmask;
5105 if (byte_offset < 0)
5106 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5108 g_assert (arm_is_imm8 (byte_offset));
5109 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5110 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5111 g_assert (imm8 >= 0);
5112 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5113 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5115 ARM_B_COND (code, ARMCOND_NE, 0);
5117 /* Uninitialized case */
5118 g_assert (ins->sreg1 == ARMREG_R0);
5120 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5121 (gpointer)"mono_generic_class_init");
5122 code = emit_call_seq (cfg, code);
5124 /* Initialized case */
5125 arm_patch (jump, code);
5129 /* round the size to 8 bytes */
5130 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5131 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5132 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5133 /* memzero the area: dreg holds the size, sp is the pointer */
5134 if (ins->flags & MONO_INST_INIT) {
5135 guint8 *start_loop, *branch_to_cond;
5136 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5137 branch_to_cond = code;
5140 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5141 arm_patch (branch_to_cond, code);
5142 /* decrement by 4 and set flags */
5143 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5144 ARM_B_COND (code, ARMCOND_GE, 0);
5145 arm_patch (code - 4, start_loop);
5147 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5148 if (cfg->param_area)
5149 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5154 MonoInst *var = cfg->dyn_call_var;
5157 g_assert (var->opcode == OP_REGOFFSET);
5158 g_assert (arm_is_imm12 (var->inst_offset));
5160 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5161 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5163 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5165 /* Save args buffer */
5166 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5168 /* Set stack slots using R0 as scratch reg */
5169 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5170 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5171 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5172 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5175 /* Set fp argument registers */
5176 if (IS_HARD_FLOAT) {
5177 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5178 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5180 ARM_B_COND (code, ARMCOND_EQ, 0);
5181 for (i = 0; i < FP_PARAM_REGS; ++i) {
5182 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5183 g_assert (arm_is_fpimm8 (offset));
5184 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5186 arm_patch (buf [0], code);
5189 /* Set argument registers */
5190 for (i = 0; i < PARAM_REGS; ++i)
5191 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5194 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5195 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5198 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5199 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5200 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5202 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5206 if (ins->sreg1 != ARMREG_R0)
5207 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5208 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5209 (gpointer)"mono_arch_throw_exception");
5210 code = emit_call_seq (cfg, code);
5214 if (ins->sreg1 != ARMREG_R0)
5215 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5216 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5217 (gpointer)"mono_arch_rethrow_exception");
5218 code = emit_call_seq (cfg, code);
5221 case OP_START_HANDLER: {
5222 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5223 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5226 /* Reserve a param area, see filter-stack.exe */
5228 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5229 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5231 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5232 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5236 if (arm_is_imm12 (spvar->inst_offset)) {
5237 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5239 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5240 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5244 case OP_ENDFILTER: {
5245 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5246 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5249 /* Free the param area */
5251 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5252 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5254 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5255 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5259 if (ins->sreg1 != ARMREG_R0)
5260 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5261 if (arm_is_imm12 (spvar->inst_offset)) {
5262 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5264 g_assert (ARMREG_IP != spvar->inst_basereg);
5265 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5266 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5268 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5271 case OP_ENDFINALLY: {
5272 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5273 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5276 /* Free the param area */
5278 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5279 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5281 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5282 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5286 if (arm_is_imm12 (spvar->inst_offset)) {
5287 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5289 g_assert (ARMREG_IP != spvar->inst_basereg);
5290 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5291 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5293 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5296 case OP_CALL_HANDLER:
5297 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5298 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5299 cfg->thunk_area += THUNK_SIZE;
5300 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5303 if (ins->dreg != ARMREG_R0)
5304 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5308 ins->inst_c0 = code - cfg->native_code;
5311 /*if (ins->inst_target_bb->native_offset) {
5313 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5315 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5316 code = mono_arm_patchable_b (code, ARMCOND_AL);
5320 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5324 * In the normal case we have:
5325 * ldr pc, [pc, ins->sreg1 << 2]
5328 * ldr lr, [pc, ins->sreg1 << 2]
5330 * After follows the data.
5331 * FIXME: add aot support.
5333 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5334 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5335 if (offset + max_len > (cfg->code_size - 16)) {
5336 cfg->code_size += max_len;
5337 cfg->code_size *= 2;
5338 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5339 code = cfg->native_code + offset;
5341 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5343 code += 4 * GPOINTER_TO_INT (ins->klass);
5347 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5348 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5352 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5353 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5357 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5358 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5362 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5363 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5367 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5368 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5371 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5372 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5375 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5376 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5379 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5380 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5383 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5384 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5387 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5388 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5390 case OP_COND_EXC_EQ:
5391 case OP_COND_EXC_NE_UN:
5392 case OP_COND_EXC_LT:
5393 case OP_COND_EXC_LT_UN:
5394 case OP_COND_EXC_GT:
5395 case OP_COND_EXC_GT_UN:
5396 case OP_COND_EXC_GE:
5397 case OP_COND_EXC_GE_UN:
5398 case OP_COND_EXC_LE:
5399 case OP_COND_EXC_LE_UN:
5400 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5402 case OP_COND_EXC_IEQ:
5403 case OP_COND_EXC_INE_UN:
5404 case OP_COND_EXC_ILT:
5405 case OP_COND_EXC_ILT_UN:
5406 case OP_COND_EXC_IGT:
5407 case OP_COND_EXC_IGT_UN:
5408 case OP_COND_EXC_IGE:
5409 case OP_COND_EXC_IGE_UN:
5410 case OP_COND_EXC_ILE:
5411 case OP_COND_EXC_ILE_UN:
5412 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5415 case OP_COND_EXC_IC:
5416 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5418 case OP_COND_EXC_OV:
5419 case OP_COND_EXC_IOV:
5420 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5422 case OP_COND_EXC_NC:
5423 case OP_COND_EXC_INC:
5424 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5426 case OP_COND_EXC_NO:
5427 case OP_COND_EXC_INO:
5428 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5440 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5443 /* floating point opcodes */
5445 if (cfg->compile_aot) {
5446 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5448 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5450 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5453 /* FIXME: we can optimize the imm load by dealing with part of
5454 * the displacement in LDFD (aligning to 512).
5456 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5457 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5461 if (cfg->compile_aot) {
5462 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5464 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5467 ARM_CVTS (code, ins->dreg, ins->dreg);
5469 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5470 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5472 ARM_CVTS (code, ins->dreg, ins->dreg);
5475 case OP_STORER8_MEMBASE_REG:
5476 /* This is generated by the local regalloc pass which runs after the lowering pass */
5477 if (!arm_is_fpimm8 (ins->inst_offset)) {
5478 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5479 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5480 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5482 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5485 case OP_LOADR8_MEMBASE:
5486 /* This is generated by the local regalloc pass which runs after the lowering pass */
5487 if (!arm_is_fpimm8 (ins->inst_offset)) {
5488 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5489 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5490 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5492 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5495 case OP_STORER4_MEMBASE_REG:
5496 g_assert (arm_is_fpimm8 (ins->inst_offset));
5498 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5500 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5501 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5502 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5503 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5506 case OP_LOADR4_MEMBASE:
5508 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5510 g_assert (arm_is_fpimm8 (ins->inst_offset));
5511 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5512 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5513 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5514 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5517 case OP_ICONV_TO_R_UN: {
5518 g_assert_not_reached ();
5521 case OP_ICONV_TO_R4:
5523 ARM_FMSR (code, ins->dreg, ins->sreg1);
5524 ARM_FSITOS (code, ins->dreg, ins->dreg);
5526 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5527 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5528 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5529 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5530 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5533 case OP_ICONV_TO_R8:
5534 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5535 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5536 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5537 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5541 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5542 if (sig_ret->type == MONO_TYPE_R4) {
5544 if (IS_HARD_FLOAT) {
5545 if (ins->sreg1 != ARM_VFP_D0)
5546 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5548 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5551 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5554 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5558 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5560 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5564 case OP_FCONV_TO_I1:
5565 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5567 case OP_FCONV_TO_U1:
5568 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5570 case OP_FCONV_TO_I2:
5571 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5573 case OP_FCONV_TO_U2:
5574 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5576 case OP_FCONV_TO_I4:
5578 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5580 case OP_FCONV_TO_U4:
5582 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5584 case OP_FCONV_TO_I8:
5585 case OP_FCONV_TO_U8:
5586 g_assert_not_reached ();
5587 /* Implemented as helper calls */
5589 case OP_LCONV_TO_R_UN:
5590 g_assert_not_reached ();
5591 /* Implemented as helper calls */
5593 case OP_LCONV_TO_OVF_I4_2: {
5594 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5596 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5599 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5600 high_bit_not_set = code;
5601 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5603 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5604 valid_negative = code;
5605 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5606 invalid_negative = code;
5607 ARM_B_COND (code, ARMCOND_AL, 0);
5609 arm_patch (high_bit_not_set, code);
5611 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5612 valid_positive = code;
5613 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5615 arm_patch (invalid_negative, code);
5616 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5618 arm_patch (valid_negative, code);
5619 arm_patch (valid_positive, code);
5621 if (ins->dreg != ins->sreg1)
5622 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5626 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5629 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5632 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5635 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5638 ARM_NEGD (code, ins->dreg, ins->sreg1);
5642 g_assert_not_reached ();
5646 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5652 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5657 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5660 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5661 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5665 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5668 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5669 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5673 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5676 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5677 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5678 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5682 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5685 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5686 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5690 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5693 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5694 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5695 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5699 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5702 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5703 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5707 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5710 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5711 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5715 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5718 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5719 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5722 /* ARM FPA flags table:
5723 * N Less than ARMCOND_MI
5724 * Z Equal ARMCOND_EQ
5725 * C Greater Than or Equal ARMCOND_CS
5726 * V Unordered ARMCOND_VS
5729 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5732 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5735 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5738 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5739 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5745 g_assert_not_reached ();
5749 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5751 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5752 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5753 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5757 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5758 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5763 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5764 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5766 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5767 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5769 *(guint32*)code = 0xffffffff;
5771 *(guint32*)code = 0x7fefffff;
5773 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5775 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5776 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5778 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5779 ARM_CPYD (code, ins->dreg, ins->sreg1);
5781 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5782 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5787 case OP_RCONV_TO_I1:
5788 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5790 case OP_RCONV_TO_U1:
5791 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5793 case OP_RCONV_TO_I2:
5794 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5796 case OP_RCONV_TO_U2:
5797 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5799 case OP_RCONV_TO_I4:
5800 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5802 case OP_RCONV_TO_U4:
5803 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5805 case OP_RCONV_TO_R4:
5807 if (ins->dreg != ins->sreg1)
5808 ARM_CPYS (code, ins->dreg, ins->sreg1);
5810 case OP_RCONV_TO_R8:
5812 ARM_CVTS (code, ins->dreg, ins->sreg1);
5815 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5818 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5821 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5824 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5827 ARM_NEGS (code, ins->dreg, ins->sreg1);
5831 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5834 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5835 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5839 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5842 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5843 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5847 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5850 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5851 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5852 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5856 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5859 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5860 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5864 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5867 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5868 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5869 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5873 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5876 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5877 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5881 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5884 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5885 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5889 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5892 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5893 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5896 case OP_GC_LIVENESS_DEF:
5897 case OP_GC_LIVENESS_USE:
5898 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5899 ins->backend.pc_offset = code - cfg->native_code;
5901 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5902 ins->backend.pc_offset = code - cfg->native_code;
5903 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5905 case OP_GC_SAFE_POINT: {
5908 g_assert (mono_threads_is_coop_enabled ());
5910 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5911 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5913 ARM_B_COND (code, ARMCOND_EQ, 0);
5914 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5915 code = emit_call_seq (cfg, code);
5916 arm_patch (buf [0], code);
5921 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5922 g_assert_not_reached ();
5925 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5926 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5927 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5928 g_assert_not_reached ();
5934 last_offset = offset;
5937 cfg->code_len = code - cfg->native_code;
5940 #endif /* DISABLE_JIT */
5943 mono_arch_register_lowlevel_calls (void)
5945 /* The signature doesn't matter */
5946 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5947 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5948 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5950 #ifndef MONO_CROSS_COMPILE
5951 if (mono_arm_have_tls_get ()) {
5952 MonoTlsImplementation tls_imp = mono_arm_get_tls_implementation ();
5954 mono_register_jit_icall (tls_imp.get_tls_thunk, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
5955 mono_register_jit_icall (tls_imp.set_tls_thunk, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
5957 if (tls_imp.get_tls_thunk_end) {
5958 mono_tramp_info_register (
5959 mono_tramp_info_create (
5961 (guint8*)tls_imp.get_tls_thunk,
5962 (guint8*)tls_imp.get_tls_thunk_end - (guint8*)tls_imp.get_tls_thunk,
5964 mono_arch_get_cie_program ()
5968 mono_tramp_info_register (
5969 mono_tramp_info_create (
5971 (guint8*)tls_imp.set_tls_thunk,
5972 (guint8*)tls_imp.set_tls_thunk_end - (guint8*)tls_imp.set_tls_thunk,
5974 mono_arch_get_cie_program ()
5983 #define patch_lis_ori(ip,val) do {\
5984 guint16 *__lis_ori = (guint16*)(ip); \
5985 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5986 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5990 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5992 unsigned char *ip = ji->ip.i + code;
5994 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5998 case MONO_PATCH_INFO_SWITCH: {
5999 gpointer *jt = (gpointer*)(ip + 8);
6001 /* jt is the inlined jump table, 2 instructions after ip
6002 * In the normal case we store the absolute addresses,
6003 * otherwise the displacements.
6005 for (i = 0; i < ji->data.table->table_size; i++)
6006 jt [i] = code + (int)ji->data.table->table [i];
6009 case MONO_PATCH_INFO_IP:
6010 g_assert_not_reached ();
6011 patch_lis_ori (ip, ip);
6013 case MONO_PATCH_INFO_METHOD_REL:
6014 g_assert_not_reached ();
6015 *((gpointer *)(ip)) = target;
6017 case MONO_PATCH_INFO_METHODCONST:
6018 case MONO_PATCH_INFO_CLASS:
6019 case MONO_PATCH_INFO_IMAGE:
6020 case MONO_PATCH_INFO_FIELD:
6021 case MONO_PATCH_INFO_VTABLE:
6022 case MONO_PATCH_INFO_IID:
6023 case MONO_PATCH_INFO_SFLDA:
6024 case MONO_PATCH_INFO_LDSTR:
6025 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6026 case MONO_PATCH_INFO_LDTOKEN:
6027 g_assert_not_reached ();
6028 /* from OP_AOTCONST : lis + ori */
6029 patch_lis_ori (ip, target);
6031 case MONO_PATCH_INFO_R4:
6032 case MONO_PATCH_INFO_R8:
6033 g_assert_not_reached ();
6034 *((gconstpointer *)(ip + 2)) = target;
6036 case MONO_PATCH_INFO_EXC_NAME:
6037 g_assert_not_reached ();
6038 *((gconstpointer *)(ip + 1)) = target;
6040 case MONO_PATCH_INFO_NONE:
6041 case MONO_PATCH_INFO_BB_OVF:
6042 case MONO_PATCH_INFO_EXC_OVF:
6043 /* everything is dealt with at epilog output time */
6046 arm_patch_general (cfg, domain, ip, target);
6052 mono_arm_unaligned_stack (MonoMethod *method)
6054 g_assert_not_reached ();
6060 * Stack frame layout:
6062 * ------------------- fp
6063 * MonoLMF structure or saved registers
6064 * -------------------
6066 * -------------------
6068 * -------------------
6069 * optional 8 bytes for tracing
6070 * -------------------
6071 * param area size is cfg->param_area
6072 * ------------------- sp
6075 mono_arch_emit_prolog (MonoCompile *cfg)
6077 MonoMethod *method = cfg->method;
6079 MonoMethodSignature *sig;
6081 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6086 int prev_sp_offset, reg_offset;
6088 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6091 sig = mono_method_signature (method);
6092 cfg->code_size = 256 + sig->param_count * 64;
6093 code = cfg->native_code = g_malloc (cfg->code_size);
6095 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6097 alloc_size = cfg->stack_offset;
6103 * The iphone uses R7 as the frame pointer, and it points at the saved
6108 * We can't use r7 as a frame pointer since it points into the middle of
6109 * the frame, so we keep using our own frame pointer.
6110 * FIXME: Optimize this.
6112 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6113 prev_sp_offset += 8; /* r7 and lr */
6114 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6115 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6116 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6119 if (!method->save_lmf) {
6121 /* No need to push LR again */
6122 if (cfg->used_int_regs)
6123 ARM_PUSH (code, cfg->used_int_regs);
6125 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6126 prev_sp_offset += 4;
6128 for (i = 0; i < 16; ++i) {
6129 if (cfg->used_int_regs & (1 << i))
6130 prev_sp_offset += 4;
6132 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6134 for (i = 0; i < 16; ++i) {
6135 if ((cfg->used_int_regs & (1 << i))) {
6136 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6137 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6141 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6142 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6144 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6145 ARM_PUSH (code, 0x5ff0);
6146 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6147 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6149 for (i = 0; i < 16; ++i) {
6150 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6151 /* The original r7 is saved at the start */
6152 if (!(iphone_abi && i == ARMREG_R7))
6153 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6157 g_assert (reg_offset == 4 * 10);
6158 pos += sizeof (MonoLMF) - (4 * 10);
6162 orig_alloc_size = alloc_size;
6163 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6164 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6165 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6166 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6169 /* the stack used in the pushed regs */
6170 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6171 cfg->stack_usage = alloc_size;
6173 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6174 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6176 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6177 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6179 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6181 if (cfg->frame_reg != ARMREG_SP) {
6182 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6183 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6185 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6186 prev_sp_offset += alloc_size;
6188 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6189 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6191 /* compute max_offset in order to use short forward jumps
6192 * we could skip do it on arm because the immediate displacement
6193 * for jumps is large enough, it may be useful later for constant pools
6196 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6197 MonoInst *ins = bb->code;
6198 bb->max_offset = max_offset;
6200 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6203 MONO_BB_FOR_EACH_INS (bb, ins)
6204 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6207 /* stack alignment check */
6211 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6212 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6213 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6214 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6216 ARM_B_COND (code, ARMCOND_EQ, 0);
6217 if (cfg->compile_aot)
6218 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6220 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6221 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6222 code = emit_call_seq (cfg, code);
6223 arm_patch (buf [0], code);
6227 /* store runtime generic context */
6228 if (cfg->rgctx_var) {
6229 MonoInst *ins = cfg->rgctx_var;
6231 g_assert (ins->opcode == OP_REGOFFSET);
6233 if (arm_is_imm12 (ins->inst_offset)) {
6234 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6236 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6237 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6241 /* load arguments allocated to register from the stack */
6244 cinfo = get_call_info (NULL, sig);
6246 if (cinfo->ret.storage == RegTypeStructByAddr) {
6247 ArgInfo *ainfo = &cinfo->ret;
6248 inst = cfg->vret_addr;
6249 g_assert (arm_is_imm12 (inst->inst_offset));
6250 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6253 if (sig->call_convention == MONO_CALL_VARARG) {
6254 ArgInfo *cookie = &cinfo->sig_cookie;
6256 /* Save the sig cookie address */
6257 g_assert (cookie->storage == RegTypeBase);
6259 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6260 g_assert (arm_is_imm12 (cfg->sig_cookie));
6261 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6262 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6265 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6266 ArgInfo *ainfo = cinfo->args + i;
6267 inst = cfg->args [pos];
6269 if (cfg->verbose_level > 2)
6270 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6272 if (inst->opcode == OP_REGVAR) {
6273 if (ainfo->storage == RegTypeGeneral)
6274 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6275 else if (ainfo->storage == RegTypeFP) {
6276 g_assert_not_reached ();
6277 } else if (ainfo->storage == RegTypeBase) {
6278 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6279 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6281 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6282 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6285 g_assert_not_reached ();
6287 if (cfg->verbose_level > 2)
6288 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6290 switch (ainfo->storage) {
6292 for (part = 0; part < ainfo->nregs; part ++) {
6293 if (ainfo->esize == 4)
6294 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6296 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6299 case RegTypeGeneral:
6300 case RegTypeIRegPair:
6301 case RegTypeGSharedVtInReg:
6302 case RegTypeStructByAddr:
6303 switch (ainfo->size) {
6305 if (arm_is_imm12 (inst->inst_offset))
6306 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6308 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6309 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6313 if (arm_is_imm8 (inst->inst_offset)) {
6314 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6316 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6317 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6321 if (arm_is_imm12 (inst->inst_offset)) {
6322 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6324 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6325 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6327 if (arm_is_imm12 (inst->inst_offset + 4)) {
6328 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6330 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6331 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6335 if (arm_is_imm12 (inst->inst_offset)) {
6336 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6338 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6339 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6344 case RegTypeBaseGen:
6345 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6346 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6348 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6349 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6351 if (arm_is_imm12 (inst->inst_offset + 4)) {
6352 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6353 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6355 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6356 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6357 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6358 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6362 case RegTypeGSharedVtOnStack:
6363 case RegTypeStructByAddrOnStack:
6364 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6365 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6367 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6368 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6371 switch (ainfo->size) {
6373 if (arm_is_imm8 (inst->inst_offset)) {
6374 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6376 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6377 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6381 if (arm_is_imm8 (inst->inst_offset)) {
6382 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6384 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6385 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6389 if (arm_is_imm12 (inst->inst_offset)) {
6390 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6392 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6393 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6395 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6396 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6398 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6399 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6401 if (arm_is_imm12 (inst->inst_offset + 4)) {
6402 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6404 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6405 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6409 if (arm_is_imm12 (inst->inst_offset)) {
6410 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6412 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6413 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6419 int imm8, rot_amount;
6421 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6422 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6423 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6425 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6427 if (ainfo->size == 8)
6428 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6430 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6433 case RegTypeStructByVal: {
6434 int doffset = inst->inst_offset;
6438 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6439 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6440 if (arm_is_imm12 (doffset)) {
6441 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6443 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6444 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6446 soffset += sizeof (gpointer);
6447 doffset += sizeof (gpointer);
6449 if (ainfo->vtsize) {
6450 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6451 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6452 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6457 g_assert_not_reached ();
6464 if (method->save_lmf)
6465 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6468 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6470 if (cfg->arch.seq_point_info_var) {
6471 MonoInst *ins = cfg->arch.seq_point_info_var;
6473 /* Initialize the variable from a GOT slot */
6474 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6475 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6477 *(gpointer*)code = NULL;
6479 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6481 g_assert (ins->opcode == OP_REGOFFSET);
6483 if (arm_is_imm12 (ins->inst_offset)) {
6484 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6486 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6487 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6491 /* Initialize ss_trigger_page_var */
6492 if (!cfg->soft_breakpoints) {
6493 MonoInst *info_var = cfg->arch.seq_point_info_var;
6494 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6495 int dreg = ARMREG_LR;
6498 g_assert (info_var->opcode == OP_REGOFFSET);
6499 g_assert (arm_is_imm12 (info_var->inst_offset));
6501 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6502 /* Load the trigger page addr */
6503 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6504 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6508 if (cfg->arch.seq_point_ss_method_var) {
6509 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6510 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6511 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6512 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6513 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6514 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6516 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6518 *(gpointer*)code = &single_step_tramp;
6520 *(gpointer*)code = breakpoint_tramp;
6523 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6524 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6525 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6526 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6529 cfg->code_len = code - cfg->native_code;
6530 g_assert (cfg->code_len < cfg->code_size);
6537 mono_arch_emit_epilog (MonoCompile *cfg)
6539 MonoMethod *method = cfg->method;
6540 int pos, i, rot_amount;
6541 int max_epilog_size = 16 + 20*4;
6545 if (cfg->method->save_lmf)
6546 max_epilog_size += 128;
6548 if (mono_jit_trace_calls != NULL)
6549 max_epilog_size += 50;
6551 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6552 max_epilog_size += 50;
6554 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6555 cfg->code_size *= 2;
6556 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6557 cfg->stat_code_reallocs++;
6561 * Keep in sync with OP_JMP
6563 code = cfg->native_code + cfg->code_len;
6565 /* Save the uwind state which is needed by the out-of-line code */
6566 mono_emit_unwind_op_remember_state (cfg, code);
6568 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6569 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6573 /* Load returned vtypes into registers if needed */
6574 cinfo = cfg->arch.cinfo;
6575 switch (cinfo->ret.storage) {
6576 case RegTypeStructByVal: {
6577 MonoInst *ins = cfg->ret;
6579 if (cinfo->ret.nregs == 1) {
6580 if (arm_is_imm12 (ins->inst_offset)) {
6581 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6583 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6584 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6587 for (i = 0; i < cinfo->ret.nregs; ++i) {
6588 int offset = ins->inst_offset + (i * 4);
6589 if (arm_is_imm12 (offset)) {
6590 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6592 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6593 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6600 MonoInst *ins = cfg->ret;
6602 for (i = 0; i < cinfo->ret.nregs; ++i) {
6603 if (cinfo->ret.esize == 4)
6604 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6606 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6614 if (method->save_lmf) {
6615 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6616 /* all but r0-r3, sp and pc */
6617 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6620 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6622 /* This points to r4 inside MonoLMF->iregs */
6623 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6625 regmask = 0x9ff0; /* restore lr to pc */
6626 /* Skip caller saved registers not used by the method */
6627 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6628 regmask &= ~(1 << reg);
6633 /* Restored later */
6634 regmask &= ~(1 << ARMREG_PC);
6635 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6636 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6637 for (i = 0; i < 16; i++) {
6638 if (regmask & (1 << i))
6641 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6643 ARM_POP (code, regmask);
6645 for (i = 0; i < 16; i++) {
6646 if (regmask & (1 << i))
6647 mono_emit_unwind_op_same_value (cfg, code, i);
6649 /* Restore saved r7, restore LR to PC */
6650 /* Skip lr from the lmf */
6651 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6652 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6653 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6654 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6657 int i, nused_int_regs = 0;
6659 for (i = 0; i < 16; i++) {
6660 if (cfg->used_int_regs & (1 << i))
6664 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6665 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6667 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6668 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6671 if (cfg->frame_reg != ARMREG_SP) {
6672 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6676 /* Restore saved gregs */
6677 if (cfg->used_int_regs) {
6678 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6679 ARM_POP (code, cfg->used_int_regs);
6680 for (i = 0; i < 16; i++) {
6681 if (cfg->used_int_regs & (1 << i))
6682 mono_emit_unwind_op_same_value (cfg, code, i);
6685 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6686 /* Restore saved r7, restore LR to PC */
6687 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6689 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6690 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6694 /* Restore the unwind state to be the same as before the epilog */
6695 mono_emit_unwind_op_restore_state (cfg, code);
6697 cfg->code_len = code - cfg->native_code;
6699 g_assert (cfg->code_len < cfg->code_size);
6704 mono_arch_emit_exceptions (MonoCompile *cfg)
6706 MonoJumpInfo *patch_info;
6709 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6710 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6711 int max_epilog_size = 50;
6713 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6714 exc_throw_pos [i] = NULL;
6715 exc_throw_found [i] = 0;
6718 /* count the number of exception infos */
6721 * make sure we have enough space for exceptions
6723 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6724 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6725 i = mini_exception_id_by_name (patch_info->data.target);
6726 if (!exc_throw_found [i]) {
6727 max_epilog_size += 32;
6728 exc_throw_found [i] = TRUE;
6733 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6734 cfg->code_size *= 2;
6735 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6736 cfg->stat_code_reallocs++;
6739 code = cfg->native_code + cfg->code_len;
6741 /* add code to raise exceptions */
6742 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6743 switch (patch_info->type) {
6744 case MONO_PATCH_INFO_EXC: {
6745 MonoClass *exc_class;
6746 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6748 i = mini_exception_id_by_name (patch_info->data.target);
6749 if (exc_throw_pos [i]) {
6750 arm_patch (ip, exc_throw_pos [i]);
6751 patch_info->type = MONO_PATCH_INFO_NONE;
6754 exc_throw_pos [i] = code;
6756 arm_patch (ip, code);
6758 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6760 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6761 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6762 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6763 patch_info->data.name = "mono_arch_throw_corlib_exception";
6764 patch_info->ip.i = code - cfg->native_code;
6766 cfg->thunk_area += THUNK_SIZE;
6767 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6777 cfg->code_len = code - cfg->native_code;
6779 g_assert (cfg->code_len < cfg->code_size);
6783 #endif /* #ifndef DISABLE_JIT */
6786 mono_arch_finish_init (void)
6791 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6796 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6803 mono_arch_print_tree (MonoInst *tree, int arity)
6813 mono_arch_get_patch_offset (guint8 *code)
6820 mono_arch_flush_register_windows (void)
6825 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6827 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6831 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6833 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6837 mono_arch_get_cie_program (void)
6841 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6846 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6847 #define BASE_SIZE (6 * 4)
6848 #define BSEARCH_ENTRY_SIZE (4 * 4)
6849 #define CMP_SIZE (3 * 4)
6850 #define BRANCH_SIZE (1 * 4)
6851 #define CALL_SIZE (2 * 4)
6852 #define WMC_SIZE (8 * 4)
6853 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6856 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6858 guint32 delta = DISTANCE (target, code);
6860 g_assert (delta >= 0 && delta <= 0xFFF);
6861 *target = *target | delta;
6866 #ifdef ENABLE_WRONG_METHOD_CHECK
6868 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6870 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6876 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6877 gpointer fail_tramp)
6880 arminstr_t *code, *start;
6881 gboolean large_offsets = FALSE;
6882 guint32 **constant_pool_starts;
6883 arminstr_t *vtable_target = NULL;
6884 int extra_space = 0;
6885 #ifdef ENABLE_WRONG_METHOD_CHECK
6891 constant_pool_starts = g_new0 (guint32*, count);
6893 for (i = 0; i < count; ++i) {
6894 MonoIMTCheckItem *item = imt_entries [i];
6895 if (item->is_equals) {
6896 gboolean fail_case = !item->check_target_idx && fail_tramp;
6898 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6899 item->chunk_size += 32;
6900 large_offsets = TRUE;
6903 if (item->check_target_idx || fail_case) {
6904 if (!item->compare_done || fail_case)
6905 item->chunk_size += CMP_SIZE;
6906 item->chunk_size += BRANCH_SIZE;
6908 #ifdef ENABLE_WRONG_METHOD_CHECK
6909 item->chunk_size += WMC_SIZE;
6913 item->chunk_size += 16;
6914 large_offsets = TRUE;
6916 item->chunk_size += CALL_SIZE;
6918 item->chunk_size += BSEARCH_ENTRY_SIZE;
6919 imt_entries [item->check_target_idx]->compare_done = TRUE;
6921 size += item->chunk_size;
6925 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6928 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6930 code = mono_domain_code_reserve (domain, size);
6933 unwind_ops = mono_arch_get_cie_program ();
6936 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6937 for (i = 0; i < count; ++i) {
6938 MonoIMTCheckItem *item = imt_entries [i];
6939 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6943 if (large_offsets) {
6944 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6945 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6947 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6948 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6950 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6951 vtable_target = code;
6952 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6953 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6955 for (i = 0; i < count; ++i) {
6956 MonoIMTCheckItem *item = imt_entries [i];
6957 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6958 gint32 vtable_offset;
6960 item->code_target = (guint8*)code;
6962 if (item->is_equals) {
6963 gboolean fail_case = !item->check_target_idx && fail_tramp;
6965 if (item->check_target_idx || fail_case) {
6966 if (!item->compare_done || fail_case) {
6968 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6969 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6971 item->jmp_code = (guint8*)code;
6972 ARM_B_COND (code, ARMCOND_NE, 0);
6974 /*Enable the commented code to assert on wrong method*/
6975 #ifdef ENABLE_WRONG_METHOD_CHECK
6977 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6978 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6980 ARM_B_COND (code, ARMCOND_EQ, 0);
6982 /* Define this if your system is so bad that gdb is failing. */
6983 #ifdef BROKEN_DEV_ENV
6984 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6986 arm_patch (code - 1, mini_dump_bad_imt);
6990 arm_patch (cond, code);
6994 if (item->has_target_code) {
6995 /* Load target address */
6996 target_code_ins = code;
6997 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6998 /* Save it to the fourth slot */
6999 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7000 /* Restore registers and branch */
7001 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7003 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7005 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7006 if (!arm_is_imm12 (vtable_offset)) {
7008 * We need to branch to a computed address but we don't have
7009 * a free register to store it, since IP must contain the
7010 * vtable address. So we push the two values to the stack, and
7011 * load them both using LDM.
7013 /* Compute target address */
7014 vtable_offset_ins = code;
7015 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7016 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7017 /* Save it to the fourth slot */
7018 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7019 /* Restore registers and branch */
7020 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7022 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7024 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7025 if (large_offsets) {
7026 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7027 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7029 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7030 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7035 arm_patch (item->jmp_code, (guchar*)code);
7037 target_code_ins = code;
7038 /* Load target address */
7039 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7040 /* Save it to the fourth slot */
7041 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7042 /* Restore registers and branch */
7043 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7045 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7046 item->jmp_code = NULL;
7050 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7052 /*must emit after unconditional branch*/
7053 if (vtable_target) {
7054 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7055 item->chunk_size += 4;
7056 vtable_target = NULL;
7059 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7060 constant_pool_starts [i] = code;
7062 code += extra_space;
7066 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7067 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7069 item->jmp_code = (guint8*)code;
7070 ARM_B_COND (code, ARMCOND_HS, 0);
7075 for (i = 0; i < count; ++i) {
7076 MonoIMTCheckItem *item = imt_entries [i];
7077 if (item->jmp_code) {
7078 if (item->check_target_idx)
7079 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7081 if (i > 0 && item->is_equals) {
7083 arminstr_t *space_start = constant_pool_starts [i];
7084 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7085 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7092 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7093 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7098 g_free (constant_pool_starts);
7100 mono_arch_flush_icache ((guint8*)start, size);
7101 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7102 mono_stats.imt_thunks_size += code - start;
7104 g_assert (DISTANCE (start, code) <= size);
7106 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7112 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7114 return ctx->regs [reg];
7118 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7120 ctx->regs [reg] = val;
7124 * mono_arch_get_trampolines:
7126 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7130 mono_arch_get_trampolines (gboolean aot)
7132 return mono_arm_get_exception_trampolines (aot);
7136 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7143 bp = MONO_CONTEXT_GET_BP (ctx);
7144 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7146 old_value = *lr_loc;
7147 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7150 *lr_loc = new_value;
7155 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7157 * mono_arch_set_breakpoint:
7159 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7160 * The location should contain code emitted by OP_SEQ_POINT.
7163 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7166 guint32 native_offset = ip - (guint8*)ji->code_start;
7167 MonoDebugOptions *opt = mini_get_debug_options ();
7169 if (opt->soft_breakpoints) {
7170 g_assert (!ji->from_aot);
7172 ARM_BLX_REG (code, ARMREG_LR);
7173 mono_arch_flush_icache (code - 4, 4);
7174 } else if (ji->from_aot) {
7175 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7177 g_assert (native_offset % 4 == 0);
7178 g_assert (info->bp_addrs [native_offset / 4] == 0);
7179 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7181 int dreg = ARMREG_LR;
7183 /* Read from another trigger page */
7184 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7186 *(int*)code = (int)bp_trigger_page;
7188 ARM_LDR_IMM (code, dreg, dreg, 0);
7190 mono_arch_flush_icache (code - 16, 16);
7193 /* This is currently implemented by emitting an SWI instruction, which
7194 * qemu/linux seems to convert to a SIGILL.
7196 *(int*)code = (0xef << 24) | 8;
7198 mono_arch_flush_icache (code - 4, 4);
7204 * mono_arch_clear_breakpoint:
7206 * Clear the breakpoint at IP.
7209 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7211 MonoDebugOptions *opt = mini_get_debug_options ();
7215 if (opt->soft_breakpoints) {
7216 g_assert (!ji->from_aot);
7219 mono_arch_flush_icache (code - 4, 4);
7220 } else if (ji->from_aot) {
7221 guint32 native_offset = ip - (guint8*)ji->code_start;
7222 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7224 g_assert (native_offset % 4 == 0);
7225 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7226 info->bp_addrs [native_offset / 4] = 0;
7228 for (i = 0; i < 4; ++i)
7231 mono_arch_flush_icache (ip, code - ip);
7236 * mono_arch_start_single_stepping:
7238 * Start single stepping.
7241 mono_arch_start_single_stepping (void)
7243 if (ss_trigger_page)
7244 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7246 single_step_tramp = mini_get_single_step_trampoline ();
7250 * mono_arch_stop_single_stepping:
7252 * Stop single stepping.
7255 mono_arch_stop_single_stepping (void)
7257 if (ss_trigger_page)
7258 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7260 single_step_tramp = NULL;
7264 #define DBG_SIGNAL SIGBUS
7266 #define DBG_SIGNAL SIGSEGV
7270 * mono_arch_is_single_step_event:
7272 * Return whenever the machine state in SIGCTX corresponds to a single
7276 mono_arch_is_single_step_event (void *info, void *sigctx)
7278 siginfo_t *sinfo = info;
7280 if (!ss_trigger_page)
7283 /* Sometimes the address is off by 4 */
7284 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7291 * mono_arch_is_breakpoint_event:
7293 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7296 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7298 siginfo_t *sinfo = info;
7300 if (!ss_trigger_page)
7303 if (sinfo->si_signo == DBG_SIGNAL) {
7304 /* Sometimes the address is off by 4 */
7305 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7315 * mono_arch_skip_breakpoint:
7317 * See mini-amd64.c for docs.
7320 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7322 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7326 * mono_arch_skip_single_step:
7328 * See mini-amd64.c for docs.
7331 mono_arch_skip_single_step (MonoContext *ctx)
7333 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7336 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7339 * mono_arch_get_seq_point_info:
7341 * See mini-amd64.c for docs.
7344 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7349 // FIXME: Add a free function
7351 mono_domain_lock (domain);
7352 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7354 mono_domain_unlock (domain);
7357 ji = mono_jit_info_table_find (domain, (char*)code);
7360 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7362 info->ss_trigger_page = ss_trigger_page;
7363 info->bp_trigger_page = bp_trigger_page;
7365 mono_domain_lock (domain);
7366 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7368 mono_domain_unlock (domain);
7375 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7377 ext->lmf.previous_lmf = prev_lmf;
7378 /* Mark that this is a MonoLMFExt */
7379 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7380 ext->lmf.sp = (gssize)ext;
7384 * mono_arch_set_target:
7386 * Set the target architecture the JIT backend should generate code for, in the form
7387 * of a GNU target triplet. Only used in AOT mode.
7390 mono_arch_set_target (char *mtriple)
7392 /* The GNU target triple format is not very well documented */
7393 if (strstr (mtriple, "armv7")) {
7394 v5_supported = TRUE;
7395 v6_supported = TRUE;
7396 v7_supported = TRUE;
7398 if (strstr (mtriple, "armv6")) {
7399 v5_supported = TRUE;
7400 v6_supported = TRUE;
7402 if (strstr (mtriple, "armv7s")) {
7403 v7s_supported = TRUE;
7405 if (strstr (mtriple, "armv7k")) {
7406 v7k_supported = TRUE;
7408 if (strstr (mtriple, "thumbv7s")) {
7409 v5_supported = TRUE;
7410 v6_supported = TRUE;
7411 v7_supported = TRUE;
7412 v7s_supported = TRUE;
7413 thumb_supported = TRUE;
7414 thumb2_supported = TRUE;
7416 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7417 v5_supported = TRUE;
7418 v6_supported = TRUE;
7419 thumb_supported = TRUE;
7422 if (strstr (mtriple, "gnueabi"))
7423 eabi_supported = TRUE;
7427 mono_arch_opcode_supported (int opcode)
7430 case OP_ATOMIC_ADD_I4:
7431 case OP_ATOMIC_EXCHANGE_I4:
7432 case OP_ATOMIC_CAS_I4:
7433 case OP_ATOMIC_LOAD_I1:
7434 case OP_ATOMIC_LOAD_I2:
7435 case OP_ATOMIC_LOAD_I4:
7436 case OP_ATOMIC_LOAD_U1:
7437 case OP_ATOMIC_LOAD_U2:
7438 case OP_ATOMIC_LOAD_U4:
7439 case OP_ATOMIC_STORE_I1:
7440 case OP_ATOMIC_STORE_I2:
7441 case OP_ATOMIC_STORE_I4:
7442 case OP_ATOMIC_STORE_U1:
7443 case OP_ATOMIC_STORE_U2:
7444 case OP_ATOMIC_STORE_U4:
7445 return v7_supported;
7446 case OP_ATOMIC_LOAD_R4:
7447 case OP_ATOMIC_LOAD_R8:
7448 case OP_ATOMIC_STORE_R4:
7449 case OP_ATOMIC_STORE_R8:
7450 return v7_supported && IS_VFP;
7457 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7459 return get_call_info (mp, sig);