2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
16 #include <mono/metadata/abi-details.h>
17 #include <mono/metadata/appdomain.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/utils/mono-mmap.h>
21 #include <mono/utils/mono-hwcap-arm.h>
22 #include <mono/utils/mono-memory-model.h>
25 #include "mini-arm-tls.h"
29 #include "debugger-agent.h"
31 #include "mono/arch/arm/arm-vfp-codegen.h"
33 #if (defined(HAVE_KW_THREAD) && defined(__linux__) && defined(__ARM_EABI__)) \
34 || defined(TARGET_ANDROID) \
35 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
39 /* Sanity check: This makes no sense */
40 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
41 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
45 * IS_SOFT_FLOAT: Is full software floating point used?
46 * IS_HARD_FLOAT: Is full hardware floating point used?
47 * IS_VFP: Is hardware floating point with software ABI used?
49 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
50 * IS_VFP may delegate to mono_arch_is_soft_float ().
53 #if defined(ARM_FPU_VFP_HARD)
54 #define IS_SOFT_FLOAT (FALSE)
55 #define IS_HARD_FLOAT (TRUE)
57 #elif defined(ARM_FPU_NONE)
58 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
59 #define IS_HARD_FLOAT (FALSE)
60 #define IS_VFP (!mono_arch_is_soft_float ())
62 #define IS_SOFT_FLOAT (FALSE)
63 #define IS_HARD_FLOAT (FALSE)
67 #define THUNK_SIZE (3 * 4)
69 #ifdef __native_client_codegen__
70 const guint kNaClAlignment = kNaClAlignmentARM;
71 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
72 gint8 nacl_align_byte = -1; /* 0xff */
75 mono_arch_nacl_pad (guint8 *code, int pad)
77 /* Not yet properly implemented. */
78 g_assert_not_reached ();
83 mono_arch_nacl_skip_nops (guint8 *code)
85 /* Not yet properly implemented. */
86 g_assert_not_reached ();
90 #endif /* __native_client_codegen__ */
92 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
95 void sys_icache_invalidate (void *start, size_t len);
98 /* This mutex protects architecture specific caches */
99 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
100 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
101 static mono_mutex_t mini_arch_mutex;
103 static gboolean v5_supported = FALSE;
104 static gboolean v6_supported = FALSE;
105 static gboolean v7_supported = FALSE;
106 static gboolean v7s_supported = FALSE;
107 static gboolean v7k_supported = FALSE;
108 static gboolean thumb_supported = FALSE;
109 static gboolean thumb2_supported = FALSE;
111 * Whenever to use the ARM EABI
113 static gboolean eabi_supported = FALSE;
116 * Whenever to use the iphone ABI extensions:
117 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
118 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
119 * This is required for debugging/profiling tools to work, but it has some overhead so it should
120 * only be turned on in debug builds.
122 static gboolean iphone_abi = FALSE;
125 * The FPU we are generating code for. This is NOT runtime configurable right now,
126 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
128 static MonoArmFPU arm_fpu;
130 #if defined(ARM_FPU_VFP_HARD)
132 * On armhf, d0-d7 are used for argument passing and d8-d15
133 * must be preserved across calls, which leaves us no room
134 * for scratch registers. So we use d14-d15 but back up their
135 * previous contents to a stack slot before using them - see
136 * mono_arm_emit_vfp_scratch_save/_restore ().
138 static int vfp_scratch1 = ARM_VFP_D14;
139 static int vfp_scratch2 = ARM_VFP_D15;
142 * On armel, d0-d7 do not need to be preserved, so we can
143 * freely make use of them as scratch registers.
145 static int vfp_scratch1 = ARM_VFP_D0;
146 static int vfp_scratch2 = ARM_VFP_D1;
151 static gpointer single_step_tramp, breakpoint_tramp;
154 * The code generated for sequence points reads from this location, which is
155 * made read-only when single stepping is enabled.
157 static gpointer ss_trigger_page;
159 /* Enabled breakpoints read from this trigger page */
160 static gpointer bp_trigger_page;
164 * floating point support: on ARM it is a mess, there are at least 3
165 * different setups, each of which binary incompat with the other.
166 * 1) FPA: old and ugly, but unfortunately what current distros use
167 * the double binary format has the two words swapped. 8 double registers.
168 * Implemented usually by kernel emulation.
169 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
170 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
171 * 3) VFP: the new and actually sensible and useful FP support. Implemented
172 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
174 * We do not care about FPA. We will support soft float and VFP.
176 int mono_exc_esp_offset = 0;
178 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
179 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
180 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
182 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
183 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
184 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
186 //#define DEBUG_IMT 0
189 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
193 mono_arch_regname (int reg)
195 static const char * rnames[] = {
196 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
197 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
198 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
201 if (reg >= 0 && reg < 16)
207 mono_arch_fregname (int reg)
209 static const char * rnames[] = {
210 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
211 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
212 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
213 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
214 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
215 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
218 if (reg >= 0 && reg < 32)
226 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
228 int imm8, rot_amount;
229 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
230 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
234 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
235 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
237 code = mono_arm_emit_load_imm (code, dreg, imm);
238 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
243 /* If dreg == sreg, this clobbers IP */
245 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
247 int imm8, rot_amount;
248 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
249 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
253 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
254 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
256 code = mono_arm_emit_load_imm (code, dreg, imm);
257 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
263 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
265 /* we can use r0-r3, since this is called only for incoming args on the stack */
266 if (size > sizeof (gpointer) * 4) {
268 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
269 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
270 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
271 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
272 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
273 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
274 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
275 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
276 ARM_B_COND (code, ARMCOND_NE, 0);
277 arm_patch (code - 4, start_loop);
280 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
281 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
283 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
284 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
290 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
291 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
292 doffset = soffset = 0;
294 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
295 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
301 g_assert (size == 0);
306 emit_call_reg (guint8 *code, int reg)
309 ARM_BLX_REG (code, reg);
311 #ifdef USE_JUMP_TABLES
312 g_assert_not_reached ();
314 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
318 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
324 emit_call_seq (MonoCompile *cfg, guint8 *code)
326 #ifdef USE_JUMP_TABLES
327 code = mono_arm_patchable_bl (code, ARMCOND_AL);
329 if (cfg->method->dynamic) {
330 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
332 *(gpointer*)code = NULL;
334 code = emit_call_reg (code, ARMREG_IP);
338 cfg->thunk_area += THUNK_SIZE;
344 mono_arm_patchable_b (guint8 *code, int cond)
346 #ifdef USE_JUMP_TABLES
349 jte = mono_jumptable_add_entry ();
350 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
351 ARM_BX_COND (code, cond, ARMREG_IP);
353 ARM_B_COND (code, cond, 0);
359 mono_arm_patchable_bl (guint8 *code, int cond)
361 #ifdef USE_JUMP_TABLES
364 jte = mono_jumptable_add_entry ();
365 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
366 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
368 ARM_BL_COND (code, cond, 0);
373 #ifdef USE_JUMP_TABLES
375 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
377 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
378 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
383 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
385 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
386 ARM_LDR_IMM (code, reg, reg, 0);
392 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
395 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
396 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
398 code = emit_call_seq (cfg, code);
399 if (dreg != ARMREG_R0)
400 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
402 g_assert_not_reached ();
408 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
411 if (tls_offset_reg != ARMREG_R0)
412 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
413 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
415 code = emit_call_seq (cfg, code);
416 if (dreg != ARMREG_R0)
417 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
419 g_assert_not_reached ();
425 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
428 if (sreg != ARMREG_R1)
429 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
430 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
431 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
433 code = emit_call_seq (cfg, code);
435 g_assert_not_reached ();
441 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
444 /* Get sreg in R1 and tls_offset_reg in R0 */
445 if (tls_offset_reg == ARMREG_R1) {
446 if (sreg == ARMREG_R0) {
447 /* swap sreg and tls_offset_reg */
448 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
449 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
450 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
452 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
453 if (sreg != ARMREG_R1)
454 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
457 if (sreg != ARMREG_R1)
458 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
459 if (tls_offset_reg != ARMREG_R0)
460 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
462 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
464 code = emit_call_seq (cfg, code);
466 g_assert_not_reached ();
474 * Emit code to push an LMF structure on the LMF stack.
475 * On arm, this is intermixed with the initialization of other fields of the structure.
478 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
480 gboolean get_lmf_fast = FALSE;
483 if (mono_arm_have_tls_get ()) {
485 if (cfg->compile_aot) {
487 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
488 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
490 *(gpointer*)code = NULL;
492 /* Load the value from the GOT */
493 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
494 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
496 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
497 g_assert (lmf_addr_tls_offset != -1);
498 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
503 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
504 (gpointer)"mono_get_lmf_addr");
505 code = emit_call_seq (cfg, code);
507 /* we build the MonoLMF structure on the stack - see mini-arm.h */
508 /* lmf_offset is the offset from the previous stack pointer,
509 * alloc_size is the total stack space allocated, so the offset
510 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
511 * The pointer to the struct is put in r1 (new_lmf).
512 * ip is used as scratch
513 * The callee-saved registers are already in the MonoLMF structure
515 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
516 /* r0 is the result from mono_get_lmf_addr () */
517 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
518 /* new_lmf->previous_lmf = *lmf_addr */
519 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
520 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
521 /* *(lmf_addr) = r1 */
522 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
523 /* Skip method (only needed for trampoline LMF frames) */
524 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
525 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
526 /* save the current IP */
527 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
528 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
530 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
531 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
542 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
546 g_assert (!cfg->r4fp);
548 for (list = inst->float_args; list; list = list->next) {
549 FloatArgData *fad = list->data;
550 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
551 gboolean imm = arm_is_fpimm8 (var->inst_offset);
553 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
559 if (*offset + *max_len > cfg->code_size) {
560 cfg->code_size += *max_len;
561 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
563 code = cfg->native_code + *offset;
567 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
568 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
570 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
572 *offset = code - cfg->native_code;
579 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
583 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
585 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
588 if (!arm_is_fpimm8 (inst->inst_offset)) {
589 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
590 ARM_FSTD (code, reg, ARMREG_LR, 0);
592 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
599 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
603 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
605 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
608 if (!arm_is_fpimm8 (inst->inst_offset)) {
609 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
610 ARM_FLDD (code, reg, ARMREG_LR, 0);
612 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
621 * Emit code to pop an LMF structure from the LMF stack.
624 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
628 if (lmf_offset < 32) {
629 basereg = cfg->frame_reg;
634 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
637 /* ip = previous_lmf */
638 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
640 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
641 /* *(lmf_addr) = previous_lmf */
642 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
647 #endif /* #ifndef DISABLE_JIT */
650 * mono_arm_have_tls_get:
652 * Returns whether we have tls access implemented on the current
656 mono_arm_have_tls_get (void)
666 * mono_arch_get_argument_info:
667 * @csig: a method signature
668 * @param_count: the number of parameters to consider
669 * @arg_info: an array to store the result infos
671 * Gathers information on parameters such as size, alignment and
672 * padding. arg_info should be large enought to hold param_count + 1 entries.
674 * Returns the size of the activation frame.
677 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
679 int k, frame_size = 0;
680 guint32 size, align, pad;
684 t = mini_get_underlying_type (csig->ret);
685 if (MONO_TYPE_ISSTRUCT (t)) {
686 frame_size += sizeof (gpointer);
690 arg_info [0].offset = offset;
693 frame_size += sizeof (gpointer);
697 arg_info [0].size = frame_size;
699 for (k = 0; k < param_count; k++) {
700 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
702 /* ignore alignment for now */
705 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
706 arg_info [k].pad = pad;
708 arg_info [k + 1].pad = 0;
709 arg_info [k + 1].size = size;
711 arg_info [k + 1].offset = offset;
715 align = MONO_ARCH_FRAME_ALIGNMENT;
716 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
717 arg_info [k].pad = pad;
722 #define MAX_ARCH_DELEGATE_PARAMS 3
725 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
727 guint8 *code, *start;
728 GSList *unwind_ops = mono_arch_get_cie_program ();
731 start = code = mono_global_codeman_reserve (12);
733 /* Replace the this argument with the target */
734 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
735 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
736 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
738 g_assert ((code - start) <= 12);
740 mono_arch_flush_icache (start, 12);
744 size = 8 + param_count * 4;
745 start = code = mono_global_codeman_reserve (size);
747 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
748 /* slide down the arguments */
749 for (i = 0; i < param_count; ++i) {
750 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
752 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
754 g_assert ((code - start) <= size);
756 mono_arch_flush_icache (start, size);
760 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
762 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
763 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
767 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
773 * mono_arch_get_delegate_invoke_impls:
775 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
779 mono_arch_get_delegate_invoke_impls (void)
785 get_delegate_invoke_impl (&info, TRUE, 0);
786 res = g_slist_prepend (res, info);
788 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
789 get_delegate_invoke_impl (&info, FALSE, i);
790 res = g_slist_prepend (res, info);
797 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
799 guint8 *code, *start;
802 /* FIXME: Support more cases */
803 sig_ret = mini_get_underlying_type (sig->ret);
804 if (MONO_TYPE_ISSTRUCT (sig_ret))
808 static guint8* cached = NULL;
809 mono_mini_arch_lock ();
811 mono_mini_arch_unlock ();
816 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
819 start = get_delegate_invoke_impl (&info, TRUE, 0);
820 mono_tramp_info_register (info, NULL);
823 mono_mini_arch_unlock ();
826 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
829 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
831 for (i = 0; i < sig->param_count; ++i)
832 if (!mono_is_regsize_var (sig->params [i]))
835 mono_mini_arch_lock ();
836 code = cache [sig->param_count];
838 mono_mini_arch_unlock ();
843 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
844 start = mono_aot_get_trampoline (name);
848 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
849 mono_tramp_info_register (info, NULL);
851 cache [sig->param_count] = start;
852 mono_mini_arch_unlock ();
860 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
866 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
868 return (gpointer)regs [ARMREG_R0];
872 * Initialize the cpu to execute managed code.
875 mono_arch_cpu_init (void)
877 i8_align = MONO_ABI_ALIGNOF (gint64);
878 #ifdef MONO_CROSS_COMPILE
879 /* Need to set the alignment of i8 since it can different on the target */
880 #ifdef TARGET_ANDROID
882 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
888 * Initialize architecture specific code.
891 mono_arch_init (void)
893 const char *cpu_arch;
895 mono_os_mutex_init_recursive (&mini_arch_mutex);
896 if (mini_get_debug_options ()->soft_breakpoints) {
897 breakpoint_tramp = mini_get_breakpoint_trampoline ();
899 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
900 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
901 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
904 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
905 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
906 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
907 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
908 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
910 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
912 #if defined(__ARM_EABI__)
913 eabi_supported = TRUE;
916 #if defined(ARM_FPU_VFP_HARD)
917 arm_fpu = MONO_ARM_FPU_VFP_HARD;
919 arm_fpu = MONO_ARM_FPU_VFP;
921 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
923 * If we're compiling with a soft float fallback and it
924 * turns out that no VFP unit is available, we need to
925 * switch to soft float. We don't do this for iOS, since
926 * iOS devices always have a VFP unit.
928 if (!mono_hwcap_arm_has_vfp)
929 arm_fpu = MONO_ARM_FPU_NONE;
932 * This environment variable can be useful in testing
933 * environments to make sure the soft float fallback
934 * works. Most ARM devices have VFP units these days, so
935 * normally soft float code would not be exercised much.
937 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
939 if (soft && !strncmp (soft, "1", 1))
940 arm_fpu = MONO_ARM_FPU_NONE;
944 v5_supported = mono_hwcap_arm_is_v5;
945 v6_supported = mono_hwcap_arm_is_v6;
946 v7_supported = mono_hwcap_arm_is_v7;
948 #if defined(__APPLE__)
949 /* iOS is special-cased here because we don't yet
950 have a way to properly detect CPU features on it. */
951 thumb_supported = TRUE;
954 thumb_supported = mono_hwcap_arm_has_thumb;
955 thumb2_supported = mono_hwcap_arm_has_thumb2;
958 /* Format: armv(5|6|7[s])[-thumb[2]] */
959 cpu_arch = g_getenv ("MONO_CPU_ARCH");
961 /* Do this here so it overrides any detection. */
963 if (strncmp (cpu_arch, "armv", 4) == 0) {
964 v5_supported = cpu_arch [4] >= '5';
965 v6_supported = cpu_arch [4] >= '6';
966 v7_supported = cpu_arch [4] >= '7';
967 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
968 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
971 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
972 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
977 * Cleanup architecture specific code.
980 mono_arch_cleanup (void)
985 * This function returns the optimizations supported on this cpu.
988 mono_arch_cpu_optimizations (guint32 *exclude_mask)
990 /* no arm-specific optimizations yet */
996 * This function test for all SIMD functions supported.
998 * Returns a bitmask corresponding to all supported versions.
1002 mono_arch_cpu_enumerate_simd_versions (void)
1004 /* SIMD is currently unimplemented */
1012 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1014 if (v7s_supported || v7k_supported) {
1028 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1030 mono_arch_is_soft_float (void)
1032 return arm_fpu == MONO_ARM_FPU_NONE;
1037 mono_arm_is_hard_float (void)
1039 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1043 is_regsize_var (MonoType *t)
1047 t = mini_get_underlying_type (t);
1054 case MONO_TYPE_FNPTR:
1056 case MONO_TYPE_OBJECT:
1057 case MONO_TYPE_STRING:
1058 case MONO_TYPE_CLASS:
1059 case MONO_TYPE_SZARRAY:
1060 case MONO_TYPE_ARRAY:
1062 case MONO_TYPE_GENERICINST:
1063 if (!mono_type_generic_inst_is_valuetype (t))
1066 case MONO_TYPE_VALUETYPE:
1073 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1078 for (i = 0; i < cfg->num_varinfo; i++) {
1079 MonoInst *ins = cfg->varinfo [i];
1080 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1083 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1086 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1089 /* we can only allocate 32 bit values */
1090 if (is_regsize_var (ins->inst_vtype)) {
1091 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1092 g_assert (i == vmv->idx);
1093 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1101 mono_arch_get_global_int_regs (MonoCompile *cfg)
1105 mono_arch_compute_omit_fp (cfg);
1108 * FIXME: Interface calls might go through a static rgctx trampoline which
1109 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1112 if (cfg->flags & MONO_CFG_HAS_CALLS)
1113 cfg->uses_rgctx_reg = TRUE;
1115 if (cfg->arch.omit_fp)
1116 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1117 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1118 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1119 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1121 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1122 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1124 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1125 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1126 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1127 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1128 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1129 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1135 * mono_arch_regalloc_cost:
1137 * Return the cost, in number of memory references, of the action of
1138 * allocating the variable VMV into a register during global register
1142 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1148 #endif /* #ifndef DISABLE_JIT */
1151 mono_arch_flush_icache (guint8 *code, gint size)
1153 #if defined(MONO_CROSS_COMPILE) || defined(__native_client__)
1154 // For Native Client we don't have to flush i-cache here,
1155 // as it's being done by dyncode interface.
1157 sys_icache_invalidate (code, size);
1159 __builtin___clear_cache (code, code + size);
1166 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1169 if (*gr > ARMREG_R3) {
1171 ainfo->offset = *stack_size;
1172 ainfo->reg = ARMREG_SP; /* in the caller */
1173 ainfo->storage = RegTypeBase;
1176 ainfo->storage = RegTypeGeneral;
1183 split = i8_align == 4;
1188 if (*gr == ARMREG_R3 && split) {
1189 /* first word in r3 and the second on the stack */
1190 ainfo->offset = *stack_size;
1191 ainfo->reg = ARMREG_SP; /* in the caller */
1192 ainfo->storage = RegTypeBaseGen;
1194 } else if (*gr >= ARMREG_R3) {
1195 if (eabi_supported) {
1196 /* darwin aligns longs to 4 byte only */
1197 if (i8_align == 8) {
1202 ainfo->offset = *stack_size;
1203 ainfo->reg = ARMREG_SP; /* in the caller */
1204 ainfo->storage = RegTypeBase;
1207 if (eabi_supported) {
1208 if (i8_align == 8 && ((*gr) & 1))
1211 ainfo->storage = RegTypeIRegPair;
1220 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1223 * If we're calling a function like this:
1225 * void foo(float a, double b, float c)
1227 * We pass a in s0 and b in d1. That leaves us
1228 * with s1 being unused. The armhf ABI recognizes
1229 * this and requires register assignment to then
1230 * use that for the next single-precision arg,
1231 * i.e. c in this example. So float_spare either
1232 * tells us which reg to use for the next single-
1233 * precision arg, or it's -1, meaning use *fpr.
1235 * Note that even though most of the JIT speaks
1236 * double-precision, fpr represents single-
1237 * precision registers.
1239 * See parts 5.5 and 6.1.2 of the AAPCS for how
1243 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1244 ainfo->storage = RegTypeFP;
1248 * If we're passing a double-precision value
1249 * and *fpr is odd (e.g. it's s1, s3, ...)
1250 * we need to use the next even register. So
1251 * we mark the current *fpr as a spare that
1252 * can be used for the next single-precision
1256 *float_spare = *fpr;
1261 * At this point, we have an even register
1262 * so we assign that and move along.
1266 } else if (*float_spare >= 0) {
1268 * We're passing a single-precision value
1269 * and it looks like a spare single-
1270 * precision register is available. Let's
1274 ainfo->reg = *float_spare;
1278 * If we hit this branch, we're passing a
1279 * single-precision value and we can simply
1280 * use the next available register.
1288 * We've exhausted available floating point
1289 * regs, so pass the rest on the stack.
1297 ainfo->offset = *stack_size;
1298 ainfo->reg = ARMREG_SP;
1299 ainfo->storage = RegTypeBase;
1306 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1310 MonoClassField *field;
1311 MonoType *ftype, *prev_ftype = NULL;
1314 klass = mono_class_from_mono_type (t);
1316 while ((field = mono_class_get_fields (klass, &iter))) {
1317 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1319 ftype = mono_field_get_type (field);
1320 ftype = mini_get_underlying_type (ftype);
1322 if (MONO_TYPE_ISSTRUCT (ftype)) {
1323 int nested_nfields, nested_esize;
1325 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1327 if (nested_esize == 4)
1328 ftype = &mono_defaults.single_class->byval_arg;
1330 ftype = &mono_defaults.double_class->byval_arg;
1331 if (prev_ftype && prev_ftype->type != ftype->type)
1334 nfields += nested_nfields;
1336 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1338 if (prev_ftype && prev_ftype->type != ftype->type)
1344 if (nfields == 0 || nfields > 4)
1346 *out_nfields = nfields;
1347 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1352 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1354 guint i, gr, fpr, pstart;
1356 int n = sig->hasthis + sig->param_count;
1360 guint32 stack_size = 0;
1362 gboolean is_pinvoke = sig->pinvoke;
1363 gboolean vtype_retaddr = FALSE;
1366 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1368 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1375 t = mini_get_underlying_type (sig->ret);
1386 case MONO_TYPE_FNPTR:
1387 case MONO_TYPE_CLASS:
1388 case MONO_TYPE_OBJECT:
1389 case MONO_TYPE_SZARRAY:
1390 case MONO_TYPE_ARRAY:
1391 case MONO_TYPE_STRING:
1392 cinfo->ret.storage = RegTypeGeneral;
1393 cinfo->ret.reg = ARMREG_R0;
1397 cinfo->ret.storage = RegTypeIRegPair;
1398 cinfo->ret.reg = ARMREG_R0;
1402 cinfo->ret.storage = RegTypeFP;
1404 if (t->type == MONO_TYPE_R4)
1405 cinfo->ret.size = 4;
1407 cinfo->ret.size = 8;
1409 if (IS_HARD_FLOAT) {
1410 cinfo->ret.reg = ARM_VFP_F0;
1412 cinfo->ret.reg = ARMREG_R0;
1415 case MONO_TYPE_GENERICINST:
1416 if (!mono_type_generic_inst_is_valuetype (t)) {
1417 cinfo->ret.storage = RegTypeGeneral;
1418 cinfo->ret.reg = ARMREG_R0;
1421 if (mini_is_gsharedvt_variable_type (t)) {
1422 cinfo->ret.storage = RegTypeStructByAddr;
1426 case MONO_TYPE_VALUETYPE:
1427 case MONO_TYPE_TYPEDBYREF:
1428 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1429 cinfo->ret.storage = RegTypeHFA;
1431 cinfo->ret.nregs = nfields;
1432 cinfo->ret.esize = esize;
1434 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1435 cinfo->ret.storage = RegTypeStructByVal;
1437 cinfo->ret.storage = RegTypeStructByAddr;
1441 case MONO_TYPE_MVAR:
1442 g_assert (mini_is_gsharedvt_type (t));
1443 cinfo->ret.storage = RegTypeStructByAddr;
1445 case MONO_TYPE_VOID:
1448 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1451 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1456 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1457 * the first argument, allowing 'this' to be always passed in the first arg reg.
1458 * Also do this if the first argument is a reference type, since virtual calls
1459 * are sometimes made using calli without sig->hasthis set, like in the delegate
1462 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1464 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1466 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1470 cinfo->ret.reg = gr;
1472 cinfo->vret_arg_index = 1;
1476 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1479 if (vtype_retaddr) {
1480 cinfo->ret.reg = gr;
1485 DEBUG(g_print("params: %d\n", sig->param_count));
1486 for (i = pstart; i < sig->param_count; ++i) {
1487 ArgInfo *ainfo = &cinfo->args [n];
1489 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1490 /* Prevent implicit arguments and sig_cookie from
1491 being passed in registers */
1494 /* Emit the signature cookie just before the implicit arguments */
1495 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1497 DEBUG(g_print("param %d: ", i));
1498 if (sig->params [i]->byref) {
1499 DEBUG(g_print("byref\n"));
1500 add_general (&gr, &stack_size, ainfo, TRUE);
1504 t = mini_get_underlying_type (sig->params [i]);
1508 cinfo->args [n].size = 1;
1509 add_general (&gr, &stack_size, ainfo, TRUE);
1513 cinfo->args [n].size = 2;
1514 add_general (&gr, &stack_size, ainfo, TRUE);
1518 cinfo->args [n].size = 4;
1519 add_general (&gr, &stack_size, ainfo, TRUE);
1524 case MONO_TYPE_FNPTR:
1525 case MONO_TYPE_CLASS:
1526 case MONO_TYPE_OBJECT:
1527 case MONO_TYPE_STRING:
1528 case MONO_TYPE_SZARRAY:
1529 case MONO_TYPE_ARRAY:
1530 cinfo->args [n].size = sizeof (gpointer);
1531 add_general (&gr, &stack_size, ainfo, TRUE);
1533 case MONO_TYPE_GENERICINST:
1534 if (!mono_type_generic_inst_is_valuetype (t)) {
1535 cinfo->args [n].size = sizeof (gpointer);
1536 add_general (&gr, &stack_size, ainfo, TRUE);
1539 if (mini_is_gsharedvt_variable_type (t)) {
1540 /* gsharedvt arguments are passed by ref */
1541 g_assert (mini_is_gsharedvt_type (t));
1542 add_general (&gr, &stack_size, ainfo, TRUE);
1543 switch (ainfo->storage) {
1544 case RegTypeGeneral:
1545 ainfo->storage = RegTypeGSharedVtInReg;
1548 ainfo->storage = RegTypeGSharedVtOnStack;
1551 g_assert_not_reached ();
1556 case MONO_TYPE_TYPEDBYREF:
1557 case MONO_TYPE_VALUETYPE: {
1560 int nwords, nfields, esize;
1563 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1564 if (fpr + nfields < ARM_VFP_F16) {
1565 ainfo->storage = RegTypeHFA;
1567 ainfo->nregs = nfields;
1568 ainfo->esize = esize;
1579 if (t->type == MONO_TYPE_TYPEDBYREF) {
1580 size = sizeof (MonoTypedRef);
1581 align = sizeof (gpointer);
1583 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1585 size = mono_class_native_size (klass, &align);
1587 size = mini_type_stack_size_full (t, &align, FALSE);
1589 DEBUG(g_print ("load %d bytes struct\n", size));
1592 align_size += (sizeof (gpointer) - 1);
1593 align_size &= ~(sizeof (gpointer) - 1);
1594 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1595 ainfo->storage = RegTypeStructByVal;
1596 ainfo->struct_size = size;
1597 /* FIXME: align stack_size if needed */
1598 if (eabi_supported) {
1599 if (align >= 8 && (gr & 1))
1602 if (gr > ARMREG_R3) {
1604 ainfo->vtsize = nwords;
1606 int rest = ARMREG_R3 - gr + 1;
1607 int n_in_regs = rest >= nwords? nwords: rest;
1609 ainfo->size = n_in_regs;
1610 ainfo->vtsize = nwords - n_in_regs;
1613 nwords -= n_in_regs;
1615 if (sig->call_convention == MONO_CALL_VARARG)
1616 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1617 stack_size = ALIGN_TO (stack_size, align);
1618 ainfo->offset = stack_size;
1619 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1620 stack_size += nwords * sizeof (gpointer);
1626 add_general (&gr, &stack_size, ainfo, FALSE);
1632 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1634 add_general (&gr, &stack_size, ainfo, TRUE);
1640 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1642 add_general (&gr, &stack_size, ainfo, FALSE);
1645 case MONO_TYPE_MVAR:
1646 /* gsharedvt arguments are passed by ref */
1647 g_assert (mini_is_gsharedvt_type (t));
1648 add_general (&gr, &stack_size, ainfo, TRUE);
1649 switch (ainfo->storage) {
1650 case RegTypeGeneral:
1651 ainfo->storage = RegTypeGSharedVtInReg;
1654 ainfo->storage = RegTypeGSharedVtOnStack;
1657 g_assert_not_reached ();
1661 g_error ("Can't handle 0x%x", sig->params [i]->type);
1666 /* Handle the case where there are no implicit arguments */
1667 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1668 /* Prevent implicit arguments and sig_cookie from
1669 being passed in registers */
1672 /* Emit the signature cookie just before the implicit arguments */
1673 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1676 /* align stack size to 8 */
1677 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1678 stack_size = (stack_size + 7) & ~7;
1680 cinfo->stack_usage = stack_size;
1686 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1688 MonoType *callee_ret;
1692 c1 = get_call_info (NULL, caller_sig);
1693 c2 = get_call_info (NULL, callee_sig);
1696 * Tail calls with more callee stack usage than the caller cannot be supported, since
1697 * the extra stack space would be left on the stack after the tail call.
1699 res = c1->stack_usage >= c2->stack_usage;
1700 callee_ret = mini_get_underlying_type (callee_sig->ret);
1701 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1702 /* An address on the callee's stack is passed as the first argument */
1705 if (c2->stack_usage > 16 * 4)
1717 debug_omit_fp (void)
1720 return mono_debug_count ();
1727 * mono_arch_compute_omit_fp:
1729 * Determine whenever the frame pointer can be eliminated.
1732 mono_arch_compute_omit_fp (MonoCompile *cfg)
1734 MonoMethodSignature *sig;
1735 MonoMethodHeader *header;
1739 if (cfg->arch.omit_fp_computed)
1742 header = cfg->header;
1744 sig = mono_method_signature (cfg->method);
1746 if (!cfg->arch.cinfo)
1747 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1748 cinfo = cfg->arch.cinfo;
1751 * FIXME: Remove some of the restrictions.
1753 cfg->arch.omit_fp = TRUE;
1754 cfg->arch.omit_fp_computed = TRUE;
1756 if (cfg->disable_omit_fp)
1757 cfg->arch.omit_fp = FALSE;
1758 if (!debug_omit_fp ())
1759 cfg->arch.omit_fp = FALSE;
1761 if (cfg->method->save_lmf)
1762 cfg->arch.omit_fp = FALSE;
1764 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1765 cfg->arch.omit_fp = FALSE;
1766 if (header->num_clauses)
1767 cfg->arch.omit_fp = FALSE;
1768 if (cfg->param_area)
1769 cfg->arch.omit_fp = FALSE;
1770 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1771 cfg->arch.omit_fp = FALSE;
1772 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1773 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1774 cfg->arch.omit_fp = FALSE;
1775 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1776 ArgInfo *ainfo = &cinfo->args [i];
1778 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1780 * The stack offset can only be determined when the frame
1783 cfg->arch.omit_fp = FALSE;
1788 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1789 MonoInst *ins = cfg->varinfo [i];
1792 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1797 * Set var information according to the calling convention. arm version.
1798 * The locals var stuff should most likely be split in another method.
1801 mono_arch_allocate_vars (MonoCompile *cfg)
1803 MonoMethodSignature *sig;
1804 MonoMethodHeader *header;
1807 int i, offset, size, align, curinst;
1812 sig = mono_method_signature (cfg->method);
1814 if (!cfg->arch.cinfo)
1815 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1816 cinfo = cfg->arch.cinfo;
1817 sig_ret = mini_get_underlying_type (sig->ret);
1819 mono_arch_compute_omit_fp (cfg);
1821 if (cfg->arch.omit_fp)
1822 cfg->frame_reg = ARMREG_SP;
1824 cfg->frame_reg = ARMREG_FP;
1826 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1828 /* allow room for the vararg method args: void* and long/double */
1829 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1830 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1832 header = cfg->header;
1834 /* See mono_arch_get_global_int_regs () */
1835 if (cfg->flags & MONO_CFG_HAS_CALLS)
1836 cfg->uses_rgctx_reg = TRUE;
1838 if (cfg->frame_reg != ARMREG_SP)
1839 cfg->used_int_regs |= 1 << cfg->frame_reg;
1841 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1842 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1843 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1847 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1848 if (sig_ret->type != MONO_TYPE_VOID) {
1849 cfg->ret->opcode = OP_REGVAR;
1850 cfg->ret->inst_c0 = ARMREG_R0;
1853 /* local vars are at a positive offset from the stack pointer */
1855 * also note that if the function uses alloca, we use FP
1856 * to point at the local variables.
1858 offset = 0; /* linkage area */
1859 /* align the offset to 16 bytes: not sure this is needed here */
1861 //offset &= ~(8 - 1);
1863 /* add parameter area size for called functions */
1864 offset += cfg->param_area;
1867 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1870 /* allow room to save the return value */
1871 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1874 switch (cinfo->ret.storage) {
1875 case RegTypeStructByVal:
1876 cfg->ret->opcode = OP_REGOFFSET;
1877 cfg->ret->inst_basereg = cfg->frame_reg;
1878 offset += sizeof (gpointer) - 1;
1879 offset &= ~(sizeof (gpointer) - 1);
1880 cfg->ret->inst_offset = - offset;
1881 offset += sizeof(gpointer);
1884 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1885 offset = ALIGN_TO (offset, 8);
1886 cfg->ret->opcode = OP_REGOFFSET;
1887 cfg->ret->inst_basereg = cfg->frame_reg;
1888 cfg->ret->inst_offset = offset;
1892 case RegTypeStructByAddr:
1893 ins = cfg->vret_addr;
1894 offset += sizeof(gpointer) - 1;
1895 offset &= ~(sizeof(gpointer) - 1);
1896 ins->inst_offset = offset;
1897 ins->opcode = OP_REGOFFSET;
1898 ins->inst_basereg = cfg->frame_reg;
1899 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1900 g_print ("vret_addr =");
1901 mono_print_ins (cfg->vret_addr);
1903 offset += sizeof(gpointer);
1909 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1910 if (cfg->arch.seq_point_info_var) {
1913 ins = cfg->arch.seq_point_info_var;
1917 offset += align - 1;
1918 offset &= ~(align - 1);
1919 ins->opcode = OP_REGOFFSET;
1920 ins->inst_basereg = cfg->frame_reg;
1921 ins->inst_offset = offset;
1924 ins = cfg->arch.ss_trigger_page_var;
1927 offset += align - 1;
1928 offset &= ~(align - 1);
1929 ins->opcode = OP_REGOFFSET;
1930 ins->inst_basereg = cfg->frame_reg;
1931 ins->inst_offset = offset;
1935 if (cfg->arch.seq_point_ss_method_var) {
1938 ins = cfg->arch.seq_point_ss_method_var;
1941 offset += align - 1;
1942 offset &= ~(align - 1);
1943 ins->opcode = OP_REGOFFSET;
1944 ins->inst_basereg = cfg->frame_reg;
1945 ins->inst_offset = offset;
1948 ins = cfg->arch.seq_point_bp_method_var;
1951 offset += align - 1;
1952 offset &= ~(align - 1);
1953 ins->opcode = OP_REGOFFSET;
1954 ins->inst_basereg = cfg->frame_reg;
1955 ins->inst_offset = offset;
1959 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1960 /* Allocate a temporary used by the atomic ops */
1964 /* Allocate a local slot to hold the sig cookie address */
1965 offset += align - 1;
1966 offset &= ~(align - 1);
1967 cfg->arch.atomic_tmp_offset = offset;
1970 cfg->arch.atomic_tmp_offset = -1;
1973 cfg->locals_min_stack_offset = offset;
1975 curinst = cfg->locals_start;
1976 for (i = curinst; i < cfg->num_varinfo; ++i) {
1979 ins = cfg->varinfo [i];
1980 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1983 t = ins->inst_vtype;
1984 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1987 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1988 * pinvoke wrappers when they call functions returning structure */
1989 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1990 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1994 size = mono_type_size (t, &align);
1996 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1997 * since it loads/stores misaligned words, which don't do the right thing.
1999 if (align < 4 && size >= 4)
2001 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2002 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2003 offset += align - 1;
2004 offset &= ~(align - 1);
2005 ins->opcode = OP_REGOFFSET;
2006 ins->inst_offset = offset;
2007 ins->inst_basereg = cfg->frame_reg;
2009 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2012 cfg->locals_max_stack_offset = offset;
2016 ins = cfg->args [curinst];
2017 if (ins->opcode != OP_REGVAR) {
2018 ins->opcode = OP_REGOFFSET;
2019 ins->inst_basereg = cfg->frame_reg;
2020 offset += sizeof (gpointer) - 1;
2021 offset &= ~(sizeof (gpointer) - 1);
2022 ins->inst_offset = offset;
2023 offset += sizeof (gpointer);
2028 if (sig->call_convention == MONO_CALL_VARARG) {
2032 /* Allocate a local slot to hold the sig cookie address */
2033 offset += align - 1;
2034 offset &= ~(align - 1);
2035 cfg->sig_cookie = offset;
2039 for (i = 0; i < sig->param_count; ++i) {
2040 ainfo = cinfo->args + i;
2042 ins = cfg->args [curinst];
2044 switch (ainfo->storage) {
2046 offset = ALIGN_TO (offset, 8);
2047 ins->opcode = OP_REGOFFSET;
2048 ins->inst_basereg = cfg->frame_reg;
2049 /* These arguments are saved to the stack in the prolog */
2050 ins->inst_offset = offset;
2051 if (cfg->verbose_level >= 2)
2052 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2060 if (ins->opcode != OP_REGVAR) {
2061 ins->opcode = OP_REGOFFSET;
2062 ins->inst_basereg = cfg->frame_reg;
2063 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2065 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2066 * since it loads/stores misaligned words, which don't do the right thing.
2068 if (align < 4 && size >= 4)
2070 /* The code in the prolog () stores words when storing vtypes received in a register */
2071 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2073 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2074 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2075 offset += align - 1;
2076 offset &= ~(align - 1);
2077 ins->inst_offset = offset;
2083 /* align the offset to 8 bytes */
2084 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2085 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2090 cfg->stack_offset = offset;
2094 mono_arch_create_vars (MonoCompile *cfg)
2096 MonoMethodSignature *sig;
2100 sig = mono_method_signature (cfg->method);
2102 if (!cfg->arch.cinfo)
2103 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2104 cinfo = cfg->arch.cinfo;
2106 if (IS_HARD_FLOAT) {
2107 for (i = 0; i < 2; i++) {
2108 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2109 inst->flags |= MONO_INST_VOLATILE;
2111 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2115 if (cinfo->ret.storage == RegTypeStructByVal)
2116 cfg->ret_var_is_local = TRUE;
2118 if (cinfo->ret.storage == RegTypeStructByAddr) {
2119 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2120 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2121 g_print ("vret_addr = ");
2122 mono_print_ins (cfg->vret_addr);
2126 if (cfg->gen_sdb_seq_points) {
2127 if (cfg->soft_breakpoints) {
2130 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2131 ins->flags |= MONO_INST_VOLATILE;
2132 cfg->arch.seq_point_ss_method_var = ins;
2134 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2135 ins->flags |= MONO_INST_VOLATILE;
2136 cfg->arch.seq_point_bp_method_var = ins;
2138 g_assert (!cfg->compile_aot);
2139 } else if (cfg->compile_aot) {
2140 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2141 ins->flags |= MONO_INST_VOLATILE;
2142 cfg->arch.seq_point_info_var = ins;
2144 /* Allocate a separate variable for this to save 1 load per seq point */
2145 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2146 ins->flags |= MONO_INST_VOLATILE;
2147 cfg->arch.ss_trigger_page_var = ins;
2153 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2155 MonoMethodSignature *tmp_sig;
2158 if (call->tail_call)
2161 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2164 * mono_ArgIterator_Setup assumes the signature cookie is
2165 * passed first and all the arguments which were before it are
2166 * passed on the stack after the signature. So compensate by
2167 * passing a different signature.
2169 tmp_sig = mono_metadata_signature_dup (call->signature);
2170 tmp_sig->param_count -= call->signature->sentinelpos;
2171 tmp_sig->sentinelpos = 0;
2172 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2174 sig_reg = mono_alloc_ireg (cfg);
2175 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2177 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2182 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2187 LLVMCallInfo *linfo;
2189 n = sig->param_count + sig->hasthis;
2191 cinfo = get_call_info (cfg->mempool, sig);
2193 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2196 * LLVM always uses the native ABI while we use our own ABI, the
2197 * only difference is the handling of vtypes:
2198 * - we only pass/receive them in registers in some cases, and only
2199 * in 1 or 2 integer registers.
2201 switch (cinfo->ret.storage) {
2202 case RegTypeGeneral:
2205 case RegTypeIRegPair:
2207 case RegTypeStructByAddr:
2208 /* Vtype returned using a hidden argument */
2209 linfo->ret.storage = LLVMArgVtypeRetAddr;
2210 linfo->vret_arg_index = cinfo->vret_arg_index;
2213 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2214 cfg->disable_llvm = TRUE;
2218 for (i = 0; i < n; ++i) {
2219 ainfo = cinfo->args + i;
2221 linfo->args [i].storage = LLVMArgNone;
2223 switch (ainfo->storage) {
2224 case RegTypeGeneral:
2225 case RegTypeIRegPair:
2227 case RegTypeBaseGen:
2229 linfo->args [i].storage = LLVMArgNormal;
2231 case RegTypeStructByVal:
2232 linfo->args [i].storage = LLVMArgAsIArgs;
2233 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2236 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2237 cfg->disable_llvm = TRUE;
2247 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2250 MonoMethodSignature *sig;
2254 sig = call->signature;
2255 n = sig->param_count + sig->hasthis;
2257 cinfo = get_call_info (cfg->mempool, sig);
2259 switch (cinfo->ret.storage) {
2260 case RegTypeStructByVal:
2261 /* The JIT will transform this into a normal call */
2262 call->vret_in_reg = TRUE;
2266 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2267 * the location pointed to by it after call in emit_move_return_value ().
2269 if (!cfg->arch.vret_addr_loc) {
2270 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2271 /* Prevent it from being register allocated or optimized away */
2272 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2275 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2277 case RegTypeStructByAddr: {
2279 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2280 vtarg->sreg1 = call->vret_var->dreg;
2281 vtarg->dreg = mono_alloc_preg (cfg);
2282 MONO_ADD_INS (cfg->cbb, vtarg);
2284 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2291 for (i = 0; i < n; ++i) {
2292 ArgInfo *ainfo = cinfo->args + i;
2295 if (i >= sig->hasthis)
2296 t = sig->params [i - sig->hasthis];
2298 t = &mono_defaults.int_class->byval_arg;
2299 t = mini_get_underlying_type (t);
2301 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2302 /* Emit the signature cookie just before the implicit arguments */
2303 emit_sig_cookie (cfg, call, cinfo);
2306 in = call->args [i];
2308 switch (ainfo->storage) {
2309 case RegTypeGeneral:
2310 case RegTypeIRegPair:
2311 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2312 MONO_INST_NEW (cfg, ins, OP_MOVE);
2313 ins->dreg = mono_alloc_ireg (cfg);
2314 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2315 MONO_ADD_INS (cfg->cbb, ins);
2316 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2318 MONO_INST_NEW (cfg, ins, OP_MOVE);
2319 ins->dreg = mono_alloc_ireg (cfg);
2320 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2321 MONO_ADD_INS (cfg->cbb, ins);
2322 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2323 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2324 if (ainfo->size == 4) {
2325 if (IS_SOFT_FLOAT) {
2326 /* mono_emit_call_args () have already done the r8->r4 conversion */
2327 /* The converted value is in an int vreg */
2328 MONO_INST_NEW (cfg, ins, OP_MOVE);
2329 ins->dreg = mono_alloc_ireg (cfg);
2330 ins->sreg1 = in->dreg;
2331 MONO_ADD_INS (cfg->cbb, ins);
2332 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2336 cfg->param_area = MAX (cfg->param_area, 8);
2337 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2338 creg = mono_alloc_ireg (cfg);
2339 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2340 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2343 if (IS_SOFT_FLOAT) {
2344 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2345 ins->dreg = mono_alloc_ireg (cfg);
2346 ins->sreg1 = in->dreg;
2347 MONO_ADD_INS (cfg->cbb, ins);
2348 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2350 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2351 ins->dreg = mono_alloc_ireg (cfg);
2352 ins->sreg1 = in->dreg;
2353 MONO_ADD_INS (cfg->cbb, ins);
2354 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2358 cfg->param_area = MAX (cfg->param_area, 8);
2359 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2360 creg = mono_alloc_ireg (cfg);
2361 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2362 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2363 creg = mono_alloc_ireg (cfg);
2364 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2365 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2368 cfg->flags |= MONO_CFG_HAS_FPOUT;
2370 MONO_INST_NEW (cfg, ins, OP_MOVE);
2371 ins->dreg = mono_alloc_ireg (cfg);
2372 ins->sreg1 = in->dreg;
2373 MONO_ADD_INS (cfg->cbb, ins);
2375 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2378 case RegTypeStructByAddr:
2381 /* FIXME: where si the data allocated? */
2382 arg->backend.reg3 = ainfo->reg;
2383 call->used_iregs |= 1 << ainfo->reg;
2384 g_assert_not_reached ();
2387 case RegTypeStructByVal:
2388 case RegTypeGSharedVtInReg:
2389 case RegTypeGSharedVtOnStack:
2391 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2392 ins->opcode = OP_OUTARG_VT;
2393 ins->sreg1 = in->dreg;
2394 ins->klass = in->klass;
2395 ins->inst_p0 = call;
2396 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2397 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2398 mono_call_inst_add_outarg_vt (cfg, call, ins);
2399 MONO_ADD_INS (cfg->cbb, ins);
2402 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2403 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2404 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2405 if (t->type == MONO_TYPE_R8) {
2406 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2409 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2411 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2414 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2417 case RegTypeBaseGen:
2418 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2419 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2420 MONO_INST_NEW (cfg, ins, OP_MOVE);
2421 ins->dreg = mono_alloc_ireg (cfg);
2422 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2423 MONO_ADD_INS (cfg->cbb, ins);
2424 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2425 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2428 /* This should work for soft-float as well */
2430 cfg->param_area = MAX (cfg->param_area, 8);
2431 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2432 creg = mono_alloc_ireg (cfg);
2433 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2434 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2435 creg = mono_alloc_ireg (cfg);
2436 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2437 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2438 cfg->flags |= MONO_CFG_HAS_FPOUT;
2440 g_assert_not_reached ();
2444 int fdreg = mono_alloc_freg (cfg);
2446 if (ainfo->size == 8) {
2447 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2448 ins->sreg1 = in->dreg;
2450 MONO_ADD_INS (cfg->cbb, ins);
2452 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2457 * Mono's register allocator doesn't speak single-precision registers that
2458 * overlap double-precision registers (i.e. armhf). So we have to work around
2459 * the register allocator and load the value from memory manually.
2461 * So we create a variable for the float argument and an instruction to store
2462 * the argument into the variable. We then store the list of these arguments
2463 * in cfg->float_args. This list is then used by emit_float_args later to
2464 * pass the arguments in the various call opcodes.
2466 * This is not very nice, and we should really try to fix the allocator.
2469 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2471 /* Make sure the instruction isn't seen as pointless and removed.
2473 float_arg->flags |= MONO_INST_VOLATILE;
2475 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2477 /* We use the dreg to look up the instruction later. The hreg is used to
2478 * emit the instruction that loads the value into the FP reg.
2480 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2481 fad->vreg = float_arg->dreg;
2482 fad->hreg = ainfo->reg;
2484 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2487 call->used_iregs |= 1 << ainfo->reg;
2488 cfg->flags |= MONO_CFG_HAS_FPOUT;
2492 g_assert_not_reached ();
2496 /* Handle the case where there are no implicit arguments */
2497 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2498 emit_sig_cookie (cfg, call, cinfo);
2500 call->call_info = cinfo;
2501 call->stack_usage = cinfo->stack_usage;
2505 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2511 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2512 ins->dreg = mono_alloc_freg (cfg);
2513 ins->sreg1 = arg->dreg;
2514 MONO_ADD_INS (cfg->cbb, ins);
2515 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2518 g_assert_not_reached ();
2524 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2526 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2528 ArgInfo *ainfo = ins->inst_p1;
2529 int ovf_size = ainfo->vtsize;
2530 int doffset = ainfo->offset;
2531 int struct_size = ainfo->struct_size;
2532 int i, soffset, dreg, tmpreg;
2534 switch (ainfo->storage) {
2535 case RegTypeGSharedVtInReg:
2537 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2539 case RegTypeGSharedVtOnStack:
2540 /* Pass by addr on stack */
2541 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2544 for (i = 0; i < ainfo->nregs; ++i) {
2545 if (ainfo->esize == 4)
2546 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2548 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2549 load->dreg = mono_alloc_freg (cfg);
2550 load->inst_basereg = src->dreg;
2551 load->inst_offset = i * ainfo->esize;
2552 MONO_ADD_INS (cfg->cbb, load);
2554 if (ainfo->esize == 4) {
2557 /* See RegTypeFP in mono_arch_emit_call () */
2558 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2559 float_arg->flags |= MONO_INST_VOLATILE;
2560 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2562 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2563 fad->vreg = float_arg->dreg;
2564 fad->hreg = ainfo->reg + i;
2566 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2568 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2574 for (i = 0; i < ainfo->size; ++i) {
2575 dreg = mono_alloc_ireg (cfg);
2576 switch (struct_size) {
2578 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2581 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2584 tmpreg = mono_alloc_ireg (cfg);
2585 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2586 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2587 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2588 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2589 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2590 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2591 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2594 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2597 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2598 soffset += sizeof (gpointer);
2599 struct_size -= sizeof (gpointer);
2601 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2603 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2609 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2611 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2614 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2617 if (COMPILE_LLVM (cfg)) {
2618 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2620 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2621 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2622 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2623 MONO_ADD_INS (cfg->cbb, ins);
2628 case MONO_ARM_FPU_NONE:
2629 if (ret->type == MONO_TYPE_R8) {
2632 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2633 ins->dreg = cfg->ret->dreg;
2634 ins->sreg1 = val->dreg;
2635 MONO_ADD_INS (cfg->cbb, ins);
2638 if (ret->type == MONO_TYPE_R4) {
2639 /* Already converted to an int in method_to_ir () */
2640 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2644 case MONO_ARM_FPU_VFP:
2645 case MONO_ARM_FPU_VFP_HARD:
2646 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2649 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2650 ins->dreg = cfg->ret->dreg;
2651 ins->sreg1 = val->dreg;
2652 MONO_ADD_INS (cfg->cbb, ins);
2657 g_assert_not_reached ();
2661 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2664 #endif /* #ifndef DISABLE_JIT */
2667 mono_arch_is_inst_imm (gint64 imm)
2673 MonoMethodSignature *sig;
2676 MonoType **param_types;
2680 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2684 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2687 switch (cinfo->ret.storage) {
2689 case RegTypeGeneral:
2690 case RegTypeIRegPair:
2691 case RegTypeStructByAddr:
2702 for (i = 0; i < cinfo->nargs; ++i) {
2703 ArgInfo *ainfo = &cinfo->args [i];
2706 switch (ainfo->storage) {
2707 case RegTypeGeneral:
2708 case RegTypeIRegPair:
2709 case RegTypeBaseGen:
2712 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2715 case RegTypeStructByVal:
2716 if (ainfo->size == 0)
2717 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2719 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2720 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2728 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2729 for (i = 0; i < sig->param_count; ++i) {
2730 MonoType *t = sig->params [i];
2735 t = mini_get_underlying_type (t);
2758 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2760 ArchDynCallInfo *info;
2764 cinfo = get_call_info (NULL, sig);
2766 if (!dyn_call_supported (cinfo, sig)) {
2771 info = g_new0 (ArchDynCallInfo, 1);
2772 // FIXME: Preprocess the info to speed up start_dyn_call ()
2774 info->cinfo = cinfo;
2775 info->rtype = mini_get_underlying_type (sig->ret);
2776 info->param_types = g_new0 (MonoType*, sig->param_count);
2777 for (i = 0; i < sig->param_count; ++i)
2778 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2780 return (MonoDynCallInfo*)info;
2784 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2786 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2788 g_free (ainfo->cinfo);
2793 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2795 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2796 DynCallArgs *p = (DynCallArgs*)buf;
2797 int arg_index, greg, i, j, pindex;
2798 MonoMethodSignature *sig = dinfo->sig;
2800 g_assert (buf_len >= sizeof (DynCallArgs));
2809 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2810 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2815 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2816 p->regs [greg ++] = (mgreg_t)ret;
2818 for (i = pindex; i < sig->param_count; i++) {
2819 MonoType *t = dinfo->param_types [i];
2820 gpointer *arg = args [arg_index ++];
2821 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2824 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2826 } else if (ainfo->storage == RegTypeBase) {
2827 slot = PARAM_REGS + (ainfo->offset / 4);
2828 } else if (ainfo->storage == RegTypeBaseGen) {
2829 /* slot + 1 is the first stack slot, so the code below will work */
2832 g_assert_not_reached ();
2836 p->regs [slot] = (mgreg_t)*arg;
2841 case MONO_TYPE_STRING:
2842 case MONO_TYPE_CLASS:
2843 case MONO_TYPE_ARRAY:
2844 case MONO_TYPE_SZARRAY:
2845 case MONO_TYPE_OBJECT:
2849 p->regs [slot] = (mgreg_t)*arg;
2852 p->regs [slot] = *(guint8*)arg;
2855 p->regs [slot] = *(gint8*)arg;
2858 p->regs [slot] = *(gint16*)arg;
2861 p->regs [slot] = *(guint16*)arg;
2864 p->regs [slot] = *(gint32*)arg;
2867 p->regs [slot] = *(guint32*)arg;
2871 p->regs [slot ++] = (mgreg_t)arg [0];
2872 p->regs [slot] = (mgreg_t)arg [1];
2875 p->regs [slot] = *(mgreg_t*)arg;
2878 p->regs [slot ++] = (mgreg_t)arg [0];
2879 p->regs [slot] = (mgreg_t)arg [1];
2881 case MONO_TYPE_GENERICINST:
2882 if (MONO_TYPE_IS_REFERENCE (t)) {
2883 p->regs [slot] = (mgreg_t)*arg;
2886 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2887 MonoClass *klass = mono_class_from_mono_type (t);
2888 guint8 *nullable_buf;
2891 size = mono_class_value_size (klass, NULL);
2892 nullable_buf = g_alloca (size);
2893 g_assert (nullable_buf);
2895 /* The argument pointed to by arg is either a boxed vtype or null */
2896 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2898 arg = (gpointer*)nullable_buf;
2904 case MONO_TYPE_VALUETYPE:
2905 g_assert (ainfo->storage == RegTypeStructByVal);
2907 if (ainfo->size == 0)
2908 slot = PARAM_REGS + (ainfo->offset / 4);
2912 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2913 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2916 g_assert_not_reached ();
2922 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2924 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2925 MonoType *ptype = ainfo->rtype;
2926 guint8 *ret = ((DynCallArgs*)buf)->ret;
2927 mgreg_t res = ((DynCallArgs*)buf)->res;
2928 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2930 switch (ptype->type) {
2931 case MONO_TYPE_VOID:
2932 *(gpointer*)ret = NULL;
2934 case MONO_TYPE_STRING:
2935 case MONO_TYPE_CLASS:
2936 case MONO_TYPE_ARRAY:
2937 case MONO_TYPE_SZARRAY:
2938 case MONO_TYPE_OBJECT:
2942 *(gpointer*)ret = (gpointer)res;
2948 *(guint8*)ret = res;
2951 *(gint16*)ret = res;
2954 *(guint16*)ret = res;
2957 *(gint32*)ret = res;
2960 *(guint32*)ret = res;
2964 /* This handles endianness as well */
2965 ((gint32*)ret) [0] = res;
2966 ((gint32*)ret) [1] = res2;
2968 case MONO_TYPE_GENERICINST:
2969 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2970 *(gpointer*)ret = (gpointer)res;
2975 case MONO_TYPE_VALUETYPE:
2976 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2981 *(float*)ret = *(float*)&res;
2983 case MONO_TYPE_R8: {
2990 *(double*)ret = *(double*)®s;
2994 g_assert_not_reached ();
3001 * Allow tracing to work with this interface (with an optional argument)
3005 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3009 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3010 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3011 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3012 code = emit_call_reg (code, ARMREG_R2);
3026 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3029 int save_mode = SAVE_NONE;
3031 MonoMethod *method = cfg->method;
3032 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3033 int rtype = ret_type->type;
3034 int save_offset = cfg->param_area;
3038 offset = code - cfg->native_code;
3039 /* we need about 16 instructions */
3040 if (offset > (cfg->code_size - 16 * 4)) {
3041 cfg->code_size *= 2;
3042 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3043 code = cfg->native_code + offset;
3046 case MONO_TYPE_VOID:
3047 /* special case string .ctor icall */
3048 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3049 save_mode = SAVE_ONE;
3051 save_mode = SAVE_NONE;
3055 save_mode = SAVE_TWO;
3059 save_mode = SAVE_ONE_FP;
3061 save_mode = SAVE_ONE;
3065 save_mode = SAVE_TWO_FP;
3067 save_mode = SAVE_TWO;
3069 case MONO_TYPE_GENERICINST:
3070 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3071 save_mode = SAVE_ONE;
3075 case MONO_TYPE_VALUETYPE:
3076 save_mode = SAVE_STRUCT;
3079 save_mode = SAVE_ONE;
3083 switch (save_mode) {
3085 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3086 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3087 if (enable_arguments) {
3088 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3089 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3093 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3094 if (enable_arguments) {
3095 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3099 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3100 if (enable_arguments) {
3101 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3105 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3106 if (enable_arguments) {
3107 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3111 if (enable_arguments) {
3112 /* FIXME: get the actual address */
3113 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3121 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3122 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3123 code = emit_call_reg (code, ARMREG_IP);
3125 switch (save_mode) {
3127 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3128 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3131 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3134 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3137 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3148 * The immediate field for cond branches is big enough for all reasonable methods
3150 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3151 if (0 && ins->inst_true_bb->native_offset) { \
3152 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3154 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3155 ARM_B_COND (code, (condcode), 0); \
3158 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3160 /* emit an exception if condition is fail
3162 * We assign the extra code used to throw the implicit exceptions
3163 * to cfg->bb_exit as far as the big branch handling is concerned
3165 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3167 mono_add_patch_info (cfg, code - cfg->native_code, \
3168 MONO_PATCH_INFO_EXC, exc_name); \
3169 ARM_BL_COND (code, (condcode), 0); \
3172 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3175 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3180 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3184 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3185 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3187 switch (ins->opcode) {
3190 /* Already done by an arch-independent pass */
3192 case OP_LOAD_MEMBASE:
3193 case OP_LOADI4_MEMBASE:
3195 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3196 * OP_LOAD_MEMBASE offset(basereg), reg
3198 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3199 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3200 ins->inst_basereg == last_ins->inst_destbasereg &&
3201 ins->inst_offset == last_ins->inst_offset) {
3202 if (ins->dreg == last_ins->sreg1) {
3203 MONO_DELETE_INS (bb, ins);
3206 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3207 ins->opcode = OP_MOVE;
3208 ins->sreg1 = last_ins->sreg1;
3212 * Note: reg1 must be different from the basereg in the second load
3213 * OP_LOAD_MEMBASE offset(basereg), reg1
3214 * OP_LOAD_MEMBASE offset(basereg), reg2
3216 * OP_LOAD_MEMBASE offset(basereg), reg1
3217 * OP_MOVE reg1, reg2
3219 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3220 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3221 ins->inst_basereg != last_ins->dreg &&
3222 ins->inst_basereg == last_ins->inst_basereg &&
3223 ins->inst_offset == last_ins->inst_offset) {
3225 if (ins->dreg == last_ins->dreg) {
3226 MONO_DELETE_INS (bb, ins);
3229 ins->opcode = OP_MOVE;
3230 ins->sreg1 = last_ins->dreg;
3233 //g_assert_not_reached ();
3237 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3238 * OP_LOAD_MEMBASE offset(basereg), reg
3240 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3241 * OP_ICONST reg, imm
3243 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3244 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3245 ins->inst_basereg == last_ins->inst_destbasereg &&
3246 ins->inst_offset == last_ins->inst_offset) {
3247 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3248 ins->opcode = OP_ICONST;
3249 ins->inst_c0 = last_ins->inst_imm;
3250 g_assert_not_reached (); // check this rule
3254 case OP_LOADU1_MEMBASE:
3255 case OP_LOADI1_MEMBASE:
3256 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3257 ins->inst_basereg == last_ins->inst_destbasereg &&
3258 ins->inst_offset == last_ins->inst_offset) {
3259 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3260 ins->sreg1 = last_ins->sreg1;
3263 case OP_LOADU2_MEMBASE:
3264 case OP_LOADI2_MEMBASE:
3265 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3266 ins->inst_basereg == last_ins->inst_destbasereg &&
3267 ins->inst_offset == last_ins->inst_offset) {
3268 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3269 ins->sreg1 = last_ins->sreg1;
3273 ins->opcode = OP_MOVE;
3277 if (ins->dreg == ins->sreg1) {
3278 MONO_DELETE_INS (bb, ins);
3282 * OP_MOVE sreg, dreg
3283 * OP_MOVE dreg, sreg
3285 if (last_ins && last_ins->opcode == OP_MOVE &&
3286 ins->sreg1 == last_ins->dreg &&
3287 ins->dreg == last_ins->sreg1) {
3288 MONO_DELETE_INS (bb, ins);
3297 * the branch_cc_table should maintain the order of these
3311 branch_cc_table [] = {
3325 #define ADD_NEW_INS(cfg,dest,op) do { \
3326 MONO_INST_NEW ((cfg), (dest), (op)); \
3327 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3331 map_to_reg_reg_op (int op)
3340 case OP_COMPARE_IMM:
3342 case OP_ICOMPARE_IMM:
3356 case OP_LOAD_MEMBASE:
3357 return OP_LOAD_MEMINDEX;
3358 case OP_LOADI4_MEMBASE:
3359 return OP_LOADI4_MEMINDEX;
3360 case OP_LOADU4_MEMBASE:
3361 return OP_LOADU4_MEMINDEX;
3362 case OP_LOADU1_MEMBASE:
3363 return OP_LOADU1_MEMINDEX;
3364 case OP_LOADI2_MEMBASE:
3365 return OP_LOADI2_MEMINDEX;
3366 case OP_LOADU2_MEMBASE:
3367 return OP_LOADU2_MEMINDEX;
3368 case OP_LOADI1_MEMBASE:
3369 return OP_LOADI1_MEMINDEX;
3370 case OP_STOREI1_MEMBASE_REG:
3371 return OP_STOREI1_MEMINDEX;
3372 case OP_STOREI2_MEMBASE_REG:
3373 return OP_STOREI2_MEMINDEX;
3374 case OP_STOREI4_MEMBASE_REG:
3375 return OP_STOREI4_MEMINDEX;
3376 case OP_STORE_MEMBASE_REG:
3377 return OP_STORE_MEMINDEX;
3378 case OP_STORER4_MEMBASE_REG:
3379 return OP_STORER4_MEMINDEX;
3380 case OP_STORER8_MEMBASE_REG:
3381 return OP_STORER8_MEMINDEX;
3382 case OP_STORE_MEMBASE_IMM:
3383 return OP_STORE_MEMBASE_REG;
3384 case OP_STOREI1_MEMBASE_IMM:
3385 return OP_STOREI1_MEMBASE_REG;
3386 case OP_STOREI2_MEMBASE_IMM:
3387 return OP_STOREI2_MEMBASE_REG;
3388 case OP_STOREI4_MEMBASE_IMM:
3389 return OP_STOREI4_MEMBASE_REG;
3391 g_assert_not_reached ();
3395 * Remove from the instruction list the instructions that can't be
3396 * represented with very simple instructions with no register
3400 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3402 MonoInst *ins, *temp, *last_ins = NULL;
3403 int rot_amount, imm8, low_imm;
3405 MONO_BB_FOR_EACH_INS (bb, ins) {
3407 switch (ins->opcode) {
3411 case OP_COMPARE_IMM:
3412 case OP_ICOMPARE_IMM:
3426 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3427 int opcode2 = mono_op_imm_to_op (ins->opcode);
3428 ADD_NEW_INS (cfg, temp, OP_ICONST);
3429 temp->inst_c0 = ins->inst_imm;
3430 temp->dreg = mono_alloc_ireg (cfg);
3431 ins->sreg2 = temp->dreg;
3433 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3434 ins->opcode = opcode2;
3436 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3442 if (ins->inst_imm == 1) {
3443 ins->opcode = OP_MOVE;
3446 if (ins->inst_imm == 0) {
3447 ins->opcode = OP_ICONST;
3451 imm8 = mono_is_power_of_two (ins->inst_imm);
3453 ins->opcode = OP_SHL_IMM;
3454 ins->inst_imm = imm8;
3457 ADD_NEW_INS (cfg, temp, OP_ICONST);
3458 temp->inst_c0 = ins->inst_imm;
3459 temp->dreg = mono_alloc_ireg (cfg);
3460 ins->sreg2 = temp->dreg;
3461 ins->opcode = OP_IMUL;
3467 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3468 /* ARM sets the C flag to 1 if there was _no_ overflow */
3469 ins->next->opcode = OP_COND_EXC_NC;
3472 case OP_IDIV_UN_IMM:
3474 case OP_IREM_UN_IMM: {
3475 int opcode2 = mono_op_imm_to_op (ins->opcode);
3476 ADD_NEW_INS (cfg, temp, OP_ICONST);
3477 temp->inst_c0 = ins->inst_imm;
3478 temp->dreg = mono_alloc_ireg (cfg);
3479 ins->sreg2 = temp->dreg;
3481 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3482 ins->opcode = opcode2;
3485 case OP_LOCALLOC_IMM:
3486 ADD_NEW_INS (cfg, temp, OP_ICONST);
3487 temp->inst_c0 = ins->inst_imm;
3488 temp->dreg = mono_alloc_ireg (cfg);
3489 ins->sreg1 = temp->dreg;
3490 ins->opcode = OP_LOCALLOC;
3492 case OP_LOAD_MEMBASE:
3493 case OP_LOADI4_MEMBASE:
3494 case OP_LOADU4_MEMBASE:
3495 case OP_LOADU1_MEMBASE:
3496 /* we can do two things: load the immed in a register
3497 * and use an indexed load, or see if the immed can be
3498 * represented as an ad_imm + a load with a smaller offset
3499 * that fits. We just do the first for now, optimize later.
3501 if (arm_is_imm12 (ins->inst_offset))
3503 ADD_NEW_INS (cfg, temp, OP_ICONST);
3504 temp->inst_c0 = ins->inst_offset;
3505 temp->dreg = mono_alloc_ireg (cfg);
3506 ins->sreg2 = temp->dreg;
3507 ins->opcode = map_to_reg_reg_op (ins->opcode);
3509 case OP_LOADI2_MEMBASE:
3510 case OP_LOADU2_MEMBASE:
3511 case OP_LOADI1_MEMBASE:
3512 if (arm_is_imm8 (ins->inst_offset))
3514 ADD_NEW_INS (cfg, temp, OP_ICONST);
3515 temp->inst_c0 = ins->inst_offset;
3516 temp->dreg = mono_alloc_ireg (cfg);
3517 ins->sreg2 = temp->dreg;
3518 ins->opcode = map_to_reg_reg_op (ins->opcode);
3520 case OP_LOADR4_MEMBASE:
3521 case OP_LOADR8_MEMBASE:
3522 if (arm_is_fpimm8 (ins->inst_offset))
3524 low_imm = ins->inst_offset & 0x1ff;
3525 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3526 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3527 temp->inst_imm = ins->inst_offset & ~0x1ff;
3528 temp->sreg1 = ins->inst_basereg;
3529 temp->dreg = mono_alloc_ireg (cfg);
3530 ins->inst_basereg = temp->dreg;
3531 ins->inst_offset = low_imm;
3535 ADD_NEW_INS (cfg, temp, OP_ICONST);
3536 temp->inst_c0 = ins->inst_offset;
3537 temp->dreg = mono_alloc_ireg (cfg);
3539 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3540 add_ins->sreg1 = ins->inst_basereg;
3541 add_ins->sreg2 = temp->dreg;
3542 add_ins->dreg = mono_alloc_ireg (cfg);
3544 ins->inst_basereg = add_ins->dreg;
3545 ins->inst_offset = 0;
3548 case OP_STORE_MEMBASE_REG:
3549 case OP_STOREI4_MEMBASE_REG:
3550 case OP_STOREI1_MEMBASE_REG:
3551 if (arm_is_imm12 (ins->inst_offset))
3553 ADD_NEW_INS (cfg, temp, OP_ICONST);
3554 temp->inst_c0 = ins->inst_offset;
3555 temp->dreg = mono_alloc_ireg (cfg);
3556 ins->sreg2 = temp->dreg;
3557 ins->opcode = map_to_reg_reg_op (ins->opcode);
3559 case OP_STOREI2_MEMBASE_REG:
3560 if (arm_is_imm8 (ins->inst_offset))
3562 ADD_NEW_INS (cfg, temp, OP_ICONST);
3563 temp->inst_c0 = ins->inst_offset;
3564 temp->dreg = mono_alloc_ireg (cfg);
3565 ins->sreg2 = temp->dreg;
3566 ins->opcode = map_to_reg_reg_op (ins->opcode);
3568 case OP_STORER4_MEMBASE_REG:
3569 case OP_STORER8_MEMBASE_REG:
3570 if (arm_is_fpimm8 (ins->inst_offset))
3572 low_imm = ins->inst_offset & 0x1ff;
3573 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3574 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3575 temp->inst_imm = ins->inst_offset & ~0x1ff;
3576 temp->sreg1 = ins->inst_destbasereg;
3577 temp->dreg = mono_alloc_ireg (cfg);
3578 ins->inst_destbasereg = temp->dreg;
3579 ins->inst_offset = low_imm;
3583 ADD_NEW_INS (cfg, temp, OP_ICONST);
3584 temp->inst_c0 = ins->inst_offset;
3585 temp->dreg = mono_alloc_ireg (cfg);
3587 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3588 add_ins->sreg1 = ins->inst_destbasereg;
3589 add_ins->sreg2 = temp->dreg;
3590 add_ins->dreg = mono_alloc_ireg (cfg);
3592 ins->inst_destbasereg = add_ins->dreg;
3593 ins->inst_offset = 0;
3596 case OP_STORE_MEMBASE_IMM:
3597 case OP_STOREI1_MEMBASE_IMM:
3598 case OP_STOREI2_MEMBASE_IMM:
3599 case OP_STOREI4_MEMBASE_IMM:
3600 ADD_NEW_INS (cfg, temp, OP_ICONST);
3601 temp->inst_c0 = ins->inst_imm;
3602 temp->dreg = mono_alloc_ireg (cfg);
3603 ins->sreg1 = temp->dreg;
3604 ins->opcode = map_to_reg_reg_op (ins->opcode);
3606 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3609 gboolean swap = FALSE;
3613 /* Optimized away */
3618 /* Some fp compares require swapped operands */
3619 switch (ins->next->opcode) {
3621 ins->next->opcode = OP_FBLT;
3625 ins->next->opcode = OP_FBLT_UN;
3629 ins->next->opcode = OP_FBGE;
3633 ins->next->opcode = OP_FBGE_UN;
3641 ins->sreg1 = ins->sreg2;
3650 bb->last_ins = last_ins;
3651 bb->max_vreg = cfg->next_vreg;
3655 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3659 if (long_ins->opcode == OP_LNEG) {
3661 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3662 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3668 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3670 /* sreg is a float, dreg is an integer reg */
3672 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3674 ARM_TOSIZD (code, vfp_scratch1, sreg);
3676 ARM_TOUIZD (code, vfp_scratch1, sreg);
3677 ARM_FMRS (code, dreg, vfp_scratch1);
3678 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3682 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3683 else if (size == 2) {
3684 ARM_SHL_IMM (code, dreg, dreg, 16);
3685 ARM_SHR_IMM (code, dreg, dreg, 16);
3689 ARM_SHL_IMM (code, dreg, dreg, 24);
3690 ARM_SAR_IMM (code, dreg, dreg, 24);
3691 } else if (size == 2) {
3692 ARM_SHL_IMM (code, dreg, dreg, 16);
3693 ARM_SAR_IMM (code, dreg, dreg, 16);
3700 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3702 /* sreg is a float, dreg is an integer reg */
3704 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3706 ARM_TOSIZS (code, vfp_scratch1, sreg);
3708 ARM_TOUIZS (code, vfp_scratch1, sreg);
3709 ARM_FMRS (code, dreg, vfp_scratch1);
3710 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3714 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3715 else if (size == 2) {
3716 ARM_SHL_IMM (code, dreg, dreg, 16);
3717 ARM_SHR_IMM (code, dreg, dreg, 16);
3721 ARM_SHL_IMM (code, dreg, dreg, 24);
3722 ARM_SAR_IMM (code, dreg, dreg, 24);
3723 } else if (size == 2) {
3724 ARM_SHL_IMM (code, dreg, dreg, 16);
3725 ARM_SAR_IMM (code, dreg, dreg, 16);
3731 #endif /* #ifndef DISABLE_JIT */
3733 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3736 emit_thunk (guint8 *code, gconstpointer target)
3740 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3741 if (thumb_supported)
3742 ARM_BX (code, ARMREG_IP);
3744 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3745 *(guint32*)code = (guint32)target;
3747 mono_arch_flush_icache (p, code - p);
3751 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3753 MonoJitInfo *ji = NULL;
3754 MonoThunkJitInfo *info;
3757 guint8 *orig_target;
3758 guint8 *target_thunk;
3761 domain = mono_domain_get ();
3765 * This can be called multiple times during JITting,
3766 * save the current position in cfg->arch to avoid
3767 * doing a O(n^2) search.
3769 if (!cfg->arch.thunks) {
3770 cfg->arch.thunks = cfg->thunks;
3771 cfg->arch.thunks_size = cfg->thunk_area;
3773 thunks = cfg->arch.thunks;
3774 thunks_size = cfg->arch.thunks_size;
3776 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3777 g_assert_not_reached ();
3780 g_assert (*(guint32*)thunks == 0);
3781 emit_thunk (thunks, target);
3782 arm_patch (code, thunks);
3784 cfg->arch.thunks += THUNK_SIZE;
3785 cfg->arch.thunks_size -= THUNK_SIZE;
3787 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3789 info = mono_jit_info_get_thunk_info (ji);
3792 thunks = (guint8*)ji->code_start + info->thunks_offset;
3793 thunks_size = info->thunks_size;
3795 orig_target = mono_arch_get_call_target (code + 4);
3797 mono_mini_arch_lock ();
3799 target_thunk = NULL;
3800 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3801 /* The call already points to a thunk, because of trampolines etc. */
3802 target_thunk = orig_target;
3804 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3805 if (((guint32*)p) [0] == 0) {
3809 } else if (((guint32*)p) [2] == (guint32)target) {
3810 /* Thunk already points to target */
3817 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3819 if (!target_thunk) {
3820 mono_mini_arch_unlock ();
3821 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3822 g_assert_not_reached ();
3825 emit_thunk (target_thunk, target);
3826 arm_patch (code, target_thunk);
3827 mono_arch_flush_icache (code, 4);
3829 mono_mini_arch_unlock ();
3834 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3836 guint32 *code32 = (void*)code;
3837 guint32 ins = *code32;
3838 guint32 prim = (ins >> 25) & 7;
3839 guint32 tval = GPOINTER_TO_UINT (target);
3841 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3842 if (prim == 5) { /* 101b */
3843 /* the diff starts 8 bytes from the branch opcode */
3844 gint diff = target - code - 8;
3846 gint tmask = 0xffffffff;
3847 if (tval & 1) { /* entering thumb mode */
3848 diff = target - 1 - code - 8;
3849 g_assert (thumb_supported);
3850 tbits = 0xf << 28; /* bl->blx bit pattern */
3851 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3852 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3856 tmask = ~(1 << 24); /* clear the link bit */
3857 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3862 if (diff <= 33554431) {
3864 ins = (ins & 0xff000000) | diff;
3866 *code32 = ins | tbits;
3870 /* diff between 0 and -33554432 */
3871 if (diff >= -33554432) {
3873 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3875 *code32 = ins | tbits;
3880 handle_thunk (cfg, domain, code, target);
3884 #ifdef USE_JUMP_TABLES
3886 gpointer *jte = mono_jumptable_get_entry (code);
3888 jte [0] = (gpointer) target;
3892 * The alternative call sequences looks like this:
3894 * ldr ip, [pc] // loads the address constant
3895 * b 1f // jumps around the constant
3896 * address constant embedded in the code
3901 * There are two cases for patching:
3902 * a) at the end of method emission: in this case code points to the start
3903 * of the call sequence
3904 * b) during runtime patching of the call site: in this case code points
3905 * to the mov pc, ip instruction
3907 * We have to handle also the thunk jump code sequence:
3911 * address constant // execution never reaches here
3913 if ((ins & 0x0ffffff0) == 0x12fff10) {
3914 /* Branch and exchange: the address is constructed in a reg
3915 * We can patch BX when the code sequence is the following:
3916 * ldr ip, [pc, #0] ; 0x8
3923 guint8 *emit = (guint8*)ccode;
3924 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3926 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3927 ARM_BX (emit, ARMREG_IP);
3929 /*patching from magic trampoline*/
3930 if (ins == ccode [3]) {
3931 g_assert (code32 [-4] == ccode [0]);
3932 g_assert (code32 [-3] == ccode [1]);
3933 g_assert (code32 [-1] == ccode [2]);
3934 code32 [-2] = (guint32)target;
3937 /*patching from JIT*/
3938 if (ins == ccode [0]) {
3939 g_assert (code32 [1] == ccode [1]);
3940 g_assert (code32 [3] == ccode [2]);
3941 g_assert (code32 [4] == ccode [3]);
3942 code32 [2] = (guint32)target;
3945 g_assert_not_reached ();
3946 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3954 guint8 *emit = (guint8*)ccode;
3955 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3957 ARM_BLX_REG (emit, ARMREG_IP);
3959 g_assert (code32 [-3] == ccode [0]);
3960 g_assert (code32 [-2] == ccode [1]);
3961 g_assert (code32 [0] == ccode [2]);
3963 code32 [-1] = (guint32)target;
3966 guint32 *tmp = ccode;
3967 guint8 *emit = (guint8*)tmp;
3968 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3969 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3970 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3971 ARM_BX (emit, ARMREG_IP);
3972 if (ins == ccode [2]) {
3973 g_assert_not_reached (); // should be -2 ...
3974 code32 [-1] = (guint32)target;
3977 if (ins == ccode [0]) {
3978 /* handles both thunk jump code and the far call sequence */
3979 code32 [2] = (guint32)target;
3982 g_assert_not_reached ();
3984 // g_print ("patched with 0x%08x\n", ins);
3989 arm_patch (guchar *code, const guchar *target)
3991 arm_patch_general (NULL, NULL, code, target);
3995 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3996 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3997 * to be used with the emit macros.
3998 * Return -1 otherwise.
4001 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4004 for (i = 0; i < 31; i+= 2) {
4005 res = (val << (32 - i)) | (val >> i);
4008 *rot_amount = i? 32 - i: 0;
4015 * Emits in code a sequence of instructions that load the value 'val'
4016 * into the dreg register. Uses at most 4 instructions.
4019 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4021 int imm8, rot_amount;
4023 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4024 /* skip the constant pool */
4030 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4031 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4032 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4036 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4037 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4038 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4039 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4042 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4044 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4048 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4050 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4052 if (val & 0xFF0000) {
4053 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4055 if (val & 0xFF000000) {
4056 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4058 } else if (val & 0xFF00) {
4059 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4060 if (val & 0xFF0000) {
4061 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4063 if (val & 0xFF000000) {
4064 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4066 } else if (val & 0xFF0000) {
4067 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4068 if (val & 0xFF000000) {
4069 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4072 //g_assert_not_reached ();
4078 mono_arm_thumb_supported (void)
4080 return thumb_supported;
4086 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4091 call = (MonoCallInst*)ins;
4092 cinfo = call->call_info;
4094 switch (cinfo->ret.storage) {
4096 MonoInst *loc = cfg->arch.vret_addr_loc;
4099 /* Load the destination address */
4100 g_assert (loc && loc->opcode == OP_REGOFFSET);
4102 if (arm_is_imm12 (loc->inst_offset)) {
4103 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4105 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4106 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4108 for (i = 0; i < cinfo->ret.nregs; ++i) {
4109 if (cinfo->ret.esize == 4)
4110 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4112 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4120 switch (ins->opcode) {
4123 case OP_FCALL_MEMBASE:
4125 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4126 if (sig_ret->type == MONO_TYPE_R4) {
4127 if (IS_HARD_FLOAT) {
4128 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4130 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4131 ARM_CVTS (code, ins->dreg, ins->dreg);
4134 if (IS_HARD_FLOAT) {
4135 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4137 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4144 case OP_RCALL_MEMBASE: {
4149 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4150 g_assert (sig_ret->type == MONO_TYPE_R4);
4151 if (IS_HARD_FLOAT) {
4152 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4154 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4155 ARM_CPYS (code, ins->dreg, ins->dreg);
4167 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4172 guint8 *code = cfg->native_code + cfg->code_len;
4173 MonoInst *last_ins = NULL;
4174 guint last_offset = 0;
4176 int imm8, rot_amount;
4178 /* we don't align basic blocks of loops on arm */
4180 if (cfg->verbose_level > 2)
4181 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4183 cpos = bb->max_offset;
4185 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4186 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4187 //g_assert (!mono_compile_aot);
4190 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4191 /* this is not thread save, but good enough */
4192 /* fixme: howto handle overflows? */
4193 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4196 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4197 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4198 (gpointer)"mono_break");
4199 code = emit_call_seq (cfg, code);
4202 MONO_BB_FOR_EACH_INS (bb, ins) {
4203 offset = code - cfg->native_code;
4205 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4207 if (offset > (cfg->code_size - max_len - 16)) {
4208 cfg->code_size *= 2;
4209 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4210 code = cfg->native_code + offset;
4212 // if (ins->cil_code)
4213 // g_print ("cil code\n");
4214 mono_debug_record_line_number (cfg, ins, offset);
4216 switch (ins->opcode) {
4217 case OP_MEMORY_BARRIER:
4219 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4220 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4224 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4226 case OP_TLS_GET_REG:
4227 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4230 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4232 case OP_TLS_SET_REG:
4233 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4235 case OP_ATOMIC_EXCHANGE_I4:
4236 case OP_ATOMIC_CAS_I4:
4237 case OP_ATOMIC_ADD_I4: {
4241 g_assert (v7_supported);
4244 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4246 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4248 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4252 g_assert (cfg->arch.atomic_tmp_offset != -1);
4253 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4255 switch (ins->opcode) {
4256 case OP_ATOMIC_EXCHANGE_I4:
4258 ARM_DMB (code, ARM_DMB_SY);
4259 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4260 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4261 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4263 ARM_B_COND (code, ARMCOND_NE, 0);
4264 arm_patch (buf [1], buf [0]);
4266 case OP_ATOMIC_CAS_I4:
4267 ARM_DMB (code, ARM_DMB_SY);
4269 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4270 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4272 ARM_B_COND (code, ARMCOND_NE, 0);
4273 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4274 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4276 ARM_B_COND (code, ARMCOND_NE, 0);
4277 arm_patch (buf [2], buf [0]);
4278 arm_patch (buf [1], code);
4280 case OP_ATOMIC_ADD_I4:
4282 ARM_DMB (code, ARM_DMB_SY);
4283 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4284 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4285 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4286 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4288 ARM_B_COND (code, ARMCOND_NE, 0);
4289 arm_patch (buf [1], buf [0]);
4292 g_assert_not_reached ();
4295 ARM_DMB (code, ARM_DMB_SY);
4296 if (tmpreg != ins->dreg)
4297 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4298 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4301 case OP_ATOMIC_LOAD_I1:
4302 case OP_ATOMIC_LOAD_U1:
4303 case OP_ATOMIC_LOAD_I2:
4304 case OP_ATOMIC_LOAD_U2:
4305 case OP_ATOMIC_LOAD_I4:
4306 case OP_ATOMIC_LOAD_U4:
4307 case OP_ATOMIC_LOAD_R4:
4308 case OP_ATOMIC_LOAD_R8: {
4309 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4310 ARM_DMB (code, ARM_DMB_SY);
4312 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4314 switch (ins->opcode) {
4315 case OP_ATOMIC_LOAD_I1:
4316 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4318 case OP_ATOMIC_LOAD_U1:
4319 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4321 case OP_ATOMIC_LOAD_I2:
4322 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4324 case OP_ATOMIC_LOAD_U2:
4325 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4327 case OP_ATOMIC_LOAD_I4:
4328 case OP_ATOMIC_LOAD_U4:
4329 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4331 case OP_ATOMIC_LOAD_R4:
4333 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4334 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4336 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4337 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4338 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4339 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4340 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4343 case OP_ATOMIC_LOAD_R8:
4344 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4345 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4349 ARM_DMB (code, ARM_DMB_SY);
4352 case OP_ATOMIC_STORE_I1:
4353 case OP_ATOMIC_STORE_U1:
4354 case OP_ATOMIC_STORE_I2:
4355 case OP_ATOMIC_STORE_U2:
4356 case OP_ATOMIC_STORE_I4:
4357 case OP_ATOMIC_STORE_U4:
4358 case OP_ATOMIC_STORE_R4:
4359 case OP_ATOMIC_STORE_R8: {
4360 ARM_DMB (code, ARM_DMB_SY);
4362 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4364 switch (ins->opcode) {
4365 case OP_ATOMIC_STORE_I1:
4366 case OP_ATOMIC_STORE_U1:
4367 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4369 case OP_ATOMIC_STORE_I2:
4370 case OP_ATOMIC_STORE_U2:
4371 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4373 case OP_ATOMIC_STORE_I4:
4374 case OP_ATOMIC_STORE_U4:
4375 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4377 case OP_ATOMIC_STORE_R4:
4379 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4380 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4382 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4383 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4384 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4385 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4386 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4389 case OP_ATOMIC_STORE_R8:
4390 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4391 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4395 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4396 ARM_DMB (code, ARM_DMB_SY);
4400 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4401 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4404 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4405 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4407 case OP_STOREI1_MEMBASE_IMM:
4408 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4409 g_assert (arm_is_imm12 (ins->inst_offset));
4410 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4412 case OP_STOREI2_MEMBASE_IMM:
4413 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4414 g_assert (arm_is_imm8 (ins->inst_offset));
4415 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4417 case OP_STORE_MEMBASE_IMM:
4418 case OP_STOREI4_MEMBASE_IMM:
4419 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4420 g_assert (arm_is_imm12 (ins->inst_offset));
4421 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4423 case OP_STOREI1_MEMBASE_REG:
4424 g_assert (arm_is_imm12 (ins->inst_offset));
4425 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4427 case OP_STOREI2_MEMBASE_REG:
4428 g_assert (arm_is_imm8 (ins->inst_offset));
4429 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4431 case OP_STORE_MEMBASE_REG:
4432 case OP_STOREI4_MEMBASE_REG:
4433 /* this case is special, since it happens for spill code after lowering has been called */
4434 if (arm_is_imm12 (ins->inst_offset)) {
4435 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4437 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4438 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4441 case OP_STOREI1_MEMINDEX:
4442 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4444 case OP_STOREI2_MEMINDEX:
4445 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4447 case OP_STORE_MEMINDEX:
4448 case OP_STOREI4_MEMINDEX:
4449 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4452 g_assert_not_reached ();
4454 case OP_LOAD_MEMINDEX:
4455 case OP_LOADI4_MEMINDEX:
4456 case OP_LOADU4_MEMINDEX:
4457 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4459 case OP_LOADI1_MEMINDEX:
4460 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4462 case OP_LOADU1_MEMINDEX:
4463 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4465 case OP_LOADI2_MEMINDEX:
4466 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4468 case OP_LOADU2_MEMINDEX:
4469 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4471 case OP_LOAD_MEMBASE:
4472 case OP_LOADI4_MEMBASE:
4473 case OP_LOADU4_MEMBASE:
4474 /* this case is special, since it happens for spill code after lowering has been called */
4475 if (arm_is_imm12 (ins->inst_offset)) {
4476 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4478 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4479 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4482 case OP_LOADI1_MEMBASE:
4483 g_assert (arm_is_imm8 (ins->inst_offset));
4484 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4486 case OP_LOADU1_MEMBASE:
4487 g_assert (arm_is_imm12 (ins->inst_offset));
4488 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4490 case OP_LOADU2_MEMBASE:
4491 g_assert (arm_is_imm8 (ins->inst_offset));
4492 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4494 case OP_LOADI2_MEMBASE:
4495 g_assert (arm_is_imm8 (ins->inst_offset));
4496 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4498 case OP_ICONV_TO_I1:
4499 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4500 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4502 case OP_ICONV_TO_I2:
4503 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4504 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4506 case OP_ICONV_TO_U1:
4507 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4509 case OP_ICONV_TO_U2:
4510 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4511 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4515 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4517 case OP_COMPARE_IMM:
4518 case OP_ICOMPARE_IMM:
4519 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4520 g_assert (imm8 >= 0);
4521 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4525 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4526 * So instead of emitting a trap, we emit a call a C function and place a
4529 //*(int*)code = 0xef9f0001;
4532 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4533 (gpointer)"mono_break");
4534 code = emit_call_seq (cfg, code);
4536 case OP_RELAXED_NOP:
4541 case OP_DUMMY_STORE:
4542 case OP_DUMMY_ICONST:
4543 case OP_DUMMY_R8CONST:
4544 case OP_NOT_REACHED:
4547 case OP_IL_SEQ_POINT:
4548 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4550 case OP_SEQ_POINT: {
4552 MonoInst *info_var = cfg->arch.seq_point_info_var;
4553 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4554 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4555 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4557 int dreg = ARMREG_LR;
4559 if (cfg->soft_breakpoints) {
4560 g_assert (!cfg->compile_aot);
4564 * For AOT, we use one got slot per method, which will point to a
4565 * SeqPointInfo structure, containing all the information required
4566 * by the code below.
4568 if (cfg->compile_aot) {
4569 g_assert (info_var);
4570 g_assert (info_var->opcode == OP_REGOFFSET);
4571 g_assert (arm_is_imm12 (info_var->inst_offset));
4574 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4576 * Read from the single stepping trigger page. This will cause a
4577 * SIGSEGV when single stepping is enabled.
4578 * We do this _before_ the breakpoint, so single stepping after
4579 * a breakpoint is hit will step to the next IL offset.
4581 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4584 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4585 if (cfg->soft_breakpoints) {
4586 /* Load the address of the sequence point method variable. */
4587 var = ss_method_var;
4589 g_assert (var->opcode == OP_REGOFFSET);
4590 g_assert (arm_is_imm12 (var->inst_offset));
4591 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4593 /* Read the value and check whether it is non-zero. */
4594 ARM_LDR_IMM (code, dreg, dreg, 0);
4595 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4596 /* Call it conditionally. */
4597 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4599 if (cfg->compile_aot) {
4600 /* Load the trigger page addr from the variable initialized in the prolog */
4601 var = ss_trigger_page_var;
4603 g_assert (var->opcode == OP_REGOFFSET);
4604 g_assert (arm_is_imm12 (var->inst_offset));
4605 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4607 #ifdef USE_JUMP_TABLES
4608 gpointer *jte = mono_jumptable_add_entry ();
4609 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4610 jte [0] = ss_trigger_page;
4612 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4614 *(int*)code = (int)ss_trigger_page;
4618 ARM_LDR_IMM (code, dreg, dreg, 0);
4622 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4624 if (cfg->soft_breakpoints) {
4625 /* Load the address of the breakpoint method into ip. */
4626 var = bp_method_var;
4628 g_assert (var->opcode == OP_REGOFFSET);
4629 g_assert (arm_is_imm12 (var->inst_offset));
4630 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4633 * A placeholder for a possible breakpoint inserted by
4634 * mono_arch_set_breakpoint ().
4637 } else if (cfg->compile_aot) {
4638 guint32 offset = code - cfg->native_code;
4641 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4642 /* Add the offset */
4643 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4644 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4645 if (arm_is_imm12 ((int)val)) {
4646 ARM_LDR_IMM (code, dreg, dreg, val);
4648 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4650 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4652 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4653 g_assert (!(val & 0xFF000000));
4655 ARM_LDR_IMM (code, dreg, dreg, 0);
4657 /* What is faster, a branch or a load ? */
4658 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4659 /* The breakpoint instruction */
4660 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4663 * A placeholder for a possible breakpoint inserted by
4664 * mono_arch_set_breakpoint ().
4666 for (i = 0; i < 4; ++i)
4671 * Add an additional nop so skipping the bp doesn't cause the ip to point
4672 * to another IL offset.
4680 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4683 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4687 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4690 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4691 g_assert (imm8 >= 0);
4692 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4696 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4697 g_assert (imm8 >= 0);
4698 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4702 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4703 g_assert (imm8 >= 0);
4704 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4707 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4708 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4710 case OP_IADD_OVF_UN:
4711 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4712 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4715 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4716 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4718 case OP_ISUB_OVF_UN:
4719 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4720 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4722 case OP_ADD_OVF_CARRY:
4723 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4724 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4726 case OP_ADD_OVF_UN_CARRY:
4727 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4728 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4730 case OP_SUB_OVF_CARRY:
4731 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4732 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4734 case OP_SUB_OVF_UN_CARRY:
4735 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4736 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4740 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4743 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4744 g_assert (imm8 >= 0);
4745 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4748 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4752 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4756 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4757 g_assert (imm8 >= 0);
4758 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4762 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4763 g_assert (imm8 >= 0);
4764 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4766 case OP_ARM_RSBS_IMM:
4767 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4768 g_assert (imm8 >= 0);
4769 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4771 case OP_ARM_RSC_IMM:
4772 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4773 g_assert (imm8 >= 0);
4774 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4777 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4781 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4782 g_assert (imm8 >= 0);
4783 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4786 g_assert (v7s_supported || v7k_supported);
4787 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4790 g_assert (v7s_supported || v7k_supported);
4791 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4794 g_assert (v7s_supported || v7k_supported);
4795 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4796 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4799 g_assert (v7s_supported || v7k_supported);
4800 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4801 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4805 g_assert_not_reached ();
4807 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4811 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4812 g_assert (imm8 >= 0);
4813 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4816 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4820 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4821 g_assert (imm8 >= 0);
4822 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4825 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4830 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4831 else if (ins->dreg != ins->sreg1)
4832 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4835 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4840 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4841 else if (ins->dreg != ins->sreg1)
4842 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4845 case OP_ISHR_UN_IMM:
4847 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4848 else if (ins->dreg != ins->sreg1)
4849 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4852 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4855 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4858 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4861 if (ins->dreg == ins->sreg2)
4862 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4864 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4867 g_assert_not_reached ();
4870 /* FIXME: handle ovf/ sreg2 != dreg */
4871 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4872 /* FIXME: MUL doesn't set the C/O flags on ARM */
4874 case OP_IMUL_OVF_UN:
4875 /* FIXME: handle ovf/ sreg2 != dreg */
4876 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4877 /* FIXME: MUL doesn't set the C/O flags on ARM */
4880 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4883 /* Load the GOT offset */
4884 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4885 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4887 *(gpointer*)code = NULL;
4889 /* Load the value from the GOT */
4890 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4892 case OP_OBJC_GET_SELECTOR:
4893 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4894 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4896 *(gpointer*)code = NULL;
4898 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4900 case OP_ICONV_TO_I4:
4901 case OP_ICONV_TO_U4:
4903 if (ins->dreg != ins->sreg1)
4904 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4907 int saved = ins->sreg2;
4908 if (ins->sreg2 == ARM_LSW_REG) {
4909 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4912 if (ins->sreg1 != ARM_LSW_REG)
4913 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4914 if (saved != ARM_MSW_REG)
4915 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4919 if (IS_VFP && ins->dreg != ins->sreg1)
4920 ARM_CPYD (code, ins->dreg, ins->sreg1);
4923 if (IS_VFP && ins->dreg != ins->sreg1)
4924 ARM_CPYS (code, ins->dreg, ins->sreg1);
4926 case OP_MOVE_F_TO_I4:
4928 ARM_FMRS (code, ins->dreg, ins->sreg1);
4930 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4931 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4932 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4933 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4936 case OP_MOVE_I4_TO_F:
4938 ARM_FMSR (code, ins->dreg, ins->sreg1);
4940 ARM_FMSR (code, ins->dreg, ins->sreg1);
4941 ARM_CVTS (code, ins->dreg, ins->dreg);
4944 case OP_FCONV_TO_R4:
4947 ARM_CVTD (code, ins->dreg, ins->sreg1);
4949 ARM_CVTD (code, ins->dreg, ins->sreg1);
4950 ARM_CVTS (code, ins->dreg, ins->dreg);
4955 MonoCallInst *call = (MonoCallInst*)ins;
4958 * The stack looks like the following:
4959 * <caller argument area>
4962 * <callee argument area>
4963 * Need to copy the arguments from the callee argument area to
4964 * the caller argument area, and pop the frame.
4966 if (call->stack_usage) {
4967 int i, prev_sp_offset = 0;
4969 /* Compute size of saved registers restored below */
4971 prev_sp_offset = 2 * 4;
4973 prev_sp_offset = 1 * 4;
4974 for (i = 0; i < 16; ++i) {
4975 if (cfg->used_int_regs & (1 << i))
4976 prev_sp_offset += 4;
4979 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4981 /* Copy arguments on the stack to our argument area */
4982 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4983 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4984 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4989 * Keep in sync with mono_arch_emit_epilog
4991 g_assert (!cfg->method->save_lmf);
4993 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4995 if (cfg->used_int_regs)
4996 ARM_POP (code, cfg->used_int_regs);
4997 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4999 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5002 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5003 if (cfg->compile_aot) {
5004 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5006 *(gpointer*)code = NULL;
5008 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5010 code = mono_arm_patchable_b (code, ARMCOND_AL);
5011 cfg->thunk_area += THUNK_SIZE;
5016 /* ensure ins->sreg1 is not NULL */
5017 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5020 g_assert (cfg->sig_cookie < 128);
5021 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5022 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5032 call = (MonoCallInst*)ins;
5035 code = emit_float_args (cfg, call, code, &max_len, &offset);
5037 if (ins->flags & MONO_INST_HAS_METHOD)
5038 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5040 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5041 code = emit_call_seq (cfg, code);
5042 ins->flags |= MONO_INST_GC_CALLSITE;
5043 ins->backend.pc_offset = code - cfg->native_code;
5044 code = emit_move_return_value (cfg, ins, code);
5051 case OP_VOIDCALL_REG:
5054 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5056 code = emit_call_reg (code, ins->sreg1);
5057 ins->flags |= MONO_INST_GC_CALLSITE;
5058 ins->backend.pc_offset = code - cfg->native_code;
5059 code = emit_move_return_value (cfg, ins, code);
5061 case OP_FCALL_MEMBASE:
5062 case OP_RCALL_MEMBASE:
5063 case OP_LCALL_MEMBASE:
5064 case OP_VCALL_MEMBASE:
5065 case OP_VCALL2_MEMBASE:
5066 case OP_VOIDCALL_MEMBASE:
5067 case OP_CALL_MEMBASE: {
5068 g_assert (ins->sreg1 != ARMREG_LR);
5069 call = (MonoCallInst*)ins;
5072 code = emit_float_args (cfg, call, code, &max_len, &offset);
5073 if (!arm_is_imm12 (ins->inst_offset)) {
5074 /* sreg1 might be IP */
5075 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5076 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5077 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5078 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5079 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5081 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5082 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5084 ins->flags |= MONO_INST_GC_CALLSITE;
5085 ins->backend.pc_offset = code - cfg->native_code;
5086 code = emit_move_return_value (cfg, ins, code);
5089 case OP_GENERIC_CLASS_INIT: {
5090 static int byte_offset = -1;
5091 static guint8 bitmask;
5095 if (byte_offset < 0)
5096 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5098 g_assert (arm_is_imm8 (byte_offset));
5099 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5100 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5101 g_assert (imm8 >= 0);
5102 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5103 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5105 ARM_B_COND (code, ARMCOND_NE, 0);
5107 /* Uninitialized case */
5108 g_assert (ins->sreg1 == ARMREG_R0);
5110 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5111 (gpointer)"mono_generic_class_init");
5112 code = emit_call_seq (cfg, code);
5114 /* Initialized case */
5115 arm_patch (jump, code);
5119 /* round the size to 8 bytes */
5120 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5121 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5122 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5123 /* memzero the area: dreg holds the size, sp is the pointer */
5124 if (ins->flags & MONO_INST_INIT) {
5125 guint8 *start_loop, *branch_to_cond;
5126 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5127 branch_to_cond = code;
5130 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5131 arm_patch (branch_to_cond, code);
5132 /* decrement by 4 and set flags */
5133 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5134 ARM_B_COND (code, ARMCOND_GE, 0);
5135 arm_patch (code - 4, start_loop);
5137 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5138 if (cfg->param_area)
5139 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5144 MonoInst *var = cfg->dyn_call_var;
5146 g_assert (var->opcode == OP_REGOFFSET);
5147 g_assert (arm_is_imm12 (var->inst_offset));
5149 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5150 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5152 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5154 /* Save args buffer */
5155 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5157 /* Set stack slots using R0 as scratch reg */
5158 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5159 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5160 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5161 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5164 /* Set argument registers */
5165 for (i = 0; i < PARAM_REGS; ++i)
5166 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5169 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5170 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5173 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5174 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5175 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5179 if (ins->sreg1 != ARMREG_R0)
5180 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5181 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5182 (gpointer)"mono_arch_throw_exception");
5183 code = emit_call_seq (cfg, code);
5187 if (ins->sreg1 != ARMREG_R0)
5188 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5189 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5190 (gpointer)"mono_arch_rethrow_exception");
5191 code = emit_call_seq (cfg, code);
5194 case OP_START_HANDLER: {
5195 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5196 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5199 /* Reserve a param area, see filter-stack.exe */
5201 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5202 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5204 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5205 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5209 if (arm_is_imm12 (spvar->inst_offset)) {
5210 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5212 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5213 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5217 case OP_ENDFILTER: {
5218 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5219 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5222 /* Free the param area */
5224 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5225 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5227 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5228 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5232 if (ins->sreg1 != ARMREG_R0)
5233 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5234 if (arm_is_imm12 (spvar->inst_offset)) {
5235 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5237 g_assert (ARMREG_IP != spvar->inst_basereg);
5238 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5239 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5241 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5244 case OP_ENDFINALLY: {
5245 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5246 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5249 /* Free the param area */
5251 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5252 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5254 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5255 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5259 if (arm_is_imm12 (spvar->inst_offset)) {
5260 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5262 g_assert (ARMREG_IP != spvar->inst_basereg);
5263 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5264 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5266 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5269 case OP_CALL_HANDLER:
5270 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5271 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5272 cfg->thunk_area += THUNK_SIZE;
5273 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5276 if (ins->dreg != ARMREG_R0)
5277 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5281 ins->inst_c0 = code - cfg->native_code;
5284 /*if (ins->inst_target_bb->native_offset) {
5286 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5288 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5289 code = mono_arm_patchable_b (code, ARMCOND_AL);
5293 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5297 * In the normal case we have:
5298 * ldr pc, [pc, ins->sreg1 << 2]
5301 * ldr lr, [pc, ins->sreg1 << 2]
5303 * After follows the data.
5304 * FIXME: add aot support.
5306 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5307 #ifdef USE_JUMP_TABLES
5309 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5310 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5311 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5315 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5316 if (offset + max_len > (cfg->code_size - 16)) {
5317 cfg->code_size += max_len;
5318 cfg->code_size *= 2;
5319 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5320 code = cfg->native_code + offset;
5322 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5324 code += 4 * GPOINTER_TO_INT (ins->klass);
5329 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5330 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5334 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5335 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5339 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5340 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5344 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5345 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5349 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5350 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5353 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5354 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5357 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5358 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5361 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5362 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5365 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5366 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5369 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5370 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5372 case OP_COND_EXC_EQ:
5373 case OP_COND_EXC_NE_UN:
5374 case OP_COND_EXC_LT:
5375 case OP_COND_EXC_LT_UN:
5376 case OP_COND_EXC_GT:
5377 case OP_COND_EXC_GT_UN:
5378 case OP_COND_EXC_GE:
5379 case OP_COND_EXC_GE_UN:
5380 case OP_COND_EXC_LE:
5381 case OP_COND_EXC_LE_UN:
5382 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5384 case OP_COND_EXC_IEQ:
5385 case OP_COND_EXC_INE_UN:
5386 case OP_COND_EXC_ILT:
5387 case OP_COND_EXC_ILT_UN:
5388 case OP_COND_EXC_IGT:
5389 case OP_COND_EXC_IGT_UN:
5390 case OP_COND_EXC_IGE:
5391 case OP_COND_EXC_IGE_UN:
5392 case OP_COND_EXC_ILE:
5393 case OP_COND_EXC_ILE_UN:
5394 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5397 case OP_COND_EXC_IC:
5398 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5400 case OP_COND_EXC_OV:
5401 case OP_COND_EXC_IOV:
5402 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5404 case OP_COND_EXC_NC:
5405 case OP_COND_EXC_INC:
5406 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5408 case OP_COND_EXC_NO:
5409 case OP_COND_EXC_INO:
5410 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5422 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5425 /* floating point opcodes */
5427 if (cfg->compile_aot) {
5428 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5430 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5432 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5435 /* FIXME: we can optimize the imm load by dealing with part of
5436 * the displacement in LDFD (aligning to 512).
5438 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5439 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5443 if (cfg->compile_aot) {
5444 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5446 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5449 ARM_CVTS (code, ins->dreg, ins->dreg);
5451 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5452 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5454 ARM_CVTS (code, ins->dreg, ins->dreg);
5457 case OP_STORER8_MEMBASE_REG:
5458 /* This is generated by the local regalloc pass which runs after the lowering pass */
5459 if (!arm_is_fpimm8 (ins->inst_offset)) {
5460 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5461 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5462 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5464 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5467 case OP_LOADR8_MEMBASE:
5468 /* This is generated by the local regalloc pass which runs after the lowering pass */
5469 if (!arm_is_fpimm8 (ins->inst_offset)) {
5470 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5471 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5472 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5474 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5477 case OP_STORER4_MEMBASE_REG:
5478 g_assert (arm_is_fpimm8 (ins->inst_offset));
5480 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5482 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5483 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5484 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5485 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5488 case OP_LOADR4_MEMBASE:
5490 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5492 g_assert (arm_is_fpimm8 (ins->inst_offset));
5493 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5494 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5495 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5496 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5499 case OP_ICONV_TO_R_UN: {
5500 g_assert_not_reached ();
5503 case OP_ICONV_TO_R4:
5505 ARM_FMSR (code, ins->dreg, ins->sreg1);
5506 ARM_FSITOS (code, ins->dreg, ins->dreg);
5508 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5509 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5510 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5511 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5512 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5515 case OP_ICONV_TO_R8:
5516 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5517 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5518 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5519 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5523 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5524 if (sig_ret->type == MONO_TYPE_R4) {
5526 g_assert (!IS_HARD_FLOAT);
5527 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5529 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5532 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5536 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5538 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5542 case OP_FCONV_TO_I1:
5543 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5545 case OP_FCONV_TO_U1:
5546 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5548 case OP_FCONV_TO_I2:
5549 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5551 case OP_FCONV_TO_U2:
5552 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5554 case OP_FCONV_TO_I4:
5556 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5558 case OP_FCONV_TO_U4:
5560 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5562 case OP_FCONV_TO_I8:
5563 case OP_FCONV_TO_U8:
5564 g_assert_not_reached ();
5565 /* Implemented as helper calls */
5567 case OP_LCONV_TO_R_UN:
5568 g_assert_not_reached ();
5569 /* Implemented as helper calls */
5571 case OP_LCONV_TO_OVF_I4_2: {
5572 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5574 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5577 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5578 high_bit_not_set = code;
5579 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5581 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5582 valid_negative = code;
5583 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5584 invalid_negative = code;
5585 ARM_B_COND (code, ARMCOND_AL, 0);
5587 arm_patch (high_bit_not_set, code);
5589 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5590 valid_positive = code;
5591 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5593 arm_patch (invalid_negative, code);
5594 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5596 arm_patch (valid_negative, code);
5597 arm_patch (valid_positive, code);
5599 if (ins->dreg != ins->sreg1)
5600 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5604 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5607 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5610 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5613 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5616 ARM_NEGD (code, ins->dreg, ins->sreg1);
5620 g_assert_not_reached ();
5624 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5630 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5635 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5638 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5639 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5643 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5646 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5647 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5651 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5654 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5655 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5656 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5660 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5663 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5664 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5668 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5671 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5672 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5673 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5677 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5680 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5681 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5685 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5688 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5689 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5693 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5696 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5697 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5700 /* ARM FPA flags table:
5701 * N Less than ARMCOND_MI
5702 * Z Equal ARMCOND_EQ
5703 * C Greater Than or Equal ARMCOND_CS
5704 * V Unordered ARMCOND_VS
5707 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5710 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5713 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5716 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5717 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5723 g_assert_not_reached ();
5727 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5729 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5730 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5731 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5735 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5736 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5741 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5742 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5744 #ifdef USE_JUMP_TABLES
5746 gpointer *jte = mono_jumptable_add_entries (2);
5747 jte [0] = GUINT_TO_POINTER (0xffffffff);
5748 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5749 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5750 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5753 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5754 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5756 *(guint32*)code = 0xffffffff;
5758 *(guint32*)code = 0x7fefffff;
5761 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5763 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5764 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5766 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5767 ARM_CPYD (code, ins->dreg, ins->sreg1);
5769 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5770 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5775 case OP_RCONV_TO_I1:
5776 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5778 case OP_RCONV_TO_U1:
5779 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5781 case OP_RCONV_TO_I2:
5782 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5784 case OP_RCONV_TO_U2:
5785 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5787 case OP_RCONV_TO_I4:
5788 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5790 case OP_RCONV_TO_U4:
5791 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5793 case OP_RCONV_TO_R4:
5795 if (ins->dreg != ins->sreg1)
5796 ARM_CPYS (code, ins->dreg, ins->sreg1);
5798 case OP_RCONV_TO_R8:
5800 ARM_CVTS (code, ins->dreg, ins->sreg1);
5803 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5806 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5809 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5812 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5815 ARM_NEGS (code, ins->dreg, ins->sreg1);
5819 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5822 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5823 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5827 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5830 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5831 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5835 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5838 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5839 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5840 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5844 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5847 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5848 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5852 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5855 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5856 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5857 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5861 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5864 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5865 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5869 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5872 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5873 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5877 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5880 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5881 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5884 case OP_GC_LIVENESS_DEF:
5885 case OP_GC_LIVENESS_USE:
5886 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5887 ins->backend.pc_offset = code - cfg->native_code;
5889 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5890 ins->backend.pc_offset = code - cfg->native_code;
5891 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5893 case OP_GC_SAFE_POINT: {
5894 const char *polling_func = NULL;
5897 g_assert (mono_threads_is_coop_enabled ());
5899 polling_func = "mono_threads_state_poll";
5900 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5901 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5903 ARM_B_COND (code, ARMCOND_EQ, 0);
5904 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5905 code = emit_call_seq (cfg, code);
5906 arm_patch (buf [0], code);
5911 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5912 g_assert_not_reached ();
5915 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5916 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5917 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5918 g_assert_not_reached ();
5924 last_offset = offset;
5927 cfg->code_len = code - cfg->native_code;
5930 #endif /* DISABLE_JIT */
5933 mono_arch_register_lowlevel_calls (void)
5935 /* The signature doesn't matter */
5936 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5937 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5938 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5940 #ifndef MONO_CROSS_COMPILE
5941 if (mono_arm_have_tls_get ()) {
5942 MonoTlsImplementation tls_imp = mono_arm_get_tls_implementation ();
5944 mono_register_jit_icall (tls_imp.get_tls_thunk, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
5945 mono_register_jit_icall (tls_imp.set_tls_thunk, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
5947 if (tls_imp.get_tls_thunk_end) {
5948 mono_tramp_info_register (
5949 mono_tramp_info_create (
5951 (guint8*)tls_imp.get_tls_thunk,
5952 (guint8*)tls_imp.get_tls_thunk_end - (guint8*)tls_imp.get_tls_thunk,
5954 mono_arch_get_cie_program ()
5958 mono_tramp_info_register (
5959 mono_tramp_info_create (
5961 (guint8*)tls_imp.set_tls_thunk,
5962 (guint8*)tls_imp.set_tls_thunk_end - (guint8*)tls_imp.set_tls_thunk,
5964 mono_arch_get_cie_program ()
5973 #define patch_lis_ori(ip,val) do {\
5974 guint16 *__lis_ori = (guint16*)(ip); \
5975 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5976 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5980 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5982 unsigned char *ip = ji->ip.i + code;
5984 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5988 case MONO_PATCH_INFO_SWITCH: {
5989 #ifdef USE_JUMP_TABLES
5990 gpointer *jt = mono_jumptable_get_entry (ip);
5992 gpointer *jt = (gpointer*)(ip + 8);
5995 /* jt is the inlined jump table, 2 instructions after ip
5996 * In the normal case we store the absolute addresses,
5997 * otherwise the displacements.
5999 for (i = 0; i < ji->data.table->table_size; i++)
6000 jt [i] = code + (int)ji->data.table->table [i];
6003 case MONO_PATCH_INFO_IP:
6004 g_assert_not_reached ();
6005 patch_lis_ori (ip, ip);
6007 case MONO_PATCH_INFO_METHOD_REL:
6008 g_assert_not_reached ();
6009 *((gpointer *)(ip)) = target;
6011 case MONO_PATCH_INFO_METHODCONST:
6012 case MONO_PATCH_INFO_CLASS:
6013 case MONO_PATCH_INFO_IMAGE:
6014 case MONO_PATCH_INFO_FIELD:
6015 case MONO_PATCH_INFO_VTABLE:
6016 case MONO_PATCH_INFO_IID:
6017 case MONO_PATCH_INFO_SFLDA:
6018 case MONO_PATCH_INFO_LDSTR:
6019 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6020 case MONO_PATCH_INFO_LDTOKEN:
6021 g_assert_not_reached ();
6022 /* from OP_AOTCONST : lis + ori */
6023 patch_lis_ori (ip, target);
6025 case MONO_PATCH_INFO_R4:
6026 case MONO_PATCH_INFO_R8:
6027 g_assert_not_reached ();
6028 *((gconstpointer *)(ip + 2)) = target;
6030 case MONO_PATCH_INFO_EXC_NAME:
6031 g_assert_not_reached ();
6032 *((gconstpointer *)(ip + 1)) = target;
6034 case MONO_PATCH_INFO_NONE:
6035 case MONO_PATCH_INFO_BB_OVF:
6036 case MONO_PATCH_INFO_EXC_OVF:
6037 /* everything is dealt with at epilog output time */
6040 arm_patch_general (cfg, domain, ip, target);
6046 mono_arm_unaligned_stack (MonoMethod *method)
6048 g_assert_not_reached ();
6054 * Stack frame layout:
6056 * ------------------- fp
6057 * MonoLMF structure or saved registers
6058 * -------------------
6060 * -------------------
6062 * -------------------
6063 * optional 8 bytes for tracing
6064 * -------------------
6065 * param area size is cfg->param_area
6066 * ------------------- sp
6069 mono_arch_emit_prolog (MonoCompile *cfg)
6071 MonoMethod *method = cfg->method;
6073 MonoMethodSignature *sig;
6075 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6080 int prev_sp_offset, reg_offset;
6082 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6085 sig = mono_method_signature (method);
6086 cfg->code_size = 256 + sig->param_count * 64;
6087 code = cfg->native_code = g_malloc (cfg->code_size);
6089 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6091 alloc_size = cfg->stack_offset;
6097 * The iphone uses R7 as the frame pointer, and it points at the saved
6102 * We can't use r7 as a frame pointer since it points into the middle of
6103 * the frame, so we keep using our own frame pointer.
6104 * FIXME: Optimize this.
6106 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6107 prev_sp_offset += 8; /* r7 and lr */
6108 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6109 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6110 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6113 if (!method->save_lmf) {
6115 /* No need to push LR again */
6116 if (cfg->used_int_regs)
6117 ARM_PUSH (code, cfg->used_int_regs);
6119 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6120 prev_sp_offset += 4;
6122 for (i = 0; i < 16; ++i) {
6123 if (cfg->used_int_regs & (1 << i))
6124 prev_sp_offset += 4;
6126 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6128 for (i = 0; i < 16; ++i) {
6129 if ((cfg->used_int_regs & (1 << i))) {
6130 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6131 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6136 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6137 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6139 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6140 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6143 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6144 ARM_PUSH (code, 0x5ff0);
6145 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6146 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6148 for (i = 0; i < 16; ++i) {
6149 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6150 /* The original r7 is saved at the start */
6151 if (!(iphone_abi && i == ARMREG_R7))
6152 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6156 g_assert (reg_offset == 4 * 10);
6157 pos += sizeof (MonoLMF) - (4 * 10);
6161 orig_alloc_size = alloc_size;
6162 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6163 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6164 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6165 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6168 /* the stack used in the pushed regs */
6169 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6170 cfg->stack_usage = alloc_size;
6172 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6173 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6175 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6176 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6178 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6180 if (cfg->frame_reg != ARMREG_SP) {
6181 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6182 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6184 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6185 prev_sp_offset += alloc_size;
6187 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6188 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6190 /* compute max_offset in order to use short forward jumps
6191 * we could skip do it on arm because the immediate displacement
6192 * for jumps is large enough, it may be useful later for constant pools
6195 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6196 MonoInst *ins = bb->code;
6197 bb->max_offset = max_offset;
6199 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6202 MONO_BB_FOR_EACH_INS (bb, ins)
6203 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6206 /* stack alignment check */
6210 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6211 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6212 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6213 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6215 ARM_B_COND (code, ARMCOND_EQ, 0);
6216 if (cfg->compile_aot)
6217 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6219 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6220 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6221 code = emit_call_seq (cfg, code);
6222 arm_patch (buf [0], code);
6226 /* store runtime generic context */
6227 if (cfg->rgctx_var) {
6228 MonoInst *ins = cfg->rgctx_var;
6230 g_assert (ins->opcode == OP_REGOFFSET);
6232 if (arm_is_imm12 (ins->inst_offset)) {
6233 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6235 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6236 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6240 /* load arguments allocated to register from the stack */
6243 cinfo = get_call_info (NULL, sig);
6245 if (cinfo->ret.storage == RegTypeStructByAddr) {
6246 ArgInfo *ainfo = &cinfo->ret;
6247 inst = cfg->vret_addr;
6248 g_assert (arm_is_imm12 (inst->inst_offset));
6249 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6252 if (sig->call_convention == MONO_CALL_VARARG) {
6253 ArgInfo *cookie = &cinfo->sig_cookie;
6255 /* Save the sig cookie address */
6256 g_assert (cookie->storage == RegTypeBase);
6258 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6259 g_assert (arm_is_imm12 (cfg->sig_cookie));
6260 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6261 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6264 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6265 ArgInfo *ainfo = cinfo->args + i;
6266 inst = cfg->args [pos];
6268 if (cfg->verbose_level > 2)
6269 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6271 if (inst->opcode == OP_REGVAR) {
6272 if (ainfo->storage == RegTypeGeneral)
6273 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6274 else if (ainfo->storage == RegTypeFP) {
6275 g_assert_not_reached ();
6276 } else if (ainfo->storage == RegTypeBase) {
6277 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6278 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6280 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6281 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6284 g_assert_not_reached ();
6286 if (cfg->verbose_level > 2)
6287 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6289 switch (ainfo->storage) {
6291 for (part = 0; part < ainfo->nregs; part ++) {
6292 if (ainfo->esize == 4)
6293 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6295 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6298 case RegTypeGeneral:
6299 case RegTypeIRegPair:
6300 case RegTypeGSharedVtInReg:
6301 switch (ainfo->size) {
6303 if (arm_is_imm12 (inst->inst_offset))
6304 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6306 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6307 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6311 if (arm_is_imm8 (inst->inst_offset)) {
6312 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6314 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6315 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6319 if (arm_is_imm12 (inst->inst_offset)) {
6320 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6322 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6323 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6325 if (arm_is_imm12 (inst->inst_offset + 4)) {
6326 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6328 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6329 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6333 if (arm_is_imm12 (inst->inst_offset)) {
6334 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6336 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6337 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6342 case RegTypeBaseGen:
6343 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6344 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6346 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6347 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6349 if (arm_is_imm12 (inst->inst_offset + 4)) {
6350 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6351 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6353 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6354 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6355 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6356 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6360 case RegTypeGSharedVtOnStack:
6361 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6362 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6364 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6365 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6368 switch (ainfo->size) {
6370 if (arm_is_imm8 (inst->inst_offset)) {
6371 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6373 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6374 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6378 if (arm_is_imm8 (inst->inst_offset)) {
6379 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6381 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6382 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6386 if (arm_is_imm12 (inst->inst_offset)) {
6387 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6389 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6390 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6392 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6393 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6395 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6396 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6398 if (arm_is_imm12 (inst->inst_offset + 4)) {
6399 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6401 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6402 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6406 if (arm_is_imm12 (inst->inst_offset)) {
6407 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6409 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6410 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6416 int imm8, rot_amount;
6418 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6419 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6420 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6422 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6424 if (ainfo->size == 8)
6425 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6427 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6430 case RegTypeStructByVal: {
6431 int doffset = inst->inst_offset;
6435 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6436 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6437 if (arm_is_imm12 (doffset)) {
6438 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6440 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6441 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6443 soffset += sizeof (gpointer);
6444 doffset += sizeof (gpointer);
6446 if (ainfo->vtsize) {
6447 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6448 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6449 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6453 case RegTypeStructByAddr:
6454 g_assert_not_reached ();
6455 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6456 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6458 g_assert_not_reached ();
6465 if (method->save_lmf)
6466 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6469 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6471 if (cfg->arch.seq_point_info_var) {
6472 MonoInst *ins = cfg->arch.seq_point_info_var;
6474 /* Initialize the variable from a GOT slot */
6475 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6476 #ifdef USE_JUMP_TABLES
6478 gpointer *jte = mono_jumptable_add_entry ();
6479 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6480 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6482 /** XXX: is it correct? */
6484 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6486 *(gpointer*)code = NULL;
6489 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6491 g_assert (ins->opcode == OP_REGOFFSET);
6493 if (arm_is_imm12 (ins->inst_offset)) {
6494 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6496 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6497 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6501 /* Initialize ss_trigger_page_var */
6502 if (!cfg->soft_breakpoints) {
6503 MonoInst *info_var = cfg->arch.seq_point_info_var;
6504 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6505 int dreg = ARMREG_LR;
6508 g_assert (info_var->opcode == OP_REGOFFSET);
6509 g_assert (arm_is_imm12 (info_var->inst_offset));
6511 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6512 /* Load the trigger page addr */
6513 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6514 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6518 if (cfg->arch.seq_point_ss_method_var) {
6519 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6520 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6521 #ifdef USE_JUMP_TABLES
6524 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6525 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6526 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6527 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6529 #ifdef USE_JUMP_TABLES
6530 jte = mono_jumptable_add_entries (3);
6531 jte [0] = &single_step_tramp;
6532 jte [1] = breakpoint_tramp;
6533 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6535 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6537 *(gpointer*)code = &single_step_tramp;
6539 *(gpointer*)code = breakpoint_tramp;
6543 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6544 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6545 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6546 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6549 cfg->code_len = code - cfg->native_code;
6550 g_assert (cfg->code_len < cfg->code_size);
6557 mono_arch_emit_epilog (MonoCompile *cfg)
6559 MonoMethod *method = cfg->method;
6560 int pos, i, rot_amount;
6561 int max_epilog_size = 16 + 20*4;
6565 if (cfg->method->save_lmf)
6566 max_epilog_size += 128;
6568 if (mono_jit_trace_calls != NULL)
6569 max_epilog_size += 50;
6571 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6572 max_epilog_size += 50;
6574 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6575 cfg->code_size *= 2;
6576 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6577 cfg->stat_code_reallocs++;
6581 * Keep in sync with OP_JMP
6583 code = cfg->native_code + cfg->code_len;
6585 /* Save the uwind state which is needed by the out-of-line code */
6586 mono_emit_unwind_op_remember_state (cfg, code);
6588 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6589 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6593 /* Load returned vtypes into registers if needed */
6594 cinfo = cfg->arch.cinfo;
6595 switch (cinfo->ret.storage) {
6596 case RegTypeStructByVal: {
6597 MonoInst *ins = cfg->ret;
6599 if (arm_is_imm12 (ins->inst_offset)) {
6600 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6602 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6603 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6608 MonoInst *ins = cfg->ret;
6610 for (i = 0; i < cinfo->ret.nregs; ++i) {
6611 if (cinfo->ret.esize == 4)
6612 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6614 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6622 if (method->save_lmf) {
6623 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6624 /* all but r0-r3, sp and pc */
6625 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6628 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6630 /* This points to r4 inside MonoLMF->iregs */
6631 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6633 regmask = 0x9ff0; /* restore lr to pc */
6634 /* Skip caller saved registers not used by the method */
6635 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6636 regmask &= ~(1 << reg);
6641 /* Restored later */
6642 regmask &= ~(1 << ARMREG_PC);
6643 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6644 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6645 for (i = 0; i < 16; i++) {
6646 if (regmask & (1 << i))
6649 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6651 ARM_POP (code, regmask);
6653 for (i = 0; i < 16; i++) {
6654 if (regmask & (1 << i))
6655 mono_emit_unwind_op_same_value (cfg, code, i);
6657 /* Restore saved r7, restore LR to PC */
6658 /* Skip lr from the lmf */
6659 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6660 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6661 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6662 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6665 int i, nused_int_regs = 0;
6667 for (i = 0; i < 16; i++) {
6668 if (cfg->used_int_regs & (1 << i))
6672 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6673 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6675 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6676 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6679 if (cfg->frame_reg != ARMREG_SP) {
6680 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6684 /* Restore saved gregs */
6685 if (cfg->used_int_regs) {
6686 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6687 ARM_POP (code, cfg->used_int_regs);
6688 for (i = 0; i < 16; i++) {
6689 if (cfg->used_int_regs & (1 << i))
6690 mono_emit_unwind_op_same_value (cfg, code, i);
6693 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6694 /* Restore saved r7, restore LR to PC */
6695 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6697 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6698 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6702 /* Restore the unwind state to be the same as before the epilog */
6703 mono_emit_unwind_op_restore_state (cfg, code);
6705 cfg->code_len = code - cfg->native_code;
6707 g_assert (cfg->code_len < cfg->code_size);
6712 mono_arch_emit_exceptions (MonoCompile *cfg)
6714 MonoJumpInfo *patch_info;
6717 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6718 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6719 int max_epilog_size = 50;
6721 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6722 exc_throw_pos [i] = NULL;
6723 exc_throw_found [i] = 0;
6726 /* count the number of exception infos */
6729 * make sure we have enough space for exceptions
6731 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6732 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6733 i = mini_exception_id_by_name (patch_info->data.target);
6734 if (!exc_throw_found [i]) {
6735 max_epilog_size += 32;
6736 exc_throw_found [i] = TRUE;
6741 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6742 cfg->code_size *= 2;
6743 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6744 cfg->stat_code_reallocs++;
6747 code = cfg->native_code + cfg->code_len;
6749 /* add code to raise exceptions */
6750 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6751 switch (patch_info->type) {
6752 case MONO_PATCH_INFO_EXC: {
6753 MonoClass *exc_class;
6754 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6756 i = mini_exception_id_by_name (patch_info->data.target);
6757 if (exc_throw_pos [i]) {
6758 arm_patch (ip, exc_throw_pos [i]);
6759 patch_info->type = MONO_PATCH_INFO_NONE;
6762 exc_throw_pos [i] = code;
6764 arm_patch (ip, code);
6766 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6768 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6769 #ifdef USE_JUMP_TABLES
6771 gpointer *jte = mono_jumptable_add_entries (2);
6772 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6773 patch_info->data.name = "mono_arch_throw_corlib_exception";
6774 patch_info->ip.i = code - cfg->native_code;
6775 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6776 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6777 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6778 ARM_BLX_REG (code, ARMREG_IP);
6779 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6782 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6783 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6784 patch_info->data.name = "mono_arch_throw_corlib_exception";
6785 patch_info->ip.i = code - cfg->native_code;
6787 cfg->thunk_area += THUNK_SIZE;
6788 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6799 cfg->code_len = code - cfg->native_code;
6801 g_assert (cfg->code_len < cfg->code_size);
6805 #endif /* #ifndef DISABLE_JIT */
6808 mono_arch_finish_init (void)
6813 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6818 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6825 mono_arch_print_tree (MonoInst *tree, int arity)
6835 mono_arch_get_patch_offset (guint8 *code)
6842 mono_arch_flush_register_windows (void)
6847 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6849 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6853 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6855 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6859 mono_arch_get_cie_program (void)
6863 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6868 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6869 #define BASE_SIZE (6 * 4)
6870 #define BSEARCH_ENTRY_SIZE (4 * 4)
6871 #define CMP_SIZE (3 * 4)
6872 #define BRANCH_SIZE (1 * 4)
6873 #define CALL_SIZE (2 * 4)
6874 #define WMC_SIZE (8 * 4)
6875 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6877 #ifdef USE_JUMP_TABLES
6879 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6881 g_assert (base [index] == NULL);
6882 base [index] = value;
6885 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6887 if (arm_is_imm12 (jti * 4)) {
6888 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6890 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6891 if ((jti * 4) >> 16)
6892 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6893 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6899 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6901 guint32 delta = DISTANCE (target, code);
6903 g_assert (delta >= 0 && delta <= 0xFFF);
6904 *target = *target | delta;
6910 #ifdef ENABLE_WRONG_METHOD_CHECK
6912 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6914 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6920 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6921 gpointer fail_tramp)
6924 arminstr_t *code, *start;
6925 #ifdef USE_JUMP_TABLES
6928 gboolean large_offsets = FALSE;
6929 guint32 **constant_pool_starts;
6930 arminstr_t *vtable_target = NULL;
6931 int extra_space = 0;
6933 #ifdef ENABLE_WRONG_METHOD_CHECK
6939 #ifdef USE_JUMP_TABLES
6940 for (i = 0; i < count; ++i) {
6941 MonoIMTCheckItem *item = imt_entries [i];
6942 item->chunk_size += 4 * 16;
6943 if (!item->is_equals)
6944 imt_entries [item->check_target_idx]->compare_done = TRUE;
6945 size += item->chunk_size;
6948 constant_pool_starts = g_new0 (guint32*, count);
6950 for (i = 0; i < count; ++i) {
6951 MonoIMTCheckItem *item = imt_entries [i];
6952 if (item->is_equals) {
6953 gboolean fail_case = !item->check_target_idx && fail_tramp;
6955 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6956 item->chunk_size += 32;
6957 large_offsets = TRUE;
6960 if (item->check_target_idx || fail_case) {
6961 if (!item->compare_done || fail_case)
6962 item->chunk_size += CMP_SIZE;
6963 item->chunk_size += BRANCH_SIZE;
6965 #ifdef ENABLE_WRONG_METHOD_CHECK
6966 item->chunk_size += WMC_SIZE;
6970 item->chunk_size += 16;
6971 large_offsets = TRUE;
6973 item->chunk_size += CALL_SIZE;
6975 item->chunk_size += BSEARCH_ENTRY_SIZE;
6976 imt_entries [item->check_target_idx]->compare_done = TRUE;
6978 size += item->chunk_size;
6982 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6986 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6988 code = mono_domain_code_reserve (domain, size);
6991 unwind_ops = mono_arch_get_cie_program ();
6994 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6995 for (i = 0; i < count; ++i) {
6996 MonoIMTCheckItem *item = imt_entries [i];
6997 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
7001 #ifdef USE_JUMP_TABLES
7002 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7003 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 3 * sizeof (mgreg_t));
7004 #define VTABLE_JTI 0
7005 #define IMT_METHOD_OFFSET 0
7006 #define TARGET_CODE_OFFSET 1
7007 #define JUMP_CODE_OFFSET 2
7008 #define RECORDS_PER_ENTRY 3
7009 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
7010 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
7011 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
7013 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
7014 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
7015 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
7016 set_jumptable_element (jte, VTABLE_JTI, vtable);
7018 if (large_offsets) {
7019 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7020 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
7022 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7023 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7025 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7026 vtable_target = code;
7027 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7029 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7031 for (i = 0; i < count; ++i) {
7032 MonoIMTCheckItem *item = imt_entries [i];
7033 #ifdef USE_JUMP_TABLES
7034 guint32 imt_method_jti = 0, target_code_jti = 0;
7036 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7038 gint32 vtable_offset;
7040 item->code_target = (guint8*)code;
7042 if (item->is_equals) {
7043 gboolean fail_case = !item->check_target_idx && fail_tramp;
7045 if (item->check_target_idx || fail_case) {
7046 if (!item->compare_done || fail_case) {
7047 #ifdef USE_JUMP_TABLES
7048 imt_method_jti = IMT_METHOD_JTI (i);
7049 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7052 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7054 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7056 #ifdef USE_JUMP_TABLES
7057 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7058 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7059 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7061 item->jmp_code = (guint8*)code;
7062 ARM_B_COND (code, ARMCOND_NE, 0);
7065 /*Enable the commented code to assert on wrong method*/
7066 #ifdef ENABLE_WRONG_METHOD_CHECK
7067 #ifdef USE_JUMP_TABLES
7068 imt_method_jti = IMT_METHOD_JTI (i);
7069 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7072 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7074 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7076 ARM_B_COND (code, ARMCOND_EQ, 0);
7078 /* Define this if your system is so bad that gdb is failing. */
7079 #ifdef BROKEN_DEV_ENV
7080 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7082 arm_patch (code - 1, mini_dump_bad_imt);
7086 arm_patch (cond, code);
7090 if (item->has_target_code) {
7091 /* Load target address */
7092 #ifdef USE_JUMP_TABLES
7093 target_code_jti = TARGET_CODE_JTI (i);
7094 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7095 /* Restore registers */
7096 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7097 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7099 ARM_BX (code, ARMREG_R1);
7100 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7102 target_code_ins = code;
7103 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7104 /* Save it to the fourth slot */
7105 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7106 /* Restore registers and branch */
7107 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7109 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7112 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7113 if (!arm_is_imm12 (vtable_offset)) {
7115 * We need to branch to a computed address but we don't have
7116 * a free register to store it, since IP must contain the
7117 * vtable address. So we push the two values to the stack, and
7118 * load them both using LDM.
7120 /* Compute target address */
7121 #ifdef USE_JUMP_TABLES
7122 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7123 if (vtable_offset >> 16)
7124 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7125 /* IP had vtable base. */
7126 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7127 /* Restore registers and branch */
7128 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7129 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7130 ARM_BX (code, ARMREG_IP);
7132 vtable_offset_ins = code;
7133 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7134 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7135 /* Save it to the fourth slot */
7136 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7137 /* Restore registers and branch */
7138 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7140 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7143 #ifdef USE_JUMP_TABLES
7144 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7145 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7146 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7147 ARM_BX (code, ARMREG_IP);
7149 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7150 if (large_offsets) {
7151 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7152 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7154 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7155 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7161 #ifdef USE_JUMP_TABLES
7162 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7163 target_code_jti = TARGET_CODE_JTI (i);
7164 /* Load target address */
7165 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7166 /* Restore registers */
7167 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7168 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7170 ARM_BX (code, ARMREG_R1);
7171 set_jumptable_element (jte, target_code_jti, fail_tramp);
7173 arm_patch (item->jmp_code, (guchar*)code);
7175 target_code_ins = code;
7176 /* Load target address */
7177 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7178 /* Save it to the fourth slot */
7179 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7180 /* Restore registers and branch */
7181 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7183 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7185 item->jmp_code = NULL;
7188 #ifdef USE_JUMP_TABLES
7190 set_jumptable_element (jte, imt_method_jti, item->key);
7193 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7195 /*must emit after unconditional branch*/
7196 if (vtable_target) {
7197 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7198 item->chunk_size += 4;
7199 vtable_target = NULL;
7202 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7203 constant_pool_starts [i] = code;
7205 code += extra_space;
7210 #ifdef USE_JUMP_TABLES
7211 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7212 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7213 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7214 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7215 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7217 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7218 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7220 item->jmp_code = (guint8*)code;
7221 ARM_B_COND (code, ARMCOND_HS, 0);
7227 for (i = 0; i < count; ++i) {
7228 MonoIMTCheckItem *item = imt_entries [i];
7229 if (item->jmp_code) {
7230 if (item->check_target_idx)
7231 #ifdef USE_JUMP_TABLES
7232 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7234 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7237 if (i > 0 && item->is_equals) {
7239 #ifdef USE_JUMP_TABLES
7240 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7241 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7243 arminstr_t *space_start = constant_pool_starts [i];
7244 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7245 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7253 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7254 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7259 #ifndef USE_JUMP_TABLES
7260 g_free (constant_pool_starts);
7263 mono_arch_flush_icache ((guint8*)start, size);
7264 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7265 mono_stats.imt_thunks_size += code - start;
7267 g_assert (DISTANCE (start, code) <= size);
7269 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7275 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7277 return ctx->regs [reg];
7281 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7283 ctx->regs [reg] = val;
7287 * mono_arch_get_trampolines:
7289 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7293 mono_arch_get_trampolines (gboolean aot)
7295 return mono_arm_get_exception_trampolines (aot);
7299 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7306 bp = MONO_CONTEXT_GET_BP (ctx);
7307 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7309 old_value = *lr_loc;
7310 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7313 *lr_loc = new_value;
7318 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7320 * mono_arch_set_breakpoint:
7322 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7323 * The location should contain code emitted by OP_SEQ_POINT.
7326 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7329 guint32 native_offset = ip - (guint8*)ji->code_start;
7330 MonoDebugOptions *opt = mini_get_debug_options ();
7332 if (opt->soft_breakpoints) {
7333 g_assert (!ji->from_aot);
7335 ARM_BLX_REG (code, ARMREG_LR);
7336 mono_arch_flush_icache (code - 4, 4);
7337 } else if (ji->from_aot) {
7338 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7340 g_assert (native_offset % 4 == 0);
7341 g_assert (info->bp_addrs [native_offset / 4] == 0);
7342 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7344 int dreg = ARMREG_LR;
7346 /* Read from another trigger page */
7347 #ifdef USE_JUMP_TABLES
7348 gpointer *jte = mono_jumptable_add_entry ();
7349 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7350 jte [0] = bp_trigger_page;
7352 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7354 *(int*)code = (int)bp_trigger_page;
7357 ARM_LDR_IMM (code, dreg, dreg, 0);
7359 mono_arch_flush_icache (code - 16, 16);
7362 /* This is currently implemented by emitting an SWI instruction, which
7363 * qemu/linux seems to convert to a SIGILL.
7365 *(int*)code = (0xef << 24) | 8;
7367 mono_arch_flush_icache (code - 4, 4);
7373 * mono_arch_clear_breakpoint:
7375 * Clear the breakpoint at IP.
7378 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7380 MonoDebugOptions *opt = mini_get_debug_options ();
7384 if (opt->soft_breakpoints) {
7385 g_assert (!ji->from_aot);
7388 mono_arch_flush_icache (code - 4, 4);
7389 } else if (ji->from_aot) {
7390 guint32 native_offset = ip - (guint8*)ji->code_start;
7391 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7393 g_assert (native_offset % 4 == 0);
7394 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7395 info->bp_addrs [native_offset / 4] = 0;
7397 for (i = 0; i < 4; ++i)
7400 mono_arch_flush_icache (ip, code - ip);
7405 * mono_arch_start_single_stepping:
7407 * Start single stepping.
7410 mono_arch_start_single_stepping (void)
7412 if (ss_trigger_page)
7413 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7415 single_step_tramp = mini_get_single_step_trampoline ();
7419 * mono_arch_stop_single_stepping:
7421 * Stop single stepping.
7424 mono_arch_stop_single_stepping (void)
7426 if (ss_trigger_page)
7427 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7429 single_step_tramp = NULL;
7433 #define DBG_SIGNAL SIGBUS
7435 #define DBG_SIGNAL SIGSEGV
7439 * mono_arch_is_single_step_event:
7441 * Return whenever the machine state in SIGCTX corresponds to a single
7445 mono_arch_is_single_step_event (void *info, void *sigctx)
7447 siginfo_t *sinfo = info;
7449 if (!ss_trigger_page)
7452 /* Sometimes the address is off by 4 */
7453 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7460 * mono_arch_is_breakpoint_event:
7462 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7465 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7467 siginfo_t *sinfo = info;
7469 if (!ss_trigger_page)
7472 if (sinfo->si_signo == DBG_SIGNAL) {
7473 /* Sometimes the address is off by 4 */
7474 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7484 * mono_arch_skip_breakpoint:
7486 * See mini-amd64.c for docs.
7489 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7491 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7495 * mono_arch_skip_single_step:
7497 * See mini-amd64.c for docs.
7500 mono_arch_skip_single_step (MonoContext *ctx)
7502 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7505 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7508 * mono_arch_get_seq_point_info:
7510 * See mini-amd64.c for docs.
7513 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7518 // FIXME: Add a free function
7520 mono_domain_lock (domain);
7521 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7523 mono_domain_unlock (domain);
7526 ji = mono_jit_info_table_find (domain, (char*)code);
7529 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7531 info->ss_trigger_page = ss_trigger_page;
7532 info->bp_trigger_page = bp_trigger_page;
7534 mono_domain_lock (domain);
7535 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7537 mono_domain_unlock (domain);
7544 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7546 ext->lmf.previous_lmf = prev_lmf;
7547 /* Mark that this is a MonoLMFExt */
7548 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7549 ext->lmf.sp = (gssize)ext;
7553 * mono_arch_set_target:
7555 * Set the target architecture the JIT backend should generate code for, in the form
7556 * of a GNU target triplet. Only used in AOT mode.
7559 mono_arch_set_target (char *mtriple)
7561 /* The GNU target triple format is not very well documented */
7562 if (strstr (mtriple, "armv7")) {
7563 v5_supported = TRUE;
7564 v6_supported = TRUE;
7565 v7_supported = TRUE;
7567 if (strstr (mtriple, "armv6")) {
7568 v5_supported = TRUE;
7569 v6_supported = TRUE;
7571 if (strstr (mtriple, "armv7s")) {
7572 v7s_supported = TRUE;
7574 if (strstr (mtriple, "armv7k")) {
7575 v7k_supported = TRUE;
7577 if (strstr (mtriple, "thumbv7s")) {
7578 v5_supported = TRUE;
7579 v6_supported = TRUE;
7580 v7_supported = TRUE;
7581 v7s_supported = TRUE;
7582 thumb_supported = TRUE;
7583 thumb2_supported = TRUE;
7585 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7586 v5_supported = TRUE;
7587 v6_supported = TRUE;
7588 thumb_supported = TRUE;
7591 if (strstr (mtriple, "gnueabi"))
7592 eabi_supported = TRUE;
7596 mono_arch_opcode_supported (int opcode)
7599 case OP_ATOMIC_ADD_I4:
7600 case OP_ATOMIC_EXCHANGE_I4:
7601 case OP_ATOMIC_CAS_I4:
7602 case OP_ATOMIC_LOAD_I1:
7603 case OP_ATOMIC_LOAD_I2:
7604 case OP_ATOMIC_LOAD_I4:
7605 case OP_ATOMIC_LOAD_U1:
7606 case OP_ATOMIC_LOAD_U2:
7607 case OP_ATOMIC_LOAD_U4:
7608 case OP_ATOMIC_STORE_I1:
7609 case OP_ATOMIC_STORE_I2:
7610 case OP_ATOMIC_STORE_I4:
7611 case OP_ATOMIC_STORE_U1:
7612 case OP_ATOMIC_STORE_U2:
7613 case OP_ATOMIC_STORE_U4:
7614 return v7_supported;
7615 case OP_ATOMIC_LOAD_R4:
7616 case OP_ATOMIC_LOAD_R8:
7617 case OP_ATOMIC_STORE_R4:
7618 case OP_ATOMIC_STORE_R8:
7619 return v7_supported && IS_VFP;
7626 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7628 return get_call_info (mp, sig);