2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/appdomain.h>
16 #include <mono/metadata/debug-helpers.h>
17 #include <mono/utils/mono-mmap.h>
23 #include "debugger-agent.h"
25 #include "mono/arch/arm/arm-fpa-codegen.h"
26 #include "mono/arch/arm/arm-vfp-codegen.h"
28 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
29 #define HAVE_AEABI_READ_TP 1
32 #ifdef ARM_FPU_VFP_HARD
48 #ifdef MONO_ARCH_SOFT_FLOAT
49 #define IS_SOFT_FLOAT 1
51 #define IS_SOFT_FLOAT 0
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
56 static gint lmf_tls_offset = -1;
57 static gint lmf_addr_tls_offset = -1;
59 /* This mutex protects architecture specific caches */
60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
62 static CRITICAL_SECTION mini_arch_mutex;
64 static int v5_supported = 0;
65 static int v6_supported = 0;
66 static int v7_supported = 0;
67 static int thumb_supported = 0;
69 * Whenever to use the ARM EABI
71 static int eabi_supported = 0;
74 * Whenever we are on arm/darwin aka the iphone.
76 static int darwin = 0;
78 * Whenever to use the iphone ABI extensions:
79 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
80 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
81 * This is required for debugging/profiling tools to work, but it has some overhead so it should
82 * only be turned on in debug builds.
84 static int iphone_abi = 0;
87 * The FPU we are generating code for. This is NOT runtime configurable right now,
88 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
90 static MonoArmFPU arm_fpu;
94 static volatile int ss_trigger_var = 0;
96 static gpointer single_step_func_wrapper;
97 static gpointer breakpoint_func_wrapper;
100 * The code generated for sequence points reads from this location, which is
101 * made read-only when single stepping is enabled.
103 static gpointer ss_trigger_page;
105 /* Enabled breakpoints read from this trigger page */
106 static gpointer bp_trigger_page;
108 /* Structure used by the sequence points in AOTed code */
110 gpointer ss_trigger_page;
111 gpointer bp_trigger_page;
112 guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
117 * floating point support: on ARM it is a mess, there are at least 3
118 * different setups, each of which binary incompat with the other.
119 * 1) FPA: old and ugly, but unfortunately what current distros use
120 * the double binary format has the two words swapped. 8 double registers.
121 * Implemented usually by kernel emulation.
122 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
123 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
124 * 3) VFP: the new and actually sensible and useful FP support. Implemented
125 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
127 * The plan is to write the FPA support first. softfloat can be tested in a chroot.
129 int mono_exc_esp_offset = 0;
131 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
132 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
133 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
135 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
136 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
137 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
139 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
140 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) | (ARMREG_LR << 12) | ARMREG_PC)
143 /* A variant of ARM_LDR_IMM which can handle large offsets */
144 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
145 if (arm_is_imm12 ((offset))) { \
146 ARM_LDR_IMM (code, (dreg), (basereg), (offset)); \
148 g_assert ((scratch_reg) != (basereg)); \
149 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
150 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
154 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
155 if (arm_is_imm12 ((offset))) { \
156 ARM_STR_IMM (code, (dreg), (basereg), (offset)); \
158 g_assert ((scratch_reg) != (basereg)); \
159 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
160 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
164 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
167 mono_arch_regname (int reg)
169 static const char * rnames[] = {
170 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
171 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
172 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
175 if (reg >= 0 && reg < 16)
181 mono_arch_fregname (int reg)
183 static const char * rnames[] = {
184 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
185 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
186 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
187 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
188 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
189 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
192 if (reg >= 0 && reg < 32)
200 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
202 int imm8, rot_amount;
203 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
204 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
207 g_assert (dreg != sreg);
208 code = mono_arm_emit_load_imm (code, dreg, imm);
209 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
214 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
216 /* we can use r0-r3, since this is called only for incoming args on the stack */
217 if (size > sizeof (gpointer) * 4) {
219 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
220 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
221 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
222 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
223 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
224 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
225 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
226 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
227 ARM_B_COND (code, ARMCOND_NE, 0);
228 arm_patch (code - 4, start_loop);
231 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
232 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
234 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
235 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
241 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
242 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
243 doffset = soffset = 0;
245 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
246 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
252 g_assert (size == 0);
257 emit_call_reg (guint8 *code, int reg)
260 ARM_BLX_REG (code, reg);
262 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
266 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
272 emit_call_seq (MonoCompile *cfg, guint8 *code)
274 if (cfg->method->dynamic) {
275 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
277 *(gpointer*)code = NULL;
279 code = emit_call_reg (code, ARMREG_IP);
287 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
289 switch (ins->opcode) {
292 case OP_FCALL_MEMBASE:
294 if (ins->dreg != ARM_FPA_F0)
295 ARM_FPA_MVFD (code, ins->dreg, ARM_FPA_F0);
297 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
298 ARM_FMSR (code, ins->dreg, ARMREG_R0);
299 ARM_CVTS (code, ins->dreg, ins->dreg);
301 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
313 * Emit code to push an LMF structure on the LMF stack.
314 * On arm, this is intermixed with the initialization of other fields of the structure.
317 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
319 gboolean get_lmf_fast = FALSE;
322 #ifdef HAVE_AEABI_READ_TP
323 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
325 if (lmf_addr_tls_offset != -1) {
328 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
329 (gpointer)"__aeabi_read_tp");
330 code = emit_call_seq (cfg, code);
332 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
337 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
338 (gpointer)"mono_get_lmf_addr");
339 code = emit_call_seq (cfg, code);
341 /* we build the MonoLMF structure on the stack - see mini-arm.h */
342 /* lmf_offset is the offset from the previous stack pointer,
343 * alloc_size is the total stack space allocated, so the offset
344 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
345 * The pointer to the struct is put in r1 (new_lmf).
346 * ip is used as scratch
347 * The callee-saved registers are already in the MonoLMF structure
349 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
350 /* r0 is the result from mono_get_lmf_addr () */
351 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
352 /* new_lmf->previous_lmf = *lmf_addr */
353 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
354 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
355 /* *(lmf_addr) = r1 */
356 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
357 /* Skip method (only needed for trampoline LMF frames) */
358 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, sp));
359 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, fp));
360 /* save the current IP */
361 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
362 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ip));
364 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
365 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
373 * Emit code to pop an LMF structure from the LMF stack.
376 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
380 if (lmf_offset < 32) {
381 basereg = cfg->frame_reg;
386 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
389 /* ip = previous_lmf */
390 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
392 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
393 /* *(lmf_addr) = previous_lmf */
394 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
399 #endif /* #ifndef DISABLE_JIT */
402 * mono_arch_get_argument_info:
403 * @csig: a method signature
404 * @param_count: the number of parameters to consider
405 * @arg_info: an array to store the result infos
407 * Gathers information on parameters such as size, alignment and
408 * padding. arg_info should be large enought to hold param_count + 1 entries.
410 * Returns the size of the activation frame.
413 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
415 int k, frame_size = 0;
416 guint32 size, align, pad;
419 if (MONO_TYPE_ISSTRUCT (csig->ret)) {
420 frame_size += sizeof (gpointer);
424 arg_info [0].offset = offset;
427 frame_size += sizeof (gpointer);
431 arg_info [0].size = frame_size;
433 for (k = 0; k < param_count; k++) {
434 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
436 /* ignore alignment for now */
439 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
440 arg_info [k].pad = pad;
442 arg_info [k + 1].pad = 0;
443 arg_info [k + 1].size = size;
445 arg_info [k + 1].offset = offset;
449 align = MONO_ARCH_FRAME_ALIGNMENT;
450 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
451 arg_info [k].pad = pad;
456 #define MAX_ARCH_DELEGATE_PARAMS 3
459 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
461 guint8 *code, *start;
464 start = code = mono_global_codeman_reserve (12);
466 /* Replace the this argument with the target */
467 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
468 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
469 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
471 g_assert ((code - start) <= 12);
473 mono_arch_flush_icache (start, 12);
477 size = 8 + param_count * 4;
478 start = code = mono_global_codeman_reserve (size);
480 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
481 /* slide down the arguments */
482 for (i = 0; i < param_count; ++i) {
483 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
485 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
487 g_assert ((code - start) <= size);
489 mono_arch_flush_icache (start, size);
493 *code_size = code - start;
499 * mono_arch_get_delegate_invoke_impls:
501 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
505 mono_arch_get_delegate_invoke_impls (void)
512 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
513 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
515 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
516 code = get_delegate_invoke_impl (FALSE, i, &code_len);
517 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
524 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
526 guint8 *code, *start;
528 /* FIXME: Support more cases */
529 if (MONO_TYPE_ISSTRUCT (sig->ret))
533 static guint8* cached = NULL;
534 mono_mini_arch_lock ();
536 mono_mini_arch_unlock ();
541 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
543 start = get_delegate_invoke_impl (TRUE, 0, NULL);
545 mono_mini_arch_unlock ();
548 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
551 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
553 for (i = 0; i < sig->param_count; ++i)
554 if (!mono_is_regsize_var (sig->params [i]))
557 mono_mini_arch_lock ();
558 code = cache [sig->param_count];
560 mono_mini_arch_unlock ();
565 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
566 start = mono_aot_get_trampoline (name);
569 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
571 cache [sig->param_count] = start;
572 mono_mini_arch_unlock ();
580 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
582 return (gpointer)regs [ARMREG_R0];
586 * Initialize the cpu to execute managed code.
589 mono_arch_cpu_init (void)
591 #if defined(__ARM_EABI__)
592 eabi_supported = TRUE;
594 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
597 i8_align = __alignof__ (gint64);
602 create_function_wrapper (gpointer function)
604 guint8 *start, *code;
606 start = code = mono_global_codeman_reserve (96);
609 * Construct the MonoContext structure on the stack.
612 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, sizeof (MonoContext));
614 /* save ip, lr and pc into their correspodings ctx.regs slots. */
615 ARM_STR_IMM (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + sizeof (mgreg_t) * ARMREG_IP);
616 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
617 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
619 /* save r0..r10 and fp */
620 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs));
621 ARM_STM (code, ARMREG_IP, 0x0fff);
623 /* now we can update fp. */
624 ARM_MOV_REG_REG (code, ARMREG_FP, ARMREG_SP);
626 /* make ctx.esp hold the actual value of sp at the beginning of this method. */
627 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_FP, sizeof (MonoContext));
628 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, 4 * ARMREG_SP);
629 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_SP);
631 /* make ctx.eip hold the address of the call. */
632 ARM_SUB_REG_IMM8 (code, ARMREG_LR, ARMREG_LR, 4);
633 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, pc));
635 /* r0 now points to the MonoContext */
636 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_FP);
639 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
641 *(gpointer*)code = function;
643 ARM_BLX_REG (code, ARMREG_IP);
645 /* we're back; save ctx.eip and ctx.esp into the corresponding regs slots. */
646 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, pc));
647 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
648 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
650 /* make ip point to the regs array, then restore everything, including pc. */
651 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs));
652 ARM_LDM (code, ARMREG_IP, 0xffff);
654 mono_arch_flush_icache (start, code - start);
660 * Initialize architecture specific code.
663 mono_arch_init (void)
665 InitializeCriticalSection (&mini_arch_mutex);
667 if (mini_get_debug_options ()->soft_breakpoints) {
668 single_step_func_wrapper = create_function_wrapper (debugger_agent_single_step_from_context);
669 breakpoint_func_wrapper = create_function_wrapper (debugger_agent_breakpoint_from_context);
671 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
672 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
673 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
676 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
677 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
678 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
681 arm_fpu = MONO_ARM_FPU_FPA;
682 #elif defined(ARM_FPU_VFP_HARD)
683 arm_fpu = MONO_ARM_FPU_VFP_HARD;
684 #elif defined(ARM_FPU_VFP)
685 arm_fpu = MONO_ARM_FPU_VFP;
687 arm_fpu = MONO_ARM_FPU_NONE;
692 * Cleanup architecture specific code.
695 mono_arch_cleanup (void)
700 * This function returns the optimizations supported on this cpu.
703 mono_arch_cpu_optimizations (guint32 *exclude_mask)
706 const char *cpu_arch = getenv ("MONO_CPU_ARCH");
707 if (cpu_arch != NULL) {
708 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
709 if (strncmp (cpu_arch, "armv", 4) == 0) {
710 v5_supported = cpu_arch [4] >= '5';
711 v6_supported = cpu_arch [4] >= '6';
712 v7_supported = cpu_arch [4] >= '7';
716 thumb_supported = TRUE;
723 FILE *file = fopen ("/proc/cpuinfo", "r");
725 while ((line = fgets (buf, 512, file))) {
726 if (strncmp (line, "Processor", 9) == 0) {
727 char *ver = strstr (line, "(v");
728 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
730 if (ver && (ver [2] == '6' || ver [2] == '7'))
732 if (ver && (ver [2] == '7'))
736 if (strncmp (line, "Features", 8) == 0) {
737 char *th = strstr (line, "thumb");
739 thumb_supported = TRUE;
747 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
752 /* no arm-specific optimizations yet */
758 * This function test for all SIMD functions supported.
760 * Returns a bitmask corresponding to all supported versions.
764 mono_arch_cpu_enumerate_simd_versions (void)
766 /* SIMD is currently unimplemented */
774 is_regsize_var (MonoType *t) {
777 t = mini_type_get_underlying_type (NULL, t);
784 case MONO_TYPE_FNPTR:
786 case MONO_TYPE_OBJECT:
787 case MONO_TYPE_STRING:
788 case MONO_TYPE_CLASS:
789 case MONO_TYPE_SZARRAY:
790 case MONO_TYPE_ARRAY:
792 case MONO_TYPE_GENERICINST:
793 if (!mono_type_generic_inst_is_valuetype (t))
796 case MONO_TYPE_VALUETYPE:
803 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
808 for (i = 0; i < cfg->num_varinfo; i++) {
809 MonoInst *ins = cfg->varinfo [i];
810 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
813 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
816 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
819 /* we can only allocate 32 bit values */
820 if (is_regsize_var (ins->inst_vtype)) {
821 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
822 g_assert (i == vmv->idx);
823 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
830 #define USE_EXTRA_TEMPS 0
833 mono_arch_get_global_int_regs (MonoCompile *cfg)
837 mono_arch_compute_omit_fp (cfg);
840 * FIXME: Interface calls might go through a static rgctx trampoline which
841 * sets V5, but it doesn't save it, so we need to save it ourselves, and
844 if (cfg->flags & MONO_CFG_HAS_CALLS)
845 cfg->uses_rgctx_reg = TRUE;
847 if (cfg->arch.omit_fp)
848 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
849 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
850 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
851 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
853 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
854 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
856 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
857 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
858 /* V5 is reserved for passing the vtable/rgctx/IMT method */
859 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
860 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
861 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
867 * mono_arch_regalloc_cost:
869 * Return the cost, in number of memory references, of the action of
870 * allocating the variable VMV into a register during global register
874 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
880 #endif /* #ifndef DISABLE_JIT */
882 #ifndef __GNUC_PREREQ
883 #define __GNUC_PREREQ(maj, min) (0)
887 mono_arch_flush_icache (guint8 *code, gint size)
890 sys_icache_invalidate (code, size);
891 #elif __GNUC_PREREQ(4, 1)
892 __clear_cache (code, code + size);
893 #elif defined(PLATFORM_ANDROID)
894 const int syscall = 0xf0002;
902 : "r" (code), "r" (code + size), "r" (syscall)
903 : "r0", "r1", "r7", "r2"
906 __asm __volatile ("mov r0, %0\n"
909 "swi 0x9f0002 @ sys_cacheflush"
911 : "r" (code), "r" (code + size), "r" (0)
912 : "r0", "r1", "r3" );
929 guint16 vtsize; /* in param area */
933 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
939 gboolean vtype_retaddr;
940 /* The index of the vret arg in the argument list */
950 /*#define __alignof__(a) sizeof(a)*/
951 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
957 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
960 if (*gr > ARMREG_R3) {
961 ainfo->offset = *stack_size;
962 ainfo->reg = ARMREG_SP; /* in the caller */
963 ainfo->storage = RegTypeBase;
966 ainfo->storage = RegTypeGeneral;
973 split = i8_align == 4;
977 if (*gr == ARMREG_R3 && split) {
978 /* first word in r3 and the second on the stack */
979 ainfo->offset = *stack_size;
980 ainfo->reg = ARMREG_SP; /* in the caller */
981 ainfo->storage = RegTypeBaseGen;
983 } else if (*gr >= ARMREG_R3) {
984 if (eabi_supported) {
985 /* darwin aligns longs to 4 byte only */
991 ainfo->offset = *stack_size;
992 ainfo->reg = ARMREG_SP; /* in the caller */
993 ainfo->storage = RegTypeBase;
996 if (eabi_supported) {
997 if (i8_align == 8 && ((*gr) & 1))
1000 ainfo->storage = RegTypeIRegPair;
1009 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
1011 guint i, gr, pstart;
1012 int n = sig->hasthis + sig->param_count;
1013 MonoType *simpletype;
1014 guint32 stack_size = 0;
1016 gboolean is_pinvoke = sig->pinvoke;
1019 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1021 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1026 /* FIXME: handle returning a struct */
1027 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1030 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (sig->ret), &align) <= sizeof (gpointer)) {
1031 cinfo->ret.storage = RegTypeStructByVal;
1033 cinfo->vtype_retaddr = TRUE;
1040 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1041 * the first argument, allowing 'this' to be always passed in the first arg reg.
1042 * Also do this if the first argument is a reference type, since virtual calls
1043 * are sometimes made using calli without sig->hasthis set, like in the delegate
1046 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1048 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1050 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1054 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1055 cinfo->vret_arg_index = 1;
1059 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1063 if (cinfo->vtype_retaddr)
1064 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1067 DEBUG(printf("params: %d\n", sig->param_count));
1068 for (i = pstart; i < sig->param_count; ++i) {
1069 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1070 /* Prevent implicit arguments and sig_cookie from
1071 being passed in registers */
1073 /* Emit the signature cookie just before the implicit arguments */
1074 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1076 DEBUG(printf("param %d: ", i));
1077 if (sig->params [i]->byref) {
1078 DEBUG(printf("byref\n"));
1079 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1083 simpletype = mini_type_get_underlying_type (NULL, sig->params [i]);
1084 switch (simpletype->type) {
1085 case MONO_TYPE_BOOLEAN:
1088 cinfo->args [n].size = 1;
1089 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1092 case MONO_TYPE_CHAR:
1095 cinfo->args [n].size = 2;
1096 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1101 cinfo->args [n].size = 4;
1102 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1108 case MONO_TYPE_FNPTR:
1109 case MONO_TYPE_CLASS:
1110 case MONO_TYPE_OBJECT:
1111 case MONO_TYPE_STRING:
1112 case MONO_TYPE_SZARRAY:
1113 case MONO_TYPE_ARRAY:
1115 cinfo->args [n].size = sizeof (gpointer);
1116 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1119 case MONO_TYPE_GENERICINST:
1120 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1121 cinfo->args [n].size = sizeof (gpointer);
1122 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1127 case MONO_TYPE_TYPEDBYREF:
1128 case MONO_TYPE_VALUETYPE: {
1134 if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1135 size = sizeof (MonoTypedRef);
1136 align = sizeof (gpointer);
1138 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1140 size = mono_class_native_size (klass, &align);
1142 size = mono_class_value_size (klass, &align);
1144 DEBUG(printf ("load %d bytes struct\n",
1145 mono_class_native_size (sig->params [i]->data.klass, NULL)));
1148 align_size += (sizeof (gpointer) - 1);
1149 align_size &= ~(sizeof (gpointer) - 1);
1150 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1151 cinfo->args [n].storage = RegTypeStructByVal;
1152 cinfo->args [n].struct_size = size;
1153 /* FIXME: align stack_size if needed */
1154 if (eabi_supported) {
1155 if (align >= 8 && (gr & 1))
1158 if (gr > ARMREG_R3) {
1159 cinfo->args [n].size = 0;
1160 cinfo->args [n].vtsize = nwords;
1162 int rest = ARMREG_R3 - gr + 1;
1163 int n_in_regs = rest >= nwords? nwords: rest;
1165 cinfo->args [n].size = n_in_regs;
1166 cinfo->args [n].vtsize = nwords - n_in_regs;
1167 cinfo->args [n].reg = gr;
1169 nwords -= n_in_regs;
1171 cinfo->args [n].offset = stack_size;
1172 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1173 stack_size += nwords * sizeof (gpointer);
1180 cinfo->args [n].size = 8;
1181 add_general (&gr, &stack_size, cinfo->args + n, FALSE);
1185 g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1189 /* Handle the case where there are no implicit arguments */
1190 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1191 /* Prevent implicit arguments and sig_cookie from
1192 being passed in registers */
1194 /* Emit the signature cookie just before the implicit arguments */
1195 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1199 simpletype = mini_type_get_underlying_type (NULL, sig->ret);
1200 switch (simpletype->type) {
1201 case MONO_TYPE_BOOLEAN:
1206 case MONO_TYPE_CHAR:
1212 case MONO_TYPE_FNPTR:
1213 case MONO_TYPE_CLASS:
1214 case MONO_TYPE_OBJECT:
1215 case MONO_TYPE_SZARRAY:
1216 case MONO_TYPE_ARRAY:
1217 case MONO_TYPE_STRING:
1218 cinfo->ret.storage = RegTypeGeneral;
1219 cinfo->ret.reg = ARMREG_R0;
1223 cinfo->ret.storage = RegTypeIRegPair;
1224 cinfo->ret.reg = ARMREG_R0;
1228 cinfo->ret.storage = RegTypeFP;
1229 cinfo->ret.reg = ARMREG_R0;
1230 /* FIXME: cinfo->ret.reg = ???;
1231 cinfo->ret.storage = RegTypeFP;*/
1233 case MONO_TYPE_GENERICINST:
1234 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1235 cinfo->ret.storage = RegTypeGeneral;
1236 cinfo->ret.reg = ARMREG_R0;
1240 case MONO_TYPE_VALUETYPE:
1241 case MONO_TYPE_TYPEDBYREF:
1242 if (cinfo->ret.storage != RegTypeStructByVal)
1243 cinfo->ret.storage = RegTypeStructByAddr;
1245 case MONO_TYPE_VOID:
1248 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1252 /* align stack size to 8 */
1253 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1254 stack_size = (stack_size + 7) & ~7;
1256 cinfo->stack_usage = stack_size;
1262 G_GNUC_UNUSED static void
1267 G_GNUC_UNUSED static gboolean
1270 static int count = 0;
1273 if (!getenv ("COUNT"))
1276 if (count == atoi (getenv ("COUNT"))) {
1280 if (count > atoi (getenv ("COUNT"))) {
1288 debug_omit_fp (void)
1291 return debug_count ();
1298 * mono_arch_compute_omit_fp:
1300 * Determine whenever the frame pointer can be eliminated.
1303 mono_arch_compute_omit_fp (MonoCompile *cfg)
1305 MonoMethodSignature *sig;
1306 MonoMethodHeader *header;
1310 if (cfg->arch.omit_fp_computed)
1313 header = cfg->header;
1315 sig = mono_method_signature (cfg->method);
1317 if (!cfg->arch.cinfo)
1318 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1319 cinfo = cfg->arch.cinfo;
1322 * FIXME: Remove some of the restrictions.
1324 cfg->arch.omit_fp = TRUE;
1325 cfg->arch.omit_fp_computed = TRUE;
1327 if (cfg->disable_omit_fp)
1328 cfg->arch.omit_fp = FALSE;
1329 if (!debug_omit_fp ())
1330 cfg->arch.omit_fp = FALSE;
1332 if (cfg->method->save_lmf)
1333 cfg->arch.omit_fp = FALSE;
1335 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1336 cfg->arch.omit_fp = FALSE;
1337 if (header->num_clauses)
1338 cfg->arch.omit_fp = FALSE;
1339 if (cfg->param_area)
1340 cfg->arch.omit_fp = FALSE;
1341 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1342 cfg->arch.omit_fp = FALSE;
1343 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1344 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1345 cfg->arch.omit_fp = FALSE;
1346 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1347 ArgInfo *ainfo = &cinfo->args [i];
1349 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1351 * The stack offset can only be determined when the frame
1354 cfg->arch.omit_fp = FALSE;
1359 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1360 MonoInst *ins = cfg->varinfo [i];
1363 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1368 * Set var information according to the calling convention. arm version.
1369 * The locals var stuff should most likely be split in another method.
1372 mono_arch_allocate_vars (MonoCompile *cfg)
1374 MonoMethodSignature *sig;
1375 MonoMethodHeader *header;
1377 int i, offset, size, align, curinst;
1381 sig = mono_method_signature (cfg->method);
1383 if (!cfg->arch.cinfo)
1384 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1385 cinfo = cfg->arch.cinfo;
1387 mono_arch_compute_omit_fp (cfg);
1389 if (cfg->arch.omit_fp)
1390 cfg->frame_reg = ARMREG_SP;
1392 cfg->frame_reg = ARMREG_FP;
1394 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1396 /* allow room for the vararg method args: void* and long/double */
1397 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1398 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1400 header = cfg->header;
1402 /* See mono_arch_get_global_int_regs () */
1403 if (cfg->flags & MONO_CFG_HAS_CALLS)
1404 cfg->uses_rgctx_reg = TRUE;
1406 if (cfg->frame_reg != ARMREG_SP)
1407 cfg->used_int_regs |= 1 << cfg->frame_reg;
1409 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1410 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1411 cfg->used_int_regs |= (1 << ARMREG_V5);
1415 if (!MONO_TYPE_ISSTRUCT (sig->ret)) {
1416 switch (mini_type_get_underlying_type (NULL, sig->ret)->type) {
1417 case MONO_TYPE_VOID:
1420 cfg->ret->opcode = OP_REGVAR;
1421 cfg->ret->inst_c0 = ARMREG_R0;
1425 /* local vars are at a positive offset from the stack pointer */
1427 * also note that if the function uses alloca, we use FP
1428 * to point at the local variables.
1430 offset = 0; /* linkage area */
1431 /* align the offset to 16 bytes: not sure this is needed here */
1433 //offset &= ~(8 - 1);
1435 /* add parameter area size for called functions */
1436 offset += cfg->param_area;
1439 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1442 /* allow room to save the return value */
1443 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1446 /* the MonoLMF structure is stored just below the stack pointer */
1447 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1448 if (cinfo->ret.storage == RegTypeStructByVal) {
1449 cfg->ret->opcode = OP_REGOFFSET;
1450 cfg->ret->inst_basereg = cfg->frame_reg;
1451 offset += sizeof (gpointer) - 1;
1452 offset &= ~(sizeof (gpointer) - 1);
1453 cfg->ret->inst_offset = - offset;
1455 ins = cfg->vret_addr;
1456 offset += sizeof(gpointer) - 1;
1457 offset &= ~(sizeof(gpointer) - 1);
1458 ins->inst_offset = offset;
1459 ins->opcode = OP_REGOFFSET;
1460 ins->inst_basereg = cfg->frame_reg;
1461 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1462 printf ("vret_addr =");
1463 mono_print_ins (cfg->vret_addr);
1466 offset += sizeof(gpointer);
1469 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1470 if (cfg->arch.seq_point_info_var) {
1473 ins = cfg->arch.seq_point_info_var;
1477 offset += align - 1;
1478 offset &= ~(align - 1);
1479 ins->opcode = OP_REGOFFSET;
1480 ins->inst_basereg = cfg->frame_reg;
1481 ins->inst_offset = offset;
1484 ins = cfg->arch.ss_trigger_page_var;
1487 offset += align - 1;
1488 offset &= ~(align - 1);
1489 ins->opcode = OP_REGOFFSET;
1490 ins->inst_basereg = cfg->frame_reg;
1491 ins->inst_offset = offset;
1495 if (cfg->arch.seq_point_read_var) {
1498 ins = cfg->arch.seq_point_read_var;
1502 offset += align - 1;
1503 offset &= ~(align - 1);
1504 ins->opcode = OP_REGOFFSET;
1505 ins->inst_basereg = cfg->frame_reg;
1506 ins->inst_offset = offset;
1509 ins = cfg->arch.seq_point_ss_method_var;
1512 offset += align - 1;
1513 offset &= ~(align - 1);
1514 ins->opcode = OP_REGOFFSET;
1515 ins->inst_basereg = cfg->frame_reg;
1516 ins->inst_offset = offset;
1519 ins = cfg->arch.seq_point_bp_method_var;
1522 offset += align - 1;
1523 offset &= ~(align - 1);
1524 ins->opcode = OP_REGOFFSET;
1525 ins->inst_basereg = cfg->frame_reg;
1526 ins->inst_offset = offset;
1530 cfg->locals_min_stack_offset = offset;
1532 curinst = cfg->locals_start;
1533 for (i = curinst; i < cfg->num_varinfo; ++i) {
1534 ins = cfg->varinfo [i];
1535 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1538 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1539 * pinvoke wrappers when they call functions returning structure */
1540 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (ins->inst_vtype) && ins->inst_vtype->type != MONO_TYPE_TYPEDBYREF) {
1541 size = mono_class_native_size (mono_class_from_mono_type (ins->inst_vtype), &ualign);
1545 size = mono_type_size (ins->inst_vtype, &align);
1547 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1548 * since it loads/stores misaligned words, which don't do the right thing.
1550 if (align < 4 && size >= 4)
1552 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1553 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1554 offset += align - 1;
1555 offset &= ~(align - 1);
1556 ins->opcode = OP_REGOFFSET;
1557 ins->inst_offset = offset;
1558 ins->inst_basereg = cfg->frame_reg;
1560 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1563 cfg->locals_max_stack_offset = offset;
1567 ins = cfg->args [curinst];
1568 if (ins->opcode != OP_REGVAR) {
1569 ins->opcode = OP_REGOFFSET;
1570 ins->inst_basereg = cfg->frame_reg;
1571 offset += sizeof (gpointer) - 1;
1572 offset &= ~(sizeof (gpointer) - 1);
1573 ins->inst_offset = offset;
1574 offset += sizeof (gpointer);
1579 if (sig->call_convention == MONO_CALL_VARARG) {
1583 /* Allocate a local slot to hold the sig cookie address */
1584 offset += align - 1;
1585 offset &= ~(align - 1);
1586 cfg->sig_cookie = offset;
1590 for (i = 0; i < sig->param_count; ++i) {
1591 ins = cfg->args [curinst];
1593 if (ins->opcode != OP_REGVAR) {
1594 ins->opcode = OP_REGOFFSET;
1595 ins->inst_basereg = cfg->frame_reg;
1596 size = mini_type_stack_size_full (NULL, sig->params [i], &ualign, sig->pinvoke);
1598 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1599 * since it loads/stores misaligned words, which don't do the right thing.
1601 if (align < 4 && size >= 4)
1603 /* The code in the prolog () stores words when storing vtypes received in a register */
1604 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1606 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1607 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1608 offset += align - 1;
1609 offset &= ~(align - 1);
1610 ins->inst_offset = offset;
1616 /* align the offset to 8 bytes */
1617 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
1618 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1623 cfg->stack_offset = offset;
1627 mono_arch_create_vars (MonoCompile *cfg)
1629 MonoMethodSignature *sig;
1632 sig = mono_method_signature (cfg->method);
1634 if (!cfg->arch.cinfo)
1635 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1636 cinfo = cfg->arch.cinfo;
1638 if (cinfo->ret.storage == RegTypeStructByVal)
1639 cfg->ret_var_is_local = TRUE;
1641 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
1642 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1643 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1644 printf ("vret_addr = ");
1645 mono_print_ins (cfg->vret_addr);
1649 if (cfg->gen_seq_points) {
1650 if (cfg->soft_breakpoints) {
1651 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1652 ins->flags |= MONO_INST_VOLATILE;
1653 cfg->arch.seq_point_read_var = ins;
1655 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1656 ins->flags |= MONO_INST_VOLATILE;
1657 cfg->arch.seq_point_ss_method_var = ins;
1659 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1660 ins->flags |= MONO_INST_VOLATILE;
1661 cfg->arch.seq_point_bp_method_var = ins;
1663 g_assert (!cfg->compile_aot);
1664 } else if (cfg->compile_aot) {
1665 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1666 ins->flags |= MONO_INST_VOLATILE;
1667 cfg->arch.seq_point_info_var = ins;
1669 /* Allocate a separate variable for this to save 1 load per seq point */
1670 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1671 ins->flags |= MONO_INST_VOLATILE;
1672 cfg->arch.ss_trigger_page_var = ins;
1678 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1680 MonoMethodSignature *tmp_sig;
1683 if (call->tail_call)
1686 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1689 * mono_ArgIterator_Setup assumes the signature cookie is
1690 * passed first and all the arguments which were before it are
1691 * passed on the stack after the signature. So compensate by
1692 * passing a different signature.
1694 tmp_sig = mono_metadata_signature_dup (call->signature);
1695 tmp_sig->param_count -= call->signature->sentinelpos;
1696 tmp_sig->sentinelpos = 0;
1697 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1699 sig_reg = mono_alloc_ireg (cfg);
1700 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1702 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
1707 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1712 LLVMCallInfo *linfo;
1714 n = sig->param_count + sig->hasthis;
1716 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1718 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1721 * LLVM always uses the native ABI while we use our own ABI, the
1722 * only difference is the handling of vtypes:
1723 * - we only pass/receive them in registers in some cases, and only
1724 * in 1 or 2 integer registers.
1726 if (cinfo->vtype_retaddr) {
1727 /* Vtype returned using a hidden argument */
1728 linfo->ret.storage = LLVMArgVtypeRetAddr;
1729 linfo->vret_arg_index = cinfo->vret_arg_index;
1730 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1731 cfg->exception_message = g_strdup ("unknown ret conv");
1732 cfg->disable_llvm = TRUE;
1736 for (i = 0; i < n; ++i) {
1737 ainfo = cinfo->args + i;
1739 linfo->args [i].storage = LLVMArgNone;
1741 switch (ainfo->storage) {
1742 case RegTypeGeneral:
1743 case RegTypeIRegPair:
1745 linfo->args [i].storage = LLVMArgInIReg;
1747 case RegTypeStructByVal:
1748 // FIXME: Passing entirely on the stack or split reg/stack
1749 if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1750 linfo->args [i].storage = LLVMArgVtypeInReg;
1751 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1752 if (ainfo->size == 2)
1753 linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1755 linfo->args [i].pair_storage [1] = LLVMArgNone;
1757 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1758 cfg->disable_llvm = TRUE;
1762 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1763 cfg->disable_llvm = TRUE;
1773 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1776 MonoMethodSignature *sig;
1780 sig = call->signature;
1781 n = sig->param_count + sig->hasthis;
1783 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1785 for (i = 0; i < n; ++i) {
1786 ArgInfo *ainfo = cinfo->args + i;
1789 if (i >= sig->hasthis)
1790 t = sig->params [i - sig->hasthis];
1792 t = &mono_defaults.int_class->byval_arg;
1793 t = mini_type_get_underlying_type (NULL, t);
1795 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1796 /* Emit the signature cookie just before the implicit arguments */
1797 emit_sig_cookie (cfg, call, cinfo);
1800 in = call->args [i];
1802 switch (ainfo->storage) {
1803 case RegTypeGeneral:
1804 case RegTypeIRegPair:
1805 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1806 MONO_INST_NEW (cfg, ins, OP_MOVE);
1807 ins->dreg = mono_alloc_ireg (cfg);
1808 ins->sreg1 = in->dreg + 1;
1809 MONO_ADD_INS (cfg->cbb, ins);
1810 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1812 MONO_INST_NEW (cfg, ins, OP_MOVE);
1813 ins->dreg = mono_alloc_ireg (cfg);
1814 ins->sreg1 = in->dreg + 2;
1815 MONO_ADD_INS (cfg->cbb, ins);
1816 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1817 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1818 if (ainfo->size == 4) {
1819 if (IS_SOFT_FLOAT) {
1820 /* mono_emit_call_args () have already done the r8->r4 conversion */
1821 /* The converted value is in an int vreg */
1822 MONO_INST_NEW (cfg, ins, OP_MOVE);
1823 ins->dreg = mono_alloc_ireg (cfg);
1824 ins->sreg1 = in->dreg;
1825 MONO_ADD_INS (cfg->cbb, ins);
1826 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1830 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1831 creg = mono_alloc_ireg (cfg);
1832 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1833 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1836 if (IS_SOFT_FLOAT) {
1837 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1838 ins->dreg = mono_alloc_ireg (cfg);
1839 ins->sreg1 = in->dreg;
1840 MONO_ADD_INS (cfg->cbb, ins);
1841 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1843 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1844 ins->dreg = mono_alloc_ireg (cfg);
1845 ins->sreg1 = in->dreg;
1846 MONO_ADD_INS (cfg->cbb, ins);
1847 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1851 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1852 creg = mono_alloc_ireg (cfg);
1853 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1854 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1855 creg = mono_alloc_ireg (cfg);
1856 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1857 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1860 cfg->flags |= MONO_CFG_HAS_FPOUT;
1862 MONO_INST_NEW (cfg, ins, OP_MOVE);
1863 ins->dreg = mono_alloc_ireg (cfg);
1864 ins->sreg1 = in->dreg;
1865 MONO_ADD_INS (cfg->cbb, ins);
1867 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1870 case RegTypeStructByAddr:
1873 /* FIXME: where si the data allocated? */
1874 arg->backend.reg3 = ainfo->reg;
1875 call->used_iregs |= 1 << ainfo->reg;
1876 g_assert_not_reached ();
1879 case RegTypeStructByVal:
1880 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1881 ins->opcode = OP_OUTARG_VT;
1882 ins->sreg1 = in->dreg;
1883 ins->klass = in->klass;
1884 ins->inst_p0 = call;
1885 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1886 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1887 mono_call_inst_add_outarg_vt (cfg, call, ins);
1888 MONO_ADD_INS (cfg->cbb, ins);
1891 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1892 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1893 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1894 if (t->type == MONO_TYPE_R8) {
1895 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1898 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1900 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1903 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1906 case RegTypeBaseGen:
1907 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1908 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1909 MONO_INST_NEW (cfg, ins, OP_MOVE);
1910 ins->dreg = mono_alloc_ireg (cfg);
1911 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1912 MONO_ADD_INS (cfg->cbb, ins);
1913 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1914 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1917 /* This should work for soft-float as well */
1919 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1920 creg = mono_alloc_ireg (cfg);
1921 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1922 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1923 creg = mono_alloc_ireg (cfg);
1924 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1925 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1926 cfg->flags |= MONO_CFG_HAS_FPOUT;
1928 g_assert_not_reached ();
1935 arg->backend.reg3 = ainfo->reg;
1936 /* FP args are passed in int regs */
1937 call->used_iregs |= 1 << ainfo->reg;
1938 if (ainfo->size == 8) {
1939 arg->opcode = OP_OUTARG_R8;
1940 call->used_iregs |= 1 << (ainfo->reg + 1);
1942 arg->opcode = OP_OUTARG_R4;
1945 cfg->flags |= MONO_CFG_HAS_FPOUT;
1949 g_assert_not_reached ();
1953 /* Handle the case where there are no implicit arguments */
1954 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1955 emit_sig_cookie (cfg, call, cinfo);
1957 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1960 if (cinfo->ret.storage == RegTypeStructByVal) {
1961 /* The JIT will transform this into a normal call */
1962 call->vret_in_reg = TRUE;
1964 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1965 vtarg->sreg1 = call->vret_var->dreg;
1966 vtarg->dreg = mono_alloc_preg (cfg);
1967 MONO_ADD_INS (cfg->cbb, vtarg);
1969 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1973 call->stack_usage = cinfo->stack_usage;
1979 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1981 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1982 ArgInfo *ainfo = ins->inst_p1;
1983 int ovf_size = ainfo->vtsize;
1984 int doffset = ainfo->offset;
1985 int struct_size = ainfo->struct_size;
1986 int i, soffset, dreg, tmpreg;
1989 for (i = 0; i < ainfo->size; ++i) {
1990 dreg = mono_alloc_ireg (cfg);
1991 switch (struct_size) {
1993 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1996 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
1999 tmpreg = mono_alloc_ireg (cfg);
2000 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2001 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2002 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2003 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2004 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2005 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2006 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2009 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2012 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2013 soffset += sizeof (gpointer);
2014 struct_size -= sizeof (gpointer);
2016 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2018 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2022 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2024 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2027 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2030 if (COMPILE_LLVM (cfg)) {
2031 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2033 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2034 ins->sreg1 = val->dreg + 1;
2035 ins->sreg2 = val->dreg + 2;
2036 MONO_ADD_INS (cfg->cbb, ins);
2041 case MONO_ARM_FPU_NONE:
2042 if (ret->type == MONO_TYPE_R8) {
2045 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2046 ins->dreg = cfg->ret->dreg;
2047 ins->sreg1 = val->dreg;
2048 MONO_ADD_INS (cfg->cbb, ins);
2051 if (ret->type == MONO_TYPE_R4) {
2052 /* Already converted to an int in method_to_ir () */
2053 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2057 case MONO_ARM_FPU_VFP:
2058 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2061 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2062 ins->dreg = cfg->ret->dreg;
2063 ins->sreg1 = val->dreg;
2064 MONO_ADD_INS (cfg->cbb, ins);
2068 case MONO_ARM_FPU_FPA:
2069 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
2070 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2075 g_assert_not_reached ();
2079 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2082 #endif /* #ifndef DISABLE_JIT */
2085 mono_arch_is_inst_imm (gint64 imm)
2090 #define DYN_CALL_STACK_ARGS 6
2093 MonoMethodSignature *sig;
2098 mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
2104 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2108 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2111 switch (cinfo->ret.storage) {
2113 case RegTypeGeneral:
2114 case RegTypeIRegPair:
2115 case RegTypeStructByAddr:
2128 for (i = 0; i < cinfo->nargs; ++i) {
2129 switch (cinfo->args [i].storage) {
2130 case RegTypeGeneral:
2132 case RegTypeIRegPair:
2135 if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2138 case RegTypeStructByVal:
2139 if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2147 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2148 for (i = 0; i < sig->param_count; ++i) {
2149 MonoType *t = sig->params [i];
2175 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2177 ArchDynCallInfo *info;
2180 cinfo = get_call_info (NULL, NULL, sig);
2182 if (!dyn_call_supported (cinfo, sig)) {
2187 info = g_new0 (ArchDynCallInfo, 1);
2188 // FIXME: Preprocess the info to speed up start_dyn_call ()
2190 info->cinfo = cinfo;
2192 return (MonoDynCallInfo*)info;
2196 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2198 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2200 g_free (ainfo->cinfo);
2205 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2207 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2208 DynCallArgs *p = (DynCallArgs*)buf;
2209 int arg_index, greg, i, j, pindex;
2210 MonoMethodSignature *sig = dinfo->sig;
2212 g_assert (buf_len >= sizeof (DynCallArgs));
2221 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2222 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2227 if (dinfo->cinfo->vtype_retaddr)
2228 p->regs [greg ++] = (mgreg_t)ret;
2230 for (i = pindex; i < sig->param_count; i++) {
2231 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2232 gpointer *arg = args [arg_index ++];
2233 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2236 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2238 else if (ainfo->storage == RegTypeBase)
2239 slot = PARAM_REGS + (ainfo->offset / 4);
2241 g_assert_not_reached ();
2244 p->regs [slot] = (mgreg_t)*arg;
2249 case MONO_TYPE_STRING:
2250 case MONO_TYPE_CLASS:
2251 case MONO_TYPE_ARRAY:
2252 case MONO_TYPE_SZARRAY:
2253 case MONO_TYPE_OBJECT:
2257 p->regs [slot] = (mgreg_t)*arg;
2259 case MONO_TYPE_BOOLEAN:
2261 p->regs [slot] = *(guint8*)arg;
2264 p->regs [slot] = *(gint8*)arg;
2267 p->regs [slot] = *(gint16*)arg;
2270 case MONO_TYPE_CHAR:
2271 p->regs [slot] = *(guint16*)arg;
2274 p->regs [slot] = *(gint32*)arg;
2277 p->regs [slot] = *(guint32*)arg;
2281 p->regs [slot ++] = (mgreg_t)arg [0];
2282 p->regs [slot] = (mgreg_t)arg [1];
2285 p->regs [slot] = *(mgreg_t*)arg;
2288 p->regs [slot ++] = (mgreg_t)arg [0];
2289 p->regs [slot] = (mgreg_t)arg [1];
2291 case MONO_TYPE_GENERICINST:
2292 if (MONO_TYPE_IS_REFERENCE (t)) {
2293 p->regs [slot] = (mgreg_t)*arg;
2298 case MONO_TYPE_VALUETYPE:
2299 g_assert (ainfo->storage == RegTypeStructByVal);
2301 if (ainfo->size == 0)
2302 slot = PARAM_REGS + (ainfo->offset / 4);
2306 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2307 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2310 g_assert_not_reached ();
2316 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2318 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2319 MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2320 guint8 *ret = ((DynCallArgs*)buf)->ret;
2321 mgreg_t res = ((DynCallArgs*)buf)->res;
2322 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2324 switch (mono_type_get_underlying_type (sig->ret)->type) {
2325 case MONO_TYPE_VOID:
2326 *(gpointer*)ret = NULL;
2328 case MONO_TYPE_STRING:
2329 case MONO_TYPE_CLASS:
2330 case MONO_TYPE_ARRAY:
2331 case MONO_TYPE_SZARRAY:
2332 case MONO_TYPE_OBJECT:
2336 *(gpointer*)ret = (gpointer)res;
2342 case MONO_TYPE_BOOLEAN:
2343 *(guint8*)ret = res;
2346 *(gint16*)ret = res;
2349 case MONO_TYPE_CHAR:
2350 *(guint16*)ret = res;
2353 *(gint32*)ret = res;
2356 *(guint32*)ret = res;
2360 /* This handles endianness as well */
2361 ((gint32*)ret) [0] = res;
2362 ((gint32*)ret) [1] = res2;
2364 case MONO_TYPE_GENERICINST:
2365 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2366 *(gpointer*)ret = (gpointer)res;
2371 case MONO_TYPE_VALUETYPE:
2372 g_assert (ainfo->cinfo->vtype_retaddr);
2377 *(float*)ret = *(float*)&res;
2379 case MONO_TYPE_R8: {
2386 *(double*)ret = *(double*)®s;
2390 g_assert_not_reached ();
2397 * Allow tracing to work with this interface (with an optional argument)
2401 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2405 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2406 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2407 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2408 code = emit_call_reg (code, ARMREG_R2);
2421 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2424 int save_mode = SAVE_NONE;
2426 MonoMethod *method = cfg->method;
2427 int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2428 int save_offset = cfg->param_area;
2432 offset = code - cfg->native_code;
2433 /* we need about 16 instructions */
2434 if (offset > (cfg->code_size - 16 * 4)) {
2435 cfg->code_size *= 2;
2436 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2437 code = cfg->native_code + offset;
2440 case MONO_TYPE_VOID:
2441 /* special case string .ctor icall */
2442 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2443 save_mode = SAVE_ONE;
2445 save_mode = SAVE_NONE;
2449 save_mode = SAVE_TWO;
2453 save_mode = SAVE_FP;
2455 case MONO_TYPE_VALUETYPE:
2456 save_mode = SAVE_STRUCT;
2459 save_mode = SAVE_ONE;
2463 switch (save_mode) {
2465 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2466 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2467 if (enable_arguments) {
2468 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2469 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2473 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2474 if (enable_arguments) {
2475 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2479 /* FIXME: what reg? */
2480 if (enable_arguments) {
2481 /* FIXME: what reg? */
2485 if (enable_arguments) {
2486 /* FIXME: get the actual address */
2487 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2495 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2496 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2497 code = emit_call_reg (code, ARMREG_IP);
2499 switch (save_mode) {
2501 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2502 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2505 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2519 * The immediate field for cond branches is big enough for all reasonable methods
2521 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2522 if (0 && ins->inst_true_bb->native_offset) { \
2523 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2525 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2526 ARM_B_COND (code, (condcode), 0); \
2529 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2531 /* emit an exception if condition is fail
2533 * We assign the extra code used to throw the implicit exceptions
2534 * to cfg->bb_exit as far as the big branch handling is concerned
2536 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
2538 mono_add_patch_info (cfg, code - cfg->native_code, \
2539 MONO_PATCH_INFO_EXC, exc_name); \
2540 ARM_BL_COND (code, (condcode), 0); \
2543 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2546 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2551 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2553 MonoInst *ins, *n, *last_ins = NULL;
2555 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2556 switch (ins->opcode) {
2559 /* Already done by an arch-independent pass */
2561 case OP_LOAD_MEMBASE:
2562 case OP_LOADI4_MEMBASE:
2564 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2565 * OP_LOAD_MEMBASE offset(basereg), reg
2567 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2568 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2569 ins->inst_basereg == last_ins->inst_destbasereg &&
2570 ins->inst_offset == last_ins->inst_offset) {
2571 if (ins->dreg == last_ins->sreg1) {
2572 MONO_DELETE_INS (bb, ins);
2575 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2576 ins->opcode = OP_MOVE;
2577 ins->sreg1 = last_ins->sreg1;
2581 * Note: reg1 must be different from the basereg in the second load
2582 * OP_LOAD_MEMBASE offset(basereg), reg1
2583 * OP_LOAD_MEMBASE offset(basereg), reg2
2585 * OP_LOAD_MEMBASE offset(basereg), reg1
2586 * OP_MOVE reg1, reg2
2588 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2589 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2590 ins->inst_basereg != last_ins->dreg &&
2591 ins->inst_basereg == last_ins->inst_basereg &&
2592 ins->inst_offset == last_ins->inst_offset) {
2594 if (ins->dreg == last_ins->dreg) {
2595 MONO_DELETE_INS (bb, ins);
2598 ins->opcode = OP_MOVE;
2599 ins->sreg1 = last_ins->dreg;
2602 //g_assert_not_reached ();
2606 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2607 * OP_LOAD_MEMBASE offset(basereg), reg
2609 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2610 * OP_ICONST reg, imm
2612 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2613 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2614 ins->inst_basereg == last_ins->inst_destbasereg &&
2615 ins->inst_offset == last_ins->inst_offset) {
2616 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2617 ins->opcode = OP_ICONST;
2618 ins->inst_c0 = last_ins->inst_imm;
2619 g_assert_not_reached (); // check this rule
2623 case OP_LOADU1_MEMBASE:
2624 case OP_LOADI1_MEMBASE:
2625 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2626 ins->inst_basereg == last_ins->inst_destbasereg &&
2627 ins->inst_offset == last_ins->inst_offset) {
2628 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2629 ins->sreg1 = last_ins->sreg1;
2632 case OP_LOADU2_MEMBASE:
2633 case OP_LOADI2_MEMBASE:
2634 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2635 ins->inst_basereg == last_ins->inst_destbasereg &&
2636 ins->inst_offset == last_ins->inst_offset) {
2637 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2638 ins->sreg1 = last_ins->sreg1;
2642 ins->opcode = OP_MOVE;
2646 if (ins->dreg == ins->sreg1) {
2647 MONO_DELETE_INS (bb, ins);
2651 * OP_MOVE sreg, dreg
2652 * OP_MOVE dreg, sreg
2654 if (last_ins && last_ins->opcode == OP_MOVE &&
2655 ins->sreg1 == last_ins->dreg &&
2656 ins->dreg == last_ins->sreg1) {
2657 MONO_DELETE_INS (bb, ins);
2665 bb->last_ins = last_ins;
2669 * the branch_cc_table should maintain the order of these
2683 branch_cc_table [] = {
2697 #define ADD_NEW_INS(cfg,dest,op) do { \
2698 MONO_INST_NEW ((cfg), (dest), (op)); \
2699 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2703 map_to_reg_reg_op (int op)
2712 case OP_COMPARE_IMM:
2714 case OP_ICOMPARE_IMM:
2728 case OP_LOAD_MEMBASE:
2729 return OP_LOAD_MEMINDEX;
2730 case OP_LOADI4_MEMBASE:
2731 return OP_LOADI4_MEMINDEX;
2732 case OP_LOADU4_MEMBASE:
2733 return OP_LOADU4_MEMINDEX;
2734 case OP_LOADU1_MEMBASE:
2735 return OP_LOADU1_MEMINDEX;
2736 case OP_LOADI2_MEMBASE:
2737 return OP_LOADI2_MEMINDEX;
2738 case OP_LOADU2_MEMBASE:
2739 return OP_LOADU2_MEMINDEX;
2740 case OP_LOADI1_MEMBASE:
2741 return OP_LOADI1_MEMINDEX;
2742 case OP_STOREI1_MEMBASE_REG:
2743 return OP_STOREI1_MEMINDEX;
2744 case OP_STOREI2_MEMBASE_REG:
2745 return OP_STOREI2_MEMINDEX;
2746 case OP_STOREI4_MEMBASE_REG:
2747 return OP_STOREI4_MEMINDEX;
2748 case OP_STORE_MEMBASE_REG:
2749 return OP_STORE_MEMINDEX;
2750 case OP_STORER4_MEMBASE_REG:
2751 return OP_STORER4_MEMINDEX;
2752 case OP_STORER8_MEMBASE_REG:
2753 return OP_STORER8_MEMINDEX;
2754 case OP_STORE_MEMBASE_IMM:
2755 return OP_STORE_MEMBASE_REG;
2756 case OP_STOREI1_MEMBASE_IMM:
2757 return OP_STOREI1_MEMBASE_REG;
2758 case OP_STOREI2_MEMBASE_IMM:
2759 return OP_STOREI2_MEMBASE_REG;
2760 case OP_STOREI4_MEMBASE_IMM:
2761 return OP_STOREI4_MEMBASE_REG;
2763 g_assert_not_reached ();
2767 * Remove from the instruction list the instructions that can't be
2768 * represented with very simple instructions with no register
2772 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2774 MonoInst *ins, *temp, *last_ins = NULL;
2775 int rot_amount, imm8, low_imm;
2777 MONO_BB_FOR_EACH_INS (bb, ins) {
2779 switch (ins->opcode) {
2783 case OP_COMPARE_IMM:
2784 case OP_ICOMPARE_IMM:
2798 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2799 ADD_NEW_INS (cfg, temp, OP_ICONST);
2800 temp->inst_c0 = ins->inst_imm;
2801 temp->dreg = mono_alloc_ireg (cfg);
2802 ins->sreg2 = temp->dreg;
2803 ins->opcode = mono_op_imm_to_op (ins->opcode);
2805 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2811 if (ins->inst_imm == 1) {
2812 ins->opcode = OP_MOVE;
2815 if (ins->inst_imm == 0) {
2816 ins->opcode = OP_ICONST;
2820 imm8 = mono_is_power_of_two (ins->inst_imm);
2822 ins->opcode = OP_SHL_IMM;
2823 ins->inst_imm = imm8;
2826 ADD_NEW_INS (cfg, temp, OP_ICONST);
2827 temp->inst_c0 = ins->inst_imm;
2828 temp->dreg = mono_alloc_ireg (cfg);
2829 ins->sreg2 = temp->dreg;
2830 ins->opcode = OP_IMUL;
2836 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2837 /* ARM sets the C flag to 1 if there was _no_ overflow */
2838 ins->next->opcode = OP_COND_EXC_NC;
2840 case OP_LOCALLOC_IMM:
2841 ADD_NEW_INS (cfg, temp, OP_ICONST);
2842 temp->inst_c0 = ins->inst_imm;
2843 temp->dreg = mono_alloc_ireg (cfg);
2844 ins->sreg1 = temp->dreg;
2845 ins->opcode = OP_LOCALLOC;
2847 case OP_LOAD_MEMBASE:
2848 case OP_LOADI4_MEMBASE:
2849 case OP_LOADU4_MEMBASE:
2850 case OP_LOADU1_MEMBASE:
2851 /* we can do two things: load the immed in a register
2852 * and use an indexed load, or see if the immed can be
2853 * represented as an ad_imm + a load with a smaller offset
2854 * that fits. We just do the first for now, optimize later.
2856 if (arm_is_imm12 (ins->inst_offset))
2858 ADD_NEW_INS (cfg, temp, OP_ICONST);
2859 temp->inst_c0 = ins->inst_offset;
2860 temp->dreg = mono_alloc_ireg (cfg);
2861 ins->sreg2 = temp->dreg;
2862 ins->opcode = map_to_reg_reg_op (ins->opcode);
2864 case OP_LOADI2_MEMBASE:
2865 case OP_LOADU2_MEMBASE:
2866 case OP_LOADI1_MEMBASE:
2867 if (arm_is_imm8 (ins->inst_offset))
2869 ADD_NEW_INS (cfg, temp, OP_ICONST);
2870 temp->inst_c0 = ins->inst_offset;
2871 temp->dreg = mono_alloc_ireg (cfg);
2872 ins->sreg2 = temp->dreg;
2873 ins->opcode = map_to_reg_reg_op (ins->opcode);
2875 case OP_LOADR4_MEMBASE:
2876 case OP_LOADR8_MEMBASE:
2877 if (arm_is_fpimm8 (ins->inst_offset))
2879 low_imm = ins->inst_offset & 0x1ff;
2880 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2881 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2882 temp->inst_imm = ins->inst_offset & ~0x1ff;
2883 temp->sreg1 = ins->inst_basereg;
2884 temp->dreg = mono_alloc_ireg (cfg);
2885 ins->inst_basereg = temp->dreg;
2886 ins->inst_offset = low_imm;
2890 ADD_NEW_INS (cfg, temp, OP_ICONST);
2891 temp->inst_c0 = ins->inst_offset;
2892 temp->dreg = mono_alloc_ireg (cfg);
2894 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2895 add_ins->sreg1 = ins->inst_basereg;
2896 add_ins->sreg2 = temp->dreg;
2897 add_ins->dreg = mono_alloc_ireg (cfg);
2899 ins->inst_basereg = add_ins->dreg;
2900 ins->inst_offset = 0;
2903 case OP_STORE_MEMBASE_REG:
2904 case OP_STOREI4_MEMBASE_REG:
2905 case OP_STOREI1_MEMBASE_REG:
2906 if (arm_is_imm12 (ins->inst_offset))
2908 ADD_NEW_INS (cfg, temp, OP_ICONST);
2909 temp->inst_c0 = ins->inst_offset;
2910 temp->dreg = mono_alloc_ireg (cfg);
2911 ins->sreg2 = temp->dreg;
2912 ins->opcode = map_to_reg_reg_op (ins->opcode);
2914 case OP_STOREI2_MEMBASE_REG:
2915 if (arm_is_imm8 (ins->inst_offset))
2917 ADD_NEW_INS (cfg, temp, OP_ICONST);
2918 temp->inst_c0 = ins->inst_offset;
2919 temp->dreg = mono_alloc_ireg (cfg);
2920 ins->sreg2 = temp->dreg;
2921 ins->opcode = map_to_reg_reg_op (ins->opcode);
2923 case OP_STORER4_MEMBASE_REG:
2924 case OP_STORER8_MEMBASE_REG:
2925 if (arm_is_fpimm8 (ins->inst_offset))
2927 low_imm = ins->inst_offset & 0x1ff;
2928 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2929 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2930 temp->inst_imm = ins->inst_offset & ~0x1ff;
2931 temp->sreg1 = ins->inst_destbasereg;
2932 temp->dreg = mono_alloc_ireg (cfg);
2933 ins->inst_destbasereg = temp->dreg;
2934 ins->inst_offset = low_imm;
2938 ADD_NEW_INS (cfg, temp, OP_ICONST);
2939 temp->inst_c0 = ins->inst_offset;
2940 temp->dreg = mono_alloc_ireg (cfg);
2942 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2943 add_ins->sreg1 = ins->inst_destbasereg;
2944 add_ins->sreg2 = temp->dreg;
2945 add_ins->dreg = mono_alloc_ireg (cfg);
2947 ins->inst_destbasereg = add_ins->dreg;
2948 ins->inst_offset = 0;
2951 case OP_STORE_MEMBASE_IMM:
2952 case OP_STOREI1_MEMBASE_IMM:
2953 case OP_STOREI2_MEMBASE_IMM:
2954 case OP_STOREI4_MEMBASE_IMM:
2955 ADD_NEW_INS (cfg, temp, OP_ICONST);
2956 temp->inst_c0 = ins->inst_imm;
2957 temp->dreg = mono_alloc_ireg (cfg);
2958 ins->sreg1 = temp->dreg;
2959 ins->opcode = map_to_reg_reg_op (ins->opcode);
2961 goto loop_start; /* make it handle the possibly big ins->inst_offset */
2963 gboolean swap = FALSE;
2967 /* Optimized away */
2972 /* Some fp compares require swapped operands */
2973 switch (ins->next->opcode) {
2975 ins->next->opcode = OP_FBLT;
2979 ins->next->opcode = OP_FBLT_UN;
2983 ins->next->opcode = OP_FBGE;
2987 ins->next->opcode = OP_FBGE_UN;
2995 ins->sreg1 = ins->sreg2;
3004 bb->last_ins = last_ins;
3005 bb->max_vreg = cfg->next_vreg;
3009 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3013 if (long_ins->opcode == OP_LNEG) {
3015 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3016 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3022 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3024 /* sreg is a float, dreg is an integer reg */
3026 ARM_FPA_FIXZ (code, dreg, sreg);
3029 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
3031 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
3032 ARM_FMRS (code, dreg, ARM_VFP_F0);
3036 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3037 else if (size == 2) {
3038 ARM_SHL_IMM (code, dreg, dreg, 16);
3039 ARM_SHR_IMM (code, dreg, dreg, 16);
3043 ARM_SHL_IMM (code, dreg, dreg, 24);
3044 ARM_SAR_IMM (code, dreg, dreg, 24);
3045 } else if (size == 2) {
3046 ARM_SHL_IMM (code, dreg, dreg, 16);
3047 ARM_SAR_IMM (code, dreg, dreg, 16);
3053 #endif /* #ifndef DISABLE_JIT */
3057 const guchar *target;
3062 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3065 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
3066 PatchData *pdata = (PatchData*)user_data;
3067 guchar *code = data;
3068 guint32 *thunks = data;
3069 guint32 *endthunks = (guint32*)(code + bsize);
3071 int difflow, diffhigh;
3073 /* always ensure a call from pdata->code can reach to the thunks without further thunks */
3074 difflow = (char*)pdata->code - (char*)thunks;
3075 diffhigh = (char*)pdata->code - (char*)endthunks;
3076 if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
3080 * The thunk is composed of 3 words:
3081 * load constant from thunks [2] into ARM_IP
3084 * Note that the LR register is already setup
3086 //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
3087 if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
3088 while (thunks < endthunks) {
3089 //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
3090 if (thunks [2] == (guint32)pdata->target) {
3091 arm_patch (pdata->code, (guchar*)thunks);
3092 mono_arch_flush_icache (pdata->code, 4);
3095 } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
3096 /* found a free slot instead: emit thunk */
3097 /* ARMREG_IP is fine to use since this can't be an IMT call
3100 code = (guchar*)thunks;
3101 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3102 if (thumb_supported)
3103 ARM_BX (code, ARMREG_IP);
3105 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3106 thunks [2] = (guint32)pdata->target;
3107 mono_arch_flush_icache ((guchar*)thunks, 12);
3109 arm_patch (pdata->code, (guchar*)thunks);
3110 mono_arch_flush_icache (pdata->code, 4);
3114 /* skip 12 bytes, the size of the thunk */
3118 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
3124 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3129 domain = mono_domain_get ();
3132 pdata.target = target;
3133 pdata.absolute = absolute;
3137 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
3140 if (pdata.found != 1) {
3141 mono_domain_lock (domain);
3142 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3145 /* this uses the first available slot */
3147 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3149 mono_domain_unlock (domain);
3152 if (pdata.found != 1) {
3154 GHashTableIter iter;
3155 MonoJitDynamicMethodInfo *ji;
3158 * This might be a dynamic method, search its code manager. We can only
3159 * use the dynamic method containing CODE, since the others might be freed later.
3163 mono_domain_lock (domain);
3164 hash = domain_jit_info (domain)->dynamic_code_hash;
3166 /* FIXME: Speed this up */
3167 g_hash_table_iter_init (&iter, hash);
3168 while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
3169 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
3170 if (pdata.found == 1)
3174 mono_domain_unlock (domain);
3176 if (pdata.found != 1)
3177 g_print ("thunk failed for %p from %p\n", target, code);
3178 g_assert (pdata.found == 1);
3182 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3184 guint32 *code32 = (void*)code;
3185 guint32 ins = *code32;
3186 guint32 prim = (ins >> 25) & 7;
3187 guint32 tval = GPOINTER_TO_UINT (target);
3189 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3190 if (prim == 5) { /* 101b */
3191 /* the diff starts 8 bytes from the branch opcode */
3192 gint diff = target - code - 8;
3194 gint tmask = 0xffffffff;
3195 if (tval & 1) { /* entering thumb mode */
3196 diff = target - 1 - code - 8;
3197 g_assert (thumb_supported);
3198 tbits = 0xf << 28; /* bl->blx bit pattern */
3199 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3200 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3204 tmask = ~(1 << 24); /* clear the link bit */
3205 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3210 if (diff <= 33554431) {
3212 ins = (ins & 0xff000000) | diff;
3214 *code32 = ins | tbits;
3218 /* diff between 0 and -33554432 */
3219 if (diff >= -33554432) {
3221 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3223 *code32 = ins | tbits;
3228 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3233 * The alternative call sequences looks like this:
3235 * ldr ip, [pc] // loads the address constant
3236 * b 1f // jumps around the constant
3237 * address constant embedded in the code
3242 * There are two cases for patching:
3243 * a) at the end of method emission: in this case code points to the start
3244 * of the call sequence
3245 * b) during runtime patching of the call site: in this case code points
3246 * to the mov pc, ip instruction
3248 * We have to handle also the thunk jump code sequence:
3252 * address constant // execution never reaches here
3254 if ((ins & 0x0ffffff0) == 0x12fff10) {
3255 /* Branch and exchange: the address is constructed in a reg
3256 * We can patch BX when the code sequence is the following:
3257 * ldr ip, [pc, #0] ; 0x8
3264 guint8 *emit = (guint8*)ccode;
3265 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3267 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3268 ARM_BX (emit, ARMREG_IP);
3270 /*patching from magic trampoline*/
3271 if (ins == ccode [3]) {
3272 g_assert (code32 [-4] == ccode [0]);
3273 g_assert (code32 [-3] == ccode [1]);
3274 g_assert (code32 [-1] == ccode [2]);
3275 code32 [-2] = (guint32)target;
3278 /*patching from JIT*/
3279 if (ins == ccode [0]) {
3280 g_assert (code32 [1] == ccode [1]);
3281 g_assert (code32 [3] == ccode [2]);
3282 g_assert (code32 [4] == ccode [3]);
3283 code32 [2] = (guint32)target;
3286 g_assert_not_reached ();
3287 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3295 guint8 *emit = (guint8*)ccode;
3296 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3298 ARM_BLX_REG (emit, ARMREG_IP);
3300 g_assert (code32 [-3] == ccode [0]);
3301 g_assert (code32 [-2] == ccode [1]);
3302 g_assert (code32 [0] == ccode [2]);
3304 code32 [-1] = (guint32)target;
3307 guint32 *tmp = ccode;
3308 guint8 *emit = (guint8*)tmp;
3309 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3310 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3311 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3312 ARM_BX (emit, ARMREG_IP);
3313 if (ins == ccode [2]) {
3314 g_assert_not_reached (); // should be -2 ...
3315 code32 [-1] = (guint32)target;
3318 if (ins == ccode [0]) {
3319 /* handles both thunk jump code and the far call sequence */
3320 code32 [2] = (guint32)target;
3323 g_assert_not_reached ();
3325 // g_print ("patched with 0x%08x\n", ins);
3329 arm_patch (guchar *code, const guchar *target)
3331 arm_patch_general (NULL, code, target, NULL);
3335 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3336 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3337 * to be used with the emit macros.
3338 * Return -1 otherwise.
3341 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3344 for (i = 0; i < 31; i+= 2) {
3345 res = (val << (32 - i)) | (val >> i);
3348 *rot_amount = i? 32 - i: 0;
3355 * Emits in code a sequence of instructions that load the value 'val'
3356 * into the dreg register. Uses at most 4 instructions.
3359 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3361 int imm8, rot_amount;
3363 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3364 /* skip the constant pool */
3370 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3371 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3372 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3373 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3376 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3378 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3382 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3384 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3386 if (val & 0xFF0000) {
3387 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3389 if (val & 0xFF000000) {
3390 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3392 } else if (val & 0xFF00) {
3393 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3394 if (val & 0xFF0000) {
3395 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3397 if (val & 0xFF000000) {
3398 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3400 } else if (val & 0xFF0000) {
3401 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3402 if (val & 0xFF000000) {
3403 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3406 //g_assert_not_reached ();
3412 mono_arm_thumb_supported (void)
3414 return thumb_supported;
3420 * emit_load_volatile_arguments:
3422 * Load volatile arguments from the stack to the original input registers.
3423 * Required before a tail call.
3426 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3428 MonoMethod *method = cfg->method;
3429 MonoMethodSignature *sig;
3434 /* FIXME: Generate intermediate code instead */
3436 sig = mono_method_signature (method);
3438 /* This is the opposite of the code in emit_prolog */
3442 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3444 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
3445 ArgInfo *ainfo = &cinfo->ret;
3446 inst = cfg->vret_addr;
3447 g_assert (arm_is_imm12 (inst->inst_offset));
3448 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3450 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3451 ArgInfo *ainfo = cinfo->args + i;
3452 inst = cfg->args [pos];
3454 if (cfg->verbose_level > 2)
3455 g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3456 if (inst->opcode == OP_REGVAR) {
3457 if (ainfo->storage == RegTypeGeneral)
3458 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3459 else if (ainfo->storage == RegTypeFP) {
3460 g_assert_not_reached ();
3461 } else if (ainfo->storage == RegTypeBase) {
3465 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3466 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3468 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3469 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3473 g_assert_not_reached ();
3475 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3476 switch (ainfo->size) {
3483 g_assert (arm_is_imm12 (inst->inst_offset));
3484 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3485 g_assert (arm_is_imm12 (inst->inst_offset + 4));
3486 ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3489 if (arm_is_imm12 (inst->inst_offset)) {
3490 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3492 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3493 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3497 } else if (ainfo->storage == RegTypeBaseGen) {
3500 } else if (ainfo->storage == RegTypeBase) {
3502 } else if (ainfo->storage == RegTypeFP) {
3503 g_assert_not_reached ();
3504 } else if (ainfo->storage == RegTypeStructByVal) {
3505 int doffset = inst->inst_offset;
3509 if (mono_class_from_mono_type (inst->inst_vtype))
3510 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3511 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3512 if (arm_is_imm12 (doffset)) {
3513 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3515 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3516 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3518 soffset += sizeof (gpointer);
3519 doffset += sizeof (gpointer);
3524 } else if (ainfo->storage == RegTypeStructByAddr) {
3539 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3544 guint8 *code = cfg->native_code + cfg->code_len;
3545 MonoInst *last_ins = NULL;
3546 guint last_offset = 0;
3548 int imm8, rot_amount;
3550 /* we don't align basic blocks of loops on arm */
3552 if (cfg->verbose_level > 2)
3553 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3555 cpos = bb->max_offset;
3557 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3558 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3559 //g_assert (!mono_compile_aot);
3562 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3563 /* this is not thread save, but good enough */
3564 /* fixme: howto handle overflows? */
3565 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3568 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3569 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3570 (gpointer)"mono_break");
3571 code = emit_call_seq (cfg, code);
3574 MONO_BB_FOR_EACH_INS (bb, ins) {
3575 offset = code - cfg->native_code;
3577 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3579 if (offset > (cfg->code_size - max_len - 16)) {
3580 cfg->code_size *= 2;
3581 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3582 code = cfg->native_code + offset;
3584 // if (ins->cil_code)
3585 // g_print ("cil code\n");
3586 mono_debug_record_line_number (cfg, ins, offset);
3588 switch (ins->opcode) {
3589 case OP_MEMORY_BARRIER:
3591 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
3592 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
3596 #ifdef HAVE_AEABI_READ_TP
3597 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3598 (gpointer)"__aeabi_read_tp");
3599 code = emit_call_seq (cfg, code);
3601 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3603 g_assert_not_reached ();
3607 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3608 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3611 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3612 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3614 case OP_STOREI1_MEMBASE_IMM:
3615 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3616 g_assert (arm_is_imm12 (ins->inst_offset));
3617 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3619 case OP_STOREI2_MEMBASE_IMM:
3620 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3621 g_assert (arm_is_imm8 (ins->inst_offset));
3622 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3624 case OP_STORE_MEMBASE_IMM:
3625 case OP_STOREI4_MEMBASE_IMM:
3626 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3627 g_assert (arm_is_imm12 (ins->inst_offset));
3628 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3630 case OP_STOREI1_MEMBASE_REG:
3631 g_assert (arm_is_imm12 (ins->inst_offset));
3632 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3634 case OP_STOREI2_MEMBASE_REG:
3635 g_assert (arm_is_imm8 (ins->inst_offset));
3636 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3638 case OP_STORE_MEMBASE_REG:
3639 case OP_STOREI4_MEMBASE_REG:
3640 /* this case is special, since it happens for spill code after lowering has been called */
3641 if (arm_is_imm12 (ins->inst_offset)) {
3642 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3644 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3645 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3648 case OP_STOREI1_MEMINDEX:
3649 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3651 case OP_STOREI2_MEMINDEX:
3652 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3654 case OP_STORE_MEMINDEX:
3655 case OP_STOREI4_MEMINDEX:
3656 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3659 g_assert_not_reached ();
3661 case OP_LOAD_MEMINDEX:
3662 case OP_LOADI4_MEMINDEX:
3663 case OP_LOADU4_MEMINDEX:
3664 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3666 case OP_LOADI1_MEMINDEX:
3667 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3669 case OP_LOADU1_MEMINDEX:
3670 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3672 case OP_LOADI2_MEMINDEX:
3673 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3675 case OP_LOADU2_MEMINDEX:
3676 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3678 case OP_LOAD_MEMBASE:
3679 case OP_LOADI4_MEMBASE:
3680 case OP_LOADU4_MEMBASE:
3681 /* this case is special, since it happens for spill code after lowering has been called */
3682 if (arm_is_imm12 (ins->inst_offset)) {
3683 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3685 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3686 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3689 case OP_LOADI1_MEMBASE:
3690 g_assert (arm_is_imm8 (ins->inst_offset));
3691 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3693 case OP_LOADU1_MEMBASE:
3694 g_assert (arm_is_imm12 (ins->inst_offset));
3695 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3697 case OP_LOADU2_MEMBASE:
3698 g_assert (arm_is_imm8 (ins->inst_offset));
3699 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3701 case OP_LOADI2_MEMBASE:
3702 g_assert (arm_is_imm8 (ins->inst_offset));
3703 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3705 case OP_ICONV_TO_I1:
3706 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3707 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3709 case OP_ICONV_TO_I2:
3710 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3711 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3713 case OP_ICONV_TO_U1:
3714 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3716 case OP_ICONV_TO_U2:
3717 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3718 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3722 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3724 case OP_COMPARE_IMM:
3725 case OP_ICOMPARE_IMM:
3726 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3727 g_assert (imm8 >= 0);
3728 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3732 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3733 * So instead of emitting a trap, we emit a call a C function and place a
3736 //*(int*)code = 0xef9f0001;
3739 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3740 (gpointer)"mono_break");
3741 code = emit_call_seq (cfg, code);
3743 case OP_RELAXED_NOP:
3748 case OP_DUMMY_STORE:
3749 case OP_NOT_REACHED:
3752 case OP_SEQ_POINT: {
3754 MonoInst *info_var = cfg->arch.seq_point_info_var;
3755 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3756 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
3757 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
3758 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
3760 int dreg = ARMREG_LR;
3762 if (cfg->soft_breakpoints) {
3763 g_assert (!cfg->compile_aot);
3767 * For AOT, we use one got slot per method, which will point to a
3768 * SeqPointInfo structure, containing all the information required
3769 * by the code below.
3771 if (cfg->compile_aot) {
3772 g_assert (info_var);
3773 g_assert (info_var->opcode == OP_REGOFFSET);
3774 g_assert (arm_is_imm12 (info_var->inst_offset));
3777 if (!cfg->soft_breakpoints) {
3779 * Read from the single stepping trigger page. This will cause a
3780 * SIGSEGV when single stepping is enabled.
3781 * We do this _before_ the breakpoint, so single stepping after
3782 * a breakpoint is hit will step to the next IL offset.
3784 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3787 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3788 if (cfg->soft_breakpoints) {
3789 /* Load the address of the sequence point trigger variable. */
3792 g_assert (var->opcode == OP_REGOFFSET);
3793 g_assert (arm_is_imm12 (var->inst_offset));
3794 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3796 /* Read the value and check whether it is non-zero. */
3797 ARM_LDR_IMM (code, dreg, dreg, 0);
3798 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3800 /* Load the address of the sequence point method. */
3801 var = ss_method_var;
3803 g_assert (var->opcode == OP_REGOFFSET);
3804 g_assert (arm_is_imm12 (var->inst_offset));
3805 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3807 /* Call it conditionally. */
3808 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
3810 if (cfg->compile_aot) {
3811 /* Load the trigger page addr from the variable initialized in the prolog */
3812 var = ss_trigger_page_var;
3814 g_assert (var->opcode == OP_REGOFFSET);
3815 g_assert (arm_is_imm12 (var->inst_offset));
3816 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3818 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3820 *(int*)code = (int)ss_trigger_page;
3823 ARM_LDR_IMM (code, dreg, dreg, 0);
3827 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3829 if (cfg->soft_breakpoints) {
3830 /* Load the address of the breakpoint method into ip. */
3831 var = bp_method_var;
3833 g_assert (var->opcode == OP_REGOFFSET);
3834 g_assert (arm_is_imm12 (var->inst_offset));
3835 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3838 * A placeholder for a possible breakpoint inserted by
3839 * mono_arch_set_breakpoint ().
3842 } else if (cfg->compile_aot) {
3843 guint32 offset = code - cfg->native_code;
3846 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3847 /* Add the offset */
3848 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3849 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3851 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3853 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3854 g_assert (!(val & 0xFF000000));
3855 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3856 ARM_LDR_IMM (code, dreg, dreg, 0);
3858 /* What is faster, a branch or a load ? */
3859 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3860 /* The breakpoint instruction */
3861 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3864 * A placeholder for a possible breakpoint inserted by
3865 * mono_arch_set_breakpoint ().
3867 for (i = 0; i < 4; ++i)
3874 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3877 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3881 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3884 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3885 g_assert (imm8 >= 0);
3886 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3890 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3891 g_assert (imm8 >= 0);
3892 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3896 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3897 g_assert (imm8 >= 0);
3898 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3901 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3902 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3904 case OP_IADD_OVF_UN:
3905 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3906 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3909 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3910 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3912 case OP_ISUB_OVF_UN:
3913 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3914 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3916 case OP_ADD_OVF_CARRY:
3917 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3918 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3920 case OP_ADD_OVF_UN_CARRY:
3921 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3922 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3924 case OP_SUB_OVF_CARRY:
3925 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3926 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3928 case OP_SUB_OVF_UN_CARRY:
3929 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3930 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3934 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3937 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3938 g_assert (imm8 >= 0);
3939 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3942 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3946 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3950 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3951 g_assert (imm8 >= 0);
3952 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3956 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3957 g_assert (imm8 >= 0);
3958 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3960 case OP_ARM_RSBS_IMM:
3961 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3962 g_assert (imm8 >= 0);
3963 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3965 case OP_ARM_RSC_IMM:
3966 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3967 g_assert (imm8 >= 0);
3968 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3971 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3975 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3976 g_assert (imm8 >= 0);
3977 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3985 /* crappy ARM arch doesn't have a DIV instruction */
3986 g_assert_not_reached ();
3988 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3992 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3993 g_assert (imm8 >= 0);
3994 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3997 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4001 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4002 g_assert (imm8 >= 0);
4003 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4006 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4011 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4012 else if (ins->dreg != ins->sreg1)
4013 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4016 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4021 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4022 else if (ins->dreg != ins->sreg1)
4023 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4026 case OP_ISHR_UN_IMM:
4028 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4029 else if (ins->dreg != ins->sreg1)
4030 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4033 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4036 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4039 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4042 if (ins->dreg == ins->sreg2)
4043 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4045 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4048 g_assert_not_reached ();
4051 /* FIXME: handle ovf/ sreg2 != dreg */
4052 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4053 /* FIXME: MUL doesn't set the C/O flags on ARM */
4055 case OP_IMUL_OVF_UN:
4056 /* FIXME: handle ovf/ sreg2 != dreg */
4057 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4058 /* FIXME: MUL doesn't set the C/O flags on ARM */
4061 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4064 /* Load the GOT offset */
4065 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4066 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4068 *(gpointer*)code = NULL;
4070 /* Load the value from the GOT */
4071 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4073 case OP_ICONV_TO_I4:
4074 case OP_ICONV_TO_U4:
4076 if (ins->dreg != ins->sreg1)
4077 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4080 int saved = ins->sreg2;
4081 if (ins->sreg2 == ARM_LSW_REG) {
4082 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4085 if (ins->sreg1 != ARM_LSW_REG)
4086 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4087 if (saved != ARM_MSW_REG)
4088 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4093 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4095 ARM_CPYD (code, ins->dreg, ins->sreg1);
4097 case OP_FCONV_TO_R4:
4099 ARM_FPA_MVFS (code, ins->dreg, ins->sreg1);
4101 ARM_CVTD (code, ins->dreg, ins->sreg1);
4102 ARM_CVTS (code, ins->dreg, ins->dreg);
4107 * Keep in sync with mono_arch_emit_epilog
4109 g_assert (!cfg->method->save_lmf);
4111 code = emit_load_volatile_arguments (cfg, code);
4113 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4115 if (cfg->used_int_regs)
4116 ARM_POP (code, cfg->used_int_regs);
4117 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4119 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4121 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4122 if (cfg->compile_aot) {
4123 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4125 *(gpointer*)code = NULL;
4127 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4133 /* ensure ins->sreg1 is not NULL */
4134 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4137 g_assert (cfg->sig_cookie < 128);
4138 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4139 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4148 call = (MonoCallInst*)ins;
4149 if (ins->flags & MONO_INST_HAS_METHOD)
4150 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4152 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4153 code = emit_call_seq (cfg, code);
4154 ins->flags |= MONO_INST_GC_CALLSITE;
4155 ins->backend.pc_offset = code - cfg->native_code;
4156 code = emit_move_return_value (cfg, ins, code);
4162 case OP_VOIDCALL_REG:
4164 code = emit_call_reg (code, ins->sreg1);
4165 ins->flags |= MONO_INST_GC_CALLSITE;
4166 ins->backend.pc_offset = code - cfg->native_code;
4167 code = emit_move_return_value (cfg, ins, code);
4169 case OP_FCALL_MEMBASE:
4170 case OP_LCALL_MEMBASE:
4171 case OP_VCALL_MEMBASE:
4172 case OP_VCALL2_MEMBASE:
4173 case OP_VOIDCALL_MEMBASE:
4174 case OP_CALL_MEMBASE:
4175 g_assert (arm_is_imm12 (ins->inst_offset));
4176 g_assert (ins->sreg1 != ARMREG_LR);
4177 call = (MonoCallInst*)ins;
4178 if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE) {
4179 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
4180 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4182 * We can't embed the method in the code stream in PIC code, or
4184 * Instead, we put it in V5 in code emitted by
4185 * mono_arch_emit_imt_argument (), and embed NULL here to
4186 * signal the IMT thunk that the value is in V5.
4188 if (call->dynamic_imt_arg)
4189 *((gpointer*)code) = NULL;
4191 *((gpointer*)code) = (gpointer)call->method;
4194 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4195 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4197 ins->flags |= MONO_INST_GC_CALLSITE;
4198 ins->backend.pc_offset = code - cfg->native_code;
4199 code = emit_move_return_value (cfg, ins, code);
4202 /* keep alignment */
4203 int alloca_waste = cfg->param_area;
4206 /* round the size to 8 bytes */
4207 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
4208 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
4210 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
4211 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
4212 /* memzero the area: dreg holds the size, sp is the pointer */
4213 if (ins->flags & MONO_INST_INIT) {
4214 guint8 *start_loop, *branch_to_cond;
4215 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
4216 branch_to_cond = code;
4219 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
4220 arm_patch (branch_to_cond, code);
4221 /* decrement by 4 and set flags */
4222 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
4223 ARM_B_COND (code, ARMCOND_GE, 0);
4224 arm_patch (code - 4, start_loop);
4226 ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
4231 MonoInst *var = cfg->dyn_call_var;
4233 g_assert (var->opcode == OP_REGOFFSET);
4234 g_assert (arm_is_imm12 (var->inst_offset));
4236 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
4237 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
4239 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
4241 /* Save args buffer */
4242 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4244 /* Set stack slots using R0 as scratch reg */
4245 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
4246 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4247 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
4248 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4251 /* Set argument registers */
4252 for (i = 0; i < PARAM_REGS; ++i)
4253 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
4256 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4257 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4260 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
4261 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
4262 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
4266 if (ins->sreg1 != ARMREG_R0)
4267 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4268 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4269 (gpointer)"mono_arch_throw_exception");
4270 code = emit_call_seq (cfg, code);
4274 if (ins->sreg1 != ARMREG_R0)
4275 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4276 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4277 (gpointer)"mono_arch_rethrow_exception");
4278 code = emit_call_seq (cfg, code);
4281 case OP_START_HANDLER: {
4282 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4285 /* Reserve a param area, see filter-stack.exe */
4286 if (cfg->param_area) {
4287 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4288 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4290 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4291 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4295 if (arm_is_imm12 (spvar->inst_offset)) {
4296 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4298 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4299 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
4303 case OP_ENDFILTER: {
4304 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4307 /* Free the param area */
4308 if (cfg->param_area) {
4309 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4310 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4312 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4313 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4317 if (ins->sreg1 != ARMREG_R0)
4318 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4319 if (arm_is_imm12 (spvar->inst_offset)) {
4320 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4322 g_assert (ARMREG_IP != spvar->inst_basereg);
4323 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4324 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4326 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4329 case OP_ENDFINALLY: {
4330 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4333 /* Free the param area */
4334 if (cfg->param_area) {
4335 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4336 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4338 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4339 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4343 if (arm_is_imm12 (spvar->inst_offset)) {
4344 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4346 g_assert (ARMREG_IP != spvar->inst_basereg);
4347 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4348 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4350 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4353 case OP_CALL_HANDLER:
4354 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4356 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4359 ins->inst_c0 = code - cfg->native_code;
4362 /*if (ins->inst_target_bb->native_offset) {
4364 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4366 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4371 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
4375 * In the normal case we have:
4376 * ldr pc, [pc, ins->sreg1 << 2]
4379 * ldr lr, [pc, ins->sreg1 << 2]
4381 * After follows the data.
4382 * FIXME: add aot support.
4384 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
4385 max_len += 4 * GPOINTER_TO_INT (ins->klass);
4386 if (offset + max_len > (cfg->code_size - 16)) {
4387 cfg->code_size += max_len;
4388 cfg->code_size *= 2;
4389 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4390 code = cfg->native_code + offset;
4392 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
4394 code += 4 * GPOINTER_TO_INT (ins->klass);
4398 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4399 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4403 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4404 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
4408 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4409 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
4413 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4414 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
4418 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4419 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
4421 case OP_COND_EXC_EQ:
4422 case OP_COND_EXC_NE_UN:
4423 case OP_COND_EXC_LT:
4424 case OP_COND_EXC_LT_UN:
4425 case OP_COND_EXC_GT:
4426 case OP_COND_EXC_GT_UN:
4427 case OP_COND_EXC_GE:
4428 case OP_COND_EXC_GE_UN:
4429 case OP_COND_EXC_LE:
4430 case OP_COND_EXC_LE_UN:
4431 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
4433 case OP_COND_EXC_IEQ:
4434 case OP_COND_EXC_INE_UN:
4435 case OP_COND_EXC_ILT:
4436 case OP_COND_EXC_ILT_UN:
4437 case OP_COND_EXC_IGT:
4438 case OP_COND_EXC_IGT_UN:
4439 case OP_COND_EXC_IGE:
4440 case OP_COND_EXC_IGE_UN:
4441 case OP_COND_EXC_ILE:
4442 case OP_COND_EXC_ILE_UN:
4443 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4446 case OP_COND_EXC_IC:
4447 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4449 case OP_COND_EXC_OV:
4450 case OP_COND_EXC_IOV:
4451 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4453 case OP_COND_EXC_NC:
4454 case OP_COND_EXC_INC:
4455 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4457 case OP_COND_EXC_NO:
4458 case OP_COND_EXC_INO:
4459 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4471 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4474 /* floating point opcodes */
4477 if (cfg->compile_aot) {
4478 ARM_FPA_LDFD (code, ins->dreg, ARMREG_PC, 0);
4480 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4482 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4485 /* FIXME: we can optimize the imm load by dealing with part of
4486 * the displacement in LDFD (aligning to 512).
4488 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4489 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4493 if (cfg->compile_aot) {
4494 ARM_FPA_LDFS (code, ins->dreg, ARMREG_PC, 0);
4496 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4499 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4500 ARM_FPA_LDFS (code, ins->dreg, ARMREG_LR, 0);
4503 case OP_STORER8_MEMBASE_REG:
4504 /* This is generated by the local regalloc pass which runs after the lowering pass */
4505 if (!arm_is_fpimm8 (ins->inst_offset)) {
4506 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4507 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4508 ARM_FPA_STFD (code, ins->sreg1, ARMREG_LR, 0);
4510 ARM_FPA_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4513 case OP_LOADR8_MEMBASE:
4514 /* This is generated by the local regalloc pass which runs after the lowering pass */
4515 if (!arm_is_fpimm8 (ins->inst_offset)) {
4516 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4517 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4518 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4520 ARM_FPA_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4523 case OP_STORER4_MEMBASE_REG:
4524 g_assert (arm_is_fpimm8 (ins->inst_offset));
4525 ARM_FPA_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4527 case OP_LOADR4_MEMBASE:
4528 g_assert (arm_is_fpimm8 (ins->inst_offset));
4529 ARM_FPA_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4531 case OP_ICONV_TO_R_UN: {
4533 tmpreg = ins->dreg == 0? 1: 0;
4534 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4535 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4536 ARM_B_COND (code, ARMCOND_GE, 8);
4537 /* save the temp register */
4538 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4539 ARM_FPA_STFD (code, tmpreg, ARMREG_SP, 0);
4540 ARM_FPA_LDFD (code, tmpreg, ARMREG_PC, 12);
4541 ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4542 ARM_FPA_LDFD (code, tmpreg, ARMREG_SP, 0);
4543 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4544 /* skip the constant pool */
4547 *(int*)code = 0x41f00000;
4552 * ldfltd ftemp, [pc, #8] 0x41f00000 0x00000000
4553 * adfltd fdest, fdest, ftemp
4557 case OP_ICONV_TO_R4:
4558 ARM_FPA_FLTS (code, ins->dreg, ins->sreg1);
4560 case OP_ICONV_TO_R8:
4561 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4564 #elif defined(ARM_FPU_VFP)
4567 if (cfg->compile_aot) {
4568 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4570 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4572 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4575 /* FIXME: we can optimize the imm load by dealing with part of
4576 * the displacement in LDFD (aligning to 512).
4578 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4579 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4583 if (cfg->compile_aot) {
4584 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4586 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4588 ARM_CVTS (code, ins->dreg, ins->dreg);
4590 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4591 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4592 ARM_CVTS (code, ins->dreg, ins->dreg);
4595 case OP_STORER8_MEMBASE_REG:
4596 /* This is generated by the local regalloc pass which runs after the lowering pass */
4597 if (!arm_is_fpimm8 (ins->inst_offset)) {
4598 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4599 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4600 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4602 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4605 case OP_LOADR8_MEMBASE:
4606 /* This is generated by the local regalloc pass which runs after the lowering pass */
4607 if (!arm_is_fpimm8 (ins->inst_offset)) {
4608 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4609 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4610 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4612 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4615 case OP_STORER4_MEMBASE_REG:
4616 g_assert (arm_is_fpimm8 (ins->inst_offset));
4617 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4618 ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4620 case OP_LOADR4_MEMBASE:
4621 g_assert (arm_is_fpimm8 (ins->inst_offset));
4622 ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4623 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4625 case OP_ICONV_TO_R_UN: {
4626 g_assert_not_reached ();
4629 case OP_ICONV_TO_R4:
4630 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4631 ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4632 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4634 case OP_ICONV_TO_R8:
4635 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4636 ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4640 if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4641 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4642 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4644 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4650 case OP_FCONV_TO_I1:
4651 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4653 case OP_FCONV_TO_U1:
4654 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4656 case OP_FCONV_TO_I2:
4657 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4659 case OP_FCONV_TO_U2:
4660 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4662 case OP_FCONV_TO_I4:
4664 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4666 case OP_FCONV_TO_U4:
4668 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4670 case OP_FCONV_TO_I8:
4671 case OP_FCONV_TO_U8:
4672 g_assert_not_reached ();
4673 /* Implemented as helper calls */
4675 case OP_LCONV_TO_R_UN:
4676 g_assert_not_reached ();
4677 /* Implemented as helper calls */
4679 case OP_LCONV_TO_OVF_I4_2: {
4680 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4682 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4685 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4686 high_bit_not_set = code;
4687 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4689 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4690 valid_negative = code;
4691 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4692 invalid_negative = code;
4693 ARM_B_COND (code, ARMCOND_AL, 0);
4695 arm_patch (high_bit_not_set, code);
4697 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4698 valid_positive = code;
4699 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4701 arm_patch (invalid_negative, code);
4702 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4704 arm_patch (valid_negative, code);
4705 arm_patch (valid_positive, code);
4707 if (ins->dreg != ins->sreg1)
4708 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4713 ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4716 ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4719 ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4722 ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4725 ARM_FPA_MNFD (code, ins->dreg, ins->sreg1);
4727 #elif defined(ARM_FPU_VFP)
4729 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4732 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4735 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4738 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4741 ARM_NEGD (code, ins->dreg, ins->sreg1);
4746 g_assert_not_reached ();
4750 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4751 } else if (IS_VFP) {
4752 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4758 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4759 } else if (IS_VFP) {
4760 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4763 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4764 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4768 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4770 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4773 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4774 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4778 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4779 } else if (IS_VFP) {
4780 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4783 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4784 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4785 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4790 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4791 } else if (IS_VFP) {
4792 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4795 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4796 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4801 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4802 } else if (IS_VFP) {
4803 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4806 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4807 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4808 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4810 /* ARM FPA flags table:
4811 * N Less than ARMCOND_MI
4812 * Z Equal ARMCOND_EQ
4813 * C Greater Than or Equal ARMCOND_CS
4814 * V Unordered ARMCOND_VS
4817 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4820 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4823 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4826 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4827 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4833 g_assert_not_reached ();
4837 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4839 /* FPA requires EQ even thou the docs suggests that just CS is enough */
4840 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4841 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4845 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4846 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4851 if (ins->dreg != ins->sreg1)
4852 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4853 } else if (IS_VFP) {
4854 ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4855 ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4857 *(guint32*)code = 0xffffffff;
4859 *(guint32*)code = 0x7fefffff;
4861 ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4863 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4864 ARM_CMPD (code, ins->sreg1, ins->sreg1);
4866 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4867 ARM_CPYD (code, ins->dreg, ins->sreg1);
4872 case OP_GC_LIVENESS_DEF:
4873 case OP_GC_LIVENESS_USE:
4874 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4875 ins->backend.pc_offset = code - cfg->native_code;
4877 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4878 ins->backend.pc_offset = code - cfg->native_code;
4879 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4883 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4884 g_assert_not_reached ();
4887 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4888 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4889 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4890 g_assert_not_reached ();
4896 last_offset = offset;
4899 cfg->code_len = code - cfg->native_code;
4902 #endif /* DISABLE_JIT */
4904 #ifdef HAVE_AEABI_READ_TP
4905 void __aeabi_read_tp (void);
4909 mono_arch_register_lowlevel_calls (void)
4911 /* The signature doesn't matter */
4912 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4913 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4915 #ifndef MONO_CROSS_COMPILE
4916 #ifdef HAVE_AEABI_READ_TP
4917 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4922 #define patch_lis_ori(ip,val) do {\
4923 guint16 *__lis_ori = (guint16*)(ip); \
4924 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
4925 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
4929 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4931 MonoJumpInfo *patch_info;
4932 gboolean compile_aot = !run_cctors;
4934 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4935 unsigned char *ip = patch_info->ip.i + code;
4936 const unsigned char *target;
4938 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4939 gpointer *jt = (gpointer*)(ip + 8);
4941 /* jt is the inlined jump table, 2 instructions after ip
4942 * In the normal case we store the absolute addresses,
4943 * otherwise the displacements.
4945 for (i = 0; i < patch_info->data.table->table_size; i++)
4946 jt [i] = code + (int)patch_info->data.table->table [i];
4949 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4952 switch (patch_info->type) {
4953 case MONO_PATCH_INFO_BB:
4954 case MONO_PATCH_INFO_LABEL:
4957 /* No need to patch these */
4962 switch (patch_info->type) {
4963 case MONO_PATCH_INFO_IP:
4964 g_assert_not_reached ();
4965 patch_lis_ori (ip, ip);
4967 case MONO_PATCH_INFO_METHOD_REL:
4968 g_assert_not_reached ();
4969 *((gpointer *)(ip)) = code + patch_info->data.offset;
4971 case MONO_PATCH_INFO_METHODCONST:
4972 case MONO_PATCH_INFO_CLASS:
4973 case MONO_PATCH_INFO_IMAGE:
4974 case MONO_PATCH_INFO_FIELD:
4975 case MONO_PATCH_INFO_VTABLE:
4976 case MONO_PATCH_INFO_IID:
4977 case MONO_PATCH_INFO_SFLDA:
4978 case MONO_PATCH_INFO_LDSTR:
4979 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4980 case MONO_PATCH_INFO_LDTOKEN:
4981 g_assert_not_reached ();
4982 /* from OP_AOTCONST : lis + ori */
4983 patch_lis_ori (ip, target);
4985 case MONO_PATCH_INFO_R4:
4986 case MONO_PATCH_INFO_R8:
4987 g_assert_not_reached ();
4988 *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4990 case MONO_PATCH_INFO_EXC_NAME:
4991 g_assert_not_reached ();
4992 *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4994 case MONO_PATCH_INFO_NONE:
4995 case MONO_PATCH_INFO_BB_OVF:
4996 case MONO_PATCH_INFO_EXC_OVF:
4997 /* everything is dealt with at epilog output time */
5002 arm_patch_general (domain, ip, target, dyn_code_mp);
5009 * Stack frame layout:
5011 * ------------------- fp
5012 * MonoLMF structure or saved registers
5013 * -------------------
5015 * -------------------
5017 * -------------------
5018 * optional 8 bytes for tracing
5019 * -------------------
5020 * param area size is cfg->param_area
5021 * ------------------- sp
5024 mono_arch_emit_prolog (MonoCompile *cfg)
5026 MonoMethod *method = cfg->method;
5028 MonoMethodSignature *sig;
5030 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount;
5035 int prev_sp_offset, reg_offset;
5037 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5040 sig = mono_method_signature (method);
5041 cfg->code_size = 256 + sig->param_count * 64;
5042 code = cfg->native_code = g_malloc (cfg->code_size);
5044 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
5046 alloc_size = cfg->stack_offset;
5050 if (!method->save_lmf) {
5053 * The iphone uses R7 as the frame pointer, and it points at the saved
5058 * We can't use r7 as a frame pointer since it points into the middle of
5059 * the frame, so we keep using our own frame pointer.
5060 * FIXME: Optimize this.
5063 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5064 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
5065 prev_sp_offset += 8; /* r7 and lr */
5066 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5067 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
5069 /* No need to push LR again */
5070 if (cfg->used_int_regs)
5071 ARM_PUSH (code, cfg->used_int_regs);
5073 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
5074 prev_sp_offset += 4;
5076 for (i = 0; i < 16; ++i) {
5077 if (cfg->used_int_regs & (1 << i))
5078 prev_sp_offset += 4;
5080 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5082 for (i = 0; i < 16; ++i) {
5083 if ((cfg->used_int_regs & (1 << i))) {
5084 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5085 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
5090 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5091 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5093 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5094 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5097 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
5098 ARM_PUSH (code, 0x5ff0);
5099 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
5100 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5102 for (i = 0; i < 16; ++i) {
5103 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
5104 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5108 pos += sizeof (MonoLMF) - prev_sp_offset;
5112 orig_alloc_size = alloc_size;
5113 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
5114 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
5115 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
5116 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
5119 /* the stack used in the pushed regs */
5120 if (prev_sp_offset & 4)
5122 cfg->stack_usage = alloc_size;
5124 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
5125 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5127 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
5128 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5130 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
5132 if (cfg->frame_reg != ARMREG_SP) {
5133 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
5134 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
5136 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
5137 prev_sp_offset += alloc_size;
5139 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
5140 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
5142 /* compute max_offset in order to use short forward jumps
5143 * we could skip do it on arm because the immediate displacement
5144 * for jumps is large enough, it may be useful later for constant pools
5147 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5148 MonoInst *ins = bb->code;
5149 bb->max_offset = max_offset;
5151 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5154 MONO_BB_FOR_EACH_INS (bb, ins)
5155 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5158 /* store runtime generic context */
5159 if (cfg->rgctx_var) {
5160 MonoInst *ins = cfg->rgctx_var;
5162 g_assert (ins->opcode == OP_REGOFFSET);
5164 if (arm_is_imm12 (ins->inst_offset)) {
5165 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
5167 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5168 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
5172 /* load arguments allocated to register from the stack */
5175 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
5177 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
5178 ArgInfo *ainfo = &cinfo->ret;
5179 inst = cfg->vret_addr;
5180 g_assert (arm_is_imm12 (inst->inst_offset));
5181 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5184 if (sig->call_convention == MONO_CALL_VARARG) {
5185 ArgInfo *cookie = &cinfo->sig_cookie;
5187 /* Save the sig cookie address */
5188 g_assert (cookie->storage == RegTypeBase);
5190 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
5191 g_assert (arm_is_imm12 (cfg->sig_cookie));
5192 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
5193 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5196 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5197 ArgInfo *ainfo = cinfo->args + i;
5198 inst = cfg->args [pos];
5200 if (cfg->verbose_level > 2)
5201 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
5202 if (inst->opcode == OP_REGVAR) {
5203 if (ainfo->storage == RegTypeGeneral)
5204 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
5205 else if (ainfo->storage == RegTypeFP) {
5206 g_assert_not_reached ();
5207 } else if (ainfo->storage == RegTypeBase) {
5208 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5209 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5211 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5212 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
5215 g_assert_not_reached ();
5217 if (cfg->verbose_level > 2)
5218 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5220 /* the argument should be put on the stack: FIXME handle size != word */
5221 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
5222 switch (ainfo->size) {
5224 if (arm_is_imm12 (inst->inst_offset))
5225 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5227 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5228 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5232 if (arm_is_imm8 (inst->inst_offset)) {
5233 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5235 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5236 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5240 if (arm_is_imm12 (inst->inst_offset)) {
5241 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5243 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5244 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5246 if (arm_is_imm12 (inst->inst_offset + 4)) {
5247 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
5249 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5250 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
5254 if (arm_is_imm12 (inst->inst_offset)) {
5255 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5257 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5258 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5262 } else if (ainfo->storage == RegTypeBaseGen) {
5263 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
5264 g_assert (arm_is_imm12 (inst->inst_offset));
5265 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5266 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5267 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
5268 } else if (ainfo->storage == RegTypeBase) {
5269 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5270 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5272 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
5273 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5276 switch (ainfo->size) {
5278 if (arm_is_imm8 (inst->inst_offset)) {
5279 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5281 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5282 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5286 if (arm_is_imm8 (inst->inst_offset)) {
5287 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5289 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5290 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5294 if (arm_is_imm12 (inst->inst_offset)) {
5295 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5297 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5298 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5300 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
5301 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
5303 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
5304 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5306 if (arm_is_imm12 (inst->inst_offset + 4)) {
5307 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5309 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5310 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5314 if (arm_is_imm12 (inst->inst_offset)) {
5315 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5317 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5318 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5322 } else if (ainfo->storage == RegTypeFP) {
5323 g_assert_not_reached ();
5324 } else if (ainfo->storage == RegTypeStructByVal) {
5325 int doffset = inst->inst_offset;
5329 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
5330 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
5331 if (arm_is_imm12 (doffset)) {
5332 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
5334 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
5335 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
5337 soffset += sizeof (gpointer);
5338 doffset += sizeof (gpointer);
5340 if (ainfo->vtsize) {
5341 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5342 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
5343 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
5345 } else if (ainfo->storage == RegTypeStructByAddr) {
5346 g_assert_not_reached ();
5347 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5348 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
5350 g_assert_not_reached ();
5355 if (method->save_lmf)
5356 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
5359 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5361 if (cfg->arch.seq_point_info_var) {
5362 MonoInst *ins = cfg->arch.seq_point_info_var;
5364 /* Initialize the variable from a GOT slot */
5365 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
5366 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5368 *(gpointer*)code = NULL;
5370 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
5372 g_assert (ins->opcode == OP_REGOFFSET);
5374 if (arm_is_imm12 (ins->inst_offset)) {
5375 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5377 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5378 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5382 /* Initialize ss_trigger_page_var */
5383 if (!cfg->soft_breakpoints) {
5384 MonoInst *info_var = cfg->arch.seq_point_info_var;
5385 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
5386 int dreg = ARMREG_LR;
5389 g_assert (info_var->opcode == OP_REGOFFSET);
5390 g_assert (arm_is_imm12 (info_var->inst_offset));
5392 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
5393 /* Load the trigger page addr */
5394 ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
5395 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
5399 if (cfg->arch.seq_point_read_var) {
5400 MonoInst *read_ins = cfg->arch.seq_point_read_var;
5401 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
5402 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
5404 g_assert (read_ins->opcode == OP_REGOFFSET);
5405 g_assert (arm_is_imm12 (read_ins->inst_offset));
5406 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
5407 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
5408 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
5409 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
5411 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5413 *(volatile int **)code = &ss_trigger_var;
5415 *(gpointer*)code = single_step_func_wrapper;
5417 *(gpointer*)code = breakpoint_func_wrapper;
5420 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
5421 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
5422 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
5423 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
5424 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
5425 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
5428 cfg->code_len = code - cfg->native_code;
5429 g_assert (cfg->code_len < cfg->code_size);
5436 mono_arch_emit_epilog (MonoCompile *cfg)
5438 MonoMethod *method = cfg->method;
5439 int pos, i, rot_amount;
5440 int max_epilog_size = 16 + 20*4;
5444 if (cfg->method->save_lmf)
5445 max_epilog_size += 128;
5447 if (mono_jit_trace_calls != NULL)
5448 max_epilog_size += 50;
5450 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5451 max_epilog_size += 50;
5453 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5454 cfg->code_size *= 2;
5455 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5456 cfg->stat_code_reallocs++;
5460 * Keep in sync with OP_JMP
5462 code = cfg->native_code + cfg->code_len;
5464 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5465 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5469 /* Load returned vtypes into registers if needed */
5470 cinfo = cfg->arch.cinfo;
5471 if (cinfo->ret.storage == RegTypeStructByVal) {
5472 MonoInst *ins = cfg->ret;
5474 if (arm_is_imm12 (ins->inst_offset)) {
5475 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5477 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5478 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5482 if (method->save_lmf) {
5483 int lmf_offset, reg, sp_adj, regmask;
5484 /* all but r0-r3, sp and pc */
5485 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5488 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
5490 /* This points to r4 inside MonoLMF->iregs */
5491 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5493 regmask = 0x9ff0; /* restore lr to pc */
5494 /* Skip caller saved registers not used by the method */
5495 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5496 regmask &= ~(1 << reg);
5500 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5501 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
5503 ARM_POP (code, regmask);
5505 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5506 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5508 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5509 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5513 /* Restore saved gregs */
5514 if (cfg->used_int_regs)
5515 ARM_POP (code, cfg->used_int_regs);
5516 /* Restore saved r7, restore LR to PC */
5517 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5519 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5523 cfg->code_len = code - cfg->native_code;
5525 g_assert (cfg->code_len < cfg->code_size);
5529 /* remove once throw_exception_by_name is eliminated */
5531 exception_id_by_name (const char *name)
5533 if (strcmp (name, "IndexOutOfRangeException") == 0)
5534 return MONO_EXC_INDEX_OUT_OF_RANGE;
5535 if (strcmp (name, "OverflowException") == 0)
5536 return MONO_EXC_OVERFLOW;
5537 if (strcmp (name, "ArithmeticException") == 0)
5538 return MONO_EXC_ARITHMETIC;
5539 if (strcmp (name, "DivideByZeroException") == 0)
5540 return MONO_EXC_DIVIDE_BY_ZERO;
5541 if (strcmp (name, "InvalidCastException") == 0)
5542 return MONO_EXC_INVALID_CAST;
5543 if (strcmp (name, "NullReferenceException") == 0)
5544 return MONO_EXC_NULL_REF;
5545 if (strcmp (name, "ArrayTypeMismatchException") == 0)
5546 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5547 if (strcmp (name, "ArgumentException") == 0)
5548 return MONO_EXC_ARGUMENT;
5549 g_error ("Unknown intrinsic exception %s\n", name);
5554 mono_arch_emit_exceptions (MonoCompile *cfg)
5556 MonoJumpInfo *patch_info;
5559 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5560 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5561 int max_epilog_size = 50;
5563 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5564 exc_throw_pos [i] = NULL;
5565 exc_throw_found [i] = 0;
5568 /* count the number of exception infos */
5571 * make sure we have enough space for exceptions
5573 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5574 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5575 i = exception_id_by_name (patch_info->data.target);
5576 if (!exc_throw_found [i]) {
5577 max_epilog_size += 32;
5578 exc_throw_found [i] = TRUE;
5583 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5584 cfg->code_size *= 2;
5585 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5586 cfg->stat_code_reallocs++;
5589 code = cfg->native_code + cfg->code_len;
5591 /* add code to raise exceptions */
5592 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5593 switch (patch_info->type) {
5594 case MONO_PATCH_INFO_EXC: {
5595 MonoClass *exc_class;
5596 unsigned char *ip = patch_info->ip.i + cfg->native_code;
5598 i = exception_id_by_name (patch_info->data.target);
5599 if (exc_throw_pos [i]) {
5600 arm_patch (ip, exc_throw_pos [i]);
5601 patch_info->type = MONO_PATCH_INFO_NONE;
5604 exc_throw_pos [i] = code;
5606 arm_patch (ip, code);
5608 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5609 g_assert (exc_class);
5611 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5612 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5613 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5614 patch_info->data.name = "mono_arch_throw_corlib_exception";
5615 patch_info->ip.i = code - cfg->native_code;
5617 *(guint32*)(gpointer)code = exc_class->type_token;
5627 cfg->code_len = code - cfg->native_code;
5629 g_assert (cfg->code_len < cfg->code_size);
5633 #endif /* #ifndef DISABLE_JIT */
5636 mono_arch_finish_init (void)
5638 lmf_tls_offset = mono_get_lmf_tls_offset ();
5639 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5643 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5648 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5655 mono_arch_print_tree (MonoInst *tree, int arity)
5661 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5663 return mono_get_domain_intrinsic (cfg);
5667 mono_arch_get_patch_offset (guint8 *code)
5674 mono_arch_flush_register_windows (void)
5678 #ifdef MONO_ARCH_HAVE_IMT
5683 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5685 if (cfg->compile_aot) {
5686 int method_reg = mono_alloc_ireg (cfg);
5689 call->dynamic_imt_arg = TRUE;
5692 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5694 MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5695 ins->dreg = method_reg;
5696 ins->inst_p0 = call->method;
5697 ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5698 MONO_ADD_INS (cfg->cbb, ins);
5700 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5702 } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5704 /* Always pass in a register for simplicity */
5705 call->dynamic_imt_arg = TRUE;
5707 cfg->uses_rgctx_reg = TRUE;
5710 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5713 int method_reg = mono_alloc_preg (cfg);
5715 MONO_INST_NEW (cfg, ins, OP_PCONST);
5716 ins->inst_p0 = call->method;
5717 ins->dreg = method_reg;
5718 MONO_ADD_INS (cfg->cbb, ins);
5720 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5725 #endif /* DISABLE_JIT */
5728 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5730 guint32 *code_ptr = (guint32*)code;
5735 return (MonoMethod*)regs [ARMREG_V5];
5737 /* The IMT value is stored in the code stream right after the LDC instruction. */
5738 if (!IS_LDR_PC (code_ptr [0])) {
5739 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5740 g_assert (IS_LDR_PC (code_ptr [0]));
5742 if (code_ptr [1] == 0)
5743 /* This is AOTed code, the IMT method is in V5 */
5744 return (MonoMethod*)regs [ARMREG_V5];
5746 return (MonoMethod*) code_ptr [1];
5750 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5752 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5755 #define ENABLE_WRONG_METHOD_CHECK 0
5756 #define BASE_SIZE (6 * 4)
5757 #define BSEARCH_ENTRY_SIZE (4 * 4)
5758 #define CMP_SIZE (3 * 4)
5759 #define BRANCH_SIZE (1 * 4)
5760 #define CALL_SIZE (2 * 4)
5761 #define WMC_SIZE (5 * 4)
5762 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5765 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5767 guint32 delta = DISTANCE (target, code);
5769 g_assert (delta >= 0 && delta <= 0xFFF);
5770 *target = *target | delta;
5776 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5777 gpointer fail_tramp)
5779 int size, i, extra_space = 0;
5780 arminstr_t *code, *start, *vtable_target = NULL;
5781 gboolean large_offsets = FALSE;
5782 guint32 **constant_pool_starts;
5785 constant_pool_starts = g_new0 (guint32*, count);
5787 for (i = 0; i < count; ++i) {
5788 MonoIMTCheckItem *item = imt_entries [i];
5789 if (item->is_equals) {
5790 gboolean fail_case = !item->check_target_idx && fail_tramp;
5792 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5793 item->chunk_size += 32;
5794 large_offsets = TRUE;
5797 if (item->check_target_idx || fail_case) {
5798 if (!item->compare_done || fail_case)
5799 item->chunk_size += CMP_SIZE;
5800 item->chunk_size += BRANCH_SIZE;
5802 #if ENABLE_WRONG_METHOD_CHECK
5803 item->chunk_size += WMC_SIZE;
5807 item->chunk_size += 16;
5808 large_offsets = TRUE;
5810 item->chunk_size += CALL_SIZE;
5812 item->chunk_size += BSEARCH_ENTRY_SIZE;
5813 imt_entries [item->check_target_idx]->compare_done = TRUE;
5815 size += item->chunk_size;
5819 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5822 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5824 code = mono_domain_code_reserve (domain, size);
5828 printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5829 for (i = 0; i < count; ++i) {
5830 MonoIMTCheckItem *item = imt_entries [i];
5831 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5836 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5838 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5839 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5840 vtable_target = code;
5841 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5843 if (mono_use_llvm) {
5844 /* LLVM always passes the IMT method in R5 */
5845 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5847 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5848 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5849 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5852 for (i = 0; i < count; ++i) {
5853 MonoIMTCheckItem *item = imt_entries [i];
5854 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5855 gint32 vtable_offset;
5857 item->code_target = (guint8*)code;
5859 if (item->is_equals) {
5860 gboolean fail_case = !item->check_target_idx && fail_tramp;
5862 if (item->check_target_idx || fail_case) {
5863 if (!item->compare_done || fail_case) {
5865 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5866 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5868 item->jmp_code = (guint8*)code;
5869 ARM_B_COND (code, ARMCOND_NE, 0);
5871 /*Enable the commented code to assert on wrong method*/
5872 #if ENABLE_WRONG_METHOD_CHECK
5874 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5875 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5876 ARM_B_COND (code, ARMCOND_NE, 1);
5882 if (item->has_target_code) {
5883 target_code_ins = code;
5884 /* Load target address */
5885 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5886 /* Save it to the fourth slot */
5887 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5888 /* Restore registers and branch */
5889 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5891 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5893 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5894 if (!arm_is_imm12 (vtable_offset)) {
5896 * We need to branch to a computed address but we don't have
5897 * a free register to store it, since IP must contain the
5898 * vtable address. So we push the two values to the stack, and
5899 * load them both using LDM.
5901 /* Compute target address */
5902 vtable_offset_ins = code;
5903 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5904 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5905 /* Save it to the fourth slot */
5906 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5907 /* Restore registers and branch */
5908 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5910 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5912 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5914 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5915 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5920 arm_patch (item->jmp_code, (guchar*)code);
5922 target_code_ins = code;
5923 /* Load target address */
5924 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5925 /* Save it to the fourth slot */
5926 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5927 /* Restore registers and branch */
5928 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5930 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5931 item->jmp_code = NULL;
5935 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5937 /*must emit after unconditional branch*/
5938 if (vtable_target) {
5939 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5940 item->chunk_size += 4;
5941 vtable_target = NULL;
5944 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5945 constant_pool_starts [i] = code;
5947 code += extra_space;
5951 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5952 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5954 item->jmp_code = (guint8*)code;
5955 ARM_B_COND (code, ARMCOND_GE, 0);
5960 for (i = 0; i < count; ++i) {
5961 MonoIMTCheckItem *item = imt_entries [i];
5962 if (item->jmp_code) {
5963 if (item->check_target_idx)
5964 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5966 if (i > 0 && item->is_equals) {
5968 arminstr_t *space_start = constant_pool_starts [i];
5969 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5970 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5977 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5978 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5983 g_free (constant_pool_starts);
5985 mono_arch_flush_icache ((guint8*)start, size);
5986 mono_stats.imt_thunks_size += code - start;
5988 g_assert (DISTANCE (start, code) <= size);
5995 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5997 return ctx->regs [reg];
6001 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6003 ctx->regs [reg] = val;
6007 * mono_arch_get_trampolines:
6009 * Return a list of MonoTrampInfo structures describing arch specific trampolines
6013 mono_arch_get_trampolines (gboolean aot)
6015 return mono_arm_get_exception_trampolines (aot);
6019 * mono_arch_set_breakpoint:
6021 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6022 * The location should contain code emitted by OP_SEQ_POINT.
6025 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6028 guint32 native_offset = ip - (guint8*)ji->code_start;
6029 MonoDebugOptions *opt = mini_get_debug_options ();
6031 if (opt->soft_breakpoints) {
6032 g_assert (!ji->from_aot);
6034 ARM_BLX_REG (code, ARMREG_LR);
6035 mono_arch_flush_icache (code - 4, 4);
6036 } else if (ji->from_aot) {
6037 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6039 g_assert (native_offset % 4 == 0);
6040 g_assert (info->bp_addrs [native_offset / 4] == 0);
6041 info->bp_addrs [native_offset / 4] = bp_trigger_page;
6043 int dreg = ARMREG_LR;
6045 /* Read from another trigger page */
6046 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
6048 *(int*)code = (int)bp_trigger_page;
6050 ARM_LDR_IMM (code, dreg, dreg, 0);
6052 mono_arch_flush_icache (code - 16, 16);
6055 /* This is currently implemented by emitting an SWI instruction, which
6056 * qemu/linux seems to convert to a SIGILL.
6058 *(int*)code = (0xef << 24) | 8;
6060 mono_arch_flush_icache (code - 4, 4);
6066 * mono_arch_clear_breakpoint:
6068 * Clear the breakpoint at IP.
6071 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6073 MonoDebugOptions *opt = mini_get_debug_options ();
6077 if (opt->soft_breakpoints) {
6078 g_assert (!ji->from_aot);
6081 mono_arch_flush_icache (code - 4, 4);
6082 } else if (ji->from_aot) {
6083 guint32 native_offset = ip - (guint8*)ji->code_start;
6084 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6086 g_assert (native_offset % 4 == 0);
6087 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
6088 info->bp_addrs [native_offset / 4] = 0;
6090 for (i = 0; i < 4; ++i)
6093 mono_arch_flush_icache (ip, code - ip);
6098 * mono_arch_start_single_stepping:
6100 * Start single stepping.
6103 mono_arch_start_single_stepping (void)
6105 if (ss_trigger_page)
6106 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6112 * mono_arch_stop_single_stepping:
6114 * Stop single stepping.
6117 mono_arch_stop_single_stepping (void)
6119 if (ss_trigger_page)
6120 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6126 #define DBG_SIGNAL SIGBUS
6128 #define DBG_SIGNAL SIGSEGV
6132 * mono_arch_is_single_step_event:
6134 * Return whenever the machine state in SIGCTX corresponds to a single
6138 mono_arch_is_single_step_event (void *info, void *sigctx)
6140 siginfo_t *sinfo = info;
6142 if (!ss_trigger_page)
6145 /* Sometimes the address is off by 4 */
6146 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
6153 * mono_arch_is_breakpoint_event:
6155 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
6158 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6160 siginfo_t *sinfo = info;
6162 if (!ss_trigger_page)
6165 if (sinfo->si_signo == DBG_SIGNAL) {
6166 /* Sometimes the address is off by 4 */
6167 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
6177 * mono_arch_skip_breakpoint:
6179 * See mini-amd64.c for docs.
6182 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6184 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6188 * mono_arch_skip_single_step:
6190 * See mini-amd64.c for docs.
6193 mono_arch_skip_single_step (MonoContext *ctx)
6195 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6199 * mono_arch_get_seq_point_info:
6201 * See mini-amd64.c for docs.
6204 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6209 // FIXME: Add a free function
6211 mono_domain_lock (domain);
6212 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
6214 mono_domain_unlock (domain);
6217 ji = mono_jit_info_table_find (domain, (char*)code);
6220 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
6222 info->ss_trigger_page = ss_trigger_page;
6223 info->bp_trigger_page = bp_trigger_page;
6225 mono_domain_lock (domain);
6226 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
6228 mono_domain_unlock (domain);
6235 * mono_arch_set_target:
6237 * Set the target architecture the JIT backend should generate code for, in the form
6238 * of a GNU target triplet. Only used in AOT mode.
6241 mono_arch_set_target (char *mtriple)
6243 /* The GNU target triple format is not very well documented */
6244 if (strstr (mtriple, "armv7")) {
6245 v6_supported = TRUE;
6246 v7_supported = TRUE;
6248 if (strstr (mtriple, "armv6")) {
6249 v6_supported = TRUE;
6251 if (strstr (mtriple, "darwin")) {
6252 v5_supported = TRUE;
6253 thumb_supported = TRUE;
6257 if (strstr (mtriple, "gnueabi"))
6258 eabi_supported = TRUE;