2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
24 #include "mini-arm-tls.h"
28 #include "debugger-agent.h"
30 #include "mono/arch/arm/arm-vfp-codegen.h"
32 #if (defined(HAVE_KW_THREAD) && defined(__linux__) && defined(__ARM_EABI__)) \
33 || defined(TARGET_ANDROID) \
34 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
38 /* Sanity check: This makes no sense */
39 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
40 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
44 * IS_SOFT_FLOAT: Is full software floating point used?
45 * IS_HARD_FLOAT: Is full hardware floating point used?
46 * IS_VFP: Is hardware floating point with software ABI used?
48 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
49 * IS_VFP may delegate to mono_arch_is_soft_float ().
52 #if defined(ARM_FPU_VFP_HARD)
53 #define IS_SOFT_FLOAT (FALSE)
54 #define IS_HARD_FLOAT (TRUE)
56 #elif defined(ARM_FPU_NONE)
57 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
58 #define IS_HARD_FLOAT (FALSE)
59 #define IS_VFP (!mono_arch_is_soft_float ())
61 #define IS_SOFT_FLOAT (FALSE)
62 #define IS_HARD_FLOAT (FALSE)
66 #define THUNK_SIZE (3 * 4)
68 #ifdef __native_client_codegen__
69 const guint kNaClAlignment = kNaClAlignmentARM;
70 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
71 gint8 nacl_align_byte = -1; /* 0xff */
74 mono_arch_nacl_pad (guint8 *code, int pad)
76 /* Not yet properly implemented. */
77 g_assert_not_reached ();
82 mono_arch_nacl_skip_nops (guint8 *code)
84 /* Not yet properly implemented. */
85 g_assert_not_reached ();
89 #endif /* __native_client_codegen__ */
91 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
94 void sys_icache_invalidate (void *start, size_t len);
97 /* This mutex protects architecture specific caches */
98 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
99 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
100 static mono_mutex_t mini_arch_mutex;
102 static gboolean v5_supported = FALSE;
103 static gboolean v6_supported = FALSE;
104 static gboolean v7_supported = FALSE;
105 static gboolean v7s_supported = FALSE;
106 static gboolean v7k_supported = FALSE;
107 static gboolean thumb_supported = FALSE;
108 static gboolean thumb2_supported = FALSE;
110 * Whenever to use the ARM EABI
112 static gboolean eabi_supported = FALSE;
115 * Whenever to use the iphone ABI extensions:
116 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
117 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
118 * This is required for debugging/profiling tools to work, but it has some overhead so it should
119 * only be turned on in debug builds.
121 static gboolean iphone_abi = FALSE;
124 * The FPU we are generating code for. This is NOT runtime configurable right now,
125 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
127 static MonoArmFPU arm_fpu;
129 #if defined(ARM_FPU_VFP_HARD)
131 * On armhf, d0-d7 are used for argument passing and d8-d15
132 * must be preserved across calls, which leaves us no room
133 * for scratch registers. So we use d14-d15 but back up their
134 * previous contents to a stack slot before using them - see
135 * mono_arm_emit_vfp_scratch_save/_restore ().
137 static int vfp_scratch1 = ARM_VFP_D14;
138 static int vfp_scratch2 = ARM_VFP_D15;
141 * On armel, d0-d7 do not need to be preserved, so we can
142 * freely make use of them as scratch registers.
144 static int vfp_scratch1 = ARM_VFP_D0;
145 static int vfp_scratch2 = ARM_VFP_D1;
150 static gpointer single_step_tramp, breakpoint_tramp;
153 * The code generated for sequence points reads from this location, which is
154 * made read-only when single stepping is enabled.
156 static gpointer ss_trigger_page;
158 /* Enabled breakpoints read from this trigger page */
159 static gpointer bp_trigger_page;
163 * floating point support: on ARM it is a mess, there are at least 3
164 * different setups, each of which binary incompat with the other.
165 * 1) FPA: old and ugly, but unfortunately what current distros use
166 * the double binary format has the two words swapped. 8 double registers.
167 * Implemented usually by kernel emulation.
168 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
169 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
170 * 3) VFP: the new and actually sensible and useful FP support. Implemented
171 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
173 * We do not care about FPA. We will support soft float and VFP.
175 int mono_exc_esp_offset = 0;
177 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
178 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
179 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
181 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
182 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
183 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
185 //#define DEBUG_IMT 0
188 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
192 mono_arch_regname (int reg)
194 static const char * rnames[] = {
195 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
196 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
197 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
200 if (reg >= 0 && reg < 16)
206 mono_arch_fregname (int reg)
208 static const char * rnames[] = {
209 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
210 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
211 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
212 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
213 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
214 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
217 if (reg >= 0 && reg < 32)
225 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
227 int imm8, rot_amount;
228 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
229 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
233 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
234 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
236 code = mono_arm_emit_load_imm (code, dreg, imm);
237 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
242 /* If dreg == sreg, this clobbers IP */
244 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
246 int imm8, rot_amount;
247 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
248 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
252 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
253 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
255 code = mono_arm_emit_load_imm (code, dreg, imm);
256 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
262 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
264 /* we can use r0-r3, since this is called only for incoming args on the stack */
265 if (size > sizeof (gpointer) * 4) {
267 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
268 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
269 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
270 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
271 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
272 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
273 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
274 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
275 ARM_B_COND (code, ARMCOND_NE, 0);
276 arm_patch (code - 4, start_loop);
279 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
280 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
282 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
283 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
289 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
290 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
291 doffset = soffset = 0;
293 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
294 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
300 g_assert (size == 0);
305 emit_call_reg (guint8 *code, int reg)
308 ARM_BLX_REG (code, reg);
310 #ifdef USE_JUMP_TABLES
311 g_assert_not_reached ();
313 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
317 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
323 emit_call_seq (MonoCompile *cfg, guint8 *code)
325 #ifdef USE_JUMP_TABLES
326 code = mono_arm_patchable_bl (code, ARMCOND_AL);
328 if (cfg->method->dynamic) {
329 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
331 *(gpointer*)code = NULL;
333 code = emit_call_reg (code, ARMREG_IP);
337 cfg->thunk_area += THUNK_SIZE;
343 mono_arm_patchable_b (guint8 *code, int cond)
345 #ifdef USE_JUMP_TABLES
348 jte = mono_jumptable_add_entry ();
349 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
350 ARM_BX_COND (code, cond, ARMREG_IP);
352 ARM_B_COND (code, cond, 0);
358 mono_arm_patchable_bl (guint8 *code, int cond)
360 #ifdef USE_JUMP_TABLES
363 jte = mono_jumptable_add_entry ();
364 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
365 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
367 ARM_BL_COND (code, cond, 0);
372 #ifdef USE_JUMP_TABLES
374 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
376 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
377 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
382 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
384 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
385 ARM_LDR_IMM (code, reg, reg, 0);
391 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
394 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
395 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
397 code = emit_call_seq (cfg, code);
398 if (dreg != ARMREG_R0)
399 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
401 g_assert_not_reached ();
407 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
410 if (tls_offset_reg != ARMREG_R0)
411 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
412 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
414 code = emit_call_seq (cfg, code);
415 if (dreg != ARMREG_R0)
416 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
418 g_assert_not_reached ();
424 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
427 if (sreg != ARMREG_R1)
428 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
429 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
430 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
432 code = emit_call_seq (cfg, code);
434 g_assert_not_reached ();
440 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
443 /* Get sreg in R1 and tls_offset_reg in R0 */
444 if (tls_offset_reg == ARMREG_R1) {
445 if (sreg == ARMREG_R0) {
446 /* swap sreg and tls_offset_reg */
447 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
448 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
449 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
451 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
452 if (sreg != ARMREG_R1)
453 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
456 if (sreg != ARMREG_R1)
457 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
458 if (tls_offset_reg != ARMREG_R0)
459 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
461 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
463 code = emit_call_seq (cfg, code);
465 g_assert_not_reached ();
473 * Emit code to push an LMF structure on the LMF stack.
474 * On arm, this is intermixed with the initialization of other fields of the structure.
477 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
479 gboolean get_lmf_fast = FALSE;
482 if (mono_arm_have_tls_get ()) {
484 if (cfg->compile_aot) {
486 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
487 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
489 *(gpointer*)code = NULL;
491 /* Load the value from the GOT */
492 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
493 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
495 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
496 g_assert (lmf_addr_tls_offset != -1);
497 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
502 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
503 (gpointer)"mono_get_lmf_addr");
504 code = emit_call_seq (cfg, code);
506 /* we build the MonoLMF structure on the stack - see mini-arm.h */
507 /* lmf_offset is the offset from the previous stack pointer,
508 * alloc_size is the total stack space allocated, so the offset
509 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
510 * The pointer to the struct is put in r1 (new_lmf).
511 * ip is used as scratch
512 * The callee-saved registers are already in the MonoLMF structure
514 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
515 /* r0 is the result from mono_get_lmf_addr () */
516 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
517 /* new_lmf->previous_lmf = *lmf_addr */
518 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
519 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
520 /* *(lmf_addr) = r1 */
521 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
522 /* Skip method (only needed for trampoline LMF frames) */
523 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
524 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
525 /* save the current IP */
526 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
527 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
529 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
530 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
541 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
545 g_assert (!cfg->r4fp);
547 for (list = inst->float_args; list; list = list->next) {
548 FloatArgData *fad = list->data;
549 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
550 gboolean imm = arm_is_fpimm8 (var->inst_offset);
552 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
558 if (*offset + *max_len > cfg->code_size) {
559 cfg->code_size += *max_len;
560 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
562 code = cfg->native_code + *offset;
566 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
567 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
569 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
571 *offset = code - cfg->native_code;
578 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
582 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
584 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
587 if (!arm_is_fpimm8 (inst->inst_offset)) {
588 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
589 ARM_FSTD (code, reg, ARMREG_LR, 0);
591 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
598 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
602 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
604 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
607 if (!arm_is_fpimm8 (inst->inst_offset)) {
608 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
609 ARM_FLDD (code, reg, ARMREG_LR, 0);
611 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
620 * Emit code to pop an LMF structure from the LMF stack.
623 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
627 if (lmf_offset < 32) {
628 basereg = cfg->frame_reg;
633 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
636 /* ip = previous_lmf */
637 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
639 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
640 /* *(lmf_addr) = previous_lmf */
641 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
646 #endif /* #ifndef DISABLE_JIT */
649 * mono_arm_have_tls_get:
651 * Returns whether we have tls access implemented on the current
655 mono_arm_have_tls_get (void)
665 * mono_arch_get_argument_info:
666 * @csig: a method signature
667 * @param_count: the number of parameters to consider
668 * @arg_info: an array to store the result infos
670 * Gathers information on parameters such as size, alignment and
671 * padding. arg_info should be large enought to hold param_count + 1 entries.
673 * Returns the size of the activation frame.
676 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
678 int k, frame_size = 0;
679 guint32 size, align, pad;
683 t = mini_get_underlying_type (csig->ret);
684 if (MONO_TYPE_ISSTRUCT (t)) {
685 frame_size += sizeof (gpointer);
689 arg_info [0].offset = offset;
692 frame_size += sizeof (gpointer);
696 arg_info [0].size = frame_size;
698 for (k = 0; k < param_count; k++) {
699 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
701 /* ignore alignment for now */
704 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
705 arg_info [k].pad = pad;
707 arg_info [k + 1].pad = 0;
708 arg_info [k + 1].size = size;
710 arg_info [k + 1].offset = offset;
714 align = MONO_ARCH_FRAME_ALIGNMENT;
715 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
716 arg_info [k].pad = pad;
721 #define MAX_ARCH_DELEGATE_PARAMS 3
724 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
726 guint8 *code, *start;
727 GSList *unwind_ops = mono_arch_get_cie_program ();
730 start = code = mono_global_codeman_reserve (12);
732 /* Replace the this argument with the target */
733 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
734 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
735 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
737 g_assert ((code - start) <= 12);
739 mono_arch_flush_icache (start, 12);
743 size = 8 + param_count * 4;
744 start = code = mono_global_codeman_reserve (size);
746 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
747 /* slide down the arguments */
748 for (i = 0; i < param_count; ++i) {
749 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
751 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
753 g_assert ((code - start) <= size);
755 mono_arch_flush_icache (start, size);
759 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
761 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
762 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
766 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
772 * mono_arch_get_delegate_invoke_impls:
774 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
778 mono_arch_get_delegate_invoke_impls (void)
784 get_delegate_invoke_impl (&info, TRUE, 0);
785 res = g_slist_prepend (res, info);
787 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
788 get_delegate_invoke_impl (&info, FALSE, i);
789 res = g_slist_prepend (res, info);
796 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
798 guint8 *code, *start;
801 /* FIXME: Support more cases */
802 sig_ret = mini_get_underlying_type (sig->ret);
803 if (MONO_TYPE_ISSTRUCT (sig_ret))
807 static guint8* cached = NULL;
808 mono_mini_arch_lock ();
810 mono_mini_arch_unlock ();
815 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
818 start = get_delegate_invoke_impl (&info, TRUE, 0);
819 mono_tramp_info_register (info, NULL);
822 mono_mini_arch_unlock ();
825 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
828 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
830 for (i = 0; i < sig->param_count; ++i)
831 if (!mono_is_regsize_var (sig->params [i]))
834 mono_mini_arch_lock ();
835 code = cache [sig->param_count];
837 mono_mini_arch_unlock ();
842 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
843 start = mono_aot_get_trampoline (name);
847 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
848 mono_tramp_info_register (info, NULL);
850 cache [sig->param_count] = start;
851 mono_mini_arch_unlock ();
859 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
865 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
867 return (gpointer)regs [ARMREG_R0];
871 * Initialize the cpu to execute managed code.
874 mono_arch_cpu_init (void)
876 i8_align = MONO_ABI_ALIGNOF (gint64);
877 #ifdef MONO_CROSS_COMPILE
878 /* Need to set the alignment of i8 since it can different on the target */
879 #ifdef TARGET_ANDROID
881 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
887 * Initialize architecture specific code.
890 mono_arch_init (void)
892 const char *cpu_arch;
894 mono_os_mutex_init_recursive (&mini_arch_mutex);
895 if (mini_get_debug_options ()->soft_breakpoints) {
896 breakpoint_tramp = mini_get_breakpoint_trampoline ();
898 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
899 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
900 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
903 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
904 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
905 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
906 #if defined(ENABLE_GSHAREDVT)
907 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
909 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
911 #if defined(__ARM_EABI__)
912 eabi_supported = TRUE;
915 #if defined(ARM_FPU_VFP_HARD)
916 arm_fpu = MONO_ARM_FPU_VFP_HARD;
918 arm_fpu = MONO_ARM_FPU_VFP;
920 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
922 * If we're compiling with a soft float fallback and it
923 * turns out that no VFP unit is available, we need to
924 * switch to soft float. We don't do this for iOS, since
925 * iOS devices always have a VFP unit.
927 if (!mono_hwcap_arm_has_vfp)
928 arm_fpu = MONO_ARM_FPU_NONE;
931 * This environment variable can be useful in testing
932 * environments to make sure the soft float fallback
933 * works. Most ARM devices have VFP units these days, so
934 * normally soft float code would not be exercised much.
936 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
938 if (soft && !strncmp (soft, "1", 1))
939 arm_fpu = MONO_ARM_FPU_NONE;
943 v5_supported = mono_hwcap_arm_is_v5;
944 v6_supported = mono_hwcap_arm_is_v6;
945 v7_supported = mono_hwcap_arm_is_v7;
947 #if defined(__APPLE__)
948 /* iOS is special-cased here because we don't yet
949 have a way to properly detect CPU features on it. */
950 thumb_supported = TRUE;
953 thumb_supported = mono_hwcap_arm_has_thumb;
954 thumb2_supported = mono_hwcap_arm_has_thumb2;
957 /* Format: armv(5|6|7[s])[-thumb[2]] */
958 cpu_arch = g_getenv ("MONO_CPU_ARCH");
960 /* Do this here so it overrides any detection. */
962 if (strncmp (cpu_arch, "armv", 4) == 0) {
963 v5_supported = cpu_arch [4] >= '5';
964 v6_supported = cpu_arch [4] >= '6';
965 v7_supported = cpu_arch [4] >= '7';
966 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
967 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
970 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
971 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
976 * Cleanup architecture specific code.
979 mono_arch_cleanup (void)
984 * This function returns the optimizations supported on this cpu.
987 mono_arch_cpu_optimizations (guint32 *exclude_mask)
989 /* no arm-specific optimizations yet */
995 * This function test for all SIMD functions supported.
997 * Returns a bitmask corresponding to all supported versions.
1001 mono_arch_cpu_enumerate_simd_versions (void)
1003 /* SIMD is currently unimplemented */
1011 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1013 if (v7s_supported || v7k_supported) {
1027 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1029 mono_arch_is_soft_float (void)
1031 return arm_fpu == MONO_ARM_FPU_NONE;
1036 mono_arm_is_hard_float (void)
1038 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1042 is_regsize_var (MonoType *t)
1046 t = mini_get_underlying_type (t);
1053 case MONO_TYPE_FNPTR:
1055 case MONO_TYPE_OBJECT:
1056 case MONO_TYPE_STRING:
1057 case MONO_TYPE_CLASS:
1058 case MONO_TYPE_SZARRAY:
1059 case MONO_TYPE_ARRAY:
1061 case MONO_TYPE_GENERICINST:
1062 if (!mono_type_generic_inst_is_valuetype (t))
1065 case MONO_TYPE_VALUETYPE:
1072 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1077 for (i = 0; i < cfg->num_varinfo; i++) {
1078 MonoInst *ins = cfg->varinfo [i];
1079 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1082 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1085 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1088 /* we can only allocate 32 bit values */
1089 if (is_regsize_var (ins->inst_vtype)) {
1090 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1091 g_assert (i == vmv->idx);
1092 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1100 mono_arch_get_global_int_regs (MonoCompile *cfg)
1104 mono_arch_compute_omit_fp (cfg);
1107 * FIXME: Interface calls might go through a static rgctx trampoline which
1108 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1111 if (cfg->flags & MONO_CFG_HAS_CALLS)
1112 cfg->uses_rgctx_reg = TRUE;
1114 if (cfg->arch.omit_fp)
1115 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1116 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1117 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1118 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1120 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1121 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1123 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1124 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1125 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1126 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1127 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1128 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1134 * mono_arch_regalloc_cost:
1136 * Return the cost, in number of memory references, of the action of
1137 * allocating the variable VMV into a register during global register
1141 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1147 #endif /* #ifndef DISABLE_JIT */
1150 mono_arch_flush_icache (guint8 *code, gint size)
1152 #if defined(MONO_CROSS_COMPILE) || defined(__native_client__)
1153 // For Native Client we don't have to flush i-cache here,
1154 // as it's being done by dyncode interface.
1156 sys_icache_invalidate (code, size);
1158 __builtin___clear_cache (code, code + size);
1164 /* Passed/returned in an ireg */
1166 /* Passed/returned in a pair of iregs */
1168 /* Passed on the stack */
1170 /* First word in r3, second word on the stack */
1172 /* FP value passed in either an ireg or a vfp reg */
1175 RegTypeStructByAddr,
1176 /* gsharedvt argument passed by addr in greg */
1177 RegTypeGSharedVtInReg,
1178 /* gsharedvt argument passed by addr on stack */
1179 RegTypeGSharedVtOnStack,
1185 guint16 vtsize; /* in param area */
1193 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1198 guint32 stack_usage;
1199 /* The index of the vret arg in the argument list for RegTypeStructByAddr */
1209 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1212 if (*gr > ARMREG_R3) {
1214 ainfo->offset = *stack_size;
1215 ainfo->reg = ARMREG_SP; /* in the caller */
1216 ainfo->storage = RegTypeBase;
1219 ainfo->storage = RegTypeGeneral;
1226 split = i8_align == 4;
1231 if (*gr == ARMREG_R3 && split) {
1232 /* first word in r3 and the second on the stack */
1233 ainfo->offset = *stack_size;
1234 ainfo->reg = ARMREG_SP; /* in the caller */
1235 ainfo->storage = RegTypeBaseGen;
1237 } else if (*gr >= ARMREG_R3) {
1238 if (eabi_supported) {
1239 /* darwin aligns longs to 4 byte only */
1240 if (i8_align == 8) {
1245 ainfo->offset = *stack_size;
1246 ainfo->reg = ARMREG_SP; /* in the caller */
1247 ainfo->storage = RegTypeBase;
1250 if (eabi_supported) {
1251 if (i8_align == 8 && ((*gr) & 1))
1254 ainfo->storage = RegTypeIRegPair;
1263 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1266 * If we're calling a function like this:
1268 * void foo(float a, double b, float c)
1270 * We pass a in s0 and b in d1. That leaves us
1271 * with s1 being unused. The armhf ABI recognizes
1272 * this and requires register assignment to then
1273 * use that for the next single-precision arg,
1274 * i.e. c in this example. So float_spare either
1275 * tells us which reg to use for the next single-
1276 * precision arg, or it's -1, meaning use *fpr.
1278 * Note that even though most of the JIT speaks
1279 * double-precision, fpr represents single-
1280 * precision registers.
1282 * See parts 5.5 and 6.1.2 of the AAPCS for how
1286 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1287 ainfo->storage = RegTypeFP;
1291 * If we're passing a double-precision value
1292 * and *fpr is odd (e.g. it's s1, s3, ...)
1293 * we need to use the next even register. So
1294 * we mark the current *fpr as a spare that
1295 * can be used for the next single-precision
1299 *float_spare = *fpr;
1304 * At this point, we have an even register
1305 * so we assign that and move along.
1309 } else if (*float_spare >= 0) {
1311 * We're passing a single-precision value
1312 * and it looks like a spare single-
1313 * precision register is available. Let's
1317 ainfo->reg = *float_spare;
1321 * If we hit this branch, we're passing a
1322 * single-precision value and we can simply
1323 * use the next available register.
1331 * We've exhausted available floating point
1332 * regs, so pass the rest on the stack.
1340 ainfo->offset = *stack_size;
1341 ainfo->reg = ARMREG_SP;
1342 ainfo->storage = RegTypeBase;
1349 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1353 MonoClassField *field;
1354 MonoType *ftype, *prev_ftype = NULL;
1357 klass = mono_class_from_mono_type (t);
1359 while ((field = mono_class_get_fields (klass, &iter))) {
1360 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1362 ftype = mono_field_get_type (field);
1363 ftype = mini_get_underlying_type (ftype);
1365 if (MONO_TYPE_ISSTRUCT (ftype)) {
1366 int nested_nfields, nested_esize;
1368 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1370 if (nested_esize == 4)
1371 ftype = &mono_defaults.single_class->byval_arg;
1373 ftype = &mono_defaults.double_class->byval_arg;
1374 if (prev_ftype && prev_ftype->type != ftype->type)
1377 nfields += nested_nfields;
1379 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1381 if (prev_ftype && prev_ftype->type != ftype->type)
1387 if (nfields == 0 || nfields > 4)
1389 *out_nfields = nfields;
1390 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1395 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1397 guint i, gr, fpr, pstart;
1399 int n = sig->hasthis + sig->param_count;
1403 guint32 stack_size = 0;
1405 gboolean is_pinvoke = sig->pinvoke;
1406 gboolean vtype_retaddr = FALSE;
1409 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1411 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1418 t = mini_get_underlying_type (sig->ret);
1429 case MONO_TYPE_FNPTR:
1430 case MONO_TYPE_CLASS:
1431 case MONO_TYPE_OBJECT:
1432 case MONO_TYPE_SZARRAY:
1433 case MONO_TYPE_ARRAY:
1434 case MONO_TYPE_STRING:
1435 cinfo->ret.storage = RegTypeGeneral;
1436 cinfo->ret.reg = ARMREG_R0;
1440 cinfo->ret.storage = RegTypeIRegPair;
1441 cinfo->ret.reg = ARMREG_R0;
1445 cinfo->ret.storage = RegTypeFP;
1447 if (t->type == MONO_TYPE_R4)
1448 cinfo->ret.size = 4;
1450 cinfo->ret.size = 8;
1452 if (IS_HARD_FLOAT) {
1453 cinfo->ret.reg = ARM_VFP_F0;
1455 cinfo->ret.reg = ARMREG_R0;
1458 case MONO_TYPE_GENERICINST:
1459 if (!mono_type_generic_inst_is_valuetype (t)) {
1460 cinfo->ret.storage = RegTypeGeneral;
1461 cinfo->ret.reg = ARMREG_R0;
1464 if (mini_is_gsharedvt_variable_type (t)) {
1465 cinfo->ret.storage = RegTypeStructByAddr;
1469 case MONO_TYPE_VALUETYPE:
1470 case MONO_TYPE_TYPEDBYREF:
1471 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1472 cinfo->ret.storage = RegTypeHFA;
1474 cinfo->ret.nregs = nfields;
1475 cinfo->ret.esize = esize;
1477 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1478 cinfo->ret.storage = RegTypeStructByVal;
1480 cinfo->ret.storage = RegTypeStructByAddr;
1484 case MONO_TYPE_MVAR:
1485 g_assert (mini_is_gsharedvt_type (t));
1486 cinfo->ret.storage = RegTypeStructByAddr;
1488 case MONO_TYPE_VOID:
1491 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1494 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1499 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1500 * the first argument, allowing 'this' to be always passed in the first arg reg.
1501 * Also do this if the first argument is a reference type, since virtual calls
1502 * are sometimes made using calli without sig->hasthis set, like in the delegate
1505 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1507 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1509 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1513 cinfo->ret.reg = gr;
1515 cinfo->vret_arg_index = 1;
1519 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1522 if (vtype_retaddr) {
1523 cinfo->ret.reg = gr;
1528 DEBUG(g_print("params: %d\n", sig->param_count));
1529 for (i = pstart; i < sig->param_count; ++i) {
1530 ArgInfo *ainfo = &cinfo->args [n];
1532 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1533 /* Prevent implicit arguments and sig_cookie from
1534 being passed in registers */
1537 /* Emit the signature cookie just before the implicit arguments */
1538 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1540 DEBUG(g_print("param %d: ", i));
1541 if (sig->params [i]->byref) {
1542 DEBUG(g_print("byref\n"));
1543 add_general (&gr, &stack_size, ainfo, TRUE);
1547 t = mini_get_underlying_type (sig->params [i]);
1551 cinfo->args [n].size = 1;
1552 add_general (&gr, &stack_size, ainfo, TRUE);
1556 cinfo->args [n].size = 2;
1557 add_general (&gr, &stack_size, ainfo, TRUE);
1561 cinfo->args [n].size = 4;
1562 add_general (&gr, &stack_size, ainfo, TRUE);
1567 case MONO_TYPE_FNPTR:
1568 case MONO_TYPE_CLASS:
1569 case MONO_TYPE_OBJECT:
1570 case MONO_TYPE_STRING:
1571 case MONO_TYPE_SZARRAY:
1572 case MONO_TYPE_ARRAY:
1573 cinfo->args [n].size = sizeof (gpointer);
1574 add_general (&gr, &stack_size, ainfo, TRUE);
1576 case MONO_TYPE_GENERICINST:
1577 if (!mono_type_generic_inst_is_valuetype (t)) {
1578 cinfo->args [n].size = sizeof (gpointer);
1579 add_general (&gr, &stack_size, ainfo, TRUE);
1582 if (mini_is_gsharedvt_variable_type (t)) {
1583 /* gsharedvt arguments are passed by ref */
1584 g_assert (mini_is_gsharedvt_type (t));
1585 add_general (&gr, &stack_size, ainfo, TRUE);
1586 switch (ainfo->storage) {
1587 case RegTypeGeneral:
1588 ainfo->storage = RegTypeGSharedVtInReg;
1591 ainfo->storage = RegTypeGSharedVtOnStack;
1594 g_assert_not_reached ();
1599 case MONO_TYPE_TYPEDBYREF:
1600 case MONO_TYPE_VALUETYPE: {
1603 int nwords, nfields, esize;
1606 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1607 if (fpr + nfields < ARM_VFP_F16) {
1608 ainfo->storage = RegTypeHFA;
1610 ainfo->nregs = nfields;
1611 ainfo->esize = esize;
1622 if (t->type == MONO_TYPE_TYPEDBYREF) {
1623 size = sizeof (MonoTypedRef);
1624 align = sizeof (gpointer);
1626 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1628 size = mono_class_native_size (klass, &align);
1630 size = mini_type_stack_size_full (t, &align, FALSE);
1632 DEBUG(g_print ("load %d bytes struct\n", size));
1635 align_size += (sizeof (gpointer) - 1);
1636 align_size &= ~(sizeof (gpointer) - 1);
1637 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1638 ainfo->storage = RegTypeStructByVal;
1639 ainfo->struct_size = size;
1640 /* FIXME: align stack_size if needed */
1641 if (eabi_supported) {
1642 if (align >= 8 && (gr & 1))
1645 if (gr > ARMREG_R3) {
1647 ainfo->vtsize = nwords;
1649 int rest = ARMREG_R3 - gr + 1;
1650 int n_in_regs = rest >= nwords? nwords: rest;
1652 ainfo->size = n_in_regs;
1653 ainfo->vtsize = nwords - n_in_regs;
1656 nwords -= n_in_regs;
1658 if (sig->call_convention == MONO_CALL_VARARG)
1659 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1660 stack_size = ALIGN_TO (stack_size, align);
1661 ainfo->offset = stack_size;
1662 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1663 stack_size += nwords * sizeof (gpointer);
1669 add_general (&gr, &stack_size, ainfo, FALSE);
1675 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1677 add_general (&gr, &stack_size, ainfo, TRUE);
1683 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1685 add_general (&gr, &stack_size, ainfo, FALSE);
1688 case MONO_TYPE_MVAR:
1689 /* gsharedvt arguments are passed by ref */
1690 g_assert (mini_is_gsharedvt_type (t));
1691 add_general (&gr, &stack_size, ainfo, TRUE);
1692 switch (ainfo->storage) {
1693 case RegTypeGeneral:
1694 ainfo->storage = RegTypeGSharedVtInReg;
1697 ainfo->storage = RegTypeGSharedVtOnStack;
1700 g_assert_not_reached ();
1704 g_error ("Can't handle 0x%x", sig->params [i]->type);
1709 /* Handle the case where there are no implicit arguments */
1710 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1711 /* Prevent implicit arguments and sig_cookie from
1712 being passed in registers */
1715 /* Emit the signature cookie just before the implicit arguments */
1716 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1719 /* align stack size to 8 */
1720 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1721 stack_size = (stack_size + 7) & ~7;
1723 cinfo->stack_usage = stack_size;
1729 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1731 MonoType *callee_ret;
1735 c1 = get_call_info (NULL, caller_sig);
1736 c2 = get_call_info (NULL, callee_sig);
1739 * Tail calls with more callee stack usage than the caller cannot be supported, since
1740 * the extra stack space would be left on the stack after the tail call.
1742 res = c1->stack_usage >= c2->stack_usage;
1743 callee_ret = mini_get_underlying_type (callee_sig->ret);
1744 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1745 /* An address on the callee's stack is passed as the first argument */
1748 if (c2->stack_usage > 16 * 4)
1760 debug_omit_fp (void)
1763 return mono_debug_count ();
1770 * mono_arch_compute_omit_fp:
1772 * Determine whenever the frame pointer can be eliminated.
1775 mono_arch_compute_omit_fp (MonoCompile *cfg)
1777 MonoMethodSignature *sig;
1778 MonoMethodHeader *header;
1782 if (cfg->arch.omit_fp_computed)
1785 header = cfg->header;
1787 sig = mono_method_signature (cfg->method);
1789 if (!cfg->arch.cinfo)
1790 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1791 cinfo = cfg->arch.cinfo;
1794 * FIXME: Remove some of the restrictions.
1796 cfg->arch.omit_fp = TRUE;
1797 cfg->arch.omit_fp_computed = TRUE;
1799 if (cfg->disable_omit_fp)
1800 cfg->arch.omit_fp = FALSE;
1801 if (!debug_omit_fp ())
1802 cfg->arch.omit_fp = FALSE;
1804 if (cfg->method->save_lmf)
1805 cfg->arch.omit_fp = FALSE;
1807 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1808 cfg->arch.omit_fp = FALSE;
1809 if (header->num_clauses)
1810 cfg->arch.omit_fp = FALSE;
1811 if (cfg->param_area)
1812 cfg->arch.omit_fp = FALSE;
1813 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1814 cfg->arch.omit_fp = FALSE;
1815 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1816 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1817 cfg->arch.omit_fp = FALSE;
1818 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1819 ArgInfo *ainfo = &cinfo->args [i];
1821 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1823 * The stack offset can only be determined when the frame
1826 cfg->arch.omit_fp = FALSE;
1831 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1832 MonoInst *ins = cfg->varinfo [i];
1835 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1840 * Set var information according to the calling convention. arm version.
1841 * The locals var stuff should most likely be split in another method.
1844 mono_arch_allocate_vars (MonoCompile *cfg)
1846 MonoMethodSignature *sig;
1847 MonoMethodHeader *header;
1850 int i, offset, size, align, curinst;
1855 sig = mono_method_signature (cfg->method);
1857 if (!cfg->arch.cinfo)
1858 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1859 cinfo = cfg->arch.cinfo;
1860 sig_ret = mini_get_underlying_type (sig->ret);
1862 mono_arch_compute_omit_fp (cfg);
1864 if (cfg->arch.omit_fp)
1865 cfg->frame_reg = ARMREG_SP;
1867 cfg->frame_reg = ARMREG_FP;
1869 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1871 /* allow room for the vararg method args: void* and long/double */
1872 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1873 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1875 header = cfg->header;
1877 /* See mono_arch_get_global_int_regs () */
1878 if (cfg->flags & MONO_CFG_HAS_CALLS)
1879 cfg->uses_rgctx_reg = TRUE;
1881 if (cfg->frame_reg != ARMREG_SP)
1882 cfg->used_int_regs |= 1 << cfg->frame_reg;
1884 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1885 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1886 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1890 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1891 if (sig_ret->type != MONO_TYPE_VOID) {
1892 cfg->ret->opcode = OP_REGVAR;
1893 cfg->ret->inst_c0 = ARMREG_R0;
1896 /* local vars are at a positive offset from the stack pointer */
1898 * also note that if the function uses alloca, we use FP
1899 * to point at the local variables.
1901 offset = 0; /* linkage area */
1902 /* align the offset to 16 bytes: not sure this is needed here */
1904 //offset &= ~(8 - 1);
1906 /* add parameter area size for called functions */
1907 offset += cfg->param_area;
1910 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1913 /* allow room to save the return value */
1914 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1917 switch (cinfo->ret.storage) {
1918 case RegTypeStructByVal:
1919 cfg->ret->opcode = OP_REGOFFSET;
1920 cfg->ret->inst_basereg = cfg->frame_reg;
1921 offset += sizeof (gpointer) - 1;
1922 offset &= ~(sizeof (gpointer) - 1);
1923 cfg->ret->inst_offset = - offset;
1924 offset += sizeof(gpointer);
1927 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1928 offset = ALIGN_TO (offset, 8);
1929 cfg->ret->opcode = OP_REGOFFSET;
1930 cfg->ret->inst_basereg = cfg->frame_reg;
1931 cfg->ret->inst_offset = offset;
1935 case RegTypeStructByAddr:
1936 ins = cfg->vret_addr;
1937 offset += sizeof(gpointer) - 1;
1938 offset &= ~(sizeof(gpointer) - 1);
1939 ins->inst_offset = offset;
1940 ins->opcode = OP_REGOFFSET;
1941 ins->inst_basereg = cfg->frame_reg;
1942 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1943 g_print ("vret_addr =");
1944 mono_print_ins (cfg->vret_addr);
1946 offset += sizeof(gpointer);
1952 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1953 if (cfg->arch.seq_point_info_var) {
1956 ins = cfg->arch.seq_point_info_var;
1960 offset += align - 1;
1961 offset &= ~(align - 1);
1962 ins->opcode = OP_REGOFFSET;
1963 ins->inst_basereg = cfg->frame_reg;
1964 ins->inst_offset = offset;
1967 ins = cfg->arch.ss_trigger_page_var;
1970 offset += align - 1;
1971 offset &= ~(align - 1);
1972 ins->opcode = OP_REGOFFSET;
1973 ins->inst_basereg = cfg->frame_reg;
1974 ins->inst_offset = offset;
1978 if (cfg->arch.seq_point_ss_method_var) {
1981 ins = cfg->arch.seq_point_ss_method_var;
1984 offset += align - 1;
1985 offset &= ~(align - 1);
1986 ins->opcode = OP_REGOFFSET;
1987 ins->inst_basereg = cfg->frame_reg;
1988 ins->inst_offset = offset;
1991 ins = cfg->arch.seq_point_bp_method_var;
1994 offset += align - 1;
1995 offset &= ~(align - 1);
1996 ins->opcode = OP_REGOFFSET;
1997 ins->inst_basereg = cfg->frame_reg;
1998 ins->inst_offset = offset;
2002 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
2003 /* Allocate a temporary used by the atomic ops */
2007 /* Allocate a local slot to hold the sig cookie address */
2008 offset += align - 1;
2009 offset &= ~(align - 1);
2010 cfg->arch.atomic_tmp_offset = offset;
2013 cfg->arch.atomic_tmp_offset = -1;
2016 cfg->locals_min_stack_offset = offset;
2018 curinst = cfg->locals_start;
2019 for (i = curinst; i < cfg->num_varinfo; ++i) {
2022 ins = cfg->varinfo [i];
2023 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
2026 t = ins->inst_vtype;
2027 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
2030 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
2031 * pinvoke wrappers when they call functions returning structure */
2032 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2033 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
2037 size = mono_type_size (t, &align);
2039 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2040 * since it loads/stores misaligned words, which don't do the right thing.
2042 if (align < 4 && size >= 4)
2044 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2045 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2046 offset += align - 1;
2047 offset &= ~(align - 1);
2048 ins->opcode = OP_REGOFFSET;
2049 ins->inst_offset = offset;
2050 ins->inst_basereg = cfg->frame_reg;
2052 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2055 cfg->locals_max_stack_offset = offset;
2059 ins = cfg->args [curinst];
2060 if (ins->opcode != OP_REGVAR) {
2061 ins->opcode = OP_REGOFFSET;
2062 ins->inst_basereg = cfg->frame_reg;
2063 offset += sizeof (gpointer) - 1;
2064 offset &= ~(sizeof (gpointer) - 1);
2065 ins->inst_offset = offset;
2066 offset += sizeof (gpointer);
2071 if (sig->call_convention == MONO_CALL_VARARG) {
2075 /* Allocate a local slot to hold the sig cookie address */
2076 offset += align - 1;
2077 offset &= ~(align - 1);
2078 cfg->sig_cookie = offset;
2082 for (i = 0; i < sig->param_count; ++i) {
2083 ainfo = cinfo->args + i;
2085 ins = cfg->args [curinst];
2087 switch (ainfo->storage) {
2089 offset = ALIGN_TO (offset, 8);
2090 ins->opcode = OP_REGOFFSET;
2091 ins->inst_basereg = cfg->frame_reg;
2092 /* These arguments are saved to the stack in the prolog */
2093 ins->inst_offset = offset;
2094 if (cfg->verbose_level >= 2)
2095 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2103 if (ins->opcode != OP_REGVAR) {
2104 ins->opcode = OP_REGOFFSET;
2105 ins->inst_basereg = cfg->frame_reg;
2106 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2108 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2109 * since it loads/stores misaligned words, which don't do the right thing.
2111 if (align < 4 && size >= 4)
2113 /* The code in the prolog () stores words when storing vtypes received in a register */
2114 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2116 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2117 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2118 offset += align - 1;
2119 offset &= ~(align - 1);
2120 ins->inst_offset = offset;
2126 /* align the offset to 8 bytes */
2127 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2128 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2133 cfg->stack_offset = offset;
2137 mono_arch_create_vars (MonoCompile *cfg)
2139 MonoMethodSignature *sig;
2143 sig = mono_method_signature (cfg->method);
2145 if (!cfg->arch.cinfo)
2146 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2147 cinfo = cfg->arch.cinfo;
2149 if (IS_HARD_FLOAT) {
2150 for (i = 0; i < 2; i++) {
2151 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2152 inst->flags |= MONO_INST_VOLATILE;
2154 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2158 if (cinfo->ret.storage == RegTypeStructByVal)
2159 cfg->ret_var_is_local = TRUE;
2161 if (cinfo->ret.storage == RegTypeStructByAddr) {
2162 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2163 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2164 g_print ("vret_addr = ");
2165 mono_print_ins (cfg->vret_addr);
2169 if (cfg->gen_sdb_seq_points) {
2170 if (cfg->soft_breakpoints) {
2173 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2174 ins->flags |= MONO_INST_VOLATILE;
2175 cfg->arch.seq_point_ss_method_var = ins;
2177 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2178 ins->flags |= MONO_INST_VOLATILE;
2179 cfg->arch.seq_point_bp_method_var = ins;
2181 g_assert (!cfg->compile_aot);
2182 } else if (cfg->compile_aot) {
2183 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2184 ins->flags |= MONO_INST_VOLATILE;
2185 cfg->arch.seq_point_info_var = ins;
2187 /* Allocate a separate variable for this to save 1 load per seq point */
2188 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2189 ins->flags |= MONO_INST_VOLATILE;
2190 cfg->arch.ss_trigger_page_var = ins;
2196 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2198 MonoMethodSignature *tmp_sig;
2201 if (call->tail_call)
2204 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2207 * mono_ArgIterator_Setup assumes the signature cookie is
2208 * passed first and all the arguments which were before it are
2209 * passed on the stack after the signature. So compensate by
2210 * passing a different signature.
2212 tmp_sig = mono_metadata_signature_dup (call->signature);
2213 tmp_sig->param_count -= call->signature->sentinelpos;
2214 tmp_sig->sentinelpos = 0;
2215 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2217 sig_reg = mono_alloc_ireg (cfg);
2218 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2220 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2225 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2230 LLVMCallInfo *linfo;
2232 n = sig->param_count + sig->hasthis;
2234 cinfo = get_call_info (cfg->mempool, sig);
2236 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2239 * LLVM always uses the native ABI while we use our own ABI, the
2240 * only difference is the handling of vtypes:
2241 * - we only pass/receive them in registers in some cases, and only
2242 * in 1 or 2 integer registers.
2244 switch (cinfo->ret.storage) {
2245 case RegTypeGeneral:
2248 case RegTypeIRegPair:
2250 case RegTypeStructByAddr:
2251 /* Vtype returned using a hidden argument */
2252 linfo->ret.storage = LLVMArgVtypeRetAddr;
2253 linfo->vret_arg_index = cinfo->vret_arg_index;
2256 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2257 cfg->disable_llvm = TRUE;
2261 for (i = 0; i < n; ++i) {
2262 ainfo = cinfo->args + i;
2264 linfo->args [i].storage = LLVMArgNone;
2266 switch (ainfo->storage) {
2267 case RegTypeGeneral:
2268 case RegTypeIRegPair:
2270 case RegTypeBaseGen:
2271 linfo->args [i].storage = LLVMArgNormal;
2273 case RegTypeStructByVal:
2274 linfo->args [i].storage = LLVMArgAsIArgs;
2275 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2278 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2279 cfg->disable_llvm = TRUE;
2289 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2292 MonoMethodSignature *sig;
2296 sig = call->signature;
2297 n = sig->param_count + sig->hasthis;
2299 cinfo = get_call_info (cfg->mempool, sig);
2301 switch (cinfo->ret.storage) {
2302 case RegTypeStructByVal:
2303 /* The JIT will transform this into a normal call */
2304 call->vret_in_reg = TRUE;
2308 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2309 * the location pointed to by it after call in emit_move_return_value ().
2311 if (!cfg->arch.vret_addr_loc) {
2312 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2313 /* Prevent it from being register allocated or optimized away */
2314 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2317 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2319 case RegTypeStructByAddr: {
2321 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2322 vtarg->sreg1 = call->vret_var->dreg;
2323 vtarg->dreg = mono_alloc_preg (cfg);
2324 MONO_ADD_INS (cfg->cbb, vtarg);
2326 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2333 for (i = 0; i < n; ++i) {
2334 ArgInfo *ainfo = cinfo->args + i;
2337 if (i >= sig->hasthis)
2338 t = sig->params [i - sig->hasthis];
2340 t = &mono_defaults.int_class->byval_arg;
2341 t = mini_get_underlying_type (t);
2343 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2344 /* Emit the signature cookie just before the implicit arguments */
2345 emit_sig_cookie (cfg, call, cinfo);
2348 in = call->args [i];
2350 switch (ainfo->storage) {
2351 case RegTypeGeneral:
2352 case RegTypeIRegPair:
2353 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2354 MONO_INST_NEW (cfg, ins, OP_MOVE);
2355 ins->dreg = mono_alloc_ireg (cfg);
2356 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2357 MONO_ADD_INS (cfg->cbb, ins);
2358 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2360 MONO_INST_NEW (cfg, ins, OP_MOVE);
2361 ins->dreg = mono_alloc_ireg (cfg);
2362 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2363 MONO_ADD_INS (cfg->cbb, ins);
2364 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2365 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2366 if (ainfo->size == 4) {
2367 if (IS_SOFT_FLOAT) {
2368 /* mono_emit_call_args () have already done the r8->r4 conversion */
2369 /* The converted value is in an int vreg */
2370 MONO_INST_NEW (cfg, ins, OP_MOVE);
2371 ins->dreg = mono_alloc_ireg (cfg);
2372 ins->sreg1 = in->dreg;
2373 MONO_ADD_INS (cfg->cbb, ins);
2374 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2378 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2379 creg = mono_alloc_ireg (cfg);
2380 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2381 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2384 if (IS_SOFT_FLOAT) {
2385 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2386 ins->dreg = mono_alloc_ireg (cfg);
2387 ins->sreg1 = in->dreg;
2388 MONO_ADD_INS (cfg->cbb, ins);
2389 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2391 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2392 ins->dreg = mono_alloc_ireg (cfg);
2393 ins->sreg1 = in->dreg;
2394 MONO_ADD_INS (cfg->cbb, ins);
2395 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2399 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2400 creg = mono_alloc_ireg (cfg);
2401 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2402 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2403 creg = mono_alloc_ireg (cfg);
2404 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2405 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2408 cfg->flags |= MONO_CFG_HAS_FPOUT;
2410 MONO_INST_NEW (cfg, ins, OP_MOVE);
2411 ins->dreg = mono_alloc_ireg (cfg);
2412 ins->sreg1 = in->dreg;
2413 MONO_ADD_INS (cfg->cbb, ins);
2415 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2418 case RegTypeStructByAddr:
2421 /* FIXME: where si the data allocated? */
2422 arg->backend.reg3 = ainfo->reg;
2423 call->used_iregs |= 1 << ainfo->reg;
2424 g_assert_not_reached ();
2427 case RegTypeStructByVal:
2428 case RegTypeGSharedVtInReg:
2429 case RegTypeGSharedVtOnStack:
2431 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2432 ins->opcode = OP_OUTARG_VT;
2433 ins->sreg1 = in->dreg;
2434 ins->klass = in->klass;
2435 ins->inst_p0 = call;
2436 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2437 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2438 mono_call_inst_add_outarg_vt (cfg, call, ins);
2439 MONO_ADD_INS (cfg->cbb, ins);
2442 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2443 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2444 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2445 if (t->type == MONO_TYPE_R8) {
2446 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2449 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2451 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2454 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2457 case RegTypeBaseGen:
2458 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2459 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2460 MONO_INST_NEW (cfg, ins, OP_MOVE);
2461 ins->dreg = mono_alloc_ireg (cfg);
2462 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2463 MONO_ADD_INS (cfg->cbb, ins);
2464 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2465 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2468 /* This should work for soft-float as well */
2470 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2471 creg = mono_alloc_ireg (cfg);
2472 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2473 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2474 creg = mono_alloc_ireg (cfg);
2475 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2476 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2477 cfg->flags |= MONO_CFG_HAS_FPOUT;
2479 g_assert_not_reached ();
2483 int fdreg = mono_alloc_freg (cfg);
2485 if (ainfo->size == 8) {
2486 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2487 ins->sreg1 = in->dreg;
2489 MONO_ADD_INS (cfg->cbb, ins);
2491 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2496 * Mono's register allocator doesn't speak single-precision registers that
2497 * overlap double-precision registers (i.e. armhf). So we have to work around
2498 * the register allocator and load the value from memory manually.
2500 * So we create a variable for the float argument and an instruction to store
2501 * the argument into the variable. We then store the list of these arguments
2502 * in cfg->float_args. This list is then used by emit_float_args later to
2503 * pass the arguments in the various call opcodes.
2505 * This is not very nice, and we should really try to fix the allocator.
2508 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2510 /* Make sure the instruction isn't seen as pointless and removed.
2512 float_arg->flags |= MONO_INST_VOLATILE;
2514 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2516 /* We use the dreg to look up the instruction later. The hreg is used to
2517 * emit the instruction that loads the value into the FP reg.
2519 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2520 fad->vreg = float_arg->dreg;
2521 fad->hreg = ainfo->reg;
2523 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2526 call->used_iregs |= 1 << ainfo->reg;
2527 cfg->flags |= MONO_CFG_HAS_FPOUT;
2531 g_assert_not_reached ();
2535 /* Handle the case where there are no implicit arguments */
2536 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2537 emit_sig_cookie (cfg, call, cinfo);
2539 call->call_info = cinfo;
2540 call->stack_usage = cinfo->stack_usage;
2544 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2550 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2551 ins->dreg = mono_alloc_freg (cfg);
2552 ins->sreg1 = arg->dreg;
2553 MONO_ADD_INS (cfg->cbb, ins);
2554 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2557 g_assert_not_reached ();
2563 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2565 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2567 ArgInfo *ainfo = ins->inst_p1;
2568 int ovf_size = ainfo->vtsize;
2569 int doffset = ainfo->offset;
2570 int struct_size = ainfo->struct_size;
2571 int i, soffset, dreg, tmpreg;
2573 switch (ainfo->storage) {
2574 case RegTypeGSharedVtInReg:
2576 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2578 case RegTypeGSharedVtOnStack:
2579 /* Pass by addr on stack */
2580 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2583 for (i = 0; i < ainfo->nregs; ++i) {
2584 if (ainfo->esize == 4)
2585 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2587 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2588 load->dreg = mono_alloc_freg (cfg);
2589 load->inst_basereg = src->dreg;
2590 load->inst_offset = i * ainfo->esize;
2591 MONO_ADD_INS (cfg->cbb, load);
2593 if (ainfo->esize == 4) {
2596 /* See RegTypeFP in mono_arch_emit_call () */
2597 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2598 float_arg->flags |= MONO_INST_VOLATILE;
2599 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2601 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2602 fad->vreg = float_arg->dreg;
2603 fad->hreg = ainfo->reg + i;
2605 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2607 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2613 for (i = 0; i < ainfo->size; ++i) {
2614 dreg = mono_alloc_ireg (cfg);
2615 switch (struct_size) {
2617 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2620 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2623 tmpreg = mono_alloc_ireg (cfg);
2624 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2625 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2626 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2627 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2628 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2629 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2630 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2633 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2636 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2637 soffset += sizeof (gpointer);
2638 struct_size -= sizeof (gpointer);
2640 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2642 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2648 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2650 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2653 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2656 if (COMPILE_LLVM (cfg)) {
2657 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2659 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2660 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2661 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2662 MONO_ADD_INS (cfg->cbb, ins);
2667 case MONO_ARM_FPU_NONE:
2668 if (ret->type == MONO_TYPE_R8) {
2671 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2672 ins->dreg = cfg->ret->dreg;
2673 ins->sreg1 = val->dreg;
2674 MONO_ADD_INS (cfg->cbb, ins);
2677 if (ret->type == MONO_TYPE_R4) {
2678 /* Already converted to an int in method_to_ir () */
2679 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2683 case MONO_ARM_FPU_VFP:
2684 case MONO_ARM_FPU_VFP_HARD:
2685 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2688 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2689 ins->dreg = cfg->ret->dreg;
2690 ins->sreg1 = val->dreg;
2691 MONO_ADD_INS (cfg->cbb, ins);
2696 g_assert_not_reached ();
2700 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2703 #endif /* #ifndef DISABLE_JIT */
2706 mono_arch_is_inst_imm (gint64 imm)
2712 MonoMethodSignature *sig;
2715 MonoType **param_types;
2719 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2723 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2726 switch (cinfo->ret.storage) {
2728 case RegTypeGeneral:
2729 case RegTypeIRegPair:
2730 case RegTypeStructByAddr:
2741 for (i = 0; i < cinfo->nargs; ++i) {
2742 ArgInfo *ainfo = &cinfo->args [i];
2745 switch (ainfo->storage) {
2746 case RegTypeGeneral:
2747 case RegTypeIRegPair:
2748 case RegTypeBaseGen:
2751 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2754 case RegTypeStructByVal:
2755 if (ainfo->size == 0)
2756 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2758 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2759 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2767 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2768 for (i = 0; i < sig->param_count; ++i) {
2769 MonoType *t = sig->params [i];
2774 t = mini_get_underlying_type (t);
2797 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2799 ArchDynCallInfo *info;
2803 cinfo = get_call_info (NULL, sig);
2805 if (!dyn_call_supported (cinfo, sig)) {
2810 info = g_new0 (ArchDynCallInfo, 1);
2811 // FIXME: Preprocess the info to speed up start_dyn_call ()
2813 info->cinfo = cinfo;
2814 info->rtype = mini_get_underlying_type (sig->ret);
2815 info->param_types = g_new0 (MonoType*, sig->param_count);
2816 for (i = 0; i < sig->param_count; ++i)
2817 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2819 return (MonoDynCallInfo*)info;
2823 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2825 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2827 g_free (ainfo->cinfo);
2832 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2834 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2835 DynCallArgs *p = (DynCallArgs*)buf;
2836 int arg_index, greg, i, j, pindex;
2837 MonoMethodSignature *sig = dinfo->sig;
2839 g_assert (buf_len >= sizeof (DynCallArgs));
2848 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2849 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2854 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2855 p->regs [greg ++] = (mgreg_t)ret;
2857 for (i = pindex; i < sig->param_count; i++) {
2858 MonoType *t = dinfo->param_types [i];
2859 gpointer *arg = args [arg_index ++];
2860 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2863 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2865 } else if (ainfo->storage == RegTypeBase) {
2866 slot = PARAM_REGS + (ainfo->offset / 4);
2867 } else if (ainfo->storage == RegTypeBaseGen) {
2868 /* slot + 1 is the first stack slot, so the code below will work */
2871 g_assert_not_reached ();
2875 p->regs [slot] = (mgreg_t)*arg;
2880 case MONO_TYPE_STRING:
2881 case MONO_TYPE_CLASS:
2882 case MONO_TYPE_ARRAY:
2883 case MONO_TYPE_SZARRAY:
2884 case MONO_TYPE_OBJECT:
2888 p->regs [slot] = (mgreg_t)*arg;
2891 p->regs [slot] = *(guint8*)arg;
2894 p->regs [slot] = *(gint8*)arg;
2897 p->regs [slot] = *(gint16*)arg;
2900 p->regs [slot] = *(guint16*)arg;
2903 p->regs [slot] = *(gint32*)arg;
2906 p->regs [slot] = *(guint32*)arg;
2910 p->regs [slot ++] = (mgreg_t)arg [0];
2911 p->regs [slot] = (mgreg_t)arg [1];
2914 p->regs [slot] = *(mgreg_t*)arg;
2917 p->regs [slot ++] = (mgreg_t)arg [0];
2918 p->regs [slot] = (mgreg_t)arg [1];
2920 case MONO_TYPE_GENERICINST:
2921 if (MONO_TYPE_IS_REFERENCE (t)) {
2922 p->regs [slot] = (mgreg_t)*arg;
2925 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2926 MonoClass *klass = mono_class_from_mono_type (t);
2927 guint8 *nullable_buf;
2930 size = mono_class_value_size (klass, NULL);
2931 nullable_buf = g_alloca (size);
2932 g_assert (nullable_buf);
2934 /* The argument pointed to by arg is either a boxed vtype or null */
2935 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2937 arg = (gpointer*)nullable_buf;
2943 case MONO_TYPE_VALUETYPE:
2944 g_assert (ainfo->storage == RegTypeStructByVal);
2946 if (ainfo->size == 0)
2947 slot = PARAM_REGS + (ainfo->offset / 4);
2951 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2952 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2955 g_assert_not_reached ();
2961 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2963 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2964 MonoType *ptype = ainfo->rtype;
2965 guint8 *ret = ((DynCallArgs*)buf)->ret;
2966 mgreg_t res = ((DynCallArgs*)buf)->res;
2967 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2969 switch (ptype->type) {
2970 case MONO_TYPE_VOID:
2971 *(gpointer*)ret = NULL;
2973 case MONO_TYPE_STRING:
2974 case MONO_TYPE_CLASS:
2975 case MONO_TYPE_ARRAY:
2976 case MONO_TYPE_SZARRAY:
2977 case MONO_TYPE_OBJECT:
2981 *(gpointer*)ret = (gpointer)res;
2987 *(guint8*)ret = res;
2990 *(gint16*)ret = res;
2993 *(guint16*)ret = res;
2996 *(gint32*)ret = res;
2999 *(guint32*)ret = res;
3003 /* This handles endianness as well */
3004 ((gint32*)ret) [0] = res;
3005 ((gint32*)ret) [1] = res2;
3007 case MONO_TYPE_GENERICINST:
3008 if (MONO_TYPE_IS_REFERENCE (ptype)) {
3009 *(gpointer*)ret = (gpointer)res;
3014 case MONO_TYPE_VALUETYPE:
3015 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
3020 *(float*)ret = *(float*)&res;
3022 case MONO_TYPE_R8: {
3029 *(double*)ret = *(double*)®s;
3033 g_assert_not_reached ();
3040 * Allow tracing to work with this interface (with an optional argument)
3044 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3048 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3049 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3050 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3051 code = emit_call_reg (code, ARMREG_R2);
3065 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3068 int save_mode = SAVE_NONE;
3070 MonoMethod *method = cfg->method;
3071 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3072 int rtype = ret_type->type;
3073 int save_offset = cfg->param_area;
3077 offset = code - cfg->native_code;
3078 /* we need about 16 instructions */
3079 if (offset > (cfg->code_size - 16 * 4)) {
3080 cfg->code_size *= 2;
3081 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3082 code = cfg->native_code + offset;
3085 case MONO_TYPE_VOID:
3086 /* special case string .ctor icall */
3087 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3088 save_mode = SAVE_ONE;
3090 save_mode = SAVE_NONE;
3094 save_mode = SAVE_TWO;
3098 save_mode = SAVE_ONE_FP;
3100 save_mode = SAVE_ONE;
3104 save_mode = SAVE_TWO_FP;
3106 save_mode = SAVE_TWO;
3108 case MONO_TYPE_GENERICINST:
3109 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3110 save_mode = SAVE_ONE;
3114 case MONO_TYPE_VALUETYPE:
3115 save_mode = SAVE_STRUCT;
3118 save_mode = SAVE_ONE;
3122 switch (save_mode) {
3124 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3125 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3126 if (enable_arguments) {
3127 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3128 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3132 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3133 if (enable_arguments) {
3134 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3138 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3139 if (enable_arguments) {
3140 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3144 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3145 if (enable_arguments) {
3146 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3150 if (enable_arguments) {
3151 /* FIXME: get the actual address */
3152 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3160 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3161 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3162 code = emit_call_reg (code, ARMREG_IP);
3164 switch (save_mode) {
3166 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3167 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3170 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3173 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3176 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3187 * The immediate field for cond branches is big enough for all reasonable methods
3189 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3190 if (0 && ins->inst_true_bb->native_offset) { \
3191 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3193 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3194 ARM_B_COND (code, (condcode), 0); \
3197 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3199 /* emit an exception if condition is fail
3201 * We assign the extra code used to throw the implicit exceptions
3202 * to cfg->bb_exit as far as the big branch handling is concerned
3204 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3206 mono_add_patch_info (cfg, code - cfg->native_code, \
3207 MONO_PATCH_INFO_EXC, exc_name); \
3208 ARM_BL_COND (code, (condcode), 0); \
3211 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3214 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3219 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3223 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3224 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3226 switch (ins->opcode) {
3229 /* Already done by an arch-independent pass */
3231 case OP_LOAD_MEMBASE:
3232 case OP_LOADI4_MEMBASE:
3234 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3235 * OP_LOAD_MEMBASE offset(basereg), reg
3237 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3238 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3239 ins->inst_basereg == last_ins->inst_destbasereg &&
3240 ins->inst_offset == last_ins->inst_offset) {
3241 if (ins->dreg == last_ins->sreg1) {
3242 MONO_DELETE_INS (bb, ins);
3245 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3246 ins->opcode = OP_MOVE;
3247 ins->sreg1 = last_ins->sreg1;
3251 * Note: reg1 must be different from the basereg in the second load
3252 * OP_LOAD_MEMBASE offset(basereg), reg1
3253 * OP_LOAD_MEMBASE offset(basereg), reg2
3255 * OP_LOAD_MEMBASE offset(basereg), reg1
3256 * OP_MOVE reg1, reg2
3258 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3259 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3260 ins->inst_basereg != last_ins->dreg &&
3261 ins->inst_basereg == last_ins->inst_basereg &&
3262 ins->inst_offset == last_ins->inst_offset) {
3264 if (ins->dreg == last_ins->dreg) {
3265 MONO_DELETE_INS (bb, ins);
3268 ins->opcode = OP_MOVE;
3269 ins->sreg1 = last_ins->dreg;
3272 //g_assert_not_reached ();
3276 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3277 * OP_LOAD_MEMBASE offset(basereg), reg
3279 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3280 * OP_ICONST reg, imm
3282 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3283 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3284 ins->inst_basereg == last_ins->inst_destbasereg &&
3285 ins->inst_offset == last_ins->inst_offset) {
3286 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3287 ins->opcode = OP_ICONST;
3288 ins->inst_c0 = last_ins->inst_imm;
3289 g_assert_not_reached (); // check this rule
3293 case OP_LOADU1_MEMBASE:
3294 case OP_LOADI1_MEMBASE:
3295 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3296 ins->inst_basereg == last_ins->inst_destbasereg &&
3297 ins->inst_offset == last_ins->inst_offset) {
3298 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3299 ins->sreg1 = last_ins->sreg1;
3302 case OP_LOADU2_MEMBASE:
3303 case OP_LOADI2_MEMBASE:
3304 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3305 ins->inst_basereg == last_ins->inst_destbasereg &&
3306 ins->inst_offset == last_ins->inst_offset) {
3307 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3308 ins->sreg1 = last_ins->sreg1;
3312 ins->opcode = OP_MOVE;
3316 if (ins->dreg == ins->sreg1) {
3317 MONO_DELETE_INS (bb, ins);
3321 * OP_MOVE sreg, dreg
3322 * OP_MOVE dreg, sreg
3324 if (last_ins && last_ins->opcode == OP_MOVE &&
3325 ins->sreg1 == last_ins->dreg &&
3326 ins->dreg == last_ins->sreg1) {
3327 MONO_DELETE_INS (bb, ins);
3336 * the branch_cc_table should maintain the order of these
3350 branch_cc_table [] = {
3364 #define ADD_NEW_INS(cfg,dest,op) do { \
3365 MONO_INST_NEW ((cfg), (dest), (op)); \
3366 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3370 map_to_reg_reg_op (int op)
3379 case OP_COMPARE_IMM:
3381 case OP_ICOMPARE_IMM:
3395 case OP_LOAD_MEMBASE:
3396 return OP_LOAD_MEMINDEX;
3397 case OP_LOADI4_MEMBASE:
3398 return OP_LOADI4_MEMINDEX;
3399 case OP_LOADU4_MEMBASE:
3400 return OP_LOADU4_MEMINDEX;
3401 case OP_LOADU1_MEMBASE:
3402 return OP_LOADU1_MEMINDEX;
3403 case OP_LOADI2_MEMBASE:
3404 return OP_LOADI2_MEMINDEX;
3405 case OP_LOADU2_MEMBASE:
3406 return OP_LOADU2_MEMINDEX;
3407 case OP_LOADI1_MEMBASE:
3408 return OP_LOADI1_MEMINDEX;
3409 case OP_STOREI1_MEMBASE_REG:
3410 return OP_STOREI1_MEMINDEX;
3411 case OP_STOREI2_MEMBASE_REG:
3412 return OP_STOREI2_MEMINDEX;
3413 case OP_STOREI4_MEMBASE_REG:
3414 return OP_STOREI4_MEMINDEX;
3415 case OP_STORE_MEMBASE_REG:
3416 return OP_STORE_MEMINDEX;
3417 case OP_STORER4_MEMBASE_REG:
3418 return OP_STORER4_MEMINDEX;
3419 case OP_STORER8_MEMBASE_REG:
3420 return OP_STORER8_MEMINDEX;
3421 case OP_STORE_MEMBASE_IMM:
3422 return OP_STORE_MEMBASE_REG;
3423 case OP_STOREI1_MEMBASE_IMM:
3424 return OP_STOREI1_MEMBASE_REG;
3425 case OP_STOREI2_MEMBASE_IMM:
3426 return OP_STOREI2_MEMBASE_REG;
3427 case OP_STOREI4_MEMBASE_IMM:
3428 return OP_STOREI4_MEMBASE_REG;
3430 g_assert_not_reached ();
3434 * Remove from the instruction list the instructions that can't be
3435 * represented with very simple instructions with no register
3439 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3441 MonoInst *ins, *temp, *last_ins = NULL;
3442 int rot_amount, imm8, low_imm;
3444 MONO_BB_FOR_EACH_INS (bb, ins) {
3446 switch (ins->opcode) {
3450 case OP_COMPARE_IMM:
3451 case OP_ICOMPARE_IMM:
3465 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3466 int opcode2 = mono_op_imm_to_op (ins->opcode);
3467 ADD_NEW_INS (cfg, temp, OP_ICONST);
3468 temp->inst_c0 = ins->inst_imm;
3469 temp->dreg = mono_alloc_ireg (cfg);
3470 ins->sreg2 = temp->dreg;
3472 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3473 ins->opcode = opcode2;
3475 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3481 if (ins->inst_imm == 1) {
3482 ins->opcode = OP_MOVE;
3485 if (ins->inst_imm == 0) {
3486 ins->opcode = OP_ICONST;
3490 imm8 = mono_is_power_of_two (ins->inst_imm);
3492 ins->opcode = OP_SHL_IMM;
3493 ins->inst_imm = imm8;
3496 ADD_NEW_INS (cfg, temp, OP_ICONST);
3497 temp->inst_c0 = ins->inst_imm;
3498 temp->dreg = mono_alloc_ireg (cfg);
3499 ins->sreg2 = temp->dreg;
3500 ins->opcode = OP_IMUL;
3506 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3507 /* ARM sets the C flag to 1 if there was _no_ overflow */
3508 ins->next->opcode = OP_COND_EXC_NC;
3511 case OP_IDIV_UN_IMM:
3513 case OP_IREM_UN_IMM: {
3514 int opcode2 = mono_op_imm_to_op (ins->opcode);
3515 ADD_NEW_INS (cfg, temp, OP_ICONST);
3516 temp->inst_c0 = ins->inst_imm;
3517 temp->dreg = mono_alloc_ireg (cfg);
3518 ins->sreg2 = temp->dreg;
3520 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3521 ins->opcode = opcode2;
3524 case OP_LOCALLOC_IMM:
3525 ADD_NEW_INS (cfg, temp, OP_ICONST);
3526 temp->inst_c0 = ins->inst_imm;
3527 temp->dreg = mono_alloc_ireg (cfg);
3528 ins->sreg1 = temp->dreg;
3529 ins->opcode = OP_LOCALLOC;
3531 case OP_LOAD_MEMBASE:
3532 case OP_LOADI4_MEMBASE:
3533 case OP_LOADU4_MEMBASE:
3534 case OP_LOADU1_MEMBASE:
3535 /* we can do two things: load the immed in a register
3536 * and use an indexed load, or see if the immed can be
3537 * represented as an ad_imm + a load with a smaller offset
3538 * that fits. We just do the first for now, optimize later.
3540 if (arm_is_imm12 (ins->inst_offset))
3542 ADD_NEW_INS (cfg, temp, OP_ICONST);
3543 temp->inst_c0 = ins->inst_offset;
3544 temp->dreg = mono_alloc_ireg (cfg);
3545 ins->sreg2 = temp->dreg;
3546 ins->opcode = map_to_reg_reg_op (ins->opcode);
3548 case OP_LOADI2_MEMBASE:
3549 case OP_LOADU2_MEMBASE:
3550 case OP_LOADI1_MEMBASE:
3551 if (arm_is_imm8 (ins->inst_offset))
3553 ADD_NEW_INS (cfg, temp, OP_ICONST);
3554 temp->inst_c0 = ins->inst_offset;
3555 temp->dreg = mono_alloc_ireg (cfg);
3556 ins->sreg2 = temp->dreg;
3557 ins->opcode = map_to_reg_reg_op (ins->opcode);
3559 case OP_LOADR4_MEMBASE:
3560 case OP_LOADR8_MEMBASE:
3561 if (arm_is_fpimm8 (ins->inst_offset))
3563 low_imm = ins->inst_offset & 0x1ff;
3564 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3565 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3566 temp->inst_imm = ins->inst_offset & ~0x1ff;
3567 temp->sreg1 = ins->inst_basereg;
3568 temp->dreg = mono_alloc_ireg (cfg);
3569 ins->inst_basereg = temp->dreg;
3570 ins->inst_offset = low_imm;
3574 ADD_NEW_INS (cfg, temp, OP_ICONST);
3575 temp->inst_c0 = ins->inst_offset;
3576 temp->dreg = mono_alloc_ireg (cfg);
3578 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3579 add_ins->sreg1 = ins->inst_basereg;
3580 add_ins->sreg2 = temp->dreg;
3581 add_ins->dreg = mono_alloc_ireg (cfg);
3583 ins->inst_basereg = add_ins->dreg;
3584 ins->inst_offset = 0;
3587 case OP_STORE_MEMBASE_REG:
3588 case OP_STOREI4_MEMBASE_REG:
3589 case OP_STOREI1_MEMBASE_REG:
3590 if (arm_is_imm12 (ins->inst_offset))
3592 ADD_NEW_INS (cfg, temp, OP_ICONST);
3593 temp->inst_c0 = ins->inst_offset;
3594 temp->dreg = mono_alloc_ireg (cfg);
3595 ins->sreg2 = temp->dreg;
3596 ins->opcode = map_to_reg_reg_op (ins->opcode);
3598 case OP_STOREI2_MEMBASE_REG:
3599 if (arm_is_imm8 (ins->inst_offset))
3601 ADD_NEW_INS (cfg, temp, OP_ICONST);
3602 temp->inst_c0 = ins->inst_offset;
3603 temp->dreg = mono_alloc_ireg (cfg);
3604 ins->sreg2 = temp->dreg;
3605 ins->opcode = map_to_reg_reg_op (ins->opcode);
3607 case OP_STORER4_MEMBASE_REG:
3608 case OP_STORER8_MEMBASE_REG:
3609 if (arm_is_fpimm8 (ins->inst_offset))
3611 low_imm = ins->inst_offset & 0x1ff;
3612 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3613 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3614 temp->inst_imm = ins->inst_offset & ~0x1ff;
3615 temp->sreg1 = ins->inst_destbasereg;
3616 temp->dreg = mono_alloc_ireg (cfg);
3617 ins->inst_destbasereg = temp->dreg;
3618 ins->inst_offset = low_imm;
3622 ADD_NEW_INS (cfg, temp, OP_ICONST);
3623 temp->inst_c0 = ins->inst_offset;
3624 temp->dreg = mono_alloc_ireg (cfg);
3626 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3627 add_ins->sreg1 = ins->inst_destbasereg;
3628 add_ins->sreg2 = temp->dreg;
3629 add_ins->dreg = mono_alloc_ireg (cfg);
3631 ins->inst_destbasereg = add_ins->dreg;
3632 ins->inst_offset = 0;
3635 case OP_STORE_MEMBASE_IMM:
3636 case OP_STOREI1_MEMBASE_IMM:
3637 case OP_STOREI2_MEMBASE_IMM:
3638 case OP_STOREI4_MEMBASE_IMM:
3639 ADD_NEW_INS (cfg, temp, OP_ICONST);
3640 temp->inst_c0 = ins->inst_imm;
3641 temp->dreg = mono_alloc_ireg (cfg);
3642 ins->sreg1 = temp->dreg;
3643 ins->opcode = map_to_reg_reg_op (ins->opcode);
3645 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3648 gboolean swap = FALSE;
3652 /* Optimized away */
3657 /* Some fp compares require swapped operands */
3658 switch (ins->next->opcode) {
3660 ins->next->opcode = OP_FBLT;
3664 ins->next->opcode = OP_FBLT_UN;
3668 ins->next->opcode = OP_FBGE;
3672 ins->next->opcode = OP_FBGE_UN;
3680 ins->sreg1 = ins->sreg2;
3689 bb->last_ins = last_ins;
3690 bb->max_vreg = cfg->next_vreg;
3694 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3698 if (long_ins->opcode == OP_LNEG) {
3700 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3701 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3707 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3709 /* sreg is a float, dreg is an integer reg */
3711 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3713 ARM_TOSIZD (code, vfp_scratch1, sreg);
3715 ARM_TOUIZD (code, vfp_scratch1, sreg);
3716 ARM_FMRS (code, dreg, vfp_scratch1);
3717 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3721 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3722 else if (size == 2) {
3723 ARM_SHL_IMM (code, dreg, dreg, 16);
3724 ARM_SHR_IMM (code, dreg, dreg, 16);
3728 ARM_SHL_IMM (code, dreg, dreg, 24);
3729 ARM_SAR_IMM (code, dreg, dreg, 24);
3730 } else if (size == 2) {
3731 ARM_SHL_IMM (code, dreg, dreg, 16);
3732 ARM_SAR_IMM (code, dreg, dreg, 16);
3739 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3741 /* sreg is a float, dreg is an integer reg */
3743 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3745 ARM_TOSIZS (code, vfp_scratch1, sreg);
3747 ARM_TOUIZS (code, vfp_scratch1, sreg);
3748 ARM_FMRS (code, dreg, vfp_scratch1);
3749 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3753 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3754 else if (size == 2) {
3755 ARM_SHL_IMM (code, dreg, dreg, 16);
3756 ARM_SHR_IMM (code, dreg, dreg, 16);
3760 ARM_SHL_IMM (code, dreg, dreg, 24);
3761 ARM_SAR_IMM (code, dreg, dreg, 24);
3762 } else if (size == 2) {
3763 ARM_SHL_IMM (code, dreg, dreg, 16);
3764 ARM_SAR_IMM (code, dreg, dreg, 16);
3770 #endif /* #ifndef DISABLE_JIT */
3772 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3775 emit_thunk (guint8 *code, gconstpointer target)
3779 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3780 if (thumb_supported)
3781 ARM_BX (code, ARMREG_IP);
3783 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3784 *(guint32*)code = (guint32)target;
3786 mono_arch_flush_icache (p, code - p);
3790 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3792 MonoJitInfo *ji = NULL;
3793 MonoThunkJitInfo *info;
3796 guint8 *orig_target;
3797 guint8 *target_thunk;
3800 domain = mono_domain_get ();
3804 * This can be called multiple times during JITting,
3805 * save the current position in cfg->arch to avoid
3806 * doing a O(n^2) search.
3808 if (!cfg->arch.thunks) {
3809 cfg->arch.thunks = cfg->thunks;
3810 cfg->arch.thunks_size = cfg->thunk_area;
3812 thunks = cfg->arch.thunks;
3813 thunks_size = cfg->arch.thunks_size;
3815 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3816 g_assert_not_reached ();
3819 g_assert (*(guint32*)thunks == 0);
3820 emit_thunk (thunks, target);
3821 arm_patch (code, thunks);
3823 cfg->arch.thunks += THUNK_SIZE;
3824 cfg->arch.thunks_size -= THUNK_SIZE;
3826 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3828 info = mono_jit_info_get_thunk_info (ji);
3831 thunks = (guint8*)ji->code_start + info->thunks_offset;
3832 thunks_size = info->thunks_size;
3834 orig_target = mono_arch_get_call_target (code + 4);
3836 mono_mini_arch_lock ();
3838 target_thunk = NULL;
3839 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3840 /* The call already points to a thunk, because of trampolines etc. */
3841 target_thunk = orig_target;
3843 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3844 if (((guint32*)p) [0] == 0) {
3848 } else if (((guint32*)p) [2] == (guint32)target) {
3849 /* Thunk already points to target */
3856 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3858 if (!target_thunk) {
3859 mono_mini_arch_unlock ();
3860 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3861 g_assert_not_reached ();
3864 emit_thunk (target_thunk, target);
3865 arm_patch (code, target_thunk);
3866 mono_arch_flush_icache (code, 4);
3868 mono_mini_arch_unlock ();
3873 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3875 guint32 *code32 = (void*)code;
3876 guint32 ins = *code32;
3877 guint32 prim = (ins >> 25) & 7;
3878 guint32 tval = GPOINTER_TO_UINT (target);
3880 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3881 if (prim == 5) { /* 101b */
3882 /* the diff starts 8 bytes from the branch opcode */
3883 gint diff = target - code - 8;
3885 gint tmask = 0xffffffff;
3886 if (tval & 1) { /* entering thumb mode */
3887 diff = target - 1 - code - 8;
3888 g_assert (thumb_supported);
3889 tbits = 0xf << 28; /* bl->blx bit pattern */
3890 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3891 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3895 tmask = ~(1 << 24); /* clear the link bit */
3896 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3901 if (diff <= 33554431) {
3903 ins = (ins & 0xff000000) | diff;
3905 *code32 = ins | tbits;
3909 /* diff between 0 and -33554432 */
3910 if (diff >= -33554432) {
3912 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3914 *code32 = ins | tbits;
3919 handle_thunk (cfg, domain, code, target);
3923 #ifdef USE_JUMP_TABLES
3925 gpointer *jte = mono_jumptable_get_entry (code);
3927 jte [0] = (gpointer) target;
3931 * The alternative call sequences looks like this:
3933 * ldr ip, [pc] // loads the address constant
3934 * b 1f // jumps around the constant
3935 * address constant embedded in the code
3940 * There are two cases for patching:
3941 * a) at the end of method emission: in this case code points to the start
3942 * of the call sequence
3943 * b) during runtime patching of the call site: in this case code points
3944 * to the mov pc, ip instruction
3946 * We have to handle also the thunk jump code sequence:
3950 * address constant // execution never reaches here
3952 if ((ins & 0x0ffffff0) == 0x12fff10) {
3953 /* Branch and exchange: the address is constructed in a reg
3954 * We can patch BX when the code sequence is the following:
3955 * ldr ip, [pc, #0] ; 0x8
3962 guint8 *emit = (guint8*)ccode;
3963 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3965 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3966 ARM_BX (emit, ARMREG_IP);
3968 /*patching from magic trampoline*/
3969 if (ins == ccode [3]) {
3970 g_assert (code32 [-4] == ccode [0]);
3971 g_assert (code32 [-3] == ccode [1]);
3972 g_assert (code32 [-1] == ccode [2]);
3973 code32 [-2] = (guint32)target;
3976 /*patching from JIT*/
3977 if (ins == ccode [0]) {
3978 g_assert (code32 [1] == ccode [1]);
3979 g_assert (code32 [3] == ccode [2]);
3980 g_assert (code32 [4] == ccode [3]);
3981 code32 [2] = (guint32)target;
3984 g_assert_not_reached ();
3985 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3993 guint8 *emit = (guint8*)ccode;
3994 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3996 ARM_BLX_REG (emit, ARMREG_IP);
3998 g_assert (code32 [-3] == ccode [0]);
3999 g_assert (code32 [-2] == ccode [1]);
4000 g_assert (code32 [0] == ccode [2]);
4002 code32 [-1] = (guint32)target;
4005 guint32 *tmp = ccode;
4006 guint8 *emit = (guint8*)tmp;
4007 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4008 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4009 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
4010 ARM_BX (emit, ARMREG_IP);
4011 if (ins == ccode [2]) {
4012 g_assert_not_reached (); // should be -2 ...
4013 code32 [-1] = (guint32)target;
4016 if (ins == ccode [0]) {
4017 /* handles both thunk jump code and the far call sequence */
4018 code32 [2] = (guint32)target;
4021 g_assert_not_reached ();
4023 // g_print ("patched with 0x%08x\n", ins);
4028 arm_patch (guchar *code, const guchar *target)
4030 arm_patch_general (NULL, NULL, code, target);
4034 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4035 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4036 * to be used with the emit macros.
4037 * Return -1 otherwise.
4040 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4043 for (i = 0; i < 31; i+= 2) {
4044 res = (val << (32 - i)) | (val >> i);
4047 *rot_amount = i? 32 - i: 0;
4054 * Emits in code a sequence of instructions that load the value 'val'
4055 * into the dreg register. Uses at most 4 instructions.
4058 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4060 int imm8, rot_amount;
4062 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4063 /* skip the constant pool */
4069 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4070 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4071 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4075 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4076 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4077 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4078 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4081 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4083 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4087 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4089 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4091 if (val & 0xFF0000) {
4092 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4094 if (val & 0xFF000000) {
4095 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4097 } else if (val & 0xFF00) {
4098 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4099 if (val & 0xFF0000) {
4100 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4102 if (val & 0xFF000000) {
4103 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4105 } else if (val & 0xFF0000) {
4106 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4107 if (val & 0xFF000000) {
4108 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4111 //g_assert_not_reached ();
4117 mono_arm_thumb_supported (void)
4119 return thumb_supported;
4125 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4130 call = (MonoCallInst*)ins;
4131 cinfo = call->call_info;
4133 switch (cinfo->ret.storage) {
4135 MonoInst *loc = cfg->arch.vret_addr_loc;
4138 /* Load the destination address */
4139 g_assert (loc && loc->opcode == OP_REGOFFSET);
4141 if (arm_is_imm12 (loc->inst_offset)) {
4142 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4144 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4145 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4147 for (i = 0; i < cinfo->ret.nregs; ++i) {
4148 if (cinfo->ret.esize == 4)
4149 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4151 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4159 switch (ins->opcode) {
4162 case OP_FCALL_MEMBASE:
4164 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4165 if (sig_ret->type == MONO_TYPE_R4) {
4166 if (IS_HARD_FLOAT) {
4167 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4169 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4170 ARM_CVTS (code, ins->dreg, ins->dreg);
4173 if (IS_HARD_FLOAT) {
4174 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4176 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4183 case OP_RCALL_MEMBASE: {
4188 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4189 g_assert (sig_ret->type == MONO_TYPE_R4);
4190 if (IS_HARD_FLOAT) {
4191 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4193 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4194 ARM_CPYS (code, ins->dreg, ins->dreg);
4206 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4211 guint8 *code = cfg->native_code + cfg->code_len;
4212 MonoInst *last_ins = NULL;
4213 guint last_offset = 0;
4215 int imm8, rot_amount;
4217 /* we don't align basic blocks of loops on arm */
4219 if (cfg->verbose_level > 2)
4220 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4222 cpos = bb->max_offset;
4224 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4225 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4226 //g_assert (!mono_compile_aot);
4229 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4230 /* this is not thread save, but good enough */
4231 /* fixme: howto handle overflows? */
4232 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4235 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4236 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4237 (gpointer)"mono_break");
4238 code = emit_call_seq (cfg, code);
4241 MONO_BB_FOR_EACH_INS (bb, ins) {
4242 offset = code - cfg->native_code;
4244 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4246 if (offset > (cfg->code_size - max_len - 16)) {
4247 cfg->code_size *= 2;
4248 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4249 code = cfg->native_code + offset;
4251 // if (ins->cil_code)
4252 // g_print ("cil code\n");
4253 mono_debug_record_line_number (cfg, ins, offset);
4255 switch (ins->opcode) {
4256 case OP_MEMORY_BARRIER:
4258 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4259 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4263 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4265 case OP_TLS_GET_REG:
4266 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4269 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4271 case OP_TLS_SET_REG:
4272 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4274 case OP_ATOMIC_EXCHANGE_I4:
4275 case OP_ATOMIC_CAS_I4:
4276 case OP_ATOMIC_ADD_I4: {
4280 g_assert (v7_supported);
4283 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4285 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4287 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4291 g_assert (cfg->arch.atomic_tmp_offset != -1);
4292 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4294 switch (ins->opcode) {
4295 case OP_ATOMIC_EXCHANGE_I4:
4297 ARM_DMB (code, ARM_DMB_SY);
4298 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4299 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4300 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4302 ARM_B_COND (code, ARMCOND_NE, 0);
4303 arm_patch (buf [1], buf [0]);
4305 case OP_ATOMIC_CAS_I4:
4306 ARM_DMB (code, ARM_DMB_SY);
4308 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4309 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4311 ARM_B_COND (code, ARMCOND_NE, 0);
4312 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4313 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4315 ARM_B_COND (code, ARMCOND_NE, 0);
4316 arm_patch (buf [2], buf [0]);
4317 arm_patch (buf [1], code);
4319 case OP_ATOMIC_ADD_I4:
4321 ARM_DMB (code, ARM_DMB_SY);
4322 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4323 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4324 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4325 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4327 ARM_B_COND (code, ARMCOND_NE, 0);
4328 arm_patch (buf [1], buf [0]);
4331 g_assert_not_reached ();
4334 ARM_DMB (code, ARM_DMB_SY);
4335 if (tmpreg != ins->dreg)
4336 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4337 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4340 case OP_ATOMIC_LOAD_I1:
4341 case OP_ATOMIC_LOAD_U1:
4342 case OP_ATOMIC_LOAD_I2:
4343 case OP_ATOMIC_LOAD_U2:
4344 case OP_ATOMIC_LOAD_I4:
4345 case OP_ATOMIC_LOAD_U4:
4346 case OP_ATOMIC_LOAD_R4:
4347 case OP_ATOMIC_LOAD_R8: {
4348 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4349 ARM_DMB (code, ARM_DMB_SY);
4351 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4353 switch (ins->opcode) {
4354 case OP_ATOMIC_LOAD_I1:
4355 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4357 case OP_ATOMIC_LOAD_U1:
4358 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4360 case OP_ATOMIC_LOAD_I2:
4361 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4363 case OP_ATOMIC_LOAD_U2:
4364 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4366 case OP_ATOMIC_LOAD_I4:
4367 case OP_ATOMIC_LOAD_U4:
4368 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4370 case OP_ATOMIC_LOAD_R4:
4372 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4373 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4375 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4376 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4377 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4378 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4379 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4382 case OP_ATOMIC_LOAD_R8:
4383 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4384 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4388 ARM_DMB (code, ARM_DMB_SY);
4391 case OP_ATOMIC_STORE_I1:
4392 case OP_ATOMIC_STORE_U1:
4393 case OP_ATOMIC_STORE_I2:
4394 case OP_ATOMIC_STORE_U2:
4395 case OP_ATOMIC_STORE_I4:
4396 case OP_ATOMIC_STORE_U4:
4397 case OP_ATOMIC_STORE_R4:
4398 case OP_ATOMIC_STORE_R8: {
4399 ARM_DMB (code, ARM_DMB_SY);
4401 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4403 switch (ins->opcode) {
4404 case OP_ATOMIC_STORE_I1:
4405 case OP_ATOMIC_STORE_U1:
4406 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4408 case OP_ATOMIC_STORE_I2:
4409 case OP_ATOMIC_STORE_U2:
4410 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4412 case OP_ATOMIC_STORE_I4:
4413 case OP_ATOMIC_STORE_U4:
4414 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4416 case OP_ATOMIC_STORE_R4:
4418 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4419 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4421 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4422 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4423 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4424 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4425 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4428 case OP_ATOMIC_STORE_R8:
4429 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4430 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4434 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4435 ARM_DMB (code, ARM_DMB_SY);
4439 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4440 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4443 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4444 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4446 case OP_STOREI1_MEMBASE_IMM:
4447 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4448 g_assert (arm_is_imm12 (ins->inst_offset));
4449 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4451 case OP_STOREI2_MEMBASE_IMM:
4452 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4453 g_assert (arm_is_imm8 (ins->inst_offset));
4454 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4456 case OP_STORE_MEMBASE_IMM:
4457 case OP_STOREI4_MEMBASE_IMM:
4458 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4459 g_assert (arm_is_imm12 (ins->inst_offset));
4460 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4462 case OP_STOREI1_MEMBASE_REG:
4463 g_assert (arm_is_imm12 (ins->inst_offset));
4464 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4466 case OP_STOREI2_MEMBASE_REG:
4467 g_assert (arm_is_imm8 (ins->inst_offset));
4468 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4470 case OP_STORE_MEMBASE_REG:
4471 case OP_STOREI4_MEMBASE_REG:
4472 /* this case is special, since it happens for spill code after lowering has been called */
4473 if (arm_is_imm12 (ins->inst_offset)) {
4474 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4476 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4477 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4480 case OP_STOREI1_MEMINDEX:
4481 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4483 case OP_STOREI2_MEMINDEX:
4484 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4486 case OP_STORE_MEMINDEX:
4487 case OP_STOREI4_MEMINDEX:
4488 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4491 g_assert_not_reached ();
4493 case OP_LOAD_MEMINDEX:
4494 case OP_LOADI4_MEMINDEX:
4495 case OP_LOADU4_MEMINDEX:
4496 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4498 case OP_LOADI1_MEMINDEX:
4499 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4501 case OP_LOADU1_MEMINDEX:
4502 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4504 case OP_LOADI2_MEMINDEX:
4505 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4507 case OP_LOADU2_MEMINDEX:
4508 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4510 case OP_LOAD_MEMBASE:
4511 case OP_LOADI4_MEMBASE:
4512 case OP_LOADU4_MEMBASE:
4513 /* this case is special, since it happens for spill code after lowering has been called */
4514 if (arm_is_imm12 (ins->inst_offset)) {
4515 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4517 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4518 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4521 case OP_LOADI1_MEMBASE:
4522 g_assert (arm_is_imm8 (ins->inst_offset));
4523 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4525 case OP_LOADU1_MEMBASE:
4526 g_assert (arm_is_imm12 (ins->inst_offset));
4527 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4529 case OP_LOADU2_MEMBASE:
4530 g_assert (arm_is_imm8 (ins->inst_offset));
4531 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4533 case OP_LOADI2_MEMBASE:
4534 g_assert (arm_is_imm8 (ins->inst_offset));
4535 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4537 case OP_ICONV_TO_I1:
4538 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4539 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4541 case OP_ICONV_TO_I2:
4542 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4543 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4545 case OP_ICONV_TO_U1:
4546 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4548 case OP_ICONV_TO_U2:
4549 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4550 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4554 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4556 case OP_COMPARE_IMM:
4557 case OP_ICOMPARE_IMM:
4558 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4559 g_assert (imm8 >= 0);
4560 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4564 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4565 * So instead of emitting a trap, we emit a call a C function and place a
4568 //*(int*)code = 0xef9f0001;
4571 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4572 (gpointer)"mono_break");
4573 code = emit_call_seq (cfg, code);
4575 case OP_RELAXED_NOP:
4580 case OP_DUMMY_STORE:
4581 case OP_DUMMY_ICONST:
4582 case OP_DUMMY_R8CONST:
4583 case OP_NOT_REACHED:
4586 case OP_IL_SEQ_POINT:
4587 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4589 case OP_SEQ_POINT: {
4591 MonoInst *info_var = cfg->arch.seq_point_info_var;
4592 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4593 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4594 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4596 int dreg = ARMREG_LR;
4598 if (cfg->soft_breakpoints) {
4599 g_assert (!cfg->compile_aot);
4603 * For AOT, we use one got slot per method, which will point to a
4604 * SeqPointInfo structure, containing all the information required
4605 * by the code below.
4607 if (cfg->compile_aot) {
4608 g_assert (info_var);
4609 g_assert (info_var->opcode == OP_REGOFFSET);
4610 g_assert (arm_is_imm12 (info_var->inst_offset));
4613 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4615 * Read from the single stepping trigger page. This will cause a
4616 * SIGSEGV when single stepping is enabled.
4617 * We do this _before_ the breakpoint, so single stepping after
4618 * a breakpoint is hit will step to the next IL offset.
4620 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4623 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4624 if (cfg->soft_breakpoints) {
4625 /* Load the address of the sequence point method variable. */
4626 var = ss_method_var;
4628 g_assert (var->opcode == OP_REGOFFSET);
4629 g_assert (arm_is_imm12 (var->inst_offset));
4630 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4632 /* Read the value and check whether it is non-zero. */
4633 ARM_LDR_IMM (code, dreg, dreg, 0);
4634 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4635 /* Call it conditionally. */
4636 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4638 if (cfg->compile_aot) {
4639 /* Load the trigger page addr from the variable initialized in the prolog */
4640 var = ss_trigger_page_var;
4642 g_assert (var->opcode == OP_REGOFFSET);
4643 g_assert (arm_is_imm12 (var->inst_offset));
4644 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4646 #ifdef USE_JUMP_TABLES
4647 gpointer *jte = mono_jumptable_add_entry ();
4648 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4649 jte [0] = ss_trigger_page;
4651 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4653 *(int*)code = (int)ss_trigger_page;
4657 ARM_LDR_IMM (code, dreg, dreg, 0);
4661 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4663 if (cfg->soft_breakpoints) {
4664 /* Load the address of the breakpoint method into ip. */
4665 var = bp_method_var;
4667 g_assert (var->opcode == OP_REGOFFSET);
4668 g_assert (arm_is_imm12 (var->inst_offset));
4669 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4672 * A placeholder for a possible breakpoint inserted by
4673 * mono_arch_set_breakpoint ().
4676 } else if (cfg->compile_aot) {
4677 guint32 offset = code - cfg->native_code;
4680 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4681 /* Add the offset */
4682 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4683 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4684 if (arm_is_imm12 ((int)val)) {
4685 ARM_LDR_IMM (code, dreg, dreg, val);
4687 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4689 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4691 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4692 g_assert (!(val & 0xFF000000));
4694 ARM_LDR_IMM (code, dreg, dreg, 0);
4696 /* What is faster, a branch or a load ? */
4697 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4698 /* The breakpoint instruction */
4699 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4702 * A placeholder for a possible breakpoint inserted by
4703 * mono_arch_set_breakpoint ().
4705 for (i = 0; i < 4; ++i)
4710 * Add an additional nop so skipping the bp doesn't cause the ip to point
4711 * to another IL offset.
4719 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4722 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4726 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4729 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4730 g_assert (imm8 >= 0);
4731 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4735 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4736 g_assert (imm8 >= 0);
4737 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4741 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4742 g_assert (imm8 >= 0);
4743 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4746 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4747 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4749 case OP_IADD_OVF_UN:
4750 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4751 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4754 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4755 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4757 case OP_ISUB_OVF_UN:
4758 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4759 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4761 case OP_ADD_OVF_CARRY:
4762 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4763 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4765 case OP_ADD_OVF_UN_CARRY:
4766 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4767 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4769 case OP_SUB_OVF_CARRY:
4770 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4771 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4773 case OP_SUB_OVF_UN_CARRY:
4774 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4775 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4779 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4782 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4783 g_assert (imm8 >= 0);
4784 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4787 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4791 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4795 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4796 g_assert (imm8 >= 0);
4797 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4801 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4802 g_assert (imm8 >= 0);
4803 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4805 case OP_ARM_RSBS_IMM:
4806 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4807 g_assert (imm8 >= 0);
4808 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4810 case OP_ARM_RSC_IMM:
4811 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4812 g_assert (imm8 >= 0);
4813 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4816 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4820 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4821 g_assert (imm8 >= 0);
4822 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4825 g_assert (v7s_supported || v7k_supported);
4826 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4829 g_assert (v7s_supported || v7k_supported);
4830 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4833 g_assert (v7s_supported || v7k_supported);
4834 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4835 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4838 g_assert (v7s_supported || v7k_supported);
4839 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4840 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4844 g_assert_not_reached ();
4846 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4850 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4851 g_assert (imm8 >= 0);
4852 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4855 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4859 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4860 g_assert (imm8 >= 0);
4861 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4864 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4869 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4870 else if (ins->dreg != ins->sreg1)
4871 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4874 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4879 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4880 else if (ins->dreg != ins->sreg1)
4881 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4884 case OP_ISHR_UN_IMM:
4886 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4887 else if (ins->dreg != ins->sreg1)
4888 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4891 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4894 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4897 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4900 if (ins->dreg == ins->sreg2)
4901 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4903 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4906 g_assert_not_reached ();
4909 /* FIXME: handle ovf/ sreg2 != dreg */
4910 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4911 /* FIXME: MUL doesn't set the C/O flags on ARM */
4913 case OP_IMUL_OVF_UN:
4914 /* FIXME: handle ovf/ sreg2 != dreg */
4915 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4916 /* FIXME: MUL doesn't set the C/O flags on ARM */
4919 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4922 /* Load the GOT offset */
4923 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4924 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4926 *(gpointer*)code = NULL;
4928 /* Load the value from the GOT */
4929 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4931 case OP_OBJC_GET_SELECTOR:
4932 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4933 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4935 *(gpointer*)code = NULL;
4937 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4939 case OP_ICONV_TO_I4:
4940 case OP_ICONV_TO_U4:
4942 if (ins->dreg != ins->sreg1)
4943 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4946 int saved = ins->sreg2;
4947 if (ins->sreg2 == ARM_LSW_REG) {
4948 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4951 if (ins->sreg1 != ARM_LSW_REG)
4952 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4953 if (saved != ARM_MSW_REG)
4954 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4958 if (IS_VFP && ins->dreg != ins->sreg1)
4959 ARM_CPYD (code, ins->dreg, ins->sreg1);
4962 if (IS_VFP && ins->dreg != ins->sreg1)
4963 ARM_CPYS (code, ins->dreg, ins->sreg1);
4965 case OP_MOVE_F_TO_I4:
4967 ARM_FMRS (code, ins->dreg, ins->sreg1);
4969 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4970 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4971 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4972 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4975 case OP_MOVE_I4_TO_F:
4977 ARM_FMSR (code, ins->dreg, ins->sreg1);
4979 ARM_FMSR (code, ins->dreg, ins->sreg1);
4980 ARM_CVTS (code, ins->dreg, ins->dreg);
4983 case OP_FCONV_TO_R4:
4986 ARM_CVTD (code, ins->dreg, ins->sreg1);
4988 ARM_CVTD (code, ins->dreg, ins->sreg1);
4989 ARM_CVTS (code, ins->dreg, ins->dreg);
4994 MonoCallInst *call = (MonoCallInst*)ins;
4997 * The stack looks like the following:
4998 * <caller argument area>
5001 * <callee argument area>
5002 * Need to copy the arguments from the callee argument area to
5003 * the caller argument area, and pop the frame.
5005 if (call->stack_usage) {
5006 int i, prev_sp_offset = 0;
5008 /* Compute size of saved registers restored below */
5010 prev_sp_offset = 2 * 4;
5012 prev_sp_offset = 1 * 4;
5013 for (i = 0; i < 16; ++i) {
5014 if (cfg->used_int_regs & (1 << i))
5015 prev_sp_offset += 4;
5018 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5020 /* Copy arguments on the stack to our argument area */
5021 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5022 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5023 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5028 * Keep in sync with mono_arch_emit_epilog
5030 g_assert (!cfg->method->save_lmf);
5032 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5034 if (cfg->used_int_regs)
5035 ARM_POP (code, cfg->used_int_regs);
5036 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5038 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5041 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5042 if (cfg->compile_aot) {
5043 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5045 *(gpointer*)code = NULL;
5047 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5049 code = mono_arm_patchable_b (code, ARMCOND_AL);
5050 cfg->thunk_area += THUNK_SIZE;
5055 /* ensure ins->sreg1 is not NULL */
5056 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5059 g_assert (cfg->sig_cookie < 128);
5060 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5061 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5071 call = (MonoCallInst*)ins;
5074 code = emit_float_args (cfg, call, code, &max_len, &offset);
5076 if (ins->flags & MONO_INST_HAS_METHOD)
5077 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5079 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5080 code = emit_call_seq (cfg, code);
5081 ins->flags |= MONO_INST_GC_CALLSITE;
5082 ins->backend.pc_offset = code - cfg->native_code;
5083 code = emit_move_return_value (cfg, ins, code);
5090 case OP_VOIDCALL_REG:
5093 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5095 code = emit_call_reg (code, ins->sreg1);
5096 ins->flags |= MONO_INST_GC_CALLSITE;
5097 ins->backend.pc_offset = code - cfg->native_code;
5098 code = emit_move_return_value (cfg, ins, code);
5100 case OP_FCALL_MEMBASE:
5101 case OP_RCALL_MEMBASE:
5102 case OP_LCALL_MEMBASE:
5103 case OP_VCALL_MEMBASE:
5104 case OP_VCALL2_MEMBASE:
5105 case OP_VOIDCALL_MEMBASE:
5106 case OP_CALL_MEMBASE: {
5107 g_assert (ins->sreg1 != ARMREG_LR);
5108 call = (MonoCallInst*)ins;
5111 code = emit_float_args (cfg, call, code, &max_len, &offset);
5112 if (!arm_is_imm12 (ins->inst_offset))
5113 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5114 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5115 if (!arm_is_imm12 (ins->inst_offset))
5116 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5118 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5119 ins->flags |= MONO_INST_GC_CALLSITE;
5120 ins->backend.pc_offset = code - cfg->native_code;
5121 code = emit_move_return_value (cfg, ins, code);
5124 case OP_GENERIC_CLASS_INIT: {
5125 static int byte_offset = -1;
5126 static guint8 bitmask;
5130 if (byte_offset < 0)
5131 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5133 g_assert (arm_is_imm8 (byte_offset));
5134 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5135 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5136 g_assert (imm8 >= 0);
5137 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5138 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5140 ARM_B_COND (code, ARMCOND_NE, 0);
5142 /* Uninitialized case */
5143 g_assert (ins->sreg1 == ARMREG_R0);
5145 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5146 (gpointer)"mono_generic_class_init");
5147 code = emit_call_seq (cfg, code);
5149 /* Initialized case */
5150 arm_patch (jump, code);
5154 /* round the size to 8 bytes */
5155 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5156 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5157 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5158 /* memzero the area: dreg holds the size, sp is the pointer */
5159 if (ins->flags & MONO_INST_INIT) {
5160 guint8 *start_loop, *branch_to_cond;
5161 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5162 branch_to_cond = code;
5165 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5166 arm_patch (branch_to_cond, code);
5167 /* decrement by 4 and set flags */
5168 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5169 ARM_B_COND (code, ARMCOND_GE, 0);
5170 arm_patch (code - 4, start_loop);
5172 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5173 if (cfg->param_area)
5174 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5179 MonoInst *var = cfg->dyn_call_var;
5181 g_assert (var->opcode == OP_REGOFFSET);
5182 g_assert (arm_is_imm12 (var->inst_offset));
5184 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5185 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5187 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5189 /* Save args buffer */
5190 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5192 /* Set stack slots using R0 as scratch reg */
5193 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5194 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5195 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5196 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5199 /* Set argument registers */
5200 for (i = 0; i < PARAM_REGS; ++i)
5201 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5204 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5205 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5208 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5209 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5210 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5214 if (ins->sreg1 != ARMREG_R0)
5215 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5216 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5217 (gpointer)"mono_arch_throw_exception");
5218 code = emit_call_seq (cfg, code);
5222 if (ins->sreg1 != ARMREG_R0)
5223 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5224 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5225 (gpointer)"mono_arch_rethrow_exception");
5226 code = emit_call_seq (cfg, code);
5229 case OP_START_HANDLER: {
5230 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5231 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5234 /* Reserve a param area, see filter-stack.exe */
5236 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5237 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5239 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5240 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5244 if (arm_is_imm12 (spvar->inst_offset)) {
5245 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5247 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5248 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5252 case OP_ENDFILTER: {
5253 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5254 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5257 /* Free the param area */
5259 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5260 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5262 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5263 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5267 if (ins->sreg1 != ARMREG_R0)
5268 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5269 if (arm_is_imm12 (spvar->inst_offset)) {
5270 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5272 g_assert (ARMREG_IP != spvar->inst_basereg);
5273 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5274 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5276 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5279 case OP_ENDFINALLY: {
5280 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5281 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5284 /* Free the param area */
5286 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5287 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5289 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5290 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5294 if (arm_is_imm12 (spvar->inst_offset)) {
5295 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5297 g_assert (ARMREG_IP != spvar->inst_basereg);
5298 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5299 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5301 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5304 case OP_CALL_HANDLER:
5305 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5306 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5307 cfg->thunk_area += THUNK_SIZE;
5308 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5311 if (ins->dreg != ARMREG_R0)
5312 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5316 ins->inst_c0 = code - cfg->native_code;
5319 /*if (ins->inst_target_bb->native_offset) {
5321 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5323 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5324 code = mono_arm_patchable_b (code, ARMCOND_AL);
5328 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5332 * In the normal case we have:
5333 * ldr pc, [pc, ins->sreg1 << 2]
5336 * ldr lr, [pc, ins->sreg1 << 2]
5338 * After follows the data.
5339 * FIXME: add aot support.
5341 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5342 #ifdef USE_JUMP_TABLES
5344 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5345 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5346 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5350 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5351 if (offset + max_len > (cfg->code_size - 16)) {
5352 cfg->code_size += max_len;
5353 cfg->code_size *= 2;
5354 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5355 code = cfg->native_code + offset;
5357 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5359 code += 4 * GPOINTER_TO_INT (ins->klass);
5364 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5365 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5369 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5370 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5374 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5375 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5379 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5380 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5384 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5385 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5388 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5389 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5392 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5393 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5396 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5397 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5400 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5401 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5404 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5405 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5407 case OP_COND_EXC_EQ:
5408 case OP_COND_EXC_NE_UN:
5409 case OP_COND_EXC_LT:
5410 case OP_COND_EXC_LT_UN:
5411 case OP_COND_EXC_GT:
5412 case OP_COND_EXC_GT_UN:
5413 case OP_COND_EXC_GE:
5414 case OP_COND_EXC_GE_UN:
5415 case OP_COND_EXC_LE:
5416 case OP_COND_EXC_LE_UN:
5417 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5419 case OP_COND_EXC_IEQ:
5420 case OP_COND_EXC_INE_UN:
5421 case OP_COND_EXC_ILT:
5422 case OP_COND_EXC_ILT_UN:
5423 case OP_COND_EXC_IGT:
5424 case OP_COND_EXC_IGT_UN:
5425 case OP_COND_EXC_IGE:
5426 case OP_COND_EXC_IGE_UN:
5427 case OP_COND_EXC_ILE:
5428 case OP_COND_EXC_ILE_UN:
5429 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5432 case OP_COND_EXC_IC:
5433 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5435 case OP_COND_EXC_OV:
5436 case OP_COND_EXC_IOV:
5437 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5439 case OP_COND_EXC_NC:
5440 case OP_COND_EXC_INC:
5441 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5443 case OP_COND_EXC_NO:
5444 case OP_COND_EXC_INO:
5445 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5457 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5460 /* floating point opcodes */
5462 if (cfg->compile_aot) {
5463 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5465 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5467 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5470 /* FIXME: we can optimize the imm load by dealing with part of
5471 * the displacement in LDFD (aligning to 512).
5473 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5474 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5478 if (cfg->compile_aot) {
5479 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5481 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5484 ARM_CVTS (code, ins->dreg, ins->dreg);
5486 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5487 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5489 ARM_CVTS (code, ins->dreg, ins->dreg);
5492 case OP_STORER8_MEMBASE_REG:
5493 /* This is generated by the local regalloc pass which runs after the lowering pass */
5494 if (!arm_is_fpimm8 (ins->inst_offset)) {
5495 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5496 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5497 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5499 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5502 case OP_LOADR8_MEMBASE:
5503 /* This is generated by the local regalloc pass which runs after the lowering pass */
5504 if (!arm_is_fpimm8 (ins->inst_offset)) {
5505 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5506 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5507 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5509 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5512 case OP_STORER4_MEMBASE_REG:
5513 g_assert (arm_is_fpimm8 (ins->inst_offset));
5515 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5517 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5518 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5519 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5520 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5523 case OP_LOADR4_MEMBASE:
5525 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5527 g_assert (arm_is_fpimm8 (ins->inst_offset));
5528 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5529 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5530 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5531 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5534 case OP_ICONV_TO_R_UN: {
5535 g_assert_not_reached ();
5538 case OP_ICONV_TO_R4:
5540 ARM_FMSR (code, ins->dreg, ins->sreg1);
5541 ARM_FSITOS (code, ins->dreg, ins->dreg);
5543 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5544 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5545 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5546 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5547 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5550 case OP_ICONV_TO_R8:
5551 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5552 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5553 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5554 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5558 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5559 if (sig_ret->type == MONO_TYPE_R4) {
5561 g_assert (!IS_HARD_FLOAT);
5562 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5564 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5567 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5571 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5573 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5577 case OP_FCONV_TO_I1:
5578 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5580 case OP_FCONV_TO_U1:
5581 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5583 case OP_FCONV_TO_I2:
5584 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5586 case OP_FCONV_TO_U2:
5587 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5589 case OP_FCONV_TO_I4:
5591 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5593 case OP_FCONV_TO_U4:
5595 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5597 case OP_FCONV_TO_I8:
5598 case OP_FCONV_TO_U8:
5599 g_assert_not_reached ();
5600 /* Implemented as helper calls */
5602 case OP_LCONV_TO_R_UN:
5603 g_assert_not_reached ();
5604 /* Implemented as helper calls */
5606 case OP_LCONV_TO_OVF_I4_2: {
5607 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5609 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5612 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5613 high_bit_not_set = code;
5614 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5616 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5617 valid_negative = code;
5618 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5619 invalid_negative = code;
5620 ARM_B_COND (code, ARMCOND_AL, 0);
5622 arm_patch (high_bit_not_set, code);
5624 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5625 valid_positive = code;
5626 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5628 arm_patch (invalid_negative, code);
5629 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5631 arm_patch (valid_negative, code);
5632 arm_patch (valid_positive, code);
5634 if (ins->dreg != ins->sreg1)
5635 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5639 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5642 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5645 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5648 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5651 ARM_NEGD (code, ins->dreg, ins->sreg1);
5655 g_assert_not_reached ();
5659 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5665 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5670 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5673 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5674 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5678 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5681 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5682 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5686 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5689 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5690 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5691 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5695 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5698 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5699 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5703 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5706 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5707 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5708 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5712 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5715 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5716 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5720 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5723 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5724 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5728 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5731 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5732 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5735 /* ARM FPA flags table:
5736 * N Less than ARMCOND_MI
5737 * Z Equal ARMCOND_EQ
5738 * C Greater Than or Equal ARMCOND_CS
5739 * V Unordered ARMCOND_VS
5742 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5745 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5748 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5751 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5752 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5758 g_assert_not_reached ();
5762 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5764 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5765 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5766 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5770 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5771 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5776 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5777 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5779 #ifdef USE_JUMP_TABLES
5781 gpointer *jte = mono_jumptable_add_entries (2);
5782 jte [0] = GUINT_TO_POINTER (0xffffffff);
5783 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5784 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5785 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5788 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5789 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5791 *(guint32*)code = 0xffffffff;
5793 *(guint32*)code = 0x7fefffff;
5796 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5798 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5799 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5801 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5802 ARM_CPYD (code, ins->dreg, ins->sreg1);
5804 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5805 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5810 case OP_RCONV_TO_I1:
5811 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5813 case OP_RCONV_TO_U1:
5814 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5816 case OP_RCONV_TO_I2:
5817 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5819 case OP_RCONV_TO_U2:
5820 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5822 case OP_RCONV_TO_I4:
5823 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5825 case OP_RCONV_TO_U4:
5826 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5828 case OP_RCONV_TO_R4:
5830 if (ins->dreg != ins->sreg1)
5831 ARM_CPYS (code, ins->dreg, ins->sreg1);
5833 case OP_RCONV_TO_R8:
5835 ARM_CVTS (code, ins->dreg, ins->sreg1);
5838 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5841 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5844 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5847 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5850 ARM_NEGS (code, ins->dreg, ins->sreg1);
5854 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5857 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5858 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5862 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5865 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5866 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5870 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5873 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5874 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5875 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5879 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5882 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5883 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5887 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5890 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5891 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5892 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5896 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5899 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5900 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5904 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5907 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5908 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5912 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5915 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5916 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5919 case OP_GC_LIVENESS_DEF:
5920 case OP_GC_LIVENESS_USE:
5921 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5922 ins->backend.pc_offset = code - cfg->native_code;
5924 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5925 ins->backend.pc_offset = code - cfg->native_code;
5926 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5928 case OP_GC_SAFE_POINT: {
5929 const char *polling_func = NULL;
5932 g_assert (mono_threads_is_coop_enabled ());
5934 polling_func = "mono_threads_state_poll";
5935 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5936 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5938 ARM_B_COND (code, ARMCOND_EQ, 0);
5939 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5940 code = emit_call_seq (cfg, code);
5941 arm_patch (buf [0], code);
5946 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5947 g_assert_not_reached ();
5950 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5951 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5952 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5953 g_assert_not_reached ();
5959 last_offset = offset;
5962 cfg->code_len = code - cfg->native_code;
5965 #endif /* DISABLE_JIT */
5968 mono_arch_register_lowlevel_calls (void)
5970 /* The signature doesn't matter */
5971 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5972 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5973 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5975 #ifndef MONO_CROSS_COMPILE
5976 if (mono_arm_have_tls_get ()) {
5977 MonoTlsImplementation tls_imp = mono_arm_get_tls_implementation ();
5979 mono_register_jit_icall (tls_imp.get_tls_thunk, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
5980 mono_register_jit_icall (tls_imp.set_tls_thunk, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
5982 if (tls_imp.get_tls_thunk_end) {
5983 mono_tramp_info_register (
5984 mono_tramp_info_create (
5986 (guint8*)tls_imp.get_tls_thunk,
5987 (guint8*)tls_imp.get_tls_thunk_end - (guint8*)tls_imp.get_tls_thunk,
5989 mono_arch_get_cie_program ()
5993 mono_tramp_info_register (
5994 mono_tramp_info_create (
5996 (guint8*)tls_imp.set_tls_thunk,
5997 (guint8*)tls_imp.set_tls_thunk_end - (guint8*)tls_imp.set_tls_thunk,
5999 mono_arch_get_cie_program ()
6008 #define patch_lis_ori(ip,val) do {\
6009 guint16 *__lis_ori = (guint16*)(ip); \
6010 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
6011 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
6015 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6017 unsigned char *ip = ji->ip.i + code;
6019 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6023 case MONO_PATCH_INFO_SWITCH: {
6024 #ifdef USE_JUMP_TABLES
6025 gpointer *jt = mono_jumptable_get_entry (ip);
6027 gpointer *jt = (gpointer*)(ip + 8);
6030 /* jt is the inlined jump table, 2 instructions after ip
6031 * In the normal case we store the absolute addresses,
6032 * otherwise the displacements.
6034 for (i = 0; i < ji->data.table->table_size; i++)
6035 jt [i] = code + (int)ji->data.table->table [i];
6038 case MONO_PATCH_INFO_IP:
6039 g_assert_not_reached ();
6040 patch_lis_ori (ip, ip);
6042 case MONO_PATCH_INFO_METHOD_REL:
6043 g_assert_not_reached ();
6044 *((gpointer *)(ip)) = target;
6046 case MONO_PATCH_INFO_METHODCONST:
6047 case MONO_PATCH_INFO_CLASS:
6048 case MONO_PATCH_INFO_IMAGE:
6049 case MONO_PATCH_INFO_FIELD:
6050 case MONO_PATCH_INFO_VTABLE:
6051 case MONO_PATCH_INFO_IID:
6052 case MONO_PATCH_INFO_SFLDA:
6053 case MONO_PATCH_INFO_LDSTR:
6054 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6055 case MONO_PATCH_INFO_LDTOKEN:
6056 g_assert_not_reached ();
6057 /* from OP_AOTCONST : lis + ori */
6058 patch_lis_ori (ip, target);
6060 case MONO_PATCH_INFO_R4:
6061 case MONO_PATCH_INFO_R8:
6062 g_assert_not_reached ();
6063 *((gconstpointer *)(ip + 2)) = target;
6065 case MONO_PATCH_INFO_EXC_NAME:
6066 g_assert_not_reached ();
6067 *((gconstpointer *)(ip + 1)) = target;
6069 case MONO_PATCH_INFO_NONE:
6070 case MONO_PATCH_INFO_BB_OVF:
6071 case MONO_PATCH_INFO_EXC_OVF:
6072 /* everything is dealt with at epilog output time */
6075 arm_patch_general (cfg, domain, ip, target);
6081 mono_arm_unaligned_stack (MonoMethod *method)
6083 g_assert_not_reached ();
6089 * Stack frame layout:
6091 * ------------------- fp
6092 * MonoLMF structure or saved registers
6093 * -------------------
6095 * -------------------
6097 * -------------------
6098 * optional 8 bytes for tracing
6099 * -------------------
6100 * param area size is cfg->param_area
6101 * ------------------- sp
6104 mono_arch_emit_prolog (MonoCompile *cfg)
6106 MonoMethod *method = cfg->method;
6108 MonoMethodSignature *sig;
6110 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6115 int prev_sp_offset, reg_offset;
6117 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6120 sig = mono_method_signature (method);
6121 cfg->code_size = 256 + sig->param_count * 64;
6122 code = cfg->native_code = g_malloc (cfg->code_size);
6124 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6126 alloc_size = cfg->stack_offset;
6132 * The iphone uses R7 as the frame pointer, and it points at the saved
6137 * We can't use r7 as a frame pointer since it points into the middle of
6138 * the frame, so we keep using our own frame pointer.
6139 * FIXME: Optimize this.
6141 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6142 prev_sp_offset += 8; /* r7 and lr */
6143 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6144 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6145 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6148 if (!method->save_lmf) {
6150 /* No need to push LR again */
6151 if (cfg->used_int_regs)
6152 ARM_PUSH (code, cfg->used_int_regs);
6154 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6155 prev_sp_offset += 4;
6157 for (i = 0; i < 16; ++i) {
6158 if (cfg->used_int_regs & (1 << i))
6159 prev_sp_offset += 4;
6161 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6163 for (i = 0; i < 16; ++i) {
6164 if ((cfg->used_int_regs & (1 << i))) {
6165 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6166 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6171 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6172 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6174 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6175 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6178 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6179 ARM_PUSH (code, 0x5ff0);
6180 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6181 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6183 for (i = 0; i < 16; ++i) {
6184 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6185 /* The original r7 is saved at the start */
6186 if (!(iphone_abi && i == ARMREG_R7))
6187 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6191 g_assert (reg_offset == 4 * 10);
6192 pos += sizeof (MonoLMF) - (4 * 10);
6196 orig_alloc_size = alloc_size;
6197 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6198 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6199 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6200 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6203 /* the stack used in the pushed regs */
6204 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6205 cfg->stack_usage = alloc_size;
6207 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6208 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6210 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6211 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6213 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6215 if (cfg->frame_reg != ARMREG_SP) {
6216 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6217 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6219 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6220 prev_sp_offset += alloc_size;
6222 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6223 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6225 /* compute max_offset in order to use short forward jumps
6226 * we could skip do it on arm because the immediate displacement
6227 * for jumps is large enough, it may be useful later for constant pools
6230 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6231 MonoInst *ins = bb->code;
6232 bb->max_offset = max_offset;
6234 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6237 MONO_BB_FOR_EACH_INS (bb, ins)
6238 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6241 /* stack alignment check */
6245 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6246 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6247 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6248 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6250 ARM_B_COND (code, ARMCOND_EQ, 0);
6251 if (cfg->compile_aot)
6252 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6254 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6255 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6256 code = emit_call_seq (cfg, code);
6257 arm_patch (buf [0], code);
6261 /* store runtime generic context */
6262 if (cfg->rgctx_var) {
6263 MonoInst *ins = cfg->rgctx_var;
6265 g_assert (ins->opcode == OP_REGOFFSET);
6267 if (arm_is_imm12 (ins->inst_offset)) {
6268 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6270 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6271 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6275 /* load arguments allocated to register from the stack */
6278 cinfo = get_call_info (NULL, sig);
6280 if (cinfo->ret.storage == RegTypeStructByAddr) {
6281 ArgInfo *ainfo = &cinfo->ret;
6282 inst = cfg->vret_addr;
6283 g_assert (arm_is_imm12 (inst->inst_offset));
6284 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6287 if (sig->call_convention == MONO_CALL_VARARG) {
6288 ArgInfo *cookie = &cinfo->sig_cookie;
6290 /* Save the sig cookie address */
6291 g_assert (cookie->storage == RegTypeBase);
6293 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6294 g_assert (arm_is_imm12 (cfg->sig_cookie));
6295 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6296 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6299 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6300 ArgInfo *ainfo = cinfo->args + i;
6301 inst = cfg->args [pos];
6303 if (cfg->verbose_level > 2)
6304 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6306 if (inst->opcode == OP_REGVAR) {
6307 if (ainfo->storage == RegTypeGeneral)
6308 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6309 else if (ainfo->storage == RegTypeFP) {
6310 g_assert_not_reached ();
6311 } else if (ainfo->storage == RegTypeBase) {
6312 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6313 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6315 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6316 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6319 g_assert_not_reached ();
6321 if (cfg->verbose_level > 2)
6322 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6324 switch (ainfo->storage) {
6326 for (part = 0; part < ainfo->nregs; part ++) {
6327 if (ainfo->esize == 4)
6328 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6330 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6333 case RegTypeGeneral:
6334 case RegTypeIRegPair:
6335 case RegTypeGSharedVtInReg:
6336 switch (ainfo->size) {
6338 if (arm_is_imm12 (inst->inst_offset))
6339 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6341 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6342 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6346 if (arm_is_imm8 (inst->inst_offset)) {
6347 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6349 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6350 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6354 if (arm_is_imm12 (inst->inst_offset)) {
6355 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6357 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6358 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6360 if (arm_is_imm12 (inst->inst_offset + 4)) {
6361 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6363 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6364 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6368 if (arm_is_imm12 (inst->inst_offset)) {
6369 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6371 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6372 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6377 case RegTypeBaseGen:
6378 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6379 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6381 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6382 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6384 if (arm_is_imm12 (inst->inst_offset + 4)) {
6385 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6386 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6388 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6389 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6390 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6391 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6395 case RegTypeGSharedVtOnStack:
6396 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6397 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6399 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6400 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6403 switch (ainfo->size) {
6405 if (arm_is_imm8 (inst->inst_offset)) {
6406 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6408 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6409 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6413 if (arm_is_imm8 (inst->inst_offset)) {
6414 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6416 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6417 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6421 if (arm_is_imm12 (inst->inst_offset)) {
6422 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6424 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6425 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6427 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6428 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6430 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6431 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6433 if (arm_is_imm12 (inst->inst_offset + 4)) {
6434 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6436 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6437 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6441 if (arm_is_imm12 (inst->inst_offset)) {
6442 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6444 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6445 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6451 int imm8, rot_amount;
6453 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6454 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6455 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6457 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6459 if (ainfo->size == 8)
6460 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6462 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6465 case RegTypeStructByVal: {
6466 int doffset = inst->inst_offset;
6470 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6471 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6472 if (arm_is_imm12 (doffset)) {
6473 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6475 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6476 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6478 soffset += sizeof (gpointer);
6479 doffset += sizeof (gpointer);
6481 if (ainfo->vtsize) {
6482 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6483 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6484 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6488 case RegTypeStructByAddr:
6489 g_assert_not_reached ();
6490 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6491 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6493 g_assert_not_reached ();
6500 if (method->save_lmf)
6501 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6504 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6506 if (cfg->arch.seq_point_info_var) {
6507 MonoInst *ins = cfg->arch.seq_point_info_var;
6509 /* Initialize the variable from a GOT slot */
6510 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6511 #ifdef USE_JUMP_TABLES
6513 gpointer *jte = mono_jumptable_add_entry ();
6514 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6515 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6517 /** XXX: is it correct? */
6519 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6521 *(gpointer*)code = NULL;
6524 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6526 g_assert (ins->opcode == OP_REGOFFSET);
6528 if (arm_is_imm12 (ins->inst_offset)) {
6529 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6531 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6532 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6536 /* Initialize ss_trigger_page_var */
6537 if (!cfg->soft_breakpoints) {
6538 MonoInst *info_var = cfg->arch.seq_point_info_var;
6539 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6540 int dreg = ARMREG_LR;
6543 g_assert (info_var->opcode == OP_REGOFFSET);
6544 g_assert (arm_is_imm12 (info_var->inst_offset));
6546 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6547 /* Load the trigger page addr */
6548 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6549 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6553 if (cfg->arch.seq_point_ss_method_var) {
6554 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6555 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6556 #ifdef USE_JUMP_TABLES
6559 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6560 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6561 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6562 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6564 #ifdef USE_JUMP_TABLES
6565 jte = mono_jumptable_add_entries (3);
6566 jte [0] = &single_step_tramp;
6567 jte [1] = breakpoint_tramp;
6568 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6570 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6572 *(gpointer*)code = &single_step_tramp;
6574 *(gpointer*)code = breakpoint_tramp;
6578 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6579 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6580 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6581 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6584 cfg->code_len = code - cfg->native_code;
6585 g_assert (cfg->code_len < cfg->code_size);
6592 mono_arch_emit_epilog (MonoCompile *cfg)
6594 MonoMethod *method = cfg->method;
6595 int pos, i, rot_amount;
6596 int max_epilog_size = 16 + 20*4;
6600 if (cfg->method->save_lmf)
6601 max_epilog_size += 128;
6603 if (mono_jit_trace_calls != NULL)
6604 max_epilog_size += 50;
6606 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6607 max_epilog_size += 50;
6609 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6610 cfg->code_size *= 2;
6611 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6612 cfg->stat_code_reallocs++;
6616 * Keep in sync with OP_JMP
6618 code = cfg->native_code + cfg->code_len;
6620 /* Save the uwind state which is needed by the out-of-line code */
6621 mono_emit_unwind_op_remember_state (cfg, code);
6623 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6624 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6628 /* Load returned vtypes into registers if needed */
6629 cinfo = cfg->arch.cinfo;
6630 switch (cinfo->ret.storage) {
6631 case RegTypeStructByVal: {
6632 MonoInst *ins = cfg->ret;
6634 if (arm_is_imm12 (ins->inst_offset)) {
6635 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6637 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6638 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6643 MonoInst *ins = cfg->ret;
6645 for (i = 0; i < cinfo->ret.nregs; ++i) {
6646 if (cinfo->ret.esize == 4)
6647 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6649 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6657 if (method->save_lmf) {
6658 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6659 /* all but r0-r3, sp and pc */
6660 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6663 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6665 /* This points to r4 inside MonoLMF->iregs */
6666 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6668 regmask = 0x9ff0; /* restore lr to pc */
6669 /* Skip caller saved registers not used by the method */
6670 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6671 regmask &= ~(1 << reg);
6676 /* Restored later */
6677 regmask &= ~(1 << ARMREG_PC);
6678 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6679 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6680 for (i = 0; i < 16; i++) {
6681 if (regmask & (1 << i))
6684 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6686 ARM_POP (code, regmask);
6688 for (i = 0; i < 16; i++) {
6689 if (regmask & (1 << i))
6690 mono_emit_unwind_op_same_value (cfg, code, i);
6692 /* Restore saved r7, restore LR to PC */
6693 /* Skip lr from the lmf */
6694 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6695 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6696 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6697 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6700 int i, nused_int_regs = 0;
6702 for (i = 0; i < 16; i++) {
6703 if (cfg->used_int_regs & (1 << i))
6707 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6708 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6710 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6711 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6714 if (cfg->frame_reg != ARMREG_SP) {
6715 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6719 /* Restore saved gregs */
6720 if (cfg->used_int_regs) {
6721 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6722 ARM_POP (code, cfg->used_int_regs);
6723 for (i = 0; i < 16; i++) {
6724 if (cfg->used_int_regs & (1 << i))
6725 mono_emit_unwind_op_same_value (cfg, code, i);
6728 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6729 /* Restore saved r7, restore LR to PC */
6730 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6732 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6733 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6737 /* Restore the unwind state to be the same as before the epilog */
6738 mono_emit_unwind_op_restore_state (cfg, code);
6740 cfg->code_len = code - cfg->native_code;
6742 g_assert (cfg->code_len < cfg->code_size);
6747 mono_arch_emit_exceptions (MonoCompile *cfg)
6749 MonoJumpInfo *patch_info;
6752 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6753 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6754 int max_epilog_size = 50;
6756 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6757 exc_throw_pos [i] = NULL;
6758 exc_throw_found [i] = 0;
6761 /* count the number of exception infos */
6764 * make sure we have enough space for exceptions
6766 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6767 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6768 i = mini_exception_id_by_name (patch_info->data.target);
6769 if (!exc_throw_found [i]) {
6770 max_epilog_size += 32;
6771 exc_throw_found [i] = TRUE;
6776 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6777 cfg->code_size *= 2;
6778 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6779 cfg->stat_code_reallocs++;
6782 code = cfg->native_code + cfg->code_len;
6784 /* add code to raise exceptions */
6785 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6786 switch (patch_info->type) {
6787 case MONO_PATCH_INFO_EXC: {
6788 MonoClass *exc_class;
6789 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6791 i = mini_exception_id_by_name (patch_info->data.target);
6792 if (exc_throw_pos [i]) {
6793 arm_patch (ip, exc_throw_pos [i]);
6794 patch_info->type = MONO_PATCH_INFO_NONE;
6797 exc_throw_pos [i] = code;
6799 arm_patch (ip, code);
6801 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6802 g_assert (exc_class);
6804 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6805 #ifdef USE_JUMP_TABLES
6807 gpointer *jte = mono_jumptable_add_entries (2);
6808 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6809 patch_info->data.name = "mono_arch_throw_corlib_exception";
6810 patch_info->ip.i = code - cfg->native_code;
6811 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6812 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6813 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6814 ARM_BLX_REG (code, ARMREG_IP);
6815 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6818 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6819 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6820 patch_info->data.name = "mono_arch_throw_corlib_exception";
6821 patch_info->ip.i = code - cfg->native_code;
6823 cfg->thunk_area += THUNK_SIZE;
6824 *(guint32*)(gpointer)code = exc_class->type_token;
6835 cfg->code_len = code - cfg->native_code;
6837 g_assert (cfg->code_len < cfg->code_size);
6841 #endif /* #ifndef DISABLE_JIT */
6844 mono_arch_finish_init (void)
6849 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6854 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6861 mono_arch_print_tree (MonoInst *tree, int arity)
6871 mono_arch_get_patch_offset (guint8 *code)
6878 mono_arch_flush_register_windows (void)
6883 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6885 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6889 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6891 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6895 mono_arch_get_cie_program (void)
6899 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6904 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6905 #define BASE_SIZE (6 * 4)
6906 #define BSEARCH_ENTRY_SIZE (4 * 4)
6907 #define CMP_SIZE (3 * 4)
6908 #define BRANCH_SIZE (1 * 4)
6909 #define CALL_SIZE (2 * 4)
6910 #define WMC_SIZE (8 * 4)
6911 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6913 #ifdef USE_JUMP_TABLES
6915 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6917 g_assert (base [index] == NULL);
6918 base [index] = value;
6921 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6923 if (arm_is_imm12 (jti * 4)) {
6924 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6926 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6927 if ((jti * 4) >> 16)
6928 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6929 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6935 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6937 guint32 delta = DISTANCE (target, code);
6939 g_assert (delta >= 0 && delta <= 0xFFF);
6940 *target = *target | delta;
6946 #ifdef ENABLE_WRONG_METHOD_CHECK
6948 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6950 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6956 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6957 gpointer fail_tramp)
6960 arminstr_t *code, *start;
6961 #ifdef USE_JUMP_TABLES
6964 gboolean large_offsets = FALSE;
6965 guint32 **constant_pool_starts;
6966 arminstr_t *vtable_target = NULL;
6967 int extra_space = 0;
6969 #ifdef ENABLE_WRONG_METHOD_CHECK
6975 #ifdef USE_JUMP_TABLES
6976 for (i = 0; i < count; ++i) {
6977 MonoIMTCheckItem *item = imt_entries [i];
6978 item->chunk_size += 4 * 16;
6979 if (!item->is_equals)
6980 imt_entries [item->check_target_idx]->compare_done = TRUE;
6981 size += item->chunk_size;
6984 constant_pool_starts = g_new0 (guint32*, count);
6986 for (i = 0; i < count; ++i) {
6987 MonoIMTCheckItem *item = imt_entries [i];
6988 if (item->is_equals) {
6989 gboolean fail_case = !item->check_target_idx && fail_tramp;
6991 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6992 item->chunk_size += 32;
6993 large_offsets = TRUE;
6996 if (item->check_target_idx || fail_case) {
6997 if (!item->compare_done || fail_case)
6998 item->chunk_size += CMP_SIZE;
6999 item->chunk_size += BRANCH_SIZE;
7001 #ifdef ENABLE_WRONG_METHOD_CHECK
7002 item->chunk_size += WMC_SIZE;
7006 item->chunk_size += 16;
7007 large_offsets = TRUE;
7009 item->chunk_size += CALL_SIZE;
7011 item->chunk_size += BSEARCH_ENTRY_SIZE;
7012 imt_entries [item->check_target_idx]->compare_done = TRUE;
7014 size += item->chunk_size;
7018 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
7022 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7024 code = mono_domain_code_reserve (domain, size);
7027 unwind_ops = mono_arch_get_cie_program ();
7030 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
7031 for (i = 0; i < count; ++i) {
7032 MonoIMTCheckItem *item = imt_entries [i];
7033 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
7037 #ifdef USE_JUMP_TABLES
7038 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7039 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 3 * sizeof (mgreg_t));
7040 #define VTABLE_JTI 0
7041 #define IMT_METHOD_OFFSET 0
7042 #define TARGET_CODE_OFFSET 1
7043 #define JUMP_CODE_OFFSET 2
7044 #define RECORDS_PER_ENTRY 3
7045 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
7046 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
7047 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
7049 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
7050 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
7051 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
7052 set_jumptable_element (jte, VTABLE_JTI, vtable);
7054 if (large_offsets) {
7055 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7056 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
7058 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7059 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7061 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7062 vtable_target = code;
7063 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7065 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7067 for (i = 0; i < count; ++i) {
7068 MonoIMTCheckItem *item = imt_entries [i];
7069 #ifdef USE_JUMP_TABLES
7070 guint32 imt_method_jti = 0, target_code_jti = 0;
7072 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7074 gint32 vtable_offset;
7076 item->code_target = (guint8*)code;
7078 if (item->is_equals) {
7079 gboolean fail_case = !item->check_target_idx && fail_tramp;
7081 if (item->check_target_idx || fail_case) {
7082 if (!item->compare_done || fail_case) {
7083 #ifdef USE_JUMP_TABLES
7084 imt_method_jti = IMT_METHOD_JTI (i);
7085 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7088 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7090 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7092 #ifdef USE_JUMP_TABLES
7093 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7094 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7095 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7097 item->jmp_code = (guint8*)code;
7098 ARM_B_COND (code, ARMCOND_NE, 0);
7101 /*Enable the commented code to assert on wrong method*/
7102 #ifdef ENABLE_WRONG_METHOD_CHECK
7103 #ifdef USE_JUMP_TABLES
7104 imt_method_jti = IMT_METHOD_JTI (i);
7105 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7108 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7110 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7112 ARM_B_COND (code, ARMCOND_EQ, 0);
7114 /* Define this if your system is so bad that gdb is failing. */
7115 #ifdef BROKEN_DEV_ENV
7116 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7118 arm_patch (code - 1, mini_dump_bad_imt);
7122 arm_patch (cond, code);
7126 if (item->has_target_code) {
7127 /* Load target address */
7128 #ifdef USE_JUMP_TABLES
7129 target_code_jti = TARGET_CODE_JTI (i);
7130 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7131 /* Restore registers */
7132 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7133 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7135 ARM_BX (code, ARMREG_R1);
7136 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7138 target_code_ins = code;
7139 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7140 /* Save it to the fourth slot */
7141 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7142 /* Restore registers and branch */
7143 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7145 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7148 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7149 if (!arm_is_imm12 (vtable_offset)) {
7151 * We need to branch to a computed address but we don't have
7152 * a free register to store it, since IP must contain the
7153 * vtable address. So we push the two values to the stack, and
7154 * load them both using LDM.
7156 /* Compute target address */
7157 #ifdef USE_JUMP_TABLES
7158 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7159 if (vtable_offset >> 16)
7160 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7161 /* IP had vtable base. */
7162 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7163 /* Restore registers and branch */
7164 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7165 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7166 ARM_BX (code, ARMREG_IP);
7168 vtable_offset_ins = code;
7169 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7170 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7171 /* Save it to the fourth slot */
7172 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7173 /* Restore registers and branch */
7174 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7176 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7179 #ifdef USE_JUMP_TABLES
7180 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7181 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7182 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7183 ARM_BX (code, ARMREG_IP);
7185 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7186 if (large_offsets) {
7187 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7188 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7190 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7191 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7197 #ifdef USE_JUMP_TABLES
7198 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7199 target_code_jti = TARGET_CODE_JTI (i);
7200 /* Load target address */
7201 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7202 /* Restore registers */
7203 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7204 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7206 ARM_BX (code, ARMREG_R1);
7207 set_jumptable_element (jte, target_code_jti, fail_tramp);
7209 arm_patch (item->jmp_code, (guchar*)code);
7211 target_code_ins = code;
7212 /* Load target address */
7213 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7214 /* Save it to the fourth slot */
7215 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7216 /* Restore registers and branch */
7217 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7219 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7221 item->jmp_code = NULL;
7224 #ifdef USE_JUMP_TABLES
7226 set_jumptable_element (jte, imt_method_jti, item->key);
7229 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7231 /*must emit after unconditional branch*/
7232 if (vtable_target) {
7233 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7234 item->chunk_size += 4;
7235 vtable_target = NULL;
7238 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7239 constant_pool_starts [i] = code;
7241 code += extra_space;
7246 #ifdef USE_JUMP_TABLES
7247 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7248 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7249 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7250 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7251 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7253 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7254 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7256 item->jmp_code = (guint8*)code;
7257 ARM_B_COND (code, ARMCOND_HS, 0);
7263 for (i = 0; i < count; ++i) {
7264 MonoIMTCheckItem *item = imt_entries [i];
7265 if (item->jmp_code) {
7266 if (item->check_target_idx)
7267 #ifdef USE_JUMP_TABLES
7268 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7270 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7273 if (i > 0 && item->is_equals) {
7275 #ifdef USE_JUMP_TABLES
7276 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7277 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7279 arminstr_t *space_start = constant_pool_starts [i];
7280 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7281 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7289 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7290 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7295 #ifndef USE_JUMP_TABLES
7296 g_free (constant_pool_starts);
7299 mono_arch_flush_icache ((guint8*)start, size);
7300 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7301 mono_stats.imt_thunks_size += code - start;
7303 g_assert (DISTANCE (start, code) <= size);
7305 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7311 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7313 return ctx->regs [reg];
7317 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7319 ctx->regs [reg] = val;
7323 * mono_arch_get_trampolines:
7325 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7329 mono_arch_get_trampolines (gboolean aot)
7331 return mono_arm_get_exception_trampolines (aot);
7335 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7342 bp = MONO_CONTEXT_GET_BP (ctx);
7343 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7345 old_value = *lr_loc;
7346 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7349 *lr_loc = new_value;
7354 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7356 * mono_arch_set_breakpoint:
7358 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7359 * The location should contain code emitted by OP_SEQ_POINT.
7362 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7365 guint32 native_offset = ip - (guint8*)ji->code_start;
7366 MonoDebugOptions *opt = mini_get_debug_options ();
7368 if (opt->soft_breakpoints) {
7369 g_assert (!ji->from_aot);
7371 ARM_BLX_REG (code, ARMREG_LR);
7372 mono_arch_flush_icache (code - 4, 4);
7373 } else if (ji->from_aot) {
7374 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7376 g_assert (native_offset % 4 == 0);
7377 g_assert (info->bp_addrs [native_offset / 4] == 0);
7378 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7380 int dreg = ARMREG_LR;
7382 /* Read from another trigger page */
7383 #ifdef USE_JUMP_TABLES
7384 gpointer *jte = mono_jumptable_add_entry ();
7385 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7386 jte [0] = bp_trigger_page;
7388 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7390 *(int*)code = (int)bp_trigger_page;
7393 ARM_LDR_IMM (code, dreg, dreg, 0);
7395 mono_arch_flush_icache (code - 16, 16);
7398 /* This is currently implemented by emitting an SWI instruction, which
7399 * qemu/linux seems to convert to a SIGILL.
7401 *(int*)code = (0xef << 24) | 8;
7403 mono_arch_flush_icache (code - 4, 4);
7409 * mono_arch_clear_breakpoint:
7411 * Clear the breakpoint at IP.
7414 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7416 MonoDebugOptions *opt = mini_get_debug_options ();
7420 if (opt->soft_breakpoints) {
7421 g_assert (!ji->from_aot);
7424 mono_arch_flush_icache (code - 4, 4);
7425 } else if (ji->from_aot) {
7426 guint32 native_offset = ip - (guint8*)ji->code_start;
7427 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7429 g_assert (native_offset % 4 == 0);
7430 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7431 info->bp_addrs [native_offset / 4] = 0;
7433 for (i = 0; i < 4; ++i)
7436 mono_arch_flush_icache (ip, code - ip);
7441 * mono_arch_start_single_stepping:
7443 * Start single stepping.
7446 mono_arch_start_single_stepping (void)
7448 if (ss_trigger_page)
7449 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7451 single_step_tramp = mini_get_single_step_trampoline ();
7455 * mono_arch_stop_single_stepping:
7457 * Stop single stepping.
7460 mono_arch_stop_single_stepping (void)
7462 if (ss_trigger_page)
7463 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7465 single_step_tramp = NULL;
7469 #define DBG_SIGNAL SIGBUS
7471 #define DBG_SIGNAL SIGSEGV
7475 * mono_arch_is_single_step_event:
7477 * Return whenever the machine state in SIGCTX corresponds to a single
7481 mono_arch_is_single_step_event (void *info, void *sigctx)
7483 siginfo_t *sinfo = info;
7485 if (!ss_trigger_page)
7488 /* Sometimes the address is off by 4 */
7489 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7496 * mono_arch_is_breakpoint_event:
7498 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7501 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7503 siginfo_t *sinfo = info;
7505 if (!ss_trigger_page)
7508 if (sinfo->si_signo == DBG_SIGNAL) {
7509 /* Sometimes the address is off by 4 */
7510 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7520 * mono_arch_skip_breakpoint:
7522 * See mini-amd64.c for docs.
7525 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7527 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7531 * mono_arch_skip_single_step:
7533 * See mini-amd64.c for docs.
7536 mono_arch_skip_single_step (MonoContext *ctx)
7538 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7541 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7544 * mono_arch_get_seq_point_info:
7546 * See mini-amd64.c for docs.
7549 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7554 // FIXME: Add a free function
7556 mono_domain_lock (domain);
7557 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7559 mono_domain_unlock (domain);
7562 ji = mono_jit_info_table_find (domain, (char*)code);
7565 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7567 info->ss_trigger_page = ss_trigger_page;
7568 info->bp_trigger_page = bp_trigger_page;
7570 mono_domain_lock (domain);
7571 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7573 mono_domain_unlock (domain);
7580 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7582 ext->lmf.previous_lmf = prev_lmf;
7583 /* Mark that this is a MonoLMFExt */
7584 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7585 ext->lmf.sp = (gssize)ext;
7589 * mono_arch_set_target:
7591 * Set the target architecture the JIT backend should generate code for, in the form
7592 * of a GNU target triplet. Only used in AOT mode.
7595 mono_arch_set_target (char *mtriple)
7597 /* The GNU target triple format is not very well documented */
7598 if (strstr (mtriple, "armv7")) {
7599 v5_supported = TRUE;
7600 v6_supported = TRUE;
7601 v7_supported = TRUE;
7603 if (strstr (mtriple, "armv6")) {
7604 v5_supported = TRUE;
7605 v6_supported = TRUE;
7607 if (strstr (mtriple, "armv7s")) {
7608 v7s_supported = TRUE;
7610 if (strstr (mtriple, "armv7k")) {
7611 v7k_supported = TRUE;
7613 if (strstr (mtriple, "thumbv7s")) {
7614 v5_supported = TRUE;
7615 v6_supported = TRUE;
7616 v7_supported = TRUE;
7617 v7s_supported = TRUE;
7618 thumb_supported = TRUE;
7619 thumb2_supported = TRUE;
7621 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7622 v5_supported = TRUE;
7623 v6_supported = TRUE;
7624 thumb_supported = TRUE;
7627 if (strstr (mtriple, "gnueabi"))
7628 eabi_supported = TRUE;
7632 mono_arch_opcode_supported (int opcode)
7635 case OP_ATOMIC_ADD_I4:
7636 case OP_ATOMIC_EXCHANGE_I4:
7637 case OP_ATOMIC_CAS_I4:
7638 case OP_ATOMIC_LOAD_I1:
7639 case OP_ATOMIC_LOAD_I2:
7640 case OP_ATOMIC_LOAD_I4:
7641 case OP_ATOMIC_LOAD_U1:
7642 case OP_ATOMIC_LOAD_U2:
7643 case OP_ATOMIC_LOAD_U4:
7644 case OP_ATOMIC_STORE_I1:
7645 case OP_ATOMIC_STORE_I2:
7646 case OP_ATOMIC_STORE_I4:
7647 case OP_ATOMIC_STORE_U1:
7648 case OP_ATOMIC_STORE_U2:
7649 case OP_ATOMIC_STORE_U4:
7650 return v7_supported;
7651 case OP_ATOMIC_LOAD_R4:
7652 case OP_ATOMIC_LOAD_R8:
7653 case OP_ATOMIC_STORE_R4:
7654 case OP_ATOMIC_STORE_R8:
7655 return v7_supported && IS_VFP;
7661 #if defined(ENABLE_GSHAREDVT)
7663 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7665 #endif /* !MONOTOUCH */