2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
24 #include "mini-arm-tls.h"
28 #include "debugger-agent.h"
30 #include "mono/arch/arm/arm-vfp-codegen.h"
32 #if (defined(HAVE_KW_THREAD) && defined(__linux__) && defined(__ARM_EABI__)) \
33 || defined(TARGET_ANDROID) \
34 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
38 /* Sanity check: This makes no sense */
39 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
40 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
44 * IS_SOFT_FLOAT: Is full software floating point used?
45 * IS_HARD_FLOAT: Is full hardware floating point used?
46 * IS_VFP: Is hardware floating point with software ABI used?
48 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
49 * IS_VFP may delegate to mono_arch_is_soft_float ().
52 #if defined(ARM_FPU_VFP_HARD)
53 #define IS_SOFT_FLOAT (FALSE)
54 #define IS_HARD_FLOAT (TRUE)
56 #elif defined(ARM_FPU_NONE)
57 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
58 #define IS_HARD_FLOAT (FALSE)
59 #define IS_VFP (!mono_arch_is_soft_float ())
61 #define IS_SOFT_FLOAT (FALSE)
62 #define IS_HARD_FLOAT (FALSE)
66 #define THUNK_SIZE (3 * 4)
68 #ifdef __native_client_codegen__
69 const guint kNaClAlignment = kNaClAlignmentARM;
70 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
71 gint8 nacl_align_byte = -1; /* 0xff */
74 mono_arch_nacl_pad (guint8 *code, int pad)
76 /* Not yet properly implemented. */
77 g_assert_not_reached ();
82 mono_arch_nacl_skip_nops (guint8 *code)
84 /* Not yet properly implemented. */
85 g_assert_not_reached ();
89 #endif /* __native_client_codegen__ */
91 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
94 void sys_icache_invalidate (void *start, size_t len);
97 /* This mutex protects architecture specific caches */
98 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
99 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
100 static mono_mutex_t mini_arch_mutex;
102 static gboolean v5_supported = FALSE;
103 static gboolean v6_supported = FALSE;
104 static gboolean v7_supported = FALSE;
105 static gboolean v7s_supported = FALSE;
106 static gboolean v7k_supported = FALSE;
107 static gboolean thumb_supported = FALSE;
108 static gboolean thumb2_supported = FALSE;
110 * Whenever to use the ARM EABI
112 static gboolean eabi_supported = FALSE;
115 * Whenever to use the iphone ABI extensions:
116 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
117 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
118 * This is required for debugging/profiling tools to work, but it has some overhead so it should
119 * only be turned on in debug builds.
121 static gboolean iphone_abi = FALSE;
124 * The FPU we are generating code for. This is NOT runtime configurable right now,
125 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
127 static MonoArmFPU arm_fpu;
129 #if defined(ARM_FPU_VFP_HARD)
131 * On armhf, d0-d7 are used for argument passing and d8-d15
132 * must be preserved across calls, which leaves us no room
133 * for scratch registers. So we use d14-d15 but back up their
134 * previous contents to a stack slot before using them - see
135 * mono_arm_emit_vfp_scratch_save/_restore ().
137 static int vfp_scratch1 = ARM_VFP_D14;
138 static int vfp_scratch2 = ARM_VFP_D15;
141 * On armel, d0-d7 do not need to be preserved, so we can
142 * freely make use of them as scratch registers.
144 static int vfp_scratch1 = ARM_VFP_D0;
145 static int vfp_scratch2 = ARM_VFP_D1;
150 static gpointer single_step_tramp, breakpoint_tramp;
153 * The code generated for sequence points reads from this location, which is
154 * made read-only when single stepping is enabled.
156 static gpointer ss_trigger_page;
158 /* Enabled breakpoints read from this trigger page */
159 static gpointer bp_trigger_page;
163 * floating point support: on ARM it is a mess, there are at least 3
164 * different setups, each of which binary incompat with the other.
165 * 1) FPA: old and ugly, but unfortunately what current distros use
166 * the double binary format has the two words swapped. 8 double registers.
167 * Implemented usually by kernel emulation.
168 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
169 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
170 * 3) VFP: the new and actually sensible and useful FP support. Implemented
171 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
173 * We do not care about FPA. We will support soft float and VFP.
175 int mono_exc_esp_offset = 0;
177 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
178 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
179 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
181 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
182 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
183 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
185 //#define DEBUG_IMT 0
188 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
192 mono_arch_regname (int reg)
194 static const char * rnames[] = {
195 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
196 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
197 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
200 if (reg >= 0 && reg < 16)
206 mono_arch_fregname (int reg)
208 static const char * rnames[] = {
209 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
210 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
211 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
212 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
213 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
214 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
217 if (reg >= 0 && reg < 32)
225 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
227 int imm8, rot_amount;
228 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
229 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
233 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
234 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
236 code = mono_arm_emit_load_imm (code, dreg, imm);
237 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
242 /* If dreg == sreg, this clobbers IP */
244 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
246 int imm8, rot_amount;
247 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
248 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
252 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
253 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
255 code = mono_arm_emit_load_imm (code, dreg, imm);
256 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
262 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
264 /* we can use r0-r3, since this is called only for incoming args on the stack */
265 if (size > sizeof (gpointer) * 4) {
267 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
268 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
269 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
270 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
271 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
272 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
273 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
274 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
275 ARM_B_COND (code, ARMCOND_NE, 0);
276 arm_patch (code - 4, start_loop);
279 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
280 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
282 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
283 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
289 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
290 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
291 doffset = soffset = 0;
293 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
294 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
300 g_assert (size == 0);
305 emit_call_reg (guint8 *code, int reg)
308 ARM_BLX_REG (code, reg);
310 #ifdef USE_JUMP_TABLES
311 g_assert_not_reached ();
313 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
317 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
323 emit_call_seq (MonoCompile *cfg, guint8 *code)
325 #ifdef USE_JUMP_TABLES
326 code = mono_arm_patchable_bl (code, ARMCOND_AL);
328 if (cfg->method->dynamic) {
329 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
331 *(gpointer*)code = NULL;
333 code = emit_call_reg (code, ARMREG_IP);
337 cfg->thunk_area += THUNK_SIZE;
343 mono_arm_patchable_b (guint8 *code, int cond)
345 #ifdef USE_JUMP_TABLES
348 jte = mono_jumptable_add_entry ();
349 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
350 ARM_BX_COND (code, cond, ARMREG_IP);
352 ARM_B_COND (code, cond, 0);
358 mono_arm_patchable_bl (guint8 *code, int cond)
360 #ifdef USE_JUMP_TABLES
363 jte = mono_jumptable_add_entry ();
364 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
365 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
367 ARM_BL_COND (code, cond, 0);
372 #ifdef USE_JUMP_TABLES
374 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
376 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
377 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
382 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
384 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
385 ARM_LDR_IMM (code, reg, reg, 0);
391 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
394 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
395 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
397 code = emit_call_seq (cfg, code);
398 if (dreg != ARMREG_R0)
399 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
401 g_assert_not_reached ();
407 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
410 if (tls_offset_reg != ARMREG_R0)
411 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
412 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
414 code = emit_call_seq (cfg, code);
415 if (dreg != ARMREG_R0)
416 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
418 g_assert_not_reached ();
424 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
427 if (sreg != ARMREG_R1)
428 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
429 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
430 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
432 code = emit_call_seq (cfg, code);
434 g_assert_not_reached ();
440 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
443 /* Get sreg in R1 and tls_offset_reg in R0 */
444 if (tls_offset_reg == ARMREG_R1) {
445 if (sreg == ARMREG_R0) {
446 /* swap sreg and tls_offset_reg */
447 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
448 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
449 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
451 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
452 if (sreg != ARMREG_R1)
453 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
456 if (sreg != ARMREG_R1)
457 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
458 if (tls_offset_reg != ARMREG_R0)
459 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
461 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
463 code = emit_call_seq (cfg, code);
465 g_assert_not_reached ();
473 * Emit code to push an LMF structure on the LMF stack.
474 * On arm, this is intermixed with the initialization of other fields of the structure.
477 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
479 gboolean get_lmf_fast = FALSE;
482 if (mono_arm_have_tls_get ()) {
484 if (cfg->compile_aot) {
486 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
487 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
489 *(gpointer*)code = NULL;
491 /* Load the value from the GOT */
492 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
493 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
495 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
496 g_assert (lmf_addr_tls_offset != -1);
497 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
502 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
503 (gpointer)"mono_get_lmf_addr");
504 code = emit_call_seq (cfg, code);
506 /* we build the MonoLMF structure on the stack - see mini-arm.h */
507 /* lmf_offset is the offset from the previous stack pointer,
508 * alloc_size is the total stack space allocated, so the offset
509 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
510 * The pointer to the struct is put in r1 (new_lmf).
511 * ip is used as scratch
512 * The callee-saved registers are already in the MonoLMF structure
514 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
515 /* r0 is the result from mono_get_lmf_addr () */
516 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
517 /* new_lmf->previous_lmf = *lmf_addr */
518 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
519 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
520 /* *(lmf_addr) = r1 */
521 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
522 /* Skip method (only needed for trampoline LMF frames) */
523 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
524 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
525 /* save the current IP */
526 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
527 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
529 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
530 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
541 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
545 g_assert (!cfg->r4fp);
547 for (list = inst->float_args; list; list = list->next) {
548 FloatArgData *fad = list->data;
549 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
550 gboolean imm = arm_is_fpimm8 (var->inst_offset);
552 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
558 if (*offset + *max_len > cfg->code_size) {
559 cfg->code_size += *max_len;
560 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
562 code = cfg->native_code + *offset;
566 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
567 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
569 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
571 *offset = code - cfg->native_code;
578 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
582 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
584 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
587 if (!arm_is_fpimm8 (inst->inst_offset)) {
588 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
589 ARM_FSTD (code, reg, ARMREG_LR, 0);
591 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
598 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
602 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
604 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
607 if (!arm_is_fpimm8 (inst->inst_offset)) {
608 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
609 ARM_FLDD (code, reg, ARMREG_LR, 0);
611 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
620 * Emit code to pop an LMF structure from the LMF stack.
623 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
627 if (lmf_offset < 32) {
628 basereg = cfg->frame_reg;
633 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
636 /* ip = previous_lmf */
637 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
639 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
640 /* *(lmf_addr) = previous_lmf */
641 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
646 #endif /* #ifndef DISABLE_JIT */
649 * mono_arm_have_tls_get:
651 * Returns whether we have tls access implemented on the current
655 mono_arm_have_tls_get (void)
665 * mono_arch_get_argument_info:
666 * @csig: a method signature
667 * @param_count: the number of parameters to consider
668 * @arg_info: an array to store the result infos
670 * Gathers information on parameters such as size, alignment and
671 * padding. arg_info should be large enought to hold param_count + 1 entries.
673 * Returns the size of the activation frame.
676 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
678 int k, frame_size = 0;
679 guint32 size, align, pad;
683 t = mini_get_underlying_type (csig->ret);
684 if (MONO_TYPE_ISSTRUCT (t)) {
685 frame_size += sizeof (gpointer);
689 arg_info [0].offset = offset;
692 frame_size += sizeof (gpointer);
696 arg_info [0].size = frame_size;
698 for (k = 0; k < param_count; k++) {
699 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
701 /* ignore alignment for now */
704 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
705 arg_info [k].pad = pad;
707 arg_info [k + 1].pad = 0;
708 arg_info [k + 1].size = size;
710 arg_info [k + 1].offset = offset;
714 align = MONO_ARCH_FRAME_ALIGNMENT;
715 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
716 arg_info [k].pad = pad;
721 #define MAX_ARCH_DELEGATE_PARAMS 3
724 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
726 guint8 *code, *start;
727 GSList *unwind_ops = mono_arch_get_cie_program ();
730 start = code = mono_global_codeman_reserve (12);
732 /* Replace the this argument with the target */
733 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
734 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
735 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
737 g_assert ((code - start) <= 12);
739 mono_arch_flush_icache (start, 12);
743 size = 8 + param_count * 4;
744 start = code = mono_global_codeman_reserve (size);
746 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
747 /* slide down the arguments */
748 for (i = 0; i < param_count; ++i) {
749 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
751 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
753 g_assert ((code - start) <= size);
755 mono_arch_flush_icache (start, size);
759 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
761 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
762 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
766 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
772 * mono_arch_get_delegate_invoke_impls:
774 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
778 mono_arch_get_delegate_invoke_impls (void)
784 get_delegate_invoke_impl (&info, TRUE, 0);
785 res = g_slist_prepend (res, info);
787 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
788 get_delegate_invoke_impl (&info, FALSE, i);
789 res = g_slist_prepend (res, info);
796 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
798 guint8 *code, *start;
801 /* FIXME: Support more cases */
802 sig_ret = mini_get_underlying_type (sig->ret);
803 if (MONO_TYPE_ISSTRUCT (sig_ret))
807 static guint8* cached = NULL;
808 mono_mini_arch_lock ();
810 mono_mini_arch_unlock ();
815 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
818 start = get_delegate_invoke_impl (&info, TRUE, 0);
819 mono_tramp_info_register (info, NULL);
822 mono_mini_arch_unlock ();
825 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
828 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
830 for (i = 0; i < sig->param_count; ++i)
831 if (!mono_is_regsize_var (sig->params [i]))
834 mono_mini_arch_lock ();
835 code = cache [sig->param_count];
837 mono_mini_arch_unlock ();
842 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
843 start = mono_aot_get_trampoline (name);
847 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
848 mono_tramp_info_register (info, NULL);
850 cache [sig->param_count] = start;
851 mono_mini_arch_unlock ();
859 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
865 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
867 return (gpointer)regs [ARMREG_R0];
871 * Initialize the cpu to execute managed code.
874 mono_arch_cpu_init (void)
876 i8_align = MONO_ABI_ALIGNOF (gint64);
877 #ifdef MONO_CROSS_COMPILE
878 /* Need to set the alignment of i8 since it can different on the target */
879 #ifdef TARGET_ANDROID
881 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
887 * Initialize architecture specific code.
890 mono_arch_init (void)
892 const char *cpu_arch;
894 mono_mutex_init_recursive (&mini_arch_mutex);
895 if (mini_get_debug_options ()->soft_breakpoints) {
896 breakpoint_tramp = mini_get_breakpoint_trampoline ();
898 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
899 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
900 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
903 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
904 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
905 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
906 #if defined(ENABLE_GSHAREDVT)
907 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
909 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
911 #if defined(__ARM_EABI__)
912 eabi_supported = TRUE;
915 #if defined(ARM_FPU_VFP_HARD)
916 arm_fpu = MONO_ARM_FPU_VFP_HARD;
918 arm_fpu = MONO_ARM_FPU_VFP;
920 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
922 * If we're compiling with a soft float fallback and it
923 * turns out that no VFP unit is available, we need to
924 * switch to soft float. We don't do this for iOS, since
925 * iOS devices always have a VFP unit.
927 if (!mono_hwcap_arm_has_vfp)
928 arm_fpu = MONO_ARM_FPU_NONE;
931 * This environment variable can be useful in testing
932 * environments to make sure the soft float fallback
933 * works. Most ARM devices have VFP units these days, so
934 * normally soft float code would not be exercised much.
936 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
938 if (soft && !strncmp (soft, "1", 1))
939 arm_fpu = MONO_ARM_FPU_NONE;
943 v5_supported = mono_hwcap_arm_is_v5;
944 v6_supported = mono_hwcap_arm_is_v6;
945 v7_supported = mono_hwcap_arm_is_v7;
947 #if defined(__APPLE__)
948 /* iOS is special-cased here because we don't yet
949 have a way to properly detect CPU features on it. */
950 thumb_supported = TRUE;
953 thumb_supported = mono_hwcap_arm_has_thumb;
954 thumb2_supported = mono_hwcap_arm_has_thumb2;
957 /* Format: armv(5|6|7[s])[-thumb[2]] */
958 cpu_arch = g_getenv ("MONO_CPU_ARCH");
960 /* Do this here so it overrides any detection. */
962 if (strncmp (cpu_arch, "armv", 4) == 0) {
963 v5_supported = cpu_arch [4] >= '5';
964 v6_supported = cpu_arch [4] >= '6';
965 v7_supported = cpu_arch [4] >= '7';
966 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
967 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
970 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
971 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
976 * Cleanup architecture specific code.
979 mono_arch_cleanup (void)
984 * This function returns the optimizations supported on this cpu.
987 mono_arch_cpu_optimizations (guint32 *exclude_mask)
989 /* no arm-specific optimizations yet */
995 * This function test for all SIMD functions supported.
997 * Returns a bitmask corresponding to all supported versions.
1001 mono_arch_cpu_enumerate_simd_versions (void)
1003 /* SIMD is currently unimplemented */
1011 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1013 if (v7s_supported || v7k_supported) {
1027 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1029 mono_arch_is_soft_float (void)
1031 return arm_fpu == MONO_ARM_FPU_NONE;
1036 mono_arm_is_hard_float (void)
1038 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1042 is_regsize_var (MonoType *t)
1046 t = mini_get_underlying_type (t);
1053 case MONO_TYPE_FNPTR:
1055 case MONO_TYPE_OBJECT:
1056 case MONO_TYPE_STRING:
1057 case MONO_TYPE_CLASS:
1058 case MONO_TYPE_SZARRAY:
1059 case MONO_TYPE_ARRAY:
1061 case MONO_TYPE_GENERICINST:
1062 if (!mono_type_generic_inst_is_valuetype (t))
1065 case MONO_TYPE_VALUETYPE:
1072 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1077 for (i = 0; i < cfg->num_varinfo; i++) {
1078 MonoInst *ins = cfg->varinfo [i];
1079 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1082 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1085 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1088 /* we can only allocate 32 bit values */
1089 if (is_regsize_var (ins->inst_vtype)) {
1090 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1091 g_assert (i == vmv->idx);
1092 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1100 mono_arch_get_global_int_regs (MonoCompile *cfg)
1104 mono_arch_compute_omit_fp (cfg);
1107 * FIXME: Interface calls might go through a static rgctx trampoline which
1108 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1111 if (cfg->flags & MONO_CFG_HAS_CALLS)
1112 cfg->uses_rgctx_reg = TRUE;
1114 if (cfg->arch.omit_fp)
1115 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1116 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1117 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1118 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1120 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1121 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1123 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1124 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1125 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1126 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1127 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1128 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1134 * mono_arch_regalloc_cost:
1136 * Return the cost, in number of memory references, of the action of
1137 * allocating the variable VMV into a register during global register
1141 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1147 #endif /* #ifndef DISABLE_JIT */
1150 mono_arch_flush_icache (guint8 *code, gint size)
1152 #if defined(MONO_CROSS_COMPILE) || defined(__native_client__)
1153 // For Native Client we don't have to flush i-cache here,
1154 // as it's being done by dyncode interface.
1156 sys_icache_invalidate (code, size);
1158 __builtin___clear_cache (code, code + size);
1164 /* Passed/returned in an ireg */
1166 /* Passed/returned in a pair of iregs */
1168 /* Passed on the stack */
1170 /* First word in r3, second word on the stack */
1172 /* FP value passed in either an ireg or a vfp reg */
1175 RegTypeStructByAddr,
1176 /* gsharedvt argument passed by addr in greg */
1177 RegTypeGSharedVtInReg,
1178 /* gsharedvt argument passed by addr on stack */
1179 RegTypeGSharedVtOnStack,
1185 guint16 vtsize; /* in param area */
1193 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1198 guint32 stack_usage;
1199 /* The index of the vret arg in the argument list for RegTypeStructByAddr */
1209 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1212 if (*gr > ARMREG_R3) {
1214 ainfo->offset = *stack_size;
1215 ainfo->reg = ARMREG_SP; /* in the caller */
1216 ainfo->storage = RegTypeBase;
1219 ainfo->storage = RegTypeGeneral;
1226 split = i8_align == 4;
1231 if (*gr == ARMREG_R3 && split) {
1232 /* first word in r3 and the second on the stack */
1233 ainfo->offset = *stack_size;
1234 ainfo->reg = ARMREG_SP; /* in the caller */
1235 ainfo->storage = RegTypeBaseGen;
1237 } else if (*gr >= ARMREG_R3) {
1238 if (eabi_supported) {
1239 /* darwin aligns longs to 4 byte only */
1240 if (i8_align == 8) {
1245 ainfo->offset = *stack_size;
1246 ainfo->reg = ARMREG_SP; /* in the caller */
1247 ainfo->storage = RegTypeBase;
1250 if (eabi_supported) {
1251 if (i8_align == 8 && ((*gr) & 1))
1254 ainfo->storage = RegTypeIRegPair;
1263 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1266 * If we're calling a function like this:
1268 * void foo(float a, double b, float c)
1270 * We pass a in s0 and b in d1. That leaves us
1271 * with s1 being unused. The armhf ABI recognizes
1272 * this and requires register assignment to then
1273 * use that for the next single-precision arg,
1274 * i.e. c in this example. So float_spare either
1275 * tells us which reg to use for the next single-
1276 * precision arg, or it's -1, meaning use *fpr.
1278 * Note that even though most of the JIT speaks
1279 * double-precision, fpr represents single-
1280 * precision registers.
1282 * See parts 5.5 and 6.1.2 of the AAPCS for how
1286 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1287 ainfo->storage = RegTypeFP;
1291 * If we're passing a double-precision value
1292 * and *fpr is odd (e.g. it's s1, s3, ...)
1293 * we need to use the next even register. So
1294 * we mark the current *fpr as a spare that
1295 * can be used for the next single-precision
1299 *float_spare = *fpr;
1304 * At this point, we have an even register
1305 * so we assign that and move along.
1309 } else if (*float_spare >= 0) {
1311 * We're passing a single-precision value
1312 * and it looks like a spare single-
1313 * precision register is available. Let's
1317 ainfo->reg = *float_spare;
1321 * If we hit this branch, we're passing a
1322 * single-precision value and we can simply
1323 * use the next available register.
1331 * We've exhausted available floating point
1332 * regs, so pass the rest on the stack.
1340 ainfo->offset = *stack_size;
1341 ainfo->reg = ARMREG_SP;
1342 ainfo->storage = RegTypeBase;
1349 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1353 MonoClassField *field;
1354 MonoType *ftype, *prev_ftype = NULL;
1357 klass = mono_class_from_mono_type (t);
1359 while ((field = mono_class_get_fields (klass, &iter))) {
1360 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1362 ftype = mono_field_get_type (field);
1363 ftype = mini_get_underlying_type (ftype);
1365 if (MONO_TYPE_ISSTRUCT (ftype)) {
1366 int nested_nfields, nested_esize;
1368 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1370 if (nested_esize == 4)
1371 ftype = &mono_defaults.single_class->byval_arg;
1373 ftype = &mono_defaults.double_class->byval_arg;
1374 if (prev_ftype && prev_ftype->type != ftype->type)
1377 nfields += nested_nfields;
1379 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1381 if (prev_ftype && prev_ftype->type != ftype->type)
1387 if (nfields == 0 || nfields > 4)
1389 *out_nfields = nfields;
1390 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1395 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1397 guint i, gr, fpr, pstart;
1399 int n = sig->hasthis + sig->param_count;
1403 guint32 stack_size = 0;
1405 gboolean is_pinvoke = sig->pinvoke;
1406 gboolean vtype_retaddr = FALSE;
1409 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1411 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1418 t = mini_get_underlying_type (sig->ret);
1429 case MONO_TYPE_FNPTR:
1430 case MONO_TYPE_CLASS:
1431 case MONO_TYPE_OBJECT:
1432 case MONO_TYPE_SZARRAY:
1433 case MONO_TYPE_ARRAY:
1434 case MONO_TYPE_STRING:
1435 cinfo->ret.storage = RegTypeGeneral;
1436 cinfo->ret.reg = ARMREG_R0;
1440 cinfo->ret.storage = RegTypeIRegPair;
1441 cinfo->ret.reg = ARMREG_R0;
1445 cinfo->ret.storage = RegTypeFP;
1447 if (t->type == MONO_TYPE_R4)
1448 cinfo->ret.size = 4;
1450 cinfo->ret.size = 8;
1452 if (IS_HARD_FLOAT) {
1453 cinfo->ret.reg = ARM_VFP_F0;
1455 cinfo->ret.reg = ARMREG_R0;
1458 case MONO_TYPE_GENERICINST:
1459 if (!mono_type_generic_inst_is_valuetype (t)) {
1460 cinfo->ret.storage = RegTypeGeneral;
1461 cinfo->ret.reg = ARMREG_R0;
1464 if (mini_is_gsharedvt_variable_type (t)) {
1465 cinfo->ret.storage = RegTypeStructByAddr;
1469 case MONO_TYPE_VALUETYPE:
1470 case MONO_TYPE_TYPEDBYREF:
1471 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1472 cinfo->ret.storage = RegTypeHFA;
1474 cinfo->ret.nregs = nfields;
1475 cinfo->ret.esize = esize;
1477 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1478 cinfo->ret.storage = RegTypeStructByVal;
1480 cinfo->ret.storage = RegTypeStructByAddr;
1484 case MONO_TYPE_MVAR:
1485 g_assert (mini_is_gsharedvt_type (t));
1486 cinfo->ret.storage = RegTypeStructByAddr;
1488 case MONO_TYPE_VOID:
1491 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1494 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1499 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1500 * the first argument, allowing 'this' to be always passed in the first arg reg.
1501 * Also do this if the first argument is a reference type, since virtual calls
1502 * are sometimes made using calli without sig->hasthis set, like in the delegate
1505 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1507 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1509 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1513 cinfo->ret.reg = gr;
1515 cinfo->vret_arg_index = 1;
1519 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1522 if (vtype_retaddr) {
1523 cinfo->ret.reg = gr;
1528 DEBUG(g_print("params: %d\n", sig->param_count));
1529 for (i = pstart; i < sig->param_count; ++i) {
1530 ArgInfo *ainfo = &cinfo->args [n];
1532 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1533 /* Prevent implicit arguments and sig_cookie from
1534 being passed in registers */
1537 /* Emit the signature cookie just before the implicit arguments */
1538 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1540 DEBUG(g_print("param %d: ", i));
1541 if (sig->params [i]->byref) {
1542 DEBUG(g_print("byref\n"));
1543 add_general (&gr, &stack_size, ainfo, TRUE);
1547 t = mini_get_underlying_type (sig->params [i]);
1551 cinfo->args [n].size = 1;
1552 add_general (&gr, &stack_size, ainfo, TRUE);
1556 cinfo->args [n].size = 2;
1557 add_general (&gr, &stack_size, ainfo, TRUE);
1561 cinfo->args [n].size = 4;
1562 add_general (&gr, &stack_size, ainfo, TRUE);
1567 case MONO_TYPE_FNPTR:
1568 case MONO_TYPE_CLASS:
1569 case MONO_TYPE_OBJECT:
1570 case MONO_TYPE_STRING:
1571 case MONO_TYPE_SZARRAY:
1572 case MONO_TYPE_ARRAY:
1573 cinfo->args [n].size = sizeof (gpointer);
1574 add_general (&gr, &stack_size, ainfo, TRUE);
1576 case MONO_TYPE_GENERICINST:
1577 if (!mono_type_generic_inst_is_valuetype (t)) {
1578 cinfo->args [n].size = sizeof (gpointer);
1579 add_general (&gr, &stack_size, ainfo, TRUE);
1582 if (mini_is_gsharedvt_variable_type (t)) {
1583 /* gsharedvt arguments are passed by ref */
1584 g_assert (mini_is_gsharedvt_type (t));
1585 add_general (&gr, &stack_size, ainfo, TRUE);
1586 switch (ainfo->storage) {
1587 case RegTypeGeneral:
1588 ainfo->storage = RegTypeGSharedVtInReg;
1591 ainfo->storage = RegTypeGSharedVtOnStack;
1594 g_assert_not_reached ();
1599 case MONO_TYPE_TYPEDBYREF:
1600 case MONO_TYPE_VALUETYPE: {
1603 int nwords, nfields, esize;
1606 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1607 if (fpr + nfields < ARM_VFP_F16) {
1608 ainfo->storage = RegTypeHFA;
1610 ainfo->nregs = nfields;
1611 ainfo->esize = esize;
1622 if (t->type == MONO_TYPE_TYPEDBYREF) {
1623 size = sizeof (MonoTypedRef);
1624 align = sizeof (gpointer);
1626 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1628 size = mono_class_native_size (klass, &align);
1630 size = mini_type_stack_size_full (t, &align, FALSE);
1632 DEBUG(g_print ("load %d bytes struct\n", size));
1635 align_size += (sizeof (gpointer) - 1);
1636 align_size &= ~(sizeof (gpointer) - 1);
1637 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1638 ainfo->storage = RegTypeStructByVal;
1639 ainfo->struct_size = size;
1640 /* FIXME: align stack_size if needed */
1641 if (eabi_supported) {
1642 if (align >= 8 && (gr & 1))
1645 if (gr > ARMREG_R3) {
1647 ainfo->vtsize = nwords;
1649 int rest = ARMREG_R3 - gr + 1;
1650 int n_in_regs = rest >= nwords? nwords: rest;
1652 ainfo->size = n_in_regs;
1653 ainfo->vtsize = nwords - n_in_regs;
1656 nwords -= n_in_regs;
1658 if (sig->call_convention == MONO_CALL_VARARG)
1659 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1660 stack_size = ALIGN_TO (stack_size, align);
1661 ainfo->offset = stack_size;
1662 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1663 stack_size += nwords * sizeof (gpointer);
1669 add_general (&gr, &stack_size, ainfo, FALSE);
1675 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1677 add_general (&gr, &stack_size, ainfo, TRUE);
1683 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1685 add_general (&gr, &stack_size, ainfo, FALSE);
1688 case MONO_TYPE_MVAR:
1689 /* gsharedvt arguments are passed by ref */
1690 g_assert (mini_is_gsharedvt_type (t));
1691 add_general (&gr, &stack_size, ainfo, TRUE);
1692 switch (ainfo->storage) {
1693 case RegTypeGeneral:
1694 ainfo->storage = RegTypeGSharedVtInReg;
1697 ainfo->storage = RegTypeGSharedVtOnStack;
1700 g_assert_not_reached ();
1704 g_error ("Can't handle 0x%x", sig->params [i]->type);
1709 /* Handle the case where there are no implicit arguments */
1710 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1711 /* Prevent implicit arguments and sig_cookie from
1712 being passed in registers */
1715 /* Emit the signature cookie just before the implicit arguments */
1716 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1719 /* align stack size to 8 */
1720 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1721 stack_size = (stack_size + 7) & ~7;
1723 cinfo->stack_usage = stack_size;
1729 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1731 MonoType *callee_ret;
1735 c1 = get_call_info (NULL, caller_sig);
1736 c2 = get_call_info (NULL, callee_sig);
1739 * Tail calls with more callee stack usage than the caller cannot be supported, since
1740 * the extra stack space would be left on the stack after the tail call.
1742 res = c1->stack_usage >= c2->stack_usage;
1743 callee_ret = mini_get_underlying_type (callee_sig->ret);
1744 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1745 /* An address on the callee's stack is passed as the first argument */
1748 if (c2->stack_usage > 16 * 4)
1760 debug_omit_fp (void)
1763 return mono_debug_count ();
1770 * mono_arch_compute_omit_fp:
1772 * Determine whenever the frame pointer can be eliminated.
1775 mono_arch_compute_omit_fp (MonoCompile *cfg)
1777 MonoMethodSignature *sig;
1778 MonoMethodHeader *header;
1782 if (cfg->arch.omit_fp_computed)
1785 header = cfg->header;
1787 sig = mono_method_signature (cfg->method);
1789 if (!cfg->arch.cinfo)
1790 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1791 cinfo = cfg->arch.cinfo;
1794 * FIXME: Remove some of the restrictions.
1796 cfg->arch.omit_fp = TRUE;
1797 cfg->arch.omit_fp_computed = TRUE;
1799 if (cfg->disable_omit_fp)
1800 cfg->arch.omit_fp = FALSE;
1801 if (!debug_omit_fp ())
1802 cfg->arch.omit_fp = FALSE;
1804 if (cfg->method->save_lmf)
1805 cfg->arch.omit_fp = FALSE;
1807 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1808 cfg->arch.omit_fp = FALSE;
1809 if (header->num_clauses)
1810 cfg->arch.omit_fp = FALSE;
1811 if (cfg->param_area)
1812 cfg->arch.omit_fp = FALSE;
1813 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1814 cfg->arch.omit_fp = FALSE;
1815 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1816 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1817 cfg->arch.omit_fp = FALSE;
1818 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1819 ArgInfo *ainfo = &cinfo->args [i];
1821 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1823 * The stack offset can only be determined when the frame
1826 cfg->arch.omit_fp = FALSE;
1831 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1832 MonoInst *ins = cfg->varinfo [i];
1835 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1840 * Set var information according to the calling convention. arm version.
1841 * The locals var stuff should most likely be split in another method.
1844 mono_arch_allocate_vars (MonoCompile *cfg)
1846 MonoMethodSignature *sig;
1847 MonoMethodHeader *header;
1850 int i, offset, size, align, curinst;
1855 sig = mono_method_signature (cfg->method);
1857 if (!cfg->arch.cinfo)
1858 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1859 cinfo = cfg->arch.cinfo;
1860 sig_ret = mini_get_underlying_type (sig->ret);
1862 mono_arch_compute_omit_fp (cfg);
1864 if (cfg->arch.omit_fp)
1865 cfg->frame_reg = ARMREG_SP;
1867 cfg->frame_reg = ARMREG_FP;
1869 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1871 /* allow room for the vararg method args: void* and long/double */
1872 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1873 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1875 header = cfg->header;
1877 /* See mono_arch_get_global_int_regs () */
1878 if (cfg->flags & MONO_CFG_HAS_CALLS)
1879 cfg->uses_rgctx_reg = TRUE;
1881 if (cfg->frame_reg != ARMREG_SP)
1882 cfg->used_int_regs |= 1 << cfg->frame_reg;
1884 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1885 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1886 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1890 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1891 if (sig_ret->type != MONO_TYPE_VOID) {
1892 cfg->ret->opcode = OP_REGVAR;
1893 cfg->ret->inst_c0 = ARMREG_R0;
1896 /* local vars are at a positive offset from the stack pointer */
1898 * also note that if the function uses alloca, we use FP
1899 * to point at the local variables.
1901 offset = 0; /* linkage area */
1902 /* align the offset to 16 bytes: not sure this is needed here */
1904 //offset &= ~(8 - 1);
1906 /* add parameter area size for called functions */
1907 offset += cfg->param_area;
1910 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1913 /* allow room to save the return value */
1914 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1917 switch (cinfo->ret.storage) {
1918 case RegTypeStructByVal:
1919 cfg->ret->opcode = OP_REGOFFSET;
1920 cfg->ret->inst_basereg = cfg->frame_reg;
1921 offset += sizeof (gpointer) - 1;
1922 offset &= ~(sizeof (gpointer) - 1);
1923 cfg->ret->inst_offset = - offset;
1924 offset += sizeof(gpointer);
1927 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1928 offset = ALIGN_TO (offset, 8);
1929 cfg->ret->opcode = OP_REGOFFSET;
1930 cfg->ret->inst_basereg = cfg->frame_reg;
1931 cfg->ret->inst_offset = offset;
1935 case RegTypeStructByAddr:
1936 ins = cfg->vret_addr;
1937 offset += sizeof(gpointer) - 1;
1938 offset &= ~(sizeof(gpointer) - 1);
1939 ins->inst_offset = offset;
1940 ins->opcode = OP_REGOFFSET;
1941 ins->inst_basereg = cfg->frame_reg;
1942 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1943 g_print ("vret_addr =");
1944 mono_print_ins (cfg->vret_addr);
1946 offset += sizeof(gpointer);
1952 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1953 if (cfg->arch.seq_point_info_var) {
1956 ins = cfg->arch.seq_point_info_var;
1960 offset += align - 1;
1961 offset &= ~(align - 1);
1962 ins->opcode = OP_REGOFFSET;
1963 ins->inst_basereg = cfg->frame_reg;
1964 ins->inst_offset = offset;
1967 ins = cfg->arch.ss_trigger_page_var;
1970 offset += align - 1;
1971 offset &= ~(align - 1);
1972 ins->opcode = OP_REGOFFSET;
1973 ins->inst_basereg = cfg->frame_reg;
1974 ins->inst_offset = offset;
1978 if (cfg->arch.seq_point_ss_method_var) {
1981 ins = cfg->arch.seq_point_ss_method_var;
1984 offset += align - 1;
1985 offset &= ~(align - 1);
1986 ins->opcode = OP_REGOFFSET;
1987 ins->inst_basereg = cfg->frame_reg;
1988 ins->inst_offset = offset;
1991 ins = cfg->arch.seq_point_bp_method_var;
1994 offset += align - 1;
1995 offset &= ~(align - 1);
1996 ins->opcode = OP_REGOFFSET;
1997 ins->inst_basereg = cfg->frame_reg;
1998 ins->inst_offset = offset;
2002 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
2003 /* Allocate a temporary used by the atomic ops */
2007 /* Allocate a local slot to hold the sig cookie address */
2008 offset += align - 1;
2009 offset &= ~(align - 1);
2010 cfg->arch.atomic_tmp_offset = offset;
2013 cfg->arch.atomic_tmp_offset = -1;
2016 cfg->locals_min_stack_offset = offset;
2018 curinst = cfg->locals_start;
2019 for (i = curinst; i < cfg->num_varinfo; ++i) {
2022 ins = cfg->varinfo [i];
2023 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
2026 t = ins->inst_vtype;
2027 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
2030 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
2031 * pinvoke wrappers when they call functions returning structure */
2032 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2033 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
2037 size = mono_type_size (t, &align);
2039 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2040 * since it loads/stores misaligned words, which don't do the right thing.
2042 if (align < 4 && size >= 4)
2044 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2045 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2046 offset += align - 1;
2047 offset &= ~(align - 1);
2048 ins->opcode = OP_REGOFFSET;
2049 ins->inst_offset = offset;
2050 ins->inst_basereg = cfg->frame_reg;
2052 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2055 cfg->locals_max_stack_offset = offset;
2059 ins = cfg->args [curinst];
2060 if (ins->opcode != OP_REGVAR) {
2061 ins->opcode = OP_REGOFFSET;
2062 ins->inst_basereg = cfg->frame_reg;
2063 offset += sizeof (gpointer) - 1;
2064 offset &= ~(sizeof (gpointer) - 1);
2065 ins->inst_offset = offset;
2066 offset += sizeof (gpointer);
2071 if (sig->call_convention == MONO_CALL_VARARG) {
2075 /* Allocate a local slot to hold the sig cookie address */
2076 offset += align - 1;
2077 offset &= ~(align - 1);
2078 cfg->sig_cookie = offset;
2082 for (i = 0; i < sig->param_count; ++i) {
2083 ainfo = cinfo->args + i;
2085 ins = cfg->args [curinst];
2087 switch (ainfo->storage) {
2089 offset = ALIGN_TO (offset, 8);
2090 ins->opcode = OP_REGOFFSET;
2091 ins->inst_basereg = cfg->frame_reg;
2092 /* These arguments are saved to the stack in the prolog */
2093 ins->inst_offset = offset;
2094 if (cfg->verbose_level >= 2)
2095 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2103 if (ins->opcode != OP_REGVAR) {
2104 ins->opcode = OP_REGOFFSET;
2105 ins->inst_basereg = cfg->frame_reg;
2106 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2108 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2109 * since it loads/stores misaligned words, which don't do the right thing.
2111 if (align < 4 && size >= 4)
2113 /* The code in the prolog () stores words when storing vtypes received in a register */
2114 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2116 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2117 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2118 offset += align - 1;
2119 offset &= ~(align - 1);
2120 ins->inst_offset = offset;
2126 /* align the offset to 8 bytes */
2127 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2128 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2133 cfg->stack_offset = offset;
2137 mono_arch_create_vars (MonoCompile *cfg)
2139 MonoMethodSignature *sig;
2143 sig = mono_method_signature (cfg->method);
2145 if (!cfg->arch.cinfo)
2146 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2147 cinfo = cfg->arch.cinfo;
2149 if (IS_HARD_FLOAT) {
2150 for (i = 0; i < 2; i++) {
2151 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2152 inst->flags |= MONO_INST_VOLATILE;
2154 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2158 if (cinfo->ret.storage == RegTypeStructByVal)
2159 cfg->ret_var_is_local = TRUE;
2161 if (cinfo->ret.storage == RegTypeStructByAddr) {
2162 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2163 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2164 g_print ("vret_addr = ");
2165 mono_print_ins (cfg->vret_addr);
2169 if (cfg->gen_sdb_seq_points) {
2170 if (cfg->soft_breakpoints) {
2173 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2174 ins->flags |= MONO_INST_VOLATILE;
2175 cfg->arch.seq_point_ss_method_var = ins;
2177 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2178 ins->flags |= MONO_INST_VOLATILE;
2179 cfg->arch.seq_point_bp_method_var = ins;
2181 g_assert (!cfg->compile_aot);
2182 } else if (cfg->compile_aot) {
2183 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2184 ins->flags |= MONO_INST_VOLATILE;
2185 cfg->arch.seq_point_info_var = ins;
2187 /* Allocate a separate variable for this to save 1 load per seq point */
2188 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2189 ins->flags |= MONO_INST_VOLATILE;
2190 cfg->arch.ss_trigger_page_var = ins;
2196 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2198 MonoMethodSignature *tmp_sig;
2201 if (call->tail_call)
2204 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2207 * mono_ArgIterator_Setup assumes the signature cookie is
2208 * passed first and all the arguments which were before it are
2209 * passed on the stack after the signature. So compensate by
2210 * passing a different signature.
2212 tmp_sig = mono_metadata_signature_dup (call->signature);
2213 tmp_sig->param_count -= call->signature->sentinelpos;
2214 tmp_sig->sentinelpos = 0;
2215 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2217 sig_reg = mono_alloc_ireg (cfg);
2218 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2220 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2225 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2230 LLVMCallInfo *linfo;
2232 n = sig->param_count + sig->hasthis;
2234 cinfo = get_call_info (cfg->mempool, sig);
2236 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2239 * LLVM always uses the native ABI while we use our own ABI, the
2240 * only difference is the handling of vtypes:
2241 * - we only pass/receive them in registers in some cases, and only
2242 * in 1 or 2 integer registers.
2244 switch (cinfo->ret.storage) {
2245 case RegTypeGeneral:
2248 case RegTypeIRegPair:
2250 case RegTypeStructByAddr:
2251 /* Vtype returned using a hidden argument */
2252 linfo->ret.storage = LLVMArgVtypeRetAddr;
2253 linfo->vret_arg_index = cinfo->vret_arg_index;
2256 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2257 cfg->disable_llvm = TRUE;
2261 for (i = 0; i < n; ++i) {
2262 ainfo = cinfo->args + i;
2264 linfo->args [i].storage = LLVMArgNone;
2266 switch (ainfo->storage) {
2267 case RegTypeGeneral:
2268 case RegTypeIRegPair:
2270 case RegTypeBaseGen:
2271 linfo->args [i].storage = LLVMArgNormal;
2273 case RegTypeStructByVal:
2274 linfo->args [i].storage = LLVMArgAsIArgs;
2275 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2278 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2279 cfg->disable_llvm = TRUE;
2289 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2292 MonoMethodSignature *sig;
2296 sig = call->signature;
2297 n = sig->param_count + sig->hasthis;
2299 cinfo = get_call_info (cfg->mempool, sig);
2301 switch (cinfo->ret.storage) {
2302 case RegTypeStructByVal:
2303 /* The JIT will transform this into a normal call */
2304 call->vret_in_reg = TRUE;
2308 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2309 * the location pointed to by it after call in emit_move_return_value ().
2311 if (!cfg->arch.vret_addr_loc) {
2312 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2313 /* Prevent it from being register allocated or optimized away */
2314 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2317 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2319 case RegTypeStructByAddr: {
2321 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2322 vtarg->sreg1 = call->vret_var->dreg;
2323 vtarg->dreg = mono_alloc_preg (cfg);
2324 MONO_ADD_INS (cfg->cbb, vtarg);
2326 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2333 for (i = 0; i < n; ++i) {
2334 ArgInfo *ainfo = cinfo->args + i;
2337 if (i >= sig->hasthis)
2338 t = sig->params [i - sig->hasthis];
2340 t = &mono_defaults.int_class->byval_arg;
2341 t = mini_get_underlying_type (t);
2343 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2344 /* Emit the signature cookie just before the implicit arguments */
2345 emit_sig_cookie (cfg, call, cinfo);
2348 in = call->args [i];
2350 switch (ainfo->storage) {
2351 case RegTypeGeneral:
2352 case RegTypeIRegPair:
2353 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2354 MONO_INST_NEW (cfg, ins, OP_MOVE);
2355 ins->dreg = mono_alloc_ireg (cfg);
2356 ins->sreg1 = in->dreg + 1;
2357 MONO_ADD_INS (cfg->cbb, ins);
2358 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2360 MONO_INST_NEW (cfg, ins, OP_MOVE);
2361 ins->dreg = mono_alloc_ireg (cfg);
2362 ins->sreg1 = in->dreg + 2;
2363 MONO_ADD_INS (cfg->cbb, ins);
2364 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2365 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2366 if (ainfo->size == 4) {
2367 if (IS_SOFT_FLOAT) {
2368 /* mono_emit_call_args () have already done the r8->r4 conversion */
2369 /* The converted value is in an int vreg */
2370 MONO_INST_NEW (cfg, ins, OP_MOVE);
2371 ins->dreg = mono_alloc_ireg (cfg);
2372 ins->sreg1 = in->dreg;
2373 MONO_ADD_INS (cfg->cbb, ins);
2374 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2378 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2379 creg = mono_alloc_ireg (cfg);
2380 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2381 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2384 if (IS_SOFT_FLOAT) {
2385 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2386 ins->dreg = mono_alloc_ireg (cfg);
2387 ins->sreg1 = in->dreg;
2388 MONO_ADD_INS (cfg->cbb, ins);
2389 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2391 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2392 ins->dreg = mono_alloc_ireg (cfg);
2393 ins->sreg1 = in->dreg;
2394 MONO_ADD_INS (cfg->cbb, ins);
2395 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2399 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2400 creg = mono_alloc_ireg (cfg);
2401 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2402 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2403 creg = mono_alloc_ireg (cfg);
2404 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2405 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2408 cfg->flags |= MONO_CFG_HAS_FPOUT;
2410 MONO_INST_NEW (cfg, ins, OP_MOVE);
2411 ins->dreg = mono_alloc_ireg (cfg);
2412 ins->sreg1 = in->dreg;
2413 MONO_ADD_INS (cfg->cbb, ins);
2415 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2418 case RegTypeStructByAddr:
2421 /* FIXME: where si the data allocated? */
2422 arg->backend.reg3 = ainfo->reg;
2423 call->used_iregs |= 1 << ainfo->reg;
2424 g_assert_not_reached ();
2427 case RegTypeStructByVal:
2428 case RegTypeGSharedVtInReg:
2429 case RegTypeGSharedVtOnStack:
2431 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2432 ins->opcode = OP_OUTARG_VT;
2433 ins->sreg1 = in->dreg;
2434 ins->klass = in->klass;
2435 ins->inst_p0 = call;
2436 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2437 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2438 mono_call_inst_add_outarg_vt (cfg, call, ins);
2439 MONO_ADD_INS (cfg->cbb, ins);
2442 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2443 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2444 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2445 if (t->type == MONO_TYPE_R8) {
2446 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2449 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2451 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2454 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2457 case RegTypeBaseGen:
2458 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2459 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
2460 MONO_INST_NEW (cfg, ins, OP_MOVE);
2461 ins->dreg = mono_alloc_ireg (cfg);
2462 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
2463 MONO_ADD_INS (cfg->cbb, ins);
2464 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2465 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2468 /* This should work for soft-float as well */
2470 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2471 creg = mono_alloc_ireg (cfg);
2472 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2473 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2474 creg = mono_alloc_ireg (cfg);
2475 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2476 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2477 cfg->flags |= MONO_CFG_HAS_FPOUT;
2479 g_assert_not_reached ();
2483 int fdreg = mono_alloc_freg (cfg);
2485 if (ainfo->size == 8) {
2486 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2487 ins->sreg1 = in->dreg;
2489 MONO_ADD_INS (cfg->cbb, ins);
2491 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2496 * Mono's register allocator doesn't speak single-precision registers that
2497 * overlap double-precision registers (i.e. armhf). So we have to work around
2498 * the register allocator and load the value from memory manually.
2500 * So we create a variable for the float argument and an instruction to store
2501 * the argument into the variable. We then store the list of these arguments
2502 * in cfg->float_args. This list is then used by emit_float_args later to
2503 * pass the arguments in the various call opcodes.
2505 * This is not very nice, and we should really try to fix the allocator.
2508 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2510 /* Make sure the instruction isn't seen as pointless and removed.
2512 float_arg->flags |= MONO_INST_VOLATILE;
2514 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2516 /* We use the dreg to look up the instruction later. The hreg is used to
2517 * emit the instruction that loads the value into the FP reg.
2519 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2520 fad->vreg = float_arg->dreg;
2521 fad->hreg = ainfo->reg;
2523 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2526 call->used_iregs |= 1 << ainfo->reg;
2527 cfg->flags |= MONO_CFG_HAS_FPOUT;
2531 g_assert_not_reached ();
2535 /* Handle the case where there are no implicit arguments */
2536 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2537 emit_sig_cookie (cfg, call, cinfo);
2539 call->call_info = cinfo;
2540 call->stack_usage = cinfo->stack_usage;
2544 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2550 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2551 ins->dreg = mono_alloc_freg (cfg);
2552 ins->sreg1 = arg->dreg;
2553 MONO_ADD_INS (cfg->cbb, ins);
2554 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2557 g_assert_not_reached ();
2563 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2565 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2567 ArgInfo *ainfo = ins->inst_p1;
2568 int ovf_size = ainfo->vtsize;
2569 int doffset = ainfo->offset;
2570 int struct_size = ainfo->struct_size;
2571 int i, soffset, dreg, tmpreg;
2573 switch (ainfo->storage) {
2574 case RegTypeGSharedVtInReg:
2576 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2578 case RegTypeGSharedVtOnStack:
2579 /* Pass by addr on stack */
2580 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2583 for (i = 0; i < ainfo->nregs; ++i) {
2584 if (ainfo->esize == 4)
2585 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2587 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2588 load->dreg = mono_alloc_freg (cfg);
2589 load->inst_basereg = src->dreg;
2590 load->inst_offset = i * ainfo->esize;
2591 MONO_ADD_INS (cfg->cbb, load);
2593 if (ainfo->esize == 4) {
2596 /* See RegTypeFP in mono_arch_emit_call () */
2597 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2598 float_arg->flags |= MONO_INST_VOLATILE;
2599 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2601 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2602 fad->vreg = float_arg->dreg;
2603 fad->hreg = ainfo->reg + i;
2605 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2607 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2613 for (i = 0; i < ainfo->size; ++i) {
2614 dreg = mono_alloc_ireg (cfg);
2615 switch (struct_size) {
2617 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2620 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2623 tmpreg = mono_alloc_ireg (cfg);
2624 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2625 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2626 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2627 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2628 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2629 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2630 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2633 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2636 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2637 soffset += sizeof (gpointer);
2638 struct_size -= sizeof (gpointer);
2640 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2642 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2648 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2650 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2653 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2656 if (COMPILE_LLVM (cfg)) {
2657 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2659 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2660 ins->sreg1 = val->dreg + 1;
2661 ins->sreg2 = val->dreg + 2;
2662 MONO_ADD_INS (cfg->cbb, ins);
2667 case MONO_ARM_FPU_NONE:
2668 if (ret->type == MONO_TYPE_R8) {
2671 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2672 ins->dreg = cfg->ret->dreg;
2673 ins->sreg1 = val->dreg;
2674 MONO_ADD_INS (cfg->cbb, ins);
2677 if (ret->type == MONO_TYPE_R4) {
2678 /* Already converted to an int in method_to_ir () */
2679 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2683 case MONO_ARM_FPU_VFP:
2684 case MONO_ARM_FPU_VFP_HARD:
2685 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2688 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2689 ins->dreg = cfg->ret->dreg;
2690 ins->sreg1 = val->dreg;
2691 MONO_ADD_INS (cfg->cbb, ins);
2696 g_assert_not_reached ();
2700 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2703 #endif /* #ifndef DISABLE_JIT */
2706 mono_arch_is_inst_imm (gint64 imm)
2712 MonoMethodSignature *sig;
2715 MonoType **param_types;
2719 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2723 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2726 switch (cinfo->ret.storage) {
2728 case RegTypeGeneral:
2729 case RegTypeIRegPair:
2730 case RegTypeStructByAddr:
2741 for (i = 0; i < cinfo->nargs; ++i) {
2742 ArgInfo *ainfo = &cinfo->args [i];
2745 switch (ainfo->storage) {
2746 case RegTypeGeneral:
2747 case RegTypeIRegPair:
2748 case RegTypeBaseGen:
2751 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2754 case RegTypeStructByVal:
2755 if (ainfo->size == 0)
2756 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2758 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2759 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2767 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2768 for (i = 0; i < sig->param_count; ++i) {
2769 MonoType *t = sig->params [i];
2774 t = mini_get_underlying_type (t);
2797 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2799 ArchDynCallInfo *info;
2803 cinfo = get_call_info (NULL, sig);
2805 if (!dyn_call_supported (cinfo, sig)) {
2810 info = g_new0 (ArchDynCallInfo, 1);
2811 // FIXME: Preprocess the info to speed up start_dyn_call ()
2813 info->cinfo = cinfo;
2814 info->rtype = mini_get_underlying_type (sig->ret);
2815 info->param_types = g_new0 (MonoType*, sig->param_count);
2816 for (i = 0; i < sig->param_count; ++i)
2817 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2819 return (MonoDynCallInfo*)info;
2823 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2825 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2827 g_free (ainfo->cinfo);
2832 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2834 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2835 DynCallArgs *p = (DynCallArgs*)buf;
2836 int arg_index, greg, i, j, pindex;
2837 MonoMethodSignature *sig = dinfo->sig;
2839 g_assert (buf_len >= sizeof (DynCallArgs));
2848 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2849 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2854 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2855 p->regs [greg ++] = (mgreg_t)ret;
2857 for (i = pindex; i < sig->param_count; i++) {
2858 MonoType *t = dinfo->param_types [i];
2859 gpointer *arg = args [arg_index ++];
2860 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2863 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2865 } else if (ainfo->storage == RegTypeBase) {
2866 slot = PARAM_REGS + (ainfo->offset / 4);
2867 } else if (ainfo->storage == RegTypeBaseGen) {
2868 /* slot + 1 is the first stack slot, so the code below will work */
2871 g_assert_not_reached ();
2875 p->regs [slot] = (mgreg_t)*arg;
2880 case MONO_TYPE_STRING:
2881 case MONO_TYPE_CLASS:
2882 case MONO_TYPE_ARRAY:
2883 case MONO_TYPE_SZARRAY:
2884 case MONO_TYPE_OBJECT:
2888 p->regs [slot] = (mgreg_t)*arg;
2891 p->regs [slot] = *(guint8*)arg;
2894 p->regs [slot] = *(gint8*)arg;
2897 p->regs [slot] = *(gint16*)arg;
2900 p->regs [slot] = *(guint16*)arg;
2903 p->regs [slot] = *(gint32*)arg;
2906 p->regs [slot] = *(guint32*)arg;
2910 p->regs [slot ++] = (mgreg_t)arg [0];
2911 p->regs [slot] = (mgreg_t)arg [1];
2914 p->regs [slot] = *(mgreg_t*)arg;
2917 p->regs [slot ++] = (mgreg_t)arg [0];
2918 p->regs [slot] = (mgreg_t)arg [1];
2920 case MONO_TYPE_GENERICINST:
2921 if (MONO_TYPE_IS_REFERENCE (t)) {
2922 p->regs [slot] = (mgreg_t)*arg;
2925 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2926 MonoClass *klass = mono_class_from_mono_type (t);
2927 guint8 *nullable_buf;
2930 size = mono_class_value_size (klass, NULL);
2931 nullable_buf = g_alloca (size);
2932 g_assert (nullable_buf);
2934 /* The argument pointed to by arg is either a boxed vtype or null */
2935 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2937 arg = (gpointer*)nullable_buf;
2943 case MONO_TYPE_VALUETYPE:
2944 g_assert (ainfo->storage == RegTypeStructByVal);
2946 if (ainfo->size == 0)
2947 slot = PARAM_REGS + (ainfo->offset / 4);
2951 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2952 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2955 g_assert_not_reached ();
2961 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2963 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2964 MonoType *ptype = ainfo->rtype;
2965 guint8 *ret = ((DynCallArgs*)buf)->ret;
2966 mgreg_t res = ((DynCallArgs*)buf)->res;
2967 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2969 switch (ptype->type) {
2970 case MONO_TYPE_VOID:
2971 *(gpointer*)ret = NULL;
2973 case MONO_TYPE_STRING:
2974 case MONO_TYPE_CLASS:
2975 case MONO_TYPE_ARRAY:
2976 case MONO_TYPE_SZARRAY:
2977 case MONO_TYPE_OBJECT:
2981 *(gpointer*)ret = (gpointer)res;
2987 *(guint8*)ret = res;
2990 *(gint16*)ret = res;
2993 *(guint16*)ret = res;
2996 *(gint32*)ret = res;
2999 *(guint32*)ret = res;
3003 /* This handles endianness as well */
3004 ((gint32*)ret) [0] = res;
3005 ((gint32*)ret) [1] = res2;
3007 case MONO_TYPE_GENERICINST:
3008 if (MONO_TYPE_IS_REFERENCE (ptype)) {
3009 *(gpointer*)ret = (gpointer)res;
3014 case MONO_TYPE_VALUETYPE:
3015 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
3020 *(float*)ret = *(float*)&res;
3022 case MONO_TYPE_R8: {
3029 *(double*)ret = *(double*)®s;
3033 g_assert_not_reached ();
3040 * Allow tracing to work with this interface (with an optional argument)
3044 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3048 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3049 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3050 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3051 code = emit_call_reg (code, ARMREG_R2);
3065 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3068 int save_mode = SAVE_NONE;
3070 MonoMethod *method = cfg->method;
3071 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3072 int rtype = ret_type->type;
3073 int save_offset = cfg->param_area;
3077 offset = code - cfg->native_code;
3078 /* we need about 16 instructions */
3079 if (offset > (cfg->code_size - 16 * 4)) {
3080 cfg->code_size *= 2;
3081 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3082 code = cfg->native_code + offset;
3085 case MONO_TYPE_VOID:
3086 /* special case string .ctor icall */
3087 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3088 save_mode = SAVE_ONE;
3090 save_mode = SAVE_NONE;
3094 save_mode = SAVE_TWO;
3098 save_mode = SAVE_ONE_FP;
3100 save_mode = SAVE_ONE;
3104 save_mode = SAVE_TWO_FP;
3106 save_mode = SAVE_TWO;
3108 case MONO_TYPE_GENERICINST:
3109 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3110 save_mode = SAVE_ONE;
3114 case MONO_TYPE_VALUETYPE:
3115 save_mode = SAVE_STRUCT;
3118 save_mode = SAVE_ONE;
3122 switch (save_mode) {
3124 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3125 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3126 if (enable_arguments) {
3127 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3128 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3132 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3133 if (enable_arguments) {
3134 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3138 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3139 if (enable_arguments) {
3140 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3144 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3145 if (enable_arguments) {
3146 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3150 if (enable_arguments) {
3151 /* FIXME: get the actual address */
3152 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3160 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3161 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3162 code = emit_call_reg (code, ARMREG_IP);
3164 switch (save_mode) {
3166 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3167 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3170 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3173 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3176 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3187 * The immediate field for cond branches is big enough for all reasonable methods
3189 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3190 if (0 && ins->inst_true_bb->native_offset) { \
3191 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3193 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3194 ARM_B_COND (code, (condcode), 0); \
3197 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3199 /* emit an exception if condition is fail
3201 * We assign the extra code used to throw the implicit exceptions
3202 * to cfg->bb_exit as far as the big branch handling is concerned
3204 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3206 mono_add_patch_info (cfg, code - cfg->native_code, \
3207 MONO_PATCH_INFO_EXC, exc_name); \
3208 ARM_BL_COND (code, (condcode), 0); \
3211 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3214 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3219 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3223 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3224 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3226 switch (ins->opcode) {
3229 /* Already done by an arch-independent pass */
3231 case OP_LOAD_MEMBASE:
3232 case OP_LOADI4_MEMBASE:
3234 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3235 * OP_LOAD_MEMBASE offset(basereg), reg
3237 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3238 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3239 ins->inst_basereg == last_ins->inst_destbasereg &&
3240 ins->inst_offset == last_ins->inst_offset) {
3241 if (ins->dreg == last_ins->sreg1) {
3242 MONO_DELETE_INS (bb, ins);
3245 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3246 ins->opcode = OP_MOVE;
3247 ins->sreg1 = last_ins->sreg1;
3251 * Note: reg1 must be different from the basereg in the second load
3252 * OP_LOAD_MEMBASE offset(basereg), reg1
3253 * OP_LOAD_MEMBASE offset(basereg), reg2
3255 * OP_LOAD_MEMBASE offset(basereg), reg1
3256 * OP_MOVE reg1, reg2
3258 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3259 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3260 ins->inst_basereg != last_ins->dreg &&
3261 ins->inst_basereg == last_ins->inst_basereg &&
3262 ins->inst_offset == last_ins->inst_offset) {
3264 if (ins->dreg == last_ins->dreg) {
3265 MONO_DELETE_INS (bb, ins);
3268 ins->opcode = OP_MOVE;
3269 ins->sreg1 = last_ins->dreg;
3272 //g_assert_not_reached ();
3276 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3277 * OP_LOAD_MEMBASE offset(basereg), reg
3279 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3280 * OP_ICONST reg, imm
3282 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3283 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3284 ins->inst_basereg == last_ins->inst_destbasereg &&
3285 ins->inst_offset == last_ins->inst_offset) {
3286 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3287 ins->opcode = OP_ICONST;
3288 ins->inst_c0 = last_ins->inst_imm;
3289 g_assert_not_reached (); // check this rule
3293 case OP_LOADU1_MEMBASE:
3294 case OP_LOADI1_MEMBASE:
3295 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3296 ins->inst_basereg == last_ins->inst_destbasereg &&
3297 ins->inst_offset == last_ins->inst_offset) {
3298 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3299 ins->sreg1 = last_ins->sreg1;
3302 case OP_LOADU2_MEMBASE:
3303 case OP_LOADI2_MEMBASE:
3304 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3305 ins->inst_basereg == last_ins->inst_destbasereg &&
3306 ins->inst_offset == last_ins->inst_offset) {
3307 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3308 ins->sreg1 = last_ins->sreg1;
3312 ins->opcode = OP_MOVE;
3316 if (ins->dreg == ins->sreg1) {
3317 MONO_DELETE_INS (bb, ins);
3321 * OP_MOVE sreg, dreg
3322 * OP_MOVE dreg, sreg
3324 if (last_ins && last_ins->opcode == OP_MOVE &&
3325 ins->sreg1 == last_ins->dreg &&
3326 ins->dreg == last_ins->sreg1) {
3327 MONO_DELETE_INS (bb, ins);
3336 * the branch_cc_table should maintain the order of these
3350 branch_cc_table [] = {
3364 #define ADD_NEW_INS(cfg,dest,op) do { \
3365 MONO_INST_NEW ((cfg), (dest), (op)); \
3366 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3370 map_to_reg_reg_op (int op)
3379 case OP_COMPARE_IMM:
3381 case OP_ICOMPARE_IMM:
3395 case OP_LOAD_MEMBASE:
3396 return OP_LOAD_MEMINDEX;
3397 case OP_LOADI4_MEMBASE:
3398 return OP_LOADI4_MEMINDEX;
3399 case OP_LOADU4_MEMBASE:
3400 return OP_LOADU4_MEMINDEX;
3401 case OP_LOADU1_MEMBASE:
3402 return OP_LOADU1_MEMINDEX;
3403 case OP_LOADI2_MEMBASE:
3404 return OP_LOADI2_MEMINDEX;
3405 case OP_LOADU2_MEMBASE:
3406 return OP_LOADU2_MEMINDEX;
3407 case OP_LOADI1_MEMBASE:
3408 return OP_LOADI1_MEMINDEX;
3409 case OP_STOREI1_MEMBASE_REG:
3410 return OP_STOREI1_MEMINDEX;
3411 case OP_STOREI2_MEMBASE_REG:
3412 return OP_STOREI2_MEMINDEX;
3413 case OP_STOREI4_MEMBASE_REG:
3414 return OP_STOREI4_MEMINDEX;
3415 case OP_STORE_MEMBASE_REG:
3416 return OP_STORE_MEMINDEX;
3417 case OP_STORER4_MEMBASE_REG:
3418 return OP_STORER4_MEMINDEX;
3419 case OP_STORER8_MEMBASE_REG:
3420 return OP_STORER8_MEMINDEX;
3421 case OP_STORE_MEMBASE_IMM:
3422 return OP_STORE_MEMBASE_REG;
3423 case OP_STOREI1_MEMBASE_IMM:
3424 return OP_STOREI1_MEMBASE_REG;
3425 case OP_STOREI2_MEMBASE_IMM:
3426 return OP_STOREI2_MEMBASE_REG;
3427 case OP_STOREI4_MEMBASE_IMM:
3428 return OP_STOREI4_MEMBASE_REG;
3430 g_assert_not_reached ();
3434 * Remove from the instruction list the instructions that can't be
3435 * represented with very simple instructions with no register
3439 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3441 MonoInst *ins, *temp, *last_ins = NULL;
3442 int rot_amount, imm8, low_imm;
3444 MONO_BB_FOR_EACH_INS (bb, ins) {
3446 switch (ins->opcode) {
3450 case OP_COMPARE_IMM:
3451 case OP_ICOMPARE_IMM:
3465 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3466 ADD_NEW_INS (cfg, temp, OP_ICONST);
3467 temp->inst_c0 = ins->inst_imm;
3468 temp->dreg = mono_alloc_ireg (cfg);
3469 ins->sreg2 = temp->dreg;
3470 ins->opcode = mono_op_imm_to_op (ins->opcode);
3472 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3478 if (ins->inst_imm == 1) {
3479 ins->opcode = OP_MOVE;
3482 if (ins->inst_imm == 0) {
3483 ins->opcode = OP_ICONST;
3487 imm8 = mono_is_power_of_two (ins->inst_imm);
3489 ins->opcode = OP_SHL_IMM;
3490 ins->inst_imm = imm8;
3493 ADD_NEW_INS (cfg, temp, OP_ICONST);
3494 temp->inst_c0 = ins->inst_imm;
3495 temp->dreg = mono_alloc_ireg (cfg);
3496 ins->sreg2 = temp->dreg;
3497 ins->opcode = OP_IMUL;
3503 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3504 /* ARM sets the C flag to 1 if there was _no_ overflow */
3505 ins->next->opcode = OP_COND_EXC_NC;
3508 case OP_IDIV_UN_IMM:
3510 case OP_IREM_UN_IMM:
3511 ADD_NEW_INS (cfg, temp, OP_ICONST);
3512 temp->inst_c0 = ins->inst_imm;
3513 temp->dreg = mono_alloc_ireg (cfg);
3514 ins->sreg2 = temp->dreg;
3515 ins->opcode = mono_op_imm_to_op (ins->opcode);
3517 case OP_LOCALLOC_IMM:
3518 ADD_NEW_INS (cfg, temp, OP_ICONST);
3519 temp->inst_c0 = ins->inst_imm;
3520 temp->dreg = mono_alloc_ireg (cfg);
3521 ins->sreg1 = temp->dreg;
3522 ins->opcode = OP_LOCALLOC;
3524 case OP_LOAD_MEMBASE:
3525 case OP_LOADI4_MEMBASE:
3526 case OP_LOADU4_MEMBASE:
3527 case OP_LOADU1_MEMBASE:
3528 /* we can do two things: load the immed in a register
3529 * and use an indexed load, or see if the immed can be
3530 * represented as an ad_imm + a load with a smaller offset
3531 * that fits. We just do the first for now, optimize later.
3533 if (arm_is_imm12 (ins->inst_offset))
3535 ADD_NEW_INS (cfg, temp, OP_ICONST);
3536 temp->inst_c0 = ins->inst_offset;
3537 temp->dreg = mono_alloc_ireg (cfg);
3538 ins->sreg2 = temp->dreg;
3539 ins->opcode = map_to_reg_reg_op (ins->opcode);
3541 case OP_LOADI2_MEMBASE:
3542 case OP_LOADU2_MEMBASE:
3543 case OP_LOADI1_MEMBASE:
3544 if (arm_is_imm8 (ins->inst_offset))
3546 ADD_NEW_INS (cfg, temp, OP_ICONST);
3547 temp->inst_c0 = ins->inst_offset;
3548 temp->dreg = mono_alloc_ireg (cfg);
3549 ins->sreg2 = temp->dreg;
3550 ins->opcode = map_to_reg_reg_op (ins->opcode);
3552 case OP_LOADR4_MEMBASE:
3553 case OP_LOADR8_MEMBASE:
3554 if (arm_is_fpimm8 (ins->inst_offset))
3556 low_imm = ins->inst_offset & 0x1ff;
3557 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3558 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3559 temp->inst_imm = ins->inst_offset & ~0x1ff;
3560 temp->sreg1 = ins->inst_basereg;
3561 temp->dreg = mono_alloc_ireg (cfg);
3562 ins->inst_basereg = temp->dreg;
3563 ins->inst_offset = low_imm;
3567 ADD_NEW_INS (cfg, temp, OP_ICONST);
3568 temp->inst_c0 = ins->inst_offset;
3569 temp->dreg = mono_alloc_ireg (cfg);
3571 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3572 add_ins->sreg1 = ins->inst_basereg;
3573 add_ins->sreg2 = temp->dreg;
3574 add_ins->dreg = mono_alloc_ireg (cfg);
3576 ins->inst_basereg = add_ins->dreg;
3577 ins->inst_offset = 0;
3580 case OP_STORE_MEMBASE_REG:
3581 case OP_STOREI4_MEMBASE_REG:
3582 case OP_STOREI1_MEMBASE_REG:
3583 if (arm_is_imm12 (ins->inst_offset))
3585 ADD_NEW_INS (cfg, temp, OP_ICONST);
3586 temp->inst_c0 = ins->inst_offset;
3587 temp->dreg = mono_alloc_ireg (cfg);
3588 ins->sreg2 = temp->dreg;
3589 ins->opcode = map_to_reg_reg_op (ins->opcode);
3591 case OP_STOREI2_MEMBASE_REG:
3592 if (arm_is_imm8 (ins->inst_offset))
3594 ADD_NEW_INS (cfg, temp, OP_ICONST);
3595 temp->inst_c0 = ins->inst_offset;
3596 temp->dreg = mono_alloc_ireg (cfg);
3597 ins->sreg2 = temp->dreg;
3598 ins->opcode = map_to_reg_reg_op (ins->opcode);
3600 case OP_STORER4_MEMBASE_REG:
3601 case OP_STORER8_MEMBASE_REG:
3602 if (arm_is_fpimm8 (ins->inst_offset))
3604 low_imm = ins->inst_offset & 0x1ff;
3605 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3606 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3607 temp->inst_imm = ins->inst_offset & ~0x1ff;
3608 temp->sreg1 = ins->inst_destbasereg;
3609 temp->dreg = mono_alloc_ireg (cfg);
3610 ins->inst_destbasereg = temp->dreg;
3611 ins->inst_offset = low_imm;
3615 ADD_NEW_INS (cfg, temp, OP_ICONST);
3616 temp->inst_c0 = ins->inst_offset;
3617 temp->dreg = mono_alloc_ireg (cfg);
3619 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3620 add_ins->sreg1 = ins->inst_destbasereg;
3621 add_ins->sreg2 = temp->dreg;
3622 add_ins->dreg = mono_alloc_ireg (cfg);
3624 ins->inst_destbasereg = add_ins->dreg;
3625 ins->inst_offset = 0;
3628 case OP_STORE_MEMBASE_IMM:
3629 case OP_STOREI1_MEMBASE_IMM:
3630 case OP_STOREI2_MEMBASE_IMM:
3631 case OP_STOREI4_MEMBASE_IMM:
3632 ADD_NEW_INS (cfg, temp, OP_ICONST);
3633 temp->inst_c0 = ins->inst_imm;
3634 temp->dreg = mono_alloc_ireg (cfg);
3635 ins->sreg1 = temp->dreg;
3636 ins->opcode = map_to_reg_reg_op (ins->opcode);
3638 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3641 gboolean swap = FALSE;
3645 /* Optimized away */
3650 /* Some fp compares require swapped operands */
3651 switch (ins->next->opcode) {
3653 ins->next->opcode = OP_FBLT;
3657 ins->next->opcode = OP_FBLT_UN;
3661 ins->next->opcode = OP_FBGE;
3665 ins->next->opcode = OP_FBGE_UN;
3673 ins->sreg1 = ins->sreg2;
3682 bb->last_ins = last_ins;
3683 bb->max_vreg = cfg->next_vreg;
3687 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3691 if (long_ins->opcode == OP_LNEG) {
3693 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3694 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3700 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3702 /* sreg is a float, dreg is an integer reg */
3704 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3706 ARM_TOSIZD (code, vfp_scratch1, sreg);
3708 ARM_TOUIZD (code, vfp_scratch1, sreg);
3709 ARM_FMRS (code, dreg, vfp_scratch1);
3710 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3714 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3715 else if (size == 2) {
3716 ARM_SHL_IMM (code, dreg, dreg, 16);
3717 ARM_SHR_IMM (code, dreg, dreg, 16);
3721 ARM_SHL_IMM (code, dreg, dreg, 24);
3722 ARM_SAR_IMM (code, dreg, dreg, 24);
3723 } else if (size == 2) {
3724 ARM_SHL_IMM (code, dreg, dreg, 16);
3725 ARM_SAR_IMM (code, dreg, dreg, 16);
3732 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3734 /* sreg is a float, dreg is an integer reg */
3736 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3738 ARM_TOSIZS (code, vfp_scratch1, sreg);
3740 ARM_TOUIZS (code, vfp_scratch1, sreg);
3741 ARM_FMRS (code, dreg, vfp_scratch1);
3742 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3746 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3747 else if (size == 2) {
3748 ARM_SHL_IMM (code, dreg, dreg, 16);
3749 ARM_SHR_IMM (code, dreg, dreg, 16);
3753 ARM_SHL_IMM (code, dreg, dreg, 24);
3754 ARM_SAR_IMM (code, dreg, dreg, 24);
3755 } else if (size == 2) {
3756 ARM_SHL_IMM (code, dreg, dreg, 16);
3757 ARM_SAR_IMM (code, dreg, dreg, 16);
3763 #endif /* #ifndef DISABLE_JIT */
3765 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3768 emit_thunk (guint8 *code, gconstpointer target)
3772 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3773 if (thumb_supported)
3774 ARM_BX (code, ARMREG_IP);
3776 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3777 *(guint32*)code = (guint32)target;
3779 mono_arch_flush_icache (p, code - p);
3783 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3785 MonoJitInfo *ji = NULL;
3786 MonoThunkJitInfo *info;
3789 guint8 *orig_target;
3790 guint8 *target_thunk;
3793 domain = mono_domain_get ();
3797 * This can be called multiple times during JITting,
3798 * save the current position in cfg->arch to avoid
3799 * doing a O(n^2) search.
3801 if (!cfg->arch.thunks) {
3802 cfg->arch.thunks = cfg->thunks;
3803 cfg->arch.thunks_size = cfg->thunk_area;
3805 thunks = cfg->arch.thunks;
3806 thunks_size = cfg->arch.thunks_size;
3808 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3809 g_assert_not_reached ();
3812 g_assert (*(guint32*)thunks == 0);
3813 emit_thunk (thunks, target);
3814 arm_patch (code, thunks);
3816 cfg->arch.thunks += THUNK_SIZE;
3817 cfg->arch.thunks_size -= THUNK_SIZE;
3819 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3821 info = mono_jit_info_get_thunk_info (ji);
3824 thunks = (guint8*)ji->code_start + info->thunks_offset;
3825 thunks_size = info->thunks_size;
3827 orig_target = mono_arch_get_call_target (code + 4);
3829 mono_mini_arch_lock ();
3831 target_thunk = NULL;
3832 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3833 /* The call already points to a thunk, because of trampolines etc. */
3834 target_thunk = orig_target;
3836 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3837 if (((guint32*)p) [0] == 0) {
3841 } else if (((guint32*)p) [2] == (guint32)target) {
3842 /* Thunk already points to target */
3849 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3851 if (!target_thunk) {
3852 mono_mini_arch_unlock ();
3853 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3854 g_assert_not_reached ();
3857 emit_thunk (target_thunk, target);
3858 arm_patch (code, target_thunk);
3859 mono_arch_flush_icache (code, 4);
3861 mono_mini_arch_unlock ();
3866 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3868 guint32 *code32 = (void*)code;
3869 guint32 ins = *code32;
3870 guint32 prim = (ins >> 25) & 7;
3871 guint32 tval = GPOINTER_TO_UINT (target);
3873 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3874 if (prim == 5) { /* 101b */
3875 /* the diff starts 8 bytes from the branch opcode */
3876 gint diff = target - code - 8;
3878 gint tmask = 0xffffffff;
3879 if (tval & 1) { /* entering thumb mode */
3880 diff = target - 1 - code - 8;
3881 g_assert (thumb_supported);
3882 tbits = 0xf << 28; /* bl->blx bit pattern */
3883 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3884 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3888 tmask = ~(1 << 24); /* clear the link bit */
3889 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3894 if (diff <= 33554431) {
3896 ins = (ins & 0xff000000) | diff;
3898 *code32 = ins | tbits;
3902 /* diff between 0 and -33554432 */
3903 if (diff >= -33554432) {
3905 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3907 *code32 = ins | tbits;
3912 handle_thunk (cfg, domain, code, target);
3916 #ifdef USE_JUMP_TABLES
3918 gpointer *jte = mono_jumptable_get_entry (code);
3920 jte [0] = (gpointer) target;
3924 * The alternative call sequences looks like this:
3926 * ldr ip, [pc] // loads the address constant
3927 * b 1f // jumps around the constant
3928 * address constant embedded in the code
3933 * There are two cases for patching:
3934 * a) at the end of method emission: in this case code points to the start
3935 * of the call sequence
3936 * b) during runtime patching of the call site: in this case code points
3937 * to the mov pc, ip instruction
3939 * We have to handle also the thunk jump code sequence:
3943 * address constant // execution never reaches here
3945 if ((ins & 0x0ffffff0) == 0x12fff10) {
3946 /* Branch and exchange: the address is constructed in a reg
3947 * We can patch BX when the code sequence is the following:
3948 * ldr ip, [pc, #0] ; 0x8
3955 guint8 *emit = (guint8*)ccode;
3956 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3958 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3959 ARM_BX (emit, ARMREG_IP);
3961 /*patching from magic trampoline*/
3962 if (ins == ccode [3]) {
3963 g_assert (code32 [-4] == ccode [0]);
3964 g_assert (code32 [-3] == ccode [1]);
3965 g_assert (code32 [-1] == ccode [2]);
3966 code32 [-2] = (guint32)target;
3969 /*patching from JIT*/
3970 if (ins == ccode [0]) {
3971 g_assert (code32 [1] == ccode [1]);
3972 g_assert (code32 [3] == ccode [2]);
3973 g_assert (code32 [4] == ccode [3]);
3974 code32 [2] = (guint32)target;
3977 g_assert_not_reached ();
3978 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3986 guint8 *emit = (guint8*)ccode;
3987 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3989 ARM_BLX_REG (emit, ARMREG_IP);
3991 g_assert (code32 [-3] == ccode [0]);
3992 g_assert (code32 [-2] == ccode [1]);
3993 g_assert (code32 [0] == ccode [2]);
3995 code32 [-1] = (guint32)target;
3998 guint32 *tmp = ccode;
3999 guint8 *emit = (guint8*)tmp;
4000 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4001 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4002 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
4003 ARM_BX (emit, ARMREG_IP);
4004 if (ins == ccode [2]) {
4005 g_assert_not_reached (); // should be -2 ...
4006 code32 [-1] = (guint32)target;
4009 if (ins == ccode [0]) {
4010 /* handles both thunk jump code and the far call sequence */
4011 code32 [2] = (guint32)target;
4014 g_assert_not_reached ();
4016 // g_print ("patched with 0x%08x\n", ins);
4021 arm_patch (guchar *code, const guchar *target)
4023 arm_patch_general (NULL, NULL, code, target);
4027 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4028 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4029 * to be used with the emit macros.
4030 * Return -1 otherwise.
4033 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4036 for (i = 0; i < 31; i+= 2) {
4037 res = (val << (32 - i)) | (val >> i);
4040 *rot_amount = i? 32 - i: 0;
4047 * Emits in code a sequence of instructions that load the value 'val'
4048 * into the dreg register. Uses at most 4 instructions.
4051 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4053 int imm8, rot_amount;
4055 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4056 /* skip the constant pool */
4062 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4063 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4064 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4065 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4068 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4070 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4074 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4076 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4078 if (val & 0xFF0000) {
4079 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4081 if (val & 0xFF000000) {
4082 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4084 } else if (val & 0xFF00) {
4085 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4086 if (val & 0xFF0000) {
4087 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4089 if (val & 0xFF000000) {
4090 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4092 } else if (val & 0xFF0000) {
4093 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4094 if (val & 0xFF000000) {
4095 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4098 //g_assert_not_reached ();
4104 mono_arm_thumb_supported (void)
4106 return thumb_supported;
4112 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4117 call = (MonoCallInst*)ins;
4118 cinfo = call->call_info;
4120 switch (cinfo->ret.storage) {
4122 MonoInst *loc = cfg->arch.vret_addr_loc;
4125 /* Load the destination address */
4126 g_assert (loc && loc->opcode == OP_REGOFFSET);
4128 if (arm_is_imm12 (loc->inst_offset)) {
4129 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4131 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4132 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4134 for (i = 0; i < cinfo->ret.nregs; ++i) {
4135 if (cinfo->ret.esize == 4)
4136 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4138 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4146 switch (ins->opcode) {
4149 case OP_FCALL_MEMBASE:
4151 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4152 if (sig_ret->type == MONO_TYPE_R4) {
4153 if (IS_HARD_FLOAT) {
4154 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4156 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4157 ARM_CVTS (code, ins->dreg, ins->dreg);
4160 if (IS_HARD_FLOAT) {
4161 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4163 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4170 case OP_RCALL_MEMBASE: {
4175 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4176 g_assert (sig_ret->type == MONO_TYPE_R4);
4177 if (IS_HARD_FLOAT) {
4178 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4180 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4181 ARM_CPYS (code, ins->dreg, ins->dreg);
4193 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4198 guint8 *code = cfg->native_code + cfg->code_len;
4199 MonoInst *last_ins = NULL;
4200 guint last_offset = 0;
4202 int imm8, rot_amount;
4204 /* we don't align basic blocks of loops on arm */
4206 if (cfg->verbose_level > 2)
4207 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4209 cpos = bb->max_offset;
4211 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4212 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4213 //g_assert (!mono_compile_aot);
4216 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4217 /* this is not thread save, but good enough */
4218 /* fixme: howto handle overflows? */
4219 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4222 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4223 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4224 (gpointer)"mono_break");
4225 code = emit_call_seq (cfg, code);
4228 MONO_BB_FOR_EACH_INS (bb, ins) {
4229 offset = code - cfg->native_code;
4231 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4233 if (offset > (cfg->code_size - max_len - 16)) {
4234 cfg->code_size *= 2;
4235 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4236 code = cfg->native_code + offset;
4238 // if (ins->cil_code)
4239 // g_print ("cil code\n");
4240 mono_debug_record_line_number (cfg, ins, offset);
4242 switch (ins->opcode) {
4243 case OP_MEMORY_BARRIER:
4245 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4246 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4250 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4252 case OP_TLS_GET_REG:
4253 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4256 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4258 case OP_TLS_SET_REG:
4259 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4261 case OP_ATOMIC_EXCHANGE_I4:
4262 case OP_ATOMIC_CAS_I4:
4263 case OP_ATOMIC_ADD_I4: {
4267 g_assert (v7_supported);
4270 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4272 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4274 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4278 g_assert (cfg->arch.atomic_tmp_offset != -1);
4279 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4281 switch (ins->opcode) {
4282 case OP_ATOMIC_EXCHANGE_I4:
4284 ARM_DMB (code, ARM_DMB_SY);
4285 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4286 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4287 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4289 ARM_B_COND (code, ARMCOND_NE, 0);
4290 arm_patch (buf [1], buf [0]);
4292 case OP_ATOMIC_CAS_I4:
4293 ARM_DMB (code, ARM_DMB_SY);
4295 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4296 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4298 ARM_B_COND (code, ARMCOND_NE, 0);
4299 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4300 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4302 ARM_B_COND (code, ARMCOND_NE, 0);
4303 arm_patch (buf [2], buf [0]);
4304 arm_patch (buf [1], code);
4306 case OP_ATOMIC_ADD_I4:
4308 ARM_DMB (code, ARM_DMB_SY);
4309 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4310 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4311 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4312 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4314 ARM_B_COND (code, ARMCOND_NE, 0);
4315 arm_patch (buf [1], buf [0]);
4318 g_assert_not_reached ();
4321 ARM_DMB (code, ARM_DMB_SY);
4322 if (tmpreg != ins->dreg)
4323 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4324 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4327 case OP_ATOMIC_LOAD_I1:
4328 case OP_ATOMIC_LOAD_U1:
4329 case OP_ATOMIC_LOAD_I2:
4330 case OP_ATOMIC_LOAD_U2:
4331 case OP_ATOMIC_LOAD_I4:
4332 case OP_ATOMIC_LOAD_U4:
4333 case OP_ATOMIC_LOAD_R4:
4334 case OP_ATOMIC_LOAD_R8: {
4335 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4336 ARM_DMB (code, ARM_DMB_SY);
4338 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4340 switch (ins->opcode) {
4341 case OP_ATOMIC_LOAD_I1:
4342 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4344 case OP_ATOMIC_LOAD_U1:
4345 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4347 case OP_ATOMIC_LOAD_I2:
4348 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4350 case OP_ATOMIC_LOAD_U2:
4351 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4353 case OP_ATOMIC_LOAD_I4:
4354 case OP_ATOMIC_LOAD_U4:
4355 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4357 case OP_ATOMIC_LOAD_R4:
4359 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4360 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4362 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4363 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4364 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4365 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4366 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4369 case OP_ATOMIC_LOAD_R8:
4370 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4371 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4375 ARM_DMB (code, ARM_DMB_SY);
4378 case OP_ATOMIC_STORE_I1:
4379 case OP_ATOMIC_STORE_U1:
4380 case OP_ATOMIC_STORE_I2:
4381 case OP_ATOMIC_STORE_U2:
4382 case OP_ATOMIC_STORE_I4:
4383 case OP_ATOMIC_STORE_U4:
4384 case OP_ATOMIC_STORE_R4:
4385 case OP_ATOMIC_STORE_R8: {
4386 ARM_DMB (code, ARM_DMB_SY);
4388 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4390 switch (ins->opcode) {
4391 case OP_ATOMIC_STORE_I1:
4392 case OP_ATOMIC_STORE_U1:
4393 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4395 case OP_ATOMIC_STORE_I2:
4396 case OP_ATOMIC_STORE_U2:
4397 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4399 case OP_ATOMIC_STORE_I4:
4400 case OP_ATOMIC_STORE_U4:
4401 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4403 case OP_ATOMIC_STORE_R4:
4405 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4406 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4408 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4409 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4410 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4411 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4412 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4415 case OP_ATOMIC_STORE_R8:
4416 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4417 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4421 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4422 ARM_DMB (code, ARM_DMB_SY);
4426 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4427 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4430 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4431 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4433 case OP_STOREI1_MEMBASE_IMM:
4434 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4435 g_assert (arm_is_imm12 (ins->inst_offset));
4436 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4438 case OP_STOREI2_MEMBASE_IMM:
4439 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4440 g_assert (arm_is_imm8 (ins->inst_offset));
4441 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4443 case OP_STORE_MEMBASE_IMM:
4444 case OP_STOREI4_MEMBASE_IMM:
4445 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4446 g_assert (arm_is_imm12 (ins->inst_offset));
4447 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4449 case OP_STOREI1_MEMBASE_REG:
4450 g_assert (arm_is_imm12 (ins->inst_offset));
4451 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4453 case OP_STOREI2_MEMBASE_REG:
4454 g_assert (arm_is_imm8 (ins->inst_offset));
4455 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4457 case OP_STORE_MEMBASE_REG:
4458 case OP_STOREI4_MEMBASE_REG:
4459 /* this case is special, since it happens for spill code after lowering has been called */
4460 if (arm_is_imm12 (ins->inst_offset)) {
4461 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4463 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4464 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4467 case OP_STOREI1_MEMINDEX:
4468 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4470 case OP_STOREI2_MEMINDEX:
4471 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4473 case OP_STORE_MEMINDEX:
4474 case OP_STOREI4_MEMINDEX:
4475 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4478 g_assert_not_reached ();
4480 case OP_LOAD_MEMINDEX:
4481 case OP_LOADI4_MEMINDEX:
4482 case OP_LOADU4_MEMINDEX:
4483 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4485 case OP_LOADI1_MEMINDEX:
4486 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4488 case OP_LOADU1_MEMINDEX:
4489 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4491 case OP_LOADI2_MEMINDEX:
4492 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4494 case OP_LOADU2_MEMINDEX:
4495 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4497 case OP_LOAD_MEMBASE:
4498 case OP_LOADI4_MEMBASE:
4499 case OP_LOADU4_MEMBASE:
4500 /* this case is special, since it happens for spill code after lowering has been called */
4501 if (arm_is_imm12 (ins->inst_offset)) {
4502 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4504 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4505 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4508 case OP_LOADI1_MEMBASE:
4509 g_assert (arm_is_imm8 (ins->inst_offset));
4510 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4512 case OP_LOADU1_MEMBASE:
4513 g_assert (arm_is_imm12 (ins->inst_offset));
4514 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4516 case OP_LOADU2_MEMBASE:
4517 g_assert (arm_is_imm8 (ins->inst_offset));
4518 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4520 case OP_LOADI2_MEMBASE:
4521 g_assert (arm_is_imm8 (ins->inst_offset));
4522 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4524 case OP_ICONV_TO_I1:
4525 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4526 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4528 case OP_ICONV_TO_I2:
4529 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4530 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4532 case OP_ICONV_TO_U1:
4533 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4535 case OP_ICONV_TO_U2:
4536 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4537 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4541 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4543 case OP_COMPARE_IMM:
4544 case OP_ICOMPARE_IMM:
4545 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4546 g_assert (imm8 >= 0);
4547 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4551 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4552 * So instead of emitting a trap, we emit a call a C function and place a
4555 //*(int*)code = 0xef9f0001;
4558 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4559 (gpointer)"mono_break");
4560 code = emit_call_seq (cfg, code);
4562 case OP_RELAXED_NOP:
4567 case OP_DUMMY_STORE:
4568 case OP_DUMMY_ICONST:
4569 case OP_DUMMY_R8CONST:
4570 case OP_NOT_REACHED:
4573 case OP_IL_SEQ_POINT:
4574 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4576 case OP_SEQ_POINT: {
4578 MonoInst *info_var = cfg->arch.seq_point_info_var;
4579 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4580 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4581 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4583 int dreg = ARMREG_LR;
4585 if (cfg->soft_breakpoints) {
4586 g_assert (!cfg->compile_aot);
4590 * For AOT, we use one got slot per method, which will point to a
4591 * SeqPointInfo structure, containing all the information required
4592 * by the code below.
4594 if (cfg->compile_aot) {
4595 g_assert (info_var);
4596 g_assert (info_var->opcode == OP_REGOFFSET);
4597 g_assert (arm_is_imm12 (info_var->inst_offset));
4600 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4602 * Read from the single stepping trigger page. This will cause a
4603 * SIGSEGV when single stepping is enabled.
4604 * We do this _before_ the breakpoint, so single stepping after
4605 * a breakpoint is hit will step to the next IL offset.
4607 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4610 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4611 if (cfg->soft_breakpoints) {
4612 /* Load the address of the sequence point method variable. */
4613 var = ss_method_var;
4615 g_assert (var->opcode == OP_REGOFFSET);
4616 g_assert (arm_is_imm12 (var->inst_offset));
4617 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4619 /* Read the value and check whether it is non-zero. */
4620 ARM_LDR_IMM (code, dreg, dreg, 0);
4621 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4622 /* Call it conditionally. */
4623 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4625 if (cfg->compile_aot) {
4626 /* Load the trigger page addr from the variable initialized in the prolog */
4627 var = ss_trigger_page_var;
4629 g_assert (var->opcode == OP_REGOFFSET);
4630 g_assert (arm_is_imm12 (var->inst_offset));
4631 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4633 #ifdef USE_JUMP_TABLES
4634 gpointer *jte = mono_jumptable_add_entry ();
4635 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4636 jte [0] = ss_trigger_page;
4638 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4640 *(int*)code = (int)ss_trigger_page;
4644 ARM_LDR_IMM (code, dreg, dreg, 0);
4648 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4650 if (cfg->soft_breakpoints) {
4651 /* Load the address of the breakpoint method into ip. */
4652 var = bp_method_var;
4654 g_assert (var->opcode == OP_REGOFFSET);
4655 g_assert (arm_is_imm12 (var->inst_offset));
4656 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4659 * A placeholder for a possible breakpoint inserted by
4660 * mono_arch_set_breakpoint ().
4663 } else if (cfg->compile_aot) {
4664 guint32 offset = code - cfg->native_code;
4667 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4668 /* Add the offset */
4669 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4670 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4671 if (arm_is_imm12 ((int)val)) {
4672 ARM_LDR_IMM (code, dreg, dreg, val);
4674 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4676 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4678 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4679 g_assert (!(val & 0xFF000000));
4681 ARM_LDR_IMM (code, dreg, dreg, 0);
4683 /* What is faster, a branch or a load ? */
4684 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4685 /* The breakpoint instruction */
4686 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4689 * A placeholder for a possible breakpoint inserted by
4690 * mono_arch_set_breakpoint ().
4692 for (i = 0; i < 4; ++i)
4697 * Add an additional nop so skipping the bp doesn't cause the ip to point
4698 * to another IL offset.
4706 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4709 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4713 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4716 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4717 g_assert (imm8 >= 0);
4718 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4722 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4723 g_assert (imm8 >= 0);
4724 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4728 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4729 g_assert (imm8 >= 0);
4730 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4733 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4734 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4736 case OP_IADD_OVF_UN:
4737 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4738 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4741 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4742 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4744 case OP_ISUB_OVF_UN:
4745 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4746 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4748 case OP_ADD_OVF_CARRY:
4749 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4750 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4752 case OP_ADD_OVF_UN_CARRY:
4753 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4754 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4756 case OP_SUB_OVF_CARRY:
4757 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4758 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4760 case OP_SUB_OVF_UN_CARRY:
4761 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4762 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4766 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4769 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4770 g_assert (imm8 >= 0);
4771 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4774 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4778 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4782 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4783 g_assert (imm8 >= 0);
4784 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4788 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4789 g_assert (imm8 >= 0);
4790 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4792 case OP_ARM_RSBS_IMM:
4793 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4794 g_assert (imm8 >= 0);
4795 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4797 case OP_ARM_RSC_IMM:
4798 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4799 g_assert (imm8 >= 0);
4800 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4803 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4807 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4808 g_assert (imm8 >= 0);
4809 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4812 g_assert (v7s_supported || v7k_supported);
4813 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4816 g_assert (v7s_supported || v7k_supported);
4817 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4820 g_assert (v7s_supported || v7k_supported);
4821 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4822 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4825 g_assert (v7s_supported || v7k_supported);
4826 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4827 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4831 g_assert_not_reached ();
4833 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4837 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4838 g_assert (imm8 >= 0);
4839 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4842 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4846 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4847 g_assert (imm8 >= 0);
4848 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4851 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4856 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4857 else if (ins->dreg != ins->sreg1)
4858 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4861 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4866 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4867 else if (ins->dreg != ins->sreg1)
4868 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4871 case OP_ISHR_UN_IMM:
4873 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4874 else if (ins->dreg != ins->sreg1)
4875 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4878 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4881 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4884 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4887 if (ins->dreg == ins->sreg2)
4888 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4890 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4893 g_assert_not_reached ();
4896 /* FIXME: handle ovf/ sreg2 != dreg */
4897 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4898 /* FIXME: MUL doesn't set the C/O flags on ARM */
4900 case OP_IMUL_OVF_UN:
4901 /* FIXME: handle ovf/ sreg2 != dreg */
4902 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4903 /* FIXME: MUL doesn't set the C/O flags on ARM */
4906 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4909 /* Load the GOT offset */
4910 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4911 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4913 *(gpointer*)code = NULL;
4915 /* Load the value from the GOT */
4916 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4918 case OP_OBJC_GET_SELECTOR:
4919 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4920 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4922 *(gpointer*)code = NULL;
4924 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4926 case OP_ICONV_TO_I4:
4927 case OP_ICONV_TO_U4:
4929 if (ins->dreg != ins->sreg1)
4930 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4933 int saved = ins->sreg2;
4934 if (ins->sreg2 == ARM_LSW_REG) {
4935 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4938 if (ins->sreg1 != ARM_LSW_REG)
4939 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4940 if (saved != ARM_MSW_REG)
4941 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4945 if (IS_VFP && ins->dreg != ins->sreg1)
4946 ARM_CPYD (code, ins->dreg, ins->sreg1);
4949 if (IS_VFP && ins->dreg != ins->sreg1)
4950 ARM_CPYS (code, ins->dreg, ins->sreg1);
4952 case OP_MOVE_F_TO_I4:
4954 ARM_FMRS (code, ins->dreg, ins->sreg1);
4956 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4957 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4958 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4959 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4962 case OP_MOVE_I4_TO_F:
4964 ARM_FMSR (code, ins->dreg, ins->sreg1);
4966 ARM_FMSR (code, ins->dreg, ins->sreg1);
4967 ARM_CVTS (code, ins->dreg, ins->dreg);
4970 case OP_FCONV_TO_R4:
4973 ARM_CVTD (code, ins->dreg, ins->sreg1);
4975 ARM_CVTD (code, ins->dreg, ins->sreg1);
4976 ARM_CVTS (code, ins->dreg, ins->dreg);
4981 MonoCallInst *call = (MonoCallInst*)ins;
4984 * The stack looks like the following:
4985 * <caller argument area>
4988 * <callee argument area>
4989 * Need to copy the arguments from the callee argument area to
4990 * the caller argument area, and pop the frame.
4992 if (call->stack_usage) {
4993 int i, prev_sp_offset = 0;
4995 /* Compute size of saved registers restored below */
4997 prev_sp_offset = 2 * 4;
4999 prev_sp_offset = 1 * 4;
5000 for (i = 0; i < 16; ++i) {
5001 if (cfg->used_int_regs & (1 << i))
5002 prev_sp_offset += 4;
5005 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5007 /* Copy arguments on the stack to our argument area */
5008 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5009 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5010 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5015 * Keep in sync with mono_arch_emit_epilog
5017 g_assert (!cfg->method->save_lmf);
5019 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5021 if (cfg->used_int_regs)
5022 ARM_POP (code, cfg->used_int_regs);
5023 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5025 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5028 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5029 if (cfg->compile_aot) {
5030 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5032 *(gpointer*)code = NULL;
5034 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5036 code = mono_arm_patchable_b (code, ARMCOND_AL);
5037 cfg->thunk_area += THUNK_SIZE;
5042 /* ensure ins->sreg1 is not NULL */
5043 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5046 g_assert (cfg->sig_cookie < 128);
5047 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5048 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5058 call = (MonoCallInst*)ins;
5061 code = emit_float_args (cfg, call, code, &max_len, &offset);
5063 if (ins->flags & MONO_INST_HAS_METHOD)
5064 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5066 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5067 code = emit_call_seq (cfg, code);
5068 ins->flags |= MONO_INST_GC_CALLSITE;
5069 ins->backend.pc_offset = code - cfg->native_code;
5070 code = emit_move_return_value (cfg, ins, code);
5077 case OP_VOIDCALL_REG:
5080 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5082 code = emit_call_reg (code, ins->sreg1);
5083 ins->flags |= MONO_INST_GC_CALLSITE;
5084 ins->backend.pc_offset = code - cfg->native_code;
5085 code = emit_move_return_value (cfg, ins, code);
5087 case OP_FCALL_MEMBASE:
5088 case OP_RCALL_MEMBASE:
5089 case OP_LCALL_MEMBASE:
5090 case OP_VCALL_MEMBASE:
5091 case OP_VCALL2_MEMBASE:
5092 case OP_VOIDCALL_MEMBASE:
5093 case OP_CALL_MEMBASE: {
5094 g_assert (ins->sreg1 != ARMREG_LR);
5095 call = (MonoCallInst*)ins;
5098 code = emit_float_args (cfg, call, code, &max_len, &offset);
5099 if (!arm_is_imm12 (ins->inst_offset))
5100 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5101 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5102 if (!arm_is_imm12 (ins->inst_offset))
5103 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5105 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5106 ins->flags |= MONO_INST_GC_CALLSITE;
5107 ins->backend.pc_offset = code - cfg->native_code;
5108 code = emit_move_return_value (cfg, ins, code);
5111 case OP_GENERIC_CLASS_INIT: {
5112 static int byte_offset = -1;
5113 static guint8 bitmask;
5117 if (byte_offset < 0)
5118 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5120 g_assert (arm_is_imm8 (byte_offset));
5121 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5122 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5123 g_assert (imm8 >= 0);
5124 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5125 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5127 ARM_B_COND (code, ARMCOND_NE, 0);
5129 /* Uninitialized case */
5130 g_assert (ins->sreg1 == ARMREG_R0);
5132 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5133 (gpointer)"mono_generic_class_init");
5134 code = emit_call_seq (cfg, code);
5136 /* Initialized case */
5137 arm_patch (jump, code);
5141 /* round the size to 8 bytes */
5142 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5143 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5144 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5145 /* memzero the area: dreg holds the size, sp is the pointer */
5146 if (ins->flags & MONO_INST_INIT) {
5147 guint8 *start_loop, *branch_to_cond;
5148 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5149 branch_to_cond = code;
5152 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5153 arm_patch (branch_to_cond, code);
5154 /* decrement by 4 and set flags */
5155 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5156 ARM_B_COND (code, ARMCOND_GE, 0);
5157 arm_patch (code - 4, start_loop);
5159 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5160 if (cfg->param_area)
5161 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5166 MonoInst *var = cfg->dyn_call_var;
5168 g_assert (var->opcode == OP_REGOFFSET);
5169 g_assert (arm_is_imm12 (var->inst_offset));
5171 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5172 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5174 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5176 /* Save args buffer */
5177 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5179 /* Set stack slots using R0 as scratch reg */
5180 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5181 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5182 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5183 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5186 /* Set argument registers */
5187 for (i = 0; i < PARAM_REGS; ++i)
5188 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5191 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5192 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5195 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5196 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5197 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5201 if (ins->sreg1 != ARMREG_R0)
5202 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5203 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5204 (gpointer)"mono_arch_throw_exception");
5205 code = emit_call_seq (cfg, code);
5209 if (ins->sreg1 != ARMREG_R0)
5210 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5211 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5212 (gpointer)"mono_arch_rethrow_exception");
5213 code = emit_call_seq (cfg, code);
5216 case OP_START_HANDLER: {
5217 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5218 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5221 /* Reserve a param area, see filter-stack.exe */
5223 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5224 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5226 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5227 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5231 if (arm_is_imm12 (spvar->inst_offset)) {
5232 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5234 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5235 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5239 case OP_ENDFILTER: {
5240 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5241 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5244 /* Free the param area */
5246 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5247 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5249 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5250 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5254 if (ins->sreg1 != ARMREG_R0)
5255 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5256 if (arm_is_imm12 (spvar->inst_offset)) {
5257 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5259 g_assert (ARMREG_IP != spvar->inst_basereg);
5260 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5261 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5263 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5266 case OP_ENDFINALLY: {
5267 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5268 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5271 /* Free the param area */
5273 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5274 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5276 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5277 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5281 if (arm_is_imm12 (spvar->inst_offset)) {
5282 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5284 g_assert (ARMREG_IP != spvar->inst_basereg);
5285 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5286 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5288 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5291 case OP_CALL_HANDLER:
5292 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5293 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5294 cfg->thunk_area += THUNK_SIZE;
5295 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5298 if (ins->dreg != ARMREG_R0)
5299 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5303 ins->inst_c0 = code - cfg->native_code;
5306 /*if (ins->inst_target_bb->native_offset) {
5308 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5310 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5311 code = mono_arm_patchable_b (code, ARMCOND_AL);
5315 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5319 * In the normal case we have:
5320 * ldr pc, [pc, ins->sreg1 << 2]
5323 * ldr lr, [pc, ins->sreg1 << 2]
5325 * After follows the data.
5326 * FIXME: add aot support.
5328 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5329 #ifdef USE_JUMP_TABLES
5331 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5332 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5333 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5337 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5338 if (offset + max_len > (cfg->code_size - 16)) {
5339 cfg->code_size += max_len;
5340 cfg->code_size *= 2;
5341 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5342 code = cfg->native_code + offset;
5344 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5346 code += 4 * GPOINTER_TO_INT (ins->klass);
5351 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5352 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5356 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5357 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5361 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5362 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5366 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5367 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5371 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5372 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5375 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5376 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5379 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5380 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5383 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5384 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5387 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5388 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5391 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5392 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5394 case OP_COND_EXC_EQ:
5395 case OP_COND_EXC_NE_UN:
5396 case OP_COND_EXC_LT:
5397 case OP_COND_EXC_LT_UN:
5398 case OP_COND_EXC_GT:
5399 case OP_COND_EXC_GT_UN:
5400 case OP_COND_EXC_GE:
5401 case OP_COND_EXC_GE_UN:
5402 case OP_COND_EXC_LE:
5403 case OP_COND_EXC_LE_UN:
5404 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5406 case OP_COND_EXC_IEQ:
5407 case OP_COND_EXC_INE_UN:
5408 case OP_COND_EXC_ILT:
5409 case OP_COND_EXC_ILT_UN:
5410 case OP_COND_EXC_IGT:
5411 case OP_COND_EXC_IGT_UN:
5412 case OP_COND_EXC_IGE:
5413 case OP_COND_EXC_IGE_UN:
5414 case OP_COND_EXC_ILE:
5415 case OP_COND_EXC_ILE_UN:
5416 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5419 case OP_COND_EXC_IC:
5420 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5422 case OP_COND_EXC_OV:
5423 case OP_COND_EXC_IOV:
5424 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5426 case OP_COND_EXC_NC:
5427 case OP_COND_EXC_INC:
5428 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5430 case OP_COND_EXC_NO:
5431 case OP_COND_EXC_INO:
5432 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5444 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5447 /* floating point opcodes */
5449 if (cfg->compile_aot) {
5450 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5452 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5454 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5457 /* FIXME: we can optimize the imm load by dealing with part of
5458 * the displacement in LDFD (aligning to 512).
5460 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5461 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5465 if (cfg->compile_aot) {
5466 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5468 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5471 ARM_CVTS (code, ins->dreg, ins->dreg);
5473 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5474 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5476 ARM_CVTS (code, ins->dreg, ins->dreg);
5479 case OP_STORER8_MEMBASE_REG:
5480 /* This is generated by the local regalloc pass which runs after the lowering pass */
5481 if (!arm_is_fpimm8 (ins->inst_offset)) {
5482 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5483 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5484 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5486 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5489 case OP_LOADR8_MEMBASE:
5490 /* This is generated by the local regalloc pass which runs after the lowering pass */
5491 if (!arm_is_fpimm8 (ins->inst_offset)) {
5492 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5493 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5494 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5496 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5499 case OP_STORER4_MEMBASE_REG:
5500 g_assert (arm_is_fpimm8 (ins->inst_offset));
5502 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5504 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5505 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5506 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5507 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5510 case OP_LOADR4_MEMBASE:
5512 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5514 g_assert (arm_is_fpimm8 (ins->inst_offset));
5515 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5516 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5517 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5518 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5521 case OP_ICONV_TO_R_UN: {
5522 g_assert_not_reached ();
5525 case OP_ICONV_TO_R4:
5527 ARM_FMSR (code, ins->dreg, ins->sreg1);
5528 ARM_FSITOS (code, ins->dreg, ins->dreg);
5530 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5531 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5532 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5533 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5534 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5537 case OP_ICONV_TO_R8:
5538 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5539 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5540 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5541 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5545 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5546 if (sig_ret->type == MONO_TYPE_R4) {
5548 g_assert (!IS_HARD_FLOAT);
5549 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5551 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5554 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5558 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5560 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5564 case OP_FCONV_TO_I1:
5565 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5567 case OP_FCONV_TO_U1:
5568 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5570 case OP_FCONV_TO_I2:
5571 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5573 case OP_FCONV_TO_U2:
5574 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5576 case OP_FCONV_TO_I4:
5578 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5580 case OP_FCONV_TO_U4:
5582 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5584 case OP_FCONV_TO_I8:
5585 case OP_FCONV_TO_U8:
5586 g_assert_not_reached ();
5587 /* Implemented as helper calls */
5589 case OP_LCONV_TO_R_UN:
5590 g_assert_not_reached ();
5591 /* Implemented as helper calls */
5593 case OP_LCONV_TO_OVF_I4_2: {
5594 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5596 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5599 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5600 high_bit_not_set = code;
5601 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5603 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5604 valid_negative = code;
5605 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5606 invalid_negative = code;
5607 ARM_B_COND (code, ARMCOND_AL, 0);
5609 arm_patch (high_bit_not_set, code);
5611 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5612 valid_positive = code;
5613 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5615 arm_patch (invalid_negative, code);
5616 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5618 arm_patch (valid_negative, code);
5619 arm_patch (valid_positive, code);
5621 if (ins->dreg != ins->sreg1)
5622 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5626 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5629 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5632 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5635 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5638 ARM_NEGD (code, ins->dreg, ins->sreg1);
5642 g_assert_not_reached ();
5646 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5652 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5657 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5660 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5661 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5665 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5668 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5669 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5673 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5676 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5677 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5678 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5682 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5685 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5686 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5690 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5693 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5694 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5695 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5699 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5702 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5703 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5707 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5710 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5711 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5715 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5718 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5719 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5722 /* ARM FPA flags table:
5723 * N Less than ARMCOND_MI
5724 * Z Equal ARMCOND_EQ
5725 * C Greater Than or Equal ARMCOND_CS
5726 * V Unordered ARMCOND_VS
5729 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5732 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5735 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5738 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5739 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5745 g_assert_not_reached ();
5749 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5751 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5752 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5753 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5757 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5758 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5763 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5764 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5766 #ifdef USE_JUMP_TABLES
5768 gpointer *jte = mono_jumptable_add_entries (2);
5769 jte [0] = GUINT_TO_POINTER (0xffffffff);
5770 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5771 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5772 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5775 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5776 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5778 *(guint32*)code = 0xffffffff;
5780 *(guint32*)code = 0x7fefffff;
5783 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5785 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5786 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5788 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5789 ARM_CPYD (code, ins->dreg, ins->sreg1);
5791 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5792 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5797 case OP_RCONV_TO_I1:
5798 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5800 case OP_RCONV_TO_U1:
5801 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5803 case OP_RCONV_TO_I2:
5804 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5806 case OP_RCONV_TO_U2:
5807 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5809 case OP_RCONV_TO_I4:
5810 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5812 case OP_RCONV_TO_U4:
5813 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5815 case OP_RCONV_TO_R4:
5817 if (ins->dreg != ins->sreg1)
5818 ARM_CPYS (code, ins->dreg, ins->sreg1);
5820 case OP_RCONV_TO_R8:
5822 ARM_CVTS (code, ins->dreg, ins->sreg1);
5825 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5828 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5831 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5834 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5837 ARM_NEGS (code, ins->dreg, ins->sreg1);
5841 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5844 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5845 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5849 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5852 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5853 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5857 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5860 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5861 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5862 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5866 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5869 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5870 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5874 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5877 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5878 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5879 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5883 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5886 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5887 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5891 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5894 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5895 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5899 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5902 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5903 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5906 case OP_GC_LIVENESS_DEF:
5907 case OP_GC_LIVENESS_USE:
5908 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5909 ins->backend.pc_offset = code - cfg->native_code;
5911 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5912 ins->backend.pc_offset = code - cfg->native_code;
5913 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5915 case OP_GC_SAFE_POINT: {
5916 const char *polling_func = NULL;
5919 g_assert (mono_threads_is_coop_enabled ());
5921 polling_func = "mono_threads_state_poll";
5922 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5923 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5925 ARM_B_COND (code, ARMCOND_EQ, 0);
5926 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5927 code = emit_call_seq (cfg, code);
5928 arm_patch (buf [0], code);
5933 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5934 g_assert_not_reached ();
5937 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5938 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5939 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5940 g_assert_not_reached ();
5946 last_offset = offset;
5949 cfg->code_len = code - cfg->native_code;
5952 #endif /* DISABLE_JIT */
5955 mono_arch_register_lowlevel_calls (void)
5957 /* The signature doesn't matter */
5958 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5959 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5960 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5962 #ifndef MONO_CROSS_COMPILE
5963 if (mono_arm_have_tls_get ()) {
5964 MonoTlsImplementation tls_imp = mono_arm_get_tls_implementation ();
5966 mono_register_jit_icall (tls_imp.get_tls_thunk, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
5967 mono_register_jit_icall (tls_imp.set_tls_thunk, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
5969 if (tls_imp.get_tls_thunk_end) {
5970 mono_tramp_info_register (
5971 mono_tramp_info_create (
5973 (guint8*)tls_imp.get_tls_thunk,
5974 (guint8*)tls_imp.get_tls_thunk_end - (guint8*)tls_imp.get_tls_thunk,
5976 mono_arch_get_cie_program ()
5980 mono_tramp_info_register (
5981 mono_tramp_info_create (
5983 (guint8*)tls_imp.set_tls_thunk,
5984 (guint8*)tls_imp.set_tls_thunk_end - (guint8*)tls_imp.set_tls_thunk,
5986 mono_arch_get_cie_program ()
5995 #define patch_lis_ori(ip,val) do {\
5996 guint16 *__lis_ori = (guint16*)(ip); \
5997 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5998 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
6002 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6004 unsigned char *ip = ji->ip.i + code;
6006 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6010 case MONO_PATCH_INFO_SWITCH: {
6011 #ifdef USE_JUMP_TABLES
6012 gpointer *jt = mono_jumptable_get_entry (ip);
6014 gpointer *jt = (gpointer*)(ip + 8);
6017 /* jt is the inlined jump table, 2 instructions after ip
6018 * In the normal case we store the absolute addresses,
6019 * otherwise the displacements.
6021 for (i = 0; i < ji->data.table->table_size; i++)
6022 jt [i] = code + (int)ji->data.table->table [i];
6025 case MONO_PATCH_INFO_IP:
6026 g_assert_not_reached ();
6027 patch_lis_ori (ip, ip);
6029 case MONO_PATCH_INFO_METHOD_REL:
6030 g_assert_not_reached ();
6031 *((gpointer *)(ip)) = target;
6033 case MONO_PATCH_INFO_METHODCONST:
6034 case MONO_PATCH_INFO_CLASS:
6035 case MONO_PATCH_INFO_IMAGE:
6036 case MONO_PATCH_INFO_FIELD:
6037 case MONO_PATCH_INFO_VTABLE:
6038 case MONO_PATCH_INFO_IID:
6039 case MONO_PATCH_INFO_SFLDA:
6040 case MONO_PATCH_INFO_LDSTR:
6041 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6042 case MONO_PATCH_INFO_LDTOKEN:
6043 g_assert_not_reached ();
6044 /* from OP_AOTCONST : lis + ori */
6045 patch_lis_ori (ip, target);
6047 case MONO_PATCH_INFO_R4:
6048 case MONO_PATCH_INFO_R8:
6049 g_assert_not_reached ();
6050 *((gconstpointer *)(ip + 2)) = target;
6052 case MONO_PATCH_INFO_EXC_NAME:
6053 g_assert_not_reached ();
6054 *((gconstpointer *)(ip + 1)) = target;
6056 case MONO_PATCH_INFO_NONE:
6057 case MONO_PATCH_INFO_BB_OVF:
6058 case MONO_PATCH_INFO_EXC_OVF:
6059 /* everything is dealt with at epilog output time */
6062 arm_patch_general (cfg, domain, ip, target);
6068 mono_arm_unaligned_stack (MonoMethod *method)
6070 g_assert_not_reached ();
6076 * Stack frame layout:
6078 * ------------------- fp
6079 * MonoLMF structure or saved registers
6080 * -------------------
6082 * -------------------
6084 * -------------------
6085 * optional 8 bytes for tracing
6086 * -------------------
6087 * param area size is cfg->param_area
6088 * ------------------- sp
6091 mono_arch_emit_prolog (MonoCompile *cfg)
6093 MonoMethod *method = cfg->method;
6095 MonoMethodSignature *sig;
6097 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6102 int prev_sp_offset, reg_offset;
6104 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6107 sig = mono_method_signature (method);
6108 cfg->code_size = 256 + sig->param_count * 64;
6109 code = cfg->native_code = g_malloc (cfg->code_size);
6111 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6113 alloc_size = cfg->stack_offset;
6119 * The iphone uses R7 as the frame pointer, and it points at the saved
6124 * We can't use r7 as a frame pointer since it points into the middle of
6125 * the frame, so we keep using our own frame pointer.
6126 * FIXME: Optimize this.
6128 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6129 prev_sp_offset += 8; /* r7 and lr */
6130 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6131 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6132 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6135 if (!method->save_lmf) {
6137 /* No need to push LR again */
6138 if (cfg->used_int_regs)
6139 ARM_PUSH (code, cfg->used_int_regs);
6141 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6142 prev_sp_offset += 4;
6144 for (i = 0; i < 16; ++i) {
6145 if (cfg->used_int_regs & (1 << i))
6146 prev_sp_offset += 4;
6148 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6150 for (i = 0; i < 16; ++i) {
6151 if ((cfg->used_int_regs & (1 << i))) {
6152 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6153 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6158 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6159 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6161 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6162 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6165 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6166 ARM_PUSH (code, 0x5ff0);
6167 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6168 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6170 for (i = 0; i < 16; ++i) {
6171 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6172 /* The original r7 is saved at the start */
6173 if (!(iphone_abi && i == ARMREG_R7))
6174 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6178 g_assert (reg_offset == 4 * 10);
6179 pos += sizeof (MonoLMF) - (4 * 10);
6183 orig_alloc_size = alloc_size;
6184 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6185 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6186 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6187 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6190 /* the stack used in the pushed regs */
6191 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6192 cfg->stack_usage = alloc_size;
6194 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6195 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6197 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6198 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6200 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6202 if (cfg->frame_reg != ARMREG_SP) {
6203 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6204 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6206 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6207 prev_sp_offset += alloc_size;
6209 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6210 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6212 /* compute max_offset in order to use short forward jumps
6213 * we could skip do it on arm because the immediate displacement
6214 * for jumps is large enough, it may be useful later for constant pools
6217 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6218 MonoInst *ins = bb->code;
6219 bb->max_offset = max_offset;
6221 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6224 MONO_BB_FOR_EACH_INS (bb, ins)
6225 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6228 /* stack alignment check */
6232 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6233 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6234 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6235 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6237 ARM_B_COND (code, ARMCOND_EQ, 0);
6238 if (cfg->compile_aot)
6239 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6241 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6242 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6243 code = emit_call_seq (cfg, code);
6244 arm_patch (buf [0], code);
6248 /* store runtime generic context */
6249 if (cfg->rgctx_var) {
6250 MonoInst *ins = cfg->rgctx_var;
6252 g_assert (ins->opcode == OP_REGOFFSET);
6254 if (arm_is_imm12 (ins->inst_offset)) {
6255 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6257 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6258 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6262 /* load arguments allocated to register from the stack */
6265 cinfo = get_call_info (NULL, sig);
6267 if (cinfo->ret.storage == RegTypeStructByAddr) {
6268 ArgInfo *ainfo = &cinfo->ret;
6269 inst = cfg->vret_addr;
6270 g_assert (arm_is_imm12 (inst->inst_offset));
6271 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6274 if (sig->call_convention == MONO_CALL_VARARG) {
6275 ArgInfo *cookie = &cinfo->sig_cookie;
6277 /* Save the sig cookie address */
6278 g_assert (cookie->storage == RegTypeBase);
6280 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6281 g_assert (arm_is_imm12 (cfg->sig_cookie));
6282 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6283 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6286 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6287 ArgInfo *ainfo = cinfo->args + i;
6288 inst = cfg->args [pos];
6290 if (cfg->verbose_level > 2)
6291 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6293 if (inst->opcode == OP_REGVAR) {
6294 if (ainfo->storage == RegTypeGeneral)
6295 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6296 else if (ainfo->storage == RegTypeFP) {
6297 g_assert_not_reached ();
6298 } else if (ainfo->storage == RegTypeBase) {
6299 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6300 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6302 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6303 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6306 g_assert_not_reached ();
6308 if (cfg->verbose_level > 2)
6309 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6311 switch (ainfo->storage) {
6313 for (part = 0; part < ainfo->nregs; part ++) {
6314 if (ainfo->esize == 4)
6315 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6317 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6320 case RegTypeGeneral:
6321 case RegTypeIRegPair:
6322 case RegTypeGSharedVtInReg:
6323 switch (ainfo->size) {
6325 if (arm_is_imm12 (inst->inst_offset))
6326 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6328 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6329 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6333 if (arm_is_imm8 (inst->inst_offset)) {
6334 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6336 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6337 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6341 if (arm_is_imm12 (inst->inst_offset)) {
6342 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6344 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6345 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6347 if (arm_is_imm12 (inst->inst_offset + 4)) {
6348 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6350 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6351 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6355 if (arm_is_imm12 (inst->inst_offset)) {
6356 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6358 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6359 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6364 case RegTypeBaseGen:
6365 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6366 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6368 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6369 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6371 if (arm_is_imm12 (inst->inst_offset + 4)) {
6372 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6373 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6375 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6376 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6377 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6378 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6382 case RegTypeGSharedVtOnStack:
6383 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6384 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6386 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6387 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6390 switch (ainfo->size) {
6392 if (arm_is_imm8 (inst->inst_offset)) {
6393 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6395 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6396 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6400 if (arm_is_imm8 (inst->inst_offset)) {
6401 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6403 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6404 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6408 if (arm_is_imm12 (inst->inst_offset)) {
6409 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6411 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6412 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6414 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6415 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6417 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6418 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6420 if (arm_is_imm12 (inst->inst_offset + 4)) {
6421 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6423 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6424 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6428 if (arm_is_imm12 (inst->inst_offset)) {
6429 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6431 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6432 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6438 int imm8, rot_amount;
6440 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6441 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6442 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6444 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6446 if (ainfo->size == 8)
6447 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6449 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6452 case RegTypeStructByVal: {
6453 int doffset = inst->inst_offset;
6457 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6458 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6459 if (arm_is_imm12 (doffset)) {
6460 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6462 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6463 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6465 soffset += sizeof (gpointer);
6466 doffset += sizeof (gpointer);
6468 if (ainfo->vtsize) {
6469 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6470 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6471 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6475 case RegTypeStructByAddr:
6476 g_assert_not_reached ();
6477 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6478 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6480 g_assert_not_reached ();
6487 if (method->save_lmf)
6488 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6491 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6493 if (cfg->arch.seq_point_info_var) {
6494 MonoInst *ins = cfg->arch.seq_point_info_var;
6496 /* Initialize the variable from a GOT slot */
6497 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6498 #ifdef USE_JUMP_TABLES
6500 gpointer *jte = mono_jumptable_add_entry ();
6501 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6502 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6504 /** XXX: is it correct? */
6506 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6508 *(gpointer*)code = NULL;
6511 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6513 g_assert (ins->opcode == OP_REGOFFSET);
6515 if (arm_is_imm12 (ins->inst_offset)) {
6516 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6518 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6519 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6523 /* Initialize ss_trigger_page_var */
6524 if (!cfg->soft_breakpoints) {
6525 MonoInst *info_var = cfg->arch.seq_point_info_var;
6526 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6527 int dreg = ARMREG_LR;
6530 g_assert (info_var->opcode == OP_REGOFFSET);
6531 g_assert (arm_is_imm12 (info_var->inst_offset));
6533 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6534 /* Load the trigger page addr */
6535 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6536 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6540 if (cfg->arch.seq_point_ss_method_var) {
6541 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6542 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6543 #ifdef USE_JUMP_TABLES
6546 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6547 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6548 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6549 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6551 #ifdef USE_JUMP_TABLES
6552 jte = mono_jumptable_add_entries (3);
6553 jte [0] = &single_step_tramp;
6554 jte [1] = breakpoint_tramp;
6555 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6557 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6559 *(gpointer*)code = &single_step_tramp;
6561 *(gpointer*)code = breakpoint_tramp;
6565 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6566 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6567 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6568 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6571 cfg->code_len = code - cfg->native_code;
6572 g_assert (cfg->code_len < cfg->code_size);
6579 mono_arch_emit_epilog (MonoCompile *cfg)
6581 MonoMethod *method = cfg->method;
6582 int pos, i, rot_amount;
6583 int max_epilog_size = 16 + 20*4;
6587 if (cfg->method->save_lmf)
6588 max_epilog_size += 128;
6590 if (mono_jit_trace_calls != NULL)
6591 max_epilog_size += 50;
6593 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6594 max_epilog_size += 50;
6596 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6597 cfg->code_size *= 2;
6598 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6599 cfg->stat_code_reallocs++;
6603 * Keep in sync with OP_JMP
6605 code = cfg->native_code + cfg->code_len;
6607 /* Save the uwind state which is needed by the out-of-line code */
6608 mono_emit_unwind_op_remember_state (cfg, code);
6610 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6611 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6615 /* Load returned vtypes into registers if needed */
6616 cinfo = cfg->arch.cinfo;
6617 switch (cinfo->ret.storage) {
6618 case RegTypeStructByVal: {
6619 MonoInst *ins = cfg->ret;
6621 if (arm_is_imm12 (ins->inst_offset)) {
6622 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6624 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6625 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6630 MonoInst *ins = cfg->ret;
6632 for (i = 0; i < cinfo->ret.nregs; ++i) {
6633 if (cinfo->ret.esize == 4)
6634 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6636 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6644 if (method->save_lmf) {
6645 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6646 /* all but r0-r3, sp and pc */
6647 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6650 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6652 /* This points to r4 inside MonoLMF->iregs */
6653 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6655 regmask = 0x9ff0; /* restore lr to pc */
6656 /* Skip caller saved registers not used by the method */
6657 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6658 regmask &= ~(1 << reg);
6663 /* Restored later */
6664 regmask &= ~(1 << ARMREG_PC);
6665 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6666 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6667 for (i = 0; i < 16; i++) {
6668 if (regmask & (1 << i))
6671 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6673 ARM_POP (code, regmask);
6675 for (i = 0; i < 16; i++) {
6676 if (regmask & (1 << i))
6677 mono_emit_unwind_op_same_value (cfg, code, i);
6679 /* Restore saved r7, restore LR to PC */
6680 /* Skip lr from the lmf */
6681 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6682 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6683 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6684 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6687 int i, nused_int_regs = 0;
6689 for (i = 0; i < 16; i++) {
6690 if (cfg->used_int_regs & (1 << i))
6694 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6695 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6697 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6698 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6701 if (cfg->frame_reg != ARMREG_SP) {
6702 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6706 /* Restore saved gregs */
6707 if (cfg->used_int_regs) {
6708 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6709 ARM_POP (code, cfg->used_int_regs);
6710 for (i = 0; i < 16; i++) {
6711 if (cfg->used_int_regs & (1 << i))
6712 mono_emit_unwind_op_same_value (cfg, code, i);
6715 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6716 /* Restore saved r7, restore LR to PC */
6717 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6719 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6720 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6724 /* Restore the unwind state to be the same as before the epilog */
6725 mono_emit_unwind_op_restore_state (cfg, code);
6727 cfg->code_len = code - cfg->native_code;
6729 g_assert (cfg->code_len < cfg->code_size);
6734 mono_arch_emit_exceptions (MonoCompile *cfg)
6736 MonoJumpInfo *patch_info;
6739 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6740 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6741 int max_epilog_size = 50;
6743 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6744 exc_throw_pos [i] = NULL;
6745 exc_throw_found [i] = 0;
6748 /* count the number of exception infos */
6751 * make sure we have enough space for exceptions
6753 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6754 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6755 i = mini_exception_id_by_name (patch_info->data.target);
6756 if (!exc_throw_found [i]) {
6757 max_epilog_size += 32;
6758 exc_throw_found [i] = TRUE;
6763 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6764 cfg->code_size *= 2;
6765 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6766 cfg->stat_code_reallocs++;
6769 code = cfg->native_code + cfg->code_len;
6771 /* add code to raise exceptions */
6772 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6773 switch (patch_info->type) {
6774 case MONO_PATCH_INFO_EXC: {
6775 MonoClass *exc_class;
6776 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6778 i = mini_exception_id_by_name (patch_info->data.target);
6779 if (exc_throw_pos [i]) {
6780 arm_patch (ip, exc_throw_pos [i]);
6781 patch_info->type = MONO_PATCH_INFO_NONE;
6784 exc_throw_pos [i] = code;
6786 arm_patch (ip, code);
6788 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6789 g_assert (exc_class);
6791 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6792 #ifdef USE_JUMP_TABLES
6794 gpointer *jte = mono_jumptable_add_entries (2);
6795 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6796 patch_info->data.name = "mono_arch_throw_corlib_exception";
6797 patch_info->ip.i = code - cfg->native_code;
6798 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6799 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6800 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6801 ARM_BLX_REG (code, ARMREG_IP);
6802 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6805 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6806 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6807 patch_info->data.name = "mono_arch_throw_corlib_exception";
6808 patch_info->ip.i = code - cfg->native_code;
6810 cfg->thunk_area += THUNK_SIZE;
6811 *(guint32*)(gpointer)code = exc_class->type_token;
6822 cfg->code_len = code - cfg->native_code;
6824 g_assert (cfg->code_len < cfg->code_size);
6828 #endif /* #ifndef DISABLE_JIT */
6831 mono_arch_finish_init (void)
6836 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6841 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6848 mono_arch_print_tree (MonoInst *tree, int arity)
6858 mono_arch_get_patch_offset (guint8 *code)
6865 mono_arch_flush_register_windows (void)
6870 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6872 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6876 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6878 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6882 mono_arch_get_cie_program (void)
6886 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6891 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6892 #define BASE_SIZE (6 * 4)
6893 #define BSEARCH_ENTRY_SIZE (4 * 4)
6894 #define CMP_SIZE (3 * 4)
6895 #define BRANCH_SIZE (1 * 4)
6896 #define CALL_SIZE (2 * 4)
6897 #define WMC_SIZE (8 * 4)
6898 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6900 #ifdef USE_JUMP_TABLES
6902 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6904 g_assert (base [index] == NULL);
6905 base [index] = value;
6908 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6910 if (arm_is_imm12 (jti * 4)) {
6911 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6913 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6914 if ((jti * 4) >> 16)
6915 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6916 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6922 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6924 guint32 delta = DISTANCE (target, code);
6926 g_assert (delta >= 0 && delta <= 0xFFF);
6927 *target = *target | delta;
6933 #ifdef ENABLE_WRONG_METHOD_CHECK
6935 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6937 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6943 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6944 gpointer fail_tramp)
6947 arminstr_t *code, *start;
6948 #ifdef USE_JUMP_TABLES
6951 gboolean large_offsets = FALSE;
6952 guint32 **constant_pool_starts;
6953 arminstr_t *vtable_target = NULL;
6954 int extra_space = 0;
6956 #ifdef ENABLE_WRONG_METHOD_CHECK
6962 #ifdef USE_JUMP_TABLES
6963 for (i = 0; i < count; ++i) {
6964 MonoIMTCheckItem *item = imt_entries [i];
6965 item->chunk_size += 4 * 16;
6966 if (!item->is_equals)
6967 imt_entries [item->check_target_idx]->compare_done = TRUE;
6968 size += item->chunk_size;
6971 constant_pool_starts = g_new0 (guint32*, count);
6973 for (i = 0; i < count; ++i) {
6974 MonoIMTCheckItem *item = imt_entries [i];
6975 if (item->is_equals) {
6976 gboolean fail_case = !item->check_target_idx && fail_tramp;
6978 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6979 item->chunk_size += 32;
6980 large_offsets = TRUE;
6983 if (item->check_target_idx || fail_case) {
6984 if (!item->compare_done || fail_case)
6985 item->chunk_size += CMP_SIZE;
6986 item->chunk_size += BRANCH_SIZE;
6988 #ifdef ENABLE_WRONG_METHOD_CHECK
6989 item->chunk_size += WMC_SIZE;
6993 item->chunk_size += 16;
6994 large_offsets = TRUE;
6996 item->chunk_size += CALL_SIZE;
6998 item->chunk_size += BSEARCH_ENTRY_SIZE;
6999 imt_entries [item->check_target_idx]->compare_done = TRUE;
7001 size += item->chunk_size;
7005 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
7009 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7011 code = mono_domain_code_reserve (domain, size);
7014 unwind_ops = mono_arch_get_cie_program ();
7017 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
7018 for (i = 0; i < count; ++i) {
7019 MonoIMTCheckItem *item = imt_entries [i];
7020 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
7024 #ifdef USE_JUMP_TABLES
7025 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7026 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 3 * sizeof (mgreg_t));
7027 #define VTABLE_JTI 0
7028 #define IMT_METHOD_OFFSET 0
7029 #define TARGET_CODE_OFFSET 1
7030 #define JUMP_CODE_OFFSET 2
7031 #define RECORDS_PER_ENTRY 3
7032 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
7033 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
7034 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
7036 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
7037 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
7038 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
7039 set_jumptable_element (jte, VTABLE_JTI, vtable);
7041 if (large_offsets) {
7042 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7043 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
7045 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7046 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7048 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7049 vtable_target = code;
7050 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7052 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7054 for (i = 0; i < count; ++i) {
7055 MonoIMTCheckItem *item = imt_entries [i];
7056 #ifdef USE_JUMP_TABLES
7057 guint32 imt_method_jti = 0, target_code_jti = 0;
7059 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7061 gint32 vtable_offset;
7063 item->code_target = (guint8*)code;
7065 if (item->is_equals) {
7066 gboolean fail_case = !item->check_target_idx && fail_tramp;
7068 if (item->check_target_idx || fail_case) {
7069 if (!item->compare_done || fail_case) {
7070 #ifdef USE_JUMP_TABLES
7071 imt_method_jti = IMT_METHOD_JTI (i);
7072 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7075 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7077 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7079 #ifdef USE_JUMP_TABLES
7080 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7081 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7082 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7084 item->jmp_code = (guint8*)code;
7085 ARM_B_COND (code, ARMCOND_NE, 0);
7088 /*Enable the commented code to assert on wrong method*/
7089 #ifdef ENABLE_WRONG_METHOD_CHECK
7090 #ifdef USE_JUMP_TABLES
7091 imt_method_jti = IMT_METHOD_JTI (i);
7092 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7095 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7097 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7099 ARM_B_COND (code, ARMCOND_EQ, 0);
7101 /* Define this if your system is so bad that gdb is failing. */
7102 #ifdef BROKEN_DEV_ENV
7103 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7105 arm_patch (code - 1, mini_dump_bad_imt);
7109 arm_patch (cond, code);
7113 if (item->has_target_code) {
7114 /* Load target address */
7115 #ifdef USE_JUMP_TABLES
7116 target_code_jti = TARGET_CODE_JTI (i);
7117 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7118 /* Restore registers */
7119 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7120 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7122 ARM_BX (code, ARMREG_R1);
7123 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7125 target_code_ins = code;
7126 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7127 /* Save it to the fourth slot */
7128 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7129 /* Restore registers and branch */
7130 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7132 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7135 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7136 if (!arm_is_imm12 (vtable_offset)) {
7138 * We need to branch to a computed address but we don't have
7139 * a free register to store it, since IP must contain the
7140 * vtable address. So we push the two values to the stack, and
7141 * load them both using LDM.
7143 /* Compute target address */
7144 #ifdef USE_JUMP_TABLES
7145 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7146 if (vtable_offset >> 16)
7147 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7148 /* IP had vtable base. */
7149 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7150 /* Restore registers and branch */
7151 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7152 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7153 ARM_BX (code, ARMREG_IP);
7155 vtable_offset_ins = code;
7156 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7157 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7158 /* Save it to the fourth slot */
7159 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7160 /* Restore registers and branch */
7161 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7163 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7166 #ifdef USE_JUMP_TABLES
7167 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7168 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7169 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7170 ARM_BX (code, ARMREG_IP);
7172 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7173 if (large_offsets) {
7174 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7175 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7177 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7178 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7184 #ifdef USE_JUMP_TABLES
7185 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7186 target_code_jti = TARGET_CODE_JTI (i);
7187 /* Load target address */
7188 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7189 /* Restore registers */
7190 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7191 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7193 ARM_BX (code, ARMREG_R1);
7194 set_jumptable_element (jte, target_code_jti, fail_tramp);
7196 arm_patch (item->jmp_code, (guchar*)code);
7198 target_code_ins = code;
7199 /* Load target address */
7200 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7201 /* Save it to the fourth slot */
7202 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7203 /* Restore registers and branch */
7204 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7206 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7208 item->jmp_code = NULL;
7211 #ifdef USE_JUMP_TABLES
7213 set_jumptable_element (jte, imt_method_jti, item->key);
7216 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7218 /*must emit after unconditional branch*/
7219 if (vtable_target) {
7220 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7221 item->chunk_size += 4;
7222 vtable_target = NULL;
7225 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7226 constant_pool_starts [i] = code;
7228 code += extra_space;
7233 #ifdef USE_JUMP_TABLES
7234 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7235 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7236 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7237 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7238 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7240 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7241 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7243 item->jmp_code = (guint8*)code;
7244 ARM_B_COND (code, ARMCOND_HS, 0);
7250 for (i = 0; i < count; ++i) {
7251 MonoIMTCheckItem *item = imt_entries [i];
7252 if (item->jmp_code) {
7253 if (item->check_target_idx)
7254 #ifdef USE_JUMP_TABLES
7255 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7257 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7260 if (i > 0 && item->is_equals) {
7262 #ifdef USE_JUMP_TABLES
7263 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7264 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7266 arminstr_t *space_start = constant_pool_starts [i];
7267 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7268 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7276 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7277 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7282 #ifndef USE_JUMP_TABLES
7283 g_free (constant_pool_starts);
7286 mono_arch_flush_icache ((guint8*)start, size);
7287 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7288 mono_stats.imt_thunks_size += code - start;
7290 g_assert (DISTANCE (start, code) <= size);
7292 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7298 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7300 return ctx->regs [reg];
7304 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7306 ctx->regs [reg] = val;
7310 * mono_arch_get_trampolines:
7312 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7316 mono_arch_get_trampolines (gboolean aot)
7318 return mono_arm_get_exception_trampolines (aot);
7322 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7329 bp = MONO_CONTEXT_GET_BP (ctx);
7330 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7332 old_value = *lr_loc;
7333 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7336 *lr_loc = new_value;
7341 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7343 * mono_arch_set_breakpoint:
7345 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7346 * The location should contain code emitted by OP_SEQ_POINT.
7349 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7352 guint32 native_offset = ip - (guint8*)ji->code_start;
7353 MonoDebugOptions *opt = mini_get_debug_options ();
7355 if (opt->soft_breakpoints) {
7356 g_assert (!ji->from_aot);
7358 ARM_BLX_REG (code, ARMREG_LR);
7359 mono_arch_flush_icache (code - 4, 4);
7360 } else if (ji->from_aot) {
7361 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7363 g_assert (native_offset % 4 == 0);
7364 g_assert (info->bp_addrs [native_offset / 4] == 0);
7365 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7367 int dreg = ARMREG_LR;
7369 /* Read from another trigger page */
7370 #ifdef USE_JUMP_TABLES
7371 gpointer *jte = mono_jumptable_add_entry ();
7372 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7373 jte [0] = bp_trigger_page;
7375 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7377 *(int*)code = (int)bp_trigger_page;
7380 ARM_LDR_IMM (code, dreg, dreg, 0);
7382 mono_arch_flush_icache (code - 16, 16);
7385 /* This is currently implemented by emitting an SWI instruction, which
7386 * qemu/linux seems to convert to a SIGILL.
7388 *(int*)code = (0xef << 24) | 8;
7390 mono_arch_flush_icache (code - 4, 4);
7396 * mono_arch_clear_breakpoint:
7398 * Clear the breakpoint at IP.
7401 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7403 MonoDebugOptions *opt = mini_get_debug_options ();
7407 if (opt->soft_breakpoints) {
7408 g_assert (!ji->from_aot);
7411 mono_arch_flush_icache (code - 4, 4);
7412 } else if (ji->from_aot) {
7413 guint32 native_offset = ip - (guint8*)ji->code_start;
7414 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7416 g_assert (native_offset % 4 == 0);
7417 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7418 info->bp_addrs [native_offset / 4] = 0;
7420 for (i = 0; i < 4; ++i)
7423 mono_arch_flush_icache (ip, code - ip);
7428 * mono_arch_start_single_stepping:
7430 * Start single stepping.
7433 mono_arch_start_single_stepping (void)
7435 if (ss_trigger_page)
7436 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7438 single_step_tramp = mini_get_single_step_trampoline ();
7442 * mono_arch_stop_single_stepping:
7444 * Stop single stepping.
7447 mono_arch_stop_single_stepping (void)
7449 if (ss_trigger_page)
7450 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7452 single_step_tramp = NULL;
7456 #define DBG_SIGNAL SIGBUS
7458 #define DBG_SIGNAL SIGSEGV
7462 * mono_arch_is_single_step_event:
7464 * Return whenever the machine state in SIGCTX corresponds to a single
7468 mono_arch_is_single_step_event (void *info, void *sigctx)
7470 siginfo_t *sinfo = info;
7472 if (!ss_trigger_page)
7475 /* Sometimes the address is off by 4 */
7476 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7483 * mono_arch_is_breakpoint_event:
7485 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7488 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7490 siginfo_t *sinfo = info;
7492 if (!ss_trigger_page)
7495 if (sinfo->si_signo == DBG_SIGNAL) {
7496 /* Sometimes the address is off by 4 */
7497 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7507 * mono_arch_skip_breakpoint:
7509 * See mini-amd64.c for docs.
7512 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7514 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7518 * mono_arch_skip_single_step:
7520 * See mini-amd64.c for docs.
7523 mono_arch_skip_single_step (MonoContext *ctx)
7525 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7528 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7531 * mono_arch_get_seq_point_info:
7533 * See mini-amd64.c for docs.
7536 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7541 // FIXME: Add a free function
7543 mono_domain_lock (domain);
7544 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7546 mono_domain_unlock (domain);
7549 ji = mono_jit_info_table_find (domain, (char*)code);
7552 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7554 info->ss_trigger_page = ss_trigger_page;
7555 info->bp_trigger_page = bp_trigger_page;
7557 mono_domain_lock (domain);
7558 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7560 mono_domain_unlock (domain);
7567 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7569 ext->lmf.previous_lmf = prev_lmf;
7570 /* Mark that this is a MonoLMFExt */
7571 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7572 ext->lmf.sp = (gssize)ext;
7576 * mono_arch_set_target:
7578 * Set the target architecture the JIT backend should generate code for, in the form
7579 * of a GNU target triplet. Only used in AOT mode.
7582 mono_arch_set_target (char *mtriple)
7584 /* The GNU target triple format is not very well documented */
7585 if (strstr (mtriple, "armv7")) {
7586 v5_supported = TRUE;
7587 v6_supported = TRUE;
7588 v7_supported = TRUE;
7590 if (strstr (mtriple, "armv6")) {
7591 v5_supported = TRUE;
7592 v6_supported = TRUE;
7594 if (strstr (mtriple, "armv7s")) {
7595 v7s_supported = TRUE;
7597 if (strstr (mtriple, "armv7k")) {
7598 v7k_supported = TRUE;
7600 if (strstr (mtriple, "thumbv7s")) {
7601 v5_supported = TRUE;
7602 v6_supported = TRUE;
7603 v7_supported = TRUE;
7604 v7s_supported = TRUE;
7605 thumb_supported = TRUE;
7606 thumb2_supported = TRUE;
7608 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7609 v5_supported = TRUE;
7610 v6_supported = TRUE;
7611 thumb_supported = TRUE;
7614 if (strstr (mtriple, "gnueabi"))
7615 eabi_supported = TRUE;
7619 mono_arch_opcode_supported (int opcode)
7622 case OP_ATOMIC_ADD_I4:
7623 case OP_ATOMIC_EXCHANGE_I4:
7624 case OP_ATOMIC_CAS_I4:
7625 case OP_ATOMIC_LOAD_I1:
7626 case OP_ATOMIC_LOAD_I2:
7627 case OP_ATOMIC_LOAD_I4:
7628 case OP_ATOMIC_LOAD_U1:
7629 case OP_ATOMIC_LOAD_U2:
7630 case OP_ATOMIC_LOAD_U4:
7631 case OP_ATOMIC_STORE_I1:
7632 case OP_ATOMIC_STORE_I2:
7633 case OP_ATOMIC_STORE_I4:
7634 case OP_ATOMIC_STORE_U1:
7635 case OP_ATOMIC_STORE_U2:
7636 case OP_ATOMIC_STORE_U4:
7637 return v7_supported;
7638 case OP_ATOMIC_LOAD_R4:
7639 case OP_ATOMIC_LOAD_R8:
7640 case OP_ATOMIC_STORE_R4:
7641 case OP_ATOMIC_STORE_R8:
7642 return v7_supported && IS_VFP;
7648 #if defined(ENABLE_GSHAREDVT)
7650 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7652 #endif /* !MONOTOUCH */