2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/appdomain.h>
16 #include <mono/metadata/debug-helpers.h>
17 #include <mono/utils/mono-mmap.h>
23 #include "debugger-agent.h"
25 #include "mono/arch/arm/arm-fpa-codegen.h"
26 #include "mono/arch/arm/arm-vfp-codegen.h"
28 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
29 #define HAVE_AEABI_READ_TP 1
44 #ifdef MONO_ARCH_SOFT_FLOAT
45 #define IS_SOFT_FLOAT 1
47 #define IS_SOFT_FLOAT 0
50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
52 static gint lmf_tls_offset = -1;
53 static gint lmf_addr_tls_offset = -1;
55 /* This mutex protects architecture specific caches */
56 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
57 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
58 static CRITICAL_SECTION mini_arch_mutex;
60 static int v5_supported = 0;
61 static int v6_supported = 0;
62 static int v7_supported = 0;
63 static int thumb_supported = 0;
65 * Whenever to use the ARM EABI
67 static int eabi_supported = 0;
70 * Whenever we are on arm/darwin aka the iphone.
72 static int darwin = 0;
74 * Whenever to use the iphone ABI extensions:
75 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
76 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
77 * This is required for debugging/profiling tools to work, but it has some overhead so it should
78 * only be turned on in debug builds.
80 static int iphone_abi = 0;
83 * The FPU we are generating code for. This is NOT runtime configurable right now,
84 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
86 static MonoArmFPU arm_fpu;
90 static volatile int ss_trigger_var = 0;
92 static gpointer single_step_func_wrapper;
93 static gpointer breakpoint_func_wrapper;
96 * The code generated for sequence points reads from this location, which is
97 * made read-only when single stepping is enabled.
99 static gpointer ss_trigger_page;
101 /* Enabled breakpoints read from this trigger page */
102 static gpointer bp_trigger_page;
104 /* Structure used by the sequence points in AOTed code */
106 gpointer ss_trigger_page;
107 gpointer bp_trigger_page;
108 guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
113 * floating point support: on ARM it is a mess, there are at least 3
114 * different setups, each of which binary incompat with the other.
115 * 1) FPA: old and ugly, but unfortunately what current distros use
116 * the double binary format has the two words swapped. 8 double registers.
117 * Implemented usually by kernel emulation.
118 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
119 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
120 * 3) VFP: the new and actually sensible and useful FP support. Implemented
121 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
123 * The plan is to write the FPA support first. softfloat can be tested in a chroot.
125 int mono_exc_esp_offset = 0;
127 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
128 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
129 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
131 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
132 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
133 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
135 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
136 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) | (ARMREG_LR << 12) | ARMREG_PC)
139 /* A variant of ARM_LDR_IMM which can handle large offsets */
140 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
141 if (arm_is_imm12 ((offset))) { \
142 ARM_LDR_IMM (code, (dreg), (basereg), (offset)); \
144 g_assert ((scratch_reg) != (basereg)); \
145 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
146 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
150 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
151 if (arm_is_imm12 ((offset))) { \
152 ARM_STR_IMM (code, (dreg), (basereg), (offset)); \
154 g_assert ((scratch_reg) != (basereg)); \
155 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
156 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
160 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
163 mono_arch_regname (int reg)
165 static const char * rnames[] = {
166 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
167 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
168 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
171 if (reg >= 0 && reg < 16)
177 mono_arch_fregname (int reg)
179 static const char * rnames[] = {
180 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
181 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
182 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
183 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
184 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
185 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
188 if (reg >= 0 && reg < 32)
196 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
198 int imm8, rot_amount;
199 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
200 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
203 g_assert (dreg != sreg);
204 code = mono_arm_emit_load_imm (code, dreg, imm);
205 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
210 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
212 /* we can use r0-r3, since this is called only for incoming args on the stack */
213 if (size > sizeof (gpointer) * 4) {
215 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
216 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
217 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
218 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
219 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
220 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
221 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
222 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
223 ARM_B_COND (code, ARMCOND_NE, 0);
224 arm_patch (code - 4, start_loop);
227 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
228 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
230 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
231 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
237 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
238 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
239 doffset = soffset = 0;
241 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
242 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
248 g_assert (size == 0);
253 emit_call_reg (guint8 *code, int reg)
256 ARM_BLX_REG (code, reg);
258 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
262 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
268 emit_call_seq (MonoCompile *cfg, guint8 *code)
270 if (cfg->method->dynamic) {
271 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
273 *(gpointer*)code = NULL;
275 code = emit_call_reg (code, ARMREG_IP);
283 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
285 switch (ins->opcode) {
288 case OP_FCALL_MEMBASE:
290 if (ins->dreg != ARM_FPA_F0)
291 ARM_FPA_MVFD (code, ins->dreg, ARM_FPA_F0);
293 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
294 ARM_FMSR (code, ins->dreg, ARMREG_R0);
295 ARM_CVTS (code, ins->dreg, ins->dreg);
297 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
309 * Emit code to push an LMF structure on the LMF stack.
310 * On arm, this is intermixed with the initialization of other fields of the structure.
313 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
315 gboolean get_lmf_fast = FALSE;
318 #ifdef HAVE_AEABI_READ_TP
319 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
321 if (lmf_addr_tls_offset != -1) {
324 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
325 (gpointer)"__aeabi_read_tp");
326 code = emit_call_seq (cfg, code);
328 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
333 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
334 (gpointer)"mono_get_lmf_addr");
335 code = emit_call_seq (cfg, code);
337 /* we build the MonoLMF structure on the stack - see mini-arm.h */
338 /* lmf_offset is the offset from the previous stack pointer,
339 * alloc_size is the total stack space allocated, so the offset
340 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
341 * The pointer to the struct is put in r1 (new_lmf).
342 * ip is used as scratch
343 * The callee-saved registers are already in the MonoLMF structure
345 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
346 /* r0 is the result from mono_get_lmf_addr () */
347 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
348 /* new_lmf->previous_lmf = *lmf_addr */
349 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
350 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
351 /* *(lmf_addr) = r1 */
352 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
353 /* Skip method (only needed for trampoline LMF frames) */
354 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, sp));
355 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, fp));
356 /* save the current IP */
357 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
358 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ip));
360 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
361 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
369 * Emit code to pop an LMF structure from the LMF stack.
372 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
376 if (lmf_offset < 32) {
377 basereg = cfg->frame_reg;
382 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
385 /* ip = previous_lmf */
386 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
388 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
389 /* *(lmf_addr) = previous_lmf */
390 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
395 #endif /* #ifndef DISABLE_JIT */
398 * mono_arch_get_argument_info:
399 * @csig: a method signature
400 * @param_count: the number of parameters to consider
401 * @arg_info: an array to store the result infos
403 * Gathers information on parameters such as size, alignment and
404 * padding. arg_info should be large enought to hold param_count + 1 entries.
406 * Returns the size of the activation frame.
409 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
411 int k, frame_size = 0;
412 guint32 size, align, pad;
415 if (MONO_TYPE_ISSTRUCT (csig->ret)) {
416 frame_size += sizeof (gpointer);
420 arg_info [0].offset = offset;
423 frame_size += sizeof (gpointer);
427 arg_info [0].size = frame_size;
429 for (k = 0; k < param_count; k++) {
430 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
432 /* ignore alignment for now */
435 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
436 arg_info [k].pad = pad;
438 arg_info [k + 1].pad = 0;
439 arg_info [k + 1].size = size;
441 arg_info [k + 1].offset = offset;
445 align = MONO_ARCH_FRAME_ALIGNMENT;
446 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
447 arg_info [k].pad = pad;
452 #define MAX_ARCH_DELEGATE_PARAMS 3
455 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
457 guint8 *code, *start;
460 start = code = mono_global_codeman_reserve (12);
462 /* Replace the this argument with the target */
463 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
464 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
465 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
467 g_assert ((code - start) <= 12);
469 mono_arch_flush_icache (start, 12);
473 size = 8 + param_count * 4;
474 start = code = mono_global_codeman_reserve (size);
476 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
477 /* slide down the arguments */
478 for (i = 0; i < param_count; ++i) {
479 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
481 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
483 g_assert ((code - start) <= size);
485 mono_arch_flush_icache (start, size);
489 *code_size = code - start;
495 * mono_arch_get_delegate_invoke_impls:
497 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
501 mono_arch_get_delegate_invoke_impls (void)
508 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
509 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
511 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
512 code = get_delegate_invoke_impl (FALSE, i, &code_len);
513 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
520 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
522 guint8 *code, *start;
524 /* FIXME: Support more cases */
525 if (MONO_TYPE_ISSTRUCT (sig->ret))
529 static guint8* cached = NULL;
530 mono_mini_arch_lock ();
532 mono_mini_arch_unlock ();
537 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
539 start = get_delegate_invoke_impl (TRUE, 0, NULL);
541 mono_mini_arch_unlock ();
544 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
547 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
549 for (i = 0; i < sig->param_count; ++i)
550 if (!mono_is_regsize_var (sig->params [i]))
553 mono_mini_arch_lock ();
554 code = cache [sig->param_count];
556 mono_mini_arch_unlock ();
561 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
562 start = mono_aot_get_trampoline (name);
565 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
567 cache [sig->param_count] = start;
568 mono_mini_arch_unlock ();
576 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
578 return (gpointer)regs [ARMREG_R0];
582 * Initialize the cpu to execute managed code.
585 mono_arch_cpu_init (void)
587 #if defined(__ARM_EABI__)
588 eabi_supported = TRUE;
590 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
593 i8_align = __alignof__ (gint64);
598 create_function_wrapper (gpointer function)
600 guint8 *start, *code;
602 start = code = mono_global_codeman_reserve (96);
605 * Construct the MonoContext structure on the stack.
608 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, sizeof (MonoContext));
610 /* save ip, lr and pc into their correspodings ctx.regs slots. */
611 ARM_STR_IMM (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_IP);
612 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
613 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
615 /* save r0..r10 and fp */
616 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs));
617 ARM_STM (code, ARMREG_IP, 0x0fff);
619 /* now we can update fp. */
620 ARM_MOV_REG_REG (code, ARMREG_FP, ARMREG_SP);
622 /* make ctx.esp hold the actual value of sp at the beginning of this method. */
623 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_FP, sizeof (MonoContext));
624 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, 4 * ARMREG_SP);
625 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, esp));
627 /* make ctx.eip hold the address of the call. */
628 ARM_SUB_REG_IMM8 (code, ARMREG_LR, ARMREG_LR, 4);
629 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, eip));
631 /* r0 now points to the MonoContext */
632 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_FP);
635 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
637 *(gpointer*)code = function;
639 ARM_BLX_REG (code, ARMREG_IP);
641 /* we're back; save ctx.eip and ctx.esp into the corresponding regs slots. */
642 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, eip));
643 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
644 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
645 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, esp));
646 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_SP);
648 /* make ip point to the regs array, then restore everything, including pc. */
649 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs));
650 ARM_LDM (code, ARMREG_IP, 0xffff);
652 mono_arch_flush_icache (start, code - start);
658 * Initialize architecture specific code.
661 mono_arch_init (void)
663 InitializeCriticalSection (&mini_arch_mutex);
665 if (mini_get_debug_options ()->soft_breakpoints) {
666 single_step_func_wrapper = create_function_wrapper (debugger_agent_single_step_from_context);
667 breakpoint_func_wrapper = create_function_wrapper (debugger_agent_breakpoint_from_context);
669 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
670 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
671 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
674 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
675 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
676 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
679 arm_fpu = MONO_ARM_FPU_FPA;
680 #elif defined(ARM_FPU_VFP)
681 arm_fpu = MONO_ARM_FPU_VFP;
683 arm_fpu = MONO_ARM_FPU_NONE;
688 * Cleanup architecture specific code.
691 mono_arch_cleanup (void)
696 * This function returns the optimizations supported on this cpu.
699 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
702 const char *cpu_arch = getenv ("MONO_CPU_ARCH");
703 if (cpu_arch != NULL) {
704 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
705 if (strncmp (cpu_arch, "armv", 4) == 0) {
706 v5_supported = cpu_arch [4] >= '5';
707 v6_supported = cpu_arch [4] >= '6';
708 v7_supported = cpu_arch [4] >= '7';
712 thumb_supported = TRUE;
719 FILE *file = fopen ("/proc/cpuinfo", "r");
721 while ((line = fgets (buf, 512, file))) {
722 if (strncmp (line, "Processor", 9) == 0) {
723 char *ver = strstr (line, "(v");
724 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
726 if (ver && (ver [2] == '6' || ver [2] == '7'))
728 if (ver && (ver [2] == '7'))
732 if (strncmp (line, "Features", 8) == 0) {
733 char *th = strstr (line, "thumb");
735 thumb_supported = TRUE;
743 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
748 /* no arm-specific optimizations yet */
756 is_regsize_var (MonoType *t) {
759 t = mini_type_get_underlying_type (NULL, t);
766 case MONO_TYPE_FNPTR:
768 case MONO_TYPE_OBJECT:
769 case MONO_TYPE_STRING:
770 case MONO_TYPE_CLASS:
771 case MONO_TYPE_SZARRAY:
772 case MONO_TYPE_ARRAY:
774 case MONO_TYPE_GENERICINST:
775 if (!mono_type_generic_inst_is_valuetype (t))
778 case MONO_TYPE_VALUETYPE:
785 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
790 for (i = 0; i < cfg->num_varinfo; i++) {
791 MonoInst *ins = cfg->varinfo [i];
792 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
795 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
798 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
801 /* we can only allocate 32 bit values */
802 if (is_regsize_var (ins->inst_vtype)) {
803 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
804 g_assert (i == vmv->idx);
805 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
812 #define USE_EXTRA_TEMPS 0
815 mono_arch_get_global_int_regs (MonoCompile *cfg)
819 mono_arch_compute_omit_fp (cfg);
822 * FIXME: Interface calls might go through a static rgctx trampoline which
823 * sets V5, but it doesn't save it, so we need to save it ourselves, and
826 if (cfg->flags & MONO_CFG_HAS_CALLS)
827 cfg->uses_rgctx_reg = TRUE;
829 if (cfg->arch.omit_fp)
830 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
831 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
832 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
833 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
835 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
836 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
838 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
839 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
840 /* V5 is reserved for passing the vtable/rgctx/IMT method */
841 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
842 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
843 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
849 * mono_arch_regalloc_cost:
851 * Return the cost, in number of memory references, of the action of
852 * allocating the variable VMV into a register during global register
856 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
862 #endif /* #ifndef DISABLE_JIT */
864 #ifndef __GNUC_PREREQ
865 #define __GNUC_PREREQ(maj, min) (0)
869 mono_arch_flush_icache (guint8 *code, gint size)
872 sys_icache_invalidate (code, size);
873 #elif __GNUC_PREREQ(4, 1)
874 __clear_cache (code, code + size);
875 #elif defined(PLATFORM_ANDROID)
876 const int syscall = 0xf0002;
884 : "r" (code), "r" (code + size), "r" (syscall)
885 : "r0", "r1", "r7", "r2"
888 __asm __volatile ("mov r0, %0\n"
891 "swi 0x9f0002 @ sys_cacheflush"
893 : "r" (code), "r" (code + size), "r" (0)
894 : "r0", "r1", "r3" );
911 guint16 vtsize; /* in param area */
915 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
921 gboolean vtype_retaddr;
922 /* The index of the vret arg in the argument list */
932 /*#define __alignof__(a) sizeof(a)*/
933 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
939 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
942 if (*gr > ARMREG_R3) {
943 ainfo->offset = *stack_size;
944 ainfo->reg = ARMREG_SP; /* in the caller */
945 ainfo->storage = RegTypeBase;
948 ainfo->storage = RegTypeGeneral;
955 split = i8_align == 4;
959 if (*gr == ARMREG_R3 && split) {
960 /* first word in r3 and the second on the stack */
961 ainfo->offset = *stack_size;
962 ainfo->reg = ARMREG_SP; /* in the caller */
963 ainfo->storage = RegTypeBaseGen;
965 } else if (*gr >= ARMREG_R3) {
966 if (eabi_supported) {
967 /* darwin aligns longs to 4 byte only */
973 ainfo->offset = *stack_size;
974 ainfo->reg = ARMREG_SP; /* in the caller */
975 ainfo->storage = RegTypeBase;
978 if (eabi_supported) {
979 if (i8_align == 8 && ((*gr) & 1))
982 ainfo->storage = RegTypeIRegPair;
991 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
994 int n = sig->hasthis + sig->param_count;
995 MonoType *simpletype;
996 guint32 stack_size = 0;
998 gboolean is_pinvoke = sig->pinvoke;
1001 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1003 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1008 /* FIXME: handle returning a struct */
1009 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1012 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (sig->ret), &align) <= sizeof (gpointer)) {
1013 cinfo->ret.storage = RegTypeStructByVal;
1015 cinfo->vtype_retaddr = TRUE;
1022 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1023 * the first argument, allowing 'this' to be always passed in the first arg reg.
1024 * Also do this if the first argument is a reference type, since virtual calls
1025 * are sometimes made using calli without sig->hasthis set, like in the delegate
1028 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1030 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1032 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1036 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1037 cinfo->vret_arg_index = 1;
1041 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1045 if (cinfo->vtype_retaddr)
1046 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1049 DEBUG(printf("params: %d\n", sig->param_count));
1050 for (i = pstart; i < sig->param_count; ++i) {
1051 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1052 /* Prevent implicit arguments and sig_cookie from
1053 being passed in registers */
1055 /* Emit the signature cookie just before the implicit arguments */
1056 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1058 DEBUG(printf("param %d: ", i));
1059 if (sig->params [i]->byref) {
1060 DEBUG(printf("byref\n"));
1061 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1065 simpletype = mini_type_get_underlying_type (NULL, sig->params [i]);
1066 switch (simpletype->type) {
1067 case MONO_TYPE_BOOLEAN:
1070 cinfo->args [n].size = 1;
1071 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1074 case MONO_TYPE_CHAR:
1077 cinfo->args [n].size = 2;
1078 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1083 cinfo->args [n].size = 4;
1084 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1090 case MONO_TYPE_FNPTR:
1091 case MONO_TYPE_CLASS:
1092 case MONO_TYPE_OBJECT:
1093 case MONO_TYPE_STRING:
1094 case MONO_TYPE_SZARRAY:
1095 case MONO_TYPE_ARRAY:
1097 cinfo->args [n].size = sizeof (gpointer);
1098 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1101 case MONO_TYPE_GENERICINST:
1102 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1103 cinfo->args [n].size = sizeof (gpointer);
1104 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1109 case MONO_TYPE_TYPEDBYREF:
1110 case MONO_TYPE_VALUETYPE: {
1116 if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1117 size = sizeof (MonoTypedRef);
1118 align = sizeof (gpointer);
1120 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1122 size = mono_class_native_size (klass, &align);
1124 size = mono_class_value_size (klass, &align);
1126 DEBUG(printf ("load %d bytes struct\n",
1127 mono_class_native_size (sig->params [i]->data.klass, NULL)));
1130 align_size += (sizeof (gpointer) - 1);
1131 align_size &= ~(sizeof (gpointer) - 1);
1132 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1133 cinfo->args [n].storage = RegTypeStructByVal;
1134 cinfo->args [n].struct_size = size;
1135 /* FIXME: align stack_size if needed */
1136 if (eabi_supported) {
1137 if (align >= 8 && (gr & 1))
1140 if (gr > ARMREG_R3) {
1141 cinfo->args [n].size = 0;
1142 cinfo->args [n].vtsize = nwords;
1144 int rest = ARMREG_R3 - gr + 1;
1145 int n_in_regs = rest >= nwords? nwords: rest;
1147 cinfo->args [n].size = n_in_regs;
1148 cinfo->args [n].vtsize = nwords - n_in_regs;
1149 cinfo->args [n].reg = gr;
1151 nwords -= n_in_regs;
1153 cinfo->args [n].offset = stack_size;
1154 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1155 stack_size += nwords * sizeof (gpointer);
1162 cinfo->args [n].size = 8;
1163 add_general (&gr, &stack_size, cinfo->args + n, FALSE);
1167 g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1171 /* Handle the case where there are no implicit arguments */
1172 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1173 /* Prevent implicit arguments and sig_cookie from
1174 being passed in registers */
1176 /* Emit the signature cookie just before the implicit arguments */
1177 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1181 simpletype = mini_type_get_underlying_type (NULL, sig->ret);
1182 switch (simpletype->type) {
1183 case MONO_TYPE_BOOLEAN:
1188 case MONO_TYPE_CHAR:
1194 case MONO_TYPE_FNPTR:
1195 case MONO_TYPE_CLASS:
1196 case MONO_TYPE_OBJECT:
1197 case MONO_TYPE_SZARRAY:
1198 case MONO_TYPE_ARRAY:
1199 case MONO_TYPE_STRING:
1200 cinfo->ret.storage = RegTypeGeneral;
1201 cinfo->ret.reg = ARMREG_R0;
1205 cinfo->ret.storage = RegTypeIRegPair;
1206 cinfo->ret.reg = ARMREG_R0;
1210 cinfo->ret.storage = RegTypeFP;
1211 cinfo->ret.reg = ARMREG_R0;
1212 /* FIXME: cinfo->ret.reg = ???;
1213 cinfo->ret.storage = RegTypeFP;*/
1215 case MONO_TYPE_GENERICINST:
1216 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1217 cinfo->ret.storage = RegTypeGeneral;
1218 cinfo->ret.reg = ARMREG_R0;
1222 case MONO_TYPE_VALUETYPE:
1223 case MONO_TYPE_TYPEDBYREF:
1224 if (cinfo->ret.storage != RegTypeStructByVal)
1225 cinfo->ret.storage = RegTypeStructByAddr;
1227 case MONO_TYPE_VOID:
1230 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1234 /* align stack size to 8 */
1235 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1236 stack_size = (stack_size + 7) & ~7;
1238 cinfo->stack_usage = stack_size;
1244 G_GNUC_UNUSED static void
1249 G_GNUC_UNUSED static gboolean
1252 static int count = 0;
1255 if (!getenv ("COUNT"))
1258 if (count == atoi (getenv ("COUNT"))) {
1262 if (count > atoi (getenv ("COUNT"))) {
1270 debug_omit_fp (void)
1273 return debug_count ();
1280 * mono_arch_compute_omit_fp:
1282 * Determine whenever the frame pointer can be eliminated.
1285 mono_arch_compute_omit_fp (MonoCompile *cfg)
1287 MonoMethodSignature *sig;
1288 MonoMethodHeader *header;
1292 if (cfg->arch.omit_fp_computed)
1295 header = cfg->header;
1297 sig = mono_method_signature (cfg->method);
1299 if (!cfg->arch.cinfo)
1300 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1301 cinfo = cfg->arch.cinfo;
1304 * FIXME: Remove some of the restrictions.
1306 cfg->arch.omit_fp = TRUE;
1307 cfg->arch.omit_fp_computed = TRUE;
1309 if (cfg->disable_omit_fp)
1310 cfg->arch.omit_fp = FALSE;
1311 if (!debug_omit_fp ())
1312 cfg->arch.omit_fp = FALSE;
1314 if (cfg->method->save_lmf)
1315 cfg->arch.omit_fp = FALSE;
1317 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1318 cfg->arch.omit_fp = FALSE;
1319 if (header->num_clauses)
1320 cfg->arch.omit_fp = FALSE;
1321 if (cfg->param_area)
1322 cfg->arch.omit_fp = FALSE;
1323 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1324 cfg->arch.omit_fp = FALSE;
1325 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1326 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1327 cfg->arch.omit_fp = FALSE;
1328 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1329 ArgInfo *ainfo = &cinfo->args [i];
1331 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1333 * The stack offset can only be determined when the frame
1336 cfg->arch.omit_fp = FALSE;
1341 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1342 MonoInst *ins = cfg->varinfo [i];
1345 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1350 * Set var information according to the calling convention. arm version.
1351 * The locals var stuff should most likely be split in another method.
1354 mono_arch_allocate_vars (MonoCompile *cfg)
1356 MonoMethodSignature *sig;
1357 MonoMethodHeader *header;
1359 int i, offset, size, align, curinst;
1363 sig = mono_method_signature (cfg->method);
1365 if (!cfg->arch.cinfo)
1366 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1367 cinfo = cfg->arch.cinfo;
1369 mono_arch_compute_omit_fp (cfg);
1371 if (cfg->arch.omit_fp)
1372 cfg->frame_reg = ARMREG_SP;
1374 cfg->frame_reg = ARMREG_FP;
1376 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1378 /* allow room for the vararg method args: void* and long/double */
1379 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1380 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1382 header = cfg->header;
1384 /* See mono_arch_get_global_int_regs () */
1385 if (cfg->flags & MONO_CFG_HAS_CALLS)
1386 cfg->uses_rgctx_reg = TRUE;
1388 if (cfg->frame_reg != ARMREG_SP)
1389 cfg->used_int_regs |= 1 << cfg->frame_reg;
1391 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1392 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1393 cfg->used_int_regs |= (1 << ARMREG_V5);
1397 if (!MONO_TYPE_ISSTRUCT (sig->ret)) {
1398 switch (mini_type_get_underlying_type (NULL, sig->ret)->type) {
1399 case MONO_TYPE_VOID:
1402 cfg->ret->opcode = OP_REGVAR;
1403 cfg->ret->inst_c0 = ARMREG_R0;
1407 /* local vars are at a positive offset from the stack pointer */
1409 * also note that if the function uses alloca, we use FP
1410 * to point at the local variables.
1412 offset = 0; /* linkage area */
1413 /* align the offset to 16 bytes: not sure this is needed here */
1415 //offset &= ~(8 - 1);
1417 /* add parameter area size for called functions */
1418 offset += cfg->param_area;
1421 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1424 /* allow room to save the return value */
1425 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1428 /* the MonoLMF structure is stored just below the stack pointer */
1429 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1430 if (cinfo->ret.storage == RegTypeStructByVal) {
1431 cfg->ret->opcode = OP_REGOFFSET;
1432 cfg->ret->inst_basereg = cfg->frame_reg;
1433 offset += sizeof (gpointer) - 1;
1434 offset &= ~(sizeof (gpointer) - 1);
1435 cfg->ret->inst_offset = - offset;
1437 ins = cfg->vret_addr;
1438 offset += sizeof(gpointer) - 1;
1439 offset &= ~(sizeof(gpointer) - 1);
1440 ins->inst_offset = offset;
1441 ins->opcode = OP_REGOFFSET;
1442 ins->inst_basereg = cfg->frame_reg;
1443 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1444 printf ("vret_addr =");
1445 mono_print_ins (cfg->vret_addr);
1448 offset += sizeof(gpointer);
1451 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1452 if (cfg->arch.seq_point_info_var) {
1455 ins = cfg->arch.seq_point_info_var;
1459 offset += align - 1;
1460 offset &= ~(align - 1);
1461 ins->opcode = OP_REGOFFSET;
1462 ins->inst_basereg = cfg->frame_reg;
1463 ins->inst_offset = offset;
1466 ins = cfg->arch.ss_trigger_page_var;
1469 offset += align - 1;
1470 offset &= ~(align - 1);
1471 ins->opcode = OP_REGOFFSET;
1472 ins->inst_basereg = cfg->frame_reg;
1473 ins->inst_offset = offset;
1477 if (cfg->arch.seq_point_read_var) {
1480 ins = cfg->arch.seq_point_read_var;
1484 offset += align - 1;
1485 offset &= ~(align - 1);
1486 ins->opcode = OP_REGOFFSET;
1487 ins->inst_basereg = cfg->frame_reg;
1488 ins->inst_offset = offset;
1491 ins = cfg->arch.seq_point_ss_method_var;
1494 offset += align - 1;
1495 offset &= ~(align - 1);
1496 ins->opcode = OP_REGOFFSET;
1497 ins->inst_basereg = cfg->frame_reg;
1498 ins->inst_offset = offset;
1501 ins = cfg->arch.seq_point_bp_method_var;
1504 offset += align - 1;
1505 offset &= ~(align - 1);
1506 ins->opcode = OP_REGOFFSET;
1507 ins->inst_basereg = cfg->frame_reg;
1508 ins->inst_offset = offset;
1512 cfg->locals_min_stack_offset = offset;
1514 curinst = cfg->locals_start;
1515 for (i = curinst; i < cfg->num_varinfo; ++i) {
1516 ins = cfg->varinfo [i];
1517 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1520 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1521 * pinvoke wrappers when they call functions returning structure */
1522 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (ins->inst_vtype) && ins->inst_vtype->type != MONO_TYPE_TYPEDBYREF) {
1523 size = mono_class_native_size (mono_class_from_mono_type (ins->inst_vtype), &ualign);
1527 size = mono_type_size (ins->inst_vtype, &align);
1529 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1530 * since it loads/stores misaligned words, which don't do the right thing.
1532 if (align < 4 && size >= 4)
1534 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1535 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1536 offset += align - 1;
1537 offset &= ~(align - 1);
1538 ins->opcode = OP_REGOFFSET;
1539 ins->inst_offset = offset;
1540 ins->inst_basereg = cfg->frame_reg;
1542 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1545 cfg->locals_max_stack_offset = offset;
1549 ins = cfg->args [curinst];
1550 if (ins->opcode != OP_REGVAR) {
1551 ins->opcode = OP_REGOFFSET;
1552 ins->inst_basereg = cfg->frame_reg;
1553 offset += sizeof (gpointer) - 1;
1554 offset &= ~(sizeof (gpointer) - 1);
1555 ins->inst_offset = offset;
1556 offset += sizeof (gpointer);
1561 if (sig->call_convention == MONO_CALL_VARARG) {
1565 /* Allocate a local slot to hold the sig cookie address */
1566 offset += align - 1;
1567 offset &= ~(align - 1);
1568 cfg->sig_cookie = offset;
1572 for (i = 0; i < sig->param_count; ++i) {
1573 ins = cfg->args [curinst];
1575 if (ins->opcode != OP_REGVAR) {
1576 ins->opcode = OP_REGOFFSET;
1577 ins->inst_basereg = cfg->frame_reg;
1578 size = mini_type_stack_size_full (NULL, sig->params [i], &ualign, sig->pinvoke);
1580 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1581 * since it loads/stores misaligned words, which don't do the right thing.
1583 if (align < 4 && size >= 4)
1585 /* The code in the prolog () stores words when storing vtypes received in a register */
1586 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1588 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1589 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1590 offset += align - 1;
1591 offset &= ~(align - 1);
1592 ins->inst_offset = offset;
1598 /* align the offset to 8 bytes */
1599 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
1600 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1605 cfg->stack_offset = offset;
1609 mono_arch_create_vars (MonoCompile *cfg)
1611 MonoMethodSignature *sig;
1614 sig = mono_method_signature (cfg->method);
1616 if (!cfg->arch.cinfo)
1617 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1618 cinfo = cfg->arch.cinfo;
1620 if (cinfo->ret.storage == RegTypeStructByVal)
1621 cfg->ret_var_is_local = TRUE;
1623 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
1624 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1625 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1626 printf ("vret_addr = ");
1627 mono_print_ins (cfg->vret_addr);
1631 if (cfg->gen_seq_points) {
1632 if (cfg->soft_breakpoints) {
1633 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1634 ins->flags |= MONO_INST_VOLATILE;
1635 cfg->arch.seq_point_read_var = ins;
1637 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1638 ins->flags |= MONO_INST_VOLATILE;
1639 cfg->arch.seq_point_ss_method_var = ins;
1641 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1642 ins->flags |= MONO_INST_VOLATILE;
1643 cfg->arch.seq_point_bp_method_var = ins;
1645 g_assert (!cfg->compile_aot);
1646 } else if (cfg->compile_aot) {
1647 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1648 ins->flags |= MONO_INST_VOLATILE;
1649 cfg->arch.seq_point_info_var = ins;
1651 /* Allocate a separate variable for this to save 1 load per seq point */
1652 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1653 ins->flags |= MONO_INST_VOLATILE;
1654 cfg->arch.ss_trigger_page_var = ins;
1660 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1662 MonoMethodSignature *tmp_sig;
1665 if (call->tail_call)
1668 /* FIXME: Add support for signature tokens to AOT */
1669 cfg->disable_aot = TRUE;
1671 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1674 * mono_ArgIterator_Setup assumes the signature cookie is
1675 * passed first and all the arguments which were before it are
1676 * passed on the stack after the signature. So compensate by
1677 * passing a different signature.
1679 tmp_sig = mono_metadata_signature_dup (call->signature);
1680 tmp_sig->param_count -= call->signature->sentinelpos;
1681 tmp_sig->sentinelpos = 0;
1682 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1684 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1685 sig_arg->dreg = mono_alloc_ireg (cfg);
1686 sig_arg->inst_p0 = tmp_sig;
1687 MONO_ADD_INS (cfg->cbb, sig_arg);
1689 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_arg->dreg);
1694 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1699 LLVMCallInfo *linfo;
1701 n = sig->param_count + sig->hasthis;
1703 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1705 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1708 * LLVM always uses the native ABI while we use our own ABI, the
1709 * only difference is the handling of vtypes:
1710 * - we only pass/receive them in registers in some cases, and only
1711 * in 1 or 2 integer registers.
1713 if (cinfo->vtype_retaddr) {
1714 /* Vtype returned using a hidden argument */
1715 linfo->ret.storage = LLVMArgVtypeRetAddr;
1716 linfo->vret_arg_index = cinfo->vret_arg_index;
1717 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1718 cfg->exception_message = g_strdup ("unknown ret conv");
1719 cfg->disable_llvm = TRUE;
1723 for (i = 0; i < n; ++i) {
1724 ainfo = cinfo->args + i;
1726 linfo->args [i].storage = LLVMArgNone;
1728 switch (ainfo->storage) {
1729 case RegTypeGeneral:
1730 case RegTypeIRegPair:
1732 linfo->args [i].storage = LLVMArgInIReg;
1734 case RegTypeStructByVal:
1735 // FIXME: Passing entirely on the stack or split reg/stack
1736 if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1737 linfo->args [i].storage = LLVMArgVtypeInReg;
1738 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1739 if (ainfo->size == 2)
1740 linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1742 linfo->args [i].pair_storage [1] = LLVMArgNone;
1744 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1745 cfg->disable_llvm = TRUE;
1749 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1750 cfg->disable_llvm = TRUE;
1760 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1763 MonoMethodSignature *sig;
1767 sig = call->signature;
1768 n = sig->param_count + sig->hasthis;
1770 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1772 for (i = 0; i < n; ++i) {
1773 ArgInfo *ainfo = cinfo->args + i;
1776 if (i >= sig->hasthis)
1777 t = sig->params [i - sig->hasthis];
1779 t = &mono_defaults.int_class->byval_arg;
1780 t = mini_type_get_underlying_type (NULL, t);
1782 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1783 /* Emit the signature cookie just before the implicit arguments */
1784 emit_sig_cookie (cfg, call, cinfo);
1787 in = call->args [i];
1789 switch (ainfo->storage) {
1790 case RegTypeGeneral:
1791 case RegTypeIRegPair:
1792 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1793 MONO_INST_NEW (cfg, ins, OP_MOVE);
1794 ins->dreg = mono_alloc_ireg (cfg);
1795 ins->sreg1 = in->dreg + 1;
1796 MONO_ADD_INS (cfg->cbb, ins);
1797 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1799 MONO_INST_NEW (cfg, ins, OP_MOVE);
1800 ins->dreg = mono_alloc_ireg (cfg);
1801 ins->sreg1 = in->dreg + 2;
1802 MONO_ADD_INS (cfg->cbb, ins);
1803 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1804 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1805 if (ainfo->size == 4) {
1806 if (IS_SOFT_FLOAT) {
1807 /* mono_emit_call_args () have already done the r8->r4 conversion */
1808 /* The converted value is in an int vreg */
1809 MONO_INST_NEW (cfg, ins, OP_MOVE);
1810 ins->dreg = mono_alloc_ireg (cfg);
1811 ins->sreg1 = in->dreg;
1812 MONO_ADD_INS (cfg->cbb, ins);
1813 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1817 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1818 creg = mono_alloc_ireg (cfg);
1819 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1820 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1823 if (IS_SOFT_FLOAT) {
1824 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1825 ins->dreg = mono_alloc_ireg (cfg);
1826 ins->sreg1 = in->dreg;
1827 MONO_ADD_INS (cfg->cbb, ins);
1828 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1830 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1831 ins->dreg = mono_alloc_ireg (cfg);
1832 ins->sreg1 = in->dreg;
1833 MONO_ADD_INS (cfg->cbb, ins);
1834 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1838 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1839 creg = mono_alloc_ireg (cfg);
1840 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1841 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1842 creg = mono_alloc_ireg (cfg);
1843 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1844 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1847 cfg->flags |= MONO_CFG_HAS_FPOUT;
1849 MONO_INST_NEW (cfg, ins, OP_MOVE);
1850 ins->dreg = mono_alloc_ireg (cfg);
1851 ins->sreg1 = in->dreg;
1852 MONO_ADD_INS (cfg->cbb, ins);
1854 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1857 case RegTypeStructByAddr:
1860 /* FIXME: where si the data allocated? */
1861 arg->backend.reg3 = ainfo->reg;
1862 call->used_iregs |= 1 << ainfo->reg;
1863 g_assert_not_reached ();
1866 case RegTypeStructByVal:
1867 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1868 ins->opcode = OP_OUTARG_VT;
1869 ins->sreg1 = in->dreg;
1870 ins->klass = in->klass;
1871 ins->inst_p0 = call;
1872 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1873 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1874 mono_call_inst_add_outarg_vt (cfg, call, ins);
1875 MONO_ADD_INS (cfg->cbb, ins);
1878 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1879 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1880 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1881 if (t->type == MONO_TYPE_R8) {
1882 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1885 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1887 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1890 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1893 case RegTypeBaseGen:
1894 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1895 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1896 MONO_INST_NEW (cfg, ins, OP_MOVE);
1897 ins->dreg = mono_alloc_ireg (cfg);
1898 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1899 MONO_ADD_INS (cfg->cbb, ins);
1900 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1901 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1904 /* This should work for soft-float as well */
1906 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1907 creg = mono_alloc_ireg (cfg);
1908 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1909 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1910 creg = mono_alloc_ireg (cfg);
1911 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1912 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1913 cfg->flags |= MONO_CFG_HAS_FPOUT;
1915 g_assert_not_reached ();
1922 arg->backend.reg3 = ainfo->reg;
1923 /* FP args are passed in int regs */
1924 call->used_iregs |= 1 << ainfo->reg;
1925 if (ainfo->size == 8) {
1926 arg->opcode = OP_OUTARG_R8;
1927 call->used_iregs |= 1 << (ainfo->reg + 1);
1929 arg->opcode = OP_OUTARG_R4;
1932 cfg->flags |= MONO_CFG_HAS_FPOUT;
1936 g_assert_not_reached ();
1940 /* Handle the case where there are no implicit arguments */
1941 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1942 emit_sig_cookie (cfg, call, cinfo);
1944 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1947 if (cinfo->ret.storage == RegTypeStructByVal) {
1948 /* The JIT will transform this into a normal call */
1949 call->vret_in_reg = TRUE;
1951 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1952 vtarg->sreg1 = call->vret_var->dreg;
1953 vtarg->dreg = mono_alloc_preg (cfg);
1954 MONO_ADD_INS (cfg->cbb, vtarg);
1956 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1960 call->stack_usage = cinfo->stack_usage;
1966 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1968 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1969 ArgInfo *ainfo = ins->inst_p1;
1970 int ovf_size = ainfo->vtsize;
1971 int doffset = ainfo->offset;
1972 int struct_size = ainfo->struct_size;
1973 int i, soffset, dreg, tmpreg;
1976 for (i = 0; i < ainfo->size; ++i) {
1977 dreg = mono_alloc_ireg (cfg);
1978 switch (struct_size) {
1980 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1983 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
1986 tmpreg = mono_alloc_ireg (cfg);
1987 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1988 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
1989 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
1990 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1991 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
1992 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
1993 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1996 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1999 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2000 soffset += sizeof (gpointer);
2001 struct_size -= sizeof (gpointer);
2003 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2005 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2009 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2011 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2014 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2017 if (COMPILE_LLVM (cfg)) {
2018 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2020 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2021 ins->sreg1 = val->dreg + 1;
2022 ins->sreg2 = val->dreg + 2;
2023 MONO_ADD_INS (cfg->cbb, ins);
2028 case MONO_ARM_FPU_NONE:
2029 if (ret->type == MONO_TYPE_R8) {
2032 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2033 ins->dreg = cfg->ret->dreg;
2034 ins->sreg1 = val->dreg;
2035 MONO_ADD_INS (cfg->cbb, ins);
2038 if (ret->type == MONO_TYPE_R4) {
2039 /* Already converted to an int in method_to_ir () */
2040 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2044 case MONO_ARM_FPU_VFP:
2045 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2048 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2049 ins->dreg = cfg->ret->dreg;
2050 ins->sreg1 = val->dreg;
2051 MONO_ADD_INS (cfg->cbb, ins);
2055 case MONO_ARM_FPU_FPA:
2056 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
2057 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2062 g_assert_not_reached ();
2066 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2069 #endif /* #ifndef DISABLE_JIT */
2072 mono_arch_is_inst_imm (gint64 imm)
2077 #define DYN_CALL_STACK_ARGS 6
2080 MonoMethodSignature *sig;
2085 mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
2091 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2095 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2098 switch (cinfo->ret.storage) {
2100 case RegTypeGeneral:
2101 case RegTypeIRegPair:
2102 case RegTypeStructByAddr:
2115 for (i = 0; i < cinfo->nargs; ++i) {
2116 switch (cinfo->args [i].storage) {
2117 case RegTypeGeneral:
2119 case RegTypeIRegPair:
2122 if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2125 case RegTypeStructByVal:
2126 if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2134 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2135 for (i = 0; i < sig->param_count; ++i) {
2136 MonoType *t = sig->params [i];
2162 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2164 ArchDynCallInfo *info;
2167 cinfo = get_call_info (NULL, NULL, sig);
2169 if (!dyn_call_supported (cinfo, sig)) {
2174 info = g_new0 (ArchDynCallInfo, 1);
2175 // FIXME: Preprocess the info to speed up start_dyn_call ()
2177 info->cinfo = cinfo;
2179 return (MonoDynCallInfo*)info;
2183 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2185 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2187 g_free (ainfo->cinfo);
2192 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2194 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2195 DynCallArgs *p = (DynCallArgs*)buf;
2196 int arg_index, greg, i, j, pindex;
2197 MonoMethodSignature *sig = dinfo->sig;
2199 g_assert (buf_len >= sizeof (DynCallArgs));
2208 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2209 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2214 if (dinfo->cinfo->vtype_retaddr)
2215 p->regs [greg ++] = (mgreg_t)ret;
2217 for (i = pindex; i < sig->param_count; i++) {
2218 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2219 gpointer *arg = args [arg_index ++];
2220 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2223 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2225 else if (ainfo->storage == RegTypeBase)
2226 slot = PARAM_REGS + (ainfo->offset / 4);
2228 g_assert_not_reached ();
2231 p->regs [slot] = (mgreg_t)*arg;
2236 case MONO_TYPE_STRING:
2237 case MONO_TYPE_CLASS:
2238 case MONO_TYPE_ARRAY:
2239 case MONO_TYPE_SZARRAY:
2240 case MONO_TYPE_OBJECT:
2244 p->regs [slot] = (mgreg_t)*arg;
2246 case MONO_TYPE_BOOLEAN:
2248 p->regs [slot] = *(guint8*)arg;
2251 p->regs [slot] = *(gint8*)arg;
2254 p->regs [slot] = *(gint16*)arg;
2257 case MONO_TYPE_CHAR:
2258 p->regs [slot] = *(guint16*)arg;
2261 p->regs [slot] = *(gint32*)arg;
2264 p->regs [slot] = *(guint32*)arg;
2268 p->regs [slot ++] = (mgreg_t)arg [0];
2269 p->regs [slot] = (mgreg_t)arg [1];
2272 p->regs [slot] = *(mgreg_t*)arg;
2275 p->regs [slot ++] = (mgreg_t)arg [0];
2276 p->regs [slot] = (mgreg_t)arg [1];
2278 case MONO_TYPE_GENERICINST:
2279 if (MONO_TYPE_IS_REFERENCE (t)) {
2280 p->regs [slot] = (mgreg_t)*arg;
2285 case MONO_TYPE_VALUETYPE:
2286 g_assert (ainfo->storage == RegTypeStructByVal);
2288 if (ainfo->size == 0)
2289 slot = PARAM_REGS + (ainfo->offset / 4);
2293 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2294 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2297 g_assert_not_reached ();
2303 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2305 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2306 MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2307 guint8 *ret = ((DynCallArgs*)buf)->ret;
2308 mgreg_t res = ((DynCallArgs*)buf)->res;
2309 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2311 switch (mono_type_get_underlying_type (sig->ret)->type) {
2312 case MONO_TYPE_VOID:
2313 *(gpointer*)ret = NULL;
2315 case MONO_TYPE_STRING:
2316 case MONO_TYPE_CLASS:
2317 case MONO_TYPE_ARRAY:
2318 case MONO_TYPE_SZARRAY:
2319 case MONO_TYPE_OBJECT:
2323 *(gpointer*)ret = (gpointer)res;
2329 case MONO_TYPE_BOOLEAN:
2330 *(guint8*)ret = res;
2333 *(gint16*)ret = res;
2336 case MONO_TYPE_CHAR:
2337 *(guint16*)ret = res;
2340 *(gint32*)ret = res;
2343 *(guint32*)ret = res;
2347 /* This handles endianness as well */
2348 ((gint32*)ret) [0] = res;
2349 ((gint32*)ret) [1] = res2;
2351 case MONO_TYPE_GENERICINST:
2352 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2353 *(gpointer*)ret = (gpointer)res;
2358 case MONO_TYPE_VALUETYPE:
2359 g_assert (ainfo->cinfo->vtype_retaddr);
2364 *(float*)ret = *(float*)&res;
2366 case MONO_TYPE_R8: {
2373 *(double*)ret = *(double*)®s;
2377 g_assert_not_reached ();
2384 * Allow tracing to work with this interface (with an optional argument)
2388 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2392 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2393 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2394 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2395 code = emit_call_reg (code, ARMREG_R2);
2408 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2411 int save_mode = SAVE_NONE;
2413 MonoMethod *method = cfg->method;
2414 int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2415 int save_offset = cfg->param_area;
2419 offset = code - cfg->native_code;
2420 /* we need about 16 instructions */
2421 if (offset > (cfg->code_size - 16 * 4)) {
2422 cfg->code_size *= 2;
2423 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2424 code = cfg->native_code + offset;
2427 case MONO_TYPE_VOID:
2428 /* special case string .ctor icall */
2429 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2430 save_mode = SAVE_ONE;
2432 save_mode = SAVE_NONE;
2436 save_mode = SAVE_TWO;
2440 save_mode = SAVE_FP;
2442 case MONO_TYPE_VALUETYPE:
2443 save_mode = SAVE_STRUCT;
2446 save_mode = SAVE_ONE;
2450 switch (save_mode) {
2452 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2453 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2454 if (enable_arguments) {
2455 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2456 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2460 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2461 if (enable_arguments) {
2462 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2466 /* FIXME: what reg? */
2467 if (enable_arguments) {
2468 /* FIXME: what reg? */
2472 if (enable_arguments) {
2473 /* FIXME: get the actual address */
2474 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2482 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2483 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2484 code = emit_call_reg (code, ARMREG_IP);
2486 switch (save_mode) {
2488 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2489 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2492 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2506 * The immediate field for cond branches is big enough for all reasonable methods
2508 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2509 if (0 && ins->inst_true_bb->native_offset) { \
2510 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2512 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2513 ARM_B_COND (code, (condcode), 0); \
2516 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2518 /* emit an exception if condition is fail
2520 * We assign the extra code used to throw the implicit exceptions
2521 * to cfg->bb_exit as far as the big branch handling is concerned
2523 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
2525 mono_add_patch_info (cfg, code - cfg->native_code, \
2526 MONO_PATCH_INFO_EXC, exc_name); \
2527 ARM_BL_COND (code, (condcode), 0); \
2530 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2533 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2538 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2540 MonoInst *ins, *n, *last_ins = NULL;
2542 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2543 switch (ins->opcode) {
2546 /* Already done by an arch-independent pass */
2548 case OP_LOAD_MEMBASE:
2549 case OP_LOADI4_MEMBASE:
2551 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2552 * OP_LOAD_MEMBASE offset(basereg), reg
2554 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2555 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2556 ins->inst_basereg == last_ins->inst_destbasereg &&
2557 ins->inst_offset == last_ins->inst_offset) {
2558 if (ins->dreg == last_ins->sreg1) {
2559 MONO_DELETE_INS (bb, ins);
2562 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2563 ins->opcode = OP_MOVE;
2564 ins->sreg1 = last_ins->sreg1;
2568 * Note: reg1 must be different from the basereg in the second load
2569 * OP_LOAD_MEMBASE offset(basereg), reg1
2570 * OP_LOAD_MEMBASE offset(basereg), reg2
2572 * OP_LOAD_MEMBASE offset(basereg), reg1
2573 * OP_MOVE reg1, reg2
2575 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2576 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2577 ins->inst_basereg != last_ins->dreg &&
2578 ins->inst_basereg == last_ins->inst_basereg &&
2579 ins->inst_offset == last_ins->inst_offset) {
2581 if (ins->dreg == last_ins->dreg) {
2582 MONO_DELETE_INS (bb, ins);
2585 ins->opcode = OP_MOVE;
2586 ins->sreg1 = last_ins->dreg;
2589 //g_assert_not_reached ();
2593 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2594 * OP_LOAD_MEMBASE offset(basereg), reg
2596 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2597 * OP_ICONST reg, imm
2599 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2600 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2601 ins->inst_basereg == last_ins->inst_destbasereg &&
2602 ins->inst_offset == last_ins->inst_offset) {
2603 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2604 ins->opcode = OP_ICONST;
2605 ins->inst_c0 = last_ins->inst_imm;
2606 g_assert_not_reached (); // check this rule
2610 case OP_LOADU1_MEMBASE:
2611 case OP_LOADI1_MEMBASE:
2612 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2613 ins->inst_basereg == last_ins->inst_destbasereg &&
2614 ins->inst_offset == last_ins->inst_offset) {
2615 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2616 ins->sreg1 = last_ins->sreg1;
2619 case OP_LOADU2_MEMBASE:
2620 case OP_LOADI2_MEMBASE:
2621 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2622 ins->inst_basereg == last_ins->inst_destbasereg &&
2623 ins->inst_offset == last_ins->inst_offset) {
2624 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2625 ins->sreg1 = last_ins->sreg1;
2629 ins->opcode = OP_MOVE;
2633 if (ins->dreg == ins->sreg1) {
2634 MONO_DELETE_INS (bb, ins);
2638 * OP_MOVE sreg, dreg
2639 * OP_MOVE dreg, sreg
2641 if (last_ins && last_ins->opcode == OP_MOVE &&
2642 ins->sreg1 == last_ins->dreg &&
2643 ins->dreg == last_ins->sreg1) {
2644 MONO_DELETE_INS (bb, ins);
2652 bb->last_ins = last_ins;
2656 * the branch_cc_table should maintain the order of these
2670 branch_cc_table [] = {
2684 #define NEW_INS(cfg,dest,op) do { \
2685 MONO_INST_NEW ((cfg), (dest), (op)); \
2686 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2690 map_to_reg_reg_op (int op)
2699 case OP_COMPARE_IMM:
2701 case OP_ICOMPARE_IMM:
2715 case OP_LOAD_MEMBASE:
2716 return OP_LOAD_MEMINDEX;
2717 case OP_LOADI4_MEMBASE:
2718 return OP_LOADI4_MEMINDEX;
2719 case OP_LOADU4_MEMBASE:
2720 return OP_LOADU4_MEMINDEX;
2721 case OP_LOADU1_MEMBASE:
2722 return OP_LOADU1_MEMINDEX;
2723 case OP_LOADI2_MEMBASE:
2724 return OP_LOADI2_MEMINDEX;
2725 case OP_LOADU2_MEMBASE:
2726 return OP_LOADU2_MEMINDEX;
2727 case OP_LOADI1_MEMBASE:
2728 return OP_LOADI1_MEMINDEX;
2729 case OP_STOREI1_MEMBASE_REG:
2730 return OP_STOREI1_MEMINDEX;
2731 case OP_STOREI2_MEMBASE_REG:
2732 return OP_STOREI2_MEMINDEX;
2733 case OP_STOREI4_MEMBASE_REG:
2734 return OP_STOREI4_MEMINDEX;
2735 case OP_STORE_MEMBASE_REG:
2736 return OP_STORE_MEMINDEX;
2737 case OP_STORER4_MEMBASE_REG:
2738 return OP_STORER4_MEMINDEX;
2739 case OP_STORER8_MEMBASE_REG:
2740 return OP_STORER8_MEMINDEX;
2741 case OP_STORE_MEMBASE_IMM:
2742 return OP_STORE_MEMBASE_REG;
2743 case OP_STOREI1_MEMBASE_IMM:
2744 return OP_STOREI1_MEMBASE_REG;
2745 case OP_STOREI2_MEMBASE_IMM:
2746 return OP_STOREI2_MEMBASE_REG;
2747 case OP_STOREI4_MEMBASE_IMM:
2748 return OP_STOREI4_MEMBASE_REG;
2750 g_assert_not_reached ();
2754 * Remove from the instruction list the instructions that can't be
2755 * represented with very simple instructions with no register
2759 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2761 MonoInst *ins, *temp, *last_ins = NULL;
2762 int rot_amount, imm8, low_imm;
2764 MONO_BB_FOR_EACH_INS (bb, ins) {
2766 switch (ins->opcode) {
2770 case OP_COMPARE_IMM:
2771 case OP_ICOMPARE_IMM:
2785 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2786 NEW_INS (cfg, temp, OP_ICONST);
2787 temp->inst_c0 = ins->inst_imm;
2788 temp->dreg = mono_alloc_ireg (cfg);
2789 ins->sreg2 = temp->dreg;
2790 ins->opcode = mono_op_imm_to_op (ins->opcode);
2792 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2798 if (ins->inst_imm == 1) {
2799 ins->opcode = OP_MOVE;
2802 if (ins->inst_imm == 0) {
2803 ins->opcode = OP_ICONST;
2807 imm8 = mono_is_power_of_two (ins->inst_imm);
2809 ins->opcode = OP_SHL_IMM;
2810 ins->inst_imm = imm8;
2813 NEW_INS (cfg, temp, OP_ICONST);
2814 temp->inst_c0 = ins->inst_imm;
2815 temp->dreg = mono_alloc_ireg (cfg);
2816 ins->sreg2 = temp->dreg;
2817 ins->opcode = OP_IMUL;
2823 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2824 /* ARM sets the C flag to 1 if there was _no_ overflow */
2825 ins->next->opcode = OP_COND_EXC_NC;
2827 case OP_LOCALLOC_IMM:
2828 NEW_INS (cfg, temp, OP_ICONST);
2829 temp->inst_c0 = ins->inst_imm;
2830 temp->dreg = mono_alloc_ireg (cfg);
2831 ins->sreg1 = temp->dreg;
2832 ins->opcode = OP_LOCALLOC;
2834 case OP_LOAD_MEMBASE:
2835 case OP_LOADI4_MEMBASE:
2836 case OP_LOADU4_MEMBASE:
2837 case OP_LOADU1_MEMBASE:
2838 /* we can do two things: load the immed in a register
2839 * and use an indexed load, or see if the immed can be
2840 * represented as an ad_imm + a load with a smaller offset
2841 * that fits. We just do the first for now, optimize later.
2843 if (arm_is_imm12 (ins->inst_offset))
2845 NEW_INS (cfg, temp, OP_ICONST);
2846 temp->inst_c0 = ins->inst_offset;
2847 temp->dreg = mono_alloc_ireg (cfg);
2848 ins->sreg2 = temp->dreg;
2849 ins->opcode = map_to_reg_reg_op (ins->opcode);
2851 case OP_LOADI2_MEMBASE:
2852 case OP_LOADU2_MEMBASE:
2853 case OP_LOADI1_MEMBASE:
2854 if (arm_is_imm8 (ins->inst_offset))
2856 NEW_INS (cfg, temp, OP_ICONST);
2857 temp->inst_c0 = ins->inst_offset;
2858 temp->dreg = mono_alloc_ireg (cfg);
2859 ins->sreg2 = temp->dreg;
2860 ins->opcode = map_to_reg_reg_op (ins->opcode);
2862 case OP_LOADR4_MEMBASE:
2863 case OP_LOADR8_MEMBASE:
2864 if (arm_is_fpimm8 (ins->inst_offset))
2866 low_imm = ins->inst_offset & 0x1ff;
2867 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2868 NEW_INS (cfg, temp, OP_ADD_IMM);
2869 temp->inst_imm = ins->inst_offset & ~0x1ff;
2870 temp->sreg1 = ins->inst_basereg;
2871 temp->dreg = mono_alloc_ireg (cfg);
2872 ins->inst_basereg = temp->dreg;
2873 ins->inst_offset = low_imm;
2876 /* VFP/FPA doesn't have indexed load instructions */
2877 g_assert_not_reached ();
2879 case OP_STORE_MEMBASE_REG:
2880 case OP_STOREI4_MEMBASE_REG:
2881 case OP_STOREI1_MEMBASE_REG:
2882 if (arm_is_imm12 (ins->inst_offset))
2884 NEW_INS (cfg, temp, OP_ICONST);
2885 temp->inst_c0 = ins->inst_offset;
2886 temp->dreg = mono_alloc_ireg (cfg);
2887 ins->sreg2 = temp->dreg;
2888 ins->opcode = map_to_reg_reg_op (ins->opcode);
2890 case OP_STOREI2_MEMBASE_REG:
2891 if (arm_is_imm8 (ins->inst_offset))
2893 NEW_INS (cfg, temp, OP_ICONST);
2894 temp->inst_c0 = ins->inst_offset;
2895 temp->dreg = mono_alloc_ireg (cfg);
2896 ins->sreg2 = temp->dreg;
2897 ins->opcode = map_to_reg_reg_op (ins->opcode);
2899 case OP_STORER4_MEMBASE_REG:
2900 case OP_STORER8_MEMBASE_REG:
2901 if (arm_is_fpimm8 (ins->inst_offset))
2903 low_imm = ins->inst_offset & 0x1ff;
2904 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2905 NEW_INS (cfg, temp, OP_ADD_IMM);
2906 temp->inst_imm = ins->inst_offset & ~0x1ff;
2907 temp->sreg1 = ins->inst_destbasereg;
2908 temp->dreg = mono_alloc_ireg (cfg);
2909 ins->inst_destbasereg = temp->dreg;
2910 ins->inst_offset = low_imm;
2913 /*g_print ("fail with: %d (%d, %d)\n", ins->inst_offset, ins->inst_offset & ~0x1ff, low_imm);*/
2914 /* VFP/FPA doesn't have indexed store instructions */
2915 g_assert_not_reached ();
2917 case OP_STORE_MEMBASE_IMM:
2918 case OP_STOREI1_MEMBASE_IMM:
2919 case OP_STOREI2_MEMBASE_IMM:
2920 case OP_STOREI4_MEMBASE_IMM:
2921 NEW_INS (cfg, temp, OP_ICONST);
2922 temp->inst_c0 = ins->inst_imm;
2923 temp->dreg = mono_alloc_ireg (cfg);
2924 ins->sreg1 = temp->dreg;
2925 ins->opcode = map_to_reg_reg_op (ins->opcode);
2927 goto loop_start; /* make it handle the possibly big ins->inst_offset */
2929 gboolean swap = FALSE;
2933 /* Optimized away */
2938 /* Some fp compares require swapped operands */
2939 switch (ins->next->opcode) {
2941 ins->next->opcode = OP_FBLT;
2945 ins->next->opcode = OP_FBLT_UN;
2949 ins->next->opcode = OP_FBGE;
2953 ins->next->opcode = OP_FBGE_UN;
2961 ins->sreg1 = ins->sreg2;
2970 bb->last_ins = last_ins;
2971 bb->max_vreg = cfg->next_vreg;
2975 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2979 if (long_ins->opcode == OP_LNEG) {
2981 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
2982 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
2988 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2990 /* sreg is a float, dreg is an integer reg */
2992 ARM_FPA_FIXZ (code, dreg, sreg);
2995 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
2997 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
2998 ARM_FMRS (code, dreg, ARM_VFP_F0);
3002 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3003 else if (size == 2) {
3004 ARM_SHL_IMM (code, dreg, dreg, 16);
3005 ARM_SHR_IMM (code, dreg, dreg, 16);
3009 ARM_SHL_IMM (code, dreg, dreg, 24);
3010 ARM_SAR_IMM (code, dreg, dreg, 24);
3011 } else if (size == 2) {
3012 ARM_SHL_IMM (code, dreg, dreg, 16);
3013 ARM_SAR_IMM (code, dreg, dreg, 16);
3019 #endif /* #ifndef DISABLE_JIT */
3023 const guchar *target;
3028 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3031 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
3032 PatchData *pdata = (PatchData*)user_data;
3033 guchar *code = data;
3034 guint32 *thunks = data;
3035 guint32 *endthunks = (guint32*)(code + bsize);
3037 int difflow, diffhigh;
3039 /* always ensure a call from pdata->code can reach to the thunks without further thunks */
3040 difflow = (char*)pdata->code - (char*)thunks;
3041 diffhigh = (char*)pdata->code - (char*)endthunks;
3042 if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
3046 * The thunk is composed of 3 words:
3047 * load constant from thunks [2] into ARM_IP
3050 * Note that the LR register is already setup
3052 //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
3053 if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
3054 while (thunks < endthunks) {
3055 //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
3056 if (thunks [2] == (guint32)pdata->target) {
3057 arm_patch (pdata->code, (guchar*)thunks);
3058 mono_arch_flush_icache (pdata->code, 4);
3061 } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
3062 /* found a free slot instead: emit thunk */
3063 /* ARMREG_IP is fine to use since this can't be an IMT call
3066 code = (guchar*)thunks;
3067 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3068 if (thumb_supported)
3069 ARM_BX (code, ARMREG_IP);
3071 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3072 thunks [2] = (guint32)pdata->target;
3073 mono_arch_flush_icache ((guchar*)thunks, 12);
3075 arm_patch (pdata->code, (guchar*)thunks);
3076 mono_arch_flush_icache (pdata->code, 4);
3080 /* skip 12 bytes, the size of the thunk */
3084 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
3090 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3095 domain = mono_domain_get ();
3098 pdata.target = target;
3099 pdata.absolute = absolute;
3103 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
3106 if (pdata.found != 1) {
3107 mono_domain_lock (domain);
3108 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3111 /* this uses the first available slot */
3113 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3115 mono_domain_unlock (domain);
3118 if (pdata.found != 1) {
3120 GHashTableIter iter;
3121 MonoJitDynamicMethodInfo *ji;
3124 * This might be a dynamic method, search its code manager. We can only
3125 * use the dynamic method containing CODE, since the others might be freed later.
3129 mono_domain_lock (domain);
3130 hash = domain_jit_info (domain)->dynamic_code_hash;
3132 /* FIXME: Speed this up */
3133 g_hash_table_iter_init (&iter, hash);
3134 while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
3135 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
3136 if (pdata.found == 1)
3140 mono_domain_unlock (domain);
3142 if (pdata.found != 1)
3143 g_print ("thunk failed for %p from %p\n", target, code);
3144 g_assert (pdata.found == 1);
3148 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3150 guint32 *code32 = (void*)code;
3151 guint32 ins = *code32;
3152 guint32 prim = (ins >> 25) & 7;
3153 guint32 tval = GPOINTER_TO_UINT (target);
3155 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3156 if (prim == 5) { /* 101b */
3157 /* the diff starts 8 bytes from the branch opcode */
3158 gint diff = target - code - 8;
3160 gint tmask = 0xffffffff;
3161 if (tval & 1) { /* entering thumb mode */
3162 diff = target - 1 - code - 8;
3163 g_assert (thumb_supported);
3164 tbits = 0xf << 28; /* bl->blx bit pattern */
3165 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3166 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3170 tmask = ~(1 << 24); /* clear the link bit */
3171 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3176 if (diff <= 33554431) {
3178 ins = (ins & 0xff000000) | diff;
3180 *code32 = ins | tbits;
3184 /* diff between 0 and -33554432 */
3185 if (diff >= -33554432) {
3187 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3189 *code32 = ins | tbits;
3194 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3199 * The alternative call sequences looks like this:
3201 * ldr ip, [pc] // loads the address constant
3202 * b 1f // jumps around the constant
3203 * address constant embedded in the code
3208 * There are two cases for patching:
3209 * a) at the end of method emission: in this case code points to the start
3210 * of the call sequence
3211 * b) during runtime patching of the call site: in this case code points
3212 * to the mov pc, ip instruction
3214 * We have to handle also the thunk jump code sequence:
3218 * address constant // execution never reaches here
3220 if ((ins & 0x0ffffff0) == 0x12fff10) {
3221 /* Branch and exchange: the address is constructed in a reg
3222 * We can patch BX when the code sequence is the following:
3223 * ldr ip, [pc, #0] ; 0x8
3230 guint8 *emit = (guint8*)ccode;
3231 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3233 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3234 ARM_BX (emit, ARMREG_IP);
3236 /*patching from magic trampoline*/
3237 if (ins == ccode [3]) {
3238 g_assert (code32 [-4] == ccode [0]);
3239 g_assert (code32 [-3] == ccode [1]);
3240 g_assert (code32 [-1] == ccode [2]);
3241 code32 [-2] = (guint32)target;
3244 /*patching from JIT*/
3245 if (ins == ccode [0]) {
3246 g_assert (code32 [1] == ccode [1]);
3247 g_assert (code32 [3] == ccode [2]);
3248 g_assert (code32 [4] == ccode [3]);
3249 code32 [2] = (guint32)target;
3252 g_assert_not_reached ();
3253 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3261 guint8 *emit = (guint8*)ccode;
3262 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3264 ARM_BLX_REG (emit, ARMREG_IP);
3266 g_assert (code32 [-3] == ccode [0]);
3267 g_assert (code32 [-2] == ccode [1]);
3268 g_assert (code32 [0] == ccode [2]);
3270 code32 [-1] = (guint32)target;
3273 guint32 *tmp = ccode;
3274 guint8 *emit = (guint8*)tmp;
3275 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3276 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3277 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3278 ARM_BX (emit, ARMREG_IP);
3279 if (ins == ccode [2]) {
3280 g_assert_not_reached (); // should be -2 ...
3281 code32 [-1] = (guint32)target;
3284 if (ins == ccode [0]) {
3285 /* handles both thunk jump code and the far call sequence */
3286 code32 [2] = (guint32)target;
3289 g_assert_not_reached ();
3291 // g_print ("patched with 0x%08x\n", ins);
3295 arm_patch (guchar *code, const guchar *target)
3297 arm_patch_general (NULL, code, target, NULL);
3301 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3302 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3303 * to be used with the emit macros.
3304 * Return -1 otherwise.
3307 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3310 for (i = 0; i < 31; i+= 2) {
3311 res = (val << (32 - i)) | (val >> i);
3314 *rot_amount = i? 32 - i: 0;
3321 * Emits in code a sequence of instructions that load the value 'val'
3322 * into the dreg register. Uses at most 4 instructions.
3325 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3327 int imm8, rot_amount;
3329 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3330 /* skip the constant pool */
3336 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3337 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3338 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3339 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3342 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3344 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3348 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3350 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3352 if (val & 0xFF0000) {
3353 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3355 if (val & 0xFF000000) {
3356 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3358 } else if (val & 0xFF00) {
3359 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3360 if (val & 0xFF0000) {
3361 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3363 if (val & 0xFF000000) {
3364 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3366 } else if (val & 0xFF0000) {
3367 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3368 if (val & 0xFF000000) {
3369 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3372 //g_assert_not_reached ();
3378 mono_arm_thumb_supported (void)
3380 return thumb_supported;
3386 * emit_load_volatile_arguments:
3388 * Load volatile arguments from the stack to the original input registers.
3389 * Required before a tail call.
3392 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3394 MonoMethod *method = cfg->method;
3395 MonoMethodSignature *sig;
3400 /* FIXME: Generate intermediate code instead */
3402 sig = mono_method_signature (method);
3404 /* This is the opposite of the code in emit_prolog */
3408 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3410 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
3411 ArgInfo *ainfo = &cinfo->ret;
3412 inst = cfg->vret_addr;
3413 g_assert (arm_is_imm12 (inst->inst_offset));
3414 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3416 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3417 ArgInfo *ainfo = cinfo->args + i;
3418 inst = cfg->args [pos];
3420 if (cfg->verbose_level > 2)
3421 g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3422 if (inst->opcode == OP_REGVAR) {
3423 if (ainfo->storage == RegTypeGeneral)
3424 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3425 else if (ainfo->storage == RegTypeFP) {
3426 g_assert_not_reached ();
3427 } else if (ainfo->storage == RegTypeBase) {
3431 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3432 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3434 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3435 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3439 g_assert_not_reached ();
3441 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3442 switch (ainfo->size) {
3449 g_assert (arm_is_imm12 (inst->inst_offset));
3450 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3451 g_assert (arm_is_imm12 (inst->inst_offset + 4));
3452 ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3455 if (arm_is_imm12 (inst->inst_offset)) {
3456 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3458 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3459 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3463 } else if (ainfo->storage == RegTypeBaseGen) {
3466 } else if (ainfo->storage == RegTypeBase) {
3468 } else if (ainfo->storage == RegTypeFP) {
3469 g_assert_not_reached ();
3470 } else if (ainfo->storage == RegTypeStructByVal) {
3471 int doffset = inst->inst_offset;
3475 if (mono_class_from_mono_type (inst->inst_vtype))
3476 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3477 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3478 if (arm_is_imm12 (doffset)) {
3479 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3481 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3482 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3484 soffset += sizeof (gpointer);
3485 doffset += sizeof (gpointer);
3490 } else if (ainfo->storage == RegTypeStructByAddr) {
3505 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3510 guint8 *code = cfg->native_code + cfg->code_len;
3511 MonoInst *last_ins = NULL;
3512 guint last_offset = 0;
3514 int imm8, rot_amount;
3516 /* we don't align basic blocks of loops on arm */
3518 if (cfg->verbose_level > 2)
3519 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3521 cpos = bb->max_offset;
3523 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3524 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3525 //g_assert (!mono_compile_aot);
3528 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3529 /* this is not thread save, but good enough */
3530 /* fixme: howto handle overflows? */
3531 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3534 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3535 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3536 (gpointer)"mono_break");
3537 code = emit_call_seq (cfg, code);
3540 MONO_BB_FOR_EACH_INS (bb, ins) {
3541 offset = code - cfg->native_code;
3543 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3545 if (offset > (cfg->code_size - max_len - 16)) {
3546 cfg->code_size *= 2;
3547 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3548 code = cfg->native_code + offset;
3550 // if (ins->cil_code)
3551 // g_print ("cil code\n");
3552 mono_debug_record_line_number (cfg, ins, offset);
3554 switch (ins->opcode) {
3555 case OP_MEMORY_BARRIER:
3557 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
3558 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
3562 #ifdef HAVE_AEABI_READ_TP
3563 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3564 (gpointer)"__aeabi_read_tp");
3565 code = emit_call_seq (cfg, code);
3567 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3569 g_assert_not_reached ();
3573 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3574 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3577 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3578 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3580 case OP_STOREI1_MEMBASE_IMM:
3581 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3582 g_assert (arm_is_imm12 (ins->inst_offset));
3583 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3585 case OP_STOREI2_MEMBASE_IMM:
3586 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3587 g_assert (arm_is_imm8 (ins->inst_offset));
3588 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3590 case OP_STORE_MEMBASE_IMM:
3591 case OP_STOREI4_MEMBASE_IMM:
3592 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3593 g_assert (arm_is_imm12 (ins->inst_offset));
3594 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3596 case OP_STOREI1_MEMBASE_REG:
3597 g_assert (arm_is_imm12 (ins->inst_offset));
3598 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3600 case OP_STOREI2_MEMBASE_REG:
3601 g_assert (arm_is_imm8 (ins->inst_offset));
3602 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3604 case OP_STORE_MEMBASE_REG:
3605 case OP_STOREI4_MEMBASE_REG:
3606 /* this case is special, since it happens for spill code after lowering has been called */
3607 if (arm_is_imm12 (ins->inst_offset)) {
3608 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3610 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3611 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3614 case OP_STOREI1_MEMINDEX:
3615 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3617 case OP_STOREI2_MEMINDEX:
3618 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3620 case OP_STORE_MEMINDEX:
3621 case OP_STOREI4_MEMINDEX:
3622 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3625 g_assert_not_reached ();
3627 case OP_LOAD_MEMINDEX:
3628 case OP_LOADI4_MEMINDEX:
3629 case OP_LOADU4_MEMINDEX:
3630 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3632 case OP_LOADI1_MEMINDEX:
3633 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3635 case OP_LOADU1_MEMINDEX:
3636 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3638 case OP_LOADI2_MEMINDEX:
3639 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3641 case OP_LOADU2_MEMINDEX:
3642 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3644 case OP_LOAD_MEMBASE:
3645 case OP_LOADI4_MEMBASE:
3646 case OP_LOADU4_MEMBASE:
3647 /* this case is special, since it happens for spill code after lowering has been called */
3648 if (arm_is_imm12 (ins->inst_offset)) {
3649 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3651 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3652 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3655 case OP_LOADI1_MEMBASE:
3656 g_assert (arm_is_imm8 (ins->inst_offset));
3657 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3659 case OP_LOADU1_MEMBASE:
3660 g_assert (arm_is_imm12 (ins->inst_offset));
3661 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3663 case OP_LOADU2_MEMBASE:
3664 g_assert (arm_is_imm8 (ins->inst_offset));
3665 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3667 case OP_LOADI2_MEMBASE:
3668 g_assert (arm_is_imm8 (ins->inst_offset));
3669 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3671 case OP_ICONV_TO_I1:
3672 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3673 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3675 case OP_ICONV_TO_I2:
3676 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3677 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3679 case OP_ICONV_TO_U1:
3680 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3682 case OP_ICONV_TO_U2:
3683 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3684 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3688 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3690 case OP_COMPARE_IMM:
3691 case OP_ICOMPARE_IMM:
3692 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3693 g_assert (imm8 >= 0);
3694 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3698 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3699 * So instead of emitting a trap, we emit a call a C function and place a
3702 //*(int*)code = 0xef9f0001;
3705 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3706 (gpointer)"mono_break");
3707 code = emit_call_seq (cfg, code);
3709 case OP_RELAXED_NOP:
3714 case OP_DUMMY_STORE:
3715 case OP_NOT_REACHED:
3718 case OP_SEQ_POINT: {
3720 MonoInst *info_var = cfg->arch.seq_point_info_var;
3721 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3722 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
3723 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
3724 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
3726 int dreg = ARMREG_LR;
3728 if (cfg->soft_breakpoints) {
3729 g_assert (!cfg->compile_aot);
3733 * For AOT, we use one got slot per method, which will point to a
3734 * SeqPointInfo structure, containing all the information required
3735 * by the code below.
3737 if (cfg->compile_aot) {
3738 g_assert (info_var);
3739 g_assert (info_var->opcode == OP_REGOFFSET);
3740 g_assert (arm_is_imm12 (info_var->inst_offset));
3743 if (!cfg->soft_breakpoints) {
3745 * Read from the single stepping trigger page. This will cause a
3746 * SIGSEGV when single stepping is enabled.
3747 * We do this _before_ the breakpoint, so single stepping after
3748 * a breakpoint is hit will step to the next IL offset.
3750 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3753 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3754 if (cfg->soft_breakpoints) {
3755 /* Load the address of the sequence point trigger variable. */
3758 g_assert (var->opcode == OP_REGOFFSET);
3759 g_assert (arm_is_imm12 (var->inst_offset));
3760 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3762 /* Read the value and check whether it is non-zero. */
3763 ARM_LDR_IMM (code, dreg, dreg, 0);
3764 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3766 /* Load the address of the sequence point method. */
3767 var = ss_method_var;
3769 g_assert (var->opcode == OP_REGOFFSET);
3770 g_assert (arm_is_imm12 (var->inst_offset));
3771 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3773 /* Call it conditionally. */
3774 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
3776 if (cfg->compile_aot) {
3777 /* Load the trigger page addr from the variable initialized in the prolog */
3778 var = ss_trigger_page_var;
3780 g_assert (var->opcode == OP_REGOFFSET);
3781 g_assert (arm_is_imm12 (var->inst_offset));
3782 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3784 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3786 *(int*)code = (int)ss_trigger_page;
3789 ARM_LDR_IMM (code, dreg, dreg, 0);
3793 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3795 if (cfg->soft_breakpoints) {
3796 /* Load the address of the breakpoint method into ip. */
3797 var = bp_method_var;
3799 g_assert (var->opcode == OP_REGOFFSET);
3800 g_assert (arm_is_imm12 (var->inst_offset));
3801 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3804 * A placeholder for a possible breakpoint inserted by
3805 * mono_arch_set_breakpoint ().
3808 } else if (cfg->compile_aot) {
3809 guint32 offset = code - cfg->native_code;
3812 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3813 /* Add the offset */
3814 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3815 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3817 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3819 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3820 g_assert (!(val & 0xFF000000));
3821 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3822 ARM_LDR_IMM (code, dreg, dreg, 0);
3824 /* What is faster, a branch or a load ? */
3825 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3826 /* The breakpoint instruction */
3827 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3830 * A placeholder for a possible breakpoint inserted by
3831 * mono_arch_set_breakpoint ().
3833 for (i = 0; i < 4; ++i)
3840 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3843 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3847 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3850 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3851 g_assert (imm8 >= 0);
3852 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3856 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3857 g_assert (imm8 >= 0);
3858 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3862 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3863 g_assert (imm8 >= 0);
3864 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3867 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3868 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3870 case OP_IADD_OVF_UN:
3871 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3872 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3875 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3876 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3878 case OP_ISUB_OVF_UN:
3879 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3880 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3882 case OP_ADD_OVF_CARRY:
3883 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3884 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3886 case OP_ADD_OVF_UN_CARRY:
3887 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3888 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3890 case OP_SUB_OVF_CARRY:
3891 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3892 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3894 case OP_SUB_OVF_UN_CARRY:
3895 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3896 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3900 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3903 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3904 g_assert (imm8 >= 0);
3905 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3908 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3912 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3916 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3917 g_assert (imm8 >= 0);
3918 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3922 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3923 g_assert (imm8 >= 0);
3924 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3926 case OP_ARM_RSBS_IMM:
3927 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3928 g_assert (imm8 >= 0);
3929 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3931 case OP_ARM_RSC_IMM:
3932 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3933 g_assert (imm8 >= 0);
3934 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3937 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3941 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3942 g_assert (imm8 >= 0);
3943 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3951 /* crappy ARM arch doesn't have a DIV instruction */
3952 g_assert_not_reached ();
3954 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3958 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3959 g_assert (imm8 >= 0);
3960 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3963 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3967 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3968 g_assert (imm8 >= 0);
3969 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3972 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3977 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3978 else if (ins->dreg != ins->sreg1)
3979 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3982 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3987 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3988 else if (ins->dreg != ins->sreg1)
3989 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3992 case OP_ISHR_UN_IMM:
3994 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3995 else if (ins->dreg != ins->sreg1)
3996 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3999 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4002 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4005 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4008 if (ins->dreg == ins->sreg2)
4009 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4011 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4014 g_assert_not_reached ();
4017 /* FIXME: handle ovf/ sreg2 != dreg */
4018 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4019 /* FIXME: MUL doesn't set the C/O flags on ARM */
4021 case OP_IMUL_OVF_UN:
4022 /* FIXME: handle ovf/ sreg2 != dreg */
4023 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4024 /* FIXME: MUL doesn't set the C/O flags on ARM */
4027 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4030 /* Load the GOT offset */
4031 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4032 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4034 *(gpointer*)code = NULL;
4036 /* Load the value from the GOT */
4037 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4039 case OP_ICONV_TO_I4:
4040 case OP_ICONV_TO_U4:
4042 if (ins->dreg != ins->sreg1)
4043 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4046 int saved = ins->sreg2;
4047 if (ins->sreg2 == ARM_LSW_REG) {
4048 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4051 if (ins->sreg1 != ARM_LSW_REG)
4052 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4053 if (saved != ARM_MSW_REG)
4054 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4059 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4061 ARM_CPYD (code, ins->dreg, ins->sreg1);
4063 case OP_FCONV_TO_R4:
4065 ARM_FPA_MVFS (code, ins->dreg, ins->sreg1);
4067 ARM_CVTD (code, ins->dreg, ins->sreg1);
4068 ARM_CVTS (code, ins->dreg, ins->dreg);
4073 * Keep in sync with mono_arch_emit_epilog
4075 g_assert (!cfg->method->save_lmf);
4077 code = emit_load_volatile_arguments (cfg, code);
4079 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4081 if (cfg->used_int_regs)
4082 ARM_POP (code, cfg->used_int_regs);
4083 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4085 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4087 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4088 if (cfg->compile_aot) {
4089 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4091 *(gpointer*)code = NULL;
4093 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4099 /* ensure ins->sreg1 is not NULL */
4100 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4103 g_assert (cfg->sig_cookie < 128);
4104 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4105 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4114 call = (MonoCallInst*)ins;
4115 if (ins->flags & MONO_INST_HAS_METHOD)
4116 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4118 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4119 code = emit_call_seq (cfg, code);
4120 ins->flags |= MONO_INST_GC_CALLSITE;
4121 ins->backend.pc_offset = code - cfg->native_code;
4122 code = emit_move_return_value (cfg, ins, code);
4128 case OP_VOIDCALL_REG:
4130 code = emit_call_reg (code, ins->sreg1);
4131 ins->flags |= MONO_INST_GC_CALLSITE;
4132 ins->backend.pc_offset = code - cfg->native_code;
4133 code = emit_move_return_value (cfg, ins, code);
4135 case OP_FCALL_MEMBASE:
4136 case OP_LCALL_MEMBASE:
4137 case OP_VCALL_MEMBASE:
4138 case OP_VCALL2_MEMBASE:
4139 case OP_VOIDCALL_MEMBASE:
4140 case OP_CALL_MEMBASE:
4141 g_assert (arm_is_imm12 (ins->inst_offset));
4142 g_assert (ins->sreg1 != ARMREG_LR);
4143 call = (MonoCallInst*)ins;
4144 if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE) {
4145 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
4146 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4148 * We can't embed the method in the code stream in PIC code, or
4150 * Instead, we put it in V5 in code emitted by
4151 * mono_arch_emit_imt_argument (), and embed NULL here to
4152 * signal the IMT thunk that the value is in V5.
4154 if (call->dynamic_imt_arg)
4155 *((gpointer*)code) = NULL;
4157 *((gpointer*)code) = (gpointer)call->method;
4160 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4161 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4163 ins->flags |= MONO_INST_GC_CALLSITE;
4164 ins->backend.pc_offset = code - cfg->native_code;
4165 code = emit_move_return_value (cfg, ins, code);
4168 /* keep alignment */
4169 int alloca_waste = cfg->param_area;
4172 /* round the size to 8 bytes */
4173 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
4174 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
4176 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
4177 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
4178 /* memzero the area: dreg holds the size, sp is the pointer */
4179 if (ins->flags & MONO_INST_INIT) {
4180 guint8 *start_loop, *branch_to_cond;
4181 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
4182 branch_to_cond = code;
4185 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
4186 arm_patch (branch_to_cond, code);
4187 /* decrement by 4 and set flags */
4188 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
4189 ARM_B_COND (code, ARMCOND_GE, 0);
4190 arm_patch (code - 4, start_loop);
4192 ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
4197 MonoInst *var = cfg->dyn_call_var;
4199 g_assert (var->opcode == OP_REGOFFSET);
4200 g_assert (arm_is_imm12 (var->inst_offset));
4202 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
4203 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
4205 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
4207 /* Save args buffer */
4208 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4210 /* Set stack slots using R0 as scratch reg */
4211 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
4212 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4213 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
4214 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4217 /* Set argument registers */
4218 for (i = 0; i < PARAM_REGS; ++i)
4219 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
4222 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4223 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4226 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
4227 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
4228 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
4232 if (ins->sreg1 != ARMREG_R0)
4233 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4234 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4235 (gpointer)"mono_arch_throw_exception");
4236 code = emit_call_seq (cfg, code);
4240 if (ins->sreg1 != ARMREG_R0)
4241 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4242 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4243 (gpointer)"mono_arch_rethrow_exception");
4244 code = emit_call_seq (cfg, code);
4247 case OP_START_HANDLER: {
4248 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4251 /* Reserve a param area, see filter-stack.exe */
4252 if (cfg->param_area) {
4253 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4254 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4256 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4257 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4261 if (arm_is_imm12 (spvar->inst_offset)) {
4262 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4264 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4265 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
4269 case OP_ENDFILTER: {
4270 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4273 /* Free the param area */
4274 if (cfg->param_area) {
4275 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4276 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4278 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4279 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4283 if (ins->sreg1 != ARMREG_R0)
4284 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4285 if (arm_is_imm12 (spvar->inst_offset)) {
4286 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4288 g_assert (ARMREG_IP != spvar->inst_basereg);
4289 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4290 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4292 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4295 case OP_ENDFINALLY: {
4296 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4299 /* Free the param area */
4300 if (cfg->param_area) {
4301 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4302 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4304 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4305 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4309 if (arm_is_imm12 (spvar->inst_offset)) {
4310 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4312 g_assert (ARMREG_IP != spvar->inst_basereg);
4313 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4314 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4316 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4319 case OP_CALL_HANDLER:
4320 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4322 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4325 ins->inst_c0 = code - cfg->native_code;
4328 /*if (ins->inst_target_bb->native_offset) {
4330 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4332 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4337 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
4341 * In the normal case we have:
4342 * ldr pc, [pc, ins->sreg1 << 2]
4345 * ldr lr, [pc, ins->sreg1 << 2]
4347 * After follows the data.
4348 * FIXME: add aot support.
4350 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
4351 max_len += 4 * GPOINTER_TO_INT (ins->klass);
4352 if (offset + max_len > (cfg->code_size - 16)) {
4353 cfg->code_size += max_len;
4354 cfg->code_size *= 2;
4355 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4356 code = cfg->native_code + offset;
4358 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
4360 code += 4 * GPOINTER_TO_INT (ins->klass);
4364 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4365 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4369 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4370 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
4374 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4375 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
4379 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4380 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
4384 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4385 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
4387 case OP_COND_EXC_EQ:
4388 case OP_COND_EXC_NE_UN:
4389 case OP_COND_EXC_LT:
4390 case OP_COND_EXC_LT_UN:
4391 case OP_COND_EXC_GT:
4392 case OP_COND_EXC_GT_UN:
4393 case OP_COND_EXC_GE:
4394 case OP_COND_EXC_GE_UN:
4395 case OP_COND_EXC_LE:
4396 case OP_COND_EXC_LE_UN:
4397 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
4399 case OP_COND_EXC_IEQ:
4400 case OP_COND_EXC_INE_UN:
4401 case OP_COND_EXC_ILT:
4402 case OP_COND_EXC_ILT_UN:
4403 case OP_COND_EXC_IGT:
4404 case OP_COND_EXC_IGT_UN:
4405 case OP_COND_EXC_IGE:
4406 case OP_COND_EXC_IGE_UN:
4407 case OP_COND_EXC_ILE:
4408 case OP_COND_EXC_ILE_UN:
4409 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4412 case OP_COND_EXC_IC:
4413 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4415 case OP_COND_EXC_OV:
4416 case OP_COND_EXC_IOV:
4417 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4419 case OP_COND_EXC_NC:
4420 case OP_COND_EXC_INC:
4421 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4423 case OP_COND_EXC_NO:
4424 case OP_COND_EXC_INO:
4425 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4437 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4440 /* floating point opcodes */
4443 if (cfg->compile_aot) {
4444 ARM_FPA_LDFD (code, ins->dreg, ARMREG_PC, 0);
4446 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4448 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4451 /* FIXME: we can optimize the imm load by dealing with part of
4452 * the displacement in LDFD (aligning to 512).
4454 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4455 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4459 if (cfg->compile_aot) {
4460 ARM_FPA_LDFS (code, ins->dreg, ARMREG_PC, 0);
4462 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4465 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4466 ARM_FPA_LDFS (code, ins->dreg, ARMREG_LR, 0);
4469 case OP_STORER8_MEMBASE_REG:
4470 /* This is generated by the local regalloc pass which runs after the lowering pass */
4471 if (!arm_is_fpimm8 (ins->inst_offset)) {
4472 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4473 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4474 ARM_FPA_STFD (code, ins->sreg1, ARMREG_LR, 0);
4476 ARM_FPA_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4479 case OP_LOADR8_MEMBASE:
4480 /* This is generated by the local regalloc pass which runs after the lowering pass */
4481 if (!arm_is_fpimm8 (ins->inst_offset)) {
4482 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4483 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4484 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4486 ARM_FPA_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4489 case OP_STORER4_MEMBASE_REG:
4490 g_assert (arm_is_fpimm8 (ins->inst_offset));
4491 ARM_FPA_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4493 case OP_LOADR4_MEMBASE:
4494 g_assert (arm_is_fpimm8 (ins->inst_offset));
4495 ARM_FPA_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4497 case OP_ICONV_TO_R_UN: {
4499 tmpreg = ins->dreg == 0? 1: 0;
4500 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4501 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4502 ARM_B_COND (code, ARMCOND_GE, 8);
4503 /* save the temp register */
4504 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4505 ARM_FPA_STFD (code, tmpreg, ARMREG_SP, 0);
4506 ARM_FPA_LDFD (code, tmpreg, ARMREG_PC, 12);
4507 ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4508 ARM_FPA_LDFD (code, tmpreg, ARMREG_SP, 0);
4509 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4510 /* skip the constant pool */
4513 *(int*)code = 0x41f00000;
4518 * ldfltd ftemp, [pc, #8] 0x41f00000 0x00000000
4519 * adfltd fdest, fdest, ftemp
4523 case OP_ICONV_TO_R4:
4524 ARM_FPA_FLTS (code, ins->dreg, ins->sreg1);
4526 case OP_ICONV_TO_R8:
4527 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4530 #elif defined(ARM_FPU_VFP)
4533 if (cfg->compile_aot) {
4534 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4536 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4538 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4541 /* FIXME: we can optimize the imm load by dealing with part of
4542 * the displacement in LDFD (aligning to 512).
4544 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4545 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4549 if (cfg->compile_aot) {
4550 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4552 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4554 ARM_CVTS (code, ins->dreg, ins->dreg);
4556 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4557 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4558 ARM_CVTS (code, ins->dreg, ins->dreg);
4561 case OP_STORER8_MEMBASE_REG:
4562 /* This is generated by the local regalloc pass which runs after the lowering pass */
4563 if (!arm_is_fpimm8 (ins->inst_offset)) {
4564 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4565 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4566 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4568 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4571 case OP_LOADR8_MEMBASE:
4572 /* This is generated by the local regalloc pass which runs after the lowering pass */
4573 if (!arm_is_fpimm8 (ins->inst_offset)) {
4574 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4575 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4576 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4578 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4581 case OP_STORER4_MEMBASE_REG:
4582 g_assert (arm_is_fpimm8 (ins->inst_offset));
4583 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4584 ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4586 case OP_LOADR4_MEMBASE:
4587 g_assert (arm_is_fpimm8 (ins->inst_offset));
4588 ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4589 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4591 case OP_ICONV_TO_R_UN: {
4592 g_assert_not_reached ();
4595 case OP_ICONV_TO_R4:
4596 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4597 ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4598 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4600 case OP_ICONV_TO_R8:
4601 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4602 ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4606 if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4607 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4608 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4610 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4616 case OP_FCONV_TO_I1:
4617 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4619 case OP_FCONV_TO_U1:
4620 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4622 case OP_FCONV_TO_I2:
4623 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4625 case OP_FCONV_TO_U2:
4626 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4628 case OP_FCONV_TO_I4:
4630 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4632 case OP_FCONV_TO_U4:
4634 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4636 case OP_FCONV_TO_I8:
4637 case OP_FCONV_TO_U8:
4638 g_assert_not_reached ();
4639 /* Implemented as helper calls */
4641 case OP_LCONV_TO_R_UN:
4642 g_assert_not_reached ();
4643 /* Implemented as helper calls */
4645 case OP_LCONV_TO_OVF_I4_2: {
4646 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4648 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4651 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4652 high_bit_not_set = code;
4653 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4655 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4656 valid_negative = code;
4657 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4658 invalid_negative = code;
4659 ARM_B_COND (code, ARMCOND_AL, 0);
4661 arm_patch (high_bit_not_set, code);
4663 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4664 valid_positive = code;
4665 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4667 arm_patch (invalid_negative, code);
4668 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4670 arm_patch (valid_negative, code);
4671 arm_patch (valid_positive, code);
4673 if (ins->dreg != ins->sreg1)
4674 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4679 ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4682 ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4685 ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4688 ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4691 ARM_FPA_MNFD (code, ins->dreg, ins->sreg1);
4693 #elif defined(ARM_FPU_VFP)
4695 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4698 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4701 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4704 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4707 ARM_NEGD (code, ins->dreg, ins->sreg1);
4712 g_assert_not_reached ();
4716 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4717 } else if (IS_VFP) {
4718 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4724 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4725 } else if (IS_VFP) {
4726 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4729 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4730 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4734 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4736 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4739 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4740 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4744 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4745 } else if (IS_VFP) {
4746 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4749 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4750 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4751 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4756 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4757 } else if (IS_VFP) {
4758 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4761 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4762 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4767 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4768 } else if (IS_VFP) {
4769 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4772 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4773 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4774 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4776 /* ARM FPA flags table:
4777 * N Less than ARMCOND_MI
4778 * Z Equal ARMCOND_EQ
4779 * C Greater Than or Equal ARMCOND_CS
4780 * V Unordered ARMCOND_VS
4783 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4786 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4789 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4792 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4793 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4799 g_assert_not_reached ();
4803 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4805 /* FPA requires EQ even thou the docs suggests that just CS is enough */
4806 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4807 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4811 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4812 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4817 if (ins->dreg != ins->sreg1)
4818 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4819 } else if (IS_VFP) {
4820 ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4821 ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4823 *(guint32*)code = 0xffffffff;
4825 *(guint32*)code = 0x7fefffff;
4827 ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4829 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4830 ARM_CMPD (code, ins->sreg1, ins->sreg1);
4832 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4833 ARM_CPYD (code, ins->dreg, ins->sreg1);
4838 case OP_GC_LIVENESS_DEF:
4839 case OP_GC_LIVENESS_USE:
4840 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4841 ins->backend.pc_offset = code - cfg->native_code;
4843 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4844 ins->backend.pc_offset = code - cfg->native_code;
4845 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4849 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4850 g_assert_not_reached ();
4853 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4854 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4855 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4856 g_assert_not_reached ();
4862 last_offset = offset;
4865 cfg->code_len = code - cfg->native_code;
4868 #endif /* DISABLE_JIT */
4870 #ifdef HAVE_AEABI_READ_TP
4871 void __aeabi_read_tp (void);
4875 mono_arch_register_lowlevel_calls (void)
4877 /* The signature doesn't matter */
4878 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4879 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4881 #ifndef MONO_CROSS_COMPILE
4882 #ifdef HAVE_AEABI_READ_TP
4883 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4888 #define patch_lis_ori(ip,val) do {\
4889 guint16 *__lis_ori = (guint16*)(ip); \
4890 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
4891 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
4895 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4897 MonoJumpInfo *patch_info;
4898 gboolean compile_aot = !run_cctors;
4900 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4901 unsigned char *ip = patch_info->ip.i + code;
4902 const unsigned char *target;
4904 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4905 gpointer *jt = (gpointer*)(ip + 8);
4907 /* jt is the inlined jump table, 2 instructions after ip
4908 * In the normal case we store the absolute addresses,
4909 * otherwise the displacements.
4911 for (i = 0; i < patch_info->data.table->table_size; i++)
4912 jt [i] = code + (int)patch_info->data.table->table [i];
4915 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4918 switch (patch_info->type) {
4919 case MONO_PATCH_INFO_BB:
4920 case MONO_PATCH_INFO_LABEL:
4923 /* No need to patch these */
4928 switch (patch_info->type) {
4929 case MONO_PATCH_INFO_IP:
4930 g_assert_not_reached ();
4931 patch_lis_ori (ip, ip);
4933 case MONO_PATCH_INFO_METHOD_REL:
4934 g_assert_not_reached ();
4935 *((gpointer *)(ip)) = code + patch_info->data.offset;
4937 case MONO_PATCH_INFO_METHODCONST:
4938 case MONO_PATCH_INFO_CLASS:
4939 case MONO_PATCH_INFO_IMAGE:
4940 case MONO_PATCH_INFO_FIELD:
4941 case MONO_PATCH_INFO_VTABLE:
4942 case MONO_PATCH_INFO_IID:
4943 case MONO_PATCH_INFO_SFLDA:
4944 case MONO_PATCH_INFO_LDSTR:
4945 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4946 case MONO_PATCH_INFO_LDTOKEN:
4947 g_assert_not_reached ();
4948 /* from OP_AOTCONST : lis + ori */
4949 patch_lis_ori (ip, target);
4951 case MONO_PATCH_INFO_R4:
4952 case MONO_PATCH_INFO_R8:
4953 g_assert_not_reached ();
4954 *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4956 case MONO_PATCH_INFO_EXC_NAME:
4957 g_assert_not_reached ();
4958 *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4960 case MONO_PATCH_INFO_NONE:
4961 case MONO_PATCH_INFO_BB_OVF:
4962 case MONO_PATCH_INFO_EXC_OVF:
4963 /* everything is dealt with at epilog output time */
4968 arm_patch_general (domain, ip, target, dyn_code_mp);
4975 * Stack frame layout:
4977 * ------------------- fp
4978 * MonoLMF structure or saved registers
4979 * -------------------
4981 * -------------------
4983 * -------------------
4984 * optional 8 bytes for tracing
4985 * -------------------
4986 * param area size is cfg->param_area
4987 * ------------------- sp
4990 mono_arch_emit_prolog (MonoCompile *cfg)
4992 MonoMethod *method = cfg->method;
4994 MonoMethodSignature *sig;
4996 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount;
5001 int prev_sp_offset, reg_offset;
5003 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5006 sig = mono_method_signature (method);
5007 cfg->code_size = 256 + sig->param_count * 64;
5008 code = cfg->native_code = g_malloc (cfg->code_size);
5010 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
5012 alloc_size = cfg->stack_offset;
5016 if (!method->save_lmf) {
5019 * The iphone uses R7 as the frame pointer, and it points at the saved
5024 * We can't use r7 as a frame pointer since it points into the middle of
5025 * the frame, so we keep using our own frame pointer.
5026 * FIXME: Optimize this.
5029 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5030 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
5031 prev_sp_offset += 8; /* r7 and lr */
5032 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5033 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
5035 /* No need to push LR again */
5036 if (cfg->used_int_regs)
5037 ARM_PUSH (code, cfg->used_int_regs);
5039 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
5040 prev_sp_offset += 4;
5042 for (i = 0; i < 16; ++i) {
5043 if (cfg->used_int_regs & (1 << i))
5044 prev_sp_offset += 4;
5046 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5048 for (i = 0; i < 16; ++i) {
5049 if ((cfg->used_int_regs & (1 << i))) {
5050 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5051 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
5056 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5057 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5059 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5060 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5063 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
5064 ARM_PUSH (code, 0x5ff0);
5065 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
5066 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5068 for (i = 0; i < 16; ++i) {
5069 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
5070 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5074 pos += sizeof (MonoLMF) - prev_sp_offset;
5078 orig_alloc_size = alloc_size;
5079 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
5080 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
5081 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
5082 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
5085 /* the stack used in the pushed regs */
5086 if (prev_sp_offset & 4)
5088 cfg->stack_usage = alloc_size;
5090 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
5091 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5093 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
5094 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5096 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
5098 if (cfg->frame_reg != ARMREG_SP) {
5099 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
5100 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
5102 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
5103 prev_sp_offset += alloc_size;
5105 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
5106 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
5108 /* compute max_offset in order to use short forward jumps
5109 * we could skip do it on arm because the immediate displacement
5110 * for jumps is large enough, it may be useful later for constant pools
5113 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5114 MonoInst *ins = bb->code;
5115 bb->max_offset = max_offset;
5117 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5120 MONO_BB_FOR_EACH_INS (bb, ins)
5121 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5124 /* store runtime generic context */
5125 if (cfg->rgctx_var) {
5126 MonoInst *ins = cfg->rgctx_var;
5128 g_assert (ins->opcode == OP_REGOFFSET);
5130 if (arm_is_imm12 (ins->inst_offset)) {
5131 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
5133 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5134 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
5138 /* load arguments allocated to register from the stack */
5141 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
5143 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
5144 ArgInfo *ainfo = &cinfo->ret;
5145 inst = cfg->vret_addr;
5146 g_assert (arm_is_imm12 (inst->inst_offset));
5147 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5150 if (sig->call_convention == MONO_CALL_VARARG) {
5151 ArgInfo *cookie = &cinfo->sig_cookie;
5153 /* Save the sig cookie address */
5154 g_assert (cookie->storage == RegTypeBase);
5156 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
5157 g_assert (arm_is_imm12 (cfg->sig_cookie));
5158 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
5159 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5162 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5163 ArgInfo *ainfo = cinfo->args + i;
5164 inst = cfg->args [pos];
5166 if (cfg->verbose_level > 2)
5167 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
5168 if (inst->opcode == OP_REGVAR) {
5169 if (ainfo->storage == RegTypeGeneral)
5170 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
5171 else if (ainfo->storage == RegTypeFP) {
5172 g_assert_not_reached ();
5173 } else if (ainfo->storage == RegTypeBase) {
5174 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5175 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5177 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5178 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
5181 g_assert_not_reached ();
5183 if (cfg->verbose_level > 2)
5184 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5186 /* the argument should be put on the stack: FIXME handle size != word */
5187 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
5188 switch (ainfo->size) {
5190 if (arm_is_imm12 (inst->inst_offset))
5191 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5193 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5194 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5198 if (arm_is_imm8 (inst->inst_offset)) {
5199 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5201 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5202 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5206 g_assert (arm_is_imm12 (inst->inst_offset));
5207 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5208 g_assert (arm_is_imm12 (inst->inst_offset + 4));
5209 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
5212 if (arm_is_imm12 (inst->inst_offset)) {
5213 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5215 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5216 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5220 } else if (ainfo->storage == RegTypeBaseGen) {
5221 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
5222 g_assert (arm_is_imm12 (inst->inst_offset));
5223 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5224 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5225 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
5226 } else if (ainfo->storage == RegTypeBase) {
5227 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5228 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5230 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
5231 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5234 switch (ainfo->size) {
5236 if (arm_is_imm8 (inst->inst_offset)) {
5237 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5239 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5240 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5244 if (arm_is_imm8 (inst->inst_offset)) {
5245 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5247 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5248 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5252 if (arm_is_imm12 (inst->inst_offset)) {
5253 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5255 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5256 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5258 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
5259 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
5261 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
5262 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5264 if (arm_is_imm12 (inst->inst_offset + 4)) {
5265 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5267 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5268 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5272 if (arm_is_imm12 (inst->inst_offset)) {
5273 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5275 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5276 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5280 } else if (ainfo->storage == RegTypeFP) {
5281 g_assert_not_reached ();
5282 } else if (ainfo->storage == RegTypeStructByVal) {
5283 int doffset = inst->inst_offset;
5287 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
5288 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
5289 if (arm_is_imm12 (doffset)) {
5290 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
5292 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
5293 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
5295 soffset += sizeof (gpointer);
5296 doffset += sizeof (gpointer);
5298 if (ainfo->vtsize) {
5299 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5300 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
5301 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
5303 } else if (ainfo->storage == RegTypeStructByAddr) {
5304 g_assert_not_reached ();
5305 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5306 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
5308 g_assert_not_reached ();
5313 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5314 if (cfg->compile_aot)
5315 /* AOT code is only used in the root domain */
5316 code = mono_arm_emit_load_imm (code, ARMREG_R0, 0);
5318 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->domain);
5319 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5320 (gpointer)"mono_jit_thread_attach");
5321 code = emit_call_seq (cfg, code);
5324 if (method->save_lmf)
5325 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
5328 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5330 if (cfg->arch.seq_point_info_var) {
5331 MonoInst *ins = cfg->arch.seq_point_info_var;
5333 /* Initialize the variable from a GOT slot */
5334 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
5335 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5337 *(gpointer*)code = NULL;
5339 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
5341 g_assert (ins->opcode == OP_REGOFFSET);
5343 if (arm_is_imm12 (ins->inst_offset)) {
5344 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5346 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5347 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5351 /* Initialize ss_trigger_page_var */
5352 if (!cfg->soft_breakpoints) {
5353 MonoInst *info_var = cfg->arch.seq_point_info_var;
5354 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
5355 int dreg = ARMREG_LR;
5358 g_assert (info_var->opcode == OP_REGOFFSET);
5359 g_assert (arm_is_imm12 (info_var->inst_offset));
5361 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
5362 /* Load the trigger page addr */
5363 ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
5364 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
5368 if (cfg->arch.seq_point_read_var) {
5369 MonoInst *read_ins = cfg->arch.seq_point_read_var;
5370 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
5371 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
5373 g_assert (read_ins->opcode == OP_REGOFFSET);
5374 g_assert (arm_is_imm12 (read_ins->inst_offset));
5375 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
5376 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
5377 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
5378 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
5380 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5382 *(volatile int **)code = &ss_trigger_var;
5384 *(gpointer*)code = single_step_func_wrapper;
5386 *(gpointer*)code = breakpoint_func_wrapper;
5389 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
5390 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
5391 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
5392 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
5393 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
5394 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
5397 cfg->code_len = code - cfg->native_code;
5398 g_assert (cfg->code_len < cfg->code_size);
5405 mono_arch_emit_epilog (MonoCompile *cfg)
5407 MonoMethod *method = cfg->method;
5408 int pos, i, rot_amount;
5409 int max_epilog_size = 16 + 20*4;
5413 if (cfg->method->save_lmf)
5414 max_epilog_size += 128;
5416 if (mono_jit_trace_calls != NULL)
5417 max_epilog_size += 50;
5419 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5420 max_epilog_size += 50;
5422 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5423 cfg->code_size *= 2;
5424 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5425 cfg->stat_code_reallocs++;
5429 * Keep in sync with OP_JMP
5431 code = cfg->native_code + cfg->code_len;
5433 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5434 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5438 /* Load returned vtypes into registers if needed */
5439 cinfo = cfg->arch.cinfo;
5440 if (cinfo->ret.storage == RegTypeStructByVal) {
5441 MonoInst *ins = cfg->ret;
5443 if (arm_is_imm12 (ins->inst_offset)) {
5444 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5446 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5447 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5451 if (method->save_lmf) {
5452 int lmf_offset, reg, sp_adj, regmask;
5453 /* all but r0-r3, sp and pc */
5454 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5457 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
5459 /* This points to r4 inside MonoLMF->iregs */
5460 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5462 regmask = 0x9ff0; /* restore lr to pc */
5463 /* Skip caller saved registers not used by the method */
5464 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5465 regmask &= ~(1 << reg);
5469 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5470 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
5472 ARM_POP (code, regmask);
5474 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5475 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5477 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5478 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5482 /* Restore saved gregs */
5483 if (cfg->used_int_regs)
5484 ARM_POP (code, cfg->used_int_regs);
5485 /* Restore saved r7, restore LR to PC */
5486 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5488 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5492 cfg->code_len = code - cfg->native_code;
5494 g_assert (cfg->code_len < cfg->code_size);
5498 /* remove once throw_exception_by_name is eliminated */
5500 exception_id_by_name (const char *name)
5502 if (strcmp (name, "IndexOutOfRangeException") == 0)
5503 return MONO_EXC_INDEX_OUT_OF_RANGE;
5504 if (strcmp (name, "OverflowException") == 0)
5505 return MONO_EXC_OVERFLOW;
5506 if (strcmp (name, "ArithmeticException") == 0)
5507 return MONO_EXC_ARITHMETIC;
5508 if (strcmp (name, "DivideByZeroException") == 0)
5509 return MONO_EXC_DIVIDE_BY_ZERO;
5510 if (strcmp (name, "InvalidCastException") == 0)
5511 return MONO_EXC_INVALID_CAST;
5512 if (strcmp (name, "NullReferenceException") == 0)
5513 return MONO_EXC_NULL_REF;
5514 if (strcmp (name, "ArrayTypeMismatchException") == 0)
5515 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5516 if (strcmp (name, "ArgumentException") == 0)
5517 return MONO_EXC_ARGUMENT;
5518 g_error ("Unknown intrinsic exception %s\n", name);
5523 mono_arch_emit_exceptions (MonoCompile *cfg)
5525 MonoJumpInfo *patch_info;
5528 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5529 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5530 int max_epilog_size = 50;
5532 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5533 exc_throw_pos [i] = NULL;
5534 exc_throw_found [i] = 0;
5537 /* count the number of exception infos */
5540 * make sure we have enough space for exceptions
5542 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5543 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5544 i = exception_id_by_name (patch_info->data.target);
5545 if (!exc_throw_found [i]) {
5546 max_epilog_size += 32;
5547 exc_throw_found [i] = TRUE;
5552 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5553 cfg->code_size *= 2;
5554 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5555 cfg->stat_code_reallocs++;
5558 code = cfg->native_code + cfg->code_len;
5560 /* add code to raise exceptions */
5561 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5562 switch (patch_info->type) {
5563 case MONO_PATCH_INFO_EXC: {
5564 MonoClass *exc_class;
5565 unsigned char *ip = patch_info->ip.i + cfg->native_code;
5567 i = exception_id_by_name (patch_info->data.target);
5568 if (exc_throw_pos [i]) {
5569 arm_patch (ip, exc_throw_pos [i]);
5570 patch_info->type = MONO_PATCH_INFO_NONE;
5573 exc_throw_pos [i] = code;
5575 arm_patch (ip, code);
5577 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5578 g_assert (exc_class);
5580 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5581 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5582 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5583 patch_info->data.name = "mono_arch_throw_corlib_exception";
5584 patch_info->ip.i = code - cfg->native_code;
5586 *(guint32*)(gpointer)code = exc_class->type_token;
5596 cfg->code_len = code - cfg->native_code;
5598 g_assert (cfg->code_len < cfg->code_size);
5602 #endif /* #ifndef DISABLE_JIT */
5604 static gboolean tls_offset_inited = FALSE;
5607 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5609 if (!tls_offset_inited) {
5610 tls_offset_inited = TRUE;
5612 lmf_tls_offset = mono_get_lmf_tls_offset ();
5613 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5618 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5623 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5630 mono_arch_print_tree (MonoInst *tree, int arity)
5636 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5638 return mono_get_domain_intrinsic (cfg);
5642 mono_arch_get_patch_offset (guint8 *code)
5649 mono_arch_flush_register_windows (void)
5653 #ifdef MONO_ARCH_HAVE_IMT
5658 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5660 if (cfg->compile_aot) {
5661 int method_reg = mono_alloc_ireg (cfg);
5664 call->dynamic_imt_arg = TRUE;
5667 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5669 MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5670 ins->dreg = method_reg;
5671 ins->inst_p0 = call->method;
5672 ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5673 MONO_ADD_INS (cfg->cbb, ins);
5675 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5677 } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5679 /* Always pass in a register for simplicity */
5680 call->dynamic_imt_arg = TRUE;
5682 cfg->uses_rgctx_reg = TRUE;
5685 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5688 int method_reg = mono_alloc_preg (cfg);
5690 MONO_INST_NEW (cfg, ins, OP_PCONST);
5691 ins->inst_p0 = call->method;
5692 ins->dreg = method_reg;
5693 MONO_ADD_INS (cfg->cbb, ins);
5695 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5700 #endif /* DISABLE_JIT */
5703 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5705 guint32 *code_ptr = (guint32*)code;
5710 return (MonoMethod*)regs [ARMREG_V5];
5712 /* The IMT value is stored in the code stream right after the LDC instruction. */
5713 if (!IS_LDR_PC (code_ptr [0])) {
5714 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5715 g_assert (IS_LDR_PC (code_ptr [0]));
5717 if (code_ptr [1] == 0)
5718 /* This is AOTed code, the IMT method is in V5 */
5719 return (MonoMethod*)regs [ARMREG_V5];
5721 return (MonoMethod*) code_ptr [1];
5725 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5727 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5730 #define ENABLE_WRONG_METHOD_CHECK 0
5731 #define BASE_SIZE (6 * 4)
5732 #define BSEARCH_ENTRY_SIZE (4 * 4)
5733 #define CMP_SIZE (3 * 4)
5734 #define BRANCH_SIZE (1 * 4)
5735 #define CALL_SIZE (2 * 4)
5736 #define WMC_SIZE (5 * 4)
5737 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5740 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5742 guint32 delta = DISTANCE (target, code);
5744 g_assert (delta >= 0 && delta <= 0xFFF);
5745 *target = *target | delta;
5751 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5752 gpointer fail_tramp)
5754 int size, i, extra_space = 0;
5755 arminstr_t *code, *start, *vtable_target = NULL;
5756 gboolean large_offsets = FALSE;
5757 guint32 **constant_pool_starts;
5760 constant_pool_starts = g_new0 (guint32*, count);
5762 for (i = 0; i < count; ++i) {
5763 MonoIMTCheckItem *item = imt_entries [i];
5764 if (item->is_equals) {
5765 gboolean fail_case = !item->check_target_idx && fail_tramp;
5767 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5768 item->chunk_size += 32;
5769 large_offsets = TRUE;
5772 if (item->check_target_idx || fail_case) {
5773 if (!item->compare_done || fail_case)
5774 item->chunk_size += CMP_SIZE;
5775 item->chunk_size += BRANCH_SIZE;
5777 #if ENABLE_WRONG_METHOD_CHECK
5778 item->chunk_size += WMC_SIZE;
5782 item->chunk_size += 16;
5783 large_offsets = TRUE;
5785 item->chunk_size += CALL_SIZE;
5787 item->chunk_size += BSEARCH_ENTRY_SIZE;
5788 imt_entries [item->check_target_idx]->compare_done = TRUE;
5790 size += item->chunk_size;
5794 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5797 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5799 code = mono_domain_code_reserve (domain, size);
5803 printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5804 for (i = 0; i < count; ++i) {
5805 MonoIMTCheckItem *item = imt_entries [i];
5806 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5811 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5813 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5814 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5815 vtable_target = code;
5816 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5818 if (mono_use_llvm) {
5819 /* LLVM always passes the IMT method in R5 */
5820 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5822 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5823 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5824 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5827 for (i = 0; i < count; ++i) {
5828 MonoIMTCheckItem *item = imt_entries [i];
5829 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5830 gint32 vtable_offset;
5832 item->code_target = (guint8*)code;
5834 if (item->is_equals) {
5835 gboolean fail_case = !item->check_target_idx && fail_tramp;
5837 if (item->check_target_idx || fail_case) {
5838 if (!item->compare_done || fail_case) {
5840 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5841 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5843 item->jmp_code = (guint8*)code;
5844 ARM_B_COND (code, ARMCOND_NE, 0);
5846 /*Enable the commented code to assert on wrong method*/
5847 #if ENABLE_WRONG_METHOD_CHECK
5849 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5850 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5851 ARM_B_COND (code, ARMCOND_NE, 1);
5857 if (item->has_target_code) {
5858 target_code_ins = code;
5859 /* Load target address */
5860 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5861 /* Save it to the fourth slot */
5862 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5863 /* Restore registers and branch */
5864 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5866 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5868 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5869 if (!arm_is_imm12 (vtable_offset)) {
5871 * We need to branch to a computed address but we don't have
5872 * a free register to store it, since IP must contain the
5873 * vtable address. So we push the two values to the stack, and
5874 * load them both using LDM.
5876 /* Compute target address */
5877 vtable_offset_ins = code;
5878 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5879 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5880 /* Save it to the fourth slot */
5881 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5882 /* Restore registers and branch */
5883 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5885 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5887 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5889 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5890 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5895 arm_patch (item->jmp_code, (guchar*)code);
5897 target_code_ins = code;
5898 /* Load target address */
5899 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5900 /* Save it to the fourth slot */
5901 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5902 /* Restore registers and branch */
5903 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5905 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5906 item->jmp_code = NULL;
5910 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5912 /*must emit after unconditional branch*/
5913 if (vtable_target) {
5914 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5915 item->chunk_size += 4;
5916 vtable_target = NULL;
5919 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5920 constant_pool_starts [i] = code;
5922 code += extra_space;
5926 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5927 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5929 item->jmp_code = (guint8*)code;
5930 ARM_B_COND (code, ARMCOND_GE, 0);
5935 for (i = 0; i < count; ++i) {
5936 MonoIMTCheckItem *item = imt_entries [i];
5937 if (item->jmp_code) {
5938 if (item->check_target_idx)
5939 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5941 if (i > 0 && item->is_equals) {
5943 arminstr_t *space_start = constant_pool_starts [i];
5944 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5945 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5952 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5953 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5958 g_free (constant_pool_starts);
5960 mono_arch_flush_icache ((guint8*)start, size);
5961 mono_stats.imt_thunks_size += code - start;
5963 g_assert (DISTANCE (start, code) <= size);
5970 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5972 if (reg == ARMREG_SP)
5975 return ctx->regs [reg];
5979 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
5981 if (reg == ARMREG_SP)
5984 ctx->regs [reg] = val;
5988 * mono_arch_get_trampolines:
5990 * Return a list of MonoTrampInfo structures describing arch specific trampolines
5994 mono_arch_get_trampolines (gboolean aot)
5996 return mono_arm_get_exception_trampolines (aot);
6000 * mono_arch_set_breakpoint:
6002 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6003 * The location should contain code emitted by OP_SEQ_POINT.
6006 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6009 guint32 native_offset = ip - (guint8*)ji->code_start;
6010 MonoDebugOptions *opt = mini_get_debug_options ();
6012 if (opt->soft_breakpoints) {
6013 g_assert (!ji->from_aot);
6015 ARM_BLX_REG (code, ARMREG_LR);
6016 mono_arch_flush_icache (code - 4, 4);
6017 } else if (ji->from_aot) {
6018 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6020 g_assert (native_offset % 4 == 0);
6021 g_assert (info->bp_addrs [native_offset / 4] == 0);
6022 info->bp_addrs [native_offset / 4] = bp_trigger_page;
6024 int dreg = ARMREG_LR;
6026 /* Read from another trigger page */
6027 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
6029 *(int*)code = (int)bp_trigger_page;
6031 ARM_LDR_IMM (code, dreg, dreg, 0);
6033 mono_arch_flush_icache (code - 16, 16);
6036 /* This is currently implemented by emitting an SWI instruction, which
6037 * qemu/linux seems to convert to a SIGILL.
6039 *(int*)code = (0xef << 24) | 8;
6041 mono_arch_flush_icache (code - 4, 4);
6047 * mono_arch_clear_breakpoint:
6049 * Clear the breakpoint at IP.
6052 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6054 MonoDebugOptions *opt = mini_get_debug_options ();
6058 if (opt->soft_breakpoints) {
6059 g_assert (!ji->from_aot);
6062 mono_arch_flush_icache (code - 4, 4);
6063 } else if (ji->from_aot) {
6064 guint32 native_offset = ip - (guint8*)ji->code_start;
6065 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6067 g_assert (native_offset % 4 == 0);
6068 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
6069 info->bp_addrs [native_offset / 4] = 0;
6071 for (i = 0; i < 4; ++i)
6074 mono_arch_flush_icache (ip, code - ip);
6079 * mono_arch_start_single_stepping:
6081 * Start single stepping.
6084 mono_arch_start_single_stepping (void)
6086 if (ss_trigger_page)
6087 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6093 * mono_arch_stop_single_stepping:
6095 * Stop single stepping.
6098 mono_arch_stop_single_stepping (void)
6100 if (ss_trigger_page)
6101 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6107 #define DBG_SIGNAL SIGBUS
6109 #define DBG_SIGNAL SIGSEGV
6113 * mono_arch_is_single_step_event:
6115 * Return whenever the machine state in SIGCTX corresponds to a single
6119 mono_arch_is_single_step_event (void *info, void *sigctx)
6121 siginfo_t *sinfo = info;
6123 if (!ss_trigger_page)
6126 /* Sometimes the address is off by 4 */
6127 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
6134 * mono_arch_is_breakpoint_event:
6136 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
6139 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6141 siginfo_t *sinfo = info;
6143 if (!ss_trigger_page)
6146 if (sinfo->si_signo == DBG_SIGNAL) {
6147 /* Sometimes the address is off by 4 */
6148 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
6158 * mono_arch_skip_breakpoint:
6160 * See mini-amd64.c for docs.
6163 mono_arch_skip_breakpoint (MonoContext *ctx)
6165 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6169 * mono_arch_skip_single_step:
6171 * See mini-amd64.c for docs.
6174 mono_arch_skip_single_step (MonoContext *ctx)
6176 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6180 * mono_arch_get_seq_point_info:
6182 * See mini-amd64.c for docs.
6185 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6190 // FIXME: Add a free function
6192 mono_domain_lock (domain);
6193 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
6195 mono_domain_unlock (domain);
6198 ji = mono_jit_info_table_find (domain, (char*)code);
6201 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
6203 info->ss_trigger_page = ss_trigger_page;
6204 info->bp_trigger_page = bp_trigger_page;
6206 mono_domain_lock (domain);
6207 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
6209 mono_domain_unlock (domain);
6216 * mono_arch_set_target:
6218 * Set the target architecture the JIT backend should generate code for, in the form
6219 * of a GNU target triplet. Only used in AOT mode.
6222 mono_arch_set_target (char *mtriple)
6224 /* The GNU target triple format is not very well documented */
6225 if (strstr (mtriple, "armv7")) {
6226 v6_supported = TRUE;
6227 v7_supported = TRUE;
6229 if (strstr (mtriple, "armv6")) {
6230 v6_supported = TRUE;
6232 if (strstr (mtriple, "darwin")) {
6233 v5_supported = TRUE;
6234 thumb_supported = TRUE;
6238 if (strstr (mtriple, "gnueabi"))
6239 eabi_supported = TRUE;