2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
24 #include "mini-arm-tls.h"
28 #include "debugger-agent.h"
30 #include "mono/arch/arm/arm-vfp-codegen.h"
32 #if defined(HAVE_KW_THREAD) && defined(__linux__) \
33 || defined(TARGET_ANDROID) \
34 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
38 /* Sanity check: This makes no sense */
39 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
40 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
44 * IS_SOFT_FLOAT: Is full software floating point used?
45 * IS_HARD_FLOAT: Is full hardware floating point used?
46 * IS_VFP: Is hardware floating point with software ABI used?
48 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
49 * IS_VFP may delegate to mono_arch_is_soft_float ().
52 #if defined(ARM_FPU_VFP_HARD)
53 #define IS_SOFT_FLOAT (FALSE)
54 #define IS_HARD_FLOAT (TRUE)
56 #elif defined(ARM_FPU_NONE)
57 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
58 #define IS_HARD_FLOAT (FALSE)
59 #define IS_VFP (!mono_arch_is_soft_float ())
61 #define IS_SOFT_FLOAT (FALSE)
62 #define IS_HARD_FLOAT (FALSE)
66 #define THUNK_SIZE (3 * 4)
68 #ifdef __native_client_codegen__
69 const guint kNaClAlignment = kNaClAlignmentARM;
70 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
71 gint8 nacl_align_byte = -1; /* 0xff */
74 mono_arch_nacl_pad (guint8 *code, int pad)
76 /* Not yet properly implemented. */
77 g_assert_not_reached ();
82 mono_arch_nacl_skip_nops (guint8 *code)
84 /* Not yet properly implemented. */
85 g_assert_not_reached ();
89 #endif /* __native_client_codegen__ */
91 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
94 void sys_icache_invalidate (void *start, size_t len);
97 /* This mutex protects architecture specific caches */
98 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
99 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
100 static mono_mutex_t mini_arch_mutex;
102 static gboolean v5_supported = FALSE;
103 static gboolean v6_supported = FALSE;
104 static gboolean v7_supported = FALSE;
105 static gboolean v7s_supported = FALSE;
106 static gboolean v7k_supported = FALSE;
107 static gboolean thumb_supported = FALSE;
108 static gboolean thumb2_supported = FALSE;
110 * Whenever to use the ARM EABI
112 static gboolean eabi_supported = FALSE;
115 * Whenever to use the iphone ABI extensions:
116 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
117 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
118 * This is required for debugging/profiling tools to work, but it has some overhead so it should
119 * only be turned on in debug builds.
121 static gboolean iphone_abi = FALSE;
124 * The FPU we are generating code for. This is NOT runtime configurable right now,
125 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
127 static MonoArmFPU arm_fpu;
129 #if defined(ARM_FPU_VFP_HARD)
131 * On armhf, d0-d7 are used for argument passing and d8-d15
132 * must be preserved across calls, which leaves us no room
133 * for scratch registers. So we use d14-d15 but back up their
134 * previous contents to a stack slot before using them - see
135 * mono_arm_emit_vfp_scratch_save/_restore ().
137 static int vfp_scratch1 = ARM_VFP_D14;
138 static int vfp_scratch2 = ARM_VFP_D15;
141 * On armel, d0-d7 do not need to be preserved, so we can
142 * freely make use of them as scratch registers.
144 static int vfp_scratch1 = ARM_VFP_D0;
145 static int vfp_scratch2 = ARM_VFP_D1;
150 static volatile int ss_trigger_var = 0;
152 static gpointer single_step_tramp, breakpoint_tramp;
155 * The code generated for sequence points reads from this location, which is
156 * made read-only when single stepping is enabled.
158 static gpointer ss_trigger_page;
160 /* Enabled breakpoints read from this trigger page */
161 static gpointer bp_trigger_page;
165 * floating point support: on ARM it is a mess, there are at least 3
166 * different setups, each of which binary incompat with the other.
167 * 1) FPA: old and ugly, but unfortunately what current distros use
168 * the double binary format has the two words swapped. 8 double registers.
169 * Implemented usually by kernel emulation.
170 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
171 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
172 * 3) VFP: the new and actually sensible and useful FP support. Implemented
173 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
175 * We do not care about FPA. We will support soft float and VFP.
177 int mono_exc_esp_offset = 0;
179 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
180 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
181 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
183 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
184 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
185 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
187 //#define DEBUG_IMT 0
190 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
194 mono_arch_regname (int reg)
196 static const char * rnames[] = {
197 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
198 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
199 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
202 if (reg >= 0 && reg < 16)
208 mono_arch_fregname (int reg)
210 static const char * rnames[] = {
211 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
212 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
213 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
214 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
215 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
216 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
219 if (reg >= 0 && reg < 32)
227 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
229 int imm8, rot_amount;
230 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
231 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
235 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
236 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
238 code = mono_arm_emit_load_imm (code, dreg, imm);
239 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
244 /* If dreg == sreg, this clobbers IP */
246 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
248 int imm8, rot_amount;
249 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
250 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
254 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
255 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
257 code = mono_arm_emit_load_imm (code, dreg, imm);
258 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
264 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
266 /* we can use r0-r3, since this is called only for incoming args on the stack */
267 if (size > sizeof (gpointer) * 4) {
269 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
270 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
271 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
272 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
273 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
274 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
275 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
276 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
277 ARM_B_COND (code, ARMCOND_NE, 0);
278 arm_patch (code - 4, start_loop);
281 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
282 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
284 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
285 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
291 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
292 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
293 doffset = soffset = 0;
295 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
296 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
302 g_assert (size == 0);
307 emit_call_reg (guint8 *code, int reg)
310 ARM_BLX_REG (code, reg);
312 #ifdef USE_JUMP_TABLES
313 g_assert_not_reached ();
315 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
319 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
325 emit_call_seq (MonoCompile *cfg, guint8 *code)
327 #ifdef USE_JUMP_TABLES
328 code = mono_arm_patchable_bl (code, ARMCOND_AL);
330 if (cfg->method->dynamic) {
331 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
333 *(gpointer*)code = NULL;
335 code = emit_call_reg (code, ARMREG_IP);
339 cfg->thunk_area += THUNK_SIZE;
345 mono_arm_patchable_b (guint8 *code, int cond)
347 #ifdef USE_JUMP_TABLES
350 jte = mono_jumptable_add_entry ();
351 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
352 ARM_BX_COND (code, cond, ARMREG_IP);
354 ARM_B_COND (code, cond, 0);
360 mono_arm_patchable_bl (guint8 *code, int cond)
362 #ifdef USE_JUMP_TABLES
365 jte = mono_jumptable_add_entry ();
366 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
367 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
369 ARM_BL_COND (code, cond, 0);
374 #ifdef USE_JUMP_TABLES
376 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
378 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
379 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
384 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
386 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
387 ARM_LDR_IMM (code, reg, reg, 0);
393 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
396 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
397 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
399 code = emit_call_seq (cfg, code);
400 if (dreg != ARMREG_R0)
401 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
403 g_assert_not_reached ();
409 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
412 if (tls_offset_reg != ARMREG_R0)
413 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
414 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
416 code = emit_call_seq (cfg, code);
417 if (dreg != ARMREG_R0)
418 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
420 g_assert_not_reached ();
426 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
429 if (sreg != ARMREG_R1)
430 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
431 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
432 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
434 code = emit_call_seq (cfg, code);
436 g_assert_not_reached ();
442 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
445 /* Get sreg in R1 and tls_offset_reg in R0 */
446 if (tls_offset_reg == ARMREG_R1) {
447 if (sreg == ARMREG_R0) {
448 /* swap sreg and tls_offset_reg */
449 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
450 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
451 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
453 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
454 if (sreg != ARMREG_R1)
455 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
458 if (sreg != ARMREG_R1)
459 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
460 if (tls_offset_reg != ARMREG_R0)
461 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
463 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
465 code = emit_call_seq (cfg, code);
467 g_assert_not_reached ();
475 * Emit code to push an LMF structure on the LMF stack.
476 * On arm, this is intermixed with the initialization of other fields of the structure.
479 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
481 gboolean get_lmf_fast = FALSE;
484 if (mono_arm_have_tls_get ()) {
486 if (cfg->compile_aot) {
488 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
489 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
491 *(gpointer*)code = NULL;
493 /* Load the value from the GOT */
494 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
495 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
497 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
498 g_assert (lmf_addr_tls_offset != -1);
499 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
504 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
505 (gpointer)"mono_get_lmf_addr");
506 code = emit_call_seq (cfg, code);
508 /* we build the MonoLMF structure on the stack - see mini-arm.h */
509 /* lmf_offset is the offset from the previous stack pointer,
510 * alloc_size is the total stack space allocated, so the offset
511 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
512 * The pointer to the struct is put in r1 (new_lmf).
513 * ip is used as scratch
514 * The callee-saved registers are already in the MonoLMF structure
516 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
517 /* r0 is the result from mono_get_lmf_addr () */
518 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
519 /* new_lmf->previous_lmf = *lmf_addr */
520 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
521 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
522 /* *(lmf_addr) = r1 */
523 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
524 /* Skip method (only needed for trampoline LMF frames) */
525 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
526 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
527 /* save the current IP */
528 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
529 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
531 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
532 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
543 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
547 g_assert (!cfg->r4fp);
549 for (list = inst->float_args; list; list = list->next) {
550 FloatArgData *fad = list->data;
551 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
552 gboolean imm = arm_is_fpimm8 (var->inst_offset);
554 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
560 if (*offset + *max_len > cfg->code_size) {
561 cfg->code_size += *max_len;
562 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
564 code = cfg->native_code + *offset;
568 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
569 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
571 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
573 *offset = code - cfg->native_code;
580 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
584 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
586 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
589 if (!arm_is_fpimm8 (inst->inst_offset)) {
590 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
591 ARM_FSTD (code, reg, ARMREG_LR, 0);
593 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
600 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
604 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
606 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
609 if (!arm_is_fpimm8 (inst->inst_offset)) {
610 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
611 ARM_FLDD (code, reg, ARMREG_LR, 0);
613 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
622 * Emit code to pop an LMF structure from the LMF stack.
625 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
629 if (lmf_offset < 32) {
630 basereg = cfg->frame_reg;
635 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
638 /* ip = previous_lmf */
639 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
641 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
642 /* *(lmf_addr) = previous_lmf */
643 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
648 #endif /* #ifndef DISABLE_JIT */
650 #ifndef MONO_CROSS_COMPILE
652 mono_arm_have_fast_tls (void)
654 if (mini_get_debug_options ()->arm_use_fallback_tls)
656 #if (defined(HAVE_KW_THREAD) && defined(__linux__)) \
657 || defined(TARGET_ANDROID)
658 guint32* kuser_get_tls = (void*)0xffff0fe0;
659 guint32 expected [] = {0xee1d0f70, 0xe12fff1e};
661 /* Expecting mrc + bx lr in the kuser_get_tls kernel helper */
662 return memcmp (kuser_get_tls, expected, 8) == 0;
663 #elif defined(TARGET_IOS)
664 guint32 expected [] = {0x1f70ee1d, 0x0103f021, 0x0020f851, 0xbf004770};
665 /* Discard thumb bit */
666 guint32* pthread_getspecific_addr = (guint32*) ((guint32)pthread_getspecific & 0xfffffffe);
667 return memcmp ((void*)pthread_getspecific_addr, expected, 16) == 0;
675 * mono_arm_have_tls_get:
677 * Returns whether we have tls access implemented on the current
681 mono_arm_have_tls_get (void)
691 * mono_arch_get_argument_info:
692 * @csig: a method signature
693 * @param_count: the number of parameters to consider
694 * @arg_info: an array to store the result infos
696 * Gathers information on parameters such as size, alignment and
697 * padding. arg_info should be large enought to hold param_count + 1 entries.
699 * Returns the size of the activation frame.
702 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
704 int k, frame_size = 0;
705 guint32 size, align, pad;
709 t = mini_get_underlying_type (csig->ret);
710 if (MONO_TYPE_ISSTRUCT (t)) {
711 frame_size += sizeof (gpointer);
715 arg_info [0].offset = offset;
718 frame_size += sizeof (gpointer);
722 arg_info [0].size = frame_size;
724 for (k = 0; k < param_count; k++) {
725 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
727 /* ignore alignment for now */
730 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
731 arg_info [k].pad = pad;
733 arg_info [k + 1].pad = 0;
734 arg_info [k + 1].size = size;
736 arg_info [k + 1].offset = offset;
740 align = MONO_ARCH_FRAME_ALIGNMENT;
741 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
742 arg_info [k].pad = pad;
747 #define MAX_ARCH_DELEGATE_PARAMS 3
750 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
752 guint8 *code, *start;
753 GSList *unwind_ops = mono_arch_get_cie_program ();
756 start = code = mono_global_codeman_reserve (12);
758 /* Replace the this argument with the target */
759 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
760 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
761 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
763 g_assert ((code - start) <= 12);
765 mono_arch_flush_icache (start, 12);
769 size = 8 + param_count * 4;
770 start = code = mono_global_codeman_reserve (size);
772 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
773 /* slide down the arguments */
774 for (i = 0; i < param_count; ++i) {
775 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
777 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
779 g_assert ((code - start) <= size);
781 mono_arch_flush_icache (start, size);
785 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
787 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
788 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
792 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
798 * mono_arch_get_delegate_invoke_impls:
800 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
804 mono_arch_get_delegate_invoke_impls (void)
810 get_delegate_invoke_impl (&info, TRUE, 0);
811 res = g_slist_prepend (res, info);
813 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
814 get_delegate_invoke_impl (&info, FALSE, i);
815 res = g_slist_prepend (res, info);
822 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
824 guint8 *code, *start;
827 /* FIXME: Support more cases */
828 sig_ret = mini_get_underlying_type (sig->ret);
829 if (MONO_TYPE_ISSTRUCT (sig_ret))
833 static guint8* cached = NULL;
834 mono_mini_arch_lock ();
836 mono_mini_arch_unlock ();
841 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
844 start = get_delegate_invoke_impl (&info, TRUE, 0);
845 mono_tramp_info_register (info, NULL);
848 mono_mini_arch_unlock ();
851 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
854 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
856 for (i = 0; i < sig->param_count; ++i)
857 if (!mono_is_regsize_var (sig->params [i]))
860 mono_mini_arch_lock ();
861 code = cache [sig->param_count];
863 mono_mini_arch_unlock ();
868 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
869 start = mono_aot_get_trampoline (name);
873 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
874 mono_tramp_info_register (info, NULL);
876 cache [sig->param_count] = start;
877 mono_mini_arch_unlock ();
885 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
891 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
893 return (gpointer)regs [ARMREG_R0];
897 * Initialize the cpu to execute managed code.
900 mono_arch_cpu_init (void)
902 i8_align = MONO_ABI_ALIGNOF (gint64);
903 #ifdef MONO_CROSS_COMPILE
904 /* Need to set the alignment of i8 since it can different on the target */
905 #ifdef TARGET_ANDROID
907 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
913 * Initialize architecture specific code.
916 mono_arch_init (void)
918 const char *cpu_arch;
920 mono_mutex_init_recursive (&mini_arch_mutex);
921 if (mini_get_debug_options ()->soft_breakpoints) {
922 single_step_tramp = mini_get_single_step_trampoline ();
923 breakpoint_tramp = mini_get_breakpoint_trampoline ();
925 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
926 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
927 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
930 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
931 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
932 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
933 #if defined(ENABLE_GSHAREDVT)
934 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
936 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
938 #if defined(__ARM_EABI__)
939 eabi_supported = TRUE;
942 #if defined(ARM_FPU_VFP_HARD)
943 arm_fpu = MONO_ARM_FPU_VFP_HARD;
945 arm_fpu = MONO_ARM_FPU_VFP;
947 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
949 * If we're compiling with a soft float fallback and it
950 * turns out that no VFP unit is available, we need to
951 * switch to soft float. We don't do this for iOS, since
952 * iOS devices always have a VFP unit.
954 if (!mono_hwcap_arm_has_vfp)
955 arm_fpu = MONO_ARM_FPU_NONE;
958 * This environment variable can be useful in testing
959 * environments to make sure the soft float fallback
960 * works. Most ARM devices have VFP units these days, so
961 * normally soft float code would not be exercised much.
963 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
965 if (soft && !strncmp (soft, "1", 1))
966 arm_fpu = MONO_ARM_FPU_NONE;
970 v5_supported = mono_hwcap_arm_is_v5;
971 v6_supported = mono_hwcap_arm_is_v6;
972 v7_supported = mono_hwcap_arm_is_v7;
974 #if defined(__APPLE__)
975 /* iOS is special-cased here because we don't yet
976 have a way to properly detect CPU features on it. */
977 thumb_supported = TRUE;
980 thumb_supported = mono_hwcap_arm_has_thumb;
981 thumb2_supported = mono_hwcap_arm_has_thumb2;
984 /* Format: armv(5|6|7[s])[-thumb[2]] */
985 cpu_arch = g_getenv ("MONO_CPU_ARCH");
987 /* Do this here so it overrides any detection. */
989 if (strncmp (cpu_arch, "armv", 4) == 0) {
990 v5_supported = cpu_arch [4] >= '5';
991 v6_supported = cpu_arch [4] >= '6';
992 v7_supported = cpu_arch [4] >= '7';
993 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
994 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
997 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
998 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
1003 * Cleanup architecture specific code.
1006 mono_arch_cleanup (void)
1011 * This function returns the optimizations supported on this cpu.
1014 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1016 /* no arm-specific optimizations yet */
1022 * This function test for all SIMD functions supported.
1024 * Returns a bitmask corresponding to all supported versions.
1028 mono_arch_cpu_enumerate_simd_versions (void)
1030 /* SIMD is currently unimplemented */
1038 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1040 if (v7s_supported || v7k_supported) {
1054 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1056 mono_arch_is_soft_float (void)
1058 return arm_fpu == MONO_ARM_FPU_NONE;
1063 mono_arm_is_hard_float (void)
1065 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1069 is_regsize_var (MonoType *t)
1073 t = mini_get_underlying_type (t);
1080 case MONO_TYPE_FNPTR:
1082 case MONO_TYPE_OBJECT:
1083 case MONO_TYPE_STRING:
1084 case MONO_TYPE_CLASS:
1085 case MONO_TYPE_SZARRAY:
1086 case MONO_TYPE_ARRAY:
1088 case MONO_TYPE_GENERICINST:
1089 if (!mono_type_generic_inst_is_valuetype (t))
1092 case MONO_TYPE_VALUETYPE:
1099 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1104 for (i = 0; i < cfg->num_varinfo; i++) {
1105 MonoInst *ins = cfg->varinfo [i];
1106 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1109 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1112 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1115 /* we can only allocate 32 bit values */
1116 if (is_regsize_var (ins->inst_vtype)) {
1117 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1118 g_assert (i == vmv->idx);
1119 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1127 mono_arch_get_global_int_regs (MonoCompile *cfg)
1131 mono_arch_compute_omit_fp (cfg);
1134 * FIXME: Interface calls might go through a static rgctx trampoline which
1135 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1138 if (cfg->flags & MONO_CFG_HAS_CALLS)
1139 cfg->uses_rgctx_reg = TRUE;
1141 if (cfg->arch.omit_fp)
1142 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1143 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1144 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1145 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1147 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1148 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1150 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1151 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1152 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1153 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1154 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1155 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1161 * mono_arch_regalloc_cost:
1163 * Return the cost, in number of memory references, of the action of
1164 * allocating the variable VMV into a register during global register
1168 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1174 #endif /* #ifndef DISABLE_JIT */
1176 #ifndef __GNUC_PREREQ
1177 #define __GNUC_PREREQ(maj, min) (0)
1181 mono_arch_flush_icache (guint8 *code, gint size)
1183 #if defined(__native_client__)
1184 // For Native Client we don't have to flush i-cache here,
1185 // as it's being done by dyncode interface.
1188 #ifdef MONO_CROSS_COMPILE
1190 sys_icache_invalidate (code, size);
1191 #elif __GNUC_PREREQ(4, 3)
1192 __builtin___clear_cache (code, code + size);
1193 #elif __GNUC_PREREQ(4, 1)
1194 __clear_cache (code, code + size);
1195 #elif defined(PLATFORM_ANDROID)
1196 const int syscall = 0xf0002;
1204 : "r" (code), "r" (code + size), "r" (syscall)
1205 : "r0", "r1", "r7", "r2"
1208 __asm __volatile ("mov r0, %0\n"
1211 "swi 0x9f0002 @ sys_cacheflush"
1213 : "r" (code), "r" (code + size), "r" (0)
1214 : "r0", "r1", "r3" );
1216 #endif /* !__native_client__ */
1221 /* Passed/returned in an ireg */
1223 /* Passed/returned in a pair of iregs */
1225 /* Passed on the stack */
1227 /* First word in r3, second word on the stack */
1229 /* FP value passed in either an ireg or a vfp reg */
1232 RegTypeStructByAddr,
1233 /* gsharedvt argument passed by addr in greg */
1234 RegTypeGSharedVtInReg,
1235 /* gsharedvt argument passed by addr on stack */
1236 RegTypeGSharedVtOnStack,
1242 guint16 vtsize; /* in param area */
1250 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1255 guint32 stack_usage;
1256 /* The index of the vret arg in the argument list for RegTypeStructByAddr */
1266 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1269 if (*gr > ARMREG_R3) {
1271 ainfo->offset = *stack_size;
1272 ainfo->reg = ARMREG_SP; /* in the caller */
1273 ainfo->storage = RegTypeBase;
1276 ainfo->storage = RegTypeGeneral;
1283 split = i8_align == 4;
1288 if (*gr == ARMREG_R3 && split) {
1289 /* first word in r3 and the second on the stack */
1290 ainfo->offset = *stack_size;
1291 ainfo->reg = ARMREG_SP; /* in the caller */
1292 ainfo->storage = RegTypeBaseGen;
1294 } else if (*gr >= ARMREG_R3) {
1295 if (eabi_supported) {
1296 /* darwin aligns longs to 4 byte only */
1297 if (i8_align == 8) {
1302 ainfo->offset = *stack_size;
1303 ainfo->reg = ARMREG_SP; /* in the caller */
1304 ainfo->storage = RegTypeBase;
1307 if (eabi_supported) {
1308 if (i8_align == 8 && ((*gr) & 1))
1311 ainfo->storage = RegTypeIRegPair;
1320 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1323 * If we're calling a function like this:
1325 * void foo(float a, double b, float c)
1327 * We pass a in s0 and b in d1. That leaves us
1328 * with s1 being unused. The armhf ABI recognizes
1329 * this and requires register assignment to then
1330 * use that for the next single-precision arg,
1331 * i.e. c in this example. So float_spare either
1332 * tells us which reg to use for the next single-
1333 * precision arg, or it's -1, meaning use *fpr.
1335 * Note that even though most of the JIT speaks
1336 * double-precision, fpr represents single-
1337 * precision registers.
1339 * See parts 5.5 and 6.1.2 of the AAPCS for how
1343 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1344 ainfo->storage = RegTypeFP;
1348 * If we're passing a double-precision value
1349 * and *fpr is odd (e.g. it's s1, s3, ...)
1350 * we need to use the next even register. So
1351 * we mark the current *fpr as a spare that
1352 * can be used for the next single-precision
1356 *float_spare = *fpr;
1361 * At this point, we have an even register
1362 * so we assign that and move along.
1366 } else if (*float_spare >= 0) {
1368 * We're passing a single-precision value
1369 * and it looks like a spare single-
1370 * precision register is available. Let's
1374 ainfo->reg = *float_spare;
1378 * If we hit this branch, we're passing a
1379 * single-precision value and we can simply
1380 * use the next available register.
1388 * We've exhausted available floating point
1389 * regs, so pass the rest on the stack.
1397 ainfo->offset = *stack_size;
1398 ainfo->reg = ARMREG_SP;
1399 ainfo->storage = RegTypeBase;
1406 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1410 MonoClassField *field;
1411 MonoType *ftype, *prev_ftype = NULL;
1414 klass = mono_class_from_mono_type (t);
1416 while ((field = mono_class_get_fields (klass, &iter))) {
1417 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1419 ftype = mono_field_get_type (field);
1420 ftype = mini_get_underlying_type (ftype);
1422 if (MONO_TYPE_ISSTRUCT (ftype)) {
1423 int nested_nfields, nested_esize;
1425 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1427 if (nested_esize == 4)
1428 ftype = &mono_defaults.single_class->byval_arg;
1430 ftype = &mono_defaults.double_class->byval_arg;
1431 if (prev_ftype && prev_ftype->type != ftype->type)
1434 nfields += nested_nfields;
1436 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1438 if (prev_ftype && prev_ftype->type != ftype->type)
1444 if (nfields == 0 || nfields > 4)
1446 *out_nfields = nfields;
1447 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1452 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1454 guint i, gr, fpr, pstart;
1456 int n = sig->hasthis + sig->param_count;
1460 guint32 stack_size = 0;
1462 gboolean is_pinvoke = sig->pinvoke;
1463 gboolean vtype_retaddr = FALSE;
1466 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1468 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1475 t = mini_get_underlying_type (sig->ret);
1486 case MONO_TYPE_FNPTR:
1487 case MONO_TYPE_CLASS:
1488 case MONO_TYPE_OBJECT:
1489 case MONO_TYPE_SZARRAY:
1490 case MONO_TYPE_ARRAY:
1491 case MONO_TYPE_STRING:
1492 cinfo->ret.storage = RegTypeGeneral;
1493 cinfo->ret.reg = ARMREG_R0;
1497 cinfo->ret.storage = RegTypeIRegPair;
1498 cinfo->ret.reg = ARMREG_R0;
1502 cinfo->ret.storage = RegTypeFP;
1504 if (t->type == MONO_TYPE_R4)
1505 cinfo->ret.size = 4;
1507 cinfo->ret.size = 8;
1509 if (IS_HARD_FLOAT) {
1510 cinfo->ret.reg = ARM_VFP_F0;
1512 cinfo->ret.reg = ARMREG_R0;
1515 case MONO_TYPE_GENERICINST:
1516 if (!mono_type_generic_inst_is_valuetype (t)) {
1517 cinfo->ret.storage = RegTypeGeneral;
1518 cinfo->ret.reg = ARMREG_R0;
1521 if (mini_is_gsharedvt_variable_type (t)) {
1522 cinfo->ret.storage = RegTypeStructByAddr;
1526 case MONO_TYPE_VALUETYPE:
1527 case MONO_TYPE_TYPEDBYREF:
1528 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1529 cinfo->ret.storage = RegTypeHFA;
1531 cinfo->ret.nregs = nfields;
1532 cinfo->ret.esize = esize;
1534 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1535 cinfo->ret.storage = RegTypeStructByVal;
1537 cinfo->ret.storage = RegTypeStructByAddr;
1541 case MONO_TYPE_MVAR:
1542 g_assert (mini_is_gsharedvt_type (t));
1543 cinfo->ret.storage = RegTypeStructByAddr;
1545 case MONO_TYPE_VOID:
1548 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1551 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1556 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1557 * the first argument, allowing 'this' to be always passed in the first arg reg.
1558 * Also do this if the first argument is a reference type, since virtual calls
1559 * are sometimes made using calli without sig->hasthis set, like in the delegate
1562 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1564 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1566 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1570 cinfo->ret.reg = gr;
1572 cinfo->vret_arg_index = 1;
1576 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1579 if (vtype_retaddr) {
1580 cinfo->ret.reg = gr;
1585 DEBUG(printf("params: %d\n", sig->param_count));
1586 for (i = pstart; i < sig->param_count; ++i) {
1587 ArgInfo *ainfo = &cinfo->args [n];
1589 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1590 /* Prevent implicit arguments and sig_cookie from
1591 being passed in registers */
1594 /* Emit the signature cookie just before the implicit arguments */
1595 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1597 DEBUG(printf("param %d: ", i));
1598 if (sig->params [i]->byref) {
1599 DEBUG(printf("byref\n"));
1600 add_general (&gr, &stack_size, ainfo, TRUE);
1604 t = mini_get_underlying_type (sig->params [i]);
1608 cinfo->args [n].size = 1;
1609 add_general (&gr, &stack_size, ainfo, TRUE);
1613 cinfo->args [n].size = 2;
1614 add_general (&gr, &stack_size, ainfo, TRUE);
1618 cinfo->args [n].size = 4;
1619 add_general (&gr, &stack_size, ainfo, TRUE);
1624 case MONO_TYPE_FNPTR:
1625 case MONO_TYPE_CLASS:
1626 case MONO_TYPE_OBJECT:
1627 case MONO_TYPE_STRING:
1628 case MONO_TYPE_SZARRAY:
1629 case MONO_TYPE_ARRAY:
1630 cinfo->args [n].size = sizeof (gpointer);
1631 add_general (&gr, &stack_size, ainfo, TRUE);
1633 case MONO_TYPE_GENERICINST:
1634 if (!mono_type_generic_inst_is_valuetype (t)) {
1635 cinfo->args [n].size = sizeof (gpointer);
1636 add_general (&gr, &stack_size, ainfo, TRUE);
1639 if (mini_is_gsharedvt_variable_type (t)) {
1640 /* gsharedvt arguments are passed by ref */
1641 g_assert (mini_is_gsharedvt_type (t));
1642 add_general (&gr, &stack_size, ainfo, TRUE);
1643 switch (ainfo->storage) {
1644 case RegTypeGeneral:
1645 ainfo->storage = RegTypeGSharedVtInReg;
1648 ainfo->storage = RegTypeGSharedVtOnStack;
1651 g_assert_not_reached ();
1656 case MONO_TYPE_TYPEDBYREF:
1657 case MONO_TYPE_VALUETYPE: {
1660 int nwords, nfields, esize;
1663 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1664 if (fpr + nfields < ARM_VFP_F16) {
1665 ainfo->storage = RegTypeHFA;
1667 ainfo->nregs = nfields;
1668 ainfo->esize = esize;
1676 if (t->type == MONO_TYPE_TYPEDBYREF) {
1677 size = sizeof (MonoTypedRef);
1678 align = sizeof (gpointer);
1680 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1682 size = mono_class_native_size (klass, &align);
1684 size = mini_type_stack_size_full (t, &align, FALSE);
1686 DEBUG(printf ("load %d bytes struct\n", size));
1689 align_size += (sizeof (gpointer) - 1);
1690 align_size &= ~(sizeof (gpointer) - 1);
1691 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1692 ainfo->storage = RegTypeStructByVal;
1693 ainfo->struct_size = size;
1694 /* FIXME: align stack_size if needed */
1695 if (eabi_supported) {
1696 if (align >= 8 && (gr & 1))
1699 if (gr > ARMREG_R3) {
1701 ainfo->vtsize = nwords;
1703 int rest = ARMREG_R3 - gr + 1;
1704 int n_in_regs = rest >= nwords? nwords: rest;
1706 ainfo->size = n_in_regs;
1707 ainfo->vtsize = nwords - n_in_regs;
1710 nwords -= n_in_regs;
1712 if (sig->call_convention == MONO_CALL_VARARG)
1713 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1714 stack_size = ALIGN_TO (stack_size, align);
1715 ainfo->offset = stack_size;
1716 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1717 stack_size += nwords * sizeof (gpointer);
1723 add_general (&gr, &stack_size, ainfo, FALSE);
1729 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1731 add_general (&gr, &stack_size, ainfo, TRUE);
1737 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1739 add_general (&gr, &stack_size, ainfo, FALSE);
1742 case MONO_TYPE_MVAR:
1743 /* gsharedvt arguments are passed by ref */
1744 g_assert (mini_is_gsharedvt_type (t));
1745 add_general (&gr, &stack_size, ainfo, TRUE);
1746 switch (ainfo->storage) {
1747 case RegTypeGeneral:
1748 ainfo->storage = RegTypeGSharedVtInReg;
1751 ainfo->storage = RegTypeGSharedVtOnStack;
1754 g_assert_not_reached ();
1758 g_error ("Can't handle 0x%x", sig->params [i]->type);
1763 /* Handle the case where there are no implicit arguments */
1764 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1765 /* Prevent implicit arguments and sig_cookie from
1766 being passed in registers */
1769 /* Emit the signature cookie just before the implicit arguments */
1770 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1773 /* align stack size to 8 */
1774 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1775 stack_size = (stack_size + 7) & ~7;
1777 cinfo->stack_usage = stack_size;
1783 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1785 MonoType *callee_ret;
1789 c1 = get_call_info (NULL, caller_sig);
1790 c2 = get_call_info (NULL, callee_sig);
1793 * Tail calls with more callee stack usage than the caller cannot be supported, since
1794 * the extra stack space would be left on the stack after the tail call.
1796 res = c1->stack_usage >= c2->stack_usage;
1797 callee_ret = mini_get_underlying_type (callee_sig->ret);
1798 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1799 /* An address on the callee's stack is passed as the first argument */
1802 if (c2->stack_usage > 16 * 4)
1814 debug_omit_fp (void)
1817 return mono_debug_count ();
1824 * mono_arch_compute_omit_fp:
1826 * Determine whenever the frame pointer can be eliminated.
1829 mono_arch_compute_omit_fp (MonoCompile *cfg)
1831 MonoMethodSignature *sig;
1832 MonoMethodHeader *header;
1836 if (cfg->arch.omit_fp_computed)
1839 header = cfg->header;
1841 sig = mono_method_signature (cfg->method);
1843 if (!cfg->arch.cinfo)
1844 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1845 cinfo = cfg->arch.cinfo;
1848 * FIXME: Remove some of the restrictions.
1850 cfg->arch.omit_fp = TRUE;
1851 cfg->arch.omit_fp_computed = TRUE;
1853 if (cfg->disable_omit_fp)
1854 cfg->arch.omit_fp = FALSE;
1855 if (!debug_omit_fp ())
1856 cfg->arch.omit_fp = FALSE;
1858 if (cfg->method->save_lmf)
1859 cfg->arch.omit_fp = FALSE;
1861 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1862 cfg->arch.omit_fp = FALSE;
1863 if (header->num_clauses)
1864 cfg->arch.omit_fp = FALSE;
1865 if (cfg->param_area)
1866 cfg->arch.omit_fp = FALSE;
1867 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1868 cfg->arch.omit_fp = FALSE;
1869 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1870 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1871 cfg->arch.omit_fp = FALSE;
1872 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1873 ArgInfo *ainfo = &cinfo->args [i];
1875 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1877 * The stack offset can only be determined when the frame
1880 cfg->arch.omit_fp = FALSE;
1885 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1886 MonoInst *ins = cfg->varinfo [i];
1889 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1894 * Set var information according to the calling convention. arm version.
1895 * The locals var stuff should most likely be split in another method.
1898 mono_arch_allocate_vars (MonoCompile *cfg)
1900 MonoMethodSignature *sig;
1901 MonoMethodHeader *header;
1904 int i, offset, size, align, curinst;
1909 sig = mono_method_signature (cfg->method);
1911 if (!cfg->arch.cinfo)
1912 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1913 cinfo = cfg->arch.cinfo;
1914 sig_ret = mini_get_underlying_type (sig->ret);
1916 mono_arch_compute_omit_fp (cfg);
1918 if (cfg->arch.omit_fp)
1919 cfg->frame_reg = ARMREG_SP;
1921 cfg->frame_reg = ARMREG_FP;
1923 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1925 /* allow room for the vararg method args: void* and long/double */
1926 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1927 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1929 header = cfg->header;
1931 /* See mono_arch_get_global_int_regs () */
1932 if (cfg->flags & MONO_CFG_HAS_CALLS)
1933 cfg->uses_rgctx_reg = TRUE;
1935 if (cfg->frame_reg != ARMREG_SP)
1936 cfg->used_int_regs |= 1 << cfg->frame_reg;
1938 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1939 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1940 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1944 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1945 if (sig_ret->type != MONO_TYPE_VOID) {
1946 cfg->ret->opcode = OP_REGVAR;
1947 cfg->ret->inst_c0 = ARMREG_R0;
1950 /* local vars are at a positive offset from the stack pointer */
1952 * also note that if the function uses alloca, we use FP
1953 * to point at the local variables.
1955 offset = 0; /* linkage area */
1956 /* align the offset to 16 bytes: not sure this is needed here */
1958 //offset &= ~(8 - 1);
1960 /* add parameter area size for called functions */
1961 offset += cfg->param_area;
1964 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1967 /* allow room to save the return value */
1968 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1971 switch (cinfo->ret.storage) {
1972 case RegTypeStructByVal:
1973 cfg->ret->opcode = OP_REGOFFSET;
1974 cfg->ret->inst_basereg = cfg->frame_reg;
1975 offset += sizeof (gpointer) - 1;
1976 offset &= ~(sizeof (gpointer) - 1);
1977 cfg->ret->inst_offset = - offset;
1978 offset += sizeof(gpointer);
1981 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1982 offset = ALIGN_TO (offset, 8);
1983 cfg->ret->opcode = OP_REGOFFSET;
1984 cfg->ret->inst_basereg = cfg->frame_reg;
1985 cfg->ret->inst_offset = offset;
1989 case RegTypeStructByAddr:
1990 ins = cfg->vret_addr;
1991 offset += sizeof(gpointer) - 1;
1992 offset &= ~(sizeof(gpointer) - 1);
1993 ins->inst_offset = offset;
1994 ins->opcode = OP_REGOFFSET;
1995 ins->inst_basereg = cfg->frame_reg;
1996 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1997 printf ("vret_addr =");
1998 mono_print_ins (cfg->vret_addr);
2000 offset += sizeof(gpointer);
2006 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
2007 if (cfg->arch.seq_point_info_var) {
2010 ins = cfg->arch.seq_point_info_var;
2014 offset += align - 1;
2015 offset &= ~(align - 1);
2016 ins->opcode = OP_REGOFFSET;
2017 ins->inst_basereg = cfg->frame_reg;
2018 ins->inst_offset = offset;
2021 ins = cfg->arch.ss_trigger_page_var;
2024 offset += align - 1;
2025 offset &= ~(align - 1);
2026 ins->opcode = OP_REGOFFSET;
2027 ins->inst_basereg = cfg->frame_reg;
2028 ins->inst_offset = offset;
2032 if (cfg->arch.seq_point_read_var) {
2035 ins = cfg->arch.seq_point_read_var;
2039 offset += align - 1;
2040 offset &= ~(align - 1);
2041 ins->opcode = OP_REGOFFSET;
2042 ins->inst_basereg = cfg->frame_reg;
2043 ins->inst_offset = offset;
2046 ins = cfg->arch.seq_point_ss_method_var;
2049 offset += align - 1;
2050 offset &= ~(align - 1);
2051 ins->opcode = OP_REGOFFSET;
2052 ins->inst_basereg = cfg->frame_reg;
2053 ins->inst_offset = offset;
2056 ins = cfg->arch.seq_point_bp_method_var;
2059 offset += align - 1;
2060 offset &= ~(align - 1);
2061 ins->opcode = OP_REGOFFSET;
2062 ins->inst_basereg = cfg->frame_reg;
2063 ins->inst_offset = offset;
2067 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
2068 /* Allocate a temporary used by the atomic ops */
2072 /* Allocate a local slot to hold the sig cookie address */
2073 offset += align - 1;
2074 offset &= ~(align - 1);
2075 cfg->arch.atomic_tmp_offset = offset;
2078 cfg->arch.atomic_tmp_offset = -1;
2081 cfg->locals_min_stack_offset = offset;
2083 curinst = cfg->locals_start;
2084 for (i = curinst; i < cfg->num_varinfo; ++i) {
2087 ins = cfg->varinfo [i];
2088 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
2091 t = ins->inst_vtype;
2092 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
2095 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
2096 * pinvoke wrappers when they call functions returning structure */
2097 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2098 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
2102 size = mono_type_size (t, &align);
2104 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2105 * since it loads/stores misaligned words, which don't do the right thing.
2107 if (align < 4 && size >= 4)
2109 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2110 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2111 offset += align - 1;
2112 offset &= ~(align - 1);
2113 ins->opcode = OP_REGOFFSET;
2114 ins->inst_offset = offset;
2115 ins->inst_basereg = cfg->frame_reg;
2117 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2120 cfg->locals_max_stack_offset = offset;
2124 ins = cfg->args [curinst];
2125 if (ins->opcode != OP_REGVAR) {
2126 ins->opcode = OP_REGOFFSET;
2127 ins->inst_basereg = cfg->frame_reg;
2128 offset += sizeof (gpointer) - 1;
2129 offset &= ~(sizeof (gpointer) - 1);
2130 ins->inst_offset = offset;
2131 offset += sizeof (gpointer);
2136 if (sig->call_convention == MONO_CALL_VARARG) {
2140 /* Allocate a local slot to hold the sig cookie address */
2141 offset += align - 1;
2142 offset &= ~(align - 1);
2143 cfg->sig_cookie = offset;
2147 for (i = 0; i < sig->param_count; ++i) {
2148 ainfo = cinfo->args + i;
2150 ins = cfg->args [curinst];
2152 switch (ainfo->storage) {
2154 offset = ALIGN_TO (offset, 8);
2155 ins->opcode = OP_REGOFFSET;
2156 ins->inst_basereg = cfg->frame_reg;
2157 /* These arguments are saved to the stack in the prolog */
2158 ins->inst_offset = offset;
2159 if (cfg->verbose_level >= 2)
2160 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2168 if (ins->opcode != OP_REGVAR) {
2169 ins->opcode = OP_REGOFFSET;
2170 ins->inst_basereg = cfg->frame_reg;
2171 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2173 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2174 * since it loads/stores misaligned words, which don't do the right thing.
2176 if (align < 4 && size >= 4)
2178 /* The code in the prolog () stores words when storing vtypes received in a register */
2179 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2181 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2182 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2183 offset += align - 1;
2184 offset &= ~(align - 1);
2185 ins->inst_offset = offset;
2191 /* align the offset to 8 bytes */
2192 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2193 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2198 cfg->stack_offset = offset;
2202 mono_arch_create_vars (MonoCompile *cfg)
2204 MonoMethodSignature *sig;
2208 sig = mono_method_signature (cfg->method);
2210 if (!cfg->arch.cinfo)
2211 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2212 cinfo = cfg->arch.cinfo;
2214 if (IS_HARD_FLOAT) {
2215 for (i = 0; i < 2; i++) {
2216 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2217 inst->flags |= MONO_INST_VOLATILE;
2219 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2223 if (cinfo->ret.storage == RegTypeStructByVal)
2224 cfg->ret_var_is_local = TRUE;
2226 if (cinfo->ret.storage == RegTypeStructByAddr) {
2227 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2228 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2229 printf ("vret_addr = ");
2230 mono_print_ins (cfg->vret_addr);
2234 if (cfg->gen_sdb_seq_points) {
2235 if (cfg->soft_breakpoints) {
2236 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2237 ins->flags |= MONO_INST_VOLATILE;
2238 cfg->arch.seq_point_read_var = ins;
2240 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2241 ins->flags |= MONO_INST_VOLATILE;
2242 cfg->arch.seq_point_ss_method_var = ins;
2244 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2245 ins->flags |= MONO_INST_VOLATILE;
2246 cfg->arch.seq_point_bp_method_var = ins;
2248 g_assert (!cfg->compile_aot);
2249 } else if (cfg->compile_aot) {
2250 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2251 ins->flags |= MONO_INST_VOLATILE;
2252 cfg->arch.seq_point_info_var = ins;
2254 /* Allocate a separate variable for this to save 1 load per seq point */
2255 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2256 ins->flags |= MONO_INST_VOLATILE;
2257 cfg->arch.ss_trigger_page_var = ins;
2263 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2265 MonoMethodSignature *tmp_sig;
2268 if (call->tail_call)
2271 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2274 * mono_ArgIterator_Setup assumes the signature cookie is
2275 * passed first and all the arguments which were before it are
2276 * passed on the stack after the signature. So compensate by
2277 * passing a different signature.
2279 tmp_sig = mono_metadata_signature_dup (call->signature);
2280 tmp_sig->param_count -= call->signature->sentinelpos;
2281 tmp_sig->sentinelpos = 0;
2282 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2284 sig_reg = mono_alloc_ireg (cfg);
2285 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2287 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2292 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2297 LLVMCallInfo *linfo;
2299 n = sig->param_count + sig->hasthis;
2301 cinfo = get_call_info (cfg->mempool, sig);
2303 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2306 * LLVM always uses the native ABI while we use our own ABI, the
2307 * only difference is the handling of vtypes:
2308 * - we only pass/receive them in registers in some cases, and only
2309 * in 1 or 2 integer registers.
2311 switch (cinfo->ret.storage) {
2312 case RegTypeGeneral:
2315 case RegTypeIRegPair:
2317 case RegTypeStructByAddr:
2318 /* Vtype returned using a hidden argument */
2319 linfo->ret.storage = LLVMArgVtypeRetAddr;
2320 linfo->vret_arg_index = cinfo->vret_arg_index;
2323 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2324 cfg->disable_llvm = TRUE;
2328 for (i = 0; i < n; ++i) {
2329 ainfo = cinfo->args + i;
2331 linfo->args [i].storage = LLVMArgNone;
2333 switch (ainfo->storage) {
2334 case RegTypeGeneral:
2335 case RegTypeIRegPair:
2337 case RegTypeBaseGen:
2338 linfo->args [i].storage = LLVMArgInIReg;
2340 case RegTypeStructByVal:
2341 linfo->args [i].storage = LLVMArgAsIArgs;
2342 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2345 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2346 cfg->disable_llvm = TRUE;
2356 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2359 MonoMethodSignature *sig;
2363 sig = call->signature;
2364 n = sig->param_count + sig->hasthis;
2366 cinfo = get_call_info (cfg->mempool, sig);
2368 switch (cinfo->ret.storage) {
2369 case RegTypeStructByVal:
2370 /* The JIT will transform this into a normal call */
2371 call->vret_in_reg = TRUE;
2375 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2376 * the location pointed to by it after call in emit_move_return_value ().
2378 if (!cfg->arch.vret_addr_loc) {
2379 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2380 /* Prevent it from being register allocated or optimized away */
2381 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2384 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2386 case RegTypeStructByAddr: {
2388 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2389 vtarg->sreg1 = call->vret_var->dreg;
2390 vtarg->dreg = mono_alloc_preg (cfg);
2391 MONO_ADD_INS (cfg->cbb, vtarg);
2393 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2400 for (i = 0; i < n; ++i) {
2401 ArgInfo *ainfo = cinfo->args + i;
2404 if (i >= sig->hasthis)
2405 t = sig->params [i - sig->hasthis];
2407 t = &mono_defaults.int_class->byval_arg;
2408 t = mini_get_underlying_type (t);
2410 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2411 /* Emit the signature cookie just before the implicit arguments */
2412 emit_sig_cookie (cfg, call, cinfo);
2415 in = call->args [i];
2417 switch (ainfo->storage) {
2418 case RegTypeGeneral:
2419 case RegTypeIRegPair:
2420 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2421 MONO_INST_NEW (cfg, ins, OP_MOVE);
2422 ins->dreg = mono_alloc_ireg (cfg);
2423 ins->sreg1 = in->dreg + 1;
2424 MONO_ADD_INS (cfg->cbb, ins);
2425 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2427 MONO_INST_NEW (cfg, ins, OP_MOVE);
2428 ins->dreg = mono_alloc_ireg (cfg);
2429 ins->sreg1 = in->dreg + 2;
2430 MONO_ADD_INS (cfg->cbb, ins);
2431 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2432 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2433 if (ainfo->size == 4) {
2434 if (IS_SOFT_FLOAT) {
2435 /* mono_emit_call_args () have already done the r8->r4 conversion */
2436 /* The converted value is in an int vreg */
2437 MONO_INST_NEW (cfg, ins, OP_MOVE);
2438 ins->dreg = mono_alloc_ireg (cfg);
2439 ins->sreg1 = in->dreg;
2440 MONO_ADD_INS (cfg->cbb, ins);
2441 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2445 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2446 creg = mono_alloc_ireg (cfg);
2447 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2448 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2451 if (IS_SOFT_FLOAT) {
2452 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2453 ins->dreg = mono_alloc_ireg (cfg);
2454 ins->sreg1 = in->dreg;
2455 MONO_ADD_INS (cfg->cbb, ins);
2456 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2458 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2459 ins->dreg = mono_alloc_ireg (cfg);
2460 ins->sreg1 = in->dreg;
2461 MONO_ADD_INS (cfg->cbb, ins);
2462 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2466 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2467 creg = mono_alloc_ireg (cfg);
2468 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2469 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2470 creg = mono_alloc_ireg (cfg);
2471 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2472 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2475 cfg->flags |= MONO_CFG_HAS_FPOUT;
2477 MONO_INST_NEW (cfg, ins, OP_MOVE);
2478 ins->dreg = mono_alloc_ireg (cfg);
2479 ins->sreg1 = in->dreg;
2480 MONO_ADD_INS (cfg->cbb, ins);
2482 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2485 case RegTypeStructByAddr:
2488 /* FIXME: where si the data allocated? */
2489 arg->backend.reg3 = ainfo->reg;
2490 call->used_iregs |= 1 << ainfo->reg;
2491 g_assert_not_reached ();
2494 case RegTypeStructByVal:
2495 case RegTypeGSharedVtInReg:
2496 case RegTypeGSharedVtOnStack:
2498 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2499 ins->opcode = OP_OUTARG_VT;
2500 ins->sreg1 = in->dreg;
2501 ins->klass = in->klass;
2502 ins->inst_p0 = call;
2503 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2504 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2505 mono_call_inst_add_outarg_vt (cfg, call, ins);
2506 MONO_ADD_INS (cfg->cbb, ins);
2509 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2510 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2511 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2512 if (t->type == MONO_TYPE_R8) {
2513 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2516 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2518 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2521 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2524 case RegTypeBaseGen:
2525 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2526 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
2527 MONO_INST_NEW (cfg, ins, OP_MOVE);
2528 ins->dreg = mono_alloc_ireg (cfg);
2529 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
2530 MONO_ADD_INS (cfg->cbb, ins);
2531 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2532 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2535 /* This should work for soft-float as well */
2537 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2538 creg = mono_alloc_ireg (cfg);
2539 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2540 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2541 creg = mono_alloc_ireg (cfg);
2542 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2543 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2544 cfg->flags |= MONO_CFG_HAS_FPOUT;
2546 g_assert_not_reached ();
2550 int fdreg = mono_alloc_freg (cfg);
2552 if (ainfo->size == 8) {
2553 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2554 ins->sreg1 = in->dreg;
2556 MONO_ADD_INS (cfg->cbb, ins);
2558 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2563 * Mono's register allocator doesn't speak single-precision registers that
2564 * overlap double-precision registers (i.e. armhf). So we have to work around
2565 * the register allocator and load the value from memory manually.
2567 * So we create a variable for the float argument and an instruction to store
2568 * the argument into the variable. We then store the list of these arguments
2569 * in cfg->float_args. This list is then used by emit_float_args later to
2570 * pass the arguments in the various call opcodes.
2572 * This is not very nice, and we should really try to fix the allocator.
2575 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2577 /* Make sure the instruction isn't seen as pointless and removed.
2579 float_arg->flags |= MONO_INST_VOLATILE;
2581 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2583 /* We use the dreg to look up the instruction later. The hreg is used to
2584 * emit the instruction that loads the value into the FP reg.
2586 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2587 fad->vreg = float_arg->dreg;
2588 fad->hreg = ainfo->reg;
2590 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2593 call->used_iregs |= 1 << ainfo->reg;
2594 cfg->flags |= MONO_CFG_HAS_FPOUT;
2598 g_assert_not_reached ();
2602 /* Handle the case where there are no implicit arguments */
2603 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2604 emit_sig_cookie (cfg, call, cinfo);
2606 call->call_info = cinfo;
2607 call->stack_usage = cinfo->stack_usage;
2611 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2617 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2618 ins->dreg = mono_alloc_freg (cfg);
2619 ins->sreg1 = arg->dreg;
2620 MONO_ADD_INS (cfg->cbb, ins);
2621 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2624 g_assert_not_reached ();
2630 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2632 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2634 ArgInfo *ainfo = ins->inst_p1;
2635 int ovf_size = ainfo->vtsize;
2636 int doffset = ainfo->offset;
2637 int struct_size = ainfo->struct_size;
2638 int i, soffset, dreg, tmpreg;
2640 switch (ainfo->storage) {
2641 case RegTypeGSharedVtInReg:
2643 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2645 case RegTypeGSharedVtOnStack:
2646 /* Pass by addr on stack */
2647 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2650 for (i = 0; i < ainfo->nregs; ++i) {
2651 if (ainfo->esize == 4)
2652 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2654 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2655 load->dreg = mono_alloc_freg (cfg);
2656 load->inst_basereg = src->dreg;
2657 load->inst_offset = i * ainfo->esize;
2658 MONO_ADD_INS (cfg->cbb, load);
2660 if (ainfo->esize == 4) {
2663 /* See RegTypeFP in mono_arch_emit_call () */
2664 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2665 float_arg->flags |= MONO_INST_VOLATILE;
2666 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2668 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2669 fad->vreg = float_arg->dreg;
2670 fad->hreg = ainfo->reg + i;
2672 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2674 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + i, load);
2680 for (i = 0; i < ainfo->size; ++i) {
2681 dreg = mono_alloc_ireg (cfg);
2682 switch (struct_size) {
2684 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2687 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2690 tmpreg = mono_alloc_ireg (cfg);
2691 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2692 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2693 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2694 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2695 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2696 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2697 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2700 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2703 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2704 soffset += sizeof (gpointer);
2705 struct_size -= sizeof (gpointer);
2707 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2709 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2715 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2717 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2720 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2723 if (COMPILE_LLVM (cfg)) {
2724 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2726 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2727 ins->sreg1 = val->dreg + 1;
2728 ins->sreg2 = val->dreg + 2;
2729 MONO_ADD_INS (cfg->cbb, ins);
2734 case MONO_ARM_FPU_NONE:
2735 if (ret->type == MONO_TYPE_R8) {
2738 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2739 ins->dreg = cfg->ret->dreg;
2740 ins->sreg1 = val->dreg;
2741 MONO_ADD_INS (cfg->cbb, ins);
2744 if (ret->type == MONO_TYPE_R4) {
2745 /* Already converted to an int in method_to_ir () */
2746 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2750 case MONO_ARM_FPU_VFP:
2751 case MONO_ARM_FPU_VFP_HARD:
2752 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2755 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2756 ins->dreg = cfg->ret->dreg;
2757 ins->sreg1 = val->dreg;
2758 MONO_ADD_INS (cfg->cbb, ins);
2763 g_assert_not_reached ();
2767 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2770 #endif /* #ifndef DISABLE_JIT */
2773 mono_arch_is_inst_imm (gint64 imm)
2779 MonoMethodSignature *sig;
2782 MonoType **param_types;
2786 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2790 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2793 switch (cinfo->ret.storage) {
2795 case RegTypeGeneral:
2796 case RegTypeIRegPair:
2797 case RegTypeStructByAddr:
2808 for (i = 0; i < cinfo->nargs; ++i) {
2809 ArgInfo *ainfo = &cinfo->args [i];
2812 switch (ainfo->storage) {
2813 case RegTypeGeneral:
2814 case RegTypeIRegPair:
2815 case RegTypeBaseGen:
2818 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2821 case RegTypeStructByVal:
2822 if (ainfo->size == 0)
2823 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2825 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2826 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2834 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2835 for (i = 0; i < sig->param_count; ++i) {
2836 MonoType *t = sig->params [i];
2841 t = mini_get_underlying_type (t);
2864 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2866 ArchDynCallInfo *info;
2870 cinfo = get_call_info (NULL, sig);
2872 if (!dyn_call_supported (cinfo, sig)) {
2877 info = g_new0 (ArchDynCallInfo, 1);
2878 // FIXME: Preprocess the info to speed up start_dyn_call ()
2880 info->cinfo = cinfo;
2881 info->rtype = mini_get_underlying_type (sig->ret);
2882 info->param_types = g_new0 (MonoType*, sig->param_count);
2883 for (i = 0; i < sig->param_count; ++i)
2884 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2886 return (MonoDynCallInfo*)info;
2890 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2892 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2894 g_free (ainfo->cinfo);
2899 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2901 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2902 DynCallArgs *p = (DynCallArgs*)buf;
2903 int arg_index, greg, i, j, pindex;
2904 MonoMethodSignature *sig = dinfo->sig;
2906 g_assert (buf_len >= sizeof (DynCallArgs));
2915 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2916 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2921 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2922 p->regs [greg ++] = (mgreg_t)ret;
2924 for (i = pindex; i < sig->param_count; i++) {
2925 MonoType *t = dinfo->param_types [i];
2926 gpointer *arg = args [arg_index ++];
2927 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2930 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2932 } else if (ainfo->storage == RegTypeBase) {
2933 slot = PARAM_REGS + (ainfo->offset / 4);
2934 } else if (ainfo->storage == RegTypeBaseGen) {
2935 /* slot + 1 is the first stack slot, so the code below will work */
2938 g_assert_not_reached ();
2942 p->regs [slot] = (mgreg_t)*arg;
2947 case MONO_TYPE_STRING:
2948 case MONO_TYPE_CLASS:
2949 case MONO_TYPE_ARRAY:
2950 case MONO_TYPE_SZARRAY:
2951 case MONO_TYPE_OBJECT:
2955 p->regs [slot] = (mgreg_t)*arg;
2958 p->regs [slot] = *(guint8*)arg;
2961 p->regs [slot] = *(gint8*)arg;
2964 p->regs [slot] = *(gint16*)arg;
2967 p->regs [slot] = *(guint16*)arg;
2970 p->regs [slot] = *(gint32*)arg;
2973 p->regs [slot] = *(guint32*)arg;
2977 p->regs [slot ++] = (mgreg_t)arg [0];
2978 p->regs [slot] = (mgreg_t)arg [1];
2981 p->regs [slot] = *(mgreg_t*)arg;
2984 p->regs [slot ++] = (mgreg_t)arg [0];
2985 p->regs [slot] = (mgreg_t)arg [1];
2987 case MONO_TYPE_GENERICINST:
2988 if (MONO_TYPE_IS_REFERENCE (t)) {
2989 p->regs [slot] = (mgreg_t)*arg;
2992 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2993 MonoClass *klass = mono_class_from_mono_type (t);
2994 guint8 *nullable_buf;
2997 size = mono_class_value_size (klass, NULL);
2998 nullable_buf = g_alloca (size);
2999 g_assert (nullable_buf);
3001 /* The argument pointed to by arg is either a boxed vtype or null */
3002 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
3004 arg = (gpointer*)nullable_buf;
3010 case MONO_TYPE_VALUETYPE:
3011 g_assert (ainfo->storage == RegTypeStructByVal);
3013 if (ainfo->size == 0)
3014 slot = PARAM_REGS + (ainfo->offset / 4);
3018 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
3019 p->regs [slot ++] = ((mgreg_t*)arg) [j];
3022 g_assert_not_reached ();
3028 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
3030 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
3031 MonoType *ptype = ainfo->rtype;
3032 guint8 *ret = ((DynCallArgs*)buf)->ret;
3033 mgreg_t res = ((DynCallArgs*)buf)->res;
3034 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
3036 switch (ptype->type) {
3037 case MONO_TYPE_VOID:
3038 *(gpointer*)ret = NULL;
3040 case MONO_TYPE_STRING:
3041 case MONO_TYPE_CLASS:
3042 case MONO_TYPE_ARRAY:
3043 case MONO_TYPE_SZARRAY:
3044 case MONO_TYPE_OBJECT:
3048 *(gpointer*)ret = (gpointer)res;
3054 *(guint8*)ret = res;
3057 *(gint16*)ret = res;
3060 *(guint16*)ret = res;
3063 *(gint32*)ret = res;
3066 *(guint32*)ret = res;
3070 /* This handles endianness as well */
3071 ((gint32*)ret) [0] = res;
3072 ((gint32*)ret) [1] = res2;
3074 case MONO_TYPE_GENERICINST:
3075 if (MONO_TYPE_IS_REFERENCE (ptype)) {
3076 *(gpointer*)ret = (gpointer)res;
3081 case MONO_TYPE_VALUETYPE:
3082 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
3087 *(float*)ret = *(float*)&res;
3089 case MONO_TYPE_R8: {
3096 *(double*)ret = *(double*)®s;
3100 g_assert_not_reached ();
3107 * Allow tracing to work with this interface (with an optional argument)
3111 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3115 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3116 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3117 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3118 code = emit_call_reg (code, ARMREG_R2);
3132 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3135 int save_mode = SAVE_NONE;
3137 MonoMethod *method = cfg->method;
3138 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3139 int rtype = ret_type->type;
3140 int save_offset = cfg->param_area;
3144 offset = code - cfg->native_code;
3145 /* we need about 16 instructions */
3146 if (offset > (cfg->code_size - 16 * 4)) {
3147 cfg->code_size *= 2;
3148 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3149 code = cfg->native_code + offset;
3152 case MONO_TYPE_VOID:
3153 /* special case string .ctor icall */
3154 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3155 save_mode = SAVE_ONE;
3157 save_mode = SAVE_NONE;
3161 save_mode = SAVE_TWO;
3165 save_mode = SAVE_ONE_FP;
3167 save_mode = SAVE_ONE;
3171 save_mode = SAVE_TWO_FP;
3173 save_mode = SAVE_TWO;
3175 case MONO_TYPE_GENERICINST:
3176 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3177 save_mode = SAVE_ONE;
3181 case MONO_TYPE_VALUETYPE:
3182 save_mode = SAVE_STRUCT;
3185 save_mode = SAVE_ONE;
3189 switch (save_mode) {
3191 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3192 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3193 if (enable_arguments) {
3194 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3195 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3199 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3200 if (enable_arguments) {
3201 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3205 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3206 if (enable_arguments) {
3207 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3211 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3212 if (enable_arguments) {
3213 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3217 if (enable_arguments) {
3218 /* FIXME: get the actual address */
3219 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3227 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3228 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3229 code = emit_call_reg (code, ARMREG_IP);
3231 switch (save_mode) {
3233 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3234 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3237 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3240 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3243 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3254 * The immediate field for cond branches is big enough for all reasonable methods
3256 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3257 if (0 && ins->inst_true_bb->native_offset) { \
3258 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3260 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3261 ARM_B_COND (code, (condcode), 0); \
3264 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3266 /* emit an exception if condition is fail
3268 * We assign the extra code used to throw the implicit exceptions
3269 * to cfg->bb_exit as far as the big branch handling is concerned
3271 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3273 mono_add_patch_info (cfg, code - cfg->native_code, \
3274 MONO_PATCH_INFO_EXC, exc_name); \
3275 ARM_BL_COND (code, (condcode), 0); \
3278 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3281 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3286 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3290 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3291 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3293 switch (ins->opcode) {
3296 /* Already done by an arch-independent pass */
3298 case OP_LOAD_MEMBASE:
3299 case OP_LOADI4_MEMBASE:
3301 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3302 * OP_LOAD_MEMBASE offset(basereg), reg
3304 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3305 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3306 ins->inst_basereg == last_ins->inst_destbasereg &&
3307 ins->inst_offset == last_ins->inst_offset) {
3308 if (ins->dreg == last_ins->sreg1) {
3309 MONO_DELETE_INS (bb, ins);
3312 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3313 ins->opcode = OP_MOVE;
3314 ins->sreg1 = last_ins->sreg1;
3318 * Note: reg1 must be different from the basereg in the second load
3319 * OP_LOAD_MEMBASE offset(basereg), reg1
3320 * OP_LOAD_MEMBASE offset(basereg), reg2
3322 * OP_LOAD_MEMBASE offset(basereg), reg1
3323 * OP_MOVE reg1, reg2
3325 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3326 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3327 ins->inst_basereg != last_ins->dreg &&
3328 ins->inst_basereg == last_ins->inst_basereg &&
3329 ins->inst_offset == last_ins->inst_offset) {
3331 if (ins->dreg == last_ins->dreg) {
3332 MONO_DELETE_INS (bb, ins);
3335 ins->opcode = OP_MOVE;
3336 ins->sreg1 = last_ins->dreg;
3339 //g_assert_not_reached ();
3343 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3344 * OP_LOAD_MEMBASE offset(basereg), reg
3346 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3347 * OP_ICONST reg, imm
3349 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3350 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3351 ins->inst_basereg == last_ins->inst_destbasereg &&
3352 ins->inst_offset == last_ins->inst_offset) {
3353 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3354 ins->opcode = OP_ICONST;
3355 ins->inst_c0 = last_ins->inst_imm;
3356 g_assert_not_reached (); // check this rule
3360 case OP_LOADU1_MEMBASE:
3361 case OP_LOADI1_MEMBASE:
3362 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3363 ins->inst_basereg == last_ins->inst_destbasereg &&
3364 ins->inst_offset == last_ins->inst_offset) {
3365 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3366 ins->sreg1 = last_ins->sreg1;
3369 case OP_LOADU2_MEMBASE:
3370 case OP_LOADI2_MEMBASE:
3371 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3372 ins->inst_basereg == last_ins->inst_destbasereg &&
3373 ins->inst_offset == last_ins->inst_offset) {
3374 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3375 ins->sreg1 = last_ins->sreg1;
3379 ins->opcode = OP_MOVE;
3383 if (ins->dreg == ins->sreg1) {
3384 MONO_DELETE_INS (bb, ins);
3388 * OP_MOVE sreg, dreg
3389 * OP_MOVE dreg, sreg
3391 if (last_ins && last_ins->opcode == OP_MOVE &&
3392 ins->sreg1 == last_ins->dreg &&
3393 ins->dreg == last_ins->sreg1) {
3394 MONO_DELETE_INS (bb, ins);
3403 * the branch_cc_table should maintain the order of these
3417 branch_cc_table [] = {
3431 #define ADD_NEW_INS(cfg,dest,op) do { \
3432 MONO_INST_NEW ((cfg), (dest), (op)); \
3433 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3437 map_to_reg_reg_op (int op)
3446 case OP_COMPARE_IMM:
3448 case OP_ICOMPARE_IMM:
3462 case OP_LOAD_MEMBASE:
3463 return OP_LOAD_MEMINDEX;
3464 case OP_LOADI4_MEMBASE:
3465 return OP_LOADI4_MEMINDEX;
3466 case OP_LOADU4_MEMBASE:
3467 return OP_LOADU4_MEMINDEX;
3468 case OP_LOADU1_MEMBASE:
3469 return OP_LOADU1_MEMINDEX;
3470 case OP_LOADI2_MEMBASE:
3471 return OP_LOADI2_MEMINDEX;
3472 case OP_LOADU2_MEMBASE:
3473 return OP_LOADU2_MEMINDEX;
3474 case OP_LOADI1_MEMBASE:
3475 return OP_LOADI1_MEMINDEX;
3476 case OP_STOREI1_MEMBASE_REG:
3477 return OP_STOREI1_MEMINDEX;
3478 case OP_STOREI2_MEMBASE_REG:
3479 return OP_STOREI2_MEMINDEX;
3480 case OP_STOREI4_MEMBASE_REG:
3481 return OP_STOREI4_MEMINDEX;
3482 case OP_STORE_MEMBASE_REG:
3483 return OP_STORE_MEMINDEX;
3484 case OP_STORER4_MEMBASE_REG:
3485 return OP_STORER4_MEMINDEX;
3486 case OP_STORER8_MEMBASE_REG:
3487 return OP_STORER8_MEMINDEX;
3488 case OP_STORE_MEMBASE_IMM:
3489 return OP_STORE_MEMBASE_REG;
3490 case OP_STOREI1_MEMBASE_IMM:
3491 return OP_STOREI1_MEMBASE_REG;
3492 case OP_STOREI2_MEMBASE_IMM:
3493 return OP_STOREI2_MEMBASE_REG;
3494 case OP_STOREI4_MEMBASE_IMM:
3495 return OP_STOREI4_MEMBASE_REG;
3497 g_assert_not_reached ();
3501 * Remove from the instruction list the instructions that can't be
3502 * represented with very simple instructions with no register
3506 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3508 MonoInst *ins, *temp, *last_ins = NULL;
3509 int rot_amount, imm8, low_imm;
3511 MONO_BB_FOR_EACH_INS (bb, ins) {
3513 switch (ins->opcode) {
3517 case OP_COMPARE_IMM:
3518 case OP_ICOMPARE_IMM:
3532 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3533 ADD_NEW_INS (cfg, temp, OP_ICONST);
3534 temp->inst_c0 = ins->inst_imm;
3535 temp->dreg = mono_alloc_ireg (cfg);
3536 ins->sreg2 = temp->dreg;
3537 ins->opcode = mono_op_imm_to_op (ins->opcode);
3539 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3545 if (ins->inst_imm == 1) {
3546 ins->opcode = OP_MOVE;
3549 if (ins->inst_imm == 0) {
3550 ins->opcode = OP_ICONST;
3554 imm8 = mono_is_power_of_two (ins->inst_imm);
3556 ins->opcode = OP_SHL_IMM;
3557 ins->inst_imm = imm8;
3560 ADD_NEW_INS (cfg, temp, OP_ICONST);
3561 temp->inst_c0 = ins->inst_imm;
3562 temp->dreg = mono_alloc_ireg (cfg);
3563 ins->sreg2 = temp->dreg;
3564 ins->opcode = OP_IMUL;
3570 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3571 /* ARM sets the C flag to 1 if there was _no_ overflow */
3572 ins->next->opcode = OP_COND_EXC_NC;
3575 case OP_IDIV_UN_IMM:
3577 case OP_IREM_UN_IMM:
3578 ADD_NEW_INS (cfg, temp, OP_ICONST);
3579 temp->inst_c0 = ins->inst_imm;
3580 temp->dreg = mono_alloc_ireg (cfg);
3581 ins->sreg2 = temp->dreg;
3582 ins->opcode = mono_op_imm_to_op (ins->opcode);
3584 case OP_LOCALLOC_IMM:
3585 ADD_NEW_INS (cfg, temp, OP_ICONST);
3586 temp->inst_c0 = ins->inst_imm;
3587 temp->dreg = mono_alloc_ireg (cfg);
3588 ins->sreg1 = temp->dreg;
3589 ins->opcode = OP_LOCALLOC;
3591 case OP_LOAD_MEMBASE:
3592 case OP_LOADI4_MEMBASE:
3593 case OP_LOADU4_MEMBASE:
3594 case OP_LOADU1_MEMBASE:
3595 /* we can do two things: load the immed in a register
3596 * and use an indexed load, or see if the immed can be
3597 * represented as an ad_imm + a load with a smaller offset
3598 * that fits. We just do the first for now, optimize later.
3600 if (arm_is_imm12 (ins->inst_offset))
3602 ADD_NEW_INS (cfg, temp, OP_ICONST);
3603 temp->inst_c0 = ins->inst_offset;
3604 temp->dreg = mono_alloc_ireg (cfg);
3605 ins->sreg2 = temp->dreg;
3606 ins->opcode = map_to_reg_reg_op (ins->opcode);
3608 case OP_LOADI2_MEMBASE:
3609 case OP_LOADU2_MEMBASE:
3610 case OP_LOADI1_MEMBASE:
3611 if (arm_is_imm8 (ins->inst_offset))
3613 ADD_NEW_INS (cfg, temp, OP_ICONST);
3614 temp->inst_c0 = ins->inst_offset;
3615 temp->dreg = mono_alloc_ireg (cfg);
3616 ins->sreg2 = temp->dreg;
3617 ins->opcode = map_to_reg_reg_op (ins->opcode);
3619 case OP_LOADR4_MEMBASE:
3620 case OP_LOADR8_MEMBASE:
3621 if (arm_is_fpimm8 (ins->inst_offset))
3623 low_imm = ins->inst_offset & 0x1ff;
3624 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3625 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3626 temp->inst_imm = ins->inst_offset & ~0x1ff;
3627 temp->sreg1 = ins->inst_basereg;
3628 temp->dreg = mono_alloc_ireg (cfg);
3629 ins->inst_basereg = temp->dreg;
3630 ins->inst_offset = low_imm;
3634 ADD_NEW_INS (cfg, temp, OP_ICONST);
3635 temp->inst_c0 = ins->inst_offset;
3636 temp->dreg = mono_alloc_ireg (cfg);
3638 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3639 add_ins->sreg1 = ins->inst_basereg;
3640 add_ins->sreg2 = temp->dreg;
3641 add_ins->dreg = mono_alloc_ireg (cfg);
3643 ins->inst_basereg = add_ins->dreg;
3644 ins->inst_offset = 0;
3647 case OP_STORE_MEMBASE_REG:
3648 case OP_STOREI4_MEMBASE_REG:
3649 case OP_STOREI1_MEMBASE_REG:
3650 if (arm_is_imm12 (ins->inst_offset))
3652 ADD_NEW_INS (cfg, temp, OP_ICONST);
3653 temp->inst_c0 = ins->inst_offset;
3654 temp->dreg = mono_alloc_ireg (cfg);
3655 ins->sreg2 = temp->dreg;
3656 ins->opcode = map_to_reg_reg_op (ins->opcode);
3658 case OP_STOREI2_MEMBASE_REG:
3659 if (arm_is_imm8 (ins->inst_offset))
3661 ADD_NEW_INS (cfg, temp, OP_ICONST);
3662 temp->inst_c0 = ins->inst_offset;
3663 temp->dreg = mono_alloc_ireg (cfg);
3664 ins->sreg2 = temp->dreg;
3665 ins->opcode = map_to_reg_reg_op (ins->opcode);
3667 case OP_STORER4_MEMBASE_REG:
3668 case OP_STORER8_MEMBASE_REG:
3669 if (arm_is_fpimm8 (ins->inst_offset))
3671 low_imm = ins->inst_offset & 0x1ff;
3672 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3673 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3674 temp->inst_imm = ins->inst_offset & ~0x1ff;
3675 temp->sreg1 = ins->inst_destbasereg;
3676 temp->dreg = mono_alloc_ireg (cfg);
3677 ins->inst_destbasereg = temp->dreg;
3678 ins->inst_offset = low_imm;
3682 ADD_NEW_INS (cfg, temp, OP_ICONST);
3683 temp->inst_c0 = ins->inst_offset;
3684 temp->dreg = mono_alloc_ireg (cfg);
3686 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3687 add_ins->sreg1 = ins->inst_destbasereg;
3688 add_ins->sreg2 = temp->dreg;
3689 add_ins->dreg = mono_alloc_ireg (cfg);
3691 ins->inst_destbasereg = add_ins->dreg;
3692 ins->inst_offset = 0;
3695 case OP_STORE_MEMBASE_IMM:
3696 case OP_STOREI1_MEMBASE_IMM:
3697 case OP_STOREI2_MEMBASE_IMM:
3698 case OP_STOREI4_MEMBASE_IMM:
3699 ADD_NEW_INS (cfg, temp, OP_ICONST);
3700 temp->inst_c0 = ins->inst_imm;
3701 temp->dreg = mono_alloc_ireg (cfg);
3702 ins->sreg1 = temp->dreg;
3703 ins->opcode = map_to_reg_reg_op (ins->opcode);
3705 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3708 gboolean swap = FALSE;
3712 /* Optimized away */
3717 /* Some fp compares require swapped operands */
3718 switch (ins->next->opcode) {
3720 ins->next->opcode = OP_FBLT;
3724 ins->next->opcode = OP_FBLT_UN;
3728 ins->next->opcode = OP_FBGE;
3732 ins->next->opcode = OP_FBGE_UN;
3740 ins->sreg1 = ins->sreg2;
3749 bb->last_ins = last_ins;
3750 bb->max_vreg = cfg->next_vreg;
3754 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3758 if (long_ins->opcode == OP_LNEG) {
3760 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3761 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3767 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3769 /* sreg is a float, dreg is an integer reg */
3771 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3773 ARM_TOSIZD (code, vfp_scratch1, sreg);
3775 ARM_TOUIZD (code, vfp_scratch1, sreg);
3776 ARM_FMRS (code, dreg, vfp_scratch1);
3777 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3781 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3782 else if (size == 2) {
3783 ARM_SHL_IMM (code, dreg, dreg, 16);
3784 ARM_SHR_IMM (code, dreg, dreg, 16);
3788 ARM_SHL_IMM (code, dreg, dreg, 24);
3789 ARM_SAR_IMM (code, dreg, dreg, 24);
3790 } else if (size == 2) {
3791 ARM_SHL_IMM (code, dreg, dreg, 16);
3792 ARM_SAR_IMM (code, dreg, dreg, 16);
3799 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3801 /* sreg is a float, dreg is an integer reg */
3803 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3805 ARM_TOSIZS (code, vfp_scratch1, sreg);
3807 ARM_TOUIZS (code, vfp_scratch1, sreg);
3808 ARM_FMRS (code, dreg, vfp_scratch1);
3809 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3813 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3814 else if (size == 2) {
3815 ARM_SHL_IMM (code, dreg, dreg, 16);
3816 ARM_SHR_IMM (code, dreg, dreg, 16);
3820 ARM_SHL_IMM (code, dreg, dreg, 24);
3821 ARM_SAR_IMM (code, dreg, dreg, 24);
3822 } else if (size == 2) {
3823 ARM_SHL_IMM (code, dreg, dreg, 16);
3824 ARM_SAR_IMM (code, dreg, dreg, 16);
3830 #endif /* #ifndef DISABLE_JIT */
3832 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3835 emit_thunk (guint8 *code, gconstpointer target)
3839 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3840 if (thumb_supported)
3841 ARM_BX (code, ARMREG_IP);
3843 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3844 *(guint32*)code = (guint32)target;
3846 mono_arch_flush_icache (p, code - p);
3850 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3852 MonoJitInfo *ji = NULL;
3853 MonoThunkJitInfo *info;
3856 guint8 *orig_target;
3857 guint8 *target_thunk;
3860 domain = mono_domain_get ();
3864 * This can be called multiple times during JITting,
3865 * save the current position in cfg->arch to avoid
3866 * doing a O(n^2) search.
3868 if (!cfg->arch.thunks) {
3869 cfg->arch.thunks = cfg->thunks;
3870 cfg->arch.thunks_size = cfg->thunk_area;
3872 thunks = cfg->arch.thunks;
3873 thunks_size = cfg->arch.thunks_size;
3875 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3876 g_assert_not_reached ();
3879 g_assert (*(guint32*)thunks == 0);
3880 emit_thunk (thunks, target);
3881 arm_patch (code, thunks);
3883 cfg->arch.thunks += THUNK_SIZE;
3884 cfg->arch.thunks_size -= THUNK_SIZE;
3886 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3888 info = mono_jit_info_get_thunk_info (ji);
3891 thunks = (guint8*)ji->code_start + info->thunks_offset;
3892 thunks_size = info->thunks_size;
3894 orig_target = mono_arch_get_call_target (code + 4);
3896 mono_mini_arch_lock ();
3898 target_thunk = NULL;
3899 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3900 /* The call already points to a thunk, because of trampolines etc. */
3901 target_thunk = orig_target;
3903 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3904 if (((guint32*)p) [0] == 0) {
3908 } else if (((guint32*)p) [2] == (guint32)target) {
3909 /* Thunk already points to target */
3916 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
3918 if (!target_thunk) {
3919 mono_mini_arch_unlock ();
3920 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3921 g_assert_not_reached ();
3924 emit_thunk (target_thunk, target);
3925 arm_patch (code, target_thunk);
3926 mono_arch_flush_icache (code, 4);
3928 mono_mini_arch_unlock ();
3933 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3935 guint32 *code32 = (void*)code;
3936 guint32 ins = *code32;
3937 guint32 prim = (ins >> 25) & 7;
3938 guint32 tval = GPOINTER_TO_UINT (target);
3940 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3941 if (prim == 5) { /* 101b */
3942 /* the diff starts 8 bytes from the branch opcode */
3943 gint diff = target - code - 8;
3945 gint tmask = 0xffffffff;
3946 if (tval & 1) { /* entering thumb mode */
3947 diff = target - 1 - code - 8;
3948 g_assert (thumb_supported);
3949 tbits = 0xf << 28; /* bl->blx bit pattern */
3950 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3951 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3955 tmask = ~(1 << 24); /* clear the link bit */
3956 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3961 if (diff <= 33554431) {
3963 ins = (ins & 0xff000000) | diff;
3965 *code32 = ins | tbits;
3969 /* diff between 0 and -33554432 */
3970 if (diff >= -33554432) {
3972 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3974 *code32 = ins | tbits;
3979 handle_thunk (cfg, domain, code, target);
3983 #ifdef USE_JUMP_TABLES
3985 gpointer *jte = mono_jumptable_get_entry (code);
3987 jte [0] = (gpointer) target;
3991 * The alternative call sequences looks like this:
3993 * ldr ip, [pc] // loads the address constant
3994 * b 1f // jumps around the constant
3995 * address constant embedded in the code
4000 * There are two cases for patching:
4001 * a) at the end of method emission: in this case code points to the start
4002 * of the call sequence
4003 * b) during runtime patching of the call site: in this case code points
4004 * to the mov pc, ip instruction
4006 * We have to handle also the thunk jump code sequence:
4010 * address constant // execution never reaches here
4012 if ((ins & 0x0ffffff0) == 0x12fff10) {
4013 /* Branch and exchange: the address is constructed in a reg
4014 * We can patch BX when the code sequence is the following:
4015 * ldr ip, [pc, #0] ; 0x8
4022 guint8 *emit = (guint8*)ccode;
4023 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4025 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4026 ARM_BX (emit, ARMREG_IP);
4028 /*patching from magic trampoline*/
4029 if (ins == ccode [3]) {
4030 g_assert (code32 [-4] == ccode [0]);
4031 g_assert (code32 [-3] == ccode [1]);
4032 g_assert (code32 [-1] == ccode [2]);
4033 code32 [-2] = (guint32)target;
4036 /*patching from JIT*/
4037 if (ins == ccode [0]) {
4038 g_assert (code32 [1] == ccode [1]);
4039 g_assert (code32 [3] == ccode [2]);
4040 g_assert (code32 [4] == ccode [3]);
4041 code32 [2] = (guint32)target;
4044 g_assert_not_reached ();
4045 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
4053 guint8 *emit = (guint8*)ccode;
4054 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4056 ARM_BLX_REG (emit, ARMREG_IP);
4058 g_assert (code32 [-3] == ccode [0]);
4059 g_assert (code32 [-2] == ccode [1]);
4060 g_assert (code32 [0] == ccode [2]);
4062 code32 [-1] = (guint32)target;
4065 guint32 *tmp = ccode;
4066 guint8 *emit = (guint8*)tmp;
4067 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4068 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4069 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
4070 ARM_BX (emit, ARMREG_IP);
4071 if (ins == ccode [2]) {
4072 g_assert_not_reached (); // should be -2 ...
4073 code32 [-1] = (guint32)target;
4076 if (ins == ccode [0]) {
4077 /* handles both thunk jump code and the far call sequence */
4078 code32 [2] = (guint32)target;
4081 g_assert_not_reached ();
4083 // g_print ("patched with 0x%08x\n", ins);
4088 arm_patch (guchar *code, const guchar *target)
4090 arm_patch_general (NULL, NULL, code, target);
4094 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4095 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4096 * to be used with the emit macros.
4097 * Return -1 otherwise.
4100 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4103 for (i = 0; i < 31; i+= 2) {
4104 res = (val << (32 - i)) | (val >> i);
4107 *rot_amount = i? 32 - i: 0;
4114 * Emits in code a sequence of instructions that load the value 'val'
4115 * into the dreg register. Uses at most 4 instructions.
4118 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4120 int imm8, rot_amount;
4122 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4123 /* skip the constant pool */
4129 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4130 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4131 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4132 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4135 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4137 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4141 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4143 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4145 if (val & 0xFF0000) {
4146 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4148 if (val & 0xFF000000) {
4149 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4151 } else if (val & 0xFF00) {
4152 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4153 if (val & 0xFF0000) {
4154 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4156 if (val & 0xFF000000) {
4157 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4159 } else if (val & 0xFF0000) {
4160 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4161 if (val & 0xFF000000) {
4162 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4165 //g_assert_not_reached ();
4171 mono_arm_thumb_supported (void)
4173 return thumb_supported;
4179 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4184 call = (MonoCallInst*)ins;
4185 cinfo = call->call_info;
4187 switch (cinfo->ret.storage) {
4189 MonoInst *loc = cfg->arch.vret_addr_loc;
4192 /* Load the destination address */
4193 g_assert (loc && loc->opcode == OP_REGOFFSET);
4195 if (arm_is_imm12 (loc->inst_offset)) {
4196 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4198 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4199 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4201 for (i = 0; i < cinfo->ret.nregs; ++i) {
4202 if (cinfo->ret.esize == 4)
4203 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4205 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4213 switch (ins->opcode) {
4216 case OP_FCALL_MEMBASE:
4218 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4219 if (sig_ret->type == MONO_TYPE_R4) {
4220 if (IS_HARD_FLOAT) {
4221 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4223 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4224 ARM_CVTS (code, ins->dreg, ins->dreg);
4227 if (IS_HARD_FLOAT) {
4228 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4230 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4237 case OP_RCALL_MEMBASE: {
4242 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4243 g_assert (sig_ret->type == MONO_TYPE_R4);
4244 if (IS_HARD_FLOAT) {
4245 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4247 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4248 ARM_CPYS (code, ins->dreg, ins->dreg);
4260 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4265 guint8 *code = cfg->native_code + cfg->code_len;
4266 MonoInst *last_ins = NULL;
4267 guint last_offset = 0;
4269 int imm8, rot_amount;
4271 /* we don't align basic blocks of loops on arm */
4273 if (cfg->verbose_level > 2)
4274 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4276 cpos = bb->max_offset;
4278 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4279 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4280 //g_assert (!mono_compile_aot);
4283 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4284 /* this is not thread save, but good enough */
4285 /* fixme: howto handle overflows? */
4286 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4289 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4290 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4291 (gpointer)"mono_break");
4292 code = emit_call_seq (cfg, code);
4295 MONO_BB_FOR_EACH_INS (bb, ins) {
4296 offset = code - cfg->native_code;
4298 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4300 if (offset > (cfg->code_size - max_len - 16)) {
4301 cfg->code_size *= 2;
4302 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4303 code = cfg->native_code + offset;
4305 // if (ins->cil_code)
4306 // g_print ("cil code\n");
4307 mono_debug_record_line_number (cfg, ins, offset);
4309 switch (ins->opcode) {
4310 case OP_MEMORY_BARRIER:
4312 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4313 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4317 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4319 case OP_TLS_GET_REG:
4320 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4323 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4325 case OP_TLS_SET_REG:
4326 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4328 case OP_ATOMIC_EXCHANGE_I4:
4329 case OP_ATOMIC_CAS_I4:
4330 case OP_ATOMIC_ADD_I4: {
4334 g_assert (v7_supported);
4337 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4339 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4341 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4345 g_assert (cfg->arch.atomic_tmp_offset != -1);
4346 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4348 switch (ins->opcode) {
4349 case OP_ATOMIC_EXCHANGE_I4:
4351 ARM_DMB (code, ARM_DMB_SY);
4352 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4353 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4354 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4356 ARM_B_COND (code, ARMCOND_NE, 0);
4357 arm_patch (buf [1], buf [0]);
4359 case OP_ATOMIC_CAS_I4:
4360 ARM_DMB (code, ARM_DMB_SY);
4362 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4363 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4365 ARM_B_COND (code, ARMCOND_NE, 0);
4366 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4367 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4369 ARM_B_COND (code, ARMCOND_NE, 0);
4370 arm_patch (buf [2], buf [0]);
4371 arm_patch (buf [1], code);
4373 case OP_ATOMIC_ADD_I4:
4375 ARM_DMB (code, ARM_DMB_SY);
4376 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4377 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4378 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4379 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4381 ARM_B_COND (code, ARMCOND_NE, 0);
4382 arm_patch (buf [1], buf [0]);
4385 g_assert_not_reached ();
4388 ARM_DMB (code, ARM_DMB_SY);
4389 if (tmpreg != ins->dreg)
4390 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4391 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4394 case OP_ATOMIC_LOAD_I1:
4395 case OP_ATOMIC_LOAD_U1:
4396 case OP_ATOMIC_LOAD_I2:
4397 case OP_ATOMIC_LOAD_U2:
4398 case OP_ATOMIC_LOAD_I4:
4399 case OP_ATOMIC_LOAD_U4:
4400 case OP_ATOMIC_LOAD_R4:
4401 case OP_ATOMIC_LOAD_R8: {
4402 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4403 ARM_DMB (code, ARM_DMB_SY);
4405 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4407 switch (ins->opcode) {
4408 case OP_ATOMIC_LOAD_I1:
4409 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4411 case OP_ATOMIC_LOAD_U1:
4412 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4414 case OP_ATOMIC_LOAD_I2:
4415 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4417 case OP_ATOMIC_LOAD_U2:
4418 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4420 case OP_ATOMIC_LOAD_I4:
4421 case OP_ATOMIC_LOAD_U4:
4422 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4424 case OP_ATOMIC_LOAD_R4:
4426 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4427 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4429 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4430 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4431 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4432 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4433 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4436 case OP_ATOMIC_LOAD_R8:
4437 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4438 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4442 ARM_DMB (code, ARM_DMB_SY);
4445 case OP_ATOMIC_STORE_I1:
4446 case OP_ATOMIC_STORE_U1:
4447 case OP_ATOMIC_STORE_I2:
4448 case OP_ATOMIC_STORE_U2:
4449 case OP_ATOMIC_STORE_I4:
4450 case OP_ATOMIC_STORE_U4:
4451 case OP_ATOMIC_STORE_R4:
4452 case OP_ATOMIC_STORE_R8: {
4453 ARM_DMB (code, ARM_DMB_SY);
4455 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4457 switch (ins->opcode) {
4458 case OP_ATOMIC_STORE_I1:
4459 case OP_ATOMIC_STORE_U1:
4460 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4462 case OP_ATOMIC_STORE_I2:
4463 case OP_ATOMIC_STORE_U2:
4464 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4466 case OP_ATOMIC_STORE_I4:
4467 case OP_ATOMIC_STORE_U4:
4468 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4470 case OP_ATOMIC_STORE_R4:
4472 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4473 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4475 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4476 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4477 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4478 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4479 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4482 case OP_ATOMIC_STORE_R8:
4483 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4484 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4488 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4489 ARM_DMB (code, ARM_DMB_SY);
4493 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4494 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4497 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4498 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4500 case OP_STOREI1_MEMBASE_IMM:
4501 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4502 g_assert (arm_is_imm12 (ins->inst_offset));
4503 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4505 case OP_STOREI2_MEMBASE_IMM:
4506 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4507 g_assert (arm_is_imm8 (ins->inst_offset));
4508 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4510 case OP_STORE_MEMBASE_IMM:
4511 case OP_STOREI4_MEMBASE_IMM:
4512 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4513 g_assert (arm_is_imm12 (ins->inst_offset));
4514 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4516 case OP_STOREI1_MEMBASE_REG:
4517 g_assert (arm_is_imm12 (ins->inst_offset));
4518 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4520 case OP_STOREI2_MEMBASE_REG:
4521 g_assert (arm_is_imm8 (ins->inst_offset));
4522 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4524 case OP_STORE_MEMBASE_REG:
4525 case OP_STOREI4_MEMBASE_REG:
4526 /* this case is special, since it happens for spill code after lowering has been called */
4527 if (arm_is_imm12 (ins->inst_offset)) {
4528 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4530 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4531 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4534 case OP_STOREI1_MEMINDEX:
4535 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4537 case OP_STOREI2_MEMINDEX:
4538 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4540 case OP_STORE_MEMINDEX:
4541 case OP_STOREI4_MEMINDEX:
4542 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4545 g_assert_not_reached ();
4547 case OP_LOAD_MEMINDEX:
4548 case OP_LOADI4_MEMINDEX:
4549 case OP_LOADU4_MEMINDEX:
4550 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4552 case OP_LOADI1_MEMINDEX:
4553 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4555 case OP_LOADU1_MEMINDEX:
4556 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4558 case OP_LOADI2_MEMINDEX:
4559 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4561 case OP_LOADU2_MEMINDEX:
4562 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4564 case OP_LOAD_MEMBASE:
4565 case OP_LOADI4_MEMBASE:
4566 case OP_LOADU4_MEMBASE:
4567 /* this case is special, since it happens for spill code after lowering has been called */
4568 if (arm_is_imm12 (ins->inst_offset)) {
4569 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4571 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4572 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4575 case OP_LOADI1_MEMBASE:
4576 g_assert (arm_is_imm8 (ins->inst_offset));
4577 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4579 case OP_LOADU1_MEMBASE:
4580 g_assert (arm_is_imm12 (ins->inst_offset));
4581 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4583 case OP_LOADU2_MEMBASE:
4584 g_assert (arm_is_imm8 (ins->inst_offset));
4585 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4587 case OP_LOADI2_MEMBASE:
4588 g_assert (arm_is_imm8 (ins->inst_offset));
4589 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4591 case OP_ICONV_TO_I1:
4592 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4593 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4595 case OP_ICONV_TO_I2:
4596 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4597 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4599 case OP_ICONV_TO_U1:
4600 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4602 case OP_ICONV_TO_U2:
4603 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4604 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4608 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4610 case OP_COMPARE_IMM:
4611 case OP_ICOMPARE_IMM:
4612 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4613 g_assert (imm8 >= 0);
4614 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4618 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4619 * So instead of emitting a trap, we emit a call a C function and place a
4622 //*(int*)code = 0xef9f0001;
4625 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4626 (gpointer)"mono_break");
4627 code = emit_call_seq (cfg, code);
4629 case OP_RELAXED_NOP:
4634 case OP_DUMMY_STORE:
4635 case OP_DUMMY_ICONST:
4636 case OP_DUMMY_R8CONST:
4637 case OP_NOT_REACHED:
4640 case OP_IL_SEQ_POINT:
4641 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4643 case OP_SEQ_POINT: {
4645 MonoInst *info_var = cfg->arch.seq_point_info_var;
4646 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4647 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
4648 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4649 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4651 int dreg = ARMREG_LR;
4653 if (cfg->soft_breakpoints) {
4654 g_assert (!cfg->compile_aot);
4658 * For AOT, we use one got slot per method, which will point to a
4659 * SeqPointInfo structure, containing all the information required
4660 * by the code below.
4662 if (cfg->compile_aot) {
4663 g_assert (info_var);
4664 g_assert (info_var->opcode == OP_REGOFFSET);
4665 g_assert (arm_is_imm12 (info_var->inst_offset));
4668 if (!cfg->soft_breakpoints) {
4670 * Read from the single stepping trigger page. This will cause a
4671 * SIGSEGV when single stepping is enabled.
4672 * We do this _before_ the breakpoint, so single stepping after
4673 * a breakpoint is hit will step to the next IL offset.
4675 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4678 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4679 if (cfg->soft_breakpoints) {
4680 /* Load the address of the sequence point trigger variable. */
4683 g_assert (var->opcode == OP_REGOFFSET);
4684 g_assert (arm_is_imm12 (var->inst_offset));
4685 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4687 /* Read the value and check whether it is non-zero. */
4688 ARM_LDR_IMM (code, dreg, dreg, 0);
4689 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4691 /* Load the address of the sequence point method. */
4692 var = ss_method_var;
4694 g_assert (var->opcode == OP_REGOFFSET);
4695 g_assert (arm_is_imm12 (var->inst_offset));
4696 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4698 /* Call it conditionally. */
4699 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4701 if (cfg->compile_aot) {
4702 /* Load the trigger page addr from the variable initialized in the prolog */
4703 var = ss_trigger_page_var;
4705 g_assert (var->opcode == OP_REGOFFSET);
4706 g_assert (arm_is_imm12 (var->inst_offset));
4707 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4709 #ifdef USE_JUMP_TABLES
4710 gpointer *jte = mono_jumptable_add_entry ();
4711 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4712 jte [0] = ss_trigger_page;
4714 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4716 *(int*)code = (int)ss_trigger_page;
4720 ARM_LDR_IMM (code, dreg, dreg, 0);
4724 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4726 if (cfg->soft_breakpoints) {
4727 /* Load the address of the breakpoint method into ip. */
4728 var = bp_method_var;
4730 g_assert (var->opcode == OP_REGOFFSET);
4731 g_assert (arm_is_imm12 (var->inst_offset));
4732 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4735 * A placeholder for a possible breakpoint inserted by
4736 * mono_arch_set_breakpoint ().
4739 } else if (cfg->compile_aot) {
4740 guint32 offset = code - cfg->native_code;
4743 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4744 /* Add the offset */
4745 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4746 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4747 if (arm_is_imm12 ((int)val)) {
4748 ARM_LDR_IMM (code, dreg, dreg, val);
4750 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4752 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4754 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4755 g_assert (!(val & 0xFF000000));
4757 ARM_LDR_IMM (code, dreg, dreg, 0);
4759 /* What is faster, a branch or a load ? */
4760 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4761 /* The breakpoint instruction */
4762 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4765 * A placeholder for a possible breakpoint inserted by
4766 * mono_arch_set_breakpoint ().
4768 for (i = 0; i < 4; ++i)
4773 * Add an additional nop so skipping the bp doesn't cause the ip to point
4774 * to another IL offset.
4782 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4785 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4789 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4792 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4793 g_assert (imm8 >= 0);
4794 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4798 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4799 g_assert (imm8 >= 0);
4800 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4804 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4805 g_assert (imm8 >= 0);
4806 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4809 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4810 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4812 case OP_IADD_OVF_UN:
4813 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4814 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4817 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4818 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4820 case OP_ISUB_OVF_UN:
4821 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4822 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4824 case OP_ADD_OVF_CARRY:
4825 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4826 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4828 case OP_ADD_OVF_UN_CARRY:
4829 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4830 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4832 case OP_SUB_OVF_CARRY:
4833 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4834 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4836 case OP_SUB_OVF_UN_CARRY:
4837 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4838 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4842 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4845 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4846 g_assert (imm8 >= 0);
4847 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4850 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4854 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4858 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4859 g_assert (imm8 >= 0);
4860 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4864 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4865 g_assert (imm8 >= 0);
4866 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4868 case OP_ARM_RSBS_IMM:
4869 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4870 g_assert (imm8 >= 0);
4871 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4873 case OP_ARM_RSC_IMM:
4874 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4875 g_assert (imm8 >= 0);
4876 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4879 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4883 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4884 g_assert (imm8 >= 0);
4885 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4888 g_assert (v7s_supported || v7k_supported);
4889 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4892 g_assert (v7s_supported || v7k_supported);
4893 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4896 g_assert (v7s_supported || v7k_supported);
4897 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4898 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4901 g_assert (v7s_supported || v7k_supported);
4902 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4903 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4907 g_assert_not_reached ();
4909 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4913 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4914 g_assert (imm8 >= 0);
4915 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4918 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4922 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4923 g_assert (imm8 >= 0);
4924 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4927 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4932 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4933 else if (ins->dreg != ins->sreg1)
4934 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4937 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4942 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4943 else if (ins->dreg != ins->sreg1)
4944 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4947 case OP_ISHR_UN_IMM:
4949 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4950 else if (ins->dreg != ins->sreg1)
4951 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4954 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4957 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4960 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4963 if (ins->dreg == ins->sreg2)
4964 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4966 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4969 g_assert_not_reached ();
4972 /* FIXME: handle ovf/ sreg2 != dreg */
4973 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4974 /* FIXME: MUL doesn't set the C/O flags on ARM */
4976 case OP_IMUL_OVF_UN:
4977 /* FIXME: handle ovf/ sreg2 != dreg */
4978 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4979 /* FIXME: MUL doesn't set the C/O flags on ARM */
4982 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4985 /* Load the GOT offset */
4986 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4987 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4989 *(gpointer*)code = NULL;
4991 /* Load the value from the GOT */
4992 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4994 case OP_OBJC_GET_SELECTOR:
4995 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4996 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4998 *(gpointer*)code = NULL;
5000 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
5002 case OP_ICONV_TO_I4:
5003 case OP_ICONV_TO_U4:
5005 if (ins->dreg != ins->sreg1)
5006 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5009 int saved = ins->sreg2;
5010 if (ins->sreg2 == ARM_LSW_REG) {
5011 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
5014 if (ins->sreg1 != ARM_LSW_REG)
5015 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
5016 if (saved != ARM_MSW_REG)
5017 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
5021 if (IS_VFP && ins->dreg != ins->sreg1)
5022 ARM_CPYD (code, ins->dreg, ins->sreg1);
5025 if (IS_VFP && ins->dreg != ins->sreg1)
5026 ARM_CPYS (code, ins->dreg, ins->sreg1);
5028 case OP_MOVE_F_TO_I4:
5030 ARM_FMRS (code, ins->dreg, ins->sreg1);
5032 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5033 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5034 ARM_FMRS (code, ins->dreg, vfp_scratch1);
5035 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5038 case OP_MOVE_I4_TO_F:
5040 ARM_FMSR (code, ins->dreg, ins->sreg1);
5042 ARM_FMSR (code, ins->dreg, ins->sreg1);
5043 ARM_CVTS (code, ins->dreg, ins->dreg);
5046 case OP_FCONV_TO_R4:
5049 ARM_CVTD (code, ins->dreg, ins->sreg1);
5051 ARM_CVTD (code, ins->dreg, ins->sreg1);
5052 ARM_CVTS (code, ins->dreg, ins->dreg);
5057 MonoCallInst *call = (MonoCallInst*)ins;
5060 * The stack looks like the following:
5061 * <caller argument area>
5064 * <callee argument area>
5065 * Need to copy the arguments from the callee argument area to
5066 * the caller argument area, and pop the frame.
5068 if (call->stack_usage) {
5069 int i, prev_sp_offset = 0;
5071 /* Compute size of saved registers restored below */
5073 prev_sp_offset = 2 * 4;
5075 prev_sp_offset = 1 * 4;
5076 for (i = 0; i < 16; ++i) {
5077 if (cfg->used_int_regs & (1 << i))
5078 prev_sp_offset += 4;
5081 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5083 /* Copy arguments on the stack to our argument area */
5084 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5085 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5086 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5091 * Keep in sync with mono_arch_emit_epilog
5093 g_assert (!cfg->method->save_lmf);
5095 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5097 if (cfg->used_int_regs)
5098 ARM_POP (code, cfg->used_int_regs);
5099 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5101 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5104 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5105 if (cfg->compile_aot) {
5106 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5108 *(gpointer*)code = NULL;
5110 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5112 code = mono_arm_patchable_b (code, ARMCOND_AL);
5113 cfg->thunk_area += THUNK_SIZE;
5118 /* ensure ins->sreg1 is not NULL */
5119 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5122 g_assert (cfg->sig_cookie < 128);
5123 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5124 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5134 call = (MonoCallInst*)ins;
5137 code = emit_float_args (cfg, call, code, &max_len, &offset);
5139 if (ins->flags & MONO_INST_HAS_METHOD)
5140 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5142 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5143 code = emit_call_seq (cfg, code);
5144 ins->flags |= MONO_INST_GC_CALLSITE;
5145 ins->backend.pc_offset = code - cfg->native_code;
5146 code = emit_move_return_value (cfg, ins, code);
5153 case OP_VOIDCALL_REG:
5156 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5158 code = emit_call_reg (code, ins->sreg1);
5159 ins->flags |= MONO_INST_GC_CALLSITE;
5160 ins->backend.pc_offset = code - cfg->native_code;
5161 code = emit_move_return_value (cfg, ins, code);
5163 case OP_FCALL_MEMBASE:
5164 case OP_RCALL_MEMBASE:
5165 case OP_LCALL_MEMBASE:
5166 case OP_VCALL_MEMBASE:
5167 case OP_VCALL2_MEMBASE:
5168 case OP_VOIDCALL_MEMBASE:
5169 case OP_CALL_MEMBASE: {
5170 g_assert (ins->sreg1 != ARMREG_LR);
5171 call = (MonoCallInst*)ins;
5174 code = emit_float_args (cfg, call, code, &max_len, &offset);
5175 if (!arm_is_imm12 (ins->inst_offset))
5176 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5177 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5178 if (!arm_is_imm12 (ins->inst_offset))
5179 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5181 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5182 ins->flags |= MONO_INST_GC_CALLSITE;
5183 ins->backend.pc_offset = code - cfg->native_code;
5184 code = emit_move_return_value (cfg, ins, code);
5187 case OP_GENERIC_CLASS_INIT: {
5188 static int byte_offset = -1;
5189 static guint8 bitmask;
5193 if (byte_offset < 0)
5194 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5196 g_assert (arm_is_imm8 (byte_offset));
5197 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5198 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5199 g_assert (imm8 >= 0);
5200 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5201 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5203 ARM_B_COND (code, ARMCOND_NE, 0);
5205 /* Uninitialized case */
5206 g_assert (ins->sreg1 == ARMREG_R0);
5208 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5209 (gpointer)"mono_generic_class_init");
5210 code = emit_call_seq (cfg, code);
5212 /* Initialized case */
5213 arm_patch (jump, code);
5217 /* round the size to 8 bytes */
5218 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5219 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5220 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5221 /* memzero the area: dreg holds the size, sp is the pointer */
5222 if (ins->flags & MONO_INST_INIT) {
5223 guint8 *start_loop, *branch_to_cond;
5224 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5225 branch_to_cond = code;
5228 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5229 arm_patch (branch_to_cond, code);
5230 /* decrement by 4 and set flags */
5231 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5232 ARM_B_COND (code, ARMCOND_GE, 0);
5233 arm_patch (code - 4, start_loop);
5235 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5236 if (cfg->param_area)
5237 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5242 MonoInst *var = cfg->dyn_call_var;
5244 g_assert (var->opcode == OP_REGOFFSET);
5245 g_assert (arm_is_imm12 (var->inst_offset));
5247 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5248 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5250 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5252 /* Save args buffer */
5253 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5255 /* Set stack slots using R0 as scratch reg */
5256 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5257 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5258 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5259 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5262 /* Set argument registers */
5263 for (i = 0; i < PARAM_REGS; ++i)
5264 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5267 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5268 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5271 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5272 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5273 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5277 if (ins->sreg1 != ARMREG_R0)
5278 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5279 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5280 (gpointer)"mono_arch_throw_exception");
5281 code = emit_call_seq (cfg, code);
5285 if (ins->sreg1 != ARMREG_R0)
5286 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5287 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5288 (gpointer)"mono_arch_rethrow_exception");
5289 code = emit_call_seq (cfg, code);
5292 case OP_START_HANDLER: {
5293 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5294 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5297 /* Reserve a param area, see filter-stack.exe */
5299 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5300 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5302 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5303 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5307 if (arm_is_imm12 (spvar->inst_offset)) {
5308 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5310 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5311 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5315 case OP_ENDFILTER: {
5316 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5317 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5320 /* Free the param area */
5322 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5323 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5325 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5326 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5330 if (ins->sreg1 != ARMREG_R0)
5331 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5332 if (arm_is_imm12 (spvar->inst_offset)) {
5333 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5335 g_assert (ARMREG_IP != spvar->inst_basereg);
5336 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5337 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5339 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5342 case OP_ENDFINALLY: {
5343 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5344 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5347 /* Free the param area */
5349 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5350 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5352 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5353 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5357 if (arm_is_imm12 (spvar->inst_offset)) {
5358 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5360 g_assert (ARMREG_IP != spvar->inst_basereg);
5361 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5362 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5364 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5367 case OP_CALL_HANDLER:
5368 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5369 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5370 cfg->thunk_area += THUNK_SIZE;
5371 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5374 if (ins->dreg != ARMREG_R0)
5375 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5379 ins->inst_c0 = code - cfg->native_code;
5382 /*if (ins->inst_target_bb->native_offset) {
5384 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5386 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5387 code = mono_arm_patchable_b (code, ARMCOND_AL);
5391 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5395 * In the normal case we have:
5396 * ldr pc, [pc, ins->sreg1 << 2]
5399 * ldr lr, [pc, ins->sreg1 << 2]
5401 * After follows the data.
5402 * FIXME: add aot support.
5404 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5405 #ifdef USE_JUMP_TABLES
5407 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5408 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5409 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5413 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5414 if (offset + max_len > (cfg->code_size - 16)) {
5415 cfg->code_size += max_len;
5416 cfg->code_size *= 2;
5417 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5418 code = cfg->native_code + offset;
5420 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5422 code += 4 * GPOINTER_TO_INT (ins->klass);
5427 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5428 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5432 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5433 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5437 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5438 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5442 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5443 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5447 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5448 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5451 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5452 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5455 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5456 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5459 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5460 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5463 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5464 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5467 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5468 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5470 case OP_COND_EXC_EQ:
5471 case OP_COND_EXC_NE_UN:
5472 case OP_COND_EXC_LT:
5473 case OP_COND_EXC_LT_UN:
5474 case OP_COND_EXC_GT:
5475 case OP_COND_EXC_GT_UN:
5476 case OP_COND_EXC_GE:
5477 case OP_COND_EXC_GE_UN:
5478 case OP_COND_EXC_LE:
5479 case OP_COND_EXC_LE_UN:
5480 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5482 case OP_COND_EXC_IEQ:
5483 case OP_COND_EXC_INE_UN:
5484 case OP_COND_EXC_ILT:
5485 case OP_COND_EXC_ILT_UN:
5486 case OP_COND_EXC_IGT:
5487 case OP_COND_EXC_IGT_UN:
5488 case OP_COND_EXC_IGE:
5489 case OP_COND_EXC_IGE_UN:
5490 case OP_COND_EXC_ILE:
5491 case OP_COND_EXC_ILE_UN:
5492 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5495 case OP_COND_EXC_IC:
5496 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5498 case OP_COND_EXC_OV:
5499 case OP_COND_EXC_IOV:
5500 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5502 case OP_COND_EXC_NC:
5503 case OP_COND_EXC_INC:
5504 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5506 case OP_COND_EXC_NO:
5507 case OP_COND_EXC_INO:
5508 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5520 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5523 /* floating point opcodes */
5525 if (cfg->compile_aot) {
5526 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5528 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5530 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5533 /* FIXME: we can optimize the imm load by dealing with part of
5534 * the displacement in LDFD (aligning to 512).
5536 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5537 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5541 if (cfg->compile_aot) {
5542 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5544 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5547 ARM_CVTS (code, ins->dreg, ins->dreg);
5549 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5550 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5552 ARM_CVTS (code, ins->dreg, ins->dreg);
5555 case OP_STORER8_MEMBASE_REG:
5556 /* This is generated by the local regalloc pass which runs after the lowering pass */
5557 if (!arm_is_fpimm8 (ins->inst_offset)) {
5558 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5559 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5560 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5562 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5565 case OP_LOADR8_MEMBASE:
5566 /* This is generated by the local regalloc pass which runs after the lowering pass */
5567 if (!arm_is_fpimm8 (ins->inst_offset)) {
5568 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5569 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5570 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5572 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5575 case OP_STORER4_MEMBASE_REG:
5576 g_assert (arm_is_fpimm8 (ins->inst_offset));
5578 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5580 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5581 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5582 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5583 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5586 case OP_LOADR4_MEMBASE:
5588 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5590 g_assert (arm_is_fpimm8 (ins->inst_offset));
5591 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5592 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5593 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5594 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5597 case OP_ICONV_TO_R_UN: {
5598 g_assert_not_reached ();
5601 case OP_ICONV_TO_R4:
5603 ARM_FMSR (code, ins->dreg, ins->sreg1);
5604 ARM_FSITOS (code, ins->dreg, ins->dreg);
5606 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5607 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5608 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5609 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5610 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5613 case OP_ICONV_TO_R8:
5614 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5615 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5616 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5617 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5621 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5622 if (sig_ret->type == MONO_TYPE_R4) {
5624 g_assert (!IS_HARD_FLOAT);
5625 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5627 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5630 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5634 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5636 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5640 case OP_FCONV_TO_I1:
5641 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5643 case OP_FCONV_TO_U1:
5644 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5646 case OP_FCONV_TO_I2:
5647 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5649 case OP_FCONV_TO_U2:
5650 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5652 case OP_FCONV_TO_I4:
5654 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5656 case OP_FCONV_TO_U4:
5658 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5660 case OP_FCONV_TO_I8:
5661 case OP_FCONV_TO_U8:
5662 g_assert_not_reached ();
5663 /* Implemented as helper calls */
5665 case OP_LCONV_TO_R_UN:
5666 g_assert_not_reached ();
5667 /* Implemented as helper calls */
5669 case OP_LCONV_TO_OVF_I4_2: {
5670 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5672 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5675 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5676 high_bit_not_set = code;
5677 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5679 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5680 valid_negative = code;
5681 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5682 invalid_negative = code;
5683 ARM_B_COND (code, ARMCOND_AL, 0);
5685 arm_patch (high_bit_not_set, code);
5687 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5688 valid_positive = code;
5689 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5691 arm_patch (invalid_negative, code);
5692 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5694 arm_patch (valid_negative, code);
5695 arm_patch (valid_positive, code);
5697 if (ins->dreg != ins->sreg1)
5698 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5702 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5705 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5708 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5711 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5714 ARM_NEGD (code, ins->dreg, ins->sreg1);
5718 g_assert_not_reached ();
5722 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5728 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5733 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5736 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5737 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5741 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5744 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5745 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5749 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5752 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5753 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5754 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5758 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5761 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5762 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5766 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5769 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5770 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5771 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5775 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5778 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5779 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5783 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5786 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5787 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5791 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5794 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5795 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5798 /* ARM FPA flags table:
5799 * N Less than ARMCOND_MI
5800 * Z Equal ARMCOND_EQ
5801 * C Greater Than or Equal ARMCOND_CS
5802 * V Unordered ARMCOND_VS
5805 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5808 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5811 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5814 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5815 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5821 g_assert_not_reached ();
5825 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5827 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5828 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5829 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5833 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5834 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5839 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5840 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5842 #ifdef USE_JUMP_TABLES
5844 gpointer *jte = mono_jumptable_add_entries (2);
5845 jte [0] = GUINT_TO_POINTER (0xffffffff);
5846 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5847 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5848 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5851 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5852 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5854 *(guint32*)code = 0xffffffff;
5856 *(guint32*)code = 0x7fefffff;
5859 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5861 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5862 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5864 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5865 ARM_CPYD (code, ins->dreg, ins->sreg1);
5867 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5868 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5873 case OP_RCONV_TO_I1:
5874 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5876 case OP_RCONV_TO_U1:
5877 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5879 case OP_RCONV_TO_I2:
5880 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5882 case OP_RCONV_TO_U2:
5883 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5885 case OP_RCONV_TO_I4:
5886 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5888 case OP_RCONV_TO_U4:
5889 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5891 case OP_RCONV_TO_R4:
5893 if (ins->dreg != ins->sreg1)
5894 ARM_CPYS (code, ins->dreg, ins->sreg1);
5896 case OP_RCONV_TO_R8:
5898 ARM_CVTS (code, ins->dreg, ins->sreg1);
5901 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5904 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5907 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5910 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5913 ARM_NEGS (code, ins->dreg, ins->sreg1);
5917 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5920 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5921 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5925 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5928 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5929 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5933 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5936 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5937 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5938 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5942 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5945 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5946 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5950 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5953 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5954 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5955 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5959 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5962 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5963 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5967 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5970 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5971 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5975 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5978 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5979 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5982 case OP_GC_LIVENESS_DEF:
5983 case OP_GC_LIVENESS_USE:
5984 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5985 ins->backend.pc_offset = code - cfg->native_code;
5987 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5988 ins->backend.pc_offset = code - cfg->native_code;
5989 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5991 case OP_GC_SAFE_POINT: {
5992 #if defined (USE_COOP_GC)
5993 const char *polling_func = NULL;
5996 polling_func = "mono_threads_state_poll";
5997 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5998 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
6000 ARM_B_COND (code, ARMCOND_EQ, 0);
6001 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
6002 code = emit_call_seq (cfg, code);
6003 arm_patch (buf [0], code);
6009 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6010 g_assert_not_reached ();
6013 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
6014 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
6015 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6016 g_assert_not_reached ();
6022 last_offset = offset;
6025 cfg->code_len = code - cfg->native_code;
6028 #endif /* DISABLE_JIT */
6031 mono_arch_register_lowlevel_calls (void)
6033 /* The signature doesn't matter */
6034 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
6035 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
6036 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
6038 #ifndef MONO_CROSS_COMPILE
6039 if (mono_arm_have_tls_get ()) {
6040 if (mono_arm_have_fast_tls ()) {
6041 mono_register_jit_icall (mono_fast_get_tls_key, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
6042 mono_register_jit_icall (mono_fast_set_tls_key, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
6044 mono_tramp_info_register (
6045 mono_tramp_info_create (
6047 (guint8*)mono_fast_get_tls_key,
6048 (guint8*)mono_fast_get_tls_key_end - (guint8*)mono_fast_get_tls_key,
6050 mono_arch_get_cie_program ()
6054 mono_tramp_info_register (
6055 mono_tramp_info_create (
6057 (guint8*)mono_fast_set_tls_key,
6058 (guint8*)mono_fast_set_tls_key_end - (guint8*)mono_fast_set_tls_key,
6060 mono_arch_get_cie_program ()
6065 g_warning ("No fast tls on device. Using fallbacks.");
6066 mono_register_jit_icall (mono_fallback_get_tls_key, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
6067 mono_register_jit_icall (mono_fallback_set_tls_key, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
6073 #define patch_lis_ori(ip,val) do {\
6074 guint16 *__lis_ori = (guint16*)(ip); \
6075 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
6076 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
6080 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6082 unsigned char *ip = ji->ip.i + code;
6084 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6088 case MONO_PATCH_INFO_SWITCH: {
6089 #ifdef USE_JUMP_TABLES
6090 gpointer *jt = mono_jumptable_get_entry (ip);
6092 gpointer *jt = (gpointer*)(ip + 8);
6095 /* jt is the inlined jump table, 2 instructions after ip
6096 * In the normal case we store the absolute addresses,
6097 * otherwise the displacements.
6099 for (i = 0; i < ji->data.table->table_size; i++)
6100 jt [i] = code + (int)ji->data.table->table [i];
6103 case MONO_PATCH_INFO_IP:
6104 g_assert_not_reached ();
6105 patch_lis_ori (ip, ip);
6107 case MONO_PATCH_INFO_METHOD_REL:
6108 g_assert_not_reached ();
6109 *((gpointer *)(ip)) = target;
6111 case MONO_PATCH_INFO_METHODCONST:
6112 case MONO_PATCH_INFO_CLASS:
6113 case MONO_PATCH_INFO_IMAGE:
6114 case MONO_PATCH_INFO_FIELD:
6115 case MONO_PATCH_INFO_VTABLE:
6116 case MONO_PATCH_INFO_IID:
6117 case MONO_PATCH_INFO_SFLDA:
6118 case MONO_PATCH_INFO_LDSTR:
6119 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6120 case MONO_PATCH_INFO_LDTOKEN:
6121 g_assert_not_reached ();
6122 /* from OP_AOTCONST : lis + ori */
6123 patch_lis_ori (ip, target);
6125 case MONO_PATCH_INFO_R4:
6126 case MONO_PATCH_INFO_R8:
6127 g_assert_not_reached ();
6128 *((gconstpointer *)(ip + 2)) = target;
6130 case MONO_PATCH_INFO_EXC_NAME:
6131 g_assert_not_reached ();
6132 *((gconstpointer *)(ip + 1)) = target;
6134 case MONO_PATCH_INFO_NONE:
6135 case MONO_PATCH_INFO_BB_OVF:
6136 case MONO_PATCH_INFO_EXC_OVF:
6137 /* everything is dealt with at epilog output time */
6140 arm_patch_general (cfg, domain, ip, target);
6146 mono_arm_unaligned_stack (MonoMethod *method)
6148 g_assert_not_reached ();
6154 * Stack frame layout:
6156 * ------------------- fp
6157 * MonoLMF structure or saved registers
6158 * -------------------
6160 * -------------------
6162 * -------------------
6163 * optional 8 bytes for tracing
6164 * -------------------
6165 * param area size is cfg->param_area
6166 * ------------------- sp
6169 mono_arch_emit_prolog (MonoCompile *cfg)
6171 MonoMethod *method = cfg->method;
6173 MonoMethodSignature *sig;
6175 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6180 int prev_sp_offset, reg_offset;
6182 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6185 sig = mono_method_signature (method);
6186 cfg->code_size = 256 + sig->param_count * 64;
6187 code = cfg->native_code = g_malloc (cfg->code_size);
6189 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6191 alloc_size = cfg->stack_offset;
6197 * The iphone uses R7 as the frame pointer, and it points at the saved
6202 * We can't use r7 as a frame pointer since it points into the middle of
6203 * the frame, so we keep using our own frame pointer.
6204 * FIXME: Optimize this.
6206 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6207 prev_sp_offset += 8; /* r7 and lr */
6208 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6209 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6210 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6213 if (!method->save_lmf) {
6215 /* No need to push LR again */
6216 if (cfg->used_int_regs)
6217 ARM_PUSH (code, cfg->used_int_regs);
6219 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6220 prev_sp_offset += 4;
6222 for (i = 0; i < 16; ++i) {
6223 if (cfg->used_int_regs & (1 << i))
6224 prev_sp_offset += 4;
6226 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6228 for (i = 0; i < 16; ++i) {
6229 if ((cfg->used_int_regs & (1 << i))) {
6230 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6231 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6236 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6237 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6239 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6240 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6243 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6244 ARM_PUSH (code, 0x5ff0);
6245 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6246 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6248 for (i = 0; i < 16; ++i) {
6249 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6250 /* The original r7 is saved at the start */
6251 if (!(iphone_abi && i == ARMREG_R7))
6252 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6256 g_assert (reg_offset == 4 * 10);
6257 pos += sizeof (MonoLMF) - (4 * 10);
6261 orig_alloc_size = alloc_size;
6262 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6263 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6264 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6265 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6268 /* the stack used in the pushed regs */
6269 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6270 cfg->stack_usage = alloc_size;
6272 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6273 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6275 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6276 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6278 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6280 if (cfg->frame_reg != ARMREG_SP) {
6281 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6282 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6284 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6285 prev_sp_offset += alloc_size;
6287 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6288 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6290 /* compute max_offset in order to use short forward jumps
6291 * we could skip do it on arm because the immediate displacement
6292 * for jumps is large enough, it may be useful later for constant pools
6295 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6296 MonoInst *ins = bb->code;
6297 bb->max_offset = max_offset;
6299 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6302 MONO_BB_FOR_EACH_INS (bb, ins)
6303 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6306 /* stack alignment check */
6310 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6311 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6312 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6313 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6315 ARM_B_COND (code, ARMCOND_EQ, 0);
6316 if (cfg->compile_aot)
6317 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6319 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6320 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6321 code = emit_call_seq (cfg, code);
6322 arm_patch (buf [0], code);
6326 /* store runtime generic context */
6327 if (cfg->rgctx_var) {
6328 MonoInst *ins = cfg->rgctx_var;
6330 g_assert (ins->opcode == OP_REGOFFSET);
6332 if (arm_is_imm12 (ins->inst_offset)) {
6333 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6335 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6336 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6340 /* load arguments allocated to register from the stack */
6343 cinfo = get_call_info (NULL, sig);
6345 if (cinfo->ret.storage == RegTypeStructByAddr) {
6346 ArgInfo *ainfo = &cinfo->ret;
6347 inst = cfg->vret_addr;
6348 g_assert (arm_is_imm12 (inst->inst_offset));
6349 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6352 if (sig->call_convention == MONO_CALL_VARARG) {
6353 ArgInfo *cookie = &cinfo->sig_cookie;
6355 /* Save the sig cookie address */
6356 g_assert (cookie->storage == RegTypeBase);
6358 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6359 g_assert (arm_is_imm12 (cfg->sig_cookie));
6360 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6361 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6364 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6365 ArgInfo *ainfo = cinfo->args + i;
6366 inst = cfg->args [pos];
6368 if (cfg->verbose_level > 2)
6369 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6371 if (inst->opcode == OP_REGVAR) {
6372 if (ainfo->storage == RegTypeGeneral)
6373 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6374 else if (ainfo->storage == RegTypeFP) {
6375 g_assert_not_reached ();
6376 } else if (ainfo->storage == RegTypeBase) {
6377 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6378 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6380 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6381 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6384 g_assert_not_reached ();
6386 if (cfg->verbose_level > 2)
6387 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6389 switch (ainfo->storage) {
6391 for (part = 0; part < ainfo->nregs; part ++) {
6392 if (ainfo->esize == 4)
6393 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6395 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6398 case RegTypeGeneral:
6399 case RegTypeIRegPair:
6400 case RegTypeGSharedVtInReg:
6401 switch (ainfo->size) {
6403 if (arm_is_imm12 (inst->inst_offset))
6404 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6406 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6407 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6411 if (arm_is_imm8 (inst->inst_offset)) {
6412 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6414 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6415 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6419 if (arm_is_imm12 (inst->inst_offset)) {
6420 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6422 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6423 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6425 if (arm_is_imm12 (inst->inst_offset + 4)) {
6426 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6428 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6429 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6433 if (arm_is_imm12 (inst->inst_offset)) {
6434 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6436 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6437 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6442 case RegTypeBaseGen:
6443 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6444 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6446 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6447 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6449 if (arm_is_imm12 (inst->inst_offset + 4)) {
6450 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6451 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6453 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6454 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6455 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6456 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6460 case RegTypeGSharedVtOnStack:
6461 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6462 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6464 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6465 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6468 switch (ainfo->size) {
6470 if (arm_is_imm8 (inst->inst_offset)) {
6471 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6473 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6474 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6478 if (arm_is_imm8 (inst->inst_offset)) {
6479 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6481 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6482 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6486 if (arm_is_imm12 (inst->inst_offset)) {
6487 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6489 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6490 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6492 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6493 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6495 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6496 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6498 if (arm_is_imm12 (inst->inst_offset + 4)) {
6499 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6501 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6502 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6506 if (arm_is_imm12 (inst->inst_offset)) {
6507 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6509 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6510 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6516 int imm8, rot_amount;
6518 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6519 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6520 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6522 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6524 if (ainfo->size == 8)
6525 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6527 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6530 case RegTypeStructByVal: {
6531 int doffset = inst->inst_offset;
6535 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6536 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6537 if (arm_is_imm12 (doffset)) {
6538 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6540 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6541 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6543 soffset += sizeof (gpointer);
6544 doffset += sizeof (gpointer);
6546 if (ainfo->vtsize) {
6547 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6548 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6549 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6553 case RegTypeStructByAddr:
6554 g_assert_not_reached ();
6555 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6556 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6558 g_assert_not_reached ();
6565 if (method->save_lmf)
6566 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6569 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6571 if (cfg->arch.seq_point_info_var) {
6572 MonoInst *ins = cfg->arch.seq_point_info_var;
6574 /* Initialize the variable from a GOT slot */
6575 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6576 #ifdef USE_JUMP_TABLES
6578 gpointer *jte = mono_jumptable_add_entry ();
6579 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6580 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6582 /** XXX: is it correct? */
6584 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6586 *(gpointer*)code = NULL;
6589 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6591 g_assert (ins->opcode == OP_REGOFFSET);
6593 if (arm_is_imm12 (ins->inst_offset)) {
6594 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6596 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6597 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6601 /* Initialize ss_trigger_page_var */
6602 if (!cfg->soft_breakpoints) {
6603 MonoInst *info_var = cfg->arch.seq_point_info_var;
6604 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6605 int dreg = ARMREG_LR;
6608 g_assert (info_var->opcode == OP_REGOFFSET);
6609 g_assert (arm_is_imm12 (info_var->inst_offset));
6611 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6612 /* Load the trigger page addr */
6613 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6614 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6618 if (cfg->arch.seq_point_read_var) {
6619 MonoInst *read_ins = cfg->arch.seq_point_read_var;
6620 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6621 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6622 #ifdef USE_JUMP_TABLES
6625 g_assert (read_ins->opcode == OP_REGOFFSET);
6626 g_assert (arm_is_imm12 (read_ins->inst_offset));
6627 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6628 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6629 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6630 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6632 #ifdef USE_JUMP_TABLES
6633 jte = mono_jumptable_add_entries (3);
6634 jte [0] = (gpointer)&ss_trigger_var;
6635 jte [1] = single_step_tramp;
6636 jte [2] = breakpoint_tramp;
6637 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6639 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6641 *(volatile int **)code = &ss_trigger_var;
6643 *(gpointer*)code = single_step_tramp;
6645 *(gpointer*)code = breakpoint_tramp;
6649 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6650 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
6651 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6652 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6653 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
6654 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6657 cfg->code_len = code - cfg->native_code;
6658 g_assert (cfg->code_len < cfg->code_size);
6665 mono_arch_emit_epilog (MonoCompile *cfg)
6667 MonoMethod *method = cfg->method;
6668 int pos, i, rot_amount;
6669 int max_epilog_size = 16 + 20*4;
6673 if (cfg->method->save_lmf)
6674 max_epilog_size += 128;
6676 if (mono_jit_trace_calls != NULL)
6677 max_epilog_size += 50;
6679 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6680 max_epilog_size += 50;
6682 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6683 cfg->code_size *= 2;
6684 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6685 cfg->stat_code_reallocs++;
6689 * Keep in sync with OP_JMP
6691 code = cfg->native_code + cfg->code_len;
6693 /* Save the uwind state which is needed by the out-of-line code */
6694 mono_emit_unwind_op_remember_state (cfg, code);
6696 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6697 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6701 /* Load returned vtypes into registers if needed */
6702 cinfo = cfg->arch.cinfo;
6703 switch (cinfo->ret.storage) {
6704 case RegTypeStructByVal: {
6705 MonoInst *ins = cfg->ret;
6707 if (arm_is_imm12 (ins->inst_offset)) {
6708 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6710 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6711 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6716 MonoInst *ins = cfg->ret;
6718 for (i = 0; i < cinfo->ret.nregs; ++i) {
6719 if (cinfo->ret.esize == 4)
6720 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6722 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6730 if (method->save_lmf) {
6731 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6732 /* all but r0-r3, sp and pc */
6733 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6736 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6738 /* This points to r4 inside MonoLMF->iregs */
6739 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6741 regmask = 0x9ff0; /* restore lr to pc */
6742 /* Skip caller saved registers not used by the method */
6743 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6744 regmask &= ~(1 << reg);
6749 /* Restored later */
6750 regmask &= ~(1 << ARMREG_PC);
6751 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6752 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6753 for (i = 0; i < 16; i++) {
6754 if (regmask & (1 << i))
6757 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6759 ARM_POP (code, regmask);
6761 for (i = 0; i < 16; i++) {
6762 if (regmask & (1 << i))
6763 mono_emit_unwind_op_same_value (cfg, code, i);
6765 /* Restore saved r7, restore LR to PC */
6766 /* Skip lr from the lmf */
6767 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6768 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6769 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6770 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6773 int i, nused_int_regs = 0;
6775 for (i = 0; i < 16; i++) {
6776 if (cfg->used_int_regs & (1 << i))
6780 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6781 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6783 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6784 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6787 if (cfg->frame_reg != ARMREG_SP) {
6788 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6792 /* Restore saved gregs */
6793 if (cfg->used_int_regs) {
6794 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6795 ARM_POP (code, cfg->used_int_regs);
6796 for (i = 0; i < 16; i++) {
6797 if (cfg->used_int_regs & (1 << i))
6798 mono_emit_unwind_op_same_value (cfg, code, i);
6801 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6802 /* Restore saved r7, restore LR to PC */
6803 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6805 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6806 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6810 /* Restore the unwind state to be the same as before the epilog */
6811 mono_emit_unwind_op_restore_state (cfg, code);
6813 cfg->code_len = code - cfg->native_code;
6815 g_assert (cfg->code_len < cfg->code_size);
6820 mono_arch_emit_exceptions (MonoCompile *cfg)
6822 MonoJumpInfo *patch_info;
6825 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6826 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6827 int max_epilog_size = 50;
6829 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6830 exc_throw_pos [i] = NULL;
6831 exc_throw_found [i] = 0;
6834 /* count the number of exception infos */
6837 * make sure we have enough space for exceptions
6839 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6840 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6841 i = mini_exception_id_by_name (patch_info->data.target);
6842 if (!exc_throw_found [i]) {
6843 max_epilog_size += 32;
6844 exc_throw_found [i] = TRUE;
6849 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6850 cfg->code_size *= 2;
6851 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6852 cfg->stat_code_reallocs++;
6855 code = cfg->native_code + cfg->code_len;
6857 /* add code to raise exceptions */
6858 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6859 switch (patch_info->type) {
6860 case MONO_PATCH_INFO_EXC: {
6861 MonoClass *exc_class;
6862 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6864 i = mini_exception_id_by_name (patch_info->data.target);
6865 if (exc_throw_pos [i]) {
6866 arm_patch (ip, exc_throw_pos [i]);
6867 patch_info->type = MONO_PATCH_INFO_NONE;
6870 exc_throw_pos [i] = code;
6872 arm_patch (ip, code);
6874 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6875 g_assert (exc_class);
6877 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6878 #ifdef USE_JUMP_TABLES
6880 gpointer *jte = mono_jumptable_add_entries (2);
6881 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6882 patch_info->data.name = "mono_arch_throw_corlib_exception";
6883 patch_info->ip.i = code - cfg->native_code;
6884 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6885 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6886 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6887 ARM_BLX_REG (code, ARMREG_IP);
6888 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6891 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6892 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6893 patch_info->data.name = "mono_arch_throw_corlib_exception";
6894 patch_info->ip.i = code - cfg->native_code;
6896 cfg->thunk_area += THUNK_SIZE;
6897 *(guint32*)(gpointer)code = exc_class->type_token;
6908 cfg->code_len = code - cfg->native_code;
6910 g_assert (cfg->code_len < cfg->code_size);
6914 #endif /* #ifndef DISABLE_JIT */
6917 mono_arch_finish_init (void)
6922 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6927 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6934 mono_arch_print_tree (MonoInst *tree, int arity)
6944 mono_arch_get_patch_offset (guint8 *code)
6951 mono_arch_flush_register_windows (void)
6956 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6958 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6962 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6964 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6968 mono_arch_get_cie_program (void)
6972 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6977 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6978 #define BASE_SIZE (6 * 4)
6979 #define BSEARCH_ENTRY_SIZE (4 * 4)
6980 #define CMP_SIZE (3 * 4)
6981 #define BRANCH_SIZE (1 * 4)
6982 #define CALL_SIZE (2 * 4)
6983 #define WMC_SIZE (8 * 4)
6984 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6986 #ifdef USE_JUMP_TABLES
6988 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6990 g_assert (base [index] == NULL);
6991 base [index] = value;
6994 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6996 if (arm_is_imm12 (jti * 4)) {
6997 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6999 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
7000 if ((jti * 4) >> 16)
7001 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
7002 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
7008 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
7010 guint32 delta = DISTANCE (target, code);
7012 g_assert (delta >= 0 && delta <= 0xFFF);
7013 *target = *target | delta;
7019 #ifdef ENABLE_WRONG_METHOD_CHECK
7021 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
7023 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
7029 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7030 gpointer fail_tramp)
7033 arminstr_t *code, *start;
7034 #ifdef USE_JUMP_TABLES
7037 gboolean large_offsets = FALSE;
7038 guint32 **constant_pool_starts;
7039 arminstr_t *vtable_target = NULL;
7040 int extra_space = 0;
7042 #ifdef ENABLE_WRONG_METHOD_CHECK
7048 #ifdef USE_JUMP_TABLES
7049 for (i = 0; i < count; ++i) {
7050 MonoIMTCheckItem *item = imt_entries [i];
7051 item->chunk_size += 4 * 16;
7052 if (!item->is_equals)
7053 imt_entries [item->check_target_idx]->compare_done = TRUE;
7054 size += item->chunk_size;
7057 constant_pool_starts = g_new0 (guint32*, count);
7059 for (i = 0; i < count; ++i) {
7060 MonoIMTCheckItem *item = imt_entries [i];
7061 if (item->is_equals) {
7062 gboolean fail_case = !item->check_target_idx && fail_tramp;
7064 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
7065 item->chunk_size += 32;
7066 large_offsets = TRUE;
7069 if (item->check_target_idx || fail_case) {
7070 if (!item->compare_done || fail_case)
7071 item->chunk_size += CMP_SIZE;
7072 item->chunk_size += BRANCH_SIZE;
7074 #ifdef ENABLE_WRONG_METHOD_CHECK
7075 item->chunk_size += WMC_SIZE;
7079 item->chunk_size += 16;
7080 large_offsets = TRUE;
7082 item->chunk_size += CALL_SIZE;
7084 item->chunk_size += BSEARCH_ENTRY_SIZE;
7085 imt_entries [item->check_target_idx]->compare_done = TRUE;
7087 size += item->chunk_size;
7091 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
7095 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7097 code = mono_domain_code_reserve (domain, size);
7100 unwind_ops = mono_arch_get_cie_program ();
7103 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
7104 for (i = 0; i < count; ++i) {
7105 MonoIMTCheckItem *item = imt_entries [i];
7106 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
7110 #ifdef USE_JUMP_TABLES
7111 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7112 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 3 * sizeof (mgreg_t));
7113 #define VTABLE_JTI 0
7114 #define IMT_METHOD_OFFSET 0
7115 #define TARGET_CODE_OFFSET 1
7116 #define JUMP_CODE_OFFSET 2
7117 #define RECORDS_PER_ENTRY 3
7118 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
7119 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
7120 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
7122 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
7123 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
7124 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
7125 set_jumptable_element (jte, VTABLE_JTI, vtable);
7127 if (large_offsets) {
7128 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7129 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
7131 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7132 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7134 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7135 vtable_target = code;
7136 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7138 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7140 for (i = 0; i < count; ++i) {
7141 MonoIMTCheckItem *item = imt_entries [i];
7142 #ifdef USE_JUMP_TABLES
7143 guint32 imt_method_jti = 0, target_code_jti = 0;
7145 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7147 gint32 vtable_offset;
7149 item->code_target = (guint8*)code;
7151 if (item->is_equals) {
7152 gboolean fail_case = !item->check_target_idx && fail_tramp;
7154 if (item->check_target_idx || fail_case) {
7155 if (!item->compare_done || fail_case) {
7156 #ifdef USE_JUMP_TABLES
7157 imt_method_jti = IMT_METHOD_JTI (i);
7158 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7161 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7163 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7165 #ifdef USE_JUMP_TABLES
7166 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7167 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7168 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7170 item->jmp_code = (guint8*)code;
7171 ARM_B_COND (code, ARMCOND_NE, 0);
7174 /*Enable the commented code to assert on wrong method*/
7175 #ifdef ENABLE_WRONG_METHOD_CHECK
7176 #ifdef USE_JUMP_TABLES
7177 imt_method_jti = IMT_METHOD_JTI (i);
7178 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7181 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7183 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7185 ARM_B_COND (code, ARMCOND_EQ, 0);
7187 /* Define this if your system is so bad that gdb is failing. */
7188 #ifdef BROKEN_DEV_ENV
7189 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7191 arm_patch (code - 1, mini_dump_bad_imt);
7195 arm_patch (cond, code);
7199 if (item->has_target_code) {
7200 /* Load target address */
7201 #ifdef USE_JUMP_TABLES
7202 target_code_jti = TARGET_CODE_JTI (i);
7203 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7204 /* Restore registers */
7205 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7206 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7208 ARM_BX (code, ARMREG_R1);
7209 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7211 target_code_ins = code;
7212 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7213 /* Save it to the fourth slot */
7214 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7215 /* Restore registers and branch */
7216 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7218 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7221 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7222 if (!arm_is_imm12 (vtable_offset)) {
7224 * We need to branch to a computed address but we don't have
7225 * a free register to store it, since IP must contain the
7226 * vtable address. So we push the two values to the stack, and
7227 * load them both using LDM.
7229 /* Compute target address */
7230 #ifdef USE_JUMP_TABLES
7231 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7232 if (vtable_offset >> 16)
7233 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7234 /* IP had vtable base. */
7235 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7236 /* Restore registers and branch */
7237 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7238 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7239 ARM_BX (code, ARMREG_IP);
7241 vtable_offset_ins = code;
7242 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7243 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7244 /* Save it to the fourth slot */
7245 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7246 /* Restore registers and branch */
7247 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7249 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7252 #ifdef USE_JUMP_TABLES
7253 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7254 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7255 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7256 ARM_BX (code, ARMREG_IP);
7258 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7259 if (large_offsets) {
7260 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7261 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7263 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7264 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7270 #ifdef USE_JUMP_TABLES
7271 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7272 target_code_jti = TARGET_CODE_JTI (i);
7273 /* Load target address */
7274 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7275 /* Restore registers */
7276 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7277 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7279 ARM_BX (code, ARMREG_R1);
7280 set_jumptable_element (jte, target_code_jti, fail_tramp);
7282 arm_patch (item->jmp_code, (guchar*)code);
7284 target_code_ins = code;
7285 /* Load target address */
7286 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7287 /* Save it to the fourth slot */
7288 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7289 /* Restore registers and branch */
7290 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7292 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7294 item->jmp_code = NULL;
7297 #ifdef USE_JUMP_TABLES
7299 set_jumptable_element (jte, imt_method_jti, item->key);
7302 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7304 /*must emit after unconditional branch*/
7305 if (vtable_target) {
7306 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7307 item->chunk_size += 4;
7308 vtable_target = NULL;
7311 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7312 constant_pool_starts [i] = code;
7314 code += extra_space;
7319 #ifdef USE_JUMP_TABLES
7320 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7321 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7322 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7323 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7324 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7326 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7327 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7329 item->jmp_code = (guint8*)code;
7330 ARM_B_COND (code, ARMCOND_HS, 0);
7336 for (i = 0; i < count; ++i) {
7337 MonoIMTCheckItem *item = imt_entries [i];
7338 if (item->jmp_code) {
7339 if (item->check_target_idx)
7340 #ifdef USE_JUMP_TABLES
7341 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7343 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7346 if (i > 0 && item->is_equals) {
7348 #ifdef USE_JUMP_TABLES
7349 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7350 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7352 arminstr_t *space_start = constant_pool_starts [i];
7353 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7354 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7362 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7363 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7368 #ifndef USE_JUMP_TABLES
7369 g_free (constant_pool_starts);
7372 mono_arch_flush_icache ((guint8*)start, size);
7373 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7374 mono_stats.imt_thunks_size += code - start;
7376 g_assert (DISTANCE (start, code) <= size);
7378 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7384 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7386 return ctx->regs [reg];
7390 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7392 ctx->regs [reg] = val;
7396 * mono_arch_get_trampolines:
7398 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7402 mono_arch_get_trampolines (gboolean aot)
7404 return mono_arm_get_exception_trampolines (aot);
7408 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7415 bp = MONO_CONTEXT_GET_BP (ctx);
7416 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7418 old_value = *lr_loc;
7419 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7422 *lr_loc = new_value;
7427 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7429 * mono_arch_set_breakpoint:
7431 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7432 * The location should contain code emitted by OP_SEQ_POINT.
7435 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7438 guint32 native_offset = ip - (guint8*)ji->code_start;
7439 MonoDebugOptions *opt = mini_get_debug_options ();
7441 if (opt->soft_breakpoints) {
7442 g_assert (!ji->from_aot);
7444 ARM_BLX_REG (code, ARMREG_LR);
7445 mono_arch_flush_icache (code - 4, 4);
7446 } else if (ji->from_aot) {
7447 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7449 g_assert (native_offset % 4 == 0);
7450 g_assert (info->bp_addrs [native_offset / 4] == 0);
7451 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7453 int dreg = ARMREG_LR;
7455 /* Read from another trigger page */
7456 #ifdef USE_JUMP_TABLES
7457 gpointer *jte = mono_jumptable_add_entry ();
7458 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7459 jte [0] = bp_trigger_page;
7461 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7463 *(int*)code = (int)bp_trigger_page;
7466 ARM_LDR_IMM (code, dreg, dreg, 0);
7468 mono_arch_flush_icache (code - 16, 16);
7471 /* This is currently implemented by emitting an SWI instruction, which
7472 * qemu/linux seems to convert to a SIGILL.
7474 *(int*)code = (0xef << 24) | 8;
7476 mono_arch_flush_icache (code - 4, 4);
7482 * mono_arch_clear_breakpoint:
7484 * Clear the breakpoint at IP.
7487 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7489 MonoDebugOptions *opt = mini_get_debug_options ();
7493 if (opt->soft_breakpoints) {
7494 g_assert (!ji->from_aot);
7497 mono_arch_flush_icache (code - 4, 4);
7498 } else if (ji->from_aot) {
7499 guint32 native_offset = ip - (guint8*)ji->code_start;
7500 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7502 g_assert (native_offset % 4 == 0);
7503 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7504 info->bp_addrs [native_offset / 4] = 0;
7506 for (i = 0; i < 4; ++i)
7509 mono_arch_flush_icache (ip, code - ip);
7514 * mono_arch_start_single_stepping:
7516 * Start single stepping.
7519 mono_arch_start_single_stepping (void)
7521 if (ss_trigger_page)
7522 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7528 * mono_arch_stop_single_stepping:
7530 * Stop single stepping.
7533 mono_arch_stop_single_stepping (void)
7535 if (ss_trigger_page)
7536 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7542 #define DBG_SIGNAL SIGBUS
7544 #define DBG_SIGNAL SIGSEGV
7548 * mono_arch_is_single_step_event:
7550 * Return whenever the machine state in SIGCTX corresponds to a single
7554 mono_arch_is_single_step_event (void *info, void *sigctx)
7556 siginfo_t *sinfo = info;
7558 if (!ss_trigger_page)
7561 /* Sometimes the address is off by 4 */
7562 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7569 * mono_arch_is_breakpoint_event:
7571 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7574 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7576 siginfo_t *sinfo = info;
7578 if (!ss_trigger_page)
7581 if (sinfo->si_signo == DBG_SIGNAL) {
7582 /* Sometimes the address is off by 4 */
7583 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7593 * mono_arch_skip_breakpoint:
7595 * See mini-amd64.c for docs.
7598 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7600 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7604 * mono_arch_skip_single_step:
7606 * See mini-amd64.c for docs.
7609 mono_arch_skip_single_step (MonoContext *ctx)
7611 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7614 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7617 * mono_arch_get_seq_point_info:
7619 * See mini-amd64.c for docs.
7622 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7627 // FIXME: Add a free function
7629 mono_domain_lock (domain);
7630 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7632 mono_domain_unlock (domain);
7635 ji = mono_jit_info_table_find (domain, (char*)code);
7638 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7640 info->ss_trigger_page = ss_trigger_page;
7641 info->bp_trigger_page = bp_trigger_page;
7643 mono_domain_lock (domain);
7644 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7646 mono_domain_unlock (domain);
7653 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7655 ext->lmf.previous_lmf = prev_lmf;
7656 /* Mark that this is a MonoLMFExt */
7657 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7658 ext->lmf.sp = (gssize)ext;
7662 * mono_arch_set_target:
7664 * Set the target architecture the JIT backend should generate code for, in the form
7665 * of a GNU target triplet. Only used in AOT mode.
7668 mono_arch_set_target (char *mtriple)
7670 /* The GNU target triple format is not very well documented */
7671 if (strstr (mtriple, "armv7")) {
7672 v5_supported = TRUE;
7673 v6_supported = TRUE;
7674 v7_supported = TRUE;
7676 if (strstr (mtriple, "armv6")) {
7677 v5_supported = TRUE;
7678 v6_supported = TRUE;
7680 if (strstr (mtriple, "armv7s")) {
7681 v7s_supported = TRUE;
7683 if (strstr (mtriple, "armv7k")) {
7684 v7k_supported = TRUE;
7686 if (strstr (mtriple, "thumbv7s")) {
7687 v5_supported = TRUE;
7688 v6_supported = TRUE;
7689 v7_supported = TRUE;
7690 v7s_supported = TRUE;
7691 thumb_supported = TRUE;
7692 thumb2_supported = TRUE;
7694 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7695 v5_supported = TRUE;
7696 v6_supported = TRUE;
7697 thumb_supported = TRUE;
7700 if (strstr (mtriple, "gnueabi"))
7701 eabi_supported = TRUE;
7705 mono_arch_opcode_supported (int opcode)
7708 case OP_ATOMIC_ADD_I4:
7709 case OP_ATOMIC_EXCHANGE_I4:
7710 case OP_ATOMIC_CAS_I4:
7711 case OP_ATOMIC_LOAD_I1:
7712 case OP_ATOMIC_LOAD_I2:
7713 case OP_ATOMIC_LOAD_I4:
7714 case OP_ATOMIC_LOAD_U1:
7715 case OP_ATOMIC_LOAD_U2:
7716 case OP_ATOMIC_LOAD_U4:
7717 case OP_ATOMIC_STORE_I1:
7718 case OP_ATOMIC_STORE_I2:
7719 case OP_ATOMIC_STORE_I4:
7720 case OP_ATOMIC_STORE_U1:
7721 case OP_ATOMIC_STORE_U2:
7722 case OP_ATOMIC_STORE_U4:
7723 return v7_supported;
7724 case OP_ATOMIC_LOAD_R4:
7725 case OP_ATOMIC_LOAD_R8:
7726 case OP_ATOMIC_STORE_R4:
7727 case OP_ATOMIC_STORE_R8:
7728 return v7_supported && IS_VFP;
7734 #if defined(ENABLE_GSHAREDVT)
7736 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7738 #endif /* !MONOTOUCH */