mono/mini/mini-arm.c

   1 /*
   2  * mini-arm.c: ARM backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *
   8  * (C) 2003 Ximian, Inc.
   9  */
  10 #include "mini.h"
  11 #include <string.h>
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15
  16 #include "mini-arm.h"
  17 #include "inssel.h"
  18 #include "cpu-arm.h"
  19 #include "trace.h"
  20 #include "mono/arch/arm/arm-fpa-codegen.h"
  21
  22 /*
  23  * TODO:
  24  * floating point support: on ARM it is a mess, there are at least 3
  25  * different setups, each of which binary incompat with the other.
  26  * 1) FPA: old and ugly, but unfortunately what current distros use
  27  *    the double binary format has the two words swapped. 8 double registers.
  28  *    Implemented usually by kernel emulation.
  29  * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
  30  *    ugly swapped double format (I guess a softfloat-vfp exists, too, though).
  31  * 3) VFP: the new and actually sensible and useful FP support. Implemented
  32  *    in HW or kernel-emulated, requires new tools. I think this ios what symbian uses.
  33  *
  34  * The plan is to write the FPA support first. softfloat can be tested in a chroot.
  35  */
  36 int mono_exc_esp_offset = 0;
  37
  38 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
  39 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
  40 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
  41
  42 const char*
  43 mono_arch_regname (int reg) {
  44         static const char * rnames[] = {
  45                 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
  46                 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
  47                 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
  48                 "arm_pc"
  49         };
  50         if (reg >= 0 && reg < 16)
  51                 return rnames [reg];
  52         return "unknown";
  53 }
  54
  55 const char*
  56 mono_arch_fregname (int reg) {
  57         static const char * rnames[] = {
  58                 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
  59                 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
  60                 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
  61                 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
  62                 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
  63                 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
  64                 "arm_f30", "arm_f31"
  65         };
  66         if (reg >= 0 && reg < 32)
  67                 return rnames [reg];
  68         return "unknown";
  69 }
  70
  71 static guint8*
  72 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
  73 {
  74         int imm8, rot_amount;
  75         if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
  76                 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
  77                 return code;
  78         }
  79         g_assert (dreg != sreg);
  80         code = mono_arm_emit_load_imm (code, dreg, imm);
  81         ARM_ADD_REG_REG (code, dreg, dreg, sreg);
  82         return code;
  83 }
  84
  85 static guint8*
  86 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
  87 {
  88         /* we can use r0-r3, since this is called only for incoming args on the stack */
  89         if (0 && size > sizeof (gpointer) * 5) {
  90                 guint8 *start_loop;
  91                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
  92                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
  93                 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
  94                 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
  95                 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
  96                 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
  97                 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
  98                 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
  99                 ARM_B_COND (code, ARMCOND_LT, 0);
 100                 arm_patch (code - 4, start_loop);
 101                 return code;
 102         }
 103         g_assert (arm_is_imm12 (doffset));
 104         g_assert (arm_is_imm12 (doffset + size));
 105         g_assert (arm_is_imm12 (soffset));
 106         g_assert (arm_is_imm12 (soffset + size));
 107         while (size >= 4) {
 108                 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
 109                 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
 110                 doffset += 4;
 111                 soffset += 4;
 112                 size -= 4;
 113         }
 114         g_assert (size == 0);
 115         return code;
 116 }
 117
 118 /*
 119  * mono_arch_get_argument_info:
 120  * @csig:  a method signature
 121  * @param_count: the number of parameters to consider
 122  * @arg_info: an array to store the result infos
 123  *
 124  * Gathers information on parameters such as size, alignment and
 125  * padding. arg_info should be large enought to hold param_count + 1 entries.
 126  *
 127  * Returns the size of the activation frame.
 128  */
 129 int
 130 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 131 {
 132         int k, frame_size = 0;
 133         int size, align, pad;
 134         int offset = 8;
 135
 136         if (MONO_TYPE_ISSTRUCT (csig->ret)) {
 137                 frame_size += sizeof (gpointer);
 138                 offset += 4;
 139         }
 140
 141         arg_info [0].offset = offset;
 142
 143         if (csig->hasthis) {
 144                 frame_size += sizeof (gpointer);
 145                 offset += 4;
 146         }
 147
 148         arg_info [0].size = frame_size;
 149
 150         for (k = 0; k < param_count; k++) {
 151
 152                 if (csig->pinvoke)
 153                         size = mono_type_native_stack_size (csig->params [k], &align);
 154                 else
 155                         size = mono_type_stack_size (csig->params [k], &align);
 156
 157                 /* ignore alignment for now */
 158                 align = 1;
 159
 160                 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 161                 arg_info [k].pad = pad;
 162                 frame_size += size;
 163                 arg_info [k + 1].pad = 0;
 164                 arg_info [k + 1].size = size;
 165                 offset += pad;
 166                 arg_info [k + 1].offset = offset;
 167                 offset += size;
 168         }
 169
 170         align = MONO_ARCH_FRAME_ALIGNMENT;
 171         frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 172         arg_info [k].pad = pad;
 173
 174         return frame_size;
 175 }
 176
 177 /*
 178  * Initialize the cpu to execute managed code.
 179  */
 180 void
 181 mono_arch_cpu_init (void)
 182 {
 183 }
 184
 185 /*
 186  * This function returns the optimizations supported on this cpu.
 187  */
 188 guint32
 189 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 190 {
 191         guint32 opts = 0;
 192
 193         /* no arm-specific optimizations yet */
 194         *exclude_mask = 0;
 195         return opts;
 196 }
 197
 198 static gboolean
 199 is_regsize_var (MonoType *t) {
 200         if (t->byref)
 201                 return TRUE;
 202         t = mono_type_get_underlying_type (t);
 203         switch (t->type) {
 204         case MONO_TYPE_I4:
 205         case MONO_TYPE_U4:
 206         case MONO_TYPE_I:
 207         case MONO_TYPE_U:
 208         case MONO_TYPE_PTR:
 209         case MONO_TYPE_FNPTR:
 210                 return TRUE;
 211         case MONO_TYPE_OBJECT:
 212         case MONO_TYPE_STRING:
 213         case MONO_TYPE_CLASS:
 214         case MONO_TYPE_SZARRAY:
 215         case MONO_TYPE_ARRAY:
 216                 return TRUE;
 217         case MONO_TYPE_VALUETYPE:
 218                 return FALSE;
 219         }
 220         return FALSE;
 221 }
 222
 223 GList *
 224 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 225 {
 226         GList *vars = NULL;
 227         int i;
 228
 229         for (i = 0; i < cfg->num_varinfo; i++) {
 230                 MonoInst *ins = cfg->varinfo [i];
 231                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 232
 233                 /* unused vars */
 234                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 235                         continue;
 236
 237                 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 238                         continue;
 239
 240                 /* we can only allocate 32 bit values */
 241                 if (is_regsize_var (ins->inst_vtype)) {
 242                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 243                         g_assert (i == vmv->idx);
 244                         vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
 245                 }
 246         }
 247
 248         return vars;
 249 }
 250
 251 #define USE_EXTRA_TEMPS 0
 252
 253 GList *
 254 mono_arch_get_global_int_regs (MonoCompile *cfg)
 255 {
 256         GList *regs = NULL;
 257         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
 258         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
 259         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
 260         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
 261         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
 262         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
 263         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
 264
 265         return regs;
 266 }
 267
 268 /*
 269  * mono_arch_regalloc_cost:
 270  *
 271  *  Return the cost, in number of memory references, of the action of
 272  * allocating the variable VMV into a register during global register
 273  * allocation.
 274  */
 275 guint32
 276 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 277 {
 278         /* FIXME: */
 279         return 2;
 280 }
 281
 282 void
 283 mono_arch_flush_icache (guint8 *code, gint size)
 284 {
 285         __asm __volatile ("mov r0, %0\n"
 286                         "mov r1, %1\n"
 287                         "mov r2, %2\n"
 288                         "swi 0x9f0002       @ sys_cacheflush"
 289                         : /* no outputs */
 290                         : "r" (code), "r" (code + size), "r" (0)
 291                         : "r0", "r1", "r3" );
 292
 293 }
 294
 295 #define NOT_IMPLEMENTED(x) \
 296                 g_error ("FIXME: %s is not yet implemented. (trampoline)", x);
 297
 298 enum {
 299         RegTypeGeneral,
 300         RegTypeBase,
 301         RegTypeFP,
 302         RegTypeStructByVal,
 303         RegTypeStructByAddr
 304 };
 305
 306 typedef struct {
 307         gint32  offset;
 308         guint16 vtsize; /* in param area */
 309         guint8  reg;
 310         guint8  regtype : 4; /* 0 general, 1 basereg, 2 floating point register, see RegType* */
 311         guint8  size    : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
 312 } ArgInfo;
 313
 314 typedef struct {
 315         int nargs;
 316         guint32 stack_usage;
 317         guint32 struct_ret;
 318         ArgInfo ret;
 319         ArgInfo sig_cookie;
 320         ArgInfo args [1];
 321 } CallInfo;
 322
 323 #define DEBUG(a)
 324
 325 static void inline
 326 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
 327 {
 328         if (simple) {
 329                 if (*gr > ARMREG_R3) {
 330                         ainfo->offset = *stack_size;
 331                         ainfo->reg = ARMREG_SP; /* in the caller */
 332                         ainfo->regtype = RegTypeBase;
 333                         *stack_size += 4;
 334                 } else {
 335                         ainfo->reg = *gr;
 336                 }
 337         } else {
 338                 if (*gr > ARMREG_R2) {
 339                         *stack_size += 7;
 340                         *stack_size &= ~7;
 341                         ainfo->offset = *stack_size;
 342                         ainfo->reg = ARMREG_SP; /* in the caller */
 343                         ainfo->regtype = RegTypeBase;
 344                         *stack_size += 8;
 345                 } else {
 346                         if ((*gr) & 1)
 347                                 (*gr) ++;
 348                         ainfo->reg = *gr;
 349                 }
 350                 (*gr) ++;
 351         }
 352         (*gr) ++;
 353 }
 354
 355 static CallInfo*
 356 calculate_sizes (MonoMethodSignature *sig, gboolean is_pinvoke)
 357 {
 358         guint i, gr;
 359         int n = sig->hasthis + sig->param_count;
 360         guint32 simpletype;
 361         guint32 stack_size = 0;
 362         CallInfo *cinfo = g_malloc0 (sizeof (CallInfo) + sizeof (ArgInfo) * n);
 363
 364         gr = ARMREG_R0;
 365
 366         /* FIXME: handle returning a struct */
 367         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 368                 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
 369                 cinfo->struct_ret = ARMREG_R0;
 370         }
 371
 372         n = 0;
 373         if (sig->hasthis) {
 374                 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 375                 n++;
 376         }
 377         DEBUG(printf("params: %d\n", sig->param_count));
 378         for (i = 0; i < sig->param_count; ++i) {
 379                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 380                         /* Prevent implicit arguments and sig_cookie from
 381                            being passed in registers */
 382                         gr = ARMREG_R3 + 1;
 383                         /* Emit the signature cookie just before the implicit arguments */
 384                         add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
 385                 }
 386                 DEBUG(printf("param %d: ", i));
 387                 if (sig->params [i]->byref) {
 388                         DEBUG(printf("byref\n"));
 389                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 390                         n++;
 391                         continue;
 392                 }
 393                 simpletype = mono_type_get_underlying_type (sig->params [i])->type;
 394                 switch (simpletype) {
 395                 case MONO_TYPE_BOOLEAN:
 396                 case MONO_TYPE_I1:
 397                 case MONO_TYPE_U1:
 398                         cinfo->args [n].size = 1;
 399                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 400                         n++;
 401                         break;
 402                 case MONO_TYPE_CHAR:
 403                 case MONO_TYPE_I2:
 404                 case MONO_TYPE_U2:
 405                         cinfo->args [n].size = 2;
 406                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 407                         n++;
 408                         break;
 409                 case MONO_TYPE_I4:
 410                 case MONO_TYPE_U4:
 411                         cinfo->args [n].size = 4;
 412                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 413                         n++;
 414                         break;
 415                 case MONO_TYPE_I:
 416                 case MONO_TYPE_U:
 417                 case MONO_TYPE_PTR:
 418                 case MONO_TYPE_FNPTR:
 419                 case MONO_TYPE_CLASS:
 420                 case MONO_TYPE_OBJECT:
 421                 case MONO_TYPE_STRING:
 422                 case MONO_TYPE_SZARRAY:
 423                 case MONO_TYPE_ARRAY:
 424                 case MONO_TYPE_R4:
 425                         cinfo->args [n].size = sizeof (gpointer);
 426                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 427                         n++;
 428                         break;
 429                 case MONO_TYPE_TYPEDBYREF:
 430                 case MONO_TYPE_VALUETYPE: {
 431                         gint size;
 432                         int align_size;
 433                         int nwords;
 434
 435                         if (simpletype == MONO_TYPE_TYPEDBYREF) {
 436                                 size = sizeof (MonoTypedRef);
 437                         } else {
 438                                 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
 439                                 if (is_pinvoke)
 440                                         size = mono_class_native_size (klass, NULL);
 441                                 else
 442                                         size = mono_class_value_size (klass, NULL);
 443                         }
 444                         DEBUG(printf ("load %d bytes struct\n",
 445                                       mono_class_native_size (sig->params [i]->data.klass, NULL)));
 446                         align_size = size;
 447                         nwords = 0;
 448                         align_size += (sizeof (gpointer) - 1);
 449                         align_size &= ~(sizeof (gpointer) - 1);
 450                         nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
 451                         cinfo->args [n].regtype = RegTypeStructByVal;
 452                         /* FIXME: align gr and stack_size if needed */
 453                         if (gr > ARMREG_R3) {
 454                                 cinfo->args [n].size = 0;
 455                                 cinfo->args [n].vtsize = nwords;
 456                         } else {
 457                                 int rest = ARMREG_R3 - gr + 1;
 458                                 int n_in_regs = rest >= nwords? nwords: rest;
 459                                 cinfo->args [n].size = n_in_regs;
 460                                 cinfo->args [n].vtsize = nwords - n_in_regs;
 461                                 cinfo->args [n].reg = gr;
 462                                 gr += n_in_regs;
 463                         }
 464                         cinfo->args [n].offset = stack_size;
 465                         /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
 466                         stack_size += nwords * sizeof (gpointer);
 467                         n++;
 468                         break;
 469                 }
 470                 case MONO_TYPE_U8:
 471                 case MONO_TYPE_I8:
 472                 case MONO_TYPE_R8:
 473                         cinfo->args [n].size = 8;
 474                         add_general (&gr, &stack_size, cinfo->args + n, FALSE);
 475                         n++;
 476                         break;
 477                 default:
 478                         g_error ("Can't trampoline 0x%x", sig->params [i]->type);
 479                 }
 480         }
 481
 482         {
 483                 simpletype = mono_type_get_underlying_type (sig->ret)->type;
 484                 switch (simpletype) {
 485                 case MONO_TYPE_BOOLEAN:
 486                 case MONO_TYPE_I1:
 487                 case MONO_TYPE_U1:
 488                 case MONO_TYPE_I2:
 489                 case MONO_TYPE_U2:
 490                 case MONO_TYPE_CHAR:
 491                 case MONO_TYPE_I4:
 492                 case MONO_TYPE_U4:
 493                 case MONO_TYPE_I:
 494                 case MONO_TYPE_U:
 495                 case MONO_TYPE_PTR:
 496                 case MONO_TYPE_FNPTR:
 497                 case MONO_TYPE_CLASS:
 498                 case MONO_TYPE_OBJECT:
 499                 case MONO_TYPE_SZARRAY:
 500                 case MONO_TYPE_ARRAY:
 501                 case MONO_TYPE_STRING:
 502                         cinfo->ret.reg = ARMREG_R0;
 503                         break;
 504                 case MONO_TYPE_U8:
 505                 case MONO_TYPE_I8:
 506                         cinfo->ret.reg = ARMREG_R0;
 507                         break;
 508                 case MONO_TYPE_R4:
 509                 case MONO_TYPE_R8:
 510                         cinfo->ret.reg = ARMREG_R0;
 511                         /* FIXME: cinfo->ret.reg = ???;
 512                         cinfo->ret.regtype = RegTypeFP;*/
 513                         break;
 514                 case MONO_TYPE_VALUETYPE:
 515                         break;
 516                 case MONO_TYPE_TYPEDBYREF:
 517                 case MONO_TYPE_VOID:
 518                         break;
 519                 default:
 520                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 521                 }
 522         }
 523
 524         /* align stack size to 8 */
 525         DEBUG (printf ("      stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
 526         stack_size = (stack_size + 7) & ~7;
 527
 528         cinfo->stack_usage = stack_size;
 529         return cinfo;
 530 }
 531
 532
 533 /*
 534  * Set var information according to the calling convention. arm version.
 535  * The locals var stuff should most likely be split in another method.
 536  */
 537 void
 538 mono_arch_allocate_vars (MonoCompile *m)
 539 {
 540         MonoMethodSignature *sig;
 541         MonoMethodHeader *header;
 542         MonoInst *inst;
 543         int i, offset, size, align, curinst;
 544         int frame_reg = ARMREG_FP;
 545
 546         /* FIXME: this will change when we use FP as gcc does */
 547         m->flags |= MONO_CFG_HAS_SPILLUP;
 548
 549         /* allow room for the vararg method args: void* and long/double */
 550         if (mono_jit_trace_calls != NULL && mono_trace_eval (m->method))
 551                 m->param_area = MAX (m->param_area, sizeof (gpointer)*8);
 552         /* this is bug #60332: remove when #59509 is fixed, so no weird vararg
 553          * call convs needs to be handled this way.
 554          */
 555         if (m->flags & MONO_CFG_HAS_VARARGS)
 556                 m->param_area = MAX (m->param_area, sizeof (gpointer)*8);
 557         /* gtk-sharp and other broken code will dllimport vararg functions even with
 558          * non-varargs signatures. Since there is little hope people will get this right
 559          * we assume they won't.
 560          */
 561         if (m->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE)
 562                 m->param_area = MAX (m->param_area, sizeof (gpointer)*8);
 563
 564         header = mono_method_get_header (m->method);
 565
 566         /*
 567          * We use the frame register also for any method that has
 568          * exception clauses. This way, when the handlers are called,
 569          * the code will reference local variables using the frame reg instead of
 570          * the stack pointer: if we had to restore the stack pointer, we'd
 571          * corrupt the method frames that are already on the stack (since
 572          * filters get called before stack unwinding happens) when the filter
 573          * code would call any method (this also applies to finally etc.).
 574          */
 575         if ((m->flags & MONO_CFG_HAS_ALLOCA) || header->num_clauses)
 576                 frame_reg = ARMREG_FP;
 577         m->frame_reg = frame_reg;
 578         if (frame_reg != ARMREG_SP) {
 579                 m->used_int_regs |= 1 << frame_reg;
 580         }
 581
 582         sig = mono_method_signature (m->method);
 583
 584         offset = 0;
 585         curinst = 0;
 586         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 587                 m->ret->opcode = OP_REGVAR;
 588                 m->ret->inst_c0 = ARMREG_R0;
 589         } else {
 590                 /* FIXME: handle long and FP values */
 591                 switch (mono_type_get_underlying_type (sig->ret)->type) {
 592                 case MONO_TYPE_VOID:
 593                         break;
 594                 default:
 595                         m->ret->opcode = OP_REGVAR;
 596                         m->ret->inst_c0 = ARMREG_R0;
 597                         break;
 598                 }
 599         }
 600         /* local vars are at a positive offset from the stack pointer */
 601         /*
 602          * also note that if the function uses alloca, we use FP
 603          * to point at the local variables.
 604          */
 605         offset = 0; /* linkage area */
 606         /* align the offset to 16 bytes: not sure this is needed here  */
 607         //offset += 8 - 1;
 608         //offset &= ~(8 - 1);
 609
 610         /* add parameter area size for called functions */
 611         offset += m->param_area;
 612         offset += 8 - 1;
 613         offset &= ~(8 - 1);
 614         if (m->flags & MONO_CFG_HAS_FPOUT)
 615                 offset += 8;
 616
 617         /* allow room to save the return value */
 618         if (mono_jit_trace_calls != NULL && mono_trace_eval (m->method))
 619                 offset += 8;
 620
 621         /* the MonoLMF structure is stored just below the stack pointer */
 622
 623         if (sig->call_convention == MONO_CALL_VARARG) {
 624                 m->sig_cookie = 0;
 625         }
 626
 627         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 628                 inst = m->ret;
 629                 offset += sizeof(gpointer) - 1;
 630                 offset &= ~(sizeof(gpointer) - 1);
 631                 inst->inst_offset = offset;
 632                 inst->opcode = OP_REGOFFSET;
 633                 inst->inst_basereg = frame_reg;
 634                 offset += sizeof(gpointer);
 635                 if (sig->call_convention == MONO_CALL_VARARG)
 636                         m->sig_cookie += sizeof (gpointer);
 637         }
 638
 639         curinst = m->locals_start;
 640         for (i = curinst; i < m->num_varinfo; ++i) {
 641                 inst = m->varinfo [i];
 642                 if ((inst->flags & MONO_INST_IS_DEAD) || inst->opcode == OP_REGVAR)
 643                         continue;
 644
 645                 /* inst->unused indicates native sized value types, this is used by the
 646                 * pinvoke wrappers when they call functions returning structure */
 647                 if (inst->unused && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
 648                         size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), &align);
 649                 else
 650                         size = mono_type_size (inst->inst_vtype, &align);
 651
 652                 offset += align - 1;
 653                 offset &= ~(align - 1);
 654                 inst->inst_offset = offset;
 655                 inst->opcode = OP_REGOFFSET;
 656                 inst->inst_basereg = frame_reg;
 657                 offset += size;
 658                 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
 659         }
 660
 661         curinst = 0;
 662         if (sig->hasthis) {
 663                 inst = m->varinfo [curinst];
 664                 if (inst->opcode != OP_REGVAR) {
 665                         inst->opcode = OP_REGOFFSET;
 666                         inst->inst_basereg = frame_reg;
 667                         offset += sizeof (gpointer) - 1;
 668                         offset &= ~(sizeof (gpointer) - 1);
 669                         inst->inst_offset = offset;
 670                         offset += sizeof (gpointer);
 671                         if (sig->call_convention == MONO_CALL_VARARG)
 672                                 m->sig_cookie += sizeof (gpointer);
 673                 }
 674                 curinst++;
 675         }
 676
 677         for (i = 0; i < sig->param_count; ++i) {
 678                 inst = m->varinfo [curinst];
 679                 if (inst->opcode != OP_REGVAR) {
 680                         inst->opcode = OP_REGOFFSET;
 681                         inst->inst_basereg = frame_reg;
 682                         size = mono_type_size (sig->params [i], &align);
 683                         offset += align - 1;
 684                         offset &= ~(align - 1);
 685                         inst->inst_offset = offset;
 686                         offset += size;
 687                         if ((sig->call_convention == MONO_CALL_VARARG) && (i < sig->sentinelpos))
 688                                 m->sig_cookie += size;
 689                 }
 690                 curinst++;
 691         }
 692
 693         /* align the offset to 8 bytes */
 694         offset += 8 - 1;
 695         offset &= ~(8 - 1);
 696
 697         /* change sign? */
 698         m->stack_offset = offset;
 699
 700 }
 701
 702 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
 703  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
 704  */
 705
 706 /*
 707  * take the arguments and generate the arch-specific
 708  * instructions to properly call the function in call.
 709  * This includes pushing, moving arguments to the right register
 710  * etc.
 711  * Issue: who does the spilling if needed, and when?
 712  */
 713 MonoCallInst*
 714 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
 715         MonoInst *arg, *in;
 716         MonoMethodSignature *sig;
 717         int i, n;
 718         CallInfo *cinfo;
 719         ArgInfo *ainfo;
 720
 721         sig = call->signature;
 722         n = sig->param_count + sig->hasthis;
 723
 724         cinfo = calculate_sizes (sig, sig->pinvoke);
 725         if (cinfo->struct_ret)
 726                 call->used_iregs |= 1 << cinfo->struct_ret;
 727
 728         for (i = 0; i < n; ++i) {
 729                 ainfo = cinfo->args + i;
 730                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 731                         MonoInst *sig_arg;
 732                         cfg->disable_aot = TRUE;
 733
 734                         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
 735                         sig_arg->inst_p0 = call->signature;
 736
 737                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
 738                         arg->inst_imm = cinfo->sig_cookie.offset;
 739                         arg->inst_left = sig_arg;
 740
 741                         /* prepend, so they get reversed */
 742                         arg->next = call->out_args;
 743                         call->out_args = arg;
 744                 }
 745                 if (is_virtual && i == 0) {
 746                         /* the argument will be attached to the call instrucion */
 747                         in = call->args [i];
 748                         call->used_iregs |= 1 << ainfo->reg;
 749                 } else {
 750                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
 751                         in = call->args [i];
 752                         arg->cil_code = in->cil_code;
 753                         arg->inst_left = in;
 754                         arg->inst_right = (MonoInst*)call;
 755                         arg->type = in->type;
 756                         /* prepend, we'll need to reverse them later */
 757                         arg->next = call->out_args;
 758                         call->out_args = arg;
 759                         if (ainfo->regtype == RegTypeGeneral) {
 760                                 arg->unused = ainfo->reg;
 761                                 call->used_iregs |= 1 << ainfo->reg;
 762                                 if (arg->type == STACK_I8)
 763                                         call->used_iregs |= 1 << (ainfo->reg + 1);
 764                                 if (arg->type == STACK_R8) {
 765                                         if (ainfo->size == 4) {
 766                                                 arg->opcode = OP_OUTARG_R4;
 767                                         } else {
 768                                                 call->used_iregs |= 1 << (ainfo->reg + 1);
 769                                         }
 770                                         cfg->flags |= MONO_CFG_HAS_FPOUT;
 771                                 }
 772                         } else if (ainfo->regtype == RegTypeStructByAddr) {
 773                                 /* FIXME: where si the data allocated? */
 774                                 arg->unused = ainfo->reg;
 775                                 call->used_iregs |= 1 << ainfo->reg;
 776                                 g_assert_not_reached ();
 777                         } else if (ainfo->regtype == RegTypeStructByVal) {
 778                                 int cur_reg;
 779                                 /* mark the used regs */
 780                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
 781                                         call->used_iregs |= 1 << (ainfo->reg + cur_reg);
 782                                 }
 783                                 arg->opcode = OP_OUTARG_VT;
 784                                 /* vtsize and offset have just 12 bits of encoding in number of words */
 785                                 g_assert (((ainfo->vtsize | (ainfo->offset / 4)) & 0xfffff000) == 0);
 786                                 arg->unused = ainfo->reg | (ainfo->size << 4) | (ainfo->vtsize << 8) | ((ainfo->offset / 4) << 20);
 787                         } else if (ainfo->regtype == RegTypeBase) {
 788                                 arg->opcode = OP_OUTARG_MEMBASE;
 789                                 arg->unused = (ainfo->offset << 8) | ainfo->size;
 790                         } else if (ainfo->regtype == RegTypeFP) {
 791                                 arg->unused = ainfo->reg;
 792                                 /* FPA args are passed in int regs */
 793                                 call->used_iregs |= 1 << ainfo->reg;
 794                                 if (ainfo->size == 8) {
 795                                         arg->opcode = OP_OUTARG_R8;
 796                                         call->used_iregs |= 1 << (ainfo->reg + 1);
 797                                 } else {
 798                                         arg->opcode = OP_OUTARG_R4;
 799                                 }
 800                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
 801                         } else {
 802                                 g_assert_not_reached ();
 803                         }
 804                 }
 805         }
 806         /*
 807          * Reverse the call->out_args list.
 808          */
 809         {
 810                 MonoInst *prev = NULL, *list = call->out_args, *next;
 811                 while (list) {
 812                         next = list->next;
 813                         list->next = prev;
 814                         prev = list;
 815                         list = next;
 816                 }
 817                 call->out_args = prev;
 818         }
 819         call->stack_usage = cinfo->stack_usage;
 820         cfg->param_area = MAX (cfg->param_area, cinfo->stack_usage);
 821         cfg->flags |= MONO_CFG_HAS_CALLS;
 822         /*
 823          * should set more info in call, such as the stack space
 824          * used by the args that needs to be added back to esp
 825          */
 826
 827         g_free (cinfo);
 828         return call;
 829 }
 830
 831 /*
 832  * Allow tracing to work with this interface (with an optional argument)
 833  */
 834
 835 void*
 836 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
 837 {
 838         guchar *code = p;
 839
 840         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
 841         ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
 842         code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
 843         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
 844         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_R2);
 845         return code;
 846 }
 847
 848 enum {
 849         SAVE_NONE,
 850         SAVE_STRUCT,
 851         SAVE_ONE,
 852         SAVE_TWO,
 853         SAVE_FP
 854 };
 855
 856 void*
 857 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
 858 {
 859         guchar *code = p;
 860         int save_mode = SAVE_NONE;
 861         int offset;
 862         MonoMethod *method = cfg->method;
 863         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
 864         int save_offset = cfg->param_area;
 865         save_offset += 7;
 866         save_offset &= ~7;
 867
 868         offset = code - cfg->native_code;
 869         /* we need about 16 instructions */
 870         if (offset > (cfg->code_size - 16 * 4)) {
 871                 cfg->code_size *= 2;
 872                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
 873                 code = cfg->native_code + offset;
 874         }
 875 handle_enum:
 876         switch (rtype) {
 877         case MONO_TYPE_VOID:
 878                 /* special case string .ctor icall */
 879                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
 880                         save_mode = SAVE_ONE;
 881                 else
 882                         save_mode = SAVE_NONE;
 883                 break;
 884         case MONO_TYPE_I8:
 885         case MONO_TYPE_U8:
 886                 save_mode = SAVE_TWO;
 887                 break;
 888         case MONO_TYPE_R4:
 889         case MONO_TYPE_R8:
 890                 save_mode = SAVE_FP;
 891                 break;
 892         case MONO_TYPE_VALUETYPE:
 893                 save_mode = SAVE_STRUCT;
 894                 break;
 895         default:
 896                 save_mode = SAVE_ONE;
 897                 break;
 898         }
 899
 900         switch (save_mode) {
 901         case SAVE_TWO:
 902                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
 903                 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
 904                 if (enable_arguments) {
 905                         ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
 906                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
 907                 }
 908                 break;
 909         case SAVE_ONE:
 910                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
 911                 if (enable_arguments) {
 912                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
 913                 }
 914                 break;
 915         case SAVE_FP:
 916                 /* FIXME: what reg?  */
 917                 if (enable_arguments) {
 918                         /* FIXME: what reg?  */
 919                 }
 920                 break;
 921         case SAVE_STRUCT:
 922                 if (enable_arguments) {
 923                         /* FIXME: get the actual address  */
 924                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
 925                 }
 926                 break;
 927         case SAVE_NONE:
 928         default:
 929                 break;
 930         }
 931
 932         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
 933         code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
 934         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
 935         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 936
 937         switch (save_mode) {
 938         case SAVE_TWO:
 939                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
 940                 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
 941                 break;
 942         case SAVE_ONE:
 943                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
 944                 break;
 945         case SAVE_FP:
 946                 /* FIXME */
 947                 break;
 948         case SAVE_NONE:
 949         default:
 950                 break;
 951         }
 952
 953         return code;
 954 }
 955
 956 /*
 957  * The immediate field for cond branches is big enough for all reasonable methods
 958  */
 959 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
 960 if (ins->flags & MONO_INST_BRLABEL) { \
 961         if (0 && ins->inst_i0->inst_c0) { \
 962                 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_i0->inst_c0) & 0xffffff);    \
 963         } else { \
 964                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
 965                 ARM_B_COND (code, (condcode), 0);       \
 966         } \
 967 } else { \
 968         if (0 && ins->inst_true_bb->native_offset) { \
 969                 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
 970         } else { \
 971                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
 972                 ARM_B_COND (code, (condcode), 0);       \
 973         } \
 974 }
 975
 976 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
 977
 978 /* emit an exception if condition is fail
 979  *
 980  * We assign the extra code used to throw the implicit exceptions
 981  * to cfg->bb_exit as far as the big branch handling is concerned
 982  */
 983 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name)            \
 984         do {                                                        \
 985                 mono_add_patch_info (cfg, code - cfg->native_code,   \
 986                                     MONO_PATCH_INFO_EXC, exc_name);  \
 987                 ARM_BL_COND (code, (condcode), 0);      \
 988         } while (0);
 989
 990 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
 991
 992 static void
 993 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
 994 {
 995         MonoInst *ins, *last_ins = NULL;
 996         ins = bb->code;
 997
 998         while (ins) {
 999
1000                 switch (ins->opcode) {
1001                 case OP_MUL_IMM:
1002                         /* remove unnecessary multiplication with 1 */
1003                         if (ins->inst_imm == 1) {
1004                                 if (ins->dreg != ins->sreg1) {
1005                                         ins->opcode = OP_MOVE;
1006                                 } else {
1007                                         last_ins->next = ins->next;
1008                                         ins = ins->next;
1009                                         continue;
1010                                 }
1011                         } else {
1012                                 int power2 = mono_is_power_of_two (ins->inst_imm);
1013                                 if (power2 > 0) {
1014                                         ins->opcode = OP_SHL_IMM;
1015                                         ins->inst_imm = power2;
1016                                 }
1017                         }
1018                         break;
1019                 case OP_LOAD_MEMBASE:
1020                 case OP_LOADI4_MEMBASE:
1021                         /*
1022                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1023                          * OP_LOAD_MEMBASE offset(basereg), reg
1024                          */
1025                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1026                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1027                             ins->inst_basereg == last_ins->inst_destbasereg &&
1028                             ins->inst_offset == last_ins->inst_offset) {
1029                                 if (ins->dreg == last_ins->sreg1) {
1030                                         last_ins->next = ins->next;
1031                                         ins = ins->next;
1032                                         continue;
1033                                 } else {
1034                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1035                                         ins->opcode = OP_MOVE;
1036                                         ins->sreg1 = last_ins->sreg1;
1037                                 }
1038
1039                         /*
1040                          * Note: reg1 must be different from the basereg in the second load
1041                          * OP_LOAD_MEMBASE offset(basereg), reg1
1042                          * OP_LOAD_MEMBASE offset(basereg), reg2
1043                          * -->
1044                          * OP_LOAD_MEMBASE offset(basereg), reg1
1045                          * OP_MOVE reg1, reg2
1046                          */
1047                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1048                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1049                               ins->inst_basereg != last_ins->dreg &&
1050                               ins->inst_basereg == last_ins->inst_basereg &&
1051                               ins->inst_offset == last_ins->inst_offset) {
1052
1053                                 if (ins->dreg == last_ins->dreg) {
1054                                         last_ins->next = ins->next;
1055                                         ins = ins->next;
1056                                         continue;
1057                                 } else {
1058                                         ins->opcode = OP_MOVE;
1059                                         ins->sreg1 = last_ins->dreg;
1060                                 }
1061
1062                                 //g_assert_not_reached ();
1063
1064 #if 0
1065                         /*
1066                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1067                          * OP_LOAD_MEMBASE offset(basereg), reg
1068                          * -->
1069                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1070                          * OP_ICONST reg, imm
1071                          */
1072                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1073                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1074                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1075                                    ins->inst_offset == last_ins->inst_offset) {
1076                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1077                                 ins->opcode = OP_ICONST;
1078                                 ins->inst_c0 = last_ins->inst_imm;
1079                                 g_assert_not_reached (); // check this rule
1080 #endif
1081                         }
1082                         break;
1083                 case OP_LOADU1_MEMBASE:
1084                 case OP_LOADI1_MEMBASE:
1085                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1086                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1087                                         ins->inst_offset == last_ins->inst_offset) {
1088                                 if (ins->dreg == last_ins->sreg1) {
1089                                         last_ins->next = ins->next;
1090                                         ins = ins->next;
1091                                         continue;
1092                                 } else {
1093                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1094                                         ins->opcode = OP_MOVE;
1095                                         ins->sreg1 = last_ins->sreg1;
1096                                 }
1097                         }
1098                         break;
1099                 case OP_LOADU2_MEMBASE:
1100                 case OP_LOADI2_MEMBASE:
1101                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1102                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1103                                         ins->inst_offset == last_ins->inst_offset) {
1104                                 if (ins->dreg == last_ins->sreg1) {
1105                                         last_ins->next = ins->next;
1106                                         ins = ins->next;
1107                                         continue;
1108                                 } else {
1109                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1110                                         ins->opcode = OP_MOVE;
1111                                         ins->sreg1 = last_ins->sreg1;
1112                                 }
1113                         }
1114                         break;
1115                 case CEE_CONV_I4:
1116                 case CEE_CONV_U4:
1117                 case OP_MOVE:
1118                 case OP_SETREG:
1119                         ins->opcode = OP_MOVE;
1120                         /*
1121                          * OP_MOVE reg, reg
1122                          */
1123                         if (ins->dreg == ins->sreg1) {
1124                                 if (last_ins)
1125                                         last_ins->next = ins->next;
1126                                 ins = ins->next;
1127                                 continue;
1128                         }
1129                         /*
1130                          * OP_MOVE sreg, dreg
1131                          * OP_MOVE dreg, sreg
1132                          */
1133                         if (last_ins && last_ins->opcode == OP_MOVE &&
1134                             ins->sreg1 == last_ins->dreg &&
1135                             ins->dreg == last_ins->sreg1) {
1136                                 last_ins->next = ins->next;
1137                                 ins = ins->next;
1138                                 continue;
1139                         }
1140                         break;
1141                 }
1142                 last_ins = ins;
1143                 ins = ins->next;
1144         }
1145         bb->last_ins = last_ins;
1146 }
1147
1148 /*
1149  * the branch_cc_table should maintain the order of these
1150  * opcodes.
1151 case CEE_BEQ:
1152 case CEE_BGE:
1153 case CEE_BGT:
1154 case CEE_BLE:
1155 case CEE_BLT:
1156 case CEE_BNE_UN:
1157 case CEE_BGE_UN:
1158 case CEE_BGT_UN:
1159 case CEE_BLE_UN:
1160 case CEE_BLT_UN:
1161  */
1162 static const guchar
1163 branch_cc_table [] = {
1164         ARMCOND_EQ,
1165         ARMCOND_GE,
1166         ARMCOND_GT,
1167         ARMCOND_LE,
1168         ARMCOND_LT,
1169
1170         ARMCOND_NE,
1171         ARMCOND_HS,
1172         ARMCOND_HI,
1173         ARMCOND_LS,
1174         ARMCOND_LO
1175 };
1176
1177
1178 static void
1179 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *to_insert)
1180 {
1181         if (ins == NULL) {
1182                 ins = bb->code;
1183                 bb->code = to_insert;
1184                 to_insert->next = ins;
1185         } else {
1186                 to_insert->next = ins->next;
1187                 ins->next = to_insert;
1188         }
1189 }
1190
1191 #define NEW_INS(cfg,dest,op) do {       \
1192                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1193                 (dest)->opcode = (op);  \
1194                 insert_after_ins (bb, last_ins, (dest)); \
1195         } while (0)
1196
1197 static int
1198 map_to_reg_reg_op (int op)
1199 {
1200         switch (op) {
1201         case OP_ADD_IMM:
1202                 return CEE_ADD;
1203         case OP_SUB_IMM:
1204                 return CEE_SUB;
1205         case OP_AND_IMM:
1206                 return CEE_AND;
1207         case OP_COMPARE_IMM:
1208                 return OP_COMPARE;
1209         case OP_ADDCC_IMM:
1210                 return OP_ADDCC;
1211         case OP_ADC_IMM:
1212                 return OP_ADC;
1213         case OP_SUBCC_IMM:
1214                 return OP_SUBCC;
1215         case OP_SBB_IMM:
1216                 return OP_SBB;
1217         case OP_OR_IMM:
1218                 return CEE_OR;
1219         case OP_XOR_IMM:
1220                 return CEE_XOR;
1221         case OP_LOAD_MEMBASE:
1222                 return OP_LOAD_MEMINDEX;
1223         case OP_LOADI4_MEMBASE:
1224                 return OP_LOADI4_MEMINDEX;
1225         case OP_LOADU4_MEMBASE:
1226                 return OP_LOADU4_MEMINDEX;
1227         case OP_LOADU1_MEMBASE:
1228                 return OP_LOADU1_MEMINDEX;
1229         case OP_LOADI2_MEMBASE:
1230                 return OP_LOADI2_MEMINDEX;
1231         case OP_LOADU2_MEMBASE:
1232                 return OP_LOADU2_MEMINDEX;
1233         case OP_LOADI1_MEMBASE:
1234                 return OP_LOADI1_MEMINDEX;
1235         case OP_STOREI1_MEMBASE_REG:
1236                 return OP_STOREI1_MEMINDEX;
1237         case OP_STOREI2_MEMBASE_REG:
1238                 return OP_STOREI2_MEMINDEX;
1239         case OP_STOREI4_MEMBASE_REG:
1240                 return OP_STOREI4_MEMINDEX;
1241         case OP_STORE_MEMBASE_REG:
1242                 return OP_STORE_MEMINDEX;
1243         case OP_STORER4_MEMBASE_REG:
1244                 return OP_STORER4_MEMINDEX;
1245         case OP_STORER8_MEMBASE_REG:
1246                 return OP_STORER8_MEMINDEX;
1247         }
1248         g_assert_not_reached ();
1249 }
1250
1251 /*
1252  * Remove from the instruction list the instructions that can't be
1253  * represented with very simple instructions with no register
1254  * requirements.
1255  */
1256 static void
1257 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1258 {
1259         MonoInst *ins, *next, *temp, *last_ins = NULL;
1260         int rot_amount, imm8;
1261
1262         /* setup the virtual reg allocator */
1263         if (bb->max_ireg > cfg->rs->next_vireg)
1264                 cfg->rs->next_vireg = bb->max_ireg;
1265
1266         ins = bb->code;
1267         while (ins) {
1268                 switch (ins->opcode) {
1269                 case OP_ADD_IMM:
1270                 case OP_SUB_IMM:
1271                 case OP_AND_IMM:
1272                 case OP_COMPARE_IMM:
1273                 case OP_ADDCC_IMM:
1274                 case OP_ADC_IMM:
1275                 case OP_SUBCC_IMM:
1276                 case OP_SBB_IMM:
1277                 case OP_OR_IMM:
1278                 case OP_XOR_IMM:
1279                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
1280                                 NEW_INS (cfg, temp, OP_ICONST);
1281                                 temp->inst_c0 = ins->inst_imm;
1282                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1283                                 ins->sreg2 = temp->dreg;
1284                                 ins->opcode = map_to_reg_reg_op (ins->opcode);
1285                         }
1286                         break;
1287                 case OP_MUL_IMM:
1288                         if (ins->inst_imm == 1) {
1289                                 ins->opcode = OP_MOVE;
1290                                 break;
1291                         }
1292                         if (ins->inst_imm == 0) {
1293                                 ins->opcode = OP_ICONST;
1294                                 ins->inst_c0 = 0;
1295                                 break;
1296                         }
1297                         imm8 = mono_is_power_of_two (ins->inst_imm);
1298                         if (imm8 > 0) {
1299                                 ins->opcode = OP_SHL_IMM;
1300                                 ins->inst_imm = imm8;
1301                                 break;
1302                         }
1303                         NEW_INS (cfg, temp, OP_ICONST);
1304                         temp->inst_c0 = ins->inst_imm;
1305                         temp->dreg = mono_regstate_next_int (cfg->rs);
1306                         ins->sreg2 = temp->dreg;
1307                         ins->opcode = CEE_MUL;
1308                         break;
1309                 case OP_LOAD_MEMBASE:
1310                 case OP_LOADI4_MEMBASE:
1311                 case OP_LOADU4_MEMBASE:
1312                 case OP_LOADU1_MEMBASE:
1313                         /* we can do two things: load the immed in a register
1314                          * and use an indexed load, or see if the immed can be
1315                          * represented as an ad_imm + a load with a smaller offset
1316                          * that fits. We just do the first for now, optimize later.
1317                          */
1318                         if (arm_is_imm12 (ins->inst_offset))
1319                                 break;
1320                         NEW_INS (cfg, temp, OP_ICONST);
1321                         temp->inst_c0 = ins->inst_offset;
1322                         temp->dreg = mono_regstate_next_int (cfg->rs);
1323                         ins->sreg2 = temp->dreg;
1324                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1325                         break;
1326                 case OP_LOADI2_MEMBASE:
1327                 case OP_LOADU2_MEMBASE:
1328                 case OP_LOADI1_MEMBASE:
1329                         if (arm_is_imm8 (ins->inst_offset))
1330                                 break;
1331                         NEW_INS (cfg, temp, OP_ICONST);
1332                         temp->inst_c0 = ins->inst_offset;
1333                         temp->dreg = mono_regstate_next_int (cfg->rs);
1334                         ins->sreg2 = temp->dreg;
1335                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1336                         break;
1337                 case OP_LOADR4_MEMBASE:
1338                 case OP_LOADR8_MEMBASE:
1339                         if (arm_is_fpimm8 (ins->inst_offset))
1340                                 break;
1341                         g_assert_not_reached ();
1342                         /* FPA doesn't have indexed load instructions */
1343                         NEW_INS (cfg, temp, OP_ICONST);
1344                         temp->inst_c0 = ins->inst_offset;
1345                         temp->dreg = mono_regstate_next_int (cfg->rs);
1346                         ins->sreg2 = temp->dreg;
1347                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1348                         break;
1349                 }
1350                 last_ins = ins;
1351                 ins = ins->next;
1352         }
1353         bb->last_ins = last_ins;
1354         bb->max_ireg = cfg->rs->next_vireg;
1355
1356 }
1357
1358 void
1359 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1360 {
1361         if (!bb->code)
1362                 return;
1363         mono_arch_lowering_pass (cfg, bb);
1364         mono_local_regalloc (cfg, bb);
1365 }
1366
1367 static guchar*
1368 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1369 {
1370         /* sreg is a float, dreg is an integer reg  */
1371         ARM_FIXZ (code, dreg, sreg);
1372         if (!is_signed) {
1373                 if (size == 1)
1374                         ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
1375                 else if (size == 2) {
1376                         ARM_SHL_IMM (code, dreg, dreg, 16);
1377                         ARM_SHR_IMM (code, dreg, dreg, 16);
1378                 }
1379         } else {
1380                 if (size == 1) {
1381                         ARM_SHL_IMM (code, dreg, dreg, 24);
1382                         ARM_SAR_IMM (code, dreg, dreg, 24);
1383                 } else if (size == 2) {
1384                         ARM_SHL_IMM (code, dreg, dreg, 16);
1385                         ARM_SAR_IMM (code, dreg, dreg, 16);
1386                 }
1387         }
1388         return code;
1389 }
1390
1391 typedef struct {
1392         guchar *code;
1393         const guchar *target;
1394         int absolute;
1395         int found;
1396 } PatchData;
1397
1398 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
1399
1400 static int
1401 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
1402         PatchData *pdata = (PatchData*)user_data;
1403         guchar *code = data;
1404         guint32 *thunks = data;
1405         guint32 *endthunks = (guint32*)(code + bsize);
1406         int i, count = 0;
1407         int difflow, diffhigh;
1408
1409         /* always ensure a call from pdata->code can reach to the thunks without further thunks */
1410         difflow = (char*)pdata->code - (char*)thunks;
1411         diffhigh = (char*)pdata->code - (char*)endthunks;
1412         if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
1413                 return 0;
1414
1415         /*
1416          * The thunk is composed of 3 words:
1417          * load constant from thunks [2] into ARM_IP
1418          * bx to ARM_IP
1419          * address constant
1420          * Note that the LR register is already setup
1421          */
1422         //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
1423         if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
1424                 while (thunks < endthunks) {
1425                         //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
1426                         if (thunks [2] == (guint32)pdata->target) {
1427                                 arm_patch (pdata->code, (guchar*)thunks);
1428                                 mono_arch_flush_icache (pdata->code, 4);
1429                                 pdata->found = 1;
1430                                 return 1;
1431                         } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
1432                                 /* found a free slot instead: emit thunk */
1433                                 code = (guchar*)thunks;
1434                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
1435                                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
1436                                 thunks [2] = (guint32)pdata->target;
1437                                 mono_arch_flush_icache ((guchar*)thunks, 12);
1438
1439                                 arm_patch (pdata->code, (guchar*)thunks);
1440                                 mono_arch_flush_icache (pdata->code, 4);
1441                                 pdata->found = 1;
1442                                 return 1;
1443                         }
1444                         /* skip 12 bytes, the size of the thunk */
1445                         thunks += 3;
1446                         count++;
1447                 }
1448                 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
1449         }
1450         return 0;
1451 }
1452
1453 static void
1454 handle_thunk (int absolute, guchar *code, const guchar *target) {
1455         MonoDomain *domain = mono_domain_get ();
1456         PatchData pdata;
1457
1458         pdata.code = code;
1459         pdata.target = target;
1460         pdata.absolute = absolute;
1461         pdata.found = 0;
1462
1463         mono_domain_lock (domain);
1464         mono_code_manager_foreach (domain->code_mp, search_thunk_slot, &pdata);
1465
1466         if (!pdata.found) {
1467                 /* this uses the first available slot */
1468                 pdata.found = 2;
1469                 mono_code_manager_foreach (domain->code_mp, search_thunk_slot, &pdata);
1470         }
1471         mono_domain_unlock (domain);
1472
1473         if (pdata.found != 1)
1474                 g_print ("thunk failed for %p from %p\n", target, code);
1475         g_assert (pdata.found == 1);
1476 }
1477
1478 void
1479 arm_patch (guchar *code, const guchar *target)
1480 {
1481         guint32 ins = *(guint32*)code;
1482         guint32 prim = (ins >> 25) & 7;
1483         guint32 ovf;
1484
1485         //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
1486         if (prim == 5) { /* 101b */
1487                 /* the diff starts 8 bytes from the branch opcode */
1488                 gint diff = target - code - 8;
1489                 if (diff >= 0) {
1490                         if (diff <= 33554431) {
1491                                 diff >>= 2;
1492                                 ins = (ins & 0xff000000) | diff;
1493                                 *(guint32*)code = ins;
1494                                 return;
1495                         }
1496                 } else {
1497                         /* diff between 0 and -33554432 */
1498                         if (diff >= -33554432) {
1499                                 diff >>= 2;
1500                                 ins = (ins & 0xff000000) | (diff & ~0xff000000);
1501                                 *(guint32*)code = ins;
1502                                 return;
1503                         }
1504                 }
1505
1506                 handle_thunk (TRUE, code, target);
1507                 return;
1508         }
1509
1510
1511         if ((ins & 0x0ffffff0) == 0x12fff10) {
1512                 /* branch and exchange: the address is constructed in a reg */
1513                 g_assert_not_reached ();
1514         } else {
1515                 g_assert_not_reached ();
1516         }
1517 //      g_print ("patched with 0x%08x\n", ins);
1518 }
1519
1520 /*
1521  * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
1522  * (with the rotation amount in *rot_amount. rot_amount is already adjusted
1523  * to be used with the emit macros.
1524  * Return -1 otherwise.
1525  */
1526 int
1527 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
1528 {
1529         guint32 res, i;
1530         for (i = 0; i < 31; i+= 2) {
1531                 res = (val << (32 - i)) | (val >> i);
1532                 if (res & ~0xff)
1533                         continue;
1534                 *rot_amount = i? 32 - i: 0;
1535                 return res;
1536         }
1537         return -1;
1538 }
1539
1540 /*
1541  * Emits in code a sequence of instructions that load the value 'val'
1542  * into the dreg register. Uses at most 4 instructions.
1543  */
1544 guint8*
1545 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
1546 {
1547         int imm8, rot_amount;
1548         if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
1549                 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
1550         } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
1551                 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
1552         } else {
1553                 if (val & 0xFF) {
1554                         ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
1555                         if (val & 0xFF00) {
1556                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
1557                         }
1558                         if (val & 0xFF0000) {
1559                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
1560                         }
1561                         if (val & 0xFF000000) {
1562                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
1563                         }
1564                 } else if (val & 0xFF00) {
1565                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
1566                         if (val & 0xFF0000) {
1567                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
1568                         }
1569                         if (val & 0xFF000000) {
1570                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
1571                         }
1572                 } else if (val & 0xFF0000) {
1573                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
1574                         if (val & 0xFF000000) {
1575                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
1576                         }
1577                 }
1578                 //g_assert_not_reached ();
1579         }
1580         return code;
1581 }
1582
1583 void
1584 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
1585 {
1586         MonoInst *ins;
1587         MonoCallInst *call;
1588         guint offset;
1589         guint8 *code = cfg->native_code + cfg->code_len;
1590         MonoInst *last_ins = NULL;
1591         guint last_offset = 0;
1592         int max_len, cpos;
1593         int imm8, rot_amount;
1594
1595         if (cfg->opt & MONO_OPT_PEEPHOLE)
1596                 peephole_pass (cfg, bb);
1597
1598         /* we don't align basic blocks of loops on arm */
1599
1600         if (cfg->verbose_level > 2)
1601                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
1602
1603         cpos = bb->max_offset;
1604
1605         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
1606                 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
1607                 //g_assert (!mono_compile_aot);
1608                 //cpos += 6;
1609                 //if (bb->cil_code)
1610                 //      cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
1611                 /* this is not thread save, but good enough */
1612                 /* fixme: howto handle overflows? */
1613                 //x86_inc_mem (code, &cov->data [bb->dfn].count);
1614         }
1615
1616         ins = bb->code;
1617         while (ins) {
1618                 offset = code - cfg->native_code;
1619
1620                 max_len = ((guint8 *)arm_cpu_desc [ins->opcode])[MONO_INST_LEN];
1621
1622                 if (offset > (cfg->code_size - max_len - 16)) {
1623                         cfg->code_size *= 2;
1624                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
1625                         code = cfg->native_code + offset;
1626                 }
1627         //      if (ins->cil_code)
1628         //              g_print ("cil code\n");
1629                 mono_debug_record_line_number (cfg, ins, offset);
1630
1631                 switch (ins->opcode) {
1632                 case OP_TLS_GET:
1633                         g_assert_not_reached ();
1634                         break;
1635                 /*case OP_BIGMUL:
1636                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
1637                         ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
1638                         break;
1639                 case OP_BIGMUL_UN:
1640                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
1641                         ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
1642                         break;*/
1643                 case OP_STOREI1_MEMBASE_IMM:
1644                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
1645                         g_assert (arm_is_imm12 (ins->inst_offset));
1646                         ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
1647                         break;
1648                 case OP_STOREI2_MEMBASE_IMM:
1649                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
1650                         g_assert (arm_is_imm8 (ins->inst_offset));
1651                         ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
1652                         break;
1653                 case OP_STORE_MEMBASE_IMM:
1654                 case OP_STOREI4_MEMBASE_IMM:
1655                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
1656                         g_assert (arm_is_imm12 (ins->inst_offset));
1657                         ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
1658                         break;
1659                 case OP_STOREI1_MEMBASE_REG:
1660                         g_assert (arm_is_imm12 (ins->inst_offset));
1661                         ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
1662                         break;
1663                 case OP_STOREI2_MEMBASE_REG:
1664                         g_assert (arm_is_imm8 (ins->inst_offset));
1665                         ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
1666                         break;
1667                 case OP_STORE_MEMBASE_REG:
1668                 case OP_STOREI4_MEMBASE_REG:
1669                         g_assert (arm_is_imm12 (ins->inst_offset));
1670                         ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
1671                         break;
1672                 case CEE_LDIND_I:
1673                 case CEE_LDIND_I4:
1674                 case CEE_LDIND_U4:
1675                         g_assert_not_reached ();
1676                         break;
1677                 case OP_LOADU4_MEM:
1678                         g_assert_not_reached ();
1679                         break;
1680                 case OP_LOAD_MEMINDEX:
1681                 case OP_LOADI4_MEMINDEX:
1682                 case OP_LOADU4_MEMINDEX:
1683                         ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1684                         break;
1685                 case OP_LOADI1_MEMINDEX:
1686                         ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1687                         break;
1688                 case OP_LOADU1_MEMINDEX:
1689                         ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1690                         break;
1691                 case OP_LOADI2_MEMINDEX:
1692                         ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1693                         break;
1694                 case OP_LOADU2_MEMINDEX:
1695                         ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1696                         break;
1697                 case OP_LOAD_MEMBASE:
1698                 case OP_LOADI4_MEMBASE:
1699                 case OP_LOADU4_MEMBASE:
1700                         g_assert (arm_is_imm12 (ins->inst_offset));
1701                         ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1702                         break;
1703                 case OP_LOADI1_MEMBASE:
1704                         g_assert (arm_is_imm8 (ins->inst_offset));
1705                         ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1706                         break;
1707                 case OP_LOADU1_MEMBASE:
1708                         g_assert (arm_is_imm12 (ins->inst_offset));
1709                         ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1710                         break;
1711                 case OP_LOADU2_MEMBASE:
1712                         g_assert (arm_is_imm8 (ins->inst_offset));
1713                         ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1714                         break;
1715                 case OP_LOADI2_MEMBASE:
1716                         g_assert (arm_is_imm8 (ins->inst_offset));
1717                         ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1718                         break;
1719                 case CEE_CONV_I1:
1720                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
1721                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
1722                         break;
1723                 case CEE_CONV_I2:
1724                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
1725                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
1726                         break;
1727                 case CEE_CONV_U1:
1728                         ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
1729                         break;
1730                 case CEE_CONV_U2:
1731                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
1732                         ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
1733                         break;
1734                 case OP_COMPARE:
1735                         ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
1736                         break;
1737                 case OP_COMPARE_IMM:
1738                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1739                         g_assert (imm8 >= 0);
1740                         ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
1741                         break;
1742                 case OP_X86_TEST_NULL:
1743                         g_assert_not_reached ();
1744                         break;
1745                 case CEE_BREAK:
1746                         *(int*)code = 0xe7f001f0;
1747                         *(int*)code = 0xef9f0001;
1748                         code += 4;
1749                         //ARM_DBRK (code);
1750                         break;
1751                 case OP_ADDCC:
1752                         ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1753                         break;
1754                 case CEE_ADD:
1755                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1756                         break;
1757                 case OP_ADC:
1758                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1759                         break;
1760                 case OP_ADDCC_IMM:
1761                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1762                         g_assert (imm8 >= 0);
1763                         ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1764                         break;
1765                 case OP_ADD_IMM:
1766                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1767                         g_assert (imm8 >= 0);
1768                         ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1769                         break;
1770                 case OP_ADC_IMM:
1771                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1772                         g_assert (imm8 >= 0);
1773                         ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1774                         break;
1775                 case CEE_ADD_OVF:
1776                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1777                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1778                         break;
1779                 case CEE_ADD_OVF_UN:
1780                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1781                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1782                         break;
1783                 case CEE_SUB_OVF:
1784                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1785                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1786                         break;
1787                 case CEE_SUB_OVF_UN:
1788                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1789                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
1790                         break;
1791                 case OP_ADD_OVF_CARRY:
1792                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1793                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1794                         break;
1795                 case OP_ADD_OVF_UN_CARRY:
1796                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1797                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1798                         break;
1799                 case OP_SUB_OVF_CARRY:
1800                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1801                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1802                         break;
1803                 case OP_SUB_OVF_UN_CARRY:
1804                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1805                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
1806                         break;
1807                 case OP_SUBCC:
1808                         ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1809                         break;
1810                 case OP_SUBCC_IMM:
1811                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1812                         g_assert (imm8 >= 0);
1813                         ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1814                         break;
1815                 case CEE_SUB:
1816                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1817                         break;
1818                 case OP_SBB:
1819                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1820                         break;
1821                 case OP_SUB_IMM:
1822                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1823                         g_assert (imm8 >= 0);
1824                         ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1825                         break;
1826                 case OP_SBB_IMM:
1827                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1828                         g_assert (imm8 >= 0);
1829                         ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1830                         break;
1831                 case OP_ARM_RSBS_IMM:
1832                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1833                         g_assert (imm8 >= 0);
1834                         ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1835                         break;
1836                 case OP_ARM_RSC_IMM:
1837                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1838                         g_assert (imm8 >= 0);
1839                         ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1840                         break;
1841                 case CEE_AND:
1842                         ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1843                         break;
1844                 case OP_AND_IMM:
1845                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1846                         g_assert (imm8 >= 0);
1847                         ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1848                         break;
1849                 case CEE_DIV:
1850                 case CEE_DIV_UN:
1851                 case OP_DIV_IMM:
1852                 case CEE_REM:
1853                 case CEE_REM_UN:
1854                 case OP_REM_IMM:
1855                         /* crappy ARM arch doesn't have a DIV instruction */
1856                         g_assert_not_reached ();
1857                 case CEE_OR:
1858                         ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1859                         break;
1860                 case OP_OR_IMM:
1861                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1862                         g_assert (imm8 >= 0);
1863                         ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1864                         break;
1865                 case CEE_XOR:
1866                         ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1867                         break;
1868                 case OP_XOR_IMM:
1869                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1870                         g_assert (imm8 >= 0);
1871                         ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1872                         break;
1873                 case CEE_SHL:
1874                         ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1875                         break;
1876                 case OP_SHL_IMM:
1877                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
1878                         break;
1879                 case CEE_SHR:
1880                         ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1881                         break;
1882                 case OP_SHR_IMM:
1883                         ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
1884                         break;
1885                 case OP_SHR_UN_IMM:
1886                         ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
1887                         break;
1888                 case CEE_SHR_UN:
1889                         ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1890                         break;
1891                 case CEE_NOT:
1892                         ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
1893                         break;
1894                 case CEE_NEG:
1895                         ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
1896                         break;
1897                 case CEE_MUL:
1898                         if (ins->dreg == ins->sreg2)
1899                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1900                         else
1901                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
1902                         break;
1903                 case OP_MUL_IMM:
1904                         g_assert_not_reached ();
1905                         break;
1906                 case CEE_MUL_OVF:
1907                         /* FIXME: handle ovf/ sreg2 != dreg */
1908                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1909                         break;
1910                 case CEE_MUL_OVF_UN:
1911                         /* FIXME: handle ovf/ sreg2 != dreg */
1912                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1913                         break;
1914                 case OP_ICONST:
1915                 case OP_SETREGIMM:
1916                         code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
1917                         break;
1918                 case OP_AOTCONST:
1919                         g_assert_not_reached ();
1920                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
1921                         break;
1922                 case CEE_CONV_I4:
1923                 case CEE_CONV_U4:
1924                 case OP_MOVE:
1925                 case OP_SETREG:
1926                         if (ins->dreg != ins->sreg1)
1927                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
1928                         break;
1929                 case OP_SETLRET: {
1930                         int saved = ins->sreg2;
1931                         if (ins->sreg2 == ARMREG_R0) {
1932                                 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
1933                                 saved = ARMREG_LR;
1934                         }
1935                         if (ins->sreg1 != ARMREG_R0)
1936                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
1937                         if (saved != ARMREG_R1)
1938                                 ARM_MOV_REG_REG (code, ARMREG_R1, saved);
1939                         break;
1940                 }
1941                 case OP_SETFREG:
1942                 case OP_FMOVE:
1943                         ARM_MVFD (code, ins->dreg, ins->sreg1);
1944                         break;
1945                 case OP_FCONV_TO_R4:
1946                         ARM_MVFS (code, ins->dreg, ins->sreg1);
1947                         break;
1948                 case CEE_JMP:
1949                         /*
1950                          * Keep in sync with mono_arch_emit_epilog
1951                          */
1952                         g_assert (!cfg->method->save_lmf);
1953                         code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
1954                         ARM_ADD_REG_IMM8 (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
1955                         ARM_POP_NWB (code, cfg->used_int_regs | ((1 << ARMREG_SP)) | ((1 << ARMREG_LR)));
1956                         mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
1957                         ARM_B (code, 0);
1958                         break;
1959                 case OP_CHECK_THIS:
1960                         /* ensure ins->sreg1 is not NULL */
1961                         ARM_LDR_IMM (code, ARMREG_LR, ins->sreg1, 0);
1962                         break;
1963                 case OP_ARGLIST: {
1964 #if ARM_PORT
1965                         if (ppc_is_imm16 (cfg->sig_cookie + cfg->stack_usage)) {
1966                                 ppc_addi (code, ppc_r11, cfg->frame_reg, cfg->sig_cookie + cfg->stack_usage);
1967                         } else {
1968                                 ppc_load (code, ppc_r11, cfg->sig_cookie + cfg->stack_usage);
1969                                 ppc_add (code, ppc_r11, cfg->frame_reg, ppc_r11);
1970                         }
1971                         ppc_stw (code, ppc_r11, 0, ins->sreg1);
1972 #endif
1973                         break;
1974                 }
1975                 case OP_FCALL:
1976                 case OP_LCALL:
1977                 case OP_VCALL:
1978                 case OP_VOIDCALL:
1979                 case CEE_CALL:
1980                         call = (MonoCallInst*)ins;
1981                         if (ins->flags & MONO_INST_HAS_METHOD)
1982                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
1983                         else
1984                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
1985                         if (cfg->method->dynamic) {
1986                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
1987                                 ARM_B (code, 0);
1988                                 *(gpointer*)code = NULL;
1989                                 code += 4;
1990                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
1991                                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
1992                         } else {
1993                                 ARM_BL (code, 0);
1994                         }
1995                         break;
1996                 case OP_FCALL_REG:
1997                 case OP_LCALL_REG:
1998                 case OP_VCALL_REG:
1999                 case OP_VOIDCALL_REG:
2000                 case OP_CALL_REG:
2001                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2002                         ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
2003                         break;
2004                 case OP_FCALL_MEMBASE:
2005                 case OP_LCALL_MEMBASE:
2006                 case OP_VCALL_MEMBASE:
2007                 case OP_VOIDCALL_MEMBASE:
2008                 case OP_CALL_MEMBASE:
2009                         g_assert (arm_is_imm12 (ins->inst_offset));
2010                         g_assert (ins->sreg1 != ARMREG_LR);
2011                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2012                         ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
2013                         break;
2014                 case OP_OUTARG:
2015                         g_assert_not_reached ();
2016                         break;
2017                 case OP_LOCALLOC: {
2018                         /* keep alignment */
2019                         int alloca_waste = cfg->param_area;
2020                         alloca_waste += 7;
2021                         alloca_waste &= ~7;
2022                         /* round the size to 8 bytes */
2023                         ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
2024                         ARM_BIC_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
2025                         ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
2026                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
2027                         /* memzero the area: dreg holds the size, sp is the pointer */
2028                         if (ins->flags & MONO_INST_INIT) {
2029                                 guint8 *start_loop, *branch_to_cond;
2030                                 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
2031                                 branch_to_cond = code;
2032                                 ARM_B (code, 0);
2033                                 start_loop = code;
2034                                 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
2035                                 arm_patch (branch_to_cond, code);
2036                                 /* decrement by 4 and set flags */
2037                                 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, 4);
2038                                 ARM_B_COND (code, ARMCOND_LT, 0);
2039                                 arm_patch (code - 4, start_loop);
2040                         }
2041                         ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
2042                         break;
2043                 }
2044                 case CEE_RET:
2045                         g_assert_not_reached ();
2046                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_LR);
2047                         break;
2048                 case CEE_THROW: {
2049                         if (ins->sreg1 != ARMREG_R0)
2050                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
2051                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2052                                              (gpointer)"mono_arch_throw_exception");
2053                         if (cfg->method->dynamic) {
2054                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2055                                 ARM_B (code, 0);
2056                                 *(gpointer*)code = NULL;
2057                                 code += 4;
2058                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2059                                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2060                         } else {
2061                                 ARM_BL (code, 0);
2062                         }
2063                         break;
2064                 }
2065                 case OP_RETHROW: {
2066                         if (ins->sreg1 != ARMREG_R0)
2067                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
2068                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2069                                              (gpointer)"mono_arch_rethrow_exception");
2070                         if (cfg->method->dynamic) {
2071                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2072                                 ARM_B (code, 0);
2073                                 *(gpointer*)code = NULL;
2074                                 code += 4;
2075                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2076                                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2077                         } else {
2078                                 ARM_BL (code, 0);
2079                         }
2080                         break;
2081                 }
2082                 case OP_START_HANDLER:
2083                         g_assert (arm_is_imm12 (ins->inst_left->inst_offset));
2084                         ARM_STR_IMM (code, ARMREG_LR, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
2085                         break;
2086                 case OP_ENDFILTER:
2087                         if (ins->sreg1 != ARMREG_R0)
2088                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
2089                         g_assert (arm_is_imm12 (ins->inst_left->inst_offset));
2090                         ARM_LDR_IMM (code, ARMREG_IP, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
2091                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2092                         break;
2093                 case CEE_ENDFINALLY:
2094                         g_assert (arm_is_imm12 (ins->inst_left->inst_offset));
2095                         ARM_LDR_IMM (code, ARMREG_IP, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
2096                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2097                         break;
2098                 case OP_CALL_HANDLER:
2099                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2100                         ARM_BL (code, 0);
2101                         break;
2102                 case OP_LABEL:
2103                         ins->inst_c0 = code - cfg->native_code;
2104                         break;
2105                 case CEE_BR:
2106                         if (ins->flags & MONO_INST_BRLABEL) {
2107                                 /*if (ins->inst_i0->inst_c0) {
2108                                         ARM_B (code, 0);
2109                                         //x86_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
2110                                 } else*/ {
2111                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2112                                         ARM_B (code, 0);
2113                                 }
2114                         } else {
2115                                 /*if (ins->inst_target_bb->native_offset) {
2116                                         ARM_B (code, 0);
2117                                         //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2118                                 } else*/ {
2119                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2120                                         ARM_B (code, 0);
2121                                 }
2122                         }
2123                         break;
2124                 case OP_BR_REG:
2125                         ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
2126                         break;
2127                 case CEE_SWITCH:
2128                         /*
2129                          * In the normal case we have:
2130                          *      ldr pc, [pc, ins->sreg1 << 2]
2131                          *      nop
2132                          * If aot, we have:
2133                          *      ldr lr, [pc, ins->sreg1 << 2]
2134                          *      add pc, pc, lr
2135                          * After follows the data.
2136                          * FIXME: add aot support.
2137                          */
2138                         max_len += 4 * GPOINTER_TO_INT (ins->klass);
2139                         if (offset > (cfg->code_size - max_len - 16)) {
2140                                 cfg->code_size += max_len;
2141                                 cfg->code_size *= 2;
2142                                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2143                                 code = cfg->native_code + offset;
2144                         }
2145                         ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
2146                         ARM_NOP (code);
2147                         code += 4 * GPOINTER_TO_INT (ins->klass);
2148                         break;
2149                 case OP_CEQ:
2150                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2151                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
2152                         break;
2153                 case OP_CLT:
2154                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2155                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
2156                         break;
2157                 case OP_CLT_UN:
2158                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2159                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
2160                         break;
2161                 case OP_CGT:
2162                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2163                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
2164                         break;
2165                 case OP_CGT_UN:
2166                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2167                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
2168                         break;
2169                 case OP_COND_EXC_EQ:
2170                 case OP_COND_EXC_NE_UN:
2171                 case OP_COND_EXC_LT:
2172                 case OP_COND_EXC_LT_UN:
2173                 case OP_COND_EXC_GT:
2174                 case OP_COND_EXC_GT_UN:
2175                 case OP_COND_EXC_GE:
2176                 case OP_COND_EXC_GE_UN:
2177                 case OP_COND_EXC_LE:
2178                 case OP_COND_EXC_LE_UN:
2179                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
2180                         break;
2181                 case OP_COND_EXC_C:
2182                 case OP_COND_EXC_OV:
2183                 case OP_COND_EXC_NC:
2184                 case OP_COND_EXC_NO:
2185                         g_assert_not_reached ();
2186                         break;
2187                 case CEE_BEQ:
2188                 case CEE_BNE_UN:
2189                 case CEE_BLT:
2190                 case CEE_BLT_UN:
2191                 case CEE_BGT:
2192                 case CEE_BGT_UN:
2193                 case CEE_BGE:
2194                 case CEE_BGE_UN:
2195                 case CEE_BLE:
2196                 case CEE_BLE_UN:
2197                         EMIT_COND_BRANCH (ins, ins->opcode - CEE_BEQ);
2198                         break;
2199
2200                 /* floating point opcodes */
2201                 case OP_R8CONST:
2202                         /* FIXME: we can optimize the imm load by dealing with part of
2203                          * the displacement in LDFD (aligning to 512).
2204                          */
2205                         code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
2206                         ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
2207                         break;
2208                 case OP_R4CONST:
2209                         code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
2210                         ARM_LDFS (code, ins->dreg, ARMREG_LR, 0);
2211                         break;
2212                 case OP_STORER8_MEMBASE_REG:
2213                         g_assert (arm_is_fpimm8 (ins->inst_offset));
2214                         ARM_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
2215                         break;
2216                 case OP_LOADR8_MEMBASE:
2217                         g_assert (arm_is_fpimm8 (ins->inst_offset));
2218                         ARM_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2219                         break;
2220                 case OP_STORER4_MEMBASE_REG:
2221                         g_assert (arm_is_fpimm8 (ins->inst_offset));
2222                         ARM_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
2223                         break;
2224                 case OP_LOADR4_MEMBASE:
2225                         g_assert (arm_is_fpimm8 (ins->inst_offset));
2226                         ARM_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2227                         break;
2228                 case CEE_CONV_R_UN: {
2229                         /*static const guint64 adjust_val = 0x4330000000000000ULL;
2230                         ppc_addis (code, ppc_r0, ppc_r0, 0x4330);
2231                         ppc_stw (code, ppc_r0, -8, ppc_sp);
2232                         ppc_stw (code, ins->sreg1, -4, ppc_sp);
2233                         ppc_load (code, ppc_r11, &adjust_val);
2234                         ppc_lfd (code, ins->dreg, -8, ppc_sp);
2235                         ppc_lfd (code, ppc_f0, 0, ppc_r11);
2236                         ppc_fsub (code, ins->dreg, ins->dreg, ppc_f0);*/
2237                         g_assert_not_reached ();
2238                         break;
2239                 }
2240                 case CEE_CONV_R4:
2241                         ARM_FLTS (code, ins->dreg, ins->sreg1);
2242                         break;
2243                 case CEE_CONV_R8:
2244                         ARM_FLTD (code, ins->dreg, ins->sreg1);
2245                         break;
2246                 case OP_X86_FP_LOAD_I8:
2247                         g_assert_not_reached ();
2248                         /*x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);*/
2249                         break;
2250                 case OP_X86_FP_LOAD_I4:
2251                         g_assert_not_reached ();
2252                         /*x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);*/
2253                         break;
2254                 case OP_FCONV_TO_I1:
2255                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
2256                         break;
2257                 case OP_FCONV_TO_U1:
2258                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
2259                         break;
2260                 case OP_FCONV_TO_I2:
2261                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
2262                         break;
2263                 case OP_FCONV_TO_U2:
2264                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
2265                         break;
2266                 case OP_FCONV_TO_I4:
2267                 case OP_FCONV_TO_I:
2268                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
2269                         break;
2270                 case OP_FCONV_TO_U4:
2271                 case OP_FCONV_TO_U:
2272                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
2273                         break;
2274                 case OP_FCONV_TO_I8:
2275                 case OP_FCONV_TO_U8:
2276                         g_assert_not_reached ();
2277                         /* Implemented as helper calls */
2278                         break;
2279                 case OP_LCONV_TO_R_UN:
2280                         g_assert_not_reached ();
2281                         /* Implemented as helper calls */
2282                         break;
2283                 case OP_LCONV_TO_OVF_I: {
2284 #if ARM_PORT
2285                         guint32 *negative_branch, *msword_positive_branch, *msword_negative_branch, *ovf_ex_target;
2286                         // Check if its negative
2287                         ppc_cmpi (code, 0, 0, ins->sreg1, 0);
2288                         negative_branch = code;
2289                         ppc_bc (code, PPC_BR_TRUE, PPC_BR_LT, 0);
2290                         // Its positive msword == 0
2291                         ppc_cmpi (code, 0, 0, ins->sreg2, 0);
2292                         msword_positive_branch = code;
2293                         ppc_bc (code, PPC_BR_TRUE, PPC_BR_EQ, 0);
2294
2295                         ovf_ex_target = code;
2296                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_ALWAYS, 0, "OverflowException");
2297                         // Negative
2298                         ppc_patch (negative_branch, code);
2299                         ppc_cmpi (code, 0, 0, ins->sreg2, -1);
2300                         msword_negative_branch = code;
2301                         ppc_bc (code, PPC_BR_FALSE, PPC_BR_EQ, 0);
2302                         ppc_patch (msword_negative_branch, ovf_ex_target);
2303
2304                         ppc_patch (msword_positive_branch, code);
2305                         if (ins->dreg != ins->sreg1)
2306                                 ppc_mr (code, ins->dreg, ins->sreg1);
2307 #endif
2308                         if (ins->dreg != ins->sreg1)
2309                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
2310                         break;
2311                 }
2312                 case OP_FADD:
2313                         ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2314                         break;
2315                 case OP_FSUB:
2316                         ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2317                         break;
2318                 case OP_FMUL:
2319                         ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2320                         break;
2321                 case OP_FDIV:
2322                         ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2323                         break;
2324                 case OP_FNEG:
2325                         ARM_MNFD (code, ins->dreg, ins->sreg1);
2326                         break;
2327                 case OP_FREM:
2328                         /* emulated */
2329                         g_assert_not_reached ();
2330                         break;
2331                 case OP_FCOMPARE:
2332                         /* each fp compare op needs to do its own */
2333                         g_assert_not_reached ();
2334                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2335                         break;
2336                 case OP_FCEQ:
2337                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2338                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2339                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
2340                         break;
2341                 case OP_FCLT:
2342                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2343                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2344                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2345                         break;
2346                 case OP_FCLT_UN:
2347                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2348                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2349                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2350                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
2351                         break;
2352                 case OP_FCGT:
2353                         /* swapped */
2354                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2355                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2356                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2357                         break;
2358                 case OP_FCGT_UN:
2359                         /* swapped */
2360                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2361                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2362                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2363                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
2364                         break;
2365                 /* ARM FPA flags table:
2366                  * N        Less than               ARMCOND_MI
2367                  * Z        Equal                   ARMCOND_EQ
2368                  * C        Greater Than or Equal   ARMCOND_CS
2369                  * V        Unordered               ARMCOND_VS
2370                  */
2371                 case OP_FBEQ:
2372                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2373                         EMIT_COND_BRANCH (ins, CEE_BEQ - CEE_BEQ);
2374                         break;
2375                 case OP_FBNE_UN:
2376                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2377                         EMIT_COND_BRANCH (ins, CEE_BNE_UN - CEE_BEQ);
2378                         break;
2379                 case OP_FBLT:
2380                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2381                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
2382                         break;
2383                 case OP_FBLT_UN:
2384                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2385                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2386                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
2387                         break;
2388                 case OP_FBGT:
2389                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2390                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set, swapped args */
2391                         break;
2392                 case OP_FBGT_UN:
2393                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2394                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2395                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set, swapped args */
2396                         break;
2397                 case OP_FBGE:
2398                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2399                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
2400                         break;
2401                 case OP_FBGE_UN:
2402                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2403                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2404                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
2405                         break;
2406                 case OP_FBLE:
2407                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2408                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS); /* swapped */
2409                         break;
2410                 case OP_FBLE_UN:
2411                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2412                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2413                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS); /* swapped */
2414                         break;
2415                 case CEE_CKFINITE: {
2416                         /*ppc_stfd (code, ins->sreg1, -8, ppc_sp);
2417                         ppc_lwz (code, ppc_r11, -8, ppc_sp);
2418                         ppc_rlwinm (code, ppc_r11, ppc_r11, 0, 1, 31);
2419                         ppc_addis (code, ppc_r11, ppc_r11, -32752);
2420                         ppc_rlwinmd (code, ppc_r11, ppc_r11, 1, 31, 31);
2421                         EMIT_COND_SYSTEM_EXCEPTION (CEE_BEQ - CEE_BEQ, "ArithmeticException");*/
2422                         g_assert_not_reached ();
2423                         break;
2424                 }
2425                 default:
2426                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
2427                         g_assert_not_reached ();
2428                 }
2429
2430                 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
2431                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
2432                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
2433                         g_assert_not_reached ();
2434                 }
2435
2436                 cpos += max_len;
2437
2438                 last_ins = ins;
2439                 last_offset = offset;
2440
2441                 ins = ins->next;
2442         }
2443
2444         cfg->code_len = code - cfg->native_code;
2445 }
2446
2447 void
2448 mono_arch_register_lowlevel_calls (void)
2449 {
2450 }
2451
2452 #define patch_lis_ori(ip,val) do {\
2453                 guint16 *__lis_ori = (guint16*)(ip);    \
2454                 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff;      \
2455                 __lis_ori [3] = ((guint32)(val)) & 0xffff;      \
2456         } while (0)
2457
2458 void
2459 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
2460 {
2461         MonoJumpInfo *patch_info;
2462
2463         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
2464                 unsigned char *ip = patch_info->ip.i + code;
2465                 const unsigned char *target;
2466
2467                 if (patch_info->type == MONO_PATCH_INFO_SWITCH) {
2468                         gpointer *table = (gpointer *)patch_info->data.table->table;
2469                         gpointer *jt = (gpointer*)(ip + 8);
2470                         int i;
2471                         /* jt is the inlined jump table, 2 instructions after ip
2472                          * In the normal case we store the absolute addresses,
2473                          * otherwise the displacements.
2474                          */
2475                         for (i = 0; i < patch_info->data.table->table_size; i++) {
2476                                 jt [i] = code + (int)patch_info->data.table->table [i];
2477                         }
2478                         continue;
2479                 }
2480                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
2481
2482                 switch (patch_info->type) {
2483                 case MONO_PATCH_INFO_IP:
2484                         g_assert_not_reached ();
2485                         patch_lis_ori (ip, ip);
2486                         continue;
2487                 case MONO_PATCH_INFO_METHOD_REL:
2488                         g_assert_not_reached ();
2489                         *((gpointer *)(ip)) = code + patch_info->data.offset;
2490                         continue;
2491                 case MONO_PATCH_INFO_METHODCONST:
2492                 case MONO_PATCH_INFO_CLASS:
2493                 case MONO_PATCH_INFO_IMAGE:
2494                 case MONO_PATCH_INFO_FIELD:
2495                 case MONO_PATCH_INFO_VTABLE:
2496                 case MONO_PATCH_INFO_IID:
2497                 case MONO_PATCH_INFO_SFLDA:
2498                 case MONO_PATCH_INFO_LDSTR:
2499                 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
2500                 case MONO_PATCH_INFO_LDTOKEN:
2501                         g_assert_not_reached ();
2502                         /* from OP_AOTCONST : lis + ori */
2503                         patch_lis_ori (ip, target);
2504                         continue;
2505                 case MONO_PATCH_INFO_R4:
2506                 case MONO_PATCH_INFO_R8:
2507                         g_assert_not_reached ();
2508                         *((gconstpointer *)(ip + 2)) = patch_info->data.target;
2509                         continue;
2510                 case MONO_PATCH_INFO_EXC_NAME:
2511                         g_assert_not_reached ();
2512                         *((gconstpointer *)(ip + 1)) = patch_info->data.name;
2513                         continue;
2514                 case MONO_PATCH_INFO_NONE:
2515                 case MONO_PATCH_INFO_BB_OVF:
2516                 case MONO_PATCH_INFO_EXC_OVF:
2517                         /* everything is dealt with at epilog output time */
2518                         continue;
2519                 default:
2520                         break;
2521                 }
2522                 arm_patch (ip, target);
2523         }
2524 }
2525
2526 /*
2527  * Stack frame layout:
2528  *
2529  *   ------------------- fp
2530  *      MonoLMF structure or saved registers
2531  *   -------------------
2532  *      locals
2533  *   -------------------
2534  *      spilled regs
2535  *   -------------------
2536  *      optional 8 bytes for tracing
2537  *   -------------------
2538  *      param area             size is cfg->param_area
2539  *   ------------------- sp
2540  */
2541 guint8 *
2542 mono_arch_emit_prolog (MonoCompile *cfg)
2543 {
2544         MonoMethod *method = cfg->method;
2545         MonoBasicBlock *bb;
2546         MonoMethodSignature *sig;
2547         MonoInst *inst;
2548         int alloc_size, pos, max_offset, i, rot_amount;
2549         guint8 *code;
2550         CallInfo *cinfo;
2551         int tracing = 0;
2552         int lmf_offset = 0;
2553         int prev_sp_offset;
2554
2555         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
2556                 tracing = 1;
2557
2558         sig = mono_method_signature (method);
2559         cfg->code_size = 256 + sig->param_count * 20;
2560         code = cfg->native_code = g_malloc (cfg->code_size);
2561
2562         ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
2563
2564         alloc_size = cfg->stack_offset;
2565         pos = 0;
2566
2567         if (1 || !method->save_lmf) {
2568                 ARM_PUSH (code, (cfg->used_int_regs | (1 << ARMREG_IP) | (1 << ARMREG_LR)));
2569                 prev_sp_offset = 8; /* ip and lr */
2570                 for (i = 0; i < 16; ++i) {
2571                         if (cfg->used_int_regs & (1 << i))
2572                                 prev_sp_offset += 4;
2573                 }
2574         } else {
2575                 ARM_PUSH (code, 0x5ff0);
2576                 prev_sp_offset = 4 * 10; /* all but r0-r3, sp and pc */
2577                 pos += sizeof (MonoLMF) - prev_sp_offset;
2578                 lmf_offset = pos;
2579         }
2580         alloc_size += pos;
2581         // align to MONO_ARCH_FRAME_ALIGNMENT bytes
2582         if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
2583                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
2584                 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
2585         }
2586
2587         cfg->stack_usage = alloc_size;
2588         g_assert ((alloc_size & (MONO_ARCH_FRAME_ALIGNMENT-1)) == 0);
2589         if (alloc_size) {
2590                 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
2591                         ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
2592                 } else {
2593                         code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
2594                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
2595                 }
2596         }
2597         if (cfg->frame_reg != ARMREG_SP)
2598                 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
2599         //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
2600         prev_sp_offset += alloc_size;
2601
2602         /* compute max_offset in order to use short forward jumps
2603          * we always do it on ppc because the immediate displacement
2604          * for jumps is too small
2605          */
2606         max_offset = 0;
2607         for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
2608                 MonoInst *ins = bb->code;
2609                 bb->max_offset = max_offset;
2610
2611                 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
2612                         max_offset += 6;
2613
2614                 while (ins) {
2615                         max_offset += ((guint8 *)arm_cpu_desc [ins->opcode])[MONO_INST_LEN];
2616                         ins = ins->next;
2617                 }
2618         }
2619
2620         /* load arguments allocated to register from the stack */
2621         pos = 0;
2622
2623         cinfo = calculate_sizes (sig, sig->pinvoke);
2624
2625         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
2626                 ArgInfo *ainfo = &cinfo->ret;
2627                 inst = cfg->ret;
2628                 g_assert (arm_is_imm12 (inst->inst_offset));
2629                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2630         }
2631         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2632                 ArgInfo *ainfo = cinfo->args + i;
2633                 inst = cfg->varinfo [pos];
2634
2635                 if (cfg->verbose_level > 2)
2636                         g_print ("Saving argument %d (type: %d)\n", i, ainfo->regtype);
2637                 if (inst->opcode == OP_REGVAR) {
2638                         if (ainfo->regtype == RegTypeGeneral)
2639                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
2640                         else if (ainfo->regtype == RegTypeFP) {
2641                                 g_assert_not_reached ();
2642                         } else if (ainfo->regtype == RegTypeBase) {
2643                                 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
2644                                 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2645                         } else
2646                                 g_assert_not_reached ();
2647
2648                         if (cfg->verbose_level > 2)
2649                                 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
2650                 } else {
2651                         /* the argument should be put on the stack: FIXME handle size != word  */
2652                         if (ainfo->regtype == RegTypeGeneral) {
2653                                 switch (ainfo->size) {
2654                                 case 1:
2655                                         g_assert (arm_is_imm12 (inst->inst_offset));
2656                                         ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2657                                         break;
2658                                 case 2:
2659                                         g_assert (arm_is_imm8 (inst->inst_offset));
2660                                         ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2661                                         break;
2662                                 case 8:
2663                                         g_assert (arm_is_imm12 (inst->inst_offset));
2664                                         ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2665                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
2666                                         ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
2667                                         break;
2668                                 default:
2669                                         g_assert (arm_is_imm12 (inst->inst_offset));
2670                                         ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2671                                         break;
2672                                 }
2673                         } else if (ainfo->regtype == RegTypeBase) {
2674                                 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
2675                                 switch (ainfo->size) {
2676                                 case 1:
2677                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2678                                         g_assert (arm_is_imm12 (inst->inst_offset));
2679                                         ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2680                                         break;
2681                                 case 2:
2682                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2683                                         g_assert (arm_is_imm8 (inst->inst_offset));
2684                                         ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2685                                         break;
2686                                 case 8:
2687                                         g_assert (arm_is_imm12 (inst->inst_offset));
2688                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2689                                         ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2690                                         g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4));
2691                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
2692                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
2693                                         ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
2694                                         break;
2695                                 default:
2696                                         g_assert (arm_is_imm12 (inst->inst_offset));
2697                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2698                                         ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2699                                         break;
2700                                 }
2701                         } else if (ainfo->regtype == RegTypeFP) {
2702                                 g_assert_not_reached ();
2703                         } else if (ainfo->regtype == RegTypeStructByVal) {
2704                                 int doffset = inst->inst_offset;
2705                                 int soffset = 0;
2706                                 int cur_reg;
2707                                 int size = 0;
2708                                 if (mono_class_from_mono_type (inst->inst_vtype))
2709                                         size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
2710                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
2711                                         g_assert (arm_is_imm12 (doffset));
2712                                         ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
2713                                         soffset += sizeof (gpointer);
2714                                         doffset += sizeof (gpointer);
2715                                 }
2716                                 if (ainfo->vtsize) {
2717                                         /* FIXME: handle overrun! with struct sizes not multiple of 4 */
2718                                         //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
2719                                         code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
2720                                 }
2721                         } else if (ainfo->regtype == RegTypeStructByAddr) {
2722                                 g_assert_not_reached ();
2723                                 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
2724                                 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
2725                         } else
2726                                 g_assert_not_reached ();
2727                 }
2728                 pos++;
2729         }
2730
2731         if (method->save_lmf) {
2732
2733                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2734                              (gpointer)"mono_get_lmf_addr");
2735                 if (cfg->method->dynamic) {
2736                         ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2737                         ARM_B (code, 0);
2738                         *(gpointer*)code = NULL;
2739                         code += 4;
2740                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2741                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2742                 } else {
2743                         ARM_BL (code, 0);
2744                 }
2745 #if ARM_PORT
2746                 /* we build the MonoLMF structure on the stack - see mini-arm.h */
2747                 /* lmf_offset is the offset from the previous stack pointer,
2748                  * alloc_size is the total stack space allocated, so the offset
2749                  * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
2750                  * The pointer to the struct is put in r1 (new_lmf).
2751                  * r2 is used as scratch
2752                  * The callee-saved registers are already in the MonoLMF structure
2753                  */
2754                 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, alloc_size - lmf_offset);
2755                 /* r0 is the result from mono_get_lmf_addr () */
2756                 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
2757                 /* new_lmf->previous_lmf = *lmf_addr */
2758                 ARM_LDR_IMM (code, ARMREG_R2, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2759                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2760                 /* *(lmf_addr) = r1 */
2761                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2762                 /* save method info */
2763                 code = mono_arm_emit_load_imm (code, ARMREG_R2, method);
2764                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, method));
2765                 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ebp));
2766                 /* save the current IP */
2767                 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
2768                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, eip));
2769 #endif
2770         }
2771
2772         if (tracing)
2773                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
2774
2775         cfg->code_len = code - cfg->native_code;
2776         g_assert (cfg->code_len < cfg->code_size);
2777         g_free (cinfo);
2778
2779         return code;
2780 }
2781
2782 void
2783 mono_arch_emit_epilog (MonoCompile *cfg)
2784 {
2785         MonoJumpInfo *patch_info;
2786         MonoMethod *method = cfg->method;
2787         int pos, i, rot_amount;
2788         int max_epilog_size = 16 + 20*4;
2789         guint8 *code;
2790
2791         if (cfg->method->save_lmf)
2792                 max_epilog_size += 128;
2793
2794         if (mono_jit_trace_calls != NULL)
2795                 max_epilog_size += 50;
2796
2797         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2798                 max_epilog_size += 50;
2799
2800         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
2801                 cfg->code_size *= 2;
2802                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2803                 mono_jit_stats.code_reallocs++;
2804         }
2805
2806         /*
2807          * Keep in sync with CEE_JMP
2808          */
2809         code = cfg->native_code + cfg->code_len;
2810
2811         if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
2812                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
2813         }
2814         pos = 0;
2815
2816         if (method->save_lmf) {
2817 #if ARM_PORT
2818                 int lmf_offset;
2819                 pos +=  sizeof (MonoLMF);
2820                 lmf_offset = pos;
2821                 /* r2 contains the pointer to the current LMF */
2822                 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, cfg->stack_usage - lmf_offset);
2823                 /* ip = previous_lmf */
2824                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2825                 /* lr = lmf_addr */
2826                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
2827                 /* *(lmf_addr) = previous_lmf */
2828                 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2829                 /* FIXME: speedup: there is no actual need to restore the registers if
2830                  * we didn't actually change them (idea from Zoltan).
2831                  */
2832                 /* restore iregs */
2833 #endif
2834                 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
2835                         ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
2836                 } else {
2837                         code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
2838                         ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
2839                 }
2840                 ARM_POP_NWB (code, cfg->used_int_regs | ((1 << ARMREG_SP) | (1 << ARMREG_PC)));
2841         } else {
2842                 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
2843                         ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
2844                 } else {
2845                         code = mono_arm_emit_load_imm (code, cfg->frame_reg, cfg->stack_usage);
2846                         ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
2847                 }
2848                 ARM_POP_NWB (code, cfg->used_int_regs | ((1 << ARMREG_SP) | (1 << ARMREG_PC)));
2849         }
2850
2851         cfg->code_len = code - cfg->native_code;
2852
2853         g_assert (cfg->code_len < cfg->code_size);
2854
2855 }
2856
2857 /* remove once throw_exception_by_name is eliminated */
2858 static int
2859 exception_id_by_name (const char *name)
2860 {
2861         if (strcmp (name, "IndexOutOfRangeException") == 0)
2862                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2863         if (strcmp (name, "OverflowException") == 0)
2864                 return MONO_EXC_OVERFLOW;
2865         if (strcmp (name, "ArithmeticException") == 0)
2866                 return MONO_EXC_ARITHMETIC;
2867         if (strcmp (name, "DivideByZeroException") == 0)
2868                 return MONO_EXC_DIVIDE_BY_ZERO;
2869         if (strcmp (name, "InvalidCastException") == 0)
2870                 return MONO_EXC_INVALID_CAST;
2871         if (strcmp (name, "NullReferenceException") == 0)
2872                 return MONO_EXC_NULL_REF;
2873         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2874                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2875         g_error ("Unknown intrinsic exception %s\n", name);
2876 }
2877
2878 void
2879 mono_arch_emit_exceptions (MonoCompile *cfg)
2880 {
2881         MonoJumpInfo *patch_info;
2882         int nthrows, i;
2883         guint8 *code;
2884         const guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM] = {NULL};
2885         guint8 exc_throw_found [MONO_EXC_INTRINS_NUM] = {0};
2886         guint32 code_size;
2887         int exc_count = 0;
2888         int max_epilog_size = 50;
2889
2890         /* count the number of exception infos */
2891
2892         /*
2893          * make sure we have enough space for exceptions
2894          * 12 is the simulated call to throw_exception_by_name
2895          */
2896         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
2897                 if (patch_info->type == MONO_PATCH_INFO_EXC) {
2898                         i = exception_id_by_name (patch_info->data.target);
2899                         if (!exc_throw_found [i]) {
2900                                 max_epilog_size += 12;
2901                                 exc_throw_found [i] = TRUE;
2902                         }
2903                 }
2904         }
2905
2906         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
2907                 cfg->code_size *= 2;
2908                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2909                 mono_jit_stats.code_reallocs++;
2910         }
2911
2912         code = cfg->native_code + cfg->code_len;
2913
2914         /* add code to raise exceptions */
2915         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
2916                 switch (patch_info->type) {
2917                 case MONO_PATCH_INFO_EXC: {
2918                         unsigned char *ip = patch_info->ip.i + cfg->native_code;
2919                         i = exception_id_by_name (patch_info->data.target);
2920                         if (exc_throw_pos [i]) {
2921                                 arm_patch (ip, exc_throw_pos [i]);
2922                                 patch_info->type = MONO_PATCH_INFO_NONE;
2923                                 break;
2924                         } else {
2925                                 exc_throw_pos [i] = code;
2926                         }
2927                         arm_patch (ip, code);
2928                         /*mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC_NAME, patch_info->data.target);*/
2929                         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
2930                         /* we got here from a conditional call, so the calling ip is set in lr already */
2931                         patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
2932                         patch_info->data.name = "mono_arch_throw_exception_by_name";
2933                         patch_info->ip.i = code - cfg->native_code;
2934                         ARM_B (code, 0);
2935                         *(gpointer*)code = patch_info->data.target;
2936                         code += 4;
2937                         break;
2938                 }
2939                 default:
2940                         /* do nothing */
2941                         break;
2942                 }
2943         }
2944
2945         cfg->code_len = code - cfg->native_code;
2946
2947         g_assert (cfg->code_len < cfg->code_size);
2948
2949 }
2950
2951 void
2952 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
2953 {
2954 }
2955
2956 void
2957 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
2958 {
2959 }
2960
2961 void
2962 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
2963 {
2964
2965         int this_dreg = ARMREG_R0;
2966
2967         if (vt_reg != -1)
2968                 this_dreg = ARMREG_R1;
2969
2970         /* add the this argument */
2971         if (this_reg != -1) {
2972                 MonoInst *this;
2973                 MONO_INST_NEW (cfg, this, OP_SETREG);
2974                 this->type = this_type;
2975                 this->sreg1 = this_reg;
2976                 this->dreg = mono_regstate_next_int (cfg->rs);
2977                 mono_bblock_add_inst (cfg->cbb, this);
2978                 mono_call_inst_add_outarg_reg (inst, this->dreg, this_dreg, FALSE);
2979         }
2980
2981         if (vt_reg != -1) {
2982                 MonoInst *vtarg;
2983                 MONO_INST_NEW (cfg, vtarg, OP_SETREG);
2984                 vtarg->type = STACK_MP;
2985                 vtarg->sreg1 = vt_reg;
2986                 vtarg->dreg = mono_regstate_next_int (cfg->rs);
2987                 mono_bblock_add_inst (cfg->cbb, vtarg);
2988                 mono_call_inst_add_outarg_reg (inst, vtarg->dreg, ARMREG_R0, FALSE);
2989         }
2990 }
2991
2992 MonoInst*
2993 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
2994 {
2995         return NULL;
2996 }
2997
2998 gboolean
2999 mono_arch_print_tree (MonoInst *tree, int arity)
3000 {
3001         return 0;
3002 }
3003
3004 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
3005 {
3006         return NULL;
3007 }
3008
3009 MonoInst*
3010 mono_arch_get_thread_intrinsic (MonoCompile* cfg)
3011 {
3012         return NULL;
3013 }
3014
3015 void
3016 mono_arch_flush_register_windows (void)
3017 {
3018 }
3019