2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
16 #include <mono/metadata/abi-details.h>
17 #include <mono/metadata/appdomain.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/utils/mono-mmap.h>
21 #include <mono/utils/mono-hwcap-arm.h>
22 #include <mono/utils/mono-memory-model.h>
25 #include "mini-arm-tls.h"
29 #include "debugger-agent.h"
31 #include "mono/arch/arm/arm-vfp-codegen.h"
33 #if (defined(HAVE_KW_THREAD) && defined(__linux__) && defined(__ARM_EABI__)) \
34 || defined(TARGET_ANDROID) \
35 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
39 /* Sanity check: This makes no sense */
40 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
41 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
45 * IS_SOFT_FLOAT: Is full software floating point used?
46 * IS_HARD_FLOAT: Is full hardware floating point used?
47 * IS_VFP: Is hardware floating point with software ABI used?
49 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
50 * IS_VFP may delegate to mono_arch_is_soft_float ().
53 #if defined(ARM_FPU_VFP_HARD)
54 #define IS_SOFT_FLOAT (FALSE)
55 #define IS_HARD_FLOAT (TRUE)
57 #elif defined(ARM_FPU_NONE)
58 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
59 #define IS_HARD_FLOAT (FALSE)
60 #define IS_VFP (!mono_arch_is_soft_float ())
62 #define IS_SOFT_FLOAT (FALSE)
63 #define IS_HARD_FLOAT (FALSE)
67 #define THUNK_SIZE (3 * 4)
69 #ifdef __native_client_codegen__
70 const guint kNaClAlignment = kNaClAlignmentARM;
71 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
72 gint8 nacl_align_byte = -1; /* 0xff */
75 mono_arch_nacl_pad (guint8 *code, int pad)
77 /* Not yet properly implemented. */
78 g_assert_not_reached ();
83 mono_arch_nacl_skip_nops (guint8 *code)
85 /* Not yet properly implemented. */
86 g_assert_not_reached ();
90 #endif /* __native_client_codegen__ */
92 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
95 void sys_icache_invalidate (void *start, size_t len);
98 /* This mutex protects architecture specific caches */
99 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
100 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
101 static mono_mutex_t mini_arch_mutex;
103 static gboolean v5_supported = FALSE;
104 static gboolean v6_supported = FALSE;
105 static gboolean v7_supported = FALSE;
106 static gboolean v7s_supported = FALSE;
107 static gboolean v7k_supported = FALSE;
108 static gboolean thumb_supported = FALSE;
109 static gboolean thumb2_supported = FALSE;
111 * Whenever to use the ARM EABI
113 static gboolean eabi_supported = FALSE;
116 * Whenever to use the iphone ABI extensions:
117 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
118 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
119 * This is required for debugging/profiling tools to work, but it has some overhead so it should
120 * only be turned on in debug builds.
122 static gboolean iphone_abi = FALSE;
125 * The FPU we are generating code for. This is NOT runtime configurable right now,
126 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
128 static MonoArmFPU arm_fpu;
130 #if defined(ARM_FPU_VFP_HARD)
132 * On armhf, d0-d7 are used for argument passing and d8-d15
133 * must be preserved across calls, which leaves us no room
134 * for scratch registers. So we use d14-d15 but back up their
135 * previous contents to a stack slot before using them - see
136 * mono_arm_emit_vfp_scratch_save/_restore ().
138 static int vfp_scratch1 = ARM_VFP_D14;
139 static int vfp_scratch2 = ARM_VFP_D15;
142 * On armel, d0-d7 do not need to be preserved, so we can
143 * freely make use of them as scratch registers.
145 static int vfp_scratch1 = ARM_VFP_D0;
146 static int vfp_scratch2 = ARM_VFP_D1;
151 static gpointer single_step_tramp, breakpoint_tramp;
154 * The code generated for sequence points reads from this location, which is
155 * made read-only when single stepping is enabled.
157 static gpointer ss_trigger_page;
159 /* Enabled breakpoints read from this trigger page */
160 static gpointer bp_trigger_page;
164 * floating point support: on ARM it is a mess, there are at least 3
165 * different setups, each of which binary incompat with the other.
166 * 1) FPA: old and ugly, but unfortunately what current distros use
167 * the double binary format has the two words swapped. 8 double registers.
168 * Implemented usually by kernel emulation.
169 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
170 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
171 * 3) VFP: the new and actually sensible and useful FP support. Implemented
172 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
174 * We do not care about FPA. We will support soft float and VFP.
176 int mono_exc_esp_offset = 0;
178 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
179 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
180 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
182 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
183 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
184 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
186 //#define DEBUG_IMT 0
189 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
193 mono_arch_regname (int reg)
195 static const char * rnames[] = {
196 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
197 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
198 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
201 if (reg >= 0 && reg < 16)
207 mono_arch_fregname (int reg)
209 static const char * rnames[] = {
210 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
211 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
212 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
213 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
214 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
215 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
218 if (reg >= 0 && reg < 32)
226 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
228 int imm8, rot_amount;
229 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
230 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
234 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
235 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
237 code = mono_arm_emit_load_imm (code, dreg, imm);
238 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
243 /* If dreg == sreg, this clobbers IP */
245 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
247 int imm8, rot_amount;
248 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
249 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
253 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
254 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
256 code = mono_arm_emit_load_imm (code, dreg, imm);
257 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
263 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
265 /* we can use r0-r3, since this is called only for incoming args on the stack */
266 if (size > sizeof (gpointer) * 4) {
268 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
269 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
270 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
271 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
272 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
273 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
274 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
275 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
276 ARM_B_COND (code, ARMCOND_NE, 0);
277 arm_patch (code - 4, start_loop);
280 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
281 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
283 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
284 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
290 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
291 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
292 doffset = soffset = 0;
294 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
295 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
301 g_assert (size == 0);
306 emit_call_reg (guint8 *code, int reg)
309 ARM_BLX_REG (code, reg);
311 #ifdef USE_JUMP_TABLES
312 g_assert_not_reached ();
314 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
318 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
324 emit_call_seq (MonoCompile *cfg, guint8 *code)
326 #ifdef USE_JUMP_TABLES
327 code = mono_arm_patchable_bl (code, ARMCOND_AL);
329 if (cfg->method->dynamic) {
330 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
332 *(gpointer*)code = NULL;
334 code = emit_call_reg (code, ARMREG_IP);
338 cfg->thunk_area += THUNK_SIZE;
344 mono_arm_patchable_b (guint8 *code, int cond)
346 #ifdef USE_JUMP_TABLES
349 jte = mono_jumptable_add_entry ();
350 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
351 ARM_BX_COND (code, cond, ARMREG_IP);
353 ARM_B_COND (code, cond, 0);
359 mono_arm_patchable_bl (guint8 *code, int cond)
361 #ifdef USE_JUMP_TABLES
364 jte = mono_jumptable_add_entry ();
365 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
366 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
368 ARM_BL_COND (code, cond, 0);
373 #ifdef USE_JUMP_TABLES
375 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
377 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
378 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
383 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
385 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
386 ARM_LDR_IMM (code, reg, reg, 0);
392 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
395 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
396 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
398 code = emit_call_seq (cfg, code);
399 if (dreg != ARMREG_R0)
400 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
402 g_assert_not_reached ();
408 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
411 if (tls_offset_reg != ARMREG_R0)
412 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
413 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
415 code = emit_call_seq (cfg, code);
416 if (dreg != ARMREG_R0)
417 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
419 g_assert_not_reached ();
425 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
428 if (sreg != ARMREG_R1)
429 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
430 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
431 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
433 code = emit_call_seq (cfg, code);
435 g_assert_not_reached ();
441 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
444 /* Get sreg in R1 and tls_offset_reg in R0 */
445 if (tls_offset_reg == ARMREG_R1) {
446 if (sreg == ARMREG_R0) {
447 /* swap sreg and tls_offset_reg */
448 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
449 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
450 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
452 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
453 if (sreg != ARMREG_R1)
454 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
457 if (sreg != ARMREG_R1)
458 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
459 if (tls_offset_reg != ARMREG_R0)
460 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
462 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
464 code = emit_call_seq (cfg, code);
466 g_assert_not_reached ();
474 * Emit code to push an LMF structure on the LMF stack.
475 * On arm, this is intermixed with the initialization of other fields of the structure.
478 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
480 gboolean get_lmf_fast = FALSE;
483 if (mono_arm_have_tls_get ()) {
485 if (cfg->compile_aot) {
487 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
488 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
490 *(gpointer*)code = NULL;
492 /* Load the value from the GOT */
493 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
494 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
496 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
497 g_assert (lmf_addr_tls_offset != -1);
498 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
503 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
504 (gpointer)"mono_get_lmf_addr");
505 code = emit_call_seq (cfg, code);
507 /* we build the MonoLMF structure on the stack - see mini-arm.h */
508 /* lmf_offset is the offset from the previous stack pointer,
509 * alloc_size is the total stack space allocated, so the offset
510 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
511 * The pointer to the struct is put in r1 (new_lmf).
512 * ip is used as scratch
513 * The callee-saved registers are already in the MonoLMF structure
515 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
516 /* r0 is the result from mono_get_lmf_addr () */
517 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
518 /* new_lmf->previous_lmf = *lmf_addr */
519 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
520 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
521 /* *(lmf_addr) = r1 */
522 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
523 /* Skip method (only needed for trampoline LMF frames) */
524 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
525 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
526 /* save the current IP */
527 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
528 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
530 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
531 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
542 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
546 g_assert (!cfg->r4fp);
548 for (list = inst->float_args; list; list = list->next) {
549 FloatArgData *fad = list->data;
550 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
551 gboolean imm = arm_is_fpimm8 (var->inst_offset);
553 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
559 if (*offset + *max_len > cfg->code_size) {
560 cfg->code_size += *max_len;
561 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
563 code = cfg->native_code + *offset;
567 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
568 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
570 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
572 *offset = code - cfg->native_code;
579 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
583 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
585 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
588 if (!arm_is_fpimm8 (inst->inst_offset)) {
589 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
590 ARM_FSTD (code, reg, ARMREG_LR, 0);
592 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
599 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
603 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
605 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
608 if (!arm_is_fpimm8 (inst->inst_offset)) {
609 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
610 ARM_FLDD (code, reg, ARMREG_LR, 0);
612 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
621 * Emit code to pop an LMF structure from the LMF stack.
624 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
628 if (lmf_offset < 32) {
629 basereg = cfg->frame_reg;
634 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
637 /* ip = previous_lmf */
638 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
640 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
641 /* *(lmf_addr) = previous_lmf */
642 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
647 #endif /* #ifndef DISABLE_JIT */
650 * mono_arm_have_tls_get:
652 * Returns whether we have tls access implemented on the current
656 mono_arm_have_tls_get (void)
666 * mono_arch_get_argument_info:
667 * @csig: a method signature
668 * @param_count: the number of parameters to consider
669 * @arg_info: an array to store the result infos
671 * Gathers information on parameters such as size, alignment and
672 * padding. arg_info should be large enought to hold param_count + 1 entries.
674 * Returns the size of the activation frame.
677 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
679 int k, frame_size = 0;
680 guint32 size, align, pad;
684 t = mini_get_underlying_type (csig->ret);
685 if (MONO_TYPE_ISSTRUCT (t)) {
686 frame_size += sizeof (gpointer);
690 arg_info [0].offset = offset;
693 frame_size += sizeof (gpointer);
697 arg_info [0].size = frame_size;
699 for (k = 0; k < param_count; k++) {
700 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
702 /* ignore alignment for now */
705 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
706 arg_info [k].pad = pad;
708 arg_info [k + 1].pad = 0;
709 arg_info [k + 1].size = size;
711 arg_info [k + 1].offset = offset;
715 align = MONO_ARCH_FRAME_ALIGNMENT;
716 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
717 arg_info [k].pad = pad;
722 #define MAX_ARCH_DELEGATE_PARAMS 3
725 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
727 guint8 *code, *start;
728 GSList *unwind_ops = mono_arch_get_cie_program ();
731 start = code = mono_global_codeman_reserve (12);
733 /* Replace the this argument with the target */
734 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
735 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
736 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
738 g_assert ((code - start) <= 12);
740 mono_arch_flush_icache (start, 12);
744 size = 8 + param_count * 4;
745 start = code = mono_global_codeman_reserve (size);
747 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
748 /* slide down the arguments */
749 for (i = 0; i < param_count; ++i) {
750 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
752 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
754 g_assert ((code - start) <= size);
756 mono_arch_flush_icache (start, size);
760 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
762 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
763 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
767 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
773 * mono_arch_get_delegate_invoke_impls:
775 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
779 mono_arch_get_delegate_invoke_impls (void)
785 get_delegate_invoke_impl (&info, TRUE, 0);
786 res = g_slist_prepend (res, info);
788 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
789 get_delegate_invoke_impl (&info, FALSE, i);
790 res = g_slist_prepend (res, info);
797 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
799 guint8 *code, *start;
802 /* FIXME: Support more cases */
803 sig_ret = mini_get_underlying_type (sig->ret);
804 if (MONO_TYPE_ISSTRUCT (sig_ret))
808 static guint8* cached = NULL;
809 mono_mini_arch_lock ();
811 mono_mini_arch_unlock ();
816 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
819 start = get_delegate_invoke_impl (&info, TRUE, 0);
820 mono_tramp_info_register (info, NULL);
823 mono_mini_arch_unlock ();
826 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
829 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
831 for (i = 0; i < sig->param_count; ++i)
832 if (!mono_is_regsize_var (sig->params [i]))
835 mono_mini_arch_lock ();
836 code = cache [sig->param_count];
838 mono_mini_arch_unlock ();
843 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
844 start = mono_aot_get_trampoline (name);
848 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
849 mono_tramp_info_register (info, NULL);
851 cache [sig->param_count] = start;
852 mono_mini_arch_unlock ();
860 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
866 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
868 return (gpointer)regs [ARMREG_R0];
872 * Initialize the cpu to execute managed code.
875 mono_arch_cpu_init (void)
877 i8_align = MONO_ABI_ALIGNOF (gint64);
878 #ifdef MONO_CROSS_COMPILE
879 /* Need to set the alignment of i8 since it can different on the target */
880 #ifdef TARGET_ANDROID
882 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
888 * Initialize architecture specific code.
891 mono_arch_init (void)
893 const char *cpu_arch;
895 mono_os_mutex_init_recursive (&mini_arch_mutex);
896 if (mini_get_debug_options ()->soft_breakpoints) {
897 breakpoint_tramp = mini_get_breakpoint_trampoline ();
899 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
900 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
901 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
904 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
905 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
906 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
907 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
908 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
910 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
912 #if defined(__ARM_EABI__)
913 eabi_supported = TRUE;
916 #if defined(ARM_FPU_VFP_HARD)
917 arm_fpu = MONO_ARM_FPU_VFP_HARD;
919 arm_fpu = MONO_ARM_FPU_VFP;
921 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
923 * If we're compiling with a soft float fallback and it
924 * turns out that no VFP unit is available, we need to
925 * switch to soft float. We don't do this for iOS, since
926 * iOS devices always have a VFP unit.
928 if (!mono_hwcap_arm_has_vfp)
929 arm_fpu = MONO_ARM_FPU_NONE;
932 * This environment variable can be useful in testing
933 * environments to make sure the soft float fallback
934 * works. Most ARM devices have VFP units these days, so
935 * normally soft float code would not be exercised much.
937 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
939 if (soft && !strncmp (soft, "1", 1))
940 arm_fpu = MONO_ARM_FPU_NONE;
944 v5_supported = mono_hwcap_arm_is_v5;
945 v6_supported = mono_hwcap_arm_is_v6;
946 v7_supported = mono_hwcap_arm_is_v7;
948 #if defined(__APPLE__)
949 /* iOS is special-cased here because we don't yet
950 have a way to properly detect CPU features on it. */
951 thumb_supported = TRUE;
954 thumb_supported = mono_hwcap_arm_has_thumb;
955 thumb2_supported = mono_hwcap_arm_has_thumb2;
958 /* Format: armv(5|6|7[s])[-thumb[2]] */
959 cpu_arch = g_getenv ("MONO_CPU_ARCH");
961 /* Do this here so it overrides any detection. */
963 if (strncmp (cpu_arch, "armv", 4) == 0) {
964 v5_supported = cpu_arch [4] >= '5';
965 v6_supported = cpu_arch [4] >= '6';
966 v7_supported = cpu_arch [4] >= '7';
967 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
968 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
971 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
972 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
977 * Cleanup architecture specific code.
980 mono_arch_cleanup (void)
985 * This function returns the optimizations supported on this cpu.
988 mono_arch_cpu_optimizations (guint32 *exclude_mask)
990 /* no arm-specific optimizations yet */
996 * This function test for all SIMD functions supported.
998 * Returns a bitmask corresponding to all supported versions.
1002 mono_arch_cpu_enumerate_simd_versions (void)
1004 /* SIMD is currently unimplemented */
1012 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1014 if (v7s_supported || v7k_supported) {
1028 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1030 mono_arch_is_soft_float (void)
1032 return arm_fpu == MONO_ARM_FPU_NONE;
1037 mono_arm_is_hard_float (void)
1039 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1043 is_regsize_var (MonoType *t)
1047 t = mini_get_underlying_type (t);
1054 case MONO_TYPE_FNPTR:
1056 case MONO_TYPE_OBJECT:
1057 case MONO_TYPE_STRING:
1058 case MONO_TYPE_CLASS:
1059 case MONO_TYPE_SZARRAY:
1060 case MONO_TYPE_ARRAY:
1062 case MONO_TYPE_GENERICINST:
1063 if (!mono_type_generic_inst_is_valuetype (t))
1066 case MONO_TYPE_VALUETYPE:
1073 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1078 for (i = 0; i < cfg->num_varinfo; i++) {
1079 MonoInst *ins = cfg->varinfo [i];
1080 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1083 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1086 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1089 /* we can only allocate 32 bit values */
1090 if (is_regsize_var (ins->inst_vtype)) {
1091 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1092 g_assert (i == vmv->idx);
1093 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1101 mono_arch_get_global_int_regs (MonoCompile *cfg)
1105 mono_arch_compute_omit_fp (cfg);
1108 * FIXME: Interface calls might go through a static rgctx trampoline which
1109 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1112 if (cfg->flags & MONO_CFG_HAS_CALLS)
1113 cfg->uses_rgctx_reg = TRUE;
1115 if (cfg->arch.omit_fp)
1116 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1117 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1118 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1119 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1121 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1122 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1124 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1125 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1126 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1127 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1128 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1129 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1135 * mono_arch_regalloc_cost:
1137 * Return the cost, in number of memory references, of the action of
1138 * allocating the variable VMV into a register during global register
1142 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1148 #endif /* #ifndef DISABLE_JIT */
1151 mono_arch_flush_icache (guint8 *code, gint size)
1153 #if defined(MONO_CROSS_COMPILE) || defined(__native_client__)
1154 // For Native Client we don't have to flush i-cache here,
1155 // as it's being done by dyncode interface.
1157 sys_icache_invalidate (code, size);
1159 __builtin___clear_cache (code, code + size);
1166 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1169 if (*gr > ARMREG_R3) {
1171 ainfo->offset = *stack_size;
1172 ainfo->reg = ARMREG_SP; /* in the caller */
1173 ainfo->storage = RegTypeBase;
1176 ainfo->storage = RegTypeGeneral;
1183 split = i8_align == 4;
1188 if (*gr == ARMREG_R3 && split) {
1189 /* first word in r3 and the second on the stack */
1190 ainfo->offset = *stack_size;
1191 ainfo->reg = ARMREG_SP; /* in the caller */
1192 ainfo->storage = RegTypeBaseGen;
1194 } else if (*gr >= ARMREG_R3) {
1195 if (eabi_supported) {
1196 /* darwin aligns longs to 4 byte only */
1197 if (i8_align == 8) {
1202 ainfo->offset = *stack_size;
1203 ainfo->reg = ARMREG_SP; /* in the caller */
1204 ainfo->storage = RegTypeBase;
1207 if (eabi_supported) {
1208 if (i8_align == 8 && ((*gr) & 1))
1211 ainfo->storage = RegTypeIRegPair;
1220 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1223 * If we're calling a function like this:
1225 * void foo(float a, double b, float c)
1227 * We pass a in s0 and b in d1. That leaves us
1228 * with s1 being unused. The armhf ABI recognizes
1229 * this and requires register assignment to then
1230 * use that for the next single-precision arg,
1231 * i.e. c in this example. So float_spare either
1232 * tells us which reg to use for the next single-
1233 * precision arg, or it's -1, meaning use *fpr.
1235 * Note that even though most of the JIT speaks
1236 * double-precision, fpr represents single-
1237 * precision registers.
1239 * See parts 5.5 and 6.1.2 of the AAPCS for how
1243 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1244 ainfo->storage = RegTypeFP;
1248 * If we're passing a double-precision value
1249 * and *fpr is odd (e.g. it's s1, s3, ...)
1250 * we need to use the next even register. So
1251 * we mark the current *fpr as a spare that
1252 * can be used for the next single-precision
1256 *float_spare = *fpr;
1261 * At this point, we have an even register
1262 * so we assign that and move along.
1266 } else if (*float_spare >= 0) {
1268 * We're passing a single-precision value
1269 * and it looks like a spare single-
1270 * precision register is available. Let's
1274 ainfo->reg = *float_spare;
1278 * If we hit this branch, we're passing a
1279 * single-precision value and we can simply
1280 * use the next available register.
1288 * We've exhausted available floating point
1289 * regs, so pass the rest on the stack.
1297 ainfo->offset = *stack_size;
1298 ainfo->reg = ARMREG_SP;
1299 ainfo->storage = RegTypeBase;
1306 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1310 MonoClassField *field;
1311 MonoType *ftype, *prev_ftype = NULL;
1314 klass = mono_class_from_mono_type (t);
1316 while ((field = mono_class_get_fields (klass, &iter))) {
1317 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1319 ftype = mono_field_get_type (field);
1320 ftype = mini_get_underlying_type (ftype);
1322 if (MONO_TYPE_ISSTRUCT (ftype)) {
1323 int nested_nfields, nested_esize;
1325 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1327 if (nested_esize == 4)
1328 ftype = &mono_defaults.single_class->byval_arg;
1330 ftype = &mono_defaults.double_class->byval_arg;
1331 if (prev_ftype && prev_ftype->type != ftype->type)
1334 nfields += nested_nfields;
1336 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1338 if (prev_ftype && prev_ftype->type != ftype->type)
1344 if (nfields == 0 || nfields > 4)
1346 *out_nfields = nfields;
1347 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1352 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1354 guint i, gr, fpr, pstart;
1356 int n = sig->hasthis + sig->param_count;
1360 guint32 stack_size = 0;
1362 gboolean is_pinvoke = sig->pinvoke;
1363 gboolean vtype_retaddr = FALSE;
1366 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1368 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1375 t = mini_get_underlying_type (sig->ret);
1386 case MONO_TYPE_FNPTR:
1387 case MONO_TYPE_CLASS:
1388 case MONO_TYPE_OBJECT:
1389 case MONO_TYPE_SZARRAY:
1390 case MONO_TYPE_ARRAY:
1391 case MONO_TYPE_STRING:
1392 cinfo->ret.storage = RegTypeGeneral;
1393 cinfo->ret.reg = ARMREG_R0;
1397 cinfo->ret.storage = RegTypeIRegPair;
1398 cinfo->ret.reg = ARMREG_R0;
1402 cinfo->ret.storage = RegTypeFP;
1404 if (t->type == MONO_TYPE_R4)
1405 cinfo->ret.size = 4;
1407 cinfo->ret.size = 8;
1409 if (IS_HARD_FLOAT) {
1410 cinfo->ret.reg = ARM_VFP_F0;
1412 cinfo->ret.reg = ARMREG_R0;
1415 case MONO_TYPE_GENERICINST:
1416 if (!mono_type_generic_inst_is_valuetype (t)) {
1417 cinfo->ret.storage = RegTypeGeneral;
1418 cinfo->ret.reg = ARMREG_R0;
1421 if (mini_is_gsharedvt_variable_type (t)) {
1422 cinfo->ret.storage = RegTypeStructByAddr;
1426 case MONO_TYPE_VALUETYPE:
1427 case MONO_TYPE_TYPEDBYREF:
1428 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1429 cinfo->ret.storage = RegTypeHFA;
1431 cinfo->ret.nregs = nfields;
1432 cinfo->ret.esize = esize;
1434 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1435 cinfo->ret.storage = RegTypeStructByVal;
1437 cinfo->ret.storage = RegTypeStructByAddr;
1441 case MONO_TYPE_MVAR:
1442 g_assert (mini_is_gsharedvt_type (t));
1443 cinfo->ret.storage = RegTypeStructByAddr;
1445 case MONO_TYPE_VOID:
1448 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1451 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1456 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1457 * the first argument, allowing 'this' to be always passed in the first arg reg.
1458 * Also do this if the first argument is a reference type, since virtual calls
1459 * are sometimes made using calli without sig->hasthis set, like in the delegate
1462 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1464 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1466 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1470 cinfo->ret.reg = gr;
1472 cinfo->vret_arg_index = 1;
1476 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1479 if (vtype_retaddr) {
1480 cinfo->ret.reg = gr;
1485 DEBUG(g_print("params: %d\n", sig->param_count));
1486 for (i = pstart; i < sig->param_count; ++i) {
1487 ArgInfo *ainfo = &cinfo->args [n];
1489 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1490 /* Prevent implicit arguments and sig_cookie from
1491 being passed in registers */
1494 /* Emit the signature cookie just before the implicit arguments */
1495 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1497 DEBUG(g_print("param %d: ", i));
1498 if (sig->params [i]->byref) {
1499 DEBUG(g_print("byref\n"));
1500 add_general (&gr, &stack_size, ainfo, TRUE);
1504 t = mini_get_underlying_type (sig->params [i]);
1508 cinfo->args [n].size = 1;
1509 add_general (&gr, &stack_size, ainfo, TRUE);
1513 cinfo->args [n].size = 2;
1514 add_general (&gr, &stack_size, ainfo, TRUE);
1518 cinfo->args [n].size = 4;
1519 add_general (&gr, &stack_size, ainfo, TRUE);
1524 case MONO_TYPE_FNPTR:
1525 case MONO_TYPE_CLASS:
1526 case MONO_TYPE_OBJECT:
1527 case MONO_TYPE_STRING:
1528 case MONO_TYPE_SZARRAY:
1529 case MONO_TYPE_ARRAY:
1530 cinfo->args [n].size = sizeof (gpointer);
1531 add_general (&gr, &stack_size, ainfo, TRUE);
1533 case MONO_TYPE_GENERICINST:
1534 if (!mono_type_generic_inst_is_valuetype (t)) {
1535 cinfo->args [n].size = sizeof (gpointer);
1536 add_general (&gr, &stack_size, ainfo, TRUE);
1539 if (mini_is_gsharedvt_variable_type (t)) {
1540 /* gsharedvt arguments are passed by ref */
1541 g_assert (mini_is_gsharedvt_type (t));
1542 add_general (&gr, &stack_size, ainfo, TRUE);
1543 switch (ainfo->storage) {
1544 case RegTypeGeneral:
1545 ainfo->storage = RegTypeGSharedVtInReg;
1548 ainfo->storage = RegTypeGSharedVtOnStack;
1551 g_assert_not_reached ();
1556 case MONO_TYPE_TYPEDBYREF:
1557 case MONO_TYPE_VALUETYPE: {
1560 int nwords, nfields, esize;
1563 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1564 if (fpr + nfields < ARM_VFP_F16) {
1565 ainfo->storage = RegTypeHFA;
1567 ainfo->nregs = nfields;
1568 ainfo->esize = esize;
1579 if (t->type == MONO_TYPE_TYPEDBYREF) {
1580 size = sizeof (MonoTypedRef);
1581 align = sizeof (gpointer);
1583 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1585 size = mono_class_native_size (klass, &align);
1587 size = mini_type_stack_size_full (t, &align, FALSE);
1589 DEBUG(g_print ("load %d bytes struct\n", size));
1592 align_size += (sizeof (gpointer) - 1);
1593 align_size &= ~(sizeof (gpointer) - 1);
1594 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1595 ainfo->storage = RegTypeStructByVal;
1596 ainfo->struct_size = size;
1597 /* FIXME: align stack_size if needed */
1598 if (eabi_supported) {
1599 if (align >= 8 && (gr & 1))
1602 if (gr > ARMREG_R3) {
1604 ainfo->vtsize = nwords;
1606 int rest = ARMREG_R3 - gr + 1;
1607 int n_in_regs = rest >= nwords? nwords: rest;
1609 ainfo->size = n_in_regs;
1610 ainfo->vtsize = nwords - n_in_regs;
1613 nwords -= n_in_regs;
1615 if (sig->call_convention == MONO_CALL_VARARG)
1616 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1617 stack_size = ALIGN_TO (stack_size, align);
1618 ainfo->offset = stack_size;
1619 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1620 stack_size += nwords * sizeof (gpointer);
1626 add_general (&gr, &stack_size, ainfo, FALSE);
1632 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1634 add_general (&gr, &stack_size, ainfo, TRUE);
1640 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1642 add_general (&gr, &stack_size, ainfo, FALSE);
1645 case MONO_TYPE_MVAR:
1646 /* gsharedvt arguments are passed by ref */
1647 g_assert (mini_is_gsharedvt_type (t));
1648 add_general (&gr, &stack_size, ainfo, TRUE);
1649 switch (ainfo->storage) {
1650 case RegTypeGeneral:
1651 ainfo->storage = RegTypeGSharedVtInReg;
1654 ainfo->storage = RegTypeGSharedVtOnStack;
1657 g_assert_not_reached ();
1661 g_error ("Can't handle 0x%x", sig->params [i]->type);
1666 /* Handle the case where there are no implicit arguments */
1667 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1668 /* Prevent implicit arguments and sig_cookie from
1669 being passed in registers */
1672 /* Emit the signature cookie just before the implicit arguments */
1673 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1676 /* align stack size to 8 */
1677 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1678 stack_size = (stack_size + 7) & ~7;
1680 cinfo->stack_usage = stack_size;
1686 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1688 MonoType *callee_ret;
1692 c1 = get_call_info (NULL, caller_sig);
1693 c2 = get_call_info (NULL, callee_sig);
1696 * Tail calls with more callee stack usage than the caller cannot be supported, since
1697 * the extra stack space would be left on the stack after the tail call.
1699 res = c1->stack_usage >= c2->stack_usage;
1700 callee_ret = mini_get_underlying_type (callee_sig->ret);
1701 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1702 /* An address on the callee's stack is passed as the first argument */
1705 if (c2->stack_usage > 16 * 4)
1717 debug_omit_fp (void)
1720 return mono_debug_count ();
1727 * mono_arch_compute_omit_fp:
1729 * Determine whenever the frame pointer can be eliminated.
1732 mono_arch_compute_omit_fp (MonoCompile *cfg)
1734 MonoMethodSignature *sig;
1735 MonoMethodHeader *header;
1739 if (cfg->arch.omit_fp_computed)
1742 header = cfg->header;
1744 sig = mono_method_signature (cfg->method);
1746 if (!cfg->arch.cinfo)
1747 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1748 cinfo = cfg->arch.cinfo;
1751 * FIXME: Remove some of the restrictions.
1753 cfg->arch.omit_fp = TRUE;
1754 cfg->arch.omit_fp_computed = TRUE;
1756 if (cfg->disable_omit_fp)
1757 cfg->arch.omit_fp = FALSE;
1758 if (!debug_omit_fp ())
1759 cfg->arch.omit_fp = FALSE;
1761 if (cfg->method->save_lmf)
1762 cfg->arch.omit_fp = FALSE;
1764 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1765 cfg->arch.omit_fp = FALSE;
1766 if (header->num_clauses)
1767 cfg->arch.omit_fp = FALSE;
1768 if (cfg->param_area)
1769 cfg->arch.omit_fp = FALSE;
1770 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1771 cfg->arch.omit_fp = FALSE;
1772 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1773 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1774 cfg->arch.omit_fp = FALSE;
1775 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1776 ArgInfo *ainfo = &cinfo->args [i];
1778 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1780 * The stack offset can only be determined when the frame
1783 cfg->arch.omit_fp = FALSE;
1788 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1789 MonoInst *ins = cfg->varinfo [i];
1792 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1797 * Set var information according to the calling convention. arm version.
1798 * The locals var stuff should most likely be split in another method.
1801 mono_arch_allocate_vars (MonoCompile *cfg)
1803 MonoMethodSignature *sig;
1804 MonoMethodHeader *header;
1807 int i, offset, size, align, curinst;
1812 sig = mono_method_signature (cfg->method);
1814 if (!cfg->arch.cinfo)
1815 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1816 cinfo = cfg->arch.cinfo;
1817 sig_ret = mini_get_underlying_type (sig->ret);
1819 mono_arch_compute_omit_fp (cfg);
1821 if (cfg->arch.omit_fp)
1822 cfg->frame_reg = ARMREG_SP;
1824 cfg->frame_reg = ARMREG_FP;
1826 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1828 /* allow room for the vararg method args: void* and long/double */
1829 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1830 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1832 header = cfg->header;
1834 /* See mono_arch_get_global_int_regs () */
1835 if (cfg->flags & MONO_CFG_HAS_CALLS)
1836 cfg->uses_rgctx_reg = TRUE;
1838 if (cfg->frame_reg != ARMREG_SP)
1839 cfg->used_int_regs |= 1 << cfg->frame_reg;
1841 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1842 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1843 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1847 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1848 if (sig_ret->type != MONO_TYPE_VOID) {
1849 cfg->ret->opcode = OP_REGVAR;
1850 cfg->ret->inst_c0 = ARMREG_R0;
1853 /* local vars are at a positive offset from the stack pointer */
1855 * also note that if the function uses alloca, we use FP
1856 * to point at the local variables.
1858 offset = 0; /* linkage area */
1859 /* align the offset to 16 bytes: not sure this is needed here */
1861 //offset &= ~(8 - 1);
1863 /* add parameter area size for called functions */
1864 offset += cfg->param_area;
1867 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1870 /* allow room to save the return value */
1871 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1874 switch (cinfo->ret.storage) {
1875 case RegTypeStructByVal:
1876 cfg->ret->opcode = OP_REGOFFSET;
1877 cfg->ret->inst_basereg = cfg->frame_reg;
1878 offset += sizeof (gpointer) - 1;
1879 offset &= ~(sizeof (gpointer) - 1);
1880 cfg->ret->inst_offset = - offset;
1881 offset += sizeof(gpointer);
1884 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1885 offset = ALIGN_TO (offset, 8);
1886 cfg->ret->opcode = OP_REGOFFSET;
1887 cfg->ret->inst_basereg = cfg->frame_reg;
1888 cfg->ret->inst_offset = offset;
1892 case RegTypeStructByAddr:
1893 ins = cfg->vret_addr;
1894 offset += sizeof(gpointer) - 1;
1895 offset &= ~(sizeof(gpointer) - 1);
1896 ins->inst_offset = offset;
1897 ins->opcode = OP_REGOFFSET;
1898 ins->inst_basereg = cfg->frame_reg;
1899 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1900 g_print ("vret_addr =");
1901 mono_print_ins (cfg->vret_addr);
1903 offset += sizeof(gpointer);
1909 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1910 if (cfg->arch.seq_point_info_var) {
1913 ins = cfg->arch.seq_point_info_var;
1917 offset += align - 1;
1918 offset &= ~(align - 1);
1919 ins->opcode = OP_REGOFFSET;
1920 ins->inst_basereg = cfg->frame_reg;
1921 ins->inst_offset = offset;
1924 ins = cfg->arch.ss_trigger_page_var;
1927 offset += align - 1;
1928 offset &= ~(align - 1);
1929 ins->opcode = OP_REGOFFSET;
1930 ins->inst_basereg = cfg->frame_reg;
1931 ins->inst_offset = offset;
1935 if (cfg->arch.seq_point_ss_method_var) {
1938 ins = cfg->arch.seq_point_ss_method_var;
1941 offset += align - 1;
1942 offset &= ~(align - 1);
1943 ins->opcode = OP_REGOFFSET;
1944 ins->inst_basereg = cfg->frame_reg;
1945 ins->inst_offset = offset;
1948 ins = cfg->arch.seq_point_bp_method_var;
1951 offset += align - 1;
1952 offset &= ~(align - 1);
1953 ins->opcode = OP_REGOFFSET;
1954 ins->inst_basereg = cfg->frame_reg;
1955 ins->inst_offset = offset;
1959 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1960 /* Allocate a temporary used by the atomic ops */
1964 /* Allocate a local slot to hold the sig cookie address */
1965 offset += align - 1;
1966 offset &= ~(align - 1);
1967 cfg->arch.atomic_tmp_offset = offset;
1970 cfg->arch.atomic_tmp_offset = -1;
1973 cfg->locals_min_stack_offset = offset;
1975 curinst = cfg->locals_start;
1976 for (i = curinst; i < cfg->num_varinfo; ++i) {
1979 ins = cfg->varinfo [i];
1980 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1983 t = ins->inst_vtype;
1984 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1987 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1988 * pinvoke wrappers when they call functions returning structure */
1989 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1990 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1994 size = mono_type_size (t, &align);
1996 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1997 * since it loads/stores misaligned words, which don't do the right thing.
1999 if (align < 4 && size >= 4)
2001 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2002 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2003 offset += align - 1;
2004 offset &= ~(align - 1);
2005 ins->opcode = OP_REGOFFSET;
2006 ins->inst_offset = offset;
2007 ins->inst_basereg = cfg->frame_reg;
2009 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2012 cfg->locals_max_stack_offset = offset;
2016 ins = cfg->args [curinst];
2017 if (ins->opcode != OP_REGVAR) {
2018 ins->opcode = OP_REGOFFSET;
2019 ins->inst_basereg = cfg->frame_reg;
2020 offset += sizeof (gpointer) - 1;
2021 offset &= ~(sizeof (gpointer) - 1);
2022 ins->inst_offset = offset;
2023 offset += sizeof (gpointer);
2028 if (sig->call_convention == MONO_CALL_VARARG) {
2032 /* Allocate a local slot to hold the sig cookie address */
2033 offset += align - 1;
2034 offset &= ~(align - 1);
2035 cfg->sig_cookie = offset;
2039 for (i = 0; i < sig->param_count; ++i) {
2040 ainfo = cinfo->args + i;
2042 ins = cfg->args [curinst];
2044 switch (ainfo->storage) {
2046 offset = ALIGN_TO (offset, 8);
2047 ins->opcode = OP_REGOFFSET;
2048 ins->inst_basereg = cfg->frame_reg;
2049 /* These arguments are saved to the stack in the prolog */
2050 ins->inst_offset = offset;
2051 if (cfg->verbose_level >= 2)
2052 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2060 if (ins->opcode != OP_REGVAR) {
2061 ins->opcode = OP_REGOFFSET;
2062 ins->inst_basereg = cfg->frame_reg;
2063 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2065 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2066 * since it loads/stores misaligned words, which don't do the right thing.
2068 if (align < 4 && size >= 4)
2070 /* The code in the prolog () stores words when storing vtypes received in a register */
2071 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2073 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2074 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2075 offset += align - 1;
2076 offset &= ~(align - 1);
2077 ins->inst_offset = offset;
2083 /* align the offset to 8 bytes */
2084 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2085 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2090 cfg->stack_offset = offset;
2094 mono_arch_create_vars (MonoCompile *cfg)
2096 MonoMethodSignature *sig;
2100 sig = mono_method_signature (cfg->method);
2102 if (!cfg->arch.cinfo)
2103 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2104 cinfo = cfg->arch.cinfo;
2106 if (IS_HARD_FLOAT) {
2107 for (i = 0; i < 2; i++) {
2108 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2109 inst->flags |= MONO_INST_VOLATILE;
2111 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2115 if (cinfo->ret.storage == RegTypeStructByVal)
2116 cfg->ret_var_is_local = TRUE;
2118 if (cinfo->ret.storage == RegTypeStructByAddr) {
2119 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2120 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2121 g_print ("vret_addr = ");
2122 mono_print_ins (cfg->vret_addr);
2126 if (cfg->gen_sdb_seq_points) {
2127 if (cfg->soft_breakpoints) {
2130 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2131 ins->flags |= MONO_INST_VOLATILE;
2132 cfg->arch.seq_point_ss_method_var = ins;
2134 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2135 ins->flags |= MONO_INST_VOLATILE;
2136 cfg->arch.seq_point_bp_method_var = ins;
2138 g_assert (!cfg->compile_aot);
2139 } else if (cfg->compile_aot) {
2140 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2141 ins->flags |= MONO_INST_VOLATILE;
2142 cfg->arch.seq_point_info_var = ins;
2144 /* Allocate a separate variable for this to save 1 load per seq point */
2145 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2146 ins->flags |= MONO_INST_VOLATILE;
2147 cfg->arch.ss_trigger_page_var = ins;
2153 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2155 MonoMethodSignature *tmp_sig;
2158 if (call->tail_call)
2161 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2164 * mono_ArgIterator_Setup assumes the signature cookie is
2165 * passed first and all the arguments which were before it are
2166 * passed on the stack after the signature. So compensate by
2167 * passing a different signature.
2169 tmp_sig = mono_metadata_signature_dup (call->signature);
2170 tmp_sig->param_count -= call->signature->sentinelpos;
2171 tmp_sig->sentinelpos = 0;
2172 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2174 sig_reg = mono_alloc_ireg (cfg);
2175 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2177 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2182 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2187 LLVMCallInfo *linfo;
2189 n = sig->param_count + sig->hasthis;
2191 cinfo = get_call_info (cfg->mempool, sig);
2193 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2196 * LLVM always uses the native ABI while we use our own ABI, the
2197 * only difference is the handling of vtypes:
2198 * - we only pass/receive them in registers in some cases, and only
2199 * in 1 or 2 integer registers.
2201 switch (cinfo->ret.storage) {
2202 case RegTypeGeneral:
2205 case RegTypeIRegPair:
2207 case RegTypeStructByAddr:
2208 /* Vtype returned using a hidden argument */
2209 linfo->ret.storage = LLVMArgVtypeRetAddr;
2210 linfo->vret_arg_index = cinfo->vret_arg_index;
2213 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2214 cfg->disable_llvm = TRUE;
2218 for (i = 0; i < n; ++i) {
2219 ainfo = cinfo->args + i;
2221 linfo->args [i].storage = LLVMArgNone;
2223 switch (ainfo->storage) {
2224 case RegTypeGeneral:
2225 case RegTypeIRegPair:
2227 case RegTypeBaseGen:
2228 linfo->args [i].storage = LLVMArgNormal;
2230 case RegTypeStructByVal:
2231 linfo->args [i].storage = LLVMArgAsIArgs;
2232 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2235 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2236 cfg->disable_llvm = TRUE;
2246 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2249 MonoMethodSignature *sig;
2253 sig = call->signature;
2254 n = sig->param_count + sig->hasthis;
2256 cinfo = get_call_info (cfg->mempool, sig);
2258 switch (cinfo->ret.storage) {
2259 case RegTypeStructByVal:
2260 /* The JIT will transform this into a normal call */
2261 call->vret_in_reg = TRUE;
2265 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2266 * the location pointed to by it after call in emit_move_return_value ().
2268 if (!cfg->arch.vret_addr_loc) {
2269 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2270 /* Prevent it from being register allocated or optimized away */
2271 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2274 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2276 case RegTypeStructByAddr: {
2278 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2279 vtarg->sreg1 = call->vret_var->dreg;
2280 vtarg->dreg = mono_alloc_preg (cfg);
2281 MONO_ADD_INS (cfg->cbb, vtarg);
2283 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2290 for (i = 0; i < n; ++i) {
2291 ArgInfo *ainfo = cinfo->args + i;
2294 if (i >= sig->hasthis)
2295 t = sig->params [i - sig->hasthis];
2297 t = &mono_defaults.int_class->byval_arg;
2298 t = mini_get_underlying_type (t);
2300 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2301 /* Emit the signature cookie just before the implicit arguments */
2302 emit_sig_cookie (cfg, call, cinfo);
2305 in = call->args [i];
2307 switch (ainfo->storage) {
2308 case RegTypeGeneral:
2309 case RegTypeIRegPair:
2310 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2311 MONO_INST_NEW (cfg, ins, OP_MOVE);
2312 ins->dreg = mono_alloc_ireg (cfg);
2313 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2314 MONO_ADD_INS (cfg->cbb, ins);
2315 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2317 MONO_INST_NEW (cfg, ins, OP_MOVE);
2318 ins->dreg = mono_alloc_ireg (cfg);
2319 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2320 MONO_ADD_INS (cfg->cbb, ins);
2321 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2322 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2323 if (ainfo->size == 4) {
2324 if (IS_SOFT_FLOAT) {
2325 /* mono_emit_call_args () have already done the r8->r4 conversion */
2326 /* The converted value is in an int vreg */
2327 MONO_INST_NEW (cfg, ins, OP_MOVE);
2328 ins->dreg = mono_alloc_ireg (cfg);
2329 ins->sreg1 = in->dreg;
2330 MONO_ADD_INS (cfg->cbb, ins);
2331 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2335 cfg->param_area = MAX (cfg->param_area, 8);
2336 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2337 creg = mono_alloc_ireg (cfg);
2338 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2339 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2342 if (IS_SOFT_FLOAT) {
2343 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2344 ins->dreg = mono_alloc_ireg (cfg);
2345 ins->sreg1 = in->dreg;
2346 MONO_ADD_INS (cfg->cbb, ins);
2347 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2349 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2350 ins->dreg = mono_alloc_ireg (cfg);
2351 ins->sreg1 = in->dreg;
2352 MONO_ADD_INS (cfg->cbb, ins);
2353 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2357 cfg->param_area = MAX (cfg->param_area, 8);
2358 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2359 creg = mono_alloc_ireg (cfg);
2360 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2361 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2362 creg = mono_alloc_ireg (cfg);
2363 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2364 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2367 cfg->flags |= MONO_CFG_HAS_FPOUT;
2369 MONO_INST_NEW (cfg, ins, OP_MOVE);
2370 ins->dreg = mono_alloc_ireg (cfg);
2371 ins->sreg1 = in->dreg;
2372 MONO_ADD_INS (cfg->cbb, ins);
2374 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2377 case RegTypeStructByAddr:
2380 /* FIXME: where si the data allocated? */
2381 arg->backend.reg3 = ainfo->reg;
2382 call->used_iregs |= 1 << ainfo->reg;
2383 g_assert_not_reached ();
2386 case RegTypeStructByVal:
2387 case RegTypeGSharedVtInReg:
2388 case RegTypeGSharedVtOnStack:
2390 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2391 ins->opcode = OP_OUTARG_VT;
2392 ins->sreg1 = in->dreg;
2393 ins->klass = in->klass;
2394 ins->inst_p0 = call;
2395 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2396 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2397 mono_call_inst_add_outarg_vt (cfg, call, ins);
2398 MONO_ADD_INS (cfg->cbb, ins);
2401 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2402 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2403 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2404 if (t->type == MONO_TYPE_R8) {
2405 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2408 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2410 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2413 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2416 case RegTypeBaseGen:
2417 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2418 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2419 MONO_INST_NEW (cfg, ins, OP_MOVE);
2420 ins->dreg = mono_alloc_ireg (cfg);
2421 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2422 MONO_ADD_INS (cfg->cbb, ins);
2423 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2424 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2427 /* This should work for soft-float as well */
2429 cfg->param_area = MAX (cfg->param_area, 8);
2430 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2431 creg = mono_alloc_ireg (cfg);
2432 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2433 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2434 creg = mono_alloc_ireg (cfg);
2435 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2436 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2437 cfg->flags |= MONO_CFG_HAS_FPOUT;
2439 g_assert_not_reached ();
2443 int fdreg = mono_alloc_freg (cfg);
2445 if (ainfo->size == 8) {
2446 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2447 ins->sreg1 = in->dreg;
2449 MONO_ADD_INS (cfg->cbb, ins);
2451 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2456 * Mono's register allocator doesn't speak single-precision registers that
2457 * overlap double-precision registers (i.e. armhf). So we have to work around
2458 * the register allocator and load the value from memory manually.
2460 * So we create a variable for the float argument and an instruction to store
2461 * the argument into the variable. We then store the list of these arguments
2462 * in cfg->float_args. This list is then used by emit_float_args later to
2463 * pass the arguments in the various call opcodes.
2465 * This is not very nice, and we should really try to fix the allocator.
2468 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2470 /* Make sure the instruction isn't seen as pointless and removed.
2472 float_arg->flags |= MONO_INST_VOLATILE;
2474 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2476 /* We use the dreg to look up the instruction later. The hreg is used to
2477 * emit the instruction that loads the value into the FP reg.
2479 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2480 fad->vreg = float_arg->dreg;
2481 fad->hreg = ainfo->reg;
2483 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2486 call->used_iregs |= 1 << ainfo->reg;
2487 cfg->flags |= MONO_CFG_HAS_FPOUT;
2491 g_assert_not_reached ();
2495 /* Handle the case where there are no implicit arguments */
2496 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2497 emit_sig_cookie (cfg, call, cinfo);
2499 call->call_info = cinfo;
2500 call->stack_usage = cinfo->stack_usage;
2504 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2510 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2511 ins->dreg = mono_alloc_freg (cfg);
2512 ins->sreg1 = arg->dreg;
2513 MONO_ADD_INS (cfg->cbb, ins);
2514 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2517 g_assert_not_reached ();
2523 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2525 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2527 ArgInfo *ainfo = ins->inst_p1;
2528 int ovf_size = ainfo->vtsize;
2529 int doffset = ainfo->offset;
2530 int struct_size = ainfo->struct_size;
2531 int i, soffset, dreg, tmpreg;
2533 switch (ainfo->storage) {
2534 case RegTypeGSharedVtInReg:
2536 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2538 case RegTypeGSharedVtOnStack:
2539 /* Pass by addr on stack */
2540 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2543 for (i = 0; i < ainfo->nregs; ++i) {
2544 if (ainfo->esize == 4)
2545 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2547 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2548 load->dreg = mono_alloc_freg (cfg);
2549 load->inst_basereg = src->dreg;
2550 load->inst_offset = i * ainfo->esize;
2551 MONO_ADD_INS (cfg->cbb, load);
2553 if (ainfo->esize == 4) {
2556 /* See RegTypeFP in mono_arch_emit_call () */
2557 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2558 float_arg->flags |= MONO_INST_VOLATILE;
2559 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2561 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2562 fad->vreg = float_arg->dreg;
2563 fad->hreg = ainfo->reg + i;
2565 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2567 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2573 for (i = 0; i < ainfo->size; ++i) {
2574 dreg = mono_alloc_ireg (cfg);
2575 switch (struct_size) {
2577 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2580 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2583 tmpreg = mono_alloc_ireg (cfg);
2584 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2585 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2586 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2587 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2588 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2589 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2590 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2593 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2596 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2597 soffset += sizeof (gpointer);
2598 struct_size -= sizeof (gpointer);
2600 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2602 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2608 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2610 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2613 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2616 if (COMPILE_LLVM (cfg)) {
2617 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2619 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2620 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2621 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2622 MONO_ADD_INS (cfg->cbb, ins);
2627 case MONO_ARM_FPU_NONE:
2628 if (ret->type == MONO_TYPE_R8) {
2631 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2632 ins->dreg = cfg->ret->dreg;
2633 ins->sreg1 = val->dreg;
2634 MONO_ADD_INS (cfg->cbb, ins);
2637 if (ret->type == MONO_TYPE_R4) {
2638 /* Already converted to an int in method_to_ir () */
2639 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2643 case MONO_ARM_FPU_VFP:
2644 case MONO_ARM_FPU_VFP_HARD:
2645 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2648 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2649 ins->dreg = cfg->ret->dreg;
2650 ins->sreg1 = val->dreg;
2651 MONO_ADD_INS (cfg->cbb, ins);
2656 g_assert_not_reached ();
2660 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2663 #endif /* #ifndef DISABLE_JIT */
2666 mono_arch_is_inst_imm (gint64 imm)
2672 MonoMethodSignature *sig;
2675 MonoType **param_types;
2679 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2683 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2686 switch (cinfo->ret.storage) {
2688 case RegTypeGeneral:
2689 case RegTypeIRegPair:
2690 case RegTypeStructByAddr:
2701 for (i = 0; i < cinfo->nargs; ++i) {
2702 ArgInfo *ainfo = &cinfo->args [i];
2705 switch (ainfo->storage) {
2706 case RegTypeGeneral:
2707 case RegTypeIRegPair:
2708 case RegTypeBaseGen:
2711 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2714 case RegTypeStructByVal:
2715 if (ainfo->size == 0)
2716 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2718 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2719 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2727 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2728 for (i = 0; i < sig->param_count; ++i) {
2729 MonoType *t = sig->params [i];
2734 t = mini_get_underlying_type (t);
2757 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2759 ArchDynCallInfo *info;
2763 cinfo = get_call_info (NULL, sig);
2765 if (!dyn_call_supported (cinfo, sig)) {
2770 info = g_new0 (ArchDynCallInfo, 1);
2771 // FIXME: Preprocess the info to speed up start_dyn_call ()
2773 info->cinfo = cinfo;
2774 info->rtype = mini_get_underlying_type (sig->ret);
2775 info->param_types = g_new0 (MonoType*, sig->param_count);
2776 for (i = 0; i < sig->param_count; ++i)
2777 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2779 return (MonoDynCallInfo*)info;
2783 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2785 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2787 g_free (ainfo->cinfo);
2792 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2794 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2795 DynCallArgs *p = (DynCallArgs*)buf;
2796 int arg_index, greg, i, j, pindex;
2797 MonoMethodSignature *sig = dinfo->sig;
2799 g_assert (buf_len >= sizeof (DynCallArgs));
2808 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2809 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2814 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2815 p->regs [greg ++] = (mgreg_t)ret;
2817 for (i = pindex; i < sig->param_count; i++) {
2818 MonoType *t = dinfo->param_types [i];
2819 gpointer *arg = args [arg_index ++];
2820 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2823 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2825 } else if (ainfo->storage == RegTypeBase) {
2826 slot = PARAM_REGS + (ainfo->offset / 4);
2827 } else if (ainfo->storage == RegTypeBaseGen) {
2828 /* slot + 1 is the first stack slot, so the code below will work */
2831 g_assert_not_reached ();
2835 p->regs [slot] = (mgreg_t)*arg;
2840 case MONO_TYPE_STRING:
2841 case MONO_TYPE_CLASS:
2842 case MONO_TYPE_ARRAY:
2843 case MONO_TYPE_SZARRAY:
2844 case MONO_TYPE_OBJECT:
2848 p->regs [slot] = (mgreg_t)*arg;
2851 p->regs [slot] = *(guint8*)arg;
2854 p->regs [slot] = *(gint8*)arg;
2857 p->regs [slot] = *(gint16*)arg;
2860 p->regs [slot] = *(guint16*)arg;
2863 p->regs [slot] = *(gint32*)arg;
2866 p->regs [slot] = *(guint32*)arg;
2870 p->regs [slot ++] = (mgreg_t)arg [0];
2871 p->regs [slot] = (mgreg_t)arg [1];
2874 p->regs [slot] = *(mgreg_t*)arg;
2877 p->regs [slot ++] = (mgreg_t)arg [0];
2878 p->regs [slot] = (mgreg_t)arg [1];
2880 case MONO_TYPE_GENERICINST:
2881 if (MONO_TYPE_IS_REFERENCE (t)) {
2882 p->regs [slot] = (mgreg_t)*arg;
2885 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2886 MonoClass *klass = mono_class_from_mono_type (t);
2887 guint8 *nullable_buf;
2890 size = mono_class_value_size (klass, NULL);
2891 nullable_buf = g_alloca (size);
2892 g_assert (nullable_buf);
2894 /* The argument pointed to by arg is either a boxed vtype or null */
2895 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2897 arg = (gpointer*)nullable_buf;
2903 case MONO_TYPE_VALUETYPE:
2904 g_assert (ainfo->storage == RegTypeStructByVal);
2906 if (ainfo->size == 0)
2907 slot = PARAM_REGS + (ainfo->offset / 4);
2911 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2912 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2915 g_assert_not_reached ();
2921 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2923 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2924 MonoType *ptype = ainfo->rtype;
2925 guint8 *ret = ((DynCallArgs*)buf)->ret;
2926 mgreg_t res = ((DynCallArgs*)buf)->res;
2927 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2929 switch (ptype->type) {
2930 case MONO_TYPE_VOID:
2931 *(gpointer*)ret = NULL;
2933 case MONO_TYPE_STRING:
2934 case MONO_TYPE_CLASS:
2935 case MONO_TYPE_ARRAY:
2936 case MONO_TYPE_SZARRAY:
2937 case MONO_TYPE_OBJECT:
2941 *(gpointer*)ret = (gpointer)res;
2947 *(guint8*)ret = res;
2950 *(gint16*)ret = res;
2953 *(guint16*)ret = res;
2956 *(gint32*)ret = res;
2959 *(guint32*)ret = res;
2963 /* This handles endianness as well */
2964 ((gint32*)ret) [0] = res;
2965 ((gint32*)ret) [1] = res2;
2967 case MONO_TYPE_GENERICINST:
2968 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2969 *(gpointer*)ret = (gpointer)res;
2974 case MONO_TYPE_VALUETYPE:
2975 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2980 *(float*)ret = *(float*)&res;
2982 case MONO_TYPE_R8: {
2989 *(double*)ret = *(double*)®s;
2993 g_assert_not_reached ();
3000 * Allow tracing to work with this interface (with an optional argument)
3004 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3008 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3009 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3010 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3011 code = emit_call_reg (code, ARMREG_R2);
3025 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3028 int save_mode = SAVE_NONE;
3030 MonoMethod *method = cfg->method;
3031 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3032 int rtype = ret_type->type;
3033 int save_offset = cfg->param_area;
3037 offset = code - cfg->native_code;
3038 /* we need about 16 instructions */
3039 if (offset > (cfg->code_size - 16 * 4)) {
3040 cfg->code_size *= 2;
3041 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3042 code = cfg->native_code + offset;
3045 case MONO_TYPE_VOID:
3046 /* special case string .ctor icall */
3047 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3048 save_mode = SAVE_ONE;
3050 save_mode = SAVE_NONE;
3054 save_mode = SAVE_TWO;
3058 save_mode = SAVE_ONE_FP;
3060 save_mode = SAVE_ONE;
3064 save_mode = SAVE_TWO_FP;
3066 save_mode = SAVE_TWO;
3068 case MONO_TYPE_GENERICINST:
3069 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3070 save_mode = SAVE_ONE;
3074 case MONO_TYPE_VALUETYPE:
3075 save_mode = SAVE_STRUCT;
3078 save_mode = SAVE_ONE;
3082 switch (save_mode) {
3084 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3085 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3086 if (enable_arguments) {
3087 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3088 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3092 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3093 if (enable_arguments) {
3094 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3098 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3099 if (enable_arguments) {
3100 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3104 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3105 if (enable_arguments) {
3106 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3110 if (enable_arguments) {
3111 /* FIXME: get the actual address */
3112 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3120 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3121 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3122 code = emit_call_reg (code, ARMREG_IP);
3124 switch (save_mode) {
3126 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3127 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3130 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3133 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3136 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3147 * The immediate field for cond branches is big enough for all reasonable methods
3149 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3150 if (0 && ins->inst_true_bb->native_offset) { \
3151 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3153 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3154 ARM_B_COND (code, (condcode), 0); \
3157 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3159 /* emit an exception if condition is fail
3161 * We assign the extra code used to throw the implicit exceptions
3162 * to cfg->bb_exit as far as the big branch handling is concerned
3164 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3166 mono_add_patch_info (cfg, code - cfg->native_code, \
3167 MONO_PATCH_INFO_EXC, exc_name); \
3168 ARM_BL_COND (code, (condcode), 0); \
3171 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3174 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3179 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3183 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3184 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3186 switch (ins->opcode) {
3189 /* Already done by an arch-independent pass */
3191 case OP_LOAD_MEMBASE:
3192 case OP_LOADI4_MEMBASE:
3194 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3195 * OP_LOAD_MEMBASE offset(basereg), reg
3197 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3198 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3199 ins->inst_basereg == last_ins->inst_destbasereg &&
3200 ins->inst_offset == last_ins->inst_offset) {
3201 if (ins->dreg == last_ins->sreg1) {
3202 MONO_DELETE_INS (bb, ins);
3205 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3206 ins->opcode = OP_MOVE;
3207 ins->sreg1 = last_ins->sreg1;
3211 * Note: reg1 must be different from the basereg in the second load
3212 * OP_LOAD_MEMBASE offset(basereg), reg1
3213 * OP_LOAD_MEMBASE offset(basereg), reg2
3215 * OP_LOAD_MEMBASE offset(basereg), reg1
3216 * OP_MOVE reg1, reg2
3218 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3219 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3220 ins->inst_basereg != last_ins->dreg &&
3221 ins->inst_basereg == last_ins->inst_basereg &&
3222 ins->inst_offset == last_ins->inst_offset) {
3224 if (ins->dreg == last_ins->dreg) {
3225 MONO_DELETE_INS (bb, ins);
3228 ins->opcode = OP_MOVE;
3229 ins->sreg1 = last_ins->dreg;
3232 //g_assert_not_reached ();
3236 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3237 * OP_LOAD_MEMBASE offset(basereg), reg
3239 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3240 * OP_ICONST reg, imm
3242 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3243 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3244 ins->inst_basereg == last_ins->inst_destbasereg &&
3245 ins->inst_offset == last_ins->inst_offset) {
3246 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3247 ins->opcode = OP_ICONST;
3248 ins->inst_c0 = last_ins->inst_imm;
3249 g_assert_not_reached (); // check this rule
3253 case OP_LOADU1_MEMBASE:
3254 case OP_LOADI1_MEMBASE:
3255 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3256 ins->inst_basereg == last_ins->inst_destbasereg &&
3257 ins->inst_offset == last_ins->inst_offset) {
3258 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3259 ins->sreg1 = last_ins->sreg1;
3262 case OP_LOADU2_MEMBASE:
3263 case OP_LOADI2_MEMBASE:
3264 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3265 ins->inst_basereg == last_ins->inst_destbasereg &&
3266 ins->inst_offset == last_ins->inst_offset) {
3267 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3268 ins->sreg1 = last_ins->sreg1;
3272 ins->opcode = OP_MOVE;
3276 if (ins->dreg == ins->sreg1) {
3277 MONO_DELETE_INS (bb, ins);
3281 * OP_MOVE sreg, dreg
3282 * OP_MOVE dreg, sreg
3284 if (last_ins && last_ins->opcode == OP_MOVE &&
3285 ins->sreg1 == last_ins->dreg &&
3286 ins->dreg == last_ins->sreg1) {
3287 MONO_DELETE_INS (bb, ins);
3296 * the branch_cc_table should maintain the order of these
3310 branch_cc_table [] = {
3324 #define ADD_NEW_INS(cfg,dest,op) do { \
3325 MONO_INST_NEW ((cfg), (dest), (op)); \
3326 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3330 map_to_reg_reg_op (int op)
3339 case OP_COMPARE_IMM:
3341 case OP_ICOMPARE_IMM:
3355 case OP_LOAD_MEMBASE:
3356 return OP_LOAD_MEMINDEX;
3357 case OP_LOADI4_MEMBASE:
3358 return OP_LOADI4_MEMINDEX;
3359 case OP_LOADU4_MEMBASE:
3360 return OP_LOADU4_MEMINDEX;
3361 case OP_LOADU1_MEMBASE:
3362 return OP_LOADU1_MEMINDEX;
3363 case OP_LOADI2_MEMBASE:
3364 return OP_LOADI2_MEMINDEX;
3365 case OP_LOADU2_MEMBASE:
3366 return OP_LOADU2_MEMINDEX;
3367 case OP_LOADI1_MEMBASE:
3368 return OP_LOADI1_MEMINDEX;
3369 case OP_STOREI1_MEMBASE_REG:
3370 return OP_STOREI1_MEMINDEX;
3371 case OP_STOREI2_MEMBASE_REG:
3372 return OP_STOREI2_MEMINDEX;
3373 case OP_STOREI4_MEMBASE_REG:
3374 return OP_STOREI4_MEMINDEX;
3375 case OP_STORE_MEMBASE_REG:
3376 return OP_STORE_MEMINDEX;
3377 case OP_STORER4_MEMBASE_REG:
3378 return OP_STORER4_MEMINDEX;
3379 case OP_STORER8_MEMBASE_REG:
3380 return OP_STORER8_MEMINDEX;
3381 case OP_STORE_MEMBASE_IMM:
3382 return OP_STORE_MEMBASE_REG;
3383 case OP_STOREI1_MEMBASE_IMM:
3384 return OP_STOREI1_MEMBASE_REG;
3385 case OP_STOREI2_MEMBASE_IMM:
3386 return OP_STOREI2_MEMBASE_REG;
3387 case OP_STOREI4_MEMBASE_IMM:
3388 return OP_STOREI4_MEMBASE_REG;
3390 g_assert_not_reached ();
3394 * Remove from the instruction list the instructions that can't be
3395 * represented with very simple instructions with no register
3399 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3401 MonoInst *ins, *temp, *last_ins = NULL;
3402 int rot_amount, imm8, low_imm;
3404 MONO_BB_FOR_EACH_INS (bb, ins) {
3406 switch (ins->opcode) {
3410 case OP_COMPARE_IMM:
3411 case OP_ICOMPARE_IMM:
3425 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3426 int opcode2 = mono_op_imm_to_op (ins->opcode);
3427 ADD_NEW_INS (cfg, temp, OP_ICONST);
3428 temp->inst_c0 = ins->inst_imm;
3429 temp->dreg = mono_alloc_ireg (cfg);
3430 ins->sreg2 = temp->dreg;
3432 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3433 ins->opcode = opcode2;
3435 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3441 if (ins->inst_imm == 1) {
3442 ins->opcode = OP_MOVE;
3445 if (ins->inst_imm == 0) {
3446 ins->opcode = OP_ICONST;
3450 imm8 = mono_is_power_of_two (ins->inst_imm);
3452 ins->opcode = OP_SHL_IMM;
3453 ins->inst_imm = imm8;
3456 ADD_NEW_INS (cfg, temp, OP_ICONST);
3457 temp->inst_c0 = ins->inst_imm;
3458 temp->dreg = mono_alloc_ireg (cfg);
3459 ins->sreg2 = temp->dreg;
3460 ins->opcode = OP_IMUL;
3466 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3467 /* ARM sets the C flag to 1 if there was _no_ overflow */
3468 ins->next->opcode = OP_COND_EXC_NC;
3471 case OP_IDIV_UN_IMM:
3473 case OP_IREM_UN_IMM: {
3474 int opcode2 = mono_op_imm_to_op (ins->opcode);
3475 ADD_NEW_INS (cfg, temp, OP_ICONST);
3476 temp->inst_c0 = ins->inst_imm;
3477 temp->dreg = mono_alloc_ireg (cfg);
3478 ins->sreg2 = temp->dreg;
3480 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3481 ins->opcode = opcode2;
3484 case OP_LOCALLOC_IMM:
3485 ADD_NEW_INS (cfg, temp, OP_ICONST);
3486 temp->inst_c0 = ins->inst_imm;
3487 temp->dreg = mono_alloc_ireg (cfg);
3488 ins->sreg1 = temp->dreg;
3489 ins->opcode = OP_LOCALLOC;
3491 case OP_LOAD_MEMBASE:
3492 case OP_LOADI4_MEMBASE:
3493 case OP_LOADU4_MEMBASE:
3494 case OP_LOADU1_MEMBASE:
3495 /* we can do two things: load the immed in a register
3496 * and use an indexed load, or see if the immed can be
3497 * represented as an ad_imm + a load with a smaller offset
3498 * that fits. We just do the first for now, optimize later.
3500 if (arm_is_imm12 (ins->inst_offset))
3502 ADD_NEW_INS (cfg, temp, OP_ICONST);
3503 temp->inst_c0 = ins->inst_offset;
3504 temp->dreg = mono_alloc_ireg (cfg);
3505 ins->sreg2 = temp->dreg;
3506 ins->opcode = map_to_reg_reg_op (ins->opcode);
3508 case OP_LOADI2_MEMBASE:
3509 case OP_LOADU2_MEMBASE:
3510 case OP_LOADI1_MEMBASE:
3511 if (arm_is_imm8 (ins->inst_offset))
3513 ADD_NEW_INS (cfg, temp, OP_ICONST);
3514 temp->inst_c0 = ins->inst_offset;
3515 temp->dreg = mono_alloc_ireg (cfg);
3516 ins->sreg2 = temp->dreg;
3517 ins->opcode = map_to_reg_reg_op (ins->opcode);
3519 case OP_LOADR4_MEMBASE:
3520 case OP_LOADR8_MEMBASE:
3521 if (arm_is_fpimm8 (ins->inst_offset))
3523 low_imm = ins->inst_offset & 0x1ff;
3524 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3525 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3526 temp->inst_imm = ins->inst_offset & ~0x1ff;
3527 temp->sreg1 = ins->inst_basereg;
3528 temp->dreg = mono_alloc_ireg (cfg);
3529 ins->inst_basereg = temp->dreg;
3530 ins->inst_offset = low_imm;
3534 ADD_NEW_INS (cfg, temp, OP_ICONST);
3535 temp->inst_c0 = ins->inst_offset;
3536 temp->dreg = mono_alloc_ireg (cfg);
3538 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3539 add_ins->sreg1 = ins->inst_basereg;
3540 add_ins->sreg2 = temp->dreg;
3541 add_ins->dreg = mono_alloc_ireg (cfg);
3543 ins->inst_basereg = add_ins->dreg;
3544 ins->inst_offset = 0;
3547 case OP_STORE_MEMBASE_REG:
3548 case OP_STOREI4_MEMBASE_REG:
3549 case OP_STOREI1_MEMBASE_REG:
3550 if (arm_is_imm12 (ins->inst_offset))
3552 ADD_NEW_INS (cfg, temp, OP_ICONST);
3553 temp->inst_c0 = ins->inst_offset;
3554 temp->dreg = mono_alloc_ireg (cfg);
3555 ins->sreg2 = temp->dreg;
3556 ins->opcode = map_to_reg_reg_op (ins->opcode);
3558 case OP_STOREI2_MEMBASE_REG:
3559 if (arm_is_imm8 (ins->inst_offset))
3561 ADD_NEW_INS (cfg, temp, OP_ICONST);
3562 temp->inst_c0 = ins->inst_offset;
3563 temp->dreg = mono_alloc_ireg (cfg);
3564 ins->sreg2 = temp->dreg;
3565 ins->opcode = map_to_reg_reg_op (ins->opcode);
3567 case OP_STORER4_MEMBASE_REG:
3568 case OP_STORER8_MEMBASE_REG:
3569 if (arm_is_fpimm8 (ins->inst_offset))
3571 low_imm = ins->inst_offset & 0x1ff;
3572 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3573 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3574 temp->inst_imm = ins->inst_offset & ~0x1ff;
3575 temp->sreg1 = ins->inst_destbasereg;
3576 temp->dreg = mono_alloc_ireg (cfg);
3577 ins->inst_destbasereg = temp->dreg;
3578 ins->inst_offset = low_imm;
3582 ADD_NEW_INS (cfg, temp, OP_ICONST);
3583 temp->inst_c0 = ins->inst_offset;
3584 temp->dreg = mono_alloc_ireg (cfg);
3586 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3587 add_ins->sreg1 = ins->inst_destbasereg;
3588 add_ins->sreg2 = temp->dreg;
3589 add_ins->dreg = mono_alloc_ireg (cfg);
3591 ins->inst_destbasereg = add_ins->dreg;
3592 ins->inst_offset = 0;
3595 case OP_STORE_MEMBASE_IMM:
3596 case OP_STOREI1_MEMBASE_IMM:
3597 case OP_STOREI2_MEMBASE_IMM:
3598 case OP_STOREI4_MEMBASE_IMM:
3599 ADD_NEW_INS (cfg, temp, OP_ICONST);
3600 temp->inst_c0 = ins->inst_imm;
3601 temp->dreg = mono_alloc_ireg (cfg);
3602 ins->sreg1 = temp->dreg;
3603 ins->opcode = map_to_reg_reg_op (ins->opcode);
3605 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3608 gboolean swap = FALSE;
3612 /* Optimized away */
3617 /* Some fp compares require swapped operands */
3618 switch (ins->next->opcode) {
3620 ins->next->opcode = OP_FBLT;
3624 ins->next->opcode = OP_FBLT_UN;
3628 ins->next->opcode = OP_FBGE;
3632 ins->next->opcode = OP_FBGE_UN;
3640 ins->sreg1 = ins->sreg2;
3649 bb->last_ins = last_ins;
3650 bb->max_vreg = cfg->next_vreg;
3654 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3658 if (long_ins->opcode == OP_LNEG) {
3660 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3661 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3667 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3669 /* sreg is a float, dreg is an integer reg */
3671 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3673 ARM_TOSIZD (code, vfp_scratch1, sreg);
3675 ARM_TOUIZD (code, vfp_scratch1, sreg);
3676 ARM_FMRS (code, dreg, vfp_scratch1);
3677 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3681 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3682 else if (size == 2) {
3683 ARM_SHL_IMM (code, dreg, dreg, 16);
3684 ARM_SHR_IMM (code, dreg, dreg, 16);
3688 ARM_SHL_IMM (code, dreg, dreg, 24);
3689 ARM_SAR_IMM (code, dreg, dreg, 24);
3690 } else if (size == 2) {
3691 ARM_SHL_IMM (code, dreg, dreg, 16);
3692 ARM_SAR_IMM (code, dreg, dreg, 16);
3699 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3701 /* sreg is a float, dreg is an integer reg */
3703 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3705 ARM_TOSIZS (code, vfp_scratch1, sreg);
3707 ARM_TOUIZS (code, vfp_scratch1, sreg);
3708 ARM_FMRS (code, dreg, vfp_scratch1);
3709 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3713 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3714 else if (size == 2) {
3715 ARM_SHL_IMM (code, dreg, dreg, 16);
3716 ARM_SHR_IMM (code, dreg, dreg, 16);
3720 ARM_SHL_IMM (code, dreg, dreg, 24);
3721 ARM_SAR_IMM (code, dreg, dreg, 24);
3722 } else if (size == 2) {
3723 ARM_SHL_IMM (code, dreg, dreg, 16);
3724 ARM_SAR_IMM (code, dreg, dreg, 16);
3730 #endif /* #ifndef DISABLE_JIT */
3732 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3735 emit_thunk (guint8 *code, gconstpointer target)
3739 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3740 if (thumb_supported)
3741 ARM_BX (code, ARMREG_IP);
3743 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3744 *(guint32*)code = (guint32)target;
3746 mono_arch_flush_icache (p, code - p);
3750 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3752 MonoJitInfo *ji = NULL;
3753 MonoThunkJitInfo *info;
3756 guint8 *orig_target;
3757 guint8 *target_thunk;
3760 domain = mono_domain_get ();
3764 * This can be called multiple times during JITting,
3765 * save the current position in cfg->arch to avoid
3766 * doing a O(n^2) search.
3768 if (!cfg->arch.thunks) {
3769 cfg->arch.thunks = cfg->thunks;
3770 cfg->arch.thunks_size = cfg->thunk_area;
3772 thunks = cfg->arch.thunks;
3773 thunks_size = cfg->arch.thunks_size;
3775 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3776 g_assert_not_reached ();
3779 g_assert (*(guint32*)thunks == 0);
3780 emit_thunk (thunks, target);
3781 arm_patch (code, thunks);
3783 cfg->arch.thunks += THUNK_SIZE;
3784 cfg->arch.thunks_size -= THUNK_SIZE;
3786 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3788 info = mono_jit_info_get_thunk_info (ji);
3791 thunks = (guint8*)ji->code_start + info->thunks_offset;
3792 thunks_size = info->thunks_size;
3794 orig_target = mono_arch_get_call_target (code + 4);
3796 mono_mini_arch_lock ();
3798 target_thunk = NULL;
3799 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3800 /* The call already points to a thunk, because of trampolines etc. */
3801 target_thunk = orig_target;
3803 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3804 if (((guint32*)p) [0] == 0) {
3808 } else if (((guint32*)p) [2] == (guint32)target) {
3809 /* Thunk already points to target */
3816 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3818 if (!target_thunk) {
3819 mono_mini_arch_unlock ();
3820 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3821 g_assert_not_reached ();
3824 emit_thunk (target_thunk, target);
3825 arm_patch (code, target_thunk);
3826 mono_arch_flush_icache (code, 4);
3828 mono_mini_arch_unlock ();
3833 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3835 guint32 *code32 = (void*)code;
3836 guint32 ins = *code32;
3837 guint32 prim = (ins >> 25) & 7;
3838 guint32 tval = GPOINTER_TO_UINT (target);
3840 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3841 if (prim == 5) { /* 101b */
3842 /* the diff starts 8 bytes from the branch opcode */
3843 gint diff = target - code - 8;
3845 gint tmask = 0xffffffff;
3846 if (tval & 1) { /* entering thumb mode */
3847 diff = target - 1 - code - 8;
3848 g_assert (thumb_supported);
3849 tbits = 0xf << 28; /* bl->blx bit pattern */
3850 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3851 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3855 tmask = ~(1 << 24); /* clear the link bit */
3856 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3861 if (diff <= 33554431) {
3863 ins = (ins & 0xff000000) | diff;
3865 *code32 = ins | tbits;
3869 /* diff between 0 and -33554432 */
3870 if (diff >= -33554432) {
3872 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3874 *code32 = ins | tbits;
3879 handle_thunk (cfg, domain, code, target);
3883 #ifdef USE_JUMP_TABLES
3885 gpointer *jte = mono_jumptable_get_entry (code);
3887 jte [0] = (gpointer) target;
3891 * The alternative call sequences looks like this:
3893 * ldr ip, [pc] // loads the address constant
3894 * b 1f // jumps around the constant
3895 * address constant embedded in the code
3900 * There are two cases for patching:
3901 * a) at the end of method emission: in this case code points to the start
3902 * of the call sequence
3903 * b) during runtime patching of the call site: in this case code points
3904 * to the mov pc, ip instruction
3906 * We have to handle also the thunk jump code sequence:
3910 * address constant // execution never reaches here
3912 if ((ins & 0x0ffffff0) == 0x12fff10) {
3913 /* Branch and exchange: the address is constructed in a reg
3914 * We can patch BX when the code sequence is the following:
3915 * ldr ip, [pc, #0] ; 0x8
3922 guint8 *emit = (guint8*)ccode;
3923 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3925 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3926 ARM_BX (emit, ARMREG_IP);
3928 /*patching from magic trampoline*/
3929 if (ins == ccode [3]) {
3930 g_assert (code32 [-4] == ccode [0]);
3931 g_assert (code32 [-3] == ccode [1]);
3932 g_assert (code32 [-1] == ccode [2]);
3933 code32 [-2] = (guint32)target;
3936 /*patching from JIT*/
3937 if (ins == ccode [0]) {
3938 g_assert (code32 [1] == ccode [1]);
3939 g_assert (code32 [3] == ccode [2]);
3940 g_assert (code32 [4] == ccode [3]);
3941 code32 [2] = (guint32)target;
3944 g_assert_not_reached ();
3945 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3953 guint8 *emit = (guint8*)ccode;
3954 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3956 ARM_BLX_REG (emit, ARMREG_IP);
3958 g_assert (code32 [-3] == ccode [0]);
3959 g_assert (code32 [-2] == ccode [1]);
3960 g_assert (code32 [0] == ccode [2]);
3962 code32 [-1] = (guint32)target;
3965 guint32 *tmp = ccode;
3966 guint8 *emit = (guint8*)tmp;
3967 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3968 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3969 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3970 ARM_BX (emit, ARMREG_IP);
3971 if (ins == ccode [2]) {
3972 g_assert_not_reached (); // should be -2 ...
3973 code32 [-1] = (guint32)target;
3976 if (ins == ccode [0]) {
3977 /* handles both thunk jump code and the far call sequence */
3978 code32 [2] = (guint32)target;
3981 g_assert_not_reached ();
3983 // g_print ("patched with 0x%08x\n", ins);
3988 arm_patch (guchar *code, const guchar *target)
3990 arm_patch_general (NULL, NULL, code, target);
3994 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3995 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3996 * to be used with the emit macros.
3997 * Return -1 otherwise.
4000 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4003 for (i = 0; i < 31; i+= 2) {
4004 res = (val << (32 - i)) | (val >> i);
4007 *rot_amount = i? 32 - i: 0;
4014 * Emits in code a sequence of instructions that load the value 'val'
4015 * into the dreg register. Uses at most 4 instructions.
4018 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4020 int imm8, rot_amount;
4022 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4023 /* skip the constant pool */
4029 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4030 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4031 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4035 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4036 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4037 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4038 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4041 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4043 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4047 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4049 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4051 if (val & 0xFF0000) {
4052 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4054 if (val & 0xFF000000) {
4055 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4057 } else if (val & 0xFF00) {
4058 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4059 if (val & 0xFF0000) {
4060 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4062 if (val & 0xFF000000) {
4063 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4065 } else if (val & 0xFF0000) {
4066 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4067 if (val & 0xFF000000) {
4068 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4071 //g_assert_not_reached ();
4077 mono_arm_thumb_supported (void)
4079 return thumb_supported;
4085 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4090 call = (MonoCallInst*)ins;
4091 cinfo = call->call_info;
4093 switch (cinfo->ret.storage) {
4095 MonoInst *loc = cfg->arch.vret_addr_loc;
4098 /* Load the destination address */
4099 g_assert (loc && loc->opcode == OP_REGOFFSET);
4101 if (arm_is_imm12 (loc->inst_offset)) {
4102 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4104 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4105 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4107 for (i = 0; i < cinfo->ret.nregs; ++i) {
4108 if (cinfo->ret.esize == 4)
4109 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4111 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4119 switch (ins->opcode) {
4122 case OP_FCALL_MEMBASE:
4124 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4125 if (sig_ret->type == MONO_TYPE_R4) {
4126 if (IS_HARD_FLOAT) {
4127 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4129 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4130 ARM_CVTS (code, ins->dreg, ins->dreg);
4133 if (IS_HARD_FLOAT) {
4134 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4136 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4143 case OP_RCALL_MEMBASE: {
4148 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4149 g_assert (sig_ret->type == MONO_TYPE_R4);
4150 if (IS_HARD_FLOAT) {
4151 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4153 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4154 ARM_CPYS (code, ins->dreg, ins->dreg);
4166 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4171 guint8 *code = cfg->native_code + cfg->code_len;
4172 MonoInst *last_ins = NULL;
4173 guint last_offset = 0;
4175 int imm8, rot_amount;
4177 /* we don't align basic blocks of loops on arm */
4179 if (cfg->verbose_level > 2)
4180 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4182 cpos = bb->max_offset;
4184 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4185 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4186 //g_assert (!mono_compile_aot);
4189 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4190 /* this is not thread save, but good enough */
4191 /* fixme: howto handle overflows? */
4192 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4195 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4196 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4197 (gpointer)"mono_break");
4198 code = emit_call_seq (cfg, code);
4201 MONO_BB_FOR_EACH_INS (bb, ins) {
4202 offset = code - cfg->native_code;
4204 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4206 if (offset > (cfg->code_size - max_len - 16)) {
4207 cfg->code_size *= 2;
4208 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4209 code = cfg->native_code + offset;
4211 // if (ins->cil_code)
4212 // g_print ("cil code\n");
4213 mono_debug_record_line_number (cfg, ins, offset);
4215 switch (ins->opcode) {
4216 case OP_MEMORY_BARRIER:
4218 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4219 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4223 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4225 case OP_TLS_GET_REG:
4226 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4229 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4231 case OP_TLS_SET_REG:
4232 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4234 case OP_ATOMIC_EXCHANGE_I4:
4235 case OP_ATOMIC_CAS_I4:
4236 case OP_ATOMIC_ADD_I4: {
4240 g_assert (v7_supported);
4243 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4245 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4247 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4251 g_assert (cfg->arch.atomic_tmp_offset != -1);
4252 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4254 switch (ins->opcode) {
4255 case OP_ATOMIC_EXCHANGE_I4:
4257 ARM_DMB (code, ARM_DMB_SY);
4258 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4259 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4260 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4262 ARM_B_COND (code, ARMCOND_NE, 0);
4263 arm_patch (buf [1], buf [0]);
4265 case OP_ATOMIC_CAS_I4:
4266 ARM_DMB (code, ARM_DMB_SY);
4268 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4269 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4271 ARM_B_COND (code, ARMCOND_NE, 0);
4272 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4273 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4275 ARM_B_COND (code, ARMCOND_NE, 0);
4276 arm_patch (buf [2], buf [0]);
4277 arm_patch (buf [1], code);
4279 case OP_ATOMIC_ADD_I4:
4281 ARM_DMB (code, ARM_DMB_SY);
4282 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4283 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4284 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4285 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4287 ARM_B_COND (code, ARMCOND_NE, 0);
4288 arm_patch (buf [1], buf [0]);
4291 g_assert_not_reached ();
4294 ARM_DMB (code, ARM_DMB_SY);
4295 if (tmpreg != ins->dreg)
4296 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4297 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4300 case OP_ATOMIC_LOAD_I1:
4301 case OP_ATOMIC_LOAD_U1:
4302 case OP_ATOMIC_LOAD_I2:
4303 case OP_ATOMIC_LOAD_U2:
4304 case OP_ATOMIC_LOAD_I4:
4305 case OP_ATOMIC_LOAD_U4:
4306 case OP_ATOMIC_LOAD_R4:
4307 case OP_ATOMIC_LOAD_R8: {
4308 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4309 ARM_DMB (code, ARM_DMB_SY);
4311 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4313 switch (ins->opcode) {
4314 case OP_ATOMIC_LOAD_I1:
4315 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4317 case OP_ATOMIC_LOAD_U1:
4318 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4320 case OP_ATOMIC_LOAD_I2:
4321 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4323 case OP_ATOMIC_LOAD_U2:
4324 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4326 case OP_ATOMIC_LOAD_I4:
4327 case OP_ATOMIC_LOAD_U4:
4328 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4330 case OP_ATOMIC_LOAD_R4:
4332 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4333 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4335 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4336 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4337 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4338 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4339 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4342 case OP_ATOMIC_LOAD_R8:
4343 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4344 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4348 ARM_DMB (code, ARM_DMB_SY);
4351 case OP_ATOMIC_STORE_I1:
4352 case OP_ATOMIC_STORE_U1:
4353 case OP_ATOMIC_STORE_I2:
4354 case OP_ATOMIC_STORE_U2:
4355 case OP_ATOMIC_STORE_I4:
4356 case OP_ATOMIC_STORE_U4:
4357 case OP_ATOMIC_STORE_R4:
4358 case OP_ATOMIC_STORE_R8: {
4359 ARM_DMB (code, ARM_DMB_SY);
4361 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4363 switch (ins->opcode) {
4364 case OP_ATOMIC_STORE_I1:
4365 case OP_ATOMIC_STORE_U1:
4366 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4368 case OP_ATOMIC_STORE_I2:
4369 case OP_ATOMIC_STORE_U2:
4370 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4372 case OP_ATOMIC_STORE_I4:
4373 case OP_ATOMIC_STORE_U4:
4374 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4376 case OP_ATOMIC_STORE_R4:
4378 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4379 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4381 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4382 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4383 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4384 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4385 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4388 case OP_ATOMIC_STORE_R8:
4389 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4390 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4394 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4395 ARM_DMB (code, ARM_DMB_SY);
4399 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4400 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4403 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4404 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4406 case OP_STOREI1_MEMBASE_IMM:
4407 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4408 g_assert (arm_is_imm12 (ins->inst_offset));
4409 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4411 case OP_STOREI2_MEMBASE_IMM:
4412 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4413 g_assert (arm_is_imm8 (ins->inst_offset));
4414 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4416 case OP_STORE_MEMBASE_IMM:
4417 case OP_STOREI4_MEMBASE_IMM:
4418 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4419 g_assert (arm_is_imm12 (ins->inst_offset));
4420 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4422 case OP_STOREI1_MEMBASE_REG:
4423 g_assert (arm_is_imm12 (ins->inst_offset));
4424 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4426 case OP_STOREI2_MEMBASE_REG:
4427 g_assert (arm_is_imm8 (ins->inst_offset));
4428 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4430 case OP_STORE_MEMBASE_REG:
4431 case OP_STOREI4_MEMBASE_REG:
4432 /* this case is special, since it happens for spill code after lowering has been called */
4433 if (arm_is_imm12 (ins->inst_offset)) {
4434 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4436 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4437 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4440 case OP_STOREI1_MEMINDEX:
4441 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4443 case OP_STOREI2_MEMINDEX:
4444 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4446 case OP_STORE_MEMINDEX:
4447 case OP_STOREI4_MEMINDEX:
4448 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4451 g_assert_not_reached ();
4453 case OP_LOAD_MEMINDEX:
4454 case OP_LOADI4_MEMINDEX:
4455 case OP_LOADU4_MEMINDEX:
4456 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4458 case OP_LOADI1_MEMINDEX:
4459 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4461 case OP_LOADU1_MEMINDEX:
4462 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4464 case OP_LOADI2_MEMINDEX:
4465 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4467 case OP_LOADU2_MEMINDEX:
4468 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4470 case OP_LOAD_MEMBASE:
4471 case OP_LOADI4_MEMBASE:
4472 case OP_LOADU4_MEMBASE:
4473 /* this case is special, since it happens for spill code after lowering has been called */
4474 if (arm_is_imm12 (ins->inst_offset)) {
4475 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4477 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4478 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4481 case OP_LOADI1_MEMBASE:
4482 g_assert (arm_is_imm8 (ins->inst_offset));
4483 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4485 case OP_LOADU1_MEMBASE:
4486 g_assert (arm_is_imm12 (ins->inst_offset));
4487 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4489 case OP_LOADU2_MEMBASE:
4490 g_assert (arm_is_imm8 (ins->inst_offset));
4491 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4493 case OP_LOADI2_MEMBASE:
4494 g_assert (arm_is_imm8 (ins->inst_offset));
4495 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4497 case OP_ICONV_TO_I1:
4498 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4499 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4501 case OP_ICONV_TO_I2:
4502 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4503 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4505 case OP_ICONV_TO_U1:
4506 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4508 case OP_ICONV_TO_U2:
4509 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4510 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4514 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4516 case OP_COMPARE_IMM:
4517 case OP_ICOMPARE_IMM:
4518 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4519 g_assert (imm8 >= 0);
4520 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4524 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4525 * So instead of emitting a trap, we emit a call a C function and place a
4528 //*(int*)code = 0xef9f0001;
4531 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4532 (gpointer)"mono_break");
4533 code = emit_call_seq (cfg, code);
4535 case OP_RELAXED_NOP:
4540 case OP_DUMMY_STORE:
4541 case OP_DUMMY_ICONST:
4542 case OP_DUMMY_R8CONST:
4543 case OP_NOT_REACHED:
4546 case OP_IL_SEQ_POINT:
4547 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4549 case OP_SEQ_POINT: {
4551 MonoInst *info_var = cfg->arch.seq_point_info_var;
4552 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4553 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4554 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4556 int dreg = ARMREG_LR;
4558 if (cfg->soft_breakpoints) {
4559 g_assert (!cfg->compile_aot);
4563 * For AOT, we use one got slot per method, which will point to a
4564 * SeqPointInfo structure, containing all the information required
4565 * by the code below.
4567 if (cfg->compile_aot) {
4568 g_assert (info_var);
4569 g_assert (info_var->opcode == OP_REGOFFSET);
4570 g_assert (arm_is_imm12 (info_var->inst_offset));
4573 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4575 * Read from the single stepping trigger page. This will cause a
4576 * SIGSEGV when single stepping is enabled.
4577 * We do this _before_ the breakpoint, so single stepping after
4578 * a breakpoint is hit will step to the next IL offset.
4580 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4583 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4584 if (cfg->soft_breakpoints) {
4585 /* Load the address of the sequence point method variable. */
4586 var = ss_method_var;
4588 g_assert (var->opcode == OP_REGOFFSET);
4589 g_assert (arm_is_imm12 (var->inst_offset));
4590 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4592 /* Read the value and check whether it is non-zero. */
4593 ARM_LDR_IMM (code, dreg, dreg, 0);
4594 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4595 /* Call it conditionally. */
4596 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4598 if (cfg->compile_aot) {
4599 /* Load the trigger page addr from the variable initialized in the prolog */
4600 var = ss_trigger_page_var;
4602 g_assert (var->opcode == OP_REGOFFSET);
4603 g_assert (arm_is_imm12 (var->inst_offset));
4604 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4606 #ifdef USE_JUMP_TABLES
4607 gpointer *jte = mono_jumptable_add_entry ();
4608 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4609 jte [0] = ss_trigger_page;
4611 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4613 *(int*)code = (int)ss_trigger_page;
4617 ARM_LDR_IMM (code, dreg, dreg, 0);
4621 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4623 if (cfg->soft_breakpoints) {
4624 /* Load the address of the breakpoint method into ip. */
4625 var = bp_method_var;
4627 g_assert (var->opcode == OP_REGOFFSET);
4628 g_assert (arm_is_imm12 (var->inst_offset));
4629 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4632 * A placeholder for a possible breakpoint inserted by
4633 * mono_arch_set_breakpoint ().
4636 } else if (cfg->compile_aot) {
4637 guint32 offset = code - cfg->native_code;
4640 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4641 /* Add the offset */
4642 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4643 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4644 if (arm_is_imm12 ((int)val)) {
4645 ARM_LDR_IMM (code, dreg, dreg, val);
4647 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4649 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4651 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4652 g_assert (!(val & 0xFF000000));
4654 ARM_LDR_IMM (code, dreg, dreg, 0);
4656 /* What is faster, a branch or a load ? */
4657 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4658 /* The breakpoint instruction */
4659 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4662 * A placeholder for a possible breakpoint inserted by
4663 * mono_arch_set_breakpoint ().
4665 for (i = 0; i < 4; ++i)
4670 * Add an additional nop so skipping the bp doesn't cause the ip to point
4671 * to another IL offset.
4679 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4682 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4686 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4689 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4690 g_assert (imm8 >= 0);
4691 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4695 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4696 g_assert (imm8 >= 0);
4697 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4701 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4702 g_assert (imm8 >= 0);
4703 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4706 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4707 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4709 case OP_IADD_OVF_UN:
4710 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4711 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4714 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4715 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4717 case OP_ISUB_OVF_UN:
4718 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4719 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4721 case OP_ADD_OVF_CARRY:
4722 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4723 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4725 case OP_ADD_OVF_UN_CARRY:
4726 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4727 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4729 case OP_SUB_OVF_CARRY:
4730 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4731 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4733 case OP_SUB_OVF_UN_CARRY:
4734 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4735 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4739 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4742 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4743 g_assert (imm8 >= 0);
4744 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4747 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4751 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4755 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4756 g_assert (imm8 >= 0);
4757 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4761 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4762 g_assert (imm8 >= 0);
4763 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4765 case OP_ARM_RSBS_IMM:
4766 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4767 g_assert (imm8 >= 0);
4768 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4770 case OP_ARM_RSC_IMM:
4771 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4772 g_assert (imm8 >= 0);
4773 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4776 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4780 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4781 g_assert (imm8 >= 0);
4782 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4785 g_assert (v7s_supported || v7k_supported);
4786 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4789 g_assert (v7s_supported || v7k_supported);
4790 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4793 g_assert (v7s_supported || v7k_supported);
4794 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4795 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4798 g_assert (v7s_supported || v7k_supported);
4799 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4800 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4804 g_assert_not_reached ();
4806 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4810 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4811 g_assert (imm8 >= 0);
4812 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4815 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4819 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4820 g_assert (imm8 >= 0);
4821 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4824 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4829 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4830 else if (ins->dreg != ins->sreg1)
4831 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4834 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4839 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4840 else if (ins->dreg != ins->sreg1)
4841 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4844 case OP_ISHR_UN_IMM:
4846 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4847 else if (ins->dreg != ins->sreg1)
4848 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4851 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4854 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4857 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4860 if (ins->dreg == ins->sreg2)
4861 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4863 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4866 g_assert_not_reached ();
4869 /* FIXME: handle ovf/ sreg2 != dreg */
4870 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4871 /* FIXME: MUL doesn't set the C/O flags on ARM */
4873 case OP_IMUL_OVF_UN:
4874 /* FIXME: handle ovf/ sreg2 != dreg */
4875 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4876 /* FIXME: MUL doesn't set the C/O flags on ARM */
4879 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4882 /* Load the GOT offset */
4883 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4884 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4886 *(gpointer*)code = NULL;
4888 /* Load the value from the GOT */
4889 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4891 case OP_OBJC_GET_SELECTOR:
4892 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4893 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4895 *(gpointer*)code = NULL;
4897 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4899 case OP_ICONV_TO_I4:
4900 case OP_ICONV_TO_U4:
4902 if (ins->dreg != ins->sreg1)
4903 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4906 int saved = ins->sreg2;
4907 if (ins->sreg2 == ARM_LSW_REG) {
4908 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4911 if (ins->sreg1 != ARM_LSW_REG)
4912 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4913 if (saved != ARM_MSW_REG)
4914 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4918 if (IS_VFP && ins->dreg != ins->sreg1)
4919 ARM_CPYD (code, ins->dreg, ins->sreg1);
4922 if (IS_VFP && ins->dreg != ins->sreg1)
4923 ARM_CPYS (code, ins->dreg, ins->sreg1);
4925 case OP_MOVE_F_TO_I4:
4927 ARM_FMRS (code, ins->dreg, ins->sreg1);
4929 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4930 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4931 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4932 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4935 case OP_MOVE_I4_TO_F:
4937 ARM_FMSR (code, ins->dreg, ins->sreg1);
4939 ARM_FMSR (code, ins->dreg, ins->sreg1);
4940 ARM_CVTS (code, ins->dreg, ins->dreg);
4943 case OP_FCONV_TO_R4:
4946 ARM_CVTD (code, ins->dreg, ins->sreg1);
4948 ARM_CVTD (code, ins->dreg, ins->sreg1);
4949 ARM_CVTS (code, ins->dreg, ins->dreg);
4954 MonoCallInst *call = (MonoCallInst*)ins;
4957 * The stack looks like the following:
4958 * <caller argument area>
4961 * <callee argument area>
4962 * Need to copy the arguments from the callee argument area to
4963 * the caller argument area, and pop the frame.
4965 if (call->stack_usage) {
4966 int i, prev_sp_offset = 0;
4968 /* Compute size of saved registers restored below */
4970 prev_sp_offset = 2 * 4;
4972 prev_sp_offset = 1 * 4;
4973 for (i = 0; i < 16; ++i) {
4974 if (cfg->used_int_regs & (1 << i))
4975 prev_sp_offset += 4;
4978 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4980 /* Copy arguments on the stack to our argument area */
4981 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4982 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4983 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4988 * Keep in sync with mono_arch_emit_epilog
4990 g_assert (!cfg->method->save_lmf);
4992 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4994 if (cfg->used_int_regs)
4995 ARM_POP (code, cfg->used_int_regs);
4996 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4998 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5001 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5002 if (cfg->compile_aot) {
5003 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5005 *(gpointer*)code = NULL;
5007 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5009 code = mono_arm_patchable_b (code, ARMCOND_AL);
5010 cfg->thunk_area += THUNK_SIZE;
5015 /* ensure ins->sreg1 is not NULL */
5016 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5019 g_assert (cfg->sig_cookie < 128);
5020 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5021 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5031 call = (MonoCallInst*)ins;
5034 code = emit_float_args (cfg, call, code, &max_len, &offset);
5036 if (ins->flags & MONO_INST_HAS_METHOD)
5037 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5039 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5040 code = emit_call_seq (cfg, code);
5041 ins->flags |= MONO_INST_GC_CALLSITE;
5042 ins->backend.pc_offset = code - cfg->native_code;
5043 code = emit_move_return_value (cfg, ins, code);
5050 case OP_VOIDCALL_REG:
5053 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5055 code = emit_call_reg (code, ins->sreg1);
5056 ins->flags |= MONO_INST_GC_CALLSITE;
5057 ins->backend.pc_offset = code - cfg->native_code;
5058 code = emit_move_return_value (cfg, ins, code);
5060 case OP_FCALL_MEMBASE:
5061 case OP_RCALL_MEMBASE:
5062 case OP_LCALL_MEMBASE:
5063 case OP_VCALL_MEMBASE:
5064 case OP_VCALL2_MEMBASE:
5065 case OP_VOIDCALL_MEMBASE:
5066 case OP_CALL_MEMBASE: {
5067 g_assert (ins->sreg1 != ARMREG_LR);
5068 call = (MonoCallInst*)ins;
5071 code = emit_float_args (cfg, call, code, &max_len, &offset);
5072 if (!arm_is_imm12 (ins->inst_offset)) {
5073 /* sreg1 might be IP */
5074 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5075 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5076 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5077 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5078 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5080 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5081 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5083 ins->flags |= MONO_INST_GC_CALLSITE;
5084 ins->backend.pc_offset = code - cfg->native_code;
5085 code = emit_move_return_value (cfg, ins, code);
5088 case OP_GENERIC_CLASS_INIT: {
5089 static int byte_offset = -1;
5090 static guint8 bitmask;
5094 if (byte_offset < 0)
5095 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5097 g_assert (arm_is_imm8 (byte_offset));
5098 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5099 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5100 g_assert (imm8 >= 0);
5101 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5102 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5104 ARM_B_COND (code, ARMCOND_NE, 0);
5106 /* Uninitialized case */
5107 g_assert (ins->sreg1 == ARMREG_R0);
5109 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5110 (gpointer)"mono_generic_class_init");
5111 code = emit_call_seq (cfg, code);
5113 /* Initialized case */
5114 arm_patch (jump, code);
5118 /* round the size to 8 bytes */
5119 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5120 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5121 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5122 /* memzero the area: dreg holds the size, sp is the pointer */
5123 if (ins->flags & MONO_INST_INIT) {
5124 guint8 *start_loop, *branch_to_cond;
5125 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5126 branch_to_cond = code;
5129 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5130 arm_patch (branch_to_cond, code);
5131 /* decrement by 4 and set flags */
5132 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5133 ARM_B_COND (code, ARMCOND_GE, 0);
5134 arm_patch (code - 4, start_loop);
5136 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5137 if (cfg->param_area)
5138 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5143 MonoInst *var = cfg->dyn_call_var;
5145 g_assert (var->opcode == OP_REGOFFSET);
5146 g_assert (arm_is_imm12 (var->inst_offset));
5148 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5149 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5151 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5153 /* Save args buffer */
5154 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5156 /* Set stack slots using R0 as scratch reg */
5157 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5158 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5159 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5160 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5163 /* Set argument registers */
5164 for (i = 0; i < PARAM_REGS; ++i)
5165 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5168 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5169 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5172 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5173 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5174 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5178 if (ins->sreg1 != ARMREG_R0)
5179 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5180 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5181 (gpointer)"mono_arch_throw_exception");
5182 code = emit_call_seq (cfg, code);
5186 if (ins->sreg1 != ARMREG_R0)
5187 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5188 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5189 (gpointer)"mono_arch_rethrow_exception");
5190 code = emit_call_seq (cfg, code);
5193 case OP_START_HANDLER: {
5194 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5195 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5198 /* Reserve a param area, see filter-stack.exe */
5200 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5201 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5203 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5204 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5208 if (arm_is_imm12 (spvar->inst_offset)) {
5209 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5211 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5212 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5216 case OP_ENDFILTER: {
5217 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5218 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5221 /* Free the param area */
5223 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5224 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5226 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5227 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5231 if (ins->sreg1 != ARMREG_R0)
5232 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5233 if (arm_is_imm12 (spvar->inst_offset)) {
5234 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5236 g_assert (ARMREG_IP != spvar->inst_basereg);
5237 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5238 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5240 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5243 case OP_ENDFINALLY: {
5244 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5245 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5248 /* Free the param area */
5250 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5251 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5253 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5254 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5258 if (arm_is_imm12 (spvar->inst_offset)) {
5259 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5261 g_assert (ARMREG_IP != spvar->inst_basereg);
5262 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5263 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5265 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5268 case OP_CALL_HANDLER:
5269 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5270 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5271 cfg->thunk_area += THUNK_SIZE;
5272 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5275 if (ins->dreg != ARMREG_R0)
5276 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5280 ins->inst_c0 = code - cfg->native_code;
5283 /*if (ins->inst_target_bb->native_offset) {
5285 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5287 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5288 code = mono_arm_patchable_b (code, ARMCOND_AL);
5292 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5296 * In the normal case we have:
5297 * ldr pc, [pc, ins->sreg1 << 2]
5300 * ldr lr, [pc, ins->sreg1 << 2]
5302 * After follows the data.
5303 * FIXME: add aot support.
5305 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5306 #ifdef USE_JUMP_TABLES
5308 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5309 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5310 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5314 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5315 if (offset + max_len > (cfg->code_size - 16)) {
5316 cfg->code_size += max_len;
5317 cfg->code_size *= 2;
5318 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5319 code = cfg->native_code + offset;
5321 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5323 code += 4 * GPOINTER_TO_INT (ins->klass);
5328 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5329 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5333 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5334 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5338 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5339 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5343 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5344 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5348 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5349 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5352 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5353 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5356 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5357 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5360 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5361 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5364 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5365 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5368 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5369 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5371 case OP_COND_EXC_EQ:
5372 case OP_COND_EXC_NE_UN:
5373 case OP_COND_EXC_LT:
5374 case OP_COND_EXC_LT_UN:
5375 case OP_COND_EXC_GT:
5376 case OP_COND_EXC_GT_UN:
5377 case OP_COND_EXC_GE:
5378 case OP_COND_EXC_GE_UN:
5379 case OP_COND_EXC_LE:
5380 case OP_COND_EXC_LE_UN:
5381 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5383 case OP_COND_EXC_IEQ:
5384 case OP_COND_EXC_INE_UN:
5385 case OP_COND_EXC_ILT:
5386 case OP_COND_EXC_ILT_UN:
5387 case OP_COND_EXC_IGT:
5388 case OP_COND_EXC_IGT_UN:
5389 case OP_COND_EXC_IGE:
5390 case OP_COND_EXC_IGE_UN:
5391 case OP_COND_EXC_ILE:
5392 case OP_COND_EXC_ILE_UN:
5393 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5396 case OP_COND_EXC_IC:
5397 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5399 case OP_COND_EXC_OV:
5400 case OP_COND_EXC_IOV:
5401 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5403 case OP_COND_EXC_NC:
5404 case OP_COND_EXC_INC:
5405 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5407 case OP_COND_EXC_NO:
5408 case OP_COND_EXC_INO:
5409 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5421 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5424 /* floating point opcodes */
5426 if (cfg->compile_aot) {
5427 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5429 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5431 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5434 /* FIXME: we can optimize the imm load by dealing with part of
5435 * the displacement in LDFD (aligning to 512).
5437 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5438 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5442 if (cfg->compile_aot) {
5443 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5445 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5448 ARM_CVTS (code, ins->dreg, ins->dreg);
5450 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5451 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5453 ARM_CVTS (code, ins->dreg, ins->dreg);
5456 case OP_STORER8_MEMBASE_REG:
5457 /* This is generated by the local regalloc pass which runs after the lowering pass */
5458 if (!arm_is_fpimm8 (ins->inst_offset)) {
5459 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5460 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5461 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5463 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5466 case OP_LOADR8_MEMBASE:
5467 /* This is generated by the local regalloc pass which runs after the lowering pass */
5468 if (!arm_is_fpimm8 (ins->inst_offset)) {
5469 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5470 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5471 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5473 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5476 case OP_STORER4_MEMBASE_REG:
5477 g_assert (arm_is_fpimm8 (ins->inst_offset));
5479 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5481 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5482 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5483 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5484 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5487 case OP_LOADR4_MEMBASE:
5489 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5491 g_assert (arm_is_fpimm8 (ins->inst_offset));
5492 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5493 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5494 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5495 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5498 case OP_ICONV_TO_R_UN: {
5499 g_assert_not_reached ();
5502 case OP_ICONV_TO_R4:
5504 ARM_FMSR (code, ins->dreg, ins->sreg1);
5505 ARM_FSITOS (code, ins->dreg, ins->dreg);
5507 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5508 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5509 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5510 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5511 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5514 case OP_ICONV_TO_R8:
5515 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5516 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5517 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5518 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5522 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5523 if (sig_ret->type == MONO_TYPE_R4) {
5525 g_assert (!IS_HARD_FLOAT);
5526 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5528 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5531 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5535 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5537 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5541 case OP_FCONV_TO_I1:
5542 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5544 case OP_FCONV_TO_U1:
5545 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5547 case OP_FCONV_TO_I2:
5548 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5550 case OP_FCONV_TO_U2:
5551 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5553 case OP_FCONV_TO_I4:
5555 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5557 case OP_FCONV_TO_U4:
5559 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5561 case OP_FCONV_TO_I8:
5562 case OP_FCONV_TO_U8:
5563 g_assert_not_reached ();
5564 /* Implemented as helper calls */
5566 case OP_LCONV_TO_R_UN:
5567 g_assert_not_reached ();
5568 /* Implemented as helper calls */
5570 case OP_LCONV_TO_OVF_I4_2: {
5571 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5573 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5576 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5577 high_bit_not_set = code;
5578 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5580 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5581 valid_negative = code;
5582 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5583 invalid_negative = code;
5584 ARM_B_COND (code, ARMCOND_AL, 0);
5586 arm_patch (high_bit_not_set, code);
5588 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5589 valid_positive = code;
5590 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5592 arm_patch (invalid_negative, code);
5593 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5595 arm_patch (valid_negative, code);
5596 arm_patch (valid_positive, code);
5598 if (ins->dreg != ins->sreg1)
5599 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5603 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5606 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5609 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5612 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5615 ARM_NEGD (code, ins->dreg, ins->sreg1);
5619 g_assert_not_reached ();
5623 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5629 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5634 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5637 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5638 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5642 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5645 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5646 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5650 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5653 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5654 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5655 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5659 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5662 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5663 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5667 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5670 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5671 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5672 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5676 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5679 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5680 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5684 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5687 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5688 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5692 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5695 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5696 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5699 /* ARM FPA flags table:
5700 * N Less than ARMCOND_MI
5701 * Z Equal ARMCOND_EQ
5702 * C Greater Than or Equal ARMCOND_CS
5703 * V Unordered ARMCOND_VS
5706 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5709 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5712 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5715 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5716 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5722 g_assert_not_reached ();
5726 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5728 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5729 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5730 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5734 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5735 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5740 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5741 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5743 #ifdef USE_JUMP_TABLES
5745 gpointer *jte = mono_jumptable_add_entries (2);
5746 jte [0] = GUINT_TO_POINTER (0xffffffff);
5747 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5748 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5749 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5752 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5753 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5755 *(guint32*)code = 0xffffffff;
5757 *(guint32*)code = 0x7fefffff;
5760 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5762 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5763 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5765 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5766 ARM_CPYD (code, ins->dreg, ins->sreg1);
5768 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5769 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5774 case OP_RCONV_TO_I1:
5775 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5777 case OP_RCONV_TO_U1:
5778 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5780 case OP_RCONV_TO_I2:
5781 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5783 case OP_RCONV_TO_U2:
5784 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5786 case OP_RCONV_TO_I4:
5787 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5789 case OP_RCONV_TO_U4:
5790 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5792 case OP_RCONV_TO_R4:
5794 if (ins->dreg != ins->sreg1)
5795 ARM_CPYS (code, ins->dreg, ins->sreg1);
5797 case OP_RCONV_TO_R8:
5799 ARM_CVTS (code, ins->dreg, ins->sreg1);
5802 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5805 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5808 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5811 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5814 ARM_NEGS (code, ins->dreg, ins->sreg1);
5818 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5821 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5822 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5826 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5829 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5830 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5834 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5837 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5838 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5839 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5843 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5846 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5847 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5851 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5854 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5855 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5856 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5860 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5863 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5864 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5868 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5871 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5872 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5876 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5879 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5880 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5883 case OP_GC_LIVENESS_DEF:
5884 case OP_GC_LIVENESS_USE:
5885 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5886 ins->backend.pc_offset = code - cfg->native_code;
5888 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5889 ins->backend.pc_offset = code - cfg->native_code;
5890 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5892 case OP_GC_SAFE_POINT: {
5893 const char *polling_func = NULL;
5896 g_assert (mono_threads_is_coop_enabled ());
5898 polling_func = "mono_threads_state_poll";
5899 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5900 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5902 ARM_B_COND (code, ARMCOND_EQ, 0);
5903 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5904 code = emit_call_seq (cfg, code);
5905 arm_patch (buf [0], code);
5910 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5911 g_assert_not_reached ();
5914 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5915 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5916 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5917 g_assert_not_reached ();
5923 last_offset = offset;
5926 cfg->code_len = code - cfg->native_code;
5929 #endif /* DISABLE_JIT */
5932 mono_arch_register_lowlevel_calls (void)
5934 /* The signature doesn't matter */
5935 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5936 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5937 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5939 #ifndef MONO_CROSS_COMPILE
5940 if (mono_arm_have_tls_get ()) {
5941 MonoTlsImplementation tls_imp = mono_arm_get_tls_implementation ();
5943 mono_register_jit_icall (tls_imp.get_tls_thunk, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
5944 mono_register_jit_icall (tls_imp.set_tls_thunk, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
5946 if (tls_imp.get_tls_thunk_end) {
5947 mono_tramp_info_register (
5948 mono_tramp_info_create (
5950 (guint8*)tls_imp.get_tls_thunk,
5951 (guint8*)tls_imp.get_tls_thunk_end - (guint8*)tls_imp.get_tls_thunk,
5953 mono_arch_get_cie_program ()
5957 mono_tramp_info_register (
5958 mono_tramp_info_create (
5960 (guint8*)tls_imp.set_tls_thunk,
5961 (guint8*)tls_imp.set_tls_thunk_end - (guint8*)tls_imp.set_tls_thunk,
5963 mono_arch_get_cie_program ()
5972 #define patch_lis_ori(ip,val) do {\
5973 guint16 *__lis_ori = (guint16*)(ip); \
5974 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5975 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5979 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5981 unsigned char *ip = ji->ip.i + code;
5983 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5987 case MONO_PATCH_INFO_SWITCH: {
5988 #ifdef USE_JUMP_TABLES
5989 gpointer *jt = mono_jumptable_get_entry (ip);
5991 gpointer *jt = (gpointer*)(ip + 8);
5994 /* jt is the inlined jump table, 2 instructions after ip
5995 * In the normal case we store the absolute addresses,
5996 * otherwise the displacements.
5998 for (i = 0; i < ji->data.table->table_size; i++)
5999 jt [i] = code + (int)ji->data.table->table [i];
6002 case MONO_PATCH_INFO_IP:
6003 g_assert_not_reached ();
6004 patch_lis_ori (ip, ip);
6006 case MONO_PATCH_INFO_METHOD_REL:
6007 g_assert_not_reached ();
6008 *((gpointer *)(ip)) = target;
6010 case MONO_PATCH_INFO_METHODCONST:
6011 case MONO_PATCH_INFO_CLASS:
6012 case MONO_PATCH_INFO_IMAGE:
6013 case MONO_PATCH_INFO_FIELD:
6014 case MONO_PATCH_INFO_VTABLE:
6015 case MONO_PATCH_INFO_IID:
6016 case MONO_PATCH_INFO_SFLDA:
6017 case MONO_PATCH_INFO_LDSTR:
6018 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6019 case MONO_PATCH_INFO_LDTOKEN:
6020 g_assert_not_reached ();
6021 /* from OP_AOTCONST : lis + ori */
6022 patch_lis_ori (ip, target);
6024 case MONO_PATCH_INFO_R4:
6025 case MONO_PATCH_INFO_R8:
6026 g_assert_not_reached ();
6027 *((gconstpointer *)(ip + 2)) = target;
6029 case MONO_PATCH_INFO_EXC_NAME:
6030 g_assert_not_reached ();
6031 *((gconstpointer *)(ip + 1)) = target;
6033 case MONO_PATCH_INFO_NONE:
6034 case MONO_PATCH_INFO_BB_OVF:
6035 case MONO_PATCH_INFO_EXC_OVF:
6036 /* everything is dealt with at epilog output time */
6039 arm_patch_general (cfg, domain, ip, target);
6045 mono_arm_unaligned_stack (MonoMethod *method)
6047 g_assert_not_reached ();
6053 * Stack frame layout:
6055 * ------------------- fp
6056 * MonoLMF structure or saved registers
6057 * -------------------
6059 * -------------------
6061 * -------------------
6062 * optional 8 bytes for tracing
6063 * -------------------
6064 * param area size is cfg->param_area
6065 * ------------------- sp
6068 mono_arch_emit_prolog (MonoCompile *cfg)
6070 MonoMethod *method = cfg->method;
6072 MonoMethodSignature *sig;
6074 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6079 int prev_sp_offset, reg_offset;
6081 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6084 sig = mono_method_signature (method);
6085 cfg->code_size = 256 + sig->param_count * 64;
6086 code = cfg->native_code = g_malloc (cfg->code_size);
6088 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6090 alloc_size = cfg->stack_offset;
6096 * The iphone uses R7 as the frame pointer, and it points at the saved
6101 * We can't use r7 as a frame pointer since it points into the middle of
6102 * the frame, so we keep using our own frame pointer.
6103 * FIXME: Optimize this.
6105 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6106 prev_sp_offset += 8; /* r7 and lr */
6107 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6108 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6109 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6112 if (!method->save_lmf) {
6114 /* No need to push LR again */
6115 if (cfg->used_int_regs)
6116 ARM_PUSH (code, cfg->used_int_regs);
6118 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6119 prev_sp_offset += 4;
6121 for (i = 0; i < 16; ++i) {
6122 if (cfg->used_int_regs & (1 << i))
6123 prev_sp_offset += 4;
6125 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6127 for (i = 0; i < 16; ++i) {
6128 if ((cfg->used_int_regs & (1 << i))) {
6129 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6130 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6135 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6136 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6138 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6139 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6142 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6143 ARM_PUSH (code, 0x5ff0);
6144 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6145 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6147 for (i = 0; i < 16; ++i) {
6148 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6149 /* The original r7 is saved at the start */
6150 if (!(iphone_abi && i == ARMREG_R7))
6151 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6155 g_assert (reg_offset == 4 * 10);
6156 pos += sizeof (MonoLMF) - (4 * 10);
6160 orig_alloc_size = alloc_size;
6161 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6162 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6163 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6164 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6167 /* the stack used in the pushed regs */
6168 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6169 cfg->stack_usage = alloc_size;
6171 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6172 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6174 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6175 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6177 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6179 if (cfg->frame_reg != ARMREG_SP) {
6180 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6181 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6183 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6184 prev_sp_offset += alloc_size;
6186 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6187 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6189 /* compute max_offset in order to use short forward jumps
6190 * we could skip do it on arm because the immediate displacement
6191 * for jumps is large enough, it may be useful later for constant pools
6194 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6195 MonoInst *ins = bb->code;
6196 bb->max_offset = max_offset;
6198 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6201 MONO_BB_FOR_EACH_INS (bb, ins)
6202 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6205 /* stack alignment check */
6209 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6210 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6211 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6212 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6214 ARM_B_COND (code, ARMCOND_EQ, 0);
6215 if (cfg->compile_aot)
6216 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6218 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6219 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6220 code = emit_call_seq (cfg, code);
6221 arm_patch (buf [0], code);
6225 /* store runtime generic context */
6226 if (cfg->rgctx_var) {
6227 MonoInst *ins = cfg->rgctx_var;
6229 g_assert (ins->opcode == OP_REGOFFSET);
6231 if (arm_is_imm12 (ins->inst_offset)) {
6232 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6234 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6235 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6239 /* load arguments allocated to register from the stack */
6242 cinfo = get_call_info (NULL, sig);
6244 if (cinfo->ret.storage == RegTypeStructByAddr) {
6245 ArgInfo *ainfo = &cinfo->ret;
6246 inst = cfg->vret_addr;
6247 g_assert (arm_is_imm12 (inst->inst_offset));
6248 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6251 if (sig->call_convention == MONO_CALL_VARARG) {
6252 ArgInfo *cookie = &cinfo->sig_cookie;
6254 /* Save the sig cookie address */
6255 g_assert (cookie->storage == RegTypeBase);
6257 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6258 g_assert (arm_is_imm12 (cfg->sig_cookie));
6259 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6260 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6263 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6264 ArgInfo *ainfo = cinfo->args + i;
6265 inst = cfg->args [pos];
6267 if (cfg->verbose_level > 2)
6268 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6270 if (inst->opcode == OP_REGVAR) {
6271 if (ainfo->storage == RegTypeGeneral)
6272 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6273 else if (ainfo->storage == RegTypeFP) {
6274 g_assert_not_reached ();
6275 } else if (ainfo->storage == RegTypeBase) {
6276 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6277 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6279 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6280 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6283 g_assert_not_reached ();
6285 if (cfg->verbose_level > 2)
6286 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6288 switch (ainfo->storage) {
6290 for (part = 0; part < ainfo->nregs; part ++) {
6291 if (ainfo->esize == 4)
6292 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6294 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6297 case RegTypeGeneral:
6298 case RegTypeIRegPair:
6299 case RegTypeGSharedVtInReg:
6300 switch (ainfo->size) {
6302 if (arm_is_imm12 (inst->inst_offset))
6303 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6305 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6306 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6310 if (arm_is_imm8 (inst->inst_offset)) {
6311 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6313 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6314 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6318 if (arm_is_imm12 (inst->inst_offset)) {
6319 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6321 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6322 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6324 if (arm_is_imm12 (inst->inst_offset + 4)) {
6325 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6327 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6328 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6332 if (arm_is_imm12 (inst->inst_offset)) {
6333 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6335 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6336 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6341 case RegTypeBaseGen:
6342 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6343 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6345 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6346 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6348 if (arm_is_imm12 (inst->inst_offset + 4)) {
6349 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6350 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6352 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6353 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6354 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6355 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6359 case RegTypeGSharedVtOnStack:
6360 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6361 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6363 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6364 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6367 switch (ainfo->size) {
6369 if (arm_is_imm8 (inst->inst_offset)) {
6370 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6372 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6373 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6377 if (arm_is_imm8 (inst->inst_offset)) {
6378 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6380 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6381 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6385 if (arm_is_imm12 (inst->inst_offset)) {
6386 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6388 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6389 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6391 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6392 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6394 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6395 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6397 if (arm_is_imm12 (inst->inst_offset + 4)) {
6398 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6400 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6401 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6405 if (arm_is_imm12 (inst->inst_offset)) {
6406 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6408 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6409 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6415 int imm8, rot_amount;
6417 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6418 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6419 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6421 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6423 if (ainfo->size == 8)
6424 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6426 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6429 case RegTypeStructByVal: {
6430 int doffset = inst->inst_offset;
6434 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6435 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6436 if (arm_is_imm12 (doffset)) {
6437 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6439 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6440 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6442 soffset += sizeof (gpointer);
6443 doffset += sizeof (gpointer);
6445 if (ainfo->vtsize) {
6446 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6447 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6448 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6452 case RegTypeStructByAddr:
6453 g_assert_not_reached ();
6454 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6455 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6457 g_assert_not_reached ();
6464 if (method->save_lmf)
6465 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6468 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6470 if (cfg->arch.seq_point_info_var) {
6471 MonoInst *ins = cfg->arch.seq_point_info_var;
6473 /* Initialize the variable from a GOT slot */
6474 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6475 #ifdef USE_JUMP_TABLES
6477 gpointer *jte = mono_jumptable_add_entry ();
6478 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6479 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6481 /** XXX: is it correct? */
6483 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6485 *(gpointer*)code = NULL;
6488 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6490 g_assert (ins->opcode == OP_REGOFFSET);
6492 if (arm_is_imm12 (ins->inst_offset)) {
6493 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6495 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6496 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6500 /* Initialize ss_trigger_page_var */
6501 if (!cfg->soft_breakpoints) {
6502 MonoInst *info_var = cfg->arch.seq_point_info_var;
6503 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6504 int dreg = ARMREG_LR;
6507 g_assert (info_var->opcode == OP_REGOFFSET);
6508 g_assert (arm_is_imm12 (info_var->inst_offset));
6510 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6511 /* Load the trigger page addr */
6512 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6513 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6517 if (cfg->arch.seq_point_ss_method_var) {
6518 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6519 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6520 #ifdef USE_JUMP_TABLES
6523 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6524 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6525 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6526 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6528 #ifdef USE_JUMP_TABLES
6529 jte = mono_jumptable_add_entries (3);
6530 jte [0] = &single_step_tramp;
6531 jte [1] = breakpoint_tramp;
6532 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6534 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6536 *(gpointer*)code = &single_step_tramp;
6538 *(gpointer*)code = breakpoint_tramp;
6542 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6543 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6544 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6545 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6548 cfg->code_len = code - cfg->native_code;
6549 g_assert (cfg->code_len < cfg->code_size);
6556 mono_arch_emit_epilog (MonoCompile *cfg)
6558 MonoMethod *method = cfg->method;
6559 int pos, i, rot_amount;
6560 int max_epilog_size = 16 + 20*4;
6564 if (cfg->method->save_lmf)
6565 max_epilog_size += 128;
6567 if (mono_jit_trace_calls != NULL)
6568 max_epilog_size += 50;
6570 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6571 max_epilog_size += 50;
6573 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6574 cfg->code_size *= 2;
6575 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6576 cfg->stat_code_reallocs++;
6580 * Keep in sync with OP_JMP
6582 code = cfg->native_code + cfg->code_len;
6584 /* Save the uwind state which is needed by the out-of-line code */
6585 mono_emit_unwind_op_remember_state (cfg, code);
6587 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6588 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6592 /* Load returned vtypes into registers if needed */
6593 cinfo = cfg->arch.cinfo;
6594 switch (cinfo->ret.storage) {
6595 case RegTypeStructByVal: {
6596 MonoInst *ins = cfg->ret;
6598 if (arm_is_imm12 (ins->inst_offset)) {
6599 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6601 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6602 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6607 MonoInst *ins = cfg->ret;
6609 for (i = 0; i < cinfo->ret.nregs; ++i) {
6610 if (cinfo->ret.esize == 4)
6611 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6613 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6621 if (method->save_lmf) {
6622 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6623 /* all but r0-r3, sp and pc */
6624 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6627 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6629 /* This points to r4 inside MonoLMF->iregs */
6630 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6632 regmask = 0x9ff0; /* restore lr to pc */
6633 /* Skip caller saved registers not used by the method */
6634 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6635 regmask &= ~(1 << reg);
6640 /* Restored later */
6641 regmask &= ~(1 << ARMREG_PC);
6642 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6643 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6644 for (i = 0; i < 16; i++) {
6645 if (regmask & (1 << i))
6648 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6650 ARM_POP (code, regmask);
6652 for (i = 0; i < 16; i++) {
6653 if (regmask & (1 << i))
6654 mono_emit_unwind_op_same_value (cfg, code, i);
6656 /* Restore saved r7, restore LR to PC */
6657 /* Skip lr from the lmf */
6658 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6659 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6660 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6661 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6664 int i, nused_int_regs = 0;
6666 for (i = 0; i < 16; i++) {
6667 if (cfg->used_int_regs & (1 << i))
6671 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6672 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6674 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6675 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6678 if (cfg->frame_reg != ARMREG_SP) {
6679 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6683 /* Restore saved gregs */
6684 if (cfg->used_int_regs) {
6685 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6686 ARM_POP (code, cfg->used_int_regs);
6687 for (i = 0; i < 16; i++) {
6688 if (cfg->used_int_regs & (1 << i))
6689 mono_emit_unwind_op_same_value (cfg, code, i);
6692 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6693 /* Restore saved r7, restore LR to PC */
6694 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6696 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6697 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6701 /* Restore the unwind state to be the same as before the epilog */
6702 mono_emit_unwind_op_restore_state (cfg, code);
6704 cfg->code_len = code - cfg->native_code;
6706 g_assert (cfg->code_len < cfg->code_size);
6711 mono_arch_emit_exceptions (MonoCompile *cfg)
6713 MonoJumpInfo *patch_info;
6716 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6717 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6718 int max_epilog_size = 50;
6720 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6721 exc_throw_pos [i] = NULL;
6722 exc_throw_found [i] = 0;
6725 /* count the number of exception infos */
6728 * make sure we have enough space for exceptions
6730 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6731 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6732 i = mini_exception_id_by_name (patch_info->data.target);
6733 if (!exc_throw_found [i]) {
6734 max_epilog_size += 32;
6735 exc_throw_found [i] = TRUE;
6740 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6741 cfg->code_size *= 2;
6742 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6743 cfg->stat_code_reallocs++;
6746 code = cfg->native_code + cfg->code_len;
6748 /* add code to raise exceptions */
6749 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6750 switch (patch_info->type) {
6751 case MONO_PATCH_INFO_EXC: {
6752 MonoClass *exc_class;
6753 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6755 i = mini_exception_id_by_name (patch_info->data.target);
6756 if (exc_throw_pos [i]) {
6757 arm_patch (ip, exc_throw_pos [i]);
6758 patch_info->type = MONO_PATCH_INFO_NONE;
6761 exc_throw_pos [i] = code;
6763 arm_patch (ip, code);
6765 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6767 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6768 #ifdef USE_JUMP_TABLES
6770 gpointer *jte = mono_jumptable_add_entries (2);
6771 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6772 patch_info->data.name = "mono_arch_throw_corlib_exception";
6773 patch_info->ip.i = code - cfg->native_code;
6774 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6775 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6776 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6777 ARM_BLX_REG (code, ARMREG_IP);
6778 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6781 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6782 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6783 patch_info->data.name = "mono_arch_throw_corlib_exception";
6784 patch_info->ip.i = code - cfg->native_code;
6786 cfg->thunk_area += THUNK_SIZE;
6787 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6798 cfg->code_len = code - cfg->native_code;
6800 g_assert (cfg->code_len < cfg->code_size);
6804 #endif /* #ifndef DISABLE_JIT */
6807 mono_arch_finish_init (void)
6812 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6817 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6824 mono_arch_print_tree (MonoInst *tree, int arity)
6834 mono_arch_get_patch_offset (guint8 *code)
6841 mono_arch_flush_register_windows (void)
6846 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6848 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6852 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6854 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6858 mono_arch_get_cie_program (void)
6862 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6867 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6868 #define BASE_SIZE (6 * 4)
6869 #define BSEARCH_ENTRY_SIZE (4 * 4)
6870 #define CMP_SIZE (3 * 4)
6871 #define BRANCH_SIZE (1 * 4)
6872 #define CALL_SIZE (2 * 4)
6873 #define WMC_SIZE (8 * 4)
6874 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6876 #ifdef USE_JUMP_TABLES
6878 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6880 g_assert (base [index] == NULL);
6881 base [index] = value;
6884 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6886 if (arm_is_imm12 (jti * 4)) {
6887 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6889 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6890 if ((jti * 4) >> 16)
6891 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6892 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6898 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6900 guint32 delta = DISTANCE (target, code);
6902 g_assert (delta >= 0 && delta <= 0xFFF);
6903 *target = *target | delta;
6909 #ifdef ENABLE_WRONG_METHOD_CHECK
6911 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6913 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6919 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6920 gpointer fail_tramp)
6923 arminstr_t *code, *start;
6924 #ifdef USE_JUMP_TABLES
6927 gboolean large_offsets = FALSE;
6928 guint32 **constant_pool_starts;
6929 arminstr_t *vtable_target = NULL;
6930 int extra_space = 0;
6932 #ifdef ENABLE_WRONG_METHOD_CHECK
6938 #ifdef USE_JUMP_TABLES
6939 for (i = 0; i < count; ++i) {
6940 MonoIMTCheckItem *item = imt_entries [i];
6941 item->chunk_size += 4 * 16;
6942 if (!item->is_equals)
6943 imt_entries [item->check_target_idx]->compare_done = TRUE;
6944 size += item->chunk_size;
6947 constant_pool_starts = g_new0 (guint32*, count);
6949 for (i = 0; i < count; ++i) {
6950 MonoIMTCheckItem *item = imt_entries [i];
6951 if (item->is_equals) {
6952 gboolean fail_case = !item->check_target_idx && fail_tramp;
6954 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6955 item->chunk_size += 32;
6956 large_offsets = TRUE;
6959 if (item->check_target_idx || fail_case) {
6960 if (!item->compare_done || fail_case)
6961 item->chunk_size += CMP_SIZE;
6962 item->chunk_size += BRANCH_SIZE;
6964 #ifdef ENABLE_WRONG_METHOD_CHECK
6965 item->chunk_size += WMC_SIZE;
6969 item->chunk_size += 16;
6970 large_offsets = TRUE;
6972 item->chunk_size += CALL_SIZE;
6974 item->chunk_size += BSEARCH_ENTRY_SIZE;
6975 imt_entries [item->check_target_idx]->compare_done = TRUE;
6977 size += item->chunk_size;
6981 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6985 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6987 code = mono_domain_code_reserve (domain, size);
6990 unwind_ops = mono_arch_get_cie_program ();
6993 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6994 for (i = 0; i < count; ++i) {
6995 MonoIMTCheckItem *item = imt_entries [i];
6996 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
7000 #ifdef USE_JUMP_TABLES
7001 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7002 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 3 * sizeof (mgreg_t));
7003 #define VTABLE_JTI 0
7004 #define IMT_METHOD_OFFSET 0
7005 #define TARGET_CODE_OFFSET 1
7006 #define JUMP_CODE_OFFSET 2
7007 #define RECORDS_PER_ENTRY 3
7008 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
7009 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
7010 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
7012 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
7013 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
7014 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
7015 set_jumptable_element (jte, VTABLE_JTI, vtable);
7017 if (large_offsets) {
7018 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7019 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
7021 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7022 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7024 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7025 vtable_target = code;
7026 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7028 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7030 for (i = 0; i < count; ++i) {
7031 MonoIMTCheckItem *item = imt_entries [i];
7032 #ifdef USE_JUMP_TABLES
7033 guint32 imt_method_jti = 0, target_code_jti = 0;
7035 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7037 gint32 vtable_offset;
7039 item->code_target = (guint8*)code;
7041 if (item->is_equals) {
7042 gboolean fail_case = !item->check_target_idx && fail_tramp;
7044 if (item->check_target_idx || fail_case) {
7045 if (!item->compare_done || fail_case) {
7046 #ifdef USE_JUMP_TABLES
7047 imt_method_jti = IMT_METHOD_JTI (i);
7048 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7051 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7053 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7055 #ifdef USE_JUMP_TABLES
7056 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7057 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7058 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7060 item->jmp_code = (guint8*)code;
7061 ARM_B_COND (code, ARMCOND_NE, 0);
7064 /*Enable the commented code to assert on wrong method*/
7065 #ifdef ENABLE_WRONG_METHOD_CHECK
7066 #ifdef USE_JUMP_TABLES
7067 imt_method_jti = IMT_METHOD_JTI (i);
7068 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7071 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7073 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7075 ARM_B_COND (code, ARMCOND_EQ, 0);
7077 /* Define this if your system is so bad that gdb is failing. */
7078 #ifdef BROKEN_DEV_ENV
7079 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7081 arm_patch (code - 1, mini_dump_bad_imt);
7085 arm_patch (cond, code);
7089 if (item->has_target_code) {
7090 /* Load target address */
7091 #ifdef USE_JUMP_TABLES
7092 target_code_jti = TARGET_CODE_JTI (i);
7093 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7094 /* Restore registers */
7095 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7096 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7098 ARM_BX (code, ARMREG_R1);
7099 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7101 target_code_ins = code;
7102 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7103 /* Save it to the fourth slot */
7104 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7105 /* Restore registers and branch */
7106 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7108 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7111 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7112 if (!arm_is_imm12 (vtable_offset)) {
7114 * We need to branch to a computed address but we don't have
7115 * a free register to store it, since IP must contain the
7116 * vtable address. So we push the two values to the stack, and
7117 * load them both using LDM.
7119 /* Compute target address */
7120 #ifdef USE_JUMP_TABLES
7121 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7122 if (vtable_offset >> 16)
7123 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7124 /* IP had vtable base. */
7125 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7126 /* Restore registers and branch */
7127 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7128 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7129 ARM_BX (code, ARMREG_IP);
7131 vtable_offset_ins = code;
7132 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7133 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7134 /* Save it to the fourth slot */
7135 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7136 /* Restore registers and branch */
7137 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7139 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7142 #ifdef USE_JUMP_TABLES
7143 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7144 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7145 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7146 ARM_BX (code, ARMREG_IP);
7148 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7149 if (large_offsets) {
7150 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7151 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7153 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7154 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7160 #ifdef USE_JUMP_TABLES
7161 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7162 target_code_jti = TARGET_CODE_JTI (i);
7163 /* Load target address */
7164 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7165 /* Restore registers */
7166 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7167 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7169 ARM_BX (code, ARMREG_R1);
7170 set_jumptable_element (jte, target_code_jti, fail_tramp);
7172 arm_patch (item->jmp_code, (guchar*)code);
7174 target_code_ins = code;
7175 /* Load target address */
7176 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7177 /* Save it to the fourth slot */
7178 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7179 /* Restore registers and branch */
7180 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7182 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7184 item->jmp_code = NULL;
7187 #ifdef USE_JUMP_TABLES
7189 set_jumptable_element (jte, imt_method_jti, item->key);
7192 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7194 /*must emit after unconditional branch*/
7195 if (vtable_target) {
7196 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7197 item->chunk_size += 4;
7198 vtable_target = NULL;
7201 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7202 constant_pool_starts [i] = code;
7204 code += extra_space;
7209 #ifdef USE_JUMP_TABLES
7210 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7211 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7212 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7213 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7214 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7216 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7217 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7219 item->jmp_code = (guint8*)code;
7220 ARM_B_COND (code, ARMCOND_HS, 0);
7226 for (i = 0; i < count; ++i) {
7227 MonoIMTCheckItem *item = imt_entries [i];
7228 if (item->jmp_code) {
7229 if (item->check_target_idx)
7230 #ifdef USE_JUMP_TABLES
7231 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7233 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7236 if (i > 0 && item->is_equals) {
7238 #ifdef USE_JUMP_TABLES
7239 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7240 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7242 arminstr_t *space_start = constant_pool_starts [i];
7243 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7244 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7252 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7253 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7258 #ifndef USE_JUMP_TABLES
7259 g_free (constant_pool_starts);
7262 mono_arch_flush_icache ((guint8*)start, size);
7263 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7264 mono_stats.imt_thunks_size += code - start;
7266 g_assert (DISTANCE (start, code) <= size);
7268 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7274 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7276 return ctx->regs [reg];
7280 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7282 ctx->regs [reg] = val;
7286 * mono_arch_get_trampolines:
7288 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7292 mono_arch_get_trampolines (gboolean aot)
7294 return mono_arm_get_exception_trampolines (aot);
7298 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7305 bp = MONO_CONTEXT_GET_BP (ctx);
7306 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7308 old_value = *lr_loc;
7309 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7312 *lr_loc = new_value;
7317 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7319 * mono_arch_set_breakpoint:
7321 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7322 * The location should contain code emitted by OP_SEQ_POINT.
7325 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7328 guint32 native_offset = ip - (guint8*)ji->code_start;
7329 MonoDebugOptions *opt = mini_get_debug_options ();
7331 if (opt->soft_breakpoints) {
7332 g_assert (!ji->from_aot);
7334 ARM_BLX_REG (code, ARMREG_LR);
7335 mono_arch_flush_icache (code - 4, 4);
7336 } else if (ji->from_aot) {
7337 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7339 g_assert (native_offset % 4 == 0);
7340 g_assert (info->bp_addrs [native_offset / 4] == 0);
7341 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7343 int dreg = ARMREG_LR;
7345 /* Read from another trigger page */
7346 #ifdef USE_JUMP_TABLES
7347 gpointer *jte = mono_jumptable_add_entry ();
7348 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7349 jte [0] = bp_trigger_page;
7351 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7353 *(int*)code = (int)bp_trigger_page;
7356 ARM_LDR_IMM (code, dreg, dreg, 0);
7358 mono_arch_flush_icache (code - 16, 16);
7361 /* This is currently implemented by emitting an SWI instruction, which
7362 * qemu/linux seems to convert to a SIGILL.
7364 *(int*)code = (0xef << 24) | 8;
7366 mono_arch_flush_icache (code - 4, 4);
7372 * mono_arch_clear_breakpoint:
7374 * Clear the breakpoint at IP.
7377 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7379 MonoDebugOptions *opt = mini_get_debug_options ();
7383 if (opt->soft_breakpoints) {
7384 g_assert (!ji->from_aot);
7387 mono_arch_flush_icache (code - 4, 4);
7388 } else if (ji->from_aot) {
7389 guint32 native_offset = ip - (guint8*)ji->code_start;
7390 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7392 g_assert (native_offset % 4 == 0);
7393 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7394 info->bp_addrs [native_offset / 4] = 0;
7396 for (i = 0; i < 4; ++i)
7399 mono_arch_flush_icache (ip, code - ip);
7404 * mono_arch_start_single_stepping:
7406 * Start single stepping.
7409 mono_arch_start_single_stepping (void)
7411 if (ss_trigger_page)
7412 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7414 single_step_tramp = mini_get_single_step_trampoline ();
7418 * mono_arch_stop_single_stepping:
7420 * Stop single stepping.
7423 mono_arch_stop_single_stepping (void)
7425 if (ss_trigger_page)
7426 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7428 single_step_tramp = NULL;
7432 #define DBG_SIGNAL SIGBUS
7434 #define DBG_SIGNAL SIGSEGV
7438 * mono_arch_is_single_step_event:
7440 * Return whenever the machine state in SIGCTX corresponds to a single
7444 mono_arch_is_single_step_event (void *info, void *sigctx)
7446 siginfo_t *sinfo = info;
7448 if (!ss_trigger_page)
7451 /* Sometimes the address is off by 4 */
7452 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7459 * mono_arch_is_breakpoint_event:
7461 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7464 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7466 siginfo_t *sinfo = info;
7468 if (!ss_trigger_page)
7471 if (sinfo->si_signo == DBG_SIGNAL) {
7472 /* Sometimes the address is off by 4 */
7473 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7483 * mono_arch_skip_breakpoint:
7485 * See mini-amd64.c for docs.
7488 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7490 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7494 * mono_arch_skip_single_step:
7496 * See mini-amd64.c for docs.
7499 mono_arch_skip_single_step (MonoContext *ctx)
7501 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7504 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7507 * mono_arch_get_seq_point_info:
7509 * See mini-amd64.c for docs.
7512 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7517 // FIXME: Add a free function
7519 mono_domain_lock (domain);
7520 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7522 mono_domain_unlock (domain);
7525 ji = mono_jit_info_table_find (domain, (char*)code);
7528 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7530 info->ss_trigger_page = ss_trigger_page;
7531 info->bp_trigger_page = bp_trigger_page;
7533 mono_domain_lock (domain);
7534 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7536 mono_domain_unlock (domain);
7543 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7545 ext->lmf.previous_lmf = prev_lmf;
7546 /* Mark that this is a MonoLMFExt */
7547 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7548 ext->lmf.sp = (gssize)ext;
7552 * mono_arch_set_target:
7554 * Set the target architecture the JIT backend should generate code for, in the form
7555 * of a GNU target triplet. Only used in AOT mode.
7558 mono_arch_set_target (char *mtriple)
7560 /* The GNU target triple format is not very well documented */
7561 if (strstr (mtriple, "armv7")) {
7562 v5_supported = TRUE;
7563 v6_supported = TRUE;
7564 v7_supported = TRUE;
7566 if (strstr (mtriple, "armv6")) {
7567 v5_supported = TRUE;
7568 v6_supported = TRUE;
7570 if (strstr (mtriple, "armv7s")) {
7571 v7s_supported = TRUE;
7573 if (strstr (mtriple, "armv7k")) {
7574 v7k_supported = TRUE;
7576 if (strstr (mtriple, "thumbv7s")) {
7577 v5_supported = TRUE;
7578 v6_supported = TRUE;
7579 v7_supported = TRUE;
7580 v7s_supported = TRUE;
7581 thumb_supported = TRUE;
7582 thumb2_supported = TRUE;
7584 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7585 v5_supported = TRUE;
7586 v6_supported = TRUE;
7587 thumb_supported = TRUE;
7590 if (strstr (mtriple, "gnueabi"))
7591 eabi_supported = TRUE;
7595 mono_arch_opcode_supported (int opcode)
7598 case OP_ATOMIC_ADD_I4:
7599 case OP_ATOMIC_EXCHANGE_I4:
7600 case OP_ATOMIC_CAS_I4:
7601 case OP_ATOMIC_LOAD_I1:
7602 case OP_ATOMIC_LOAD_I2:
7603 case OP_ATOMIC_LOAD_I4:
7604 case OP_ATOMIC_LOAD_U1:
7605 case OP_ATOMIC_LOAD_U2:
7606 case OP_ATOMIC_LOAD_U4:
7607 case OP_ATOMIC_STORE_I1:
7608 case OP_ATOMIC_STORE_I2:
7609 case OP_ATOMIC_STORE_I4:
7610 case OP_ATOMIC_STORE_U1:
7611 case OP_ATOMIC_STORE_U2:
7612 case OP_ATOMIC_STORE_U4:
7613 return v7_supported;
7614 case OP_ATOMIC_LOAD_R4:
7615 case OP_ATOMIC_LOAD_R8:
7616 case OP_ATOMIC_STORE_R4:
7617 case OP_ATOMIC_STORE_R8:
7618 return v7_supported && IS_VFP;
7625 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7627 return get_call_info (mp, sig);