2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
13 #include <mono/metadata/appdomain.h>
14 #include <mono/metadata/debug-helpers.h>
20 #include "mono/arch/arm/arm-fpa-codegen.h"
24 * floating point support: on ARM it is a mess, there are at least 3
25 * different setups, each of which binary incompat with the other.
26 * 1) FPA: old and ugly, but unfortunately what current distros use
27 * the double binary format has the two words swapped. 8 double registers.
28 * Implemented usually by kernel emulation.
29 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
30 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
31 * 3) VFP: the new and actually sensible and useful FP support. Implemented
32 * in HW or kernel-emulated, requires new tools. I think this ios what symbian uses.
34 * The plan is to write the FPA support first. softfloat can be tested in a chroot.
36 int mono_exc_esp_offset = 0;
38 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
39 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
40 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
43 mono_arch_regname (int reg) {
44 static const char * rnames[] = {
45 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
46 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
47 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
50 if (reg >= 0 && reg < 16)
56 mono_arch_fregname (int reg) {
57 static const char * rnames[] = {
58 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
59 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
60 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
61 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
62 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
63 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
66 if (reg >= 0 && reg < 32)
72 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
75 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
76 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
79 g_assert (dreg != sreg);
80 code = mono_arm_emit_load_imm (code, dreg, imm);
81 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
86 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
88 /* we can use r0-r3, since this is called only for incoming args on the stack */
89 if (size > sizeof (gpointer) * 4) {
91 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
92 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
93 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
94 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
95 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
96 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
97 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
98 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
99 ARM_B_COND (code, ARMCOND_NE, 0);
100 arm_patch (code - 4, start_loop);
103 g_assert (arm_is_imm12 (doffset));
104 g_assert (arm_is_imm12 (doffset + size));
105 g_assert (arm_is_imm12 (soffset));
106 g_assert (arm_is_imm12 (soffset + size));
108 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
109 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
114 g_assert (size == 0);
119 * mono_arch_get_argument_info:
120 * @csig: a method signature
121 * @param_count: the number of parameters to consider
122 * @arg_info: an array to store the result infos
124 * Gathers information on parameters such as size, alignment and
125 * padding. arg_info should be large enought to hold param_count + 1 entries.
127 * Returns the size of the activation frame.
130 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
132 int k, frame_size = 0;
133 int size, align, pad;
136 if (MONO_TYPE_ISSTRUCT (csig->ret)) {
137 frame_size += sizeof (gpointer);
141 arg_info [0].offset = offset;
144 frame_size += sizeof (gpointer);
148 arg_info [0].size = frame_size;
150 for (k = 0; k < param_count; k++) {
153 size = mono_type_native_stack_size (csig->params [k], &align);
155 size = mono_type_stack_size (csig->params [k], &align);
157 /* ignore alignment for now */
160 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
161 arg_info [k].pad = pad;
163 arg_info [k + 1].pad = 0;
164 arg_info [k + 1].size = size;
166 arg_info [k + 1].offset = offset;
170 align = MONO_ARCH_FRAME_ALIGNMENT;
171 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
172 arg_info [k].pad = pad;
178 * Initialize the cpu to execute managed code.
181 mono_arch_cpu_init (void)
186 * This function returns the optimizations supported on this cpu.
189 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
193 /* no arm-specific optimizations yet */
199 is_regsize_var (MonoType *t) {
202 t = mono_type_get_underlying_type (t);
209 case MONO_TYPE_FNPTR:
211 case MONO_TYPE_OBJECT:
212 case MONO_TYPE_STRING:
213 case MONO_TYPE_CLASS:
214 case MONO_TYPE_SZARRAY:
215 case MONO_TYPE_ARRAY:
217 case MONO_TYPE_VALUETYPE:
224 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
229 for (i = 0; i < cfg->num_varinfo; i++) {
230 MonoInst *ins = cfg->varinfo [i];
231 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
234 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
237 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
240 /* we can only allocate 32 bit values */
241 if (is_regsize_var (ins->inst_vtype)) {
242 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
243 g_assert (i == vmv->idx);
244 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
251 #define USE_EXTRA_TEMPS 0
254 mono_arch_get_global_int_regs (MonoCompile *cfg)
257 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
258 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
259 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
260 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
261 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
262 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
263 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
269 * mono_arch_regalloc_cost:
271 * Return the cost, in number of memory references, of the action of
272 * allocating the variable VMV into a register during global register
276 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
283 mono_arch_flush_icache (guint8 *code, gint size)
285 __asm __volatile ("mov r0, %0\n"
288 "swi 0x9f0002 @ sys_cacheflush"
290 : "r" (code), "r" (code + size), "r" (0)
291 : "r0", "r1", "r3" );
295 #define NOT_IMPLEMENTED(x) \
296 g_error ("FIXME: %s is not yet implemented. (trampoline)", x);
308 guint16 vtsize; /* in param area */
310 guint8 regtype : 4; /* 0 general, 1 basereg, 2 floating point register, see RegType* */
311 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
326 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
329 if (*gr > ARMREG_R3) {
330 ainfo->offset = *stack_size;
331 ainfo->reg = ARMREG_SP; /* in the caller */
332 ainfo->regtype = RegTypeBase;
338 if (*gr > ARMREG_R2) {
341 ainfo->offset = *stack_size;
342 ainfo->reg = ARMREG_SP; /* in the caller */
343 ainfo->regtype = RegTypeBase;
356 calculate_sizes (MonoMethodSignature *sig, gboolean is_pinvoke)
359 int n = sig->hasthis + sig->param_count;
361 guint32 stack_size = 0;
362 CallInfo *cinfo = g_malloc0 (sizeof (CallInfo) + sizeof (ArgInfo) * n);
366 /* FIXME: handle returning a struct */
367 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
368 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
369 cinfo->struct_ret = ARMREG_R0;
374 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
377 DEBUG(printf("params: %d\n", sig->param_count));
378 for (i = 0; i < sig->param_count; ++i) {
379 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
380 /* Prevent implicit arguments and sig_cookie from
381 being passed in registers */
383 /* Emit the signature cookie just before the implicit arguments */
384 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
386 DEBUG(printf("param %d: ", i));
387 if (sig->params [i]->byref) {
388 DEBUG(printf("byref\n"));
389 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
393 simpletype = mono_type_get_underlying_type (sig->params [i])->type;
394 switch (simpletype) {
395 case MONO_TYPE_BOOLEAN:
398 cinfo->args [n].size = 1;
399 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
405 cinfo->args [n].size = 2;
406 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
411 cinfo->args [n].size = 4;
412 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
418 case MONO_TYPE_FNPTR:
419 case MONO_TYPE_CLASS:
420 case MONO_TYPE_OBJECT:
421 case MONO_TYPE_STRING:
422 case MONO_TYPE_SZARRAY:
423 case MONO_TYPE_ARRAY:
425 cinfo->args [n].size = sizeof (gpointer);
426 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
429 case MONO_TYPE_TYPEDBYREF:
430 case MONO_TYPE_VALUETYPE: {
435 if (simpletype == MONO_TYPE_TYPEDBYREF) {
436 size = sizeof (MonoTypedRef);
438 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
440 size = mono_class_native_size (klass, NULL);
442 size = mono_class_value_size (klass, NULL);
444 DEBUG(printf ("load %d bytes struct\n",
445 mono_class_native_size (sig->params [i]->data.klass, NULL)));
448 align_size += (sizeof (gpointer) - 1);
449 align_size &= ~(sizeof (gpointer) - 1);
450 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
451 cinfo->args [n].regtype = RegTypeStructByVal;
452 /* FIXME: align gr and stack_size if needed */
453 if (gr > ARMREG_R3) {
454 cinfo->args [n].size = 0;
455 cinfo->args [n].vtsize = nwords;
457 int rest = ARMREG_R3 - gr + 1;
458 int n_in_regs = rest >= nwords? nwords: rest;
459 cinfo->args [n].size = n_in_regs;
460 cinfo->args [n].vtsize = nwords - n_in_regs;
461 cinfo->args [n].reg = gr;
464 cinfo->args [n].offset = stack_size;
465 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
466 stack_size += nwords * sizeof (gpointer);
473 cinfo->args [n].size = 8;
474 add_general (&gr, &stack_size, cinfo->args + n, FALSE);
478 g_error ("Can't trampoline 0x%x", sig->params [i]->type);
483 simpletype = mono_type_get_underlying_type (sig->ret)->type;
484 switch (simpletype) {
485 case MONO_TYPE_BOOLEAN:
496 case MONO_TYPE_FNPTR:
497 case MONO_TYPE_CLASS:
498 case MONO_TYPE_OBJECT:
499 case MONO_TYPE_SZARRAY:
500 case MONO_TYPE_ARRAY:
501 case MONO_TYPE_STRING:
502 cinfo->ret.reg = ARMREG_R0;
506 cinfo->ret.reg = ARMREG_R0;
510 cinfo->ret.reg = ARMREG_R0;
511 /* FIXME: cinfo->ret.reg = ???;
512 cinfo->ret.regtype = RegTypeFP;*/
514 case MONO_TYPE_VALUETYPE:
516 case MONO_TYPE_TYPEDBYREF:
520 g_error ("Can't handle as return value 0x%x", sig->ret->type);
524 /* align stack size to 8 */
525 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
526 stack_size = (stack_size + 7) & ~7;
528 cinfo->stack_usage = stack_size;
534 * Set var information according to the calling convention. arm version.
535 * The locals var stuff should most likely be split in another method.
538 mono_arch_allocate_vars (MonoCompile *m)
540 MonoMethodSignature *sig;
541 MonoMethodHeader *header;
543 int i, offset, size, align, curinst;
544 int frame_reg = ARMREG_FP;
546 /* FIXME: this will change when we use FP as gcc does */
547 m->flags |= MONO_CFG_HAS_SPILLUP;
549 /* allow room for the vararg method args: void* and long/double */
550 if (mono_jit_trace_calls != NULL && mono_trace_eval (m->method))
551 m->param_area = MAX (m->param_area, sizeof (gpointer)*8);
553 header = mono_method_get_header (m->method);
556 * We use the frame register also for any method that has
557 * exception clauses. This way, when the handlers are called,
558 * the code will reference local variables using the frame reg instead of
559 * the stack pointer: if we had to restore the stack pointer, we'd
560 * corrupt the method frames that are already on the stack (since
561 * filters get called before stack unwinding happens) when the filter
562 * code would call any method (this also applies to finally etc.).
564 if ((m->flags & MONO_CFG_HAS_ALLOCA) || header->num_clauses)
565 frame_reg = ARMREG_FP;
566 m->frame_reg = frame_reg;
567 if (frame_reg != ARMREG_SP) {
568 m->used_int_regs |= 1 << frame_reg;
571 sig = mono_method_signature (m->method);
575 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
576 m->ret->opcode = OP_REGVAR;
577 m->ret->inst_c0 = ARMREG_R0;
579 /* FIXME: handle long and FP values */
580 switch (mono_type_get_underlying_type (sig->ret)->type) {
584 m->ret->opcode = OP_REGVAR;
585 m->ret->inst_c0 = ARMREG_R0;
589 /* local vars are at a positive offset from the stack pointer */
591 * also note that if the function uses alloca, we use FP
592 * to point at the local variables.
594 offset = 0; /* linkage area */
595 /* align the offset to 16 bytes: not sure this is needed here */
597 //offset &= ~(8 - 1);
599 /* add parameter area size for called functions */
600 offset += m->param_area;
603 if (m->flags & MONO_CFG_HAS_FPOUT)
606 /* allow room to save the return value */
607 if (mono_jit_trace_calls != NULL && mono_trace_eval (m->method))
610 /* the MonoLMF structure is stored just below the stack pointer */
612 if (sig->call_convention == MONO_CALL_VARARG) {
616 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
618 offset += sizeof(gpointer) - 1;
619 offset &= ~(sizeof(gpointer) - 1);
620 inst->inst_offset = offset;
621 inst->opcode = OP_REGOFFSET;
622 inst->inst_basereg = frame_reg;
623 offset += sizeof(gpointer);
624 if (sig->call_convention == MONO_CALL_VARARG)
625 m->sig_cookie += sizeof (gpointer);
628 curinst = m->locals_start;
629 for (i = curinst; i < m->num_varinfo; ++i) {
630 inst = m->varinfo [i];
631 if ((inst->flags & MONO_INST_IS_DEAD) || inst->opcode == OP_REGVAR)
634 /* inst->unused indicates native sized value types, this is used by the
635 * pinvoke wrappers when they call functions returning structure */
636 if (inst->unused && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
637 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), &align);
639 size = mono_type_size (inst->inst_vtype, &align);
641 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
642 * since it loads/stores misaligned words, which don't do the right thing.
644 if (align < 4 && size >= 4)
647 offset &= ~(align - 1);
648 inst->inst_offset = offset;
649 inst->opcode = OP_REGOFFSET;
650 inst->inst_basereg = frame_reg;
652 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
657 inst = m->varinfo [curinst];
658 if (inst->opcode != OP_REGVAR) {
659 inst->opcode = OP_REGOFFSET;
660 inst->inst_basereg = frame_reg;
661 offset += sizeof (gpointer) - 1;
662 offset &= ~(sizeof (gpointer) - 1);
663 inst->inst_offset = offset;
664 offset += sizeof (gpointer);
665 if (sig->call_convention == MONO_CALL_VARARG)
666 m->sig_cookie += sizeof (gpointer);
671 for (i = 0; i < sig->param_count; ++i) {
672 inst = m->varinfo [curinst];
673 if (inst->opcode != OP_REGVAR) {
674 inst->opcode = OP_REGOFFSET;
675 inst->inst_basereg = frame_reg;
676 size = mono_type_size (sig->params [i], &align);
677 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
678 * since it loads/stores misaligned words, which don't do the right thing.
680 if (align < 4 && size >= 4)
683 offset &= ~(align - 1);
684 inst->inst_offset = offset;
686 if ((sig->call_convention == MONO_CALL_VARARG) && (i < sig->sentinelpos))
687 m->sig_cookie += size;
692 /* align the offset to 8 bytes */
697 m->stack_offset = offset;
701 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
702 * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
706 * take the arguments and generate the arch-specific
707 * instructions to properly call the function in call.
708 * This includes pushing, moving arguments to the right register
710 * Issue: who does the spilling if needed, and when?
713 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
715 MonoMethodSignature *sig;
720 sig = call->signature;
721 n = sig->param_count + sig->hasthis;
723 cinfo = calculate_sizes (sig, sig->pinvoke);
724 if (cinfo->struct_ret)
725 call->used_iregs |= 1 << cinfo->struct_ret;
727 for (i = 0; i < n; ++i) {
728 ainfo = cinfo->args + i;
729 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
731 cfg->disable_aot = TRUE;
733 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
734 sig_arg->inst_p0 = call->signature;
736 MONO_INST_NEW (cfg, arg, OP_OUTARG);
737 arg->inst_imm = cinfo->sig_cookie.offset;
738 arg->inst_left = sig_arg;
740 /* prepend, so they get reversed */
741 arg->next = call->out_args;
742 call->out_args = arg;
744 if (is_virtual && i == 0) {
745 /* the argument will be attached to the call instrucion */
747 call->used_iregs |= 1 << ainfo->reg;
749 MONO_INST_NEW (cfg, arg, OP_OUTARG);
751 arg->cil_code = in->cil_code;
753 arg->inst_right = (MonoInst*)call;
754 arg->type = in->type;
755 /* prepend, we'll need to reverse them later */
756 arg->next = call->out_args;
757 call->out_args = arg;
758 if (ainfo->regtype == RegTypeGeneral) {
759 arg->unused = ainfo->reg;
760 call->used_iregs |= 1 << ainfo->reg;
761 if (arg->type == STACK_I8)
762 call->used_iregs |= 1 << (ainfo->reg + 1);
763 if (arg->type == STACK_R8) {
764 if (ainfo->size == 4) {
765 arg->opcode = OP_OUTARG_R4;
767 call->used_iregs |= 1 << (ainfo->reg + 1);
769 cfg->flags |= MONO_CFG_HAS_FPOUT;
771 } else if (ainfo->regtype == RegTypeStructByAddr) {
772 /* FIXME: where si the data allocated? */
773 arg->unused = ainfo->reg;
774 call->used_iregs |= 1 << ainfo->reg;
775 g_assert_not_reached ();
776 } else if (ainfo->regtype == RegTypeStructByVal) {
778 /* mark the used regs */
779 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
780 call->used_iregs |= 1 << (ainfo->reg + cur_reg);
782 arg->opcode = OP_OUTARG_VT;
783 /* vtsize and offset have just 12 bits of encoding in number of words */
784 g_assert (((ainfo->vtsize | (ainfo->offset / 4)) & 0xfffff000) == 0);
785 arg->unused = ainfo->reg | (ainfo->size << 4) | (ainfo->vtsize << 8) | ((ainfo->offset / 4) << 20);
786 } else if (ainfo->regtype == RegTypeBase) {
787 arg->opcode = OP_OUTARG_MEMBASE;
788 arg->unused = (ainfo->offset << 8) | ainfo->size;
789 } else if (ainfo->regtype == RegTypeFP) {
790 arg->unused = ainfo->reg;
791 /* FPA args are passed in int regs */
792 call->used_iregs |= 1 << ainfo->reg;
793 if (ainfo->size == 8) {
794 arg->opcode = OP_OUTARG_R8;
795 call->used_iregs |= 1 << (ainfo->reg + 1);
797 arg->opcode = OP_OUTARG_R4;
799 cfg->flags |= MONO_CFG_HAS_FPOUT;
801 g_assert_not_reached ();
806 * Reverse the call->out_args list.
809 MonoInst *prev = NULL, *list = call->out_args, *next;
816 call->out_args = prev;
818 call->stack_usage = cinfo->stack_usage;
819 cfg->param_area = MAX (cfg->param_area, cinfo->stack_usage);
820 cfg->flags |= MONO_CFG_HAS_CALLS;
822 * should set more info in call, such as the stack space
823 * used by the args that needs to be added back to esp
831 * Allow tracing to work with this interface (with an optional argument)
835 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
839 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
840 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
841 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
842 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
843 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_R2);
856 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
859 int save_mode = SAVE_NONE;
861 MonoMethod *method = cfg->method;
862 int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
863 int save_offset = cfg->param_area;
867 offset = code - cfg->native_code;
868 /* we need about 16 instructions */
869 if (offset > (cfg->code_size - 16 * 4)) {
871 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
872 code = cfg->native_code + offset;
877 /* special case string .ctor icall */
878 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
879 save_mode = SAVE_ONE;
881 save_mode = SAVE_NONE;
885 save_mode = SAVE_TWO;
891 case MONO_TYPE_VALUETYPE:
892 save_mode = SAVE_STRUCT;
895 save_mode = SAVE_ONE;
901 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
902 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
903 if (enable_arguments) {
904 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
905 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
909 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
910 if (enable_arguments) {
911 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
915 /* FIXME: what reg? */
916 if (enable_arguments) {
917 /* FIXME: what reg? */
921 if (enable_arguments) {
922 /* FIXME: get the actual address */
923 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
931 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
932 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
933 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
934 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
938 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
939 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
942 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
956 * The immediate field for cond branches is big enough for all reasonable methods
958 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
959 if (ins->flags & MONO_INST_BRLABEL) { \
960 if (0 && ins->inst_i0->inst_c0) { \
961 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_i0->inst_c0) & 0xffffff); \
963 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
964 ARM_B_COND (code, (condcode), 0); \
967 if (0 && ins->inst_true_bb->native_offset) { \
968 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
970 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
971 ARM_B_COND (code, (condcode), 0); \
975 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
977 /* emit an exception if condition is fail
979 * We assign the extra code used to throw the implicit exceptions
980 * to cfg->bb_exit as far as the big branch handling is concerned
982 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
984 mono_add_patch_info (cfg, code - cfg->native_code, \
985 MONO_PATCH_INFO_EXC, exc_name); \
986 ARM_BL_COND (code, (condcode), 0); \
989 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
992 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
994 MonoInst *ins, *last_ins = NULL;
999 switch (ins->opcode) {
1001 /* remove unnecessary multiplication with 1 */
1002 if (ins->inst_imm == 1) {
1003 if (ins->dreg != ins->sreg1) {
1004 ins->opcode = OP_MOVE;
1006 last_ins->next = ins->next;
1011 int power2 = mono_is_power_of_two (ins->inst_imm);
1013 ins->opcode = OP_SHL_IMM;
1014 ins->inst_imm = power2;
1018 case OP_LOAD_MEMBASE:
1019 case OP_LOADI4_MEMBASE:
1021 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1022 * OP_LOAD_MEMBASE offset(basereg), reg
1024 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1025 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1026 ins->inst_basereg == last_ins->inst_destbasereg &&
1027 ins->inst_offset == last_ins->inst_offset) {
1028 if (ins->dreg == last_ins->sreg1) {
1029 last_ins->next = ins->next;
1033 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1034 ins->opcode = OP_MOVE;
1035 ins->sreg1 = last_ins->sreg1;
1039 * Note: reg1 must be different from the basereg in the second load
1040 * OP_LOAD_MEMBASE offset(basereg), reg1
1041 * OP_LOAD_MEMBASE offset(basereg), reg2
1043 * OP_LOAD_MEMBASE offset(basereg), reg1
1044 * OP_MOVE reg1, reg2
1046 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1047 || last_ins->opcode == OP_LOAD_MEMBASE) &&
1048 ins->inst_basereg != last_ins->dreg &&
1049 ins->inst_basereg == last_ins->inst_basereg &&
1050 ins->inst_offset == last_ins->inst_offset) {
1052 if (ins->dreg == last_ins->dreg) {
1053 last_ins->next = ins->next;
1057 ins->opcode = OP_MOVE;
1058 ins->sreg1 = last_ins->dreg;
1061 //g_assert_not_reached ();
1065 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1066 * OP_LOAD_MEMBASE offset(basereg), reg
1068 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1069 * OP_ICONST reg, imm
1071 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1072 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1073 ins->inst_basereg == last_ins->inst_destbasereg &&
1074 ins->inst_offset == last_ins->inst_offset) {
1075 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1076 ins->opcode = OP_ICONST;
1077 ins->inst_c0 = last_ins->inst_imm;
1078 g_assert_not_reached (); // check this rule
1082 case OP_LOADU1_MEMBASE:
1083 case OP_LOADI1_MEMBASE:
1084 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1085 ins->inst_basereg == last_ins->inst_destbasereg &&
1086 ins->inst_offset == last_ins->inst_offset) {
1087 if (ins->dreg == last_ins->sreg1) {
1088 last_ins->next = ins->next;
1092 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1093 ins->opcode = OP_MOVE;
1094 ins->sreg1 = last_ins->sreg1;
1098 case OP_LOADU2_MEMBASE:
1099 case OP_LOADI2_MEMBASE:
1100 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1101 ins->inst_basereg == last_ins->inst_destbasereg &&
1102 ins->inst_offset == last_ins->inst_offset) {
1103 if (ins->dreg == last_ins->sreg1) {
1104 last_ins->next = ins->next;
1108 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1109 ins->opcode = OP_MOVE;
1110 ins->sreg1 = last_ins->sreg1;
1118 ins->opcode = OP_MOVE;
1122 if (ins->dreg == ins->sreg1) {
1124 last_ins->next = ins->next;
1129 * OP_MOVE sreg, dreg
1130 * OP_MOVE dreg, sreg
1132 if (last_ins && last_ins->opcode == OP_MOVE &&
1133 ins->sreg1 == last_ins->dreg &&
1134 ins->dreg == last_ins->sreg1) {
1135 last_ins->next = ins->next;
1144 bb->last_ins = last_ins;
1148 * the branch_cc_table should maintain the order of these
1162 branch_cc_table [] = {
1178 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *to_insert)
1182 bb->code = to_insert;
1183 to_insert->next = ins;
1185 to_insert->next = ins->next;
1186 ins->next = to_insert;
1190 #define NEW_INS(cfg,dest,op) do { \
1191 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
1192 (dest)->opcode = (op); \
1193 insert_after_ins (bb, last_ins, (dest)); \
1197 map_to_reg_reg_op (int op)
1206 case OP_COMPARE_IMM:
1220 case OP_LOAD_MEMBASE:
1221 return OP_LOAD_MEMINDEX;
1222 case OP_LOADI4_MEMBASE:
1223 return OP_LOADI4_MEMINDEX;
1224 case OP_LOADU4_MEMBASE:
1225 return OP_LOADU4_MEMINDEX;
1226 case OP_LOADU1_MEMBASE:
1227 return OP_LOADU1_MEMINDEX;
1228 case OP_LOADI2_MEMBASE:
1229 return OP_LOADI2_MEMINDEX;
1230 case OP_LOADU2_MEMBASE:
1231 return OP_LOADU2_MEMINDEX;
1232 case OP_LOADI1_MEMBASE:
1233 return OP_LOADI1_MEMINDEX;
1234 case OP_STOREI1_MEMBASE_REG:
1235 return OP_STOREI1_MEMINDEX;
1236 case OP_STOREI2_MEMBASE_REG:
1237 return OP_STOREI2_MEMINDEX;
1238 case OP_STOREI4_MEMBASE_REG:
1239 return OP_STOREI4_MEMINDEX;
1240 case OP_STORE_MEMBASE_REG:
1241 return OP_STORE_MEMINDEX;
1242 case OP_STORER4_MEMBASE_REG:
1243 return OP_STORER4_MEMINDEX;
1244 case OP_STORER8_MEMBASE_REG:
1245 return OP_STORER8_MEMINDEX;
1246 case OP_STORE_MEMBASE_IMM:
1247 return OP_STORE_MEMBASE_REG;
1248 case OP_STOREI1_MEMBASE_IMM:
1249 return OP_STOREI1_MEMBASE_REG;
1250 case OP_STOREI2_MEMBASE_IMM:
1251 return OP_STOREI2_MEMBASE_REG;
1252 case OP_STOREI4_MEMBASE_IMM:
1253 return OP_STOREI4_MEMBASE_REG;
1255 g_assert_not_reached ();
1259 * Remove from the instruction list the instructions that can't be
1260 * represented with very simple instructions with no register
1264 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1266 MonoInst *ins, *next, *temp, *last_ins = NULL;
1267 int rot_amount, imm8, low_imm;
1269 /* setup the virtual reg allocator */
1270 if (bb->max_ireg > cfg->rs->next_vireg)
1271 cfg->rs->next_vireg = bb->max_ireg;
1276 switch (ins->opcode) {
1280 case OP_COMPARE_IMM:
1287 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
1288 NEW_INS (cfg, temp, OP_ICONST);
1289 temp->inst_c0 = ins->inst_imm;
1290 temp->dreg = mono_regstate_next_int (cfg->rs);
1291 ins->sreg2 = temp->dreg;
1292 ins->opcode = map_to_reg_reg_op (ins->opcode);
1296 if (ins->inst_imm == 1) {
1297 ins->opcode = OP_MOVE;
1300 if (ins->inst_imm == 0) {
1301 ins->opcode = OP_ICONST;
1305 imm8 = mono_is_power_of_two (ins->inst_imm);
1307 ins->opcode = OP_SHL_IMM;
1308 ins->inst_imm = imm8;
1311 NEW_INS (cfg, temp, OP_ICONST);
1312 temp->inst_c0 = ins->inst_imm;
1313 temp->dreg = mono_regstate_next_int (cfg->rs);
1314 ins->sreg2 = temp->dreg;
1315 ins->opcode = CEE_MUL;
1317 case OP_LOAD_MEMBASE:
1318 case OP_LOADI4_MEMBASE:
1319 case OP_LOADU4_MEMBASE:
1320 case OP_LOADU1_MEMBASE:
1321 /* we can do two things: load the immed in a register
1322 * and use an indexed load, or see if the immed can be
1323 * represented as an ad_imm + a load with a smaller offset
1324 * that fits. We just do the first for now, optimize later.
1326 if (arm_is_imm12 (ins->inst_offset))
1328 NEW_INS (cfg, temp, OP_ICONST);
1329 temp->inst_c0 = ins->inst_offset;
1330 temp->dreg = mono_regstate_next_int (cfg->rs);
1331 ins->sreg2 = temp->dreg;
1332 ins->opcode = map_to_reg_reg_op (ins->opcode);
1334 case OP_LOADI2_MEMBASE:
1335 case OP_LOADU2_MEMBASE:
1336 case OP_LOADI1_MEMBASE:
1337 if (arm_is_imm8 (ins->inst_offset))
1339 NEW_INS (cfg, temp, OP_ICONST);
1340 temp->inst_c0 = ins->inst_offset;
1341 temp->dreg = mono_regstate_next_int (cfg->rs);
1342 ins->sreg2 = temp->dreg;
1343 ins->opcode = map_to_reg_reg_op (ins->opcode);
1345 case OP_LOADR4_MEMBASE:
1346 case OP_LOADR8_MEMBASE:
1347 if (arm_is_fpimm8 (ins->inst_offset))
1349 low_imm = ins->inst_offset & 0x1ff;
1350 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
1351 NEW_INS (cfg, temp, OP_ADD_IMM);
1352 temp->inst_imm = ins->inst_offset & ~0x1ff;
1353 temp->sreg1 = ins->inst_basereg;
1354 temp->dreg = mono_regstate_next_int (cfg->rs);
1355 ins->inst_basereg = temp->dreg;
1356 ins->inst_offset = low_imm;
1359 /* FPA doesn't have indexed load instructions */
1360 g_assert_not_reached ();
1362 case OP_STORE_MEMBASE_REG:
1363 case OP_STOREI4_MEMBASE_REG:
1364 case OP_STOREI1_MEMBASE_REG:
1365 if (arm_is_imm12 (ins->inst_offset))
1367 NEW_INS (cfg, temp, OP_ICONST);
1368 temp->inst_c0 = ins->inst_offset;
1369 temp->dreg = mono_regstate_next_int (cfg->rs);
1370 ins->sreg2 = temp->dreg;
1371 ins->opcode = map_to_reg_reg_op (ins->opcode);
1373 case OP_STOREI2_MEMBASE_REG:
1374 if (arm_is_imm8 (ins->inst_offset))
1376 NEW_INS (cfg, temp, OP_ICONST);
1377 temp->inst_c0 = ins->inst_offset;
1378 temp->dreg = mono_regstate_next_int (cfg->rs);
1379 ins->sreg2 = temp->dreg;
1380 ins->opcode = map_to_reg_reg_op (ins->opcode);
1382 case OP_STORER4_MEMBASE_REG:
1383 case OP_STORER8_MEMBASE_REG:
1384 if (arm_is_fpimm8 (ins->inst_offset))
1386 low_imm = ins->inst_offset & 0x1ff;
1387 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
1388 NEW_INS (cfg, temp, OP_ADD_IMM);
1389 temp->inst_imm = ins->inst_offset & ~0x1ff;
1390 temp->sreg1 = ins->inst_destbasereg;
1391 temp->dreg = mono_regstate_next_int (cfg->rs);
1392 ins->inst_destbasereg = temp->dreg;
1393 ins->inst_offset = low_imm;
1396 /*g_print ("fail with: %d (%d, %d)\n", ins->inst_offset, ins->inst_offset & ~0x1ff, low_imm);*/
1397 /* FPA doesn't have indexed store instructions */
1398 g_assert_not_reached ();
1400 case OP_STORE_MEMBASE_IMM:
1401 case OP_STOREI1_MEMBASE_IMM:
1402 case OP_STOREI2_MEMBASE_IMM:
1403 case OP_STOREI4_MEMBASE_IMM:
1404 NEW_INS (cfg, temp, OP_ICONST);
1405 temp->inst_c0 = ins->inst_imm;
1406 temp->dreg = mono_regstate_next_int (cfg->rs);
1407 ins->sreg1 = temp->dreg;
1408 ins->opcode = map_to_reg_reg_op (ins->opcode);
1410 goto loop_start; /* make it handle the possibly big ins->inst_offset */
1415 bb->last_ins = last_ins;
1416 bb->max_ireg = cfg->rs->next_vireg;
1421 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1425 mono_arch_lowering_pass (cfg, bb);
1426 mono_local_regalloc (cfg, bb);
1430 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1432 /* sreg is a float, dreg is an integer reg */
1433 ARM_FIXZ (code, dreg, sreg);
1436 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
1437 else if (size == 2) {
1438 ARM_SHL_IMM (code, dreg, dreg, 16);
1439 ARM_SHR_IMM (code, dreg, dreg, 16);
1443 ARM_SHL_IMM (code, dreg, dreg, 24);
1444 ARM_SAR_IMM (code, dreg, dreg, 24);
1445 } else if (size == 2) {
1446 ARM_SHL_IMM (code, dreg, dreg, 16);
1447 ARM_SAR_IMM (code, dreg, dreg, 16);
1455 const guchar *target;
1460 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
1463 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
1464 PatchData *pdata = (PatchData*)user_data;
1465 guchar *code = data;
1466 guint32 *thunks = data;
1467 guint32 *endthunks = (guint32*)(code + bsize);
1469 int difflow, diffhigh;
1471 /* always ensure a call from pdata->code can reach to the thunks without further thunks */
1472 difflow = (char*)pdata->code - (char*)thunks;
1473 diffhigh = (char*)pdata->code - (char*)endthunks;
1474 if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
1478 * The thunk is composed of 3 words:
1479 * load constant from thunks [2] into ARM_IP
1482 * Note that the LR register is already setup
1484 //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
1485 if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
1486 while (thunks < endthunks) {
1487 //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
1488 if (thunks [2] == (guint32)pdata->target) {
1489 arm_patch (pdata->code, (guchar*)thunks);
1490 mono_arch_flush_icache (pdata->code, 4);
1493 } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
1494 /* found a free slot instead: emit thunk */
1495 code = (guchar*)thunks;
1496 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
1497 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
1498 thunks [2] = (guint32)pdata->target;
1499 mono_arch_flush_icache ((guchar*)thunks, 12);
1501 arm_patch (pdata->code, (guchar*)thunks);
1502 mono_arch_flush_icache (pdata->code, 4);
1506 /* skip 12 bytes, the size of the thunk */
1510 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
1516 handle_thunk (int absolute, guchar *code, const guchar *target) {
1517 MonoDomain *domain = mono_domain_get ();
1521 pdata.target = target;
1522 pdata.absolute = absolute;
1525 mono_domain_lock (domain);
1526 mono_code_manager_foreach (domain->code_mp, search_thunk_slot, &pdata);
1529 /* this uses the first available slot */
1531 mono_code_manager_foreach (domain->code_mp, search_thunk_slot, &pdata);
1533 mono_domain_unlock (domain);
1535 if (pdata.found != 1)
1536 g_print ("thunk failed for %p from %p\n", target, code);
1537 g_assert (pdata.found == 1);
1541 arm_patch (guchar *code, const guchar *target)
1543 guint32 ins = *(guint32*)code;
1544 guint32 prim = (ins >> 25) & 7;
1547 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
1548 if (prim == 5) { /* 101b */
1549 /* the diff starts 8 bytes from the branch opcode */
1550 gint diff = target - code - 8;
1552 if (diff <= 33554431) {
1554 ins = (ins & 0xff000000) | diff;
1555 *(guint32*)code = ins;
1559 /* diff between 0 and -33554432 */
1560 if (diff >= -33554432) {
1562 ins = (ins & 0xff000000) | (diff & ~0xff000000);
1563 *(guint32*)code = ins;
1568 handle_thunk (TRUE, code, target);
1573 if ((ins & 0x0ffffff0) == 0x12fff10) {
1574 /* branch and exchange: the address is constructed in a reg */
1575 g_assert_not_reached ();
1577 g_assert_not_reached ();
1579 // g_print ("patched with 0x%08x\n", ins);
1583 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
1584 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
1585 * to be used with the emit macros.
1586 * Return -1 otherwise.
1589 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
1592 for (i = 0; i < 31; i+= 2) {
1593 res = (val << (32 - i)) | (val >> i);
1596 *rot_amount = i? 32 - i: 0;
1603 * Emits in code a sequence of instructions that load the value 'val'
1604 * into the dreg register. Uses at most 4 instructions.
1607 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
1609 int imm8, rot_amount;
1611 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
1612 /* skip the constant pool */
1618 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
1619 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
1620 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
1621 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
1624 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
1626 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
1628 if (val & 0xFF0000) {
1629 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
1631 if (val & 0xFF000000) {
1632 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
1634 } else if (val & 0xFF00) {
1635 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
1636 if (val & 0xFF0000) {
1637 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
1639 if (val & 0xFF000000) {
1640 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
1642 } else if (val & 0xFF0000) {
1643 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
1644 if (val & 0xFF000000) {
1645 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
1648 //g_assert_not_reached ();
1654 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
1659 guint8 *code = cfg->native_code + cfg->code_len;
1660 MonoInst *last_ins = NULL;
1661 guint last_offset = 0;
1663 int imm8, rot_amount;
1665 if (cfg->opt & MONO_OPT_PEEPHOLE)
1666 peephole_pass (cfg, bb);
1668 /* we don't align basic blocks of loops on arm */
1670 if (cfg->verbose_level > 2)
1671 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
1673 cpos = bb->max_offset;
1675 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
1676 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
1677 //g_assert (!mono_compile_aot);
1680 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
1681 /* this is not thread save, but good enough */
1682 /* fixme: howto handle overflows? */
1683 //x86_inc_mem (code, &cov->data [bb->dfn].count);
1688 offset = code - cfg->native_code;
1690 max_len = ((guint8 *)arm_cpu_desc [ins->opcode])[MONO_INST_LEN];
1692 if (offset > (cfg->code_size - max_len - 16)) {
1693 cfg->code_size *= 2;
1694 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
1695 code = cfg->native_code + offset;
1697 // if (ins->cil_code)
1698 // g_print ("cil code\n");
1699 mono_debug_record_line_number (cfg, ins, offset);
1701 switch (ins->opcode) {
1703 g_assert_not_reached ();
1706 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
1707 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
1710 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
1711 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
1713 case OP_STOREI1_MEMBASE_IMM:
1714 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
1715 g_assert (arm_is_imm12 (ins->inst_offset));
1716 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
1718 case OP_STOREI2_MEMBASE_IMM:
1719 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
1720 g_assert (arm_is_imm8 (ins->inst_offset));
1721 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
1723 case OP_STORE_MEMBASE_IMM:
1724 case OP_STOREI4_MEMBASE_IMM:
1725 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
1726 g_assert (arm_is_imm12 (ins->inst_offset));
1727 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
1729 case OP_STOREI1_MEMBASE_REG:
1730 g_assert (arm_is_imm12 (ins->inst_offset));
1731 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
1733 case OP_STOREI2_MEMBASE_REG:
1734 g_assert (arm_is_imm8 (ins->inst_offset));
1735 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
1737 case OP_STORE_MEMBASE_REG:
1738 case OP_STOREI4_MEMBASE_REG:
1739 /* this case is special, since it happens for spill code after lowering has been called */
1740 if (arm_is_imm12 (ins->inst_offset)) {
1741 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
1743 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
1744 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
1747 case OP_STOREI1_MEMINDEX:
1748 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
1750 case OP_STOREI2_MEMINDEX:
1751 /* note: the args are reversed in the macro */
1752 ARM_STRH_REG_REG (code, ins->inst_destbasereg, ins->sreg1, ins->sreg2);
1754 case OP_STORE_MEMINDEX:
1755 case OP_STOREI4_MEMINDEX:
1756 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
1761 g_assert_not_reached ();
1764 g_assert_not_reached ();
1766 case OP_LOAD_MEMINDEX:
1767 case OP_LOADI4_MEMINDEX:
1768 case OP_LOADU4_MEMINDEX:
1769 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1771 case OP_LOADI1_MEMINDEX:
1772 /* note: the args are reversed in the macro */
1773 ARM_LDRSB_REG_REG (code, ins->inst_basereg, ins->dreg, ins->sreg2);
1775 case OP_LOADU1_MEMINDEX:
1776 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1778 case OP_LOADI2_MEMINDEX:
1779 /* note: the args are reversed in the macro */
1780 ARM_LDRSH_REG_REG (code, ins->inst_basereg, ins->dreg, ins->sreg2);
1782 case OP_LOADU2_MEMINDEX:
1783 /* note: the args are reversed in the macro */
1784 ARM_LDRH_REG_REG (code, ins->inst_basereg, ins->dreg, ins->sreg2);
1786 case OP_LOAD_MEMBASE:
1787 case OP_LOADI4_MEMBASE:
1788 case OP_LOADU4_MEMBASE:
1789 /* this case is special, since it happens for spill code after lowering has been called */
1790 if (arm_is_imm12 (ins->inst_offset)) {
1791 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1793 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
1794 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
1797 case OP_LOADI1_MEMBASE:
1798 g_assert (arm_is_imm8 (ins->inst_offset));
1799 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1801 case OP_LOADU1_MEMBASE:
1802 g_assert (arm_is_imm12 (ins->inst_offset));
1803 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1805 case OP_LOADU2_MEMBASE:
1806 g_assert (arm_is_imm8 (ins->inst_offset));
1807 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1809 case OP_LOADI2_MEMBASE:
1810 g_assert (arm_is_imm8 (ins->inst_offset));
1811 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1814 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
1815 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
1818 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
1819 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
1822 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
1825 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
1826 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
1829 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
1831 case OP_COMPARE_IMM:
1832 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1833 g_assert (imm8 >= 0);
1834 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
1836 case OP_X86_TEST_NULL:
1837 g_assert_not_reached ();
1840 *(int*)code = 0xe7f001f0;
1841 *(int*)code = 0xef9f0001;
1846 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1849 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1852 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1855 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1856 g_assert (imm8 >= 0);
1857 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1860 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1861 g_assert (imm8 >= 0);
1862 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1865 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1866 g_assert (imm8 >= 0);
1867 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1870 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1871 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1873 case CEE_ADD_OVF_UN:
1874 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1875 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1878 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1879 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1881 case CEE_SUB_OVF_UN:
1882 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1883 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
1885 case OP_ADD_OVF_CARRY:
1886 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1887 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1889 case OP_ADD_OVF_UN_CARRY:
1890 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1891 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1893 case OP_SUB_OVF_CARRY:
1894 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1895 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1897 case OP_SUB_OVF_UN_CARRY:
1898 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1899 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
1902 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1905 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1906 g_assert (imm8 >= 0);
1907 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1910 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1913 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1916 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1917 g_assert (imm8 >= 0);
1918 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1921 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1922 g_assert (imm8 >= 0);
1923 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1925 case OP_ARM_RSBS_IMM:
1926 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1927 g_assert (imm8 >= 0);
1928 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1930 case OP_ARM_RSC_IMM:
1931 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1932 g_assert (imm8 >= 0);
1933 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1936 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1939 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1940 g_assert (imm8 >= 0);
1941 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1949 /* crappy ARM arch doesn't have a DIV instruction */
1950 g_assert_not_reached ();
1952 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1955 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1956 g_assert (imm8 >= 0);
1957 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1960 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1963 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1964 g_assert (imm8 >= 0);
1965 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1968 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1972 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
1975 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1979 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
1983 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
1986 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1989 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
1992 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
1995 if (ins->dreg == ins->sreg2)
1996 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1998 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
2001 g_assert_not_reached ();
2004 /* FIXME: handle ovf/ sreg2 != dreg */
2005 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
2007 case CEE_MUL_OVF_UN:
2008 /* FIXME: handle ovf/ sreg2 != dreg */
2009 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
2013 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
2016 g_assert_not_reached ();
2017 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2023 if (ins->dreg != ins->sreg1)
2024 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
2027 int saved = ins->sreg2;
2028 if (ins->sreg2 == ARM_LSW_REG) {
2029 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
2032 if (ins->sreg1 != ARM_LSW_REG)
2033 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
2034 if (saved != ARM_MSW_REG)
2035 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
2040 ARM_MVFD (code, ins->dreg, ins->sreg1);
2042 case OP_FCONV_TO_R4:
2043 ARM_MVFS (code, ins->dreg, ins->sreg1);
2047 * Keep in sync with mono_arch_emit_epilog
2049 g_assert (!cfg->method->save_lmf);
2050 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
2051 ARM_POP_NWB (code, cfg->used_int_regs | ((1 << ARMREG_SP)) | ((1 << ARMREG_LR)));
2052 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2056 /* ensure ins->sreg1 is not NULL */
2057 ARM_LDR_IMM (code, ARMREG_LR, ins->sreg1, 0);
2061 if (ppc_is_imm16 (cfg->sig_cookie + cfg->stack_usage)) {
2062 ppc_addi (code, ppc_r11, cfg->frame_reg, cfg->sig_cookie + cfg->stack_usage);
2064 ppc_load (code, ppc_r11, cfg->sig_cookie + cfg->stack_usage);
2065 ppc_add (code, ppc_r11, cfg->frame_reg, ppc_r11);
2067 ppc_stw (code, ppc_r11, 0, ins->sreg1);
2076 call = (MonoCallInst*)ins;
2077 if (ins->flags & MONO_INST_HAS_METHOD)
2078 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
2080 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
2081 if (cfg->method->dynamic) {
2082 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2084 *(gpointer*)code = NULL;
2086 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2087 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2095 case OP_VOIDCALL_REG:
2097 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2098 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
2100 case OP_FCALL_MEMBASE:
2101 case OP_LCALL_MEMBASE:
2102 case OP_VCALL_MEMBASE:
2103 case OP_VOIDCALL_MEMBASE:
2104 case OP_CALL_MEMBASE:
2105 g_assert (arm_is_imm12 (ins->inst_offset));
2106 g_assert (ins->sreg1 != ARMREG_LR);
2107 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2108 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
2111 g_assert_not_reached ();
2114 /* keep alignment */
2115 int alloca_waste = cfg->param_area;
2118 /* round the size to 8 bytes */
2119 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
2120 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
2121 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
2122 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
2123 /* memzero the area: dreg holds the size, sp is the pointer */
2124 if (ins->flags & MONO_INST_INIT) {
2125 guint8 *start_loop, *branch_to_cond;
2126 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
2127 branch_to_cond = code;
2130 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
2131 arm_patch (branch_to_cond, code);
2132 /* decrement by 4 and set flags */
2133 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, 4);
2134 ARM_B_COND (code, ARMCOND_LT, 0);
2135 arm_patch (code - 4, start_loop);
2137 ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
2141 g_assert_not_reached ();
2142 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_LR);
2145 if (ins->sreg1 != ARMREG_R0)
2146 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
2147 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2148 (gpointer)"mono_arch_throw_exception");
2149 if (cfg->method->dynamic) {
2150 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2152 *(gpointer*)code = NULL;
2154 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2155 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2162 if (ins->sreg1 != ARMREG_R0)
2163 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
2164 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2165 (gpointer)"mono_arch_rethrow_exception");
2166 if (cfg->method->dynamic) {
2167 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2169 *(gpointer*)code = NULL;
2171 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2172 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2178 case OP_START_HANDLER:
2179 if (arm_is_imm12 (ins->inst_left->inst_offset)) {
2180 ARM_STR_IMM (code, ARMREG_LR, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
2182 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_left->inst_offset);
2183 ARM_STR_REG_REG (code, ARMREG_LR, ins->inst_left->inst_basereg, ARMREG_IP);
2187 if (ins->sreg1 != ARMREG_R0)
2188 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
2189 if (arm_is_imm12 (ins->inst_left->inst_offset)) {
2190 ARM_LDR_IMM (code, ARMREG_IP, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
2192 g_assert (ARMREG_IP != ins->inst_left->inst_basereg);
2193 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_left->inst_offset);
2194 ARM_LDR_REG_REG (code, ARMREG_IP, ins->inst_left->inst_basereg, ARMREG_IP);
2196 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2198 case CEE_ENDFINALLY:
2199 if (arm_is_imm12 (ins->inst_left->inst_offset)) {
2200 ARM_LDR_IMM (code, ARMREG_IP, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
2202 g_assert (ARMREG_IP != ins->inst_left->inst_basereg);
2203 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_left->inst_offset);
2204 ARM_LDR_REG_REG (code, ARMREG_IP, ins->inst_left->inst_basereg, ARMREG_IP);
2206 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2208 case OP_CALL_HANDLER:
2209 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2213 ins->inst_c0 = code - cfg->native_code;
2216 if (ins->flags & MONO_INST_BRLABEL) {
2217 /*if (ins->inst_i0->inst_c0) {
2219 //x86_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
2221 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2225 /*if (ins->inst_target_bb->native_offset) {
2227 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2229 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2235 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
2239 * In the normal case we have:
2240 * ldr pc, [pc, ins->sreg1 << 2]
2243 * ldr lr, [pc, ins->sreg1 << 2]
2245 * After follows the data.
2246 * FIXME: add aot support.
2248 max_len += 4 * GPOINTER_TO_INT (ins->klass);
2249 if (offset > (cfg->code_size - max_len - 16)) {
2250 cfg->code_size += max_len;
2251 cfg->code_size *= 2;
2252 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2253 code = cfg->native_code + offset;
2255 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
2257 code += 4 * GPOINTER_TO_INT (ins->klass);
2260 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2261 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
2264 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2265 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
2268 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2269 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
2272 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2273 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
2276 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2277 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
2279 case OP_COND_EXC_EQ:
2280 case OP_COND_EXC_NE_UN:
2281 case OP_COND_EXC_LT:
2282 case OP_COND_EXC_LT_UN:
2283 case OP_COND_EXC_GT:
2284 case OP_COND_EXC_GT_UN:
2285 case OP_COND_EXC_GE:
2286 case OP_COND_EXC_GE_UN:
2287 case OP_COND_EXC_LE:
2288 case OP_COND_EXC_LE_UN:
2289 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
2292 case OP_COND_EXC_OV:
2293 case OP_COND_EXC_NC:
2294 case OP_COND_EXC_NO:
2295 g_assert_not_reached ();
2307 EMIT_COND_BRANCH (ins, ins->opcode - CEE_BEQ);
2310 /* floating point opcodes */
2312 /* FIXME: we can optimize the imm load by dealing with part of
2313 * the displacement in LDFD (aligning to 512).
2315 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
2316 ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
2319 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
2320 ARM_LDFS (code, ins->dreg, ARMREG_LR, 0);
2322 case OP_STORER8_MEMBASE_REG:
2323 g_assert (arm_is_fpimm8 (ins->inst_offset));
2324 ARM_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
2326 case OP_LOADR8_MEMBASE:
2327 g_assert (arm_is_fpimm8 (ins->inst_offset));
2328 ARM_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2330 case OP_STORER4_MEMBASE_REG:
2331 g_assert (arm_is_fpimm8 (ins->inst_offset));
2332 ARM_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
2334 case OP_LOADR4_MEMBASE:
2335 g_assert (arm_is_fpimm8 (ins->inst_offset));
2336 ARM_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2338 case CEE_CONV_R_UN: {
2340 tmpreg = ins->dreg == 0? 1: 0;
2341 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
2342 ARM_FLTD (code, ins->dreg, ins->sreg1);
2343 ARM_B_COND (code, ARMCOND_GE, 8);
2344 /* save the temp register */
2345 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
2346 ARM_STFD (code, tmpreg, ARMREG_SP, 0);
2347 ARM_LDFD (code, tmpreg, ARMREG_PC, 4);
2348 ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
2349 ARM_LDFD (code, tmpreg, ARMREG_SP, 0);
2350 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
2351 /* skip the constant pool */
2353 *(int*)code = 0x41f00000;
2358 * ldfltd ftemp, [pc, #8] 0x41f00000 0x00000000
2359 * adfltd fdest, fdest, ftemp
2364 ARM_FLTS (code, ins->dreg, ins->sreg1);
2367 ARM_FLTD (code, ins->dreg, ins->sreg1);
2369 case OP_X86_FP_LOAD_I8:
2370 g_assert_not_reached ();
2371 /*x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);*/
2373 case OP_X86_FP_LOAD_I4:
2374 g_assert_not_reached ();
2375 /*x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);*/
2377 case OP_FCONV_TO_I1:
2378 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
2380 case OP_FCONV_TO_U1:
2381 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
2383 case OP_FCONV_TO_I2:
2384 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
2386 case OP_FCONV_TO_U2:
2387 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
2389 case OP_FCONV_TO_I4:
2391 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
2393 case OP_FCONV_TO_U4:
2395 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
2397 case OP_FCONV_TO_I8:
2398 case OP_FCONV_TO_U8:
2399 g_assert_not_reached ();
2400 /* Implemented as helper calls */
2402 case OP_LCONV_TO_R_UN:
2403 g_assert_not_reached ();
2404 /* Implemented as helper calls */
2406 case OP_LCONV_TO_OVF_I: {
2408 guint32 *negative_branch, *msword_positive_branch, *msword_negative_branch, *ovf_ex_target;
2409 // Check if its negative
2410 ppc_cmpi (code, 0, 0, ins->sreg1, 0);
2411 negative_branch = code;
2412 ppc_bc (code, PPC_BR_TRUE, PPC_BR_LT, 0);
2413 // Its positive msword == 0
2414 ppc_cmpi (code, 0, 0, ins->sreg2, 0);
2415 msword_positive_branch = code;
2416 ppc_bc (code, PPC_BR_TRUE, PPC_BR_EQ, 0);
2418 ovf_ex_target = code;
2419 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_ALWAYS, 0, "OverflowException");
2421 ppc_patch (negative_branch, code);
2422 ppc_cmpi (code, 0, 0, ins->sreg2, -1);
2423 msword_negative_branch = code;
2424 ppc_bc (code, PPC_BR_FALSE, PPC_BR_EQ, 0);
2425 ppc_patch (msword_negative_branch, ovf_ex_target);
2427 ppc_patch (msword_positive_branch, code);
2428 if (ins->dreg != ins->sreg1)
2429 ppc_mr (code, ins->dreg, ins->sreg1);
2431 if (ins->dreg != ins->sreg1)
2432 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
2436 ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2439 ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2442 ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2445 ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2448 ARM_MNFD (code, ins->dreg, ins->sreg1);
2452 g_assert_not_reached ();
2455 /* each fp compare op needs to do its own */
2456 g_assert_not_reached ();
2457 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2460 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2461 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2462 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
2465 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2466 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2467 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2470 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2471 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2472 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2473 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
2477 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2478 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2479 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2483 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2484 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2485 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2486 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
2488 /* ARM FPA flags table:
2489 * N Less than ARMCOND_MI
2490 * Z Equal ARMCOND_EQ
2491 * C Greater Than or Equal ARMCOND_CS
2492 * V Unordered ARMCOND_VS
2495 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2496 EMIT_COND_BRANCH (ins, CEE_BEQ - CEE_BEQ);
2499 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2500 EMIT_COND_BRANCH (ins, CEE_BNE_UN - CEE_BEQ);
2503 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2504 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
2507 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2508 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2509 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
2512 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2513 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set, swapped args */
2516 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2517 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2518 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set, swapped args */
2521 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2522 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
2525 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2526 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2527 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
2530 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2531 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS); /* swapped */
2534 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2535 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2536 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS); /* swapped */
2538 case CEE_CKFINITE: {
2539 /*ppc_stfd (code, ins->sreg1, -8, ppc_sp);
2540 ppc_lwz (code, ppc_r11, -8, ppc_sp);
2541 ppc_rlwinm (code, ppc_r11, ppc_r11, 0, 1, 31);
2542 ppc_addis (code, ppc_r11, ppc_r11, -32752);
2543 ppc_rlwinmd (code, ppc_r11, ppc_r11, 1, 31, 31);
2544 EMIT_COND_SYSTEM_EXCEPTION (CEE_BEQ - CEE_BEQ, "ArithmeticException");*/
2545 g_assert_not_reached ();
2549 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
2550 g_assert_not_reached ();
2553 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
2554 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
2555 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
2556 g_assert_not_reached ();
2562 last_offset = offset;
2567 cfg->code_len = code - cfg->native_code;
2571 mono_arch_register_lowlevel_calls (void)
2575 #define patch_lis_ori(ip,val) do {\
2576 guint16 *__lis_ori = (guint16*)(ip); \
2577 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
2578 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
2582 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
2584 MonoJumpInfo *patch_info;
2586 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
2587 unsigned char *ip = patch_info->ip.i + code;
2588 const unsigned char *target;
2590 if (patch_info->type == MONO_PATCH_INFO_SWITCH) {
2591 gpointer *table = (gpointer *)patch_info->data.table->table;
2592 gpointer *jt = (gpointer*)(ip + 8);
2594 /* jt is the inlined jump table, 2 instructions after ip
2595 * In the normal case we store the absolute addresses,
2596 * otherwise the displacements.
2598 for (i = 0; i < patch_info->data.table->table_size; i++) {
2599 jt [i] = code + (int)patch_info->data.table->table [i];
2603 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
2605 switch (patch_info->type) {
2606 case MONO_PATCH_INFO_IP:
2607 g_assert_not_reached ();
2608 patch_lis_ori (ip, ip);
2610 case MONO_PATCH_INFO_METHOD_REL:
2611 g_assert_not_reached ();
2612 *((gpointer *)(ip)) = code + patch_info->data.offset;
2614 case MONO_PATCH_INFO_METHODCONST:
2615 case MONO_PATCH_INFO_CLASS:
2616 case MONO_PATCH_INFO_IMAGE:
2617 case MONO_PATCH_INFO_FIELD:
2618 case MONO_PATCH_INFO_VTABLE:
2619 case MONO_PATCH_INFO_IID:
2620 case MONO_PATCH_INFO_SFLDA:
2621 case MONO_PATCH_INFO_LDSTR:
2622 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
2623 case MONO_PATCH_INFO_LDTOKEN:
2624 g_assert_not_reached ();
2625 /* from OP_AOTCONST : lis + ori */
2626 patch_lis_ori (ip, target);
2628 case MONO_PATCH_INFO_R4:
2629 case MONO_PATCH_INFO_R8:
2630 g_assert_not_reached ();
2631 *((gconstpointer *)(ip + 2)) = patch_info->data.target;
2633 case MONO_PATCH_INFO_EXC_NAME:
2634 g_assert_not_reached ();
2635 *((gconstpointer *)(ip + 1)) = patch_info->data.name;
2637 case MONO_PATCH_INFO_NONE:
2638 case MONO_PATCH_INFO_BB_OVF:
2639 case MONO_PATCH_INFO_EXC_OVF:
2640 /* everything is dealt with at epilog output time */
2645 arm_patch (ip, target);
2650 * Stack frame layout:
2652 * ------------------- fp
2653 * MonoLMF structure or saved registers
2654 * -------------------
2656 * -------------------
2658 * -------------------
2659 * optional 8 bytes for tracing
2660 * -------------------
2661 * param area size is cfg->param_area
2662 * ------------------- sp
2665 mono_arch_emit_prolog (MonoCompile *cfg)
2667 MonoMethod *method = cfg->method;
2669 MonoMethodSignature *sig;
2671 int alloc_size, pos, max_offset, i, rot_amount;
2678 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
2681 sig = mono_method_signature (method);
2682 cfg->code_size = 256 + sig->param_count * 20;
2683 code = cfg->native_code = g_malloc (cfg->code_size);
2685 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
2687 alloc_size = cfg->stack_offset;
2690 if (!method->save_lmf) {
2691 ARM_PUSH (code, (cfg->used_int_regs | (1 << ARMREG_IP) | (1 << ARMREG_LR)));
2692 prev_sp_offset = 8; /* ip and lr */
2693 for (i = 0; i < 16; ++i) {
2694 if (cfg->used_int_regs & (1 << i))
2695 prev_sp_offset += 4;
2698 ARM_PUSH (code, 0x5ff0);
2699 prev_sp_offset = 4 * 10; /* all but r0-r3, sp and pc */
2700 pos += sizeof (MonoLMF) - prev_sp_offset;
2704 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
2705 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
2706 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
2707 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
2710 /* the stack used in the pushed regs */
2711 if (prev_sp_offset & 4)
2713 cfg->stack_usage = alloc_size;
2715 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
2716 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
2718 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
2719 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
2722 if (cfg->frame_reg != ARMREG_SP)
2723 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
2724 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
2725 prev_sp_offset += alloc_size;
2727 /* compute max_offset in order to use short forward jumps
2728 * we could skip do it on arm because the immediate displacement
2729 * for jumps is large enough, it may be useful later for constant pools
2732 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
2733 MonoInst *ins = bb->code;
2734 bb->max_offset = max_offset;
2736 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
2740 max_offset += ((guint8 *)arm_cpu_desc [ins->opcode])[MONO_INST_LEN];
2745 /* load arguments allocated to register from the stack */
2748 cinfo = calculate_sizes (sig, sig->pinvoke);
2750 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
2751 ArgInfo *ainfo = &cinfo->ret;
2753 g_assert (arm_is_imm12 (inst->inst_offset));
2754 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2756 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2757 ArgInfo *ainfo = cinfo->args + i;
2758 inst = cfg->varinfo [pos];
2760 if (cfg->verbose_level > 2)
2761 g_print ("Saving argument %d (type: %d)\n", i, ainfo->regtype);
2762 if (inst->opcode == OP_REGVAR) {
2763 if (ainfo->regtype == RegTypeGeneral)
2764 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
2765 else if (ainfo->regtype == RegTypeFP) {
2766 g_assert_not_reached ();
2767 } else if (ainfo->regtype == RegTypeBase) {
2768 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
2769 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2771 g_assert_not_reached ();
2773 if (cfg->verbose_level > 2)
2774 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
2776 /* the argument should be put on the stack: FIXME handle size != word */
2777 if (ainfo->regtype == RegTypeGeneral) {
2778 switch (ainfo->size) {
2780 if (arm_is_imm12 (inst->inst_offset))
2781 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2783 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
2784 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
2788 g_assert (arm_is_imm8 (inst->inst_offset));
2789 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2792 g_assert (arm_is_imm12 (inst->inst_offset));
2793 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2794 g_assert (arm_is_imm12 (inst->inst_offset + 4));
2795 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
2798 if (arm_is_imm12 (inst->inst_offset)) {
2799 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2801 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
2802 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
2806 } else if (ainfo->regtype == RegTypeBase) {
2807 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
2808 switch (ainfo->size) {
2810 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2811 g_assert (arm_is_imm12 (inst->inst_offset));
2812 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2815 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2816 g_assert (arm_is_imm8 (inst->inst_offset));
2817 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2820 g_assert (arm_is_imm12 (inst->inst_offset));
2821 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2822 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2823 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4));
2824 g_assert (arm_is_imm12 (inst->inst_offset + 4));
2825 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
2826 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
2829 g_assert (arm_is_imm12 (inst->inst_offset));
2830 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2831 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2834 } else if (ainfo->regtype == RegTypeFP) {
2835 g_assert_not_reached ();
2836 } else if (ainfo->regtype == RegTypeStructByVal) {
2837 int doffset = inst->inst_offset;
2841 if (mono_class_from_mono_type (inst->inst_vtype))
2842 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
2843 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
2844 g_assert (arm_is_imm12 (doffset));
2845 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
2846 soffset += sizeof (gpointer);
2847 doffset += sizeof (gpointer);
2849 if (ainfo->vtsize) {
2850 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
2851 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
2852 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
2854 } else if (ainfo->regtype == RegTypeStructByAddr) {
2855 g_assert_not_reached ();
2856 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
2857 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
2859 g_assert_not_reached ();
2864 if (method->save_lmf) {
2866 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2867 (gpointer)"mono_get_lmf_addr");
2868 if (cfg->method->dynamic) {
2869 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2871 *(gpointer*)code = NULL;
2873 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2874 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2878 /* we build the MonoLMF structure on the stack - see mini-arm.h */
2879 /* lmf_offset is the offset from the previous stack pointer,
2880 * alloc_size is the total stack space allocated, so the offset
2881 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
2882 * The pointer to the struct is put in r1 (new_lmf).
2883 * r2 is used as scratch
2884 * The callee-saved registers are already in the MonoLMF structure
2886 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, alloc_size - lmf_offset);
2887 /* r0 is the result from mono_get_lmf_addr () */
2888 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
2889 /* new_lmf->previous_lmf = *lmf_addr */
2890 ARM_LDR_IMM (code, ARMREG_R2, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2891 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2892 /* *(lmf_addr) = r1 */
2893 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2894 /* save method info */
2895 code = mono_arm_emit_load_imm (code, ARMREG_R2, method);
2896 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, method));
2897 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ebp));
2898 /* save the current IP */
2899 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
2900 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, eip));
2904 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
2906 cfg->code_len = code - cfg->native_code;
2907 g_assert (cfg->code_len < cfg->code_size);
2914 mono_arch_emit_epilog (MonoCompile *cfg)
2916 MonoJumpInfo *patch_info;
2917 MonoMethod *method = cfg->method;
2918 int pos, i, rot_amount;
2919 int max_epilog_size = 16 + 20*4;
2922 if (cfg->method->save_lmf)
2923 max_epilog_size += 128;
2925 if (mono_jit_trace_calls != NULL)
2926 max_epilog_size += 50;
2928 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2929 max_epilog_size += 50;
2931 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
2932 cfg->code_size *= 2;
2933 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2934 mono_jit_stats.code_reallocs++;
2938 * Keep in sync with CEE_JMP
2940 code = cfg->native_code + cfg->code_len;
2942 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
2943 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
2947 if (method->save_lmf) {
2949 /* all but r0-r3, sp and pc */
2950 pos += sizeof (MonoLMF) - (4 * 10);
2952 /* r2 contains the pointer to the current LMF */
2953 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, cfg->stack_usage - lmf_offset);
2954 /* ip = previous_lmf */
2955 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2957 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
2958 /* *(lmf_addr) = previous_lmf */
2959 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2960 /* FIXME: speedup: there is no actual need to restore the registers if
2961 * we didn't actually change them (idea from Zoltan).
2964 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
2965 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_R2, (sizeof (MonoLMF) - 10 * sizeof (gulong)));
2966 ARM_POP_NWB (code, 0xaff0); /* restore ip to sp and lr to pc */
2968 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
2969 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
2971 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
2972 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
2974 ARM_POP_NWB (code, cfg->used_int_regs | ((1 << ARMREG_SP) | (1 << ARMREG_PC)));
2977 cfg->code_len = code - cfg->native_code;
2979 g_assert (cfg->code_len < cfg->code_size);
2983 /* remove once throw_exception_by_name is eliminated */
2985 exception_id_by_name (const char *name)
2987 if (strcmp (name, "IndexOutOfRangeException") == 0)
2988 return MONO_EXC_INDEX_OUT_OF_RANGE;
2989 if (strcmp (name, "OverflowException") == 0)
2990 return MONO_EXC_OVERFLOW;
2991 if (strcmp (name, "ArithmeticException") == 0)
2992 return MONO_EXC_ARITHMETIC;
2993 if (strcmp (name, "DivideByZeroException") == 0)
2994 return MONO_EXC_DIVIDE_BY_ZERO;
2995 if (strcmp (name, "InvalidCastException") == 0)
2996 return MONO_EXC_INVALID_CAST;
2997 if (strcmp (name, "NullReferenceException") == 0)
2998 return MONO_EXC_NULL_REF;
2999 if (strcmp (name, "ArrayTypeMismatchException") == 0)
3000 return MONO_EXC_ARRAY_TYPE_MISMATCH;
3001 g_error ("Unknown intrinsic exception %s\n", name);
3005 mono_arch_emit_exceptions (MonoCompile *cfg)
3007 MonoJumpInfo *patch_info;
3010 const guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM] = {NULL};
3011 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM] = {0};
3014 int max_epilog_size = 50;
3016 /* count the number of exception infos */
3019 * make sure we have enough space for exceptions
3020 * 12 is the simulated call to throw_exception_by_name
3022 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3023 if (patch_info->type == MONO_PATCH_INFO_EXC) {
3024 i = exception_id_by_name (patch_info->data.target);
3025 if (!exc_throw_found [i]) {
3026 max_epilog_size += 12;
3027 exc_throw_found [i] = TRUE;
3032 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
3033 cfg->code_size *= 2;
3034 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3035 mono_jit_stats.code_reallocs++;
3038 code = cfg->native_code + cfg->code_len;
3040 /* add code to raise exceptions */
3041 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3042 switch (patch_info->type) {
3043 case MONO_PATCH_INFO_EXC: {
3044 unsigned char *ip = patch_info->ip.i + cfg->native_code;
3045 const char *ex_name = patch_info->data.target;
3046 i = exception_id_by_name (patch_info->data.target);
3047 if (exc_throw_pos [i]) {
3048 arm_patch (ip, exc_throw_pos [i]);
3049 patch_info->type = MONO_PATCH_INFO_NONE;
3052 exc_throw_pos [i] = code;
3054 arm_patch (ip, code);
3055 //*(int*)code = 0xef9f0001;
3057 /*mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC_NAME, patch_info->data.target);*/
3058 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
3059 /* we got here from a conditional call, so the calling ip is set in lr already */
3060 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
3061 patch_info->data.name = "mono_arch_throw_exception_by_name";
3062 patch_info->ip.i = code - cfg->native_code;
3064 *(gpointer*)code = ex_name;
3074 cfg->code_len = code - cfg->native_code;
3076 g_assert (cfg->code_len < cfg->code_size);
3081 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
3086 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
3091 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
3094 int this_dreg = ARMREG_R0;
3097 this_dreg = ARMREG_R1;
3099 /* add the this argument */
3100 if (this_reg != -1) {
3102 MONO_INST_NEW (cfg, this, OP_SETREG);
3103 this->type = this_type;
3104 this->sreg1 = this_reg;
3105 this->dreg = mono_regstate_next_int (cfg->rs);
3106 mono_bblock_add_inst (cfg->cbb, this);
3107 mono_call_inst_add_outarg_reg (inst, this->dreg, this_dreg, FALSE);
3112 MONO_INST_NEW (cfg, vtarg, OP_SETREG);
3113 vtarg->type = STACK_MP;
3114 vtarg->sreg1 = vt_reg;
3115 vtarg->dreg = mono_regstate_next_int (cfg->rs);
3116 mono_bblock_add_inst (cfg->cbb, vtarg);
3117 mono_call_inst_add_outarg_reg (inst, vtarg->dreg, ARMREG_R0, FALSE);
3122 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
3128 mono_arch_print_tree (MonoInst *tree, int arity)
3133 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
3139 mono_arch_get_thread_intrinsic (MonoCompile* cfg)
3145 mono_arch_flush_register_windows (void)
3150 mono_arch_fixup_jinfo (MonoCompile *cfg)
3152 /* max encoded stack usage is 64KB * 4 */
3153 g_assert ((cfg->stack_usage & ~(0xffff << 2)) == 0);
3154 cfg->jit_info->used_regs |= cfg->stack_usage << 14;