2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
27 #include "debugger-agent.h"
29 #include "mono/arch/arm/arm-vfp-codegen.h"
31 /* Sanity check: This makes no sense */
32 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
33 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
37 * IS_SOFT_FLOAT: Is full software floating point used?
38 * IS_HARD_FLOAT: Is full hardware floating point used?
39 * IS_VFP: Is hardware floating point with software ABI used?
41 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
42 * IS_VFP may delegate to mono_arch_is_soft_float ().
45 #if defined(ARM_FPU_VFP_HARD)
46 #define IS_SOFT_FLOAT (FALSE)
47 #define IS_HARD_FLOAT (TRUE)
49 #elif defined(ARM_FPU_NONE)
50 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
51 #define IS_HARD_FLOAT (FALSE)
52 #define IS_VFP (!mono_arch_is_soft_float ())
54 #define IS_SOFT_FLOAT (FALSE)
55 #define IS_HARD_FLOAT (FALSE)
59 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(__native_client__)
60 #define HAVE_AEABI_READ_TP 1
63 #ifdef __native_client_codegen__
64 const guint kNaClAlignment = kNaClAlignmentARM;
65 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
66 gint8 nacl_align_byte = -1; /* 0xff */
69 mono_arch_nacl_pad (guint8 *code, int pad)
71 /* Not yet properly implemented. */
72 g_assert_not_reached ();
77 mono_arch_nacl_skip_nops (guint8 *code)
79 /* Not yet properly implemented. */
80 g_assert_not_reached ();
84 #endif /* __native_client_codegen__ */
86 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
89 void sys_icache_invalidate (void *start, size_t len);
92 /* This mutex protects architecture specific caches */
93 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
94 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
95 static mono_mutex_t mini_arch_mutex;
97 static gboolean v5_supported = FALSE;
98 static gboolean v6_supported = FALSE;
99 static gboolean v7_supported = FALSE;
100 static gboolean v7s_supported = FALSE;
101 static gboolean thumb_supported = FALSE;
102 static gboolean thumb2_supported = FALSE;
104 * Whenever to use the ARM EABI
106 static gboolean eabi_supported = FALSE;
109 * Whenever to use the iphone ABI extensions:
110 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
111 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
112 * This is required for debugging/profiling tools to work, but it has some overhead so it should
113 * only be turned on in debug builds.
115 static gboolean iphone_abi = FALSE;
118 * The FPU we are generating code for. This is NOT runtime configurable right now,
119 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
121 static MonoArmFPU arm_fpu;
123 #if defined(ARM_FPU_VFP_HARD)
125 * On armhf, d0-d7 are used for argument passing and d8-d15
126 * must be preserved across calls, which leaves us no room
127 * for scratch registers. So we use d14-d15 but back up their
128 * previous contents to a stack slot before using them - see
129 * mono_arm_emit_vfp_scratch_save/_restore ().
131 static int vfp_scratch1 = ARM_VFP_D14;
132 static int vfp_scratch2 = ARM_VFP_D15;
135 * On armel, d0-d7 do not need to be preserved, so we can
136 * freely make use of them as scratch registers.
138 static int vfp_scratch1 = ARM_VFP_D0;
139 static int vfp_scratch2 = ARM_VFP_D1;
144 static volatile int ss_trigger_var = 0;
146 static gpointer single_step_func_wrapper;
147 static gpointer breakpoint_func_wrapper;
150 * The code generated for sequence points reads from this location, which is
151 * made read-only when single stepping is enabled.
153 static gpointer ss_trigger_page;
155 /* Enabled breakpoints read from this trigger page */
156 static gpointer bp_trigger_page;
160 * floating point support: on ARM it is a mess, there are at least 3
161 * different setups, each of which binary incompat with the other.
162 * 1) FPA: old and ugly, but unfortunately what current distros use
163 * the double binary format has the two words swapped. 8 double registers.
164 * Implemented usually by kernel emulation.
165 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
166 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
167 * 3) VFP: the new and actually sensible and useful FP support. Implemented
168 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
170 * We do not care about FPA. We will support soft float and VFP.
172 int mono_exc_esp_offset = 0;
174 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
175 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
176 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
178 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
179 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
180 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
182 //#define DEBUG_IMT 0
185 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
189 mono_arch_regname (int reg)
191 static const char * rnames[] = {
192 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
193 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
194 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
197 if (reg >= 0 && reg < 16)
203 mono_arch_fregname (int reg)
205 static const char * rnames[] = {
206 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
207 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
208 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
209 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
210 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
211 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
214 if (reg >= 0 && reg < 32)
222 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
224 int imm8, rot_amount;
225 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
226 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
230 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
231 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
233 code = mono_arm_emit_load_imm (code, dreg, imm);
234 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
239 /* If dreg == sreg, this clobbers IP */
241 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
243 int imm8, rot_amount;
244 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
245 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
249 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
250 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
252 code = mono_arm_emit_load_imm (code, dreg, imm);
253 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
259 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
261 /* we can use r0-r3, since this is called only for incoming args on the stack */
262 if (size > sizeof (gpointer) * 4) {
264 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
265 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
266 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
267 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
268 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
269 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
270 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
271 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
272 ARM_B_COND (code, ARMCOND_NE, 0);
273 arm_patch (code - 4, start_loop);
276 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
277 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
279 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
280 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
286 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
287 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
288 doffset = soffset = 0;
290 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
291 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
297 g_assert (size == 0);
302 emit_call_reg (guint8 *code, int reg)
305 ARM_BLX_REG (code, reg);
307 #ifdef USE_JUMP_TABLES
308 g_assert_not_reached ();
310 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
314 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
320 emit_call_seq (MonoCompile *cfg, guint8 *code)
322 #ifdef USE_JUMP_TABLES
323 code = mono_arm_patchable_bl (code, ARMCOND_AL);
325 if (cfg->method->dynamic) {
326 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
328 *(gpointer*)code = NULL;
330 code = emit_call_reg (code, ARMREG_IP);
339 mono_arm_patchable_b (guint8 *code, int cond)
341 #ifdef USE_JUMP_TABLES
344 jte = mono_jumptable_add_entry ();
345 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
346 ARM_BX_COND (code, cond, ARMREG_IP);
348 ARM_B_COND (code, cond, 0);
354 mono_arm_patchable_bl (guint8 *code, int cond)
356 #ifdef USE_JUMP_TABLES
359 jte = mono_jumptable_add_entry ();
360 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
361 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
363 ARM_BL_COND (code, cond, 0);
368 #ifdef USE_JUMP_TABLES
370 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
372 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
373 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
378 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
380 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
381 ARM_LDR_IMM (code, reg, reg, 0);
387 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
389 switch (ins->opcode) {
392 case OP_FCALL_MEMBASE:
394 MonoType *sig_ret = mini_type_get_underlying_type (NULL, ((MonoCallInst*)ins)->signature->ret);
395 if (sig_ret->type == MONO_TYPE_R4) {
397 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
399 ARM_FMSR (code, ins->dreg, ARMREG_R0);
400 ARM_CVTS (code, ins->dreg, ins->dreg);
404 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
406 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
413 case OP_RCALL_MEMBASE: {
418 sig_ret = mini_type_get_underlying_type (NULL, ((MonoCallInst*)ins)->signature->ret);
419 g_assert (sig_ret->type == MONO_TYPE_R4);
421 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
423 ARM_FMSR (code, ins->dreg, ARMREG_R0);
424 ARM_CPYS (code, ins->dreg, ins->dreg);
438 * Emit code to push an LMF structure on the LMF stack.
439 * On arm, this is intermixed with the initialization of other fields of the structure.
442 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
444 gboolean get_lmf_fast = FALSE;
447 #ifdef HAVE_AEABI_READ_TP
448 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
450 if (lmf_addr_tls_offset != -1) {
453 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
454 (gpointer)"__aeabi_read_tp");
455 code = emit_call_seq (cfg, code);
457 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
463 if (cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) {
466 /* Inline mono_get_lmf_addr () */
467 /* jit_tls = pthread_getspecific (mono_jit_tls_id); lmf_addr = &jit_tls->lmf; */
469 /* Load mono_jit_tls_id */
471 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_TLS_ID, NULL);
472 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
474 *(gpointer*)code = NULL;
476 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
477 /* call pthread_getspecific () */
478 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
479 (gpointer)"pthread_getspecific");
480 code = emit_call_seq (cfg, code);
481 /* lmf_addr = &jit_tls->lmf */
482 lmf_offset = MONO_STRUCT_OFFSET (MonoJitTlsData, lmf);
483 g_assert (arm_is_imm8 (lmf_offset));
484 ARM_ADD_REG_IMM (code, ARMREG_R0, ARMREG_R0, lmf_offset, 0);
491 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
492 (gpointer)"mono_get_lmf_addr");
493 code = emit_call_seq (cfg, code);
495 /* we build the MonoLMF structure on the stack - see mini-arm.h */
496 /* lmf_offset is the offset from the previous stack pointer,
497 * alloc_size is the total stack space allocated, so the offset
498 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
499 * The pointer to the struct is put in r1 (new_lmf).
500 * ip is used as scratch
501 * The callee-saved registers are already in the MonoLMF structure
503 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
504 /* r0 is the result from mono_get_lmf_addr () */
505 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
506 /* new_lmf->previous_lmf = *lmf_addr */
507 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
508 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
509 /* *(lmf_addr) = r1 */
510 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
511 /* Skip method (only needed for trampoline LMF frames) */
512 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
513 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
514 /* save the current IP */
515 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
516 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
518 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
519 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
530 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
534 g_assert (!cfg->r4fp);
536 for (list = inst->float_args; list; list = list->next) {
537 FloatArgData *fad = list->data;
538 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
539 gboolean imm = arm_is_fpimm8 (var->inst_offset);
541 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
547 if (*offset + *max_len > cfg->code_size) {
548 cfg->code_size += *max_len;
549 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
551 code = cfg->native_code + *offset;
555 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
556 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
558 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
560 *offset = code - cfg->native_code;
567 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
571 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
573 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
576 if (!arm_is_fpimm8 (inst->inst_offset)) {
577 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
578 ARM_FSTD (code, reg, ARMREG_LR, 0);
580 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
587 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
591 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
593 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
596 if (!arm_is_fpimm8 (inst->inst_offset)) {
597 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
598 ARM_FLDD (code, reg, ARMREG_LR, 0);
600 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
609 * Emit code to pop an LMF structure from the LMF stack.
612 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
616 if (lmf_offset < 32) {
617 basereg = cfg->frame_reg;
622 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
625 /* ip = previous_lmf */
626 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
628 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
629 /* *(lmf_addr) = previous_lmf */
630 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
635 #endif /* #ifndef DISABLE_JIT */
638 * mono_arch_get_argument_info:
639 * @csig: a method signature
640 * @param_count: the number of parameters to consider
641 * @arg_info: an array to store the result infos
643 * Gathers information on parameters such as size, alignment and
644 * padding. arg_info should be large enought to hold param_count + 1 entries.
646 * Returns the size of the activation frame.
649 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
651 int k, frame_size = 0;
652 guint32 size, align, pad;
656 t = mini_type_get_underlying_type (gsctx, csig->ret);
657 if (MONO_TYPE_ISSTRUCT (t)) {
658 frame_size += sizeof (gpointer);
662 arg_info [0].offset = offset;
665 frame_size += sizeof (gpointer);
669 arg_info [0].size = frame_size;
671 for (k = 0; k < param_count; k++) {
672 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
674 /* ignore alignment for now */
677 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
678 arg_info [k].pad = pad;
680 arg_info [k + 1].pad = 0;
681 arg_info [k + 1].size = size;
683 arg_info [k + 1].offset = offset;
687 align = MONO_ARCH_FRAME_ALIGNMENT;
688 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
689 arg_info [k].pad = pad;
694 #define MAX_ARCH_DELEGATE_PARAMS 3
697 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
699 guint8 *code, *start;
702 start = code = mono_global_codeman_reserve (12);
704 /* Replace the this argument with the target */
705 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
706 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
707 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
709 g_assert ((code - start) <= 12);
711 mono_arch_flush_icache (start, 12);
715 size = 8 + param_count * 4;
716 start = code = mono_global_codeman_reserve (size);
718 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
719 /* slide down the arguments */
720 for (i = 0; i < param_count; ++i) {
721 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
723 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
725 g_assert ((code - start) <= size);
727 mono_arch_flush_icache (start, size);
730 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
732 *code_size = code - start;
738 * mono_arch_get_delegate_invoke_impls:
740 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
744 mono_arch_get_delegate_invoke_impls (void)
752 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
753 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
755 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
756 code = get_delegate_invoke_impl (FALSE, i, &code_len);
757 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
758 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
766 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
768 guint8 *code, *start;
771 /* FIXME: Support more cases */
772 sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
773 if (MONO_TYPE_ISSTRUCT (sig_ret))
777 static guint8* cached = NULL;
778 mono_mini_arch_lock ();
780 mono_mini_arch_unlock ();
785 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
787 start = get_delegate_invoke_impl (TRUE, 0, NULL);
789 mono_mini_arch_unlock ();
792 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
795 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
797 for (i = 0; i < sig->param_count; ++i)
798 if (!mono_is_regsize_var (sig->params [i]))
801 mono_mini_arch_lock ();
802 code = cache [sig->param_count];
804 mono_mini_arch_unlock ();
809 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
810 start = mono_aot_get_trampoline (name);
813 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
815 cache [sig->param_count] = start;
816 mono_mini_arch_unlock ();
824 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
830 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
832 return (gpointer)regs [ARMREG_R0];
836 * Initialize the cpu to execute managed code.
839 mono_arch_cpu_init (void)
841 i8_align = MONO_ABI_ALIGNOF (gint64);
842 #ifdef MONO_CROSS_COMPILE
843 /* Need to set the alignment of i8 since it can different on the target */
844 #ifdef TARGET_ANDROID
846 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
852 create_function_wrapper (gpointer function)
854 guint8 *start, *code;
856 start = code = mono_global_codeman_reserve (96);
859 * Construct the MonoContext structure on the stack.
862 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, sizeof (MonoContext));
864 /* save ip, lr and pc into their correspodings ctx.regs slots. */
865 ARM_STR_IMM (code, ARMREG_IP, ARMREG_SP, MONO_STRUCT_OFFSET (MonoContext, regs) + sizeof (mgreg_t) * ARMREG_IP);
866 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, MONO_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
867 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, MONO_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
869 /* save r0..r10 and fp */
870 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_SP, MONO_STRUCT_OFFSET (MonoContext, regs));
871 ARM_STM (code, ARMREG_IP, 0x0fff);
873 /* now we can update fp. */
874 ARM_MOV_REG_REG (code, ARMREG_FP, ARMREG_SP);
876 /* make ctx.esp hold the actual value of sp at the beginning of this method. */
877 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_FP, sizeof (MonoContext));
878 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, 4 * ARMREG_SP);
879 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, MONO_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_SP);
881 /* make ctx.eip hold the address of the call. */
882 ARM_SUB_REG_IMM8 (code, ARMREG_LR, ARMREG_LR, 4);
883 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, MONO_STRUCT_OFFSET (MonoContext, pc));
885 /* r0 now points to the MonoContext */
886 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_FP);
889 #ifdef USE_JUMP_TABLES
891 gpointer *jte = mono_jumptable_add_entry ();
892 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
896 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
898 *(gpointer*)code = function;
901 ARM_BLX_REG (code, ARMREG_IP);
903 /* we're back; save ctx.eip and ctx.esp into the corresponding regs slots. */
904 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, MONO_STRUCT_OFFSET (MonoContext, pc));
905 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, MONO_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
906 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, MONO_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
908 /* make ip point to the regs array, then restore everything, including pc. */
909 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_FP, MONO_STRUCT_OFFSET (MonoContext, regs));
910 ARM_LDM (code, ARMREG_IP, 0xffff);
912 mono_arch_flush_icache (start, code - start);
913 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_HELPER, NULL);
919 * Initialize architecture specific code.
922 mono_arch_init (void)
924 const char *cpu_arch;
926 mono_mutex_init_recursive (&mini_arch_mutex);
927 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
928 if (mini_get_debug_options ()->soft_breakpoints) {
929 single_step_func_wrapper = create_function_wrapper (debugger_agent_single_step_from_context);
930 breakpoint_func_wrapper = create_function_wrapper (debugger_agent_breakpoint_from_context);
935 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
936 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
937 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
940 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
941 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
942 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
943 #if defined(ENABLE_GSHAREDVT)
944 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
947 #if defined(__ARM_EABI__)
948 eabi_supported = TRUE;
951 #if defined(ARM_FPU_VFP_HARD)
952 arm_fpu = MONO_ARM_FPU_VFP_HARD;
954 arm_fpu = MONO_ARM_FPU_VFP;
956 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
958 * If we're compiling with a soft float fallback and it
959 * turns out that no VFP unit is available, we need to
960 * switch to soft float. We don't do this for iOS, since
961 * iOS devices always have a VFP unit.
963 if (!mono_hwcap_arm_has_vfp)
964 arm_fpu = MONO_ARM_FPU_NONE;
967 * This environment variable can be useful in testing
968 * environments to make sure the soft float fallback
969 * works. Most ARM devices have VFP units these days, so
970 * normally soft float code would not be exercised much.
972 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
974 if (soft && !strncmp (soft, "1", 1))
975 arm_fpu = MONO_ARM_FPU_NONE;
979 v5_supported = mono_hwcap_arm_is_v5;
980 v6_supported = mono_hwcap_arm_is_v6;
981 v7_supported = mono_hwcap_arm_is_v7;
982 v7s_supported = mono_hwcap_arm_is_v7s;
984 #if defined(__APPLE__)
985 /* iOS is special-cased here because we don't yet
986 have a way to properly detect CPU features on it. */
987 thumb_supported = TRUE;
990 thumb_supported = mono_hwcap_arm_has_thumb;
991 thumb2_supported = mono_hwcap_arm_has_thumb2;
994 /* Format: armv(5|6|7[s])[-thumb[2]] */
995 cpu_arch = g_getenv ("MONO_CPU_ARCH");
997 /* Do this here so it overrides any detection. */
999 if (strncmp (cpu_arch, "armv", 4) == 0) {
1000 v5_supported = cpu_arch [4] >= '5';
1001 v6_supported = cpu_arch [4] >= '6';
1002 v7_supported = cpu_arch [4] >= '7';
1003 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
1006 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
1007 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
1012 * Cleanup architecture specific code.
1015 mono_arch_cleanup (void)
1020 * This function returns the optimizations supported on this cpu.
1023 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1025 /* no arm-specific optimizations yet */
1031 * This function test for all SIMD functions supported.
1033 * Returns a bitmask corresponding to all supported versions.
1037 mono_arch_cpu_enumerate_simd_versions (void)
1039 /* SIMD is currently unimplemented */
1047 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1049 if (v7s_supported) {
1063 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1065 mono_arch_is_soft_float (void)
1067 return arm_fpu == MONO_ARM_FPU_NONE;
1072 mono_arm_is_hard_float (void)
1074 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1078 is_regsize_var (MonoGenericSharingContext *gsctx, MonoType *t) {
1081 t = mini_type_get_underlying_type (gsctx, t);
1088 case MONO_TYPE_FNPTR:
1090 case MONO_TYPE_OBJECT:
1091 case MONO_TYPE_STRING:
1092 case MONO_TYPE_CLASS:
1093 case MONO_TYPE_SZARRAY:
1094 case MONO_TYPE_ARRAY:
1096 case MONO_TYPE_GENERICINST:
1097 if (!mono_type_generic_inst_is_valuetype (t))
1100 case MONO_TYPE_VALUETYPE:
1107 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1112 for (i = 0; i < cfg->num_varinfo; i++) {
1113 MonoInst *ins = cfg->varinfo [i];
1114 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1117 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1120 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1123 /* we can only allocate 32 bit values */
1124 if (is_regsize_var (cfg->generic_sharing_context, ins->inst_vtype)) {
1125 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1126 g_assert (i == vmv->idx);
1127 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1135 mono_arch_get_global_int_regs (MonoCompile *cfg)
1139 mono_arch_compute_omit_fp (cfg);
1142 * FIXME: Interface calls might go through a static rgctx trampoline which
1143 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1146 if (cfg->flags & MONO_CFG_HAS_CALLS)
1147 cfg->uses_rgctx_reg = TRUE;
1149 if (cfg->arch.omit_fp)
1150 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1151 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1152 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1153 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1155 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1156 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1158 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1159 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1160 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1161 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1162 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1163 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1169 * mono_arch_regalloc_cost:
1171 * Return the cost, in number of memory references, of the action of
1172 * allocating the variable VMV into a register during global register
1176 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1182 #endif /* #ifndef DISABLE_JIT */
1184 #ifndef __GNUC_PREREQ
1185 #define __GNUC_PREREQ(maj, min) (0)
1189 mono_arch_flush_icache (guint8 *code, gint size)
1191 #if defined(__native_client__)
1192 // For Native Client we don't have to flush i-cache here,
1193 // as it's being done by dyncode interface.
1196 #ifdef MONO_CROSS_COMPILE
1198 sys_icache_invalidate (code, size);
1199 #elif __GNUC_PREREQ(4, 3)
1200 __builtin___clear_cache (code, code + size);
1201 #elif __GNUC_PREREQ(4, 1)
1202 __clear_cache (code, code + size);
1203 #elif defined(PLATFORM_ANDROID)
1204 const int syscall = 0xf0002;
1212 : "r" (code), "r" (code + size), "r" (syscall)
1213 : "r0", "r1", "r7", "r2"
1216 __asm __volatile ("mov r0, %0\n"
1219 "swi 0x9f0002 @ sys_cacheflush"
1221 : "r" (code), "r" (code + size), "r" (0)
1222 : "r0", "r1", "r3" );
1224 #endif /* !__native_client__ */
1235 RegTypeStructByAddr,
1236 /* gsharedvt argument passed by addr in greg */
1237 RegTypeGSharedVtInReg,
1238 /* gsharedvt argument passed by addr on stack */
1239 RegTypeGSharedVtOnStack,
1244 guint16 vtsize; /* in param area */
1248 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1253 guint32 stack_usage;
1254 gboolean vtype_retaddr;
1255 /* The index of the vret arg in the argument list */
1265 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1268 if (*gr > ARMREG_R3) {
1270 ainfo->offset = *stack_size;
1271 ainfo->reg = ARMREG_SP; /* in the caller */
1272 ainfo->storage = RegTypeBase;
1275 ainfo->storage = RegTypeGeneral;
1282 split = i8_align == 4;
1287 if (*gr == ARMREG_R3 && split) {
1288 /* first word in r3 and the second on the stack */
1289 ainfo->offset = *stack_size;
1290 ainfo->reg = ARMREG_SP; /* in the caller */
1291 ainfo->storage = RegTypeBaseGen;
1293 } else if (*gr >= ARMREG_R3) {
1294 if (eabi_supported) {
1295 /* darwin aligns longs to 4 byte only */
1296 if (i8_align == 8) {
1301 ainfo->offset = *stack_size;
1302 ainfo->reg = ARMREG_SP; /* in the caller */
1303 ainfo->storage = RegTypeBase;
1306 if (eabi_supported) {
1307 if (i8_align == 8 && ((*gr) & 1))
1310 ainfo->storage = RegTypeIRegPair;
1319 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1322 * If we're calling a function like this:
1324 * void foo(float a, double b, float c)
1326 * We pass a in s0 and b in d1. That leaves us
1327 * with s1 being unused. The armhf ABI recognizes
1328 * this and requires register assignment to then
1329 * use that for the next single-precision arg,
1330 * i.e. c in this example. So float_spare either
1331 * tells us which reg to use for the next single-
1332 * precision arg, or it's -1, meaning use *fpr.
1334 * Note that even though most of the JIT speaks
1335 * double-precision, fpr represents single-
1336 * precision registers.
1338 * See parts 5.5 and 6.1.2 of the AAPCS for how
1342 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1343 ainfo->storage = RegTypeFP;
1347 * If we're passing a double-precision value
1348 * and *fpr is odd (e.g. it's s1, s3, ...)
1349 * we need to use the next even register. So
1350 * we mark the current *fpr as a spare that
1351 * can be used for the next single-precision
1355 *float_spare = *fpr;
1360 * At this point, we have an even register
1361 * so we assign that and move along.
1365 } else if (*float_spare >= 0) {
1367 * We're passing a single-precision value
1368 * and it looks like a spare single-
1369 * precision register is available. Let's
1373 ainfo->reg = *float_spare;
1377 * If we hit this branch, we're passing a
1378 * single-precision value and we can simply
1379 * use the next available register.
1387 * We've exhausted available floating point
1388 * regs, so pass the rest on the stack.
1396 ainfo->offset = *stack_size;
1397 ainfo->reg = ARMREG_SP;
1398 ainfo->storage = RegTypeBase;
1405 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
1407 guint i, gr, fpr, pstart;
1409 int n = sig->hasthis + sig->param_count;
1410 MonoType *simpletype;
1411 guint32 stack_size = 0;
1413 gboolean is_pinvoke = sig->pinvoke;
1417 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1419 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1426 t = mini_type_get_underlying_type (gsctx, sig->ret);
1427 if (MONO_TYPE_ISSTRUCT (t)) {
1430 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer)) {
1431 cinfo->ret.storage = RegTypeStructByVal;
1433 cinfo->vtype_retaddr = TRUE;
1435 } else if (!(t->type == MONO_TYPE_GENERICINST && !mono_type_generic_inst_is_valuetype (t)) && mini_is_gsharedvt_type_gsctx (gsctx, t)) {
1436 cinfo->vtype_retaddr = TRUE;
1442 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1443 * the first argument, allowing 'this' to be always passed in the first arg reg.
1444 * Also do this if the first argument is a reference type, since virtual calls
1445 * are sometimes made using calli without sig->hasthis set, like in the delegate
1448 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1450 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1452 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1456 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1457 cinfo->vret_arg_index = 1;
1461 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1465 if (cinfo->vtype_retaddr)
1466 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1469 DEBUG(printf("params: %d\n", sig->param_count));
1470 for (i = pstart; i < sig->param_count; ++i) {
1471 ArgInfo *ainfo = &cinfo->args [n];
1473 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1474 /* Prevent implicit arguments and sig_cookie from
1475 being passed in registers */
1478 /* Emit the signature cookie just before the implicit arguments */
1479 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1481 DEBUG(printf("param %d: ", i));
1482 if (sig->params [i]->byref) {
1483 DEBUG(printf("byref\n"));
1484 add_general (&gr, &stack_size, ainfo, TRUE);
1488 simpletype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1489 switch (simpletype->type) {
1490 case MONO_TYPE_BOOLEAN:
1493 cinfo->args [n].size = 1;
1494 add_general (&gr, &stack_size, ainfo, TRUE);
1497 case MONO_TYPE_CHAR:
1500 cinfo->args [n].size = 2;
1501 add_general (&gr, &stack_size, ainfo, TRUE);
1506 cinfo->args [n].size = 4;
1507 add_general (&gr, &stack_size, ainfo, TRUE);
1513 case MONO_TYPE_FNPTR:
1514 case MONO_TYPE_CLASS:
1515 case MONO_TYPE_OBJECT:
1516 case MONO_TYPE_STRING:
1517 case MONO_TYPE_SZARRAY:
1518 case MONO_TYPE_ARRAY:
1519 cinfo->args [n].size = sizeof (gpointer);
1520 add_general (&gr, &stack_size, ainfo, TRUE);
1523 case MONO_TYPE_GENERICINST:
1524 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1525 cinfo->args [n].size = sizeof (gpointer);
1526 add_general (&gr, &stack_size, ainfo, TRUE);
1530 if (mini_is_gsharedvt_type_gsctx (gsctx, simpletype)) {
1531 /* gsharedvt arguments are passed by ref */
1532 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, simpletype));
1533 add_general (&gr, &stack_size, ainfo, TRUE);
1534 switch (ainfo->storage) {
1535 case RegTypeGeneral:
1536 ainfo->storage = RegTypeGSharedVtInReg;
1539 ainfo->storage = RegTypeGSharedVtOnStack;
1542 g_assert_not_reached ();
1548 case MONO_TYPE_TYPEDBYREF:
1549 case MONO_TYPE_VALUETYPE: {
1555 if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1556 size = sizeof (MonoTypedRef);
1557 align = sizeof (gpointer);
1559 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1561 size = mono_class_native_size (klass, &align);
1563 size = mini_type_stack_size_full (gsctx, simpletype, &align, FALSE);
1565 DEBUG(printf ("load %d bytes struct\n", size));
1568 align_size += (sizeof (gpointer) - 1);
1569 align_size &= ~(sizeof (gpointer) - 1);
1570 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1571 ainfo->storage = RegTypeStructByVal;
1572 ainfo->struct_size = size;
1573 /* FIXME: align stack_size if needed */
1574 if (eabi_supported) {
1575 if (align >= 8 && (gr & 1))
1578 if (gr > ARMREG_R3) {
1580 ainfo->vtsize = nwords;
1582 int rest = ARMREG_R3 - gr + 1;
1583 int n_in_regs = rest >= nwords? nwords: rest;
1585 ainfo->size = n_in_regs;
1586 ainfo->vtsize = nwords - n_in_regs;
1589 nwords -= n_in_regs;
1591 if (sig->call_convention == MONO_CALL_VARARG)
1592 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1593 stack_size = ALIGN_TO (stack_size, align);
1594 ainfo->offset = stack_size;
1595 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1596 stack_size += nwords * sizeof (gpointer);
1603 add_general (&gr, &stack_size, ainfo, FALSE);
1610 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1612 add_general (&gr, &stack_size, ainfo, TRUE);
1620 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1622 add_general (&gr, &stack_size, ainfo, FALSE);
1627 case MONO_TYPE_MVAR:
1628 /* gsharedvt arguments are passed by ref */
1629 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, simpletype));
1630 add_general (&gr, &stack_size, ainfo, TRUE);
1631 switch (ainfo->storage) {
1632 case RegTypeGeneral:
1633 ainfo->storage = RegTypeGSharedVtInReg;
1636 ainfo->storage = RegTypeGSharedVtOnStack;
1639 g_assert_not_reached ();
1644 g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1648 /* Handle the case where there are no implicit arguments */
1649 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1650 /* Prevent implicit arguments and sig_cookie from
1651 being passed in registers */
1654 /* Emit the signature cookie just before the implicit arguments */
1655 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1659 simpletype = mini_type_get_underlying_type (gsctx, sig->ret);
1660 switch (simpletype->type) {
1661 case MONO_TYPE_BOOLEAN:
1666 case MONO_TYPE_CHAR:
1672 case MONO_TYPE_FNPTR:
1673 case MONO_TYPE_CLASS:
1674 case MONO_TYPE_OBJECT:
1675 case MONO_TYPE_SZARRAY:
1676 case MONO_TYPE_ARRAY:
1677 case MONO_TYPE_STRING:
1678 cinfo->ret.storage = RegTypeGeneral;
1679 cinfo->ret.reg = ARMREG_R0;
1683 cinfo->ret.storage = RegTypeIRegPair;
1684 cinfo->ret.reg = ARMREG_R0;
1688 cinfo->ret.storage = RegTypeFP;
1690 if (IS_HARD_FLOAT) {
1691 cinfo->ret.reg = ARM_VFP_F0;
1693 cinfo->ret.reg = ARMREG_R0;
1697 case MONO_TYPE_GENERICINST:
1698 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1699 cinfo->ret.storage = RegTypeGeneral;
1700 cinfo->ret.reg = ARMREG_R0;
1703 // FIXME: Only for variable types
1704 if (mini_is_gsharedvt_type_gsctx (gsctx, simpletype)) {
1705 cinfo->ret.storage = RegTypeStructByAddr;
1706 g_assert (cinfo->vtype_retaddr);
1710 case MONO_TYPE_VALUETYPE:
1711 case MONO_TYPE_TYPEDBYREF:
1712 if (cinfo->ret.storage != RegTypeStructByVal)
1713 cinfo->ret.storage = RegTypeStructByAddr;
1716 case MONO_TYPE_MVAR:
1717 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, simpletype));
1718 cinfo->ret.storage = RegTypeStructByAddr;
1719 g_assert (cinfo->vtype_retaddr);
1721 case MONO_TYPE_VOID:
1724 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1728 /* align stack size to 8 */
1729 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1730 stack_size = (stack_size + 7) & ~7;
1732 cinfo->stack_usage = stack_size;
1738 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1740 MonoType *callee_ret;
1744 if (cfg->compile_aot && !cfg->full_aot)
1745 /* OP_TAILCALL doesn't work with AOT */
1748 c1 = get_call_info (NULL, NULL, caller_sig);
1749 c2 = get_call_info (NULL, NULL, callee_sig);
1752 * Tail calls with more callee stack usage than the caller cannot be supported, since
1753 * the extra stack space would be left on the stack after the tail call.
1755 res = c1->stack_usage >= c2->stack_usage;
1756 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1757 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1758 /* An address on the callee's stack is passed as the first argument */
1761 if (c2->stack_usage > 16 * 4)
1773 debug_omit_fp (void)
1776 return mono_debug_count ();
1783 * mono_arch_compute_omit_fp:
1785 * Determine whenever the frame pointer can be eliminated.
1788 mono_arch_compute_omit_fp (MonoCompile *cfg)
1790 MonoMethodSignature *sig;
1791 MonoMethodHeader *header;
1795 if (cfg->arch.omit_fp_computed)
1798 header = cfg->header;
1800 sig = mono_method_signature (cfg->method);
1802 if (!cfg->arch.cinfo)
1803 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1804 cinfo = cfg->arch.cinfo;
1807 * FIXME: Remove some of the restrictions.
1809 cfg->arch.omit_fp = TRUE;
1810 cfg->arch.omit_fp_computed = TRUE;
1812 if (cfg->disable_omit_fp)
1813 cfg->arch.omit_fp = FALSE;
1814 if (!debug_omit_fp ())
1815 cfg->arch.omit_fp = FALSE;
1817 if (cfg->method->save_lmf)
1818 cfg->arch.omit_fp = FALSE;
1820 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1821 cfg->arch.omit_fp = FALSE;
1822 if (header->num_clauses)
1823 cfg->arch.omit_fp = FALSE;
1824 if (cfg->param_area)
1825 cfg->arch.omit_fp = FALSE;
1826 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1827 cfg->arch.omit_fp = FALSE;
1828 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1829 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1830 cfg->arch.omit_fp = FALSE;
1831 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1832 ArgInfo *ainfo = &cinfo->args [i];
1834 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1836 * The stack offset can only be determined when the frame
1839 cfg->arch.omit_fp = FALSE;
1844 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1845 MonoInst *ins = cfg->varinfo [i];
1848 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1853 * Set var information according to the calling convention. arm version.
1854 * The locals var stuff should most likely be split in another method.
1857 mono_arch_allocate_vars (MonoCompile *cfg)
1859 MonoMethodSignature *sig;
1860 MonoMethodHeader *header;
1863 int i, offset, size, align, curinst;
1867 sig = mono_method_signature (cfg->method);
1869 if (!cfg->arch.cinfo)
1870 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1871 cinfo = cfg->arch.cinfo;
1872 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1874 mono_arch_compute_omit_fp (cfg);
1876 if (cfg->arch.omit_fp)
1877 cfg->frame_reg = ARMREG_SP;
1879 cfg->frame_reg = ARMREG_FP;
1881 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1883 /* allow room for the vararg method args: void* and long/double */
1884 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1885 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1887 header = cfg->header;
1889 /* See mono_arch_get_global_int_regs () */
1890 if (cfg->flags & MONO_CFG_HAS_CALLS)
1891 cfg->uses_rgctx_reg = TRUE;
1893 if (cfg->frame_reg != ARMREG_SP)
1894 cfg->used_int_regs |= 1 << cfg->frame_reg;
1896 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1897 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1898 cfg->used_int_regs |= (1 << ARMREG_V5);
1902 if (!MONO_TYPE_ISSTRUCT (sig_ret) && !cinfo->vtype_retaddr) {
1903 if (sig_ret->type != MONO_TYPE_VOID) {
1904 cfg->ret->opcode = OP_REGVAR;
1905 cfg->ret->inst_c0 = ARMREG_R0;
1908 /* local vars are at a positive offset from the stack pointer */
1910 * also note that if the function uses alloca, we use FP
1911 * to point at the local variables.
1913 offset = 0; /* linkage area */
1914 /* align the offset to 16 bytes: not sure this is needed here */
1916 //offset &= ~(8 - 1);
1918 /* add parameter area size for called functions */
1919 offset += cfg->param_area;
1922 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1925 /* allow room to save the return value */
1926 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1929 /* the MonoLMF structure is stored just below the stack pointer */
1930 if (cinfo->ret.storage == RegTypeStructByVal) {
1931 cfg->ret->opcode = OP_REGOFFSET;
1932 cfg->ret->inst_basereg = cfg->frame_reg;
1933 offset += sizeof (gpointer) - 1;
1934 offset &= ~(sizeof (gpointer) - 1);
1935 cfg->ret->inst_offset = - offset;
1936 offset += sizeof(gpointer);
1937 } else if (cinfo->vtype_retaddr) {
1938 ins = cfg->vret_addr;
1939 offset += sizeof(gpointer) - 1;
1940 offset &= ~(sizeof(gpointer) - 1);
1941 ins->inst_offset = offset;
1942 ins->opcode = OP_REGOFFSET;
1943 ins->inst_basereg = cfg->frame_reg;
1944 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1945 printf ("vret_addr =");
1946 mono_print_ins (cfg->vret_addr);
1948 offset += sizeof(gpointer);
1951 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1952 if (cfg->arch.seq_point_info_var) {
1955 ins = cfg->arch.seq_point_info_var;
1959 offset += align - 1;
1960 offset &= ~(align - 1);
1961 ins->opcode = OP_REGOFFSET;
1962 ins->inst_basereg = cfg->frame_reg;
1963 ins->inst_offset = offset;
1966 ins = cfg->arch.ss_trigger_page_var;
1969 offset += align - 1;
1970 offset &= ~(align - 1);
1971 ins->opcode = OP_REGOFFSET;
1972 ins->inst_basereg = cfg->frame_reg;
1973 ins->inst_offset = offset;
1977 if (cfg->arch.seq_point_read_var) {
1980 ins = cfg->arch.seq_point_read_var;
1984 offset += align - 1;
1985 offset &= ~(align - 1);
1986 ins->opcode = OP_REGOFFSET;
1987 ins->inst_basereg = cfg->frame_reg;
1988 ins->inst_offset = offset;
1991 ins = cfg->arch.seq_point_ss_method_var;
1994 offset += align - 1;
1995 offset &= ~(align - 1);
1996 ins->opcode = OP_REGOFFSET;
1997 ins->inst_basereg = cfg->frame_reg;
1998 ins->inst_offset = offset;
2001 ins = cfg->arch.seq_point_bp_method_var;
2004 offset += align - 1;
2005 offset &= ~(align - 1);
2006 ins->opcode = OP_REGOFFSET;
2007 ins->inst_basereg = cfg->frame_reg;
2008 ins->inst_offset = offset;
2012 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
2013 /* Allocate a temporary used by the atomic ops */
2017 /* Allocate a local slot to hold the sig cookie address */
2018 offset += align - 1;
2019 offset &= ~(align - 1);
2020 cfg->arch.atomic_tmp_offset = offset;
2023 cfg->arch.atomic_tmp_offset = -1;
2026 cfg->locals_min_stack_offset = offset;
2028 curinst = cfg->locals_start;
2029 for (i = curinst; i < cfg->num_varinfo; ++i) {
2032 ins = cfg->varinfo [i];
2033 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
2036 t = ins->inst_vtype;
2037 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (cfg, t))
2040 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
2041 * pinvoke wrappers when they call functions returning structure */
2042 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2043 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
2047 size = mono_type_size (t, &align);
2049 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2050 * since it loads/stores misaligned words, which don't do the right thing.
2052 if (align < 4 && size >= 4)
2054 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2055 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2056 offset += align - 1;
2057 offset &= ~(align - 1);
2058 ins->opcode = OP_REGOFFSET;
2059 ins->inst_offset = offset;
2060 ins->inst_basereg = cfg->frame_reg;
2062 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2065 cfg->locals_max_stack_offset = offset;
2069 ins = cfg->args [curinst];
2070 if (ins->opcode != OP_REGVAR) {
2071 ins->opcode = OP_REGOFFSET;
2072 ins->inst_basereg = cfg->frame_reg;
2073 offset += sizeof (gpointer) - 1;
2074 offset &= ~(sizeof (gpointer) - 1);
2075 ins->inst_offset = offset;
2076 offset += sizeof (gpointer);
2081 if (sig->call_convention == MONO_CALL_VARARG) {
2085 /* Allocate a local slot to hold the sig cookie address */
2086 offset += align - 1;
2087 offset &= ~(align - 1);
2088 cfg->sig_cookie = offset;
2092 for (i = 0; i < sig->param_count; ++i) {
2093 ins = cfg->args [curinst];
2095 if (ins->opcode != OP_REGVAR) {
2096 ins->opcode = OP_REGOFFSET;
2097 ins->inst_basereg = cfg->frame_reg;
2098 size = mini_type_stack_size_full (cfg->generic_sharing_context, sig->params [i], &ualign, sig->pinvoke);
2100 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2101 * since it loads/stores misaligned words, which don't do the right thing.
2103 if (align < 4 && size >= 4)
2105 /* The code in the prolog () stores words when storing vtypes received in a register */
2106 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2108 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2109 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2110 offset += align - 1;
2111 offset &= ~(align - 1);
2112 ins->inst_offset = offset;
2118 /* align the offset to 8 bytes */
2119 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2120 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2125 cfg->stack_offset = offset;
2129 mono_arch_create_vars (MonoCompile *cfg)
2131 MonoMethodSignature *sig;
2135 sig = mono_method_signature (cfg->method);
2137 if (!cfg->arch.cinfo)
2138 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2139 cinfo = cfg->arch.cinfo;
2141 if (IS_HARD_FLOAT) {
2142 for (i = 0; i < 2; i++) {
2143 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2144 inst->flags |= MONO_INST_VOLATILE;
2146 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2150 if (cinfo->ret.storage == RegTypeStructByVal)
2151 cfg->ret_var_is_local = TRUE;
2153 if (cinfo->vtype_retaddr) {
2154 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2155 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2156 printf ("vret_addr = ");
2157 mono_print_ins (cfg->vret_addr);
2161 if (cfg->gen_seq_points_debug_data) {
2162 if (cfg->soft_breakpoints) {
2163 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2164 ins->flags |= MONO_INST_VOLATILE;
2165 cfg->arch.seq_point_read_var = ins;
2167 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2168 ins->flags |= MONO_INST_VOLATILE;
2169 cfg->arch.seq_point_ss_method_var = ins;
2171 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2172 ins->flags |= MONO_INST_VOLATILE;
2173 cfg->arch.seq_point_bp_method_var = ins;
2175 g_assert (!cfg->compile_aot);
2176 } else if (cfg->compile_aot) {
2177 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2178 ins->flags |= MONO_INST_VOLATILE;
2179 cfg->arch.seq_point_info_var = ins;
2181 /* Allocate a separate variable for this to save 1 load per seq point */
2182 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2183 ins->flags |= MONO_INST_VOLATILE;
2184 cfg->arch.ss_trigger_page_var = ins;
2190 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2192 MonoMethodSignature *tmp_sig;
2195 if (call->tail_call)
2198 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2201 * mono_ArgIterator_Setup assumes the signature cookie is
2202 * passed first and all the arguments which were before it are
2203 * passed on the stack after the signature. So compensate by
2204 * passing a different signature.
2206 tmp_sig = mono_metadata_signature_dup (call->signature);
2207 tmp_sig->param_count -= call->signature->sentinelpos;
2208 tmp_sig->sentinelpos = 0;
2209 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2211 sig_reg = mono_alloc_ireg (cfg);
2212 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2214 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2219 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2224 LLVMCallInfo *linfo;
2226 n = sig->param_count + sig->hasthis;
2228 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2230 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2233 * LLVM always uses the native ABI while we use our own ABI, the
2234 * only difference is the handling of vtypes:
2235 * - we only pass/receive them in registers in some cases, and only
2236 * in 1 or 2 integer registers.
2238 if (cinfo->vtype_retaddr) {
2239 /* Vtype returned using a hidden argument */
2240 linfo->ret.storage = LLVMArgVtypeRetAddr;
2241 linfo->vret_arg_index = cinfo->vret_arg_index;
2242 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
2243 cfg->exception_message = g_strdup ("unknown ret conv");
2244 cfg->disable_llvm = TRUE;
2248 for (i = 0; i < n; ++i) {
2249 ainfo = cinfo->args + i;
2251 linfo->args [i].storage = LLVMArgNone;
2253 switch (ainfo->storage) {
2254 case RegTypeGeneral:
2255 case RegTypeIRegPair:
2257 linfo->args [i].storage = LLVMArgInIReg;
2259 case RegTypeStructByVal:
2260 linfo->args [i].storage = LLVMArgAsIArgs;
2261 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2264 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2265 cfg->disable_llvm = TRUE;
2275 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2278 MonoMethodSignature *sig;
2282 sig = call->signature;
2283 n = sig->param_count + sig->hasthis;
2285 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
2287 for (i = 0; i < n; ++i) {
2288 ArgInfo *ainfo = cinfo->args + i;
2291 if (i >= sig->hasthis)
2292 t = sig->params [i - sig->hasthis];
2294 t = &mono_defaults.int_class->byval_arg;
2295 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
2297 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2298 /* Emit the signature cookie just before the implicit arguments */
2299 emit_sig_cookie (cfg, call, cinfo);
2302 in = call->args [i];
2304 switch (ainfo->storage) {
2305 case RegTypeGeneral:
2306 case RegTypeIRegPair:
2307 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2308 MONO_INST_NEW (cfg, ins, OP_MOVE);
2309 ins->dreg = mono_alloc_ireg (cfg);
2310 ins->sreg1 = in->dreg + 1;
2311 MONO_ADD_INS (cfg->cbb, ins);
2312 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2314 MONO_INST_NEW (cfg, ins, OP_MOVE);
2315 ins->dreg = mono_alloc_ireg (cfg);
2316 ins->sreg1 = in->dreg + 2;
2317 MONO_ADD_INS (cfg->cbb, ins);
2318 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2319 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2320 if (ainfo->size == 4) {
2321 if (IS_SOFT_FLOAT) {
2322 /* mono_emit_call_args () have already done the r8->r4 conversion */
2323 /* The converted value is in an int vreg */
2324 MONO_INST_NEW (cfg, ins, OP_MOVE);
2325 ins->dreg = mono_alloc_ireg (cfg);
2326 ins->sreg1 = in->dreg;
2327 MONO_ADD_INS (cfg->cbb, ins);
2328 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2332 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2333 creg = mono_alloc_ireg (cfg);
2334 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2335 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2338 if (IS_SOFT_FLOAT) {
2339 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2340 ins->dreg = mono_alloc_ireg (cfg);
2341 ins->sreg1 = in->dreg;
2342 MONO_ADD_INS (cfg->cbb, ins);
2343 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2345 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2346 ins->dreg = mono_alloc_ireg (cfg);
2347 ins->sreg1 = in->dreg;
2348 MONO_ADD_INS (cfg->cbb, ins);
2349 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2353 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2354 creg = mono_alloc_ireg (cfg);
2355 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2356 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2357 creg = mono_alloc_ireg (cfg);
2358 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2359 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2362 cfg->flags |= MONO_CFG_HAS_FPOUT;
2364 MONO_INST_NEW (cfg, ins, OP_MOVE);
2365 ins->dreg = mono_alloc_ireg (cfg);
2366 ins->sreg1 = in->dreg;
2367 MONO_ADD_INS (cfg->cbb, ins);
2369 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2372 case RegTypeStructByAddr:
2375 /* FIXME: where si the data allocated? */
2376 arg->backend.reg3 = ainfo->reg;
2377 call->used_iregs |= 1 << ainfo->reg;
2378 g_assert_not_reached ();
2381 case RegTypeStructByVal:
2382 case RegTypeGSharedVtInReg:
2383 case RegTypeGSharedVtOnStack:
2384 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2385 ins->opcode = OP_OUTARG_VT;
2386 ins->sreg1 = in->dreg;
2387 ins->klass = in->klass;
2388 ins->inst_p0 = call;
2389 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2390 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2391 mono_call_inst_add_outarg_vt (cfg, call, ins);
2392 MONO_ADD_INS (cfg->cbb, ins);
2395 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2396 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2397 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2398 if (t->type == MONO_TYPE_R8) {
2399 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2402 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2404 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2407 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2410 case RegTypeBaseGen:
2411 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2412 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
2413 MONO_INST_NEW (cfg, ins, OP_MOVE);
2414 ins->dreg = mono_alloc_ireg (cfg);
2415 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
2416 MONO_ADD_INS (cfg->cbb, ins);
2417 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2418 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2421 /* This should work for soft-float as well */
2423 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2424 creg = mono_alloc_ireg (cfg);
2425 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2426 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2427 creg = mono_alloc_ireg (cfg);
2428 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2429 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2430 cfg->flags |= MONO_CFG_HAS_FPOUT;
2432 g_assert_not_reached ();
2436 int fdreg = mono_alloc_freg (cfg);
2438 if (ainfo->size == 8) {
2439 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2440 ins->sreg1 = in->dreg;
2442 MONO_ADD_INS (cfg->cbb, ins);
2444 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2449 * Mono's register allocator doesn't speak single-precision registers that
2450 * overlap double-precision registers (i.e. armhf). So we have to work around
2451 * the register allocator and load the value from memory manually.
2453 * So we create a variable for the float argument and an instruction to store
2454 * the argument into the variable. We then store the list of these arguments
2455 * in cfg->float_args. This list is then used by emit_float_args later to
2456 * pass the arguments in the various call opcodes.
2458 * This is not very nice, and we should really try to fix the allocator.
2461 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2463 /* Make sure the instruction isn't seen as pointless and removed.
2465 float_arg->flags |= MONO_INST_VOLATILE;
2467 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2469 /* We use the dreg to look up the instruction later. The hreg is used to
2470 * emit the instruction that loads the value into the FP reg.
2472 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2473 fad->vreg = float_arg->dreg;
2474 fad->hreg = ainfo->reg;
2476 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2479 call->used_iregs |= 1 << ainfo->reg;
2480 cfg->flags |= MONO_CFG_HAS_FPOUT;
2484 g_assert_not_reached ();
2488 /* Handle the case where there are no implicit arguments */
2489 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2490 emit_sig_cookie (cfg, call, cinfo);
2492 if (cinfo->ret.storage == RegTypeStructByVal) {
2493 /* The JIT will transform this into a normal call */
2494 call->vret_in_reg = TRUE;
2495 } else if (cinfo->vtype_retaddr) {
2497 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2498 vtarg->sreg1 = call->vret_var->dreg;
2499 vtarg->dreg = mono_alloc_preg (cfg);
2500 MONO_ADD_INS (cfg->cbb, vtarg);
2502 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2505 call->stack_usage = cinfo->stack_usage;
2511 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2513 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2514 ArgInfo *ainfo = ins->inst_p1;
2515 int ovf_size = ainfo->vtsize;
2516 int doffset = ainfo->offset;
2517 int struct_size = ainfo->struct_size;
2518 int i, soffset, dreg, tmpreg;
2520 if (ainfo->storage == RegTypeGSharedVtInReg) {
2522 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2525 if (ainfo->storage == RegTypeGSharedVtOnStack) {
2526 /* Pass by addr on stack */
2527 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2532 for (i = 0; i < ainfo->size; ++i) {
2533 dreg = mono_alloc_ireg (cfg);
2534 switch (struct_size) {
2536 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2539 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2542 tmpreg = mono_alloc_ireg (cfg);
2543 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2544 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2545 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2546 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2547 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2548 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2549 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2552 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2555 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2556 soffset += sizeof (gpointer);
2557 struct_size -= sizeof (gpointer);
2559 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2561 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2565 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2567 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2570 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2573 if (COMPILE_LLVM (cfg)) {
2574 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2576 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2577 ins->sreg1 = val->dreg + 1;
2578 ins->sreg2 = val->dreg + 2;
2579 MONO_ADD_INS (cfg->cbb, ins);
2584 case MONO_ARM_FPU_NONE:
2585 if (ret->type == MONO_TYPE_R8) {
2588 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2589 ins->dreg = cfg->ret->dreg;
2590 ins->sreg1 = val->dreg;
2591 MONO_ADD_INS (cfg->cbb, ins);
2594 if (ret->type == MONO_TYPE_R4) {
2595 /* Already converted to an int in method_to_ir () */
2596 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2600 case MONO_ARM_FPU_VFP:
2601 case MONO_ARM_FPU_VFP_HARD:
2602 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2605 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2606 ins->dreg = cfg->ret->dreg;
2607 ins->sreg1 = val->dreg;
2608 MONO_ADD_INS (cfg->cbb, ins);
2613 g_assert_not_reached ();
2617 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2620 #endif /* #ifndef DISABLE_JIT */
2623 mono_arch_is_inst_imm (gint64 imm)
2629 MonoMethodSignature *sig;
2632 MonoType **param_types;
2636 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2640 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2643 switch (cinfo->ret.storage) {
2645 case RegTypeGeneral:
2646 case RegTypeIRegPair:
2647 case RegTypeStructByAddr:
2658 for (i = 0; i < cinfo->nargs; ++i) {
2659 ArgInfo *ainfo = &cinfo->args [i];
2662 switch (ainfo->storage) {
2663 case RegTypeGeneral:
2665 case RegTypeIRegPair:
2668 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2671 case RegTypeStructByVal:
2672 if (ainfo->size == 0)
2673 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2675 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2676 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2684 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2685 for (i = 0; i < sig->param_count; ++i) {
2686 MonoType *t = sig->params [i];
2691 t = mini_replace_type (t);
2714 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2716 ArchDynCallInfo *info;
2720 cinfo = get_call_info (NULL, NULL, sig);
2722 if (!dyn_call_supported (cinfo, sig)) {
2727 info = g_new0 (ArchDynCallInfo, 1);
2728 // FIXME: Preprocess the info to speed up start_dyn_call ()
2730 info->cinfo = cinfo;
2731 info->rtype = mini_replace_type (sig->ret);
2732 info->param_types = g_new0 (MonoType*, sig->param_count);
2733 for (i = 0; i < sig->param_count; ++i)
2734 info->param_types [i] = mini_replace_type (sig->params [i]);
2736 return (MonoDynCallInfo*)info;
2740 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2742 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2744 g_free (ainfo->cinfo);
2749 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2751 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2752 DynCallArgs *p = (DynCallArgs*)buf;
2753 int arg_index, greg, i, j, pindex;
2754 MonoMethodSignature *sig = dinfo->sig;
2756 g_assert (buf_len >= sizeof (DynCallArgs));
2765 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2766 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2771 if (dinfo->cinfo->vtype_retaddr)
2772 p->regs [greg ++] = (mgreg_t)ret;
2774 for (i = pindex; i < sig->param_count; i++) {
2775 MonoType *t = dinfo->param_types [i];
2776 gpointer *arg = args [arg_index ++];
2777 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2780 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2782 else if (ainfo->storage == RegTypeBase)
2783 slot = PARAM_REGS + (ainfo->offset / 4);
2785 g_assert_not_reached ();
2788 p->regs [slot] = (mgreg_t)*arg;
2793 case MONO_TYPE_STRING:
2794 case MONO_TYPE_CLASS:
2795 case MONO_TYPE_ARRAY:
2796 case MONO_TYPE_SZARRAY:
2797 case MONO_TYPE_OBJECT:
2801 p->regs [slot] = (mgreg_t)*arg;
2803 case MONO_TYPE_BOOLEAN:
2805 p->regs [slot] = *(guint8*)arg;
2808 p->regs [slot] = *(gint8*)arg;
2811 p->regs [slot] = *(gint16*)arg;
2814 case MONO_TYPE_CHAR:
2815 p->regs [slot] = *(guint16*)arg;
2818 p->regs [slot] = *(gint32*)arg;
2821 p->regs [slot] = *(guint32*)arg;
2825 p->regs [slot ++] = (mgreg_t)arg [0];
2826 p->regs [slot] = (mgreg_t)arg [1];
2829 p->regs [slot] = *(mgreg_t*)arg;
2832 p->regs [slot ++] = (mgreg_t)arg [0];
2833 p->regs [slot] = (mgreg_t)arg [1];
2835 case MONO_TYPE_GENERICINST:
2836 if (MONO_TYPE_IS_REFERENCE (t)) {
2837 p->regs [slot] = (mgreg_t)*arg;
2842 case MONO_TYPE_VALUETYPE:
2843 g_assert (ainfo->storage == RegTypeStructByVal);
2845 if (ainfo->size == 0)
2846 slot = PARAM_REGS + (ainfo->offset / 4);
2850 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2851 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2854 g_assert_not_reached ();
2860 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2862 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2863 MonoType *ptype = ainfo->rtype;
2864 guint8 *ret = ((DynCallArgs*)buf)->ret;
2865 mgreg_t res = ((DynCallArgs*)buf)->res;
2866 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2868 switch (ptype->type) {
2869 case MONO_TYPE_VOID:
2870 *(gpointer*)ret = NULL;
2872 case MONO_TYPE_STRING:
2873 case MONO_TYPE_CLASS:
2874 case MONO_TYPE_ARRAY:
2875 case MONO_TYPE_SZARRAY:
2876 case MONO_TYPE_OBJECT:
2880 *(gpointer*)ret = (gpointer)res;
2886 case MONO_TYPE_BOOLEAN:
2887 *(guint8*)ret = res;
2890 *(gint16*)ret = res;
2893 case MONO_TYPE_CHAR:
2894 *(guint16*)ret = res;
2897 *(gint32*)ret = res;
2900 *(guint32*)ret = res;
2904 /* This handles endianness as well */
2905 ((gint32*)ret) [0] = res;
2906 ((gint32*)ret) [1] = res2;
2908 case MONO_TYPE_GENERICINST:
2909 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2910 *(gpointer*)ret = (gpointer)res;
2915 case MONO_TYPE_VALUETYPE:
2916 g_assert (ainfo->cinfo->vtype_retaddr);
2921 *(float*)ret = *(float*)&res;
2923 case MONO_TYPE_R8: {
2930 *(double*)ret = *(double*)®s;
2934 g_assert_not_reached ();
2941 * Allow tracing to work with this interface (with an optional argument)
2945 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2949 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2950 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2951 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2952 code = emit_call_reg (code, ARMREG_R2);
2966 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2969 int save_mode = SAVE_NONE;
2971 MonoMethod *method = cfg->method;
2972 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2973 int rtype = ret_type->type;
2974 int save_offset = cfg->param_area;
2978 offset = code - cfg->native_code;
2979 /* we need about 16 instructions */
2980 if (offset > (cfg->code_size - 16 * 4)) {
2981 cfg->code_size *= 2;
2982 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2983 code = cfg->native_code + offset;
2986 case MONO_TYPE_VOID:
2987 /* special case string .ctor icall */
2988 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2989 save_mode = SAVE_ONE;
2991 save_mode = SAVE_NONE;
2995 save_mode = SAVE_TWO;
2999 save_mode = SAVE_ONE_FP;
3001 save_mode = SAVE_ONE;
3005 save_mode = SAVE_TWO_FP;
3007 save_mode = SAVE_TWO;
3009 case MONO_TYPE_GENERICINST:
3010 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3011 save_mode = SAVE_ONE;
3015 case MONO_TYPE_VALUETYPE:
3016 save_mode = SAVE_STRUCT;
3019 save_mode = SAVE_ONE;
3023 switch (save_mode) {
3025 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3026 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3027 if (enable_arguments) {
3028 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3029 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3033 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3034 if (enable_arguments) {
3035 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3039 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3040 if (enable_arguments) {
3041 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3045 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3046 if (enable_arguments) {
3047 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3051 if (enable_arguments) {
3052 /* FIXME: get the actual address */
3053 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3061 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3062 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3063 code = emit_call_reg (code, ARMREG_IP);
3065 switch (save_mode) {
3067 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3068 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3071 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3074 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3077 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3088 * The immediate field for cond branches is big enough for all reasonable methods
3090 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3091 if (0 && ins->inst_true_bb->native_offset) { \
3092 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3094 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3095 ARM_B_COND (code, (condcode), 0); \
3098 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3100 /* emit an exception if condition is fail
3102 * We assign the extra code used to throw the implicit exceptions
3103 * to cfg->bb_exit as far as the big branch handling is concerned
3105 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3107 mono_add_patch_info (cfg, code - cfg->native_code, \
3108 MONO_PATCH_INFO_EXC, exc_name); \
3109 ARM_BL_COND (code, (condcode), 0); \
3112 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3115 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3120 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3122 MonoInst *ins, *n, *last_ins = NULL;
3124 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3125 switch (ins->opcode) {
3128 /* Already done by an arch-independent pass */
3130 case OP_LOAD_MEMBASE:
3131 case OP_LOADI4_MEMBASE:
3133 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3134 * OP_LOAD_MEMBASE offset(basereg), reg
3136 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3137 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3138 ins->inst_basereg == last_ins->inst_destbasereg &&
3139 ins->inst_offset == last_ins->inst_offset) {
3140 if (ins->dreg == last_ins->sreg1) {
3141 MONO_DELETE_INS (bb, ins);
3144 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3145 ins->opcode = OP_MOVE;
3146 ins->sreg1 = last_ins->sreg1;
3150 * Note: reg1 must be different from the basereg in the second load
3151 * OP_LOAD_MEMBASE offset(basereg), reg1
3152 * OP_LOAD_MEMBASE offset(basereg), reg2
3154 * OP_LOAD_MEMBASE offset(basereg), reg1
3155 * OP_MOVE reg1, reg2
3157 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3158 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3159 ins->inst_basereg != last_ins->dreg &&
3160 ins->inst_basereg == last_ins->inst_basereg &&
3161 ins->inst_offset == last_ins->inst_offset) {
3163 if (ins->dreg == last_ins->dreg) {
3164 MONO_DELETE_INS (bb, ins);
3167 ins->opcode = OP_MOVE;
3168 ins->sreg1 = last_ins->dreg;
3171 //g_assert_not_reached ();
3175 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3176 * OP_LOAD_MEMBASE offset(basereg), reg
3178 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3179 * OP_ICONST reg, imm
3181 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3182 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3183 ins->inst_basereg == last_ins->inst_destbasereg &&
3184 ins->inst_offset == last_ins->inst_offset) {
3185 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3186 ins->opcode = OP_ICONST;
3187 ins->inst_c0 = last_ins->inst_imm;
3188 g_assert_not_reached (); // check this rule
3192 case OP_LOADU1_MEMBASE:
3193 case OP_LOADI1_MEMBASE:
3194 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3195 ins->inst_basereg == last_ins->inst_destbasereg &&
3196 ins->inst_offset == last_ins->inst_offset) {
3197 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3198 ins->sreg1 = last_ins->sreg1;
3201 case OP_LOADU2_MEMBASE:
3202 case OP_LOADI2_MEMBASE:
3203 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3204 ins->inst_basereg == last_ins->inst_destbasereg &&
3205 ins->inst_offset == last_ins->inst_offset) {
3206 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3207 ins->sreg1 = last_ins->sreg1;
3211 ins->opcode = OP_MOVE;
3215 if (ins->dreg == ins->sreg1) {
3216 MONO_DELETE_INS (bb, ins);
3220 * OP_MOVE sreg, dreg
3221 * OP_MOVE dreg, sreg
3223 if (last_ins && last_ins->opcode == OP_MOVE &&
3224 ins->sreg1 == last_ins->dreg &&
3225 ins->dreg == last_ins->sreg1) {
3226 MONO_DELETE_INS (bb, ins);
3234 bb->last_ins = last_ins;
3238 * the branch_cc_table should maintain the order of these
3252 branch_cc_table [] = {
3266 #define ADD_NEW_INS(cfg,dest,op) do { \
3267 MONO_INST_NEW ((cfg), (dest), (op)); \
3268 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3272 map_to_reg_reg_op (int op)
3281 case OP_COMPARE_IMM:
3283 case OP_ICOMPARE_IMM:
3297 case OP_LOAD_MEMBASE:
3298 return OP_LOAD_MEMINDEX;
3299 case OP_LOADI4_MEMBASE:
3300 return OP_LOADI4_MEMINDEX;
3301 case OP_LOADU4_MEMBASE:
3302 return OP_LOADU4_MEMINDEX;
3303 case OP_LOADU1_MEMBASE:
3304 return OP_LOADU1_MEMINDEX;
3305 case OP_LOADI2_MEMBASE:
3306 return OP_LOADI2_MEMINDEX;
3307 case OP_LOADU2_MEMBASE:
3308 return OP_LOADU2_MEMINDEX;
3309 case OP_LOADI1_MEMBASE:
3310 return OP_LOADI1_MEMINDEX;
3311 case OP_STOREI1_MEMBASE_REG:
3312 return OP_STOREI1_MEMINDEX;
3313 case OP_STOREI2_MEMBASE_REG:
3314 return OP_STOREI2_MEMINDEX;
3315 case OP_STOREI4_MEMBASE_REG:
3316 return OP_STOREI4_MEMINDEX;
3317 case OP_STORE_MEMBASE_REG:
3318 return OP_STORE_MEMINDEX;
3319 case OP_STORER4_MEMBASE_REG:
3320 return OP_STORER4_MEMINDEX;
3321 case OP_STORER8_MEMBASE_REG:
3322 return OP_STORER8_MEMINDEX;
3323 case OP_STORE_MEMBASE_IMM:
3324 return OP_STORE_MEMBASE_REG;
3325 case OP_STOREI1_MEMBASE_IMM:
3326 return OP_STOREI1_MEMBASE_REG;
3327 case OP_STOREI2_MEMBASE_IMM:
3328 return OP_STOREI2_MEMBASE_REG;
3329 case OP_STOREI4_MEMBASE_IMM:
3330 return OP_STOREI4_MEMBASE_REG;
3332 g_assert_not_reached ();
3336 * Remove from the instruction list the instructions that can't be
3337 * represented with very simple instructions with no register
3341 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3343 MonoInst *ins, *temp, *last_ins = NULL;
3344 int rot_amount, imm8, low_imm;
3346 MONO_BB_FOR_EACH_INS (bb, ins) {
3348 switch (ins->opcode) {
3352 case OP_COMPARE_IMM:
3353 case OP_ICOMPARE_IMM:
3367 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3368 ADD_NEW_INS (cfg, temp, OP_ICONST);
3369 temp->inst_c0 = ins->inst_imm;
3370 temp->dreg = mono_alloc_ireg (cfg);
3371 ins->sreg2 = temp->dreg;
3372 ins->opcode = mono_op_imm_to_op (ins->opcode);
3374 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3380 if (ins->inst_imm == 1) {
3381 ins->opcode = OP_MOVE;
3384 if (ins->inst_imm == 0) {
3385 ins->opcode = OP_ICONST;
3389 imm8 = mono_is_power_of_two (ins->inst_imm);
3391 ins->opcode = OP_SHL_IMM;
3392 ins->inst_imm = imm8;
3395 ADD_NEW_INS (cfg, temp, OP_ICONST);
3396 temp->inst_c0 = ins->inst_imm;
3397 temp->dreg = mono_alloc_ireg (cfg);
3398 ins->sreg2 = temp->dreg;
3399 ins->opcode = OP_IMUL;
3405 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3406 /* ARM sets the C flag to 1 if there was _no_ overflow */
3407 ins->next->opcode = OP_COND_EXC_NC;
3410 case OP_IDIV_UN_IMM:
3412 case OP_IREM_UN_IMM:
3413 ADD_NEW_INS (cfg, temp, OP_ICONST);
3414 temp->inst_c0 = ins->inst_imm;
3415 temp->dreg = mono_alloc_ireg (cfg);
3416 ins->sreg2 = temp->dreg;
3417 ins->opcode = mono_op_imm_to_op (ins->opcode);
3419 case OP_LOCALLOC_IMM:
3420 ADD_NEW_INS (cfg, temp, OP_ICONST);
3421 temp->inst_c0 = ins->inst_imm;
3422 temp->dreg = mono_alloc_ireg (cfg);
3423 ins->sreg1 = temp->dreg;
3424 ins->opcode = OP_LOCALLOC;
3426 case OP_LOAD_MEMBASE:
3427 case OP_LOADI4_MEMBASE:
3428 case OP_LOADU4_MEMBASE:
3429 case OP_LOADU1_MEMBASE:
3430 /* we can do two things: load the immed in a register
3431 * and use an indexed load, or see if the immed can be
3432 * represented as an ad_imm + a load with a smaller offset
3433 * that fits. We just do the first for now, optimize later.
3435 if (arm_is_imm12 (ins->inst_offset))
3437 ADD_NEW_INS (cfg, temp, OP_ICONST);
3438 temp->inst_c0 = ins->inst_offset;
3439 temp->dreg = mono_alloc_ireg (cfg);
3440 ins->sreg2 = temp->dreg;
3441 ins->opcode = map_to_reg_reg_op (ins->opcode);
3443 case OP_LOADI2_MEMBASE:
3444 case OP_LOADU2_MEMBASE:
3445 case OP_LOADI1_MEMBASE:
3446 if (arm_is_imm8 (ins->inst_offset))
3448 ADD_NEW_INS (cfg, temp, OP_ICONST);
3449 temp->inst_c0 = ins->inst_offset;
3450 temp->dreg = mono_alloc_ireg (cfg);
3451 ins->sreg2 = temp->dreg;
3452 ins->opcode = map_to_reg_reg_op (ins->opcode);
3454 case OP_LOADR4_MEMBASE:
3455 case OP_LOADR8_MEMBASE:
3456 if (arm_is_fpimm8 (ins->inst_offset))
3458 low_imm = ins->inst_offset & 0x1ff;
3459 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3460 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3461 temp->inst_imm = ins->inst_offset & ~0x1ff;
3462 temp->sreg1 = ins->inst_basereg;
3463 temp->dreg = mono_alloc_ireg (cfg);
3464 ins->inst_basereg = temp->dreg;
3465 ins->inst_offset = low_imm;
3469 ADD_NEW_INS (cfg, temp, OP_ICONST);
3470 temp->inst_c0 = ins->inst_offset;
3471 temp->dreg = mono_alloc_ireg (cfg);
3473 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3474 add_ins->sreg1 = ins->inst_basereg;
3475 add_ins->sreg2 = temp->dreg;
3476 add_ins->dreg = mono_alloc_ireg (cfg);
3478 ins->inst_basereg = add_ins->dreg;
3479 ins->inst_offset = 0;
3482 case OP_STORE_MEMBASE_REG:
3483 case OP_STOREI4_MEMBASE_REG:
3484 case OP_STOREI1_MEMBASE_REG:
3485 if (arm_is_imm12 (ins->inst_offset))
3487 ADD_NEW_INS (cfg, temp, OP_ICONST);
3488 temp->inst_c0 = ins->inst_offset;
3489 temp->dreg = mono_alloc_ireg (cfg);
3490 ins->sreg2 = temp->dreg;
3491 ins->opcode = map_to_reg_reg_op (ins->opcode);
3493 case OP_STOREI2_MEMBASE_REG:
3494 if (arm_is_imm8 (ins->inst_offset))
3496 ADD_NEW_INS (cfg, temp, OP_ICONST);
3497 temp->inst_c0 = ins->inst_offset;
3498 temp->dreg = mono_alloc_ireg (cfg);
3499 ins->sreg2 = temp->dreg;
3500 ins->opcode = map_to_reg_reg_op (ins->opcode);
3502 case OP_STORER4_MEMBASE_REG:
3503 case OP_STORER8_MEMBASE_REG:
3504 if (arm_is_fpimm8 (ins->inst_offset))
3506 low_imm = ins->inst_offset & 0x1ff;
3507 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3508 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3509 temp->inst_imm = ins->inst_offset & ~0x1ff;
3510 temp->sreg1 = ins->inst_destbasereg;
3511 temp->dreg = mono_alloc_ireg (cfg);
3512 ins->inst_destbasereg = temp->dreg;
3513 ins->inst_offset = low_imm;
3517 ADD_NEW_INS (cfg, temp, OP_ICONST);
3518 temp->inst_c0 = ins->inst_offset;
3519 temp->dreg = mono_alloc_ireg (cfg);
3521 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3522 add_ins->sreg1 = ins->inst_destbasereg;
3523 add_ins->sreg2 = temp->dreg;
3524 add_ins->dreg = mono_alloc_ireg (cfg);
3526 ins->inst_destbasereg = add_ins->dreg;
3527 ins->inst_offset = 0;
3530 case OP_STORE_MEMBASE_IMM:
3531 case OP_STOREI1_MEMBASE_IMM:
3532 case OP_STOREI2_MEMBASE_IMM:
3533 case OP_STOREI4_MEMBASE_IMM:
3534 ADD_NEW_INS (cfg, temp, OP_ICONST);
3535 temp->inst_c0 = ins->inst_imm;
3536 temp->dreg = mono_alloc_ireg (cfg);
3537 ins->sreg1 = temp->dreg;
3538 ins->opcode = map_to_reg_reg_op (ins->opcode);
3540 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3543 gboolean swap = FALSE;
3547 /* Optimized away */
3552 /* Some fp compares require swapped operands */
3553 switch (ins->next->opcode) {
3555 ins->next->opcode = OP_FBLT;
3559 ins->next->opcode = OP_FBLT_UN;
3563 ins->next->opcode = OP_FBGE;
3567 ins->next->opcode = OP_FBGE_UN;
3575 ins->sreg1 = ins->sreg2;
3584 bb->last_ins = last_ins;
3585 bb->max_vreg = cfg->next_vreg;
3589 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3593 if (long_ins->opcode == OP_LNEG) {
3595 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3596 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3602 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3604 /* sreg is a float, dreg is an integer reg */
3606 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3608 ARM_TOSIZD (code, vfp_scratch1, sreg);
3610 ARM_TOUIZD (code, vfp_scratch1, sreg);
3611 ARM_FMRS (code, dreg, vfp_scratch1);
3612 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3616 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3617 else if (size == 2) {
3618 ARM_SHL_IMM (code, dreg, dreg, 16);
3619 ARM_SHR_IMM (code, dreg, dreg, 16);
3623 ARM_SHL_IMM (code, dreg, dreg, 24);
3624 ARM_SAR_IMM (code, dreg, dreg, 24);
3625 } else if (size == 2) {
3626 ARM_SHL_IMM (code, dreg, dreg, 16);
3627 ARM_SAR_IMM (code, dreg, dreg, 16);
3634 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3636 /* sreg is a float, dreg is an integer reg */
3638 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3640 ARM_TOSIZS (code, vfp_scratch1, sreg);
3642 ARM_TOUIZS (code, vfp_scratch1, sreg);
3643 ARM_FMRS (code, dreg, vfp_scratch1);
3644 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3648 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3649 else if (size == 2) {
3650 ARM_SHL_IMM (code, dreg, dreg, 16);
3651 ARM_SHR_IMM (code, dreg, dreg, 16);
3655 ARM_SHL_IMM (code, dreg, dreg, 24);
3656 ARM_SAR_IMM (code, dreg, dreg, 24);
3657 } else if (size == 2) {
3658 ARM_SHL_IMM (code, dreg, dreg, 16);
3659 ARM_SAR_IMM (code, dreg, dreg, 16);
3665 #endif /* #ifndef DISABLE_JIT */
3669 const guchar *target;
3674 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3677 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
3678 PatchData *pdata = (PatchData*)user_data;
3679 guchar *code = data;
3680 guint32 *thunks = data;
3681 guint32 *endthunks = (guint32*)(code + bsize);
3683 int difflow, diffhigh;
3685 /* always ensure a call from pdata->code can reach to the thunks without further thunks */
3686 difflow = (char*)pdata->code - (char*)thunks;
3687 diffhigh = (char*)pdata->code - (char*)endthunks;
3688 if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
3692 * The thunk is composed of 3 words:
3693 * load constant from thunks [2] into ARM_IP
3696 * Note that the LR register is already setup
3698 //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
3699 if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
3700 while (thunks < endthunks) {
3701 //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
3702 if (thunks [2] == (guint32)pdata->target) {
3703 arm_patch (pdata->code, (guchar*)thunks);
3704 mono_arch_flush_icache (pdata->code, 4);
3707 } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
3708 /* found a free slot instead: emit thunk */
3709 /* ARMREG_IP is fine to use since this can't be an IMT call
3712 code = (guchar*)thunks;
3713 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3714 if (thumb_supported)
3715 ARM_BX (code, ARMREG_IP);
3717 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3718 thunks [2] = (guint32)pdata->target;
3719 mono_arch_flush_icache ((guchar*)thunks, 12);
3721 arm_patch (pdata->code, (guchar*)thunks);
3722 mono_arch_flush_icache (pdata->code, 4);
3726 /* skip 12 bytes, the size of the thunk */
3730 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
3736 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3741 domain = mono_domain_get ();
3744 pdata.target = target;
3745 pdata.absolute = absolute;
3749 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
3752 if (pdata.found != 1) {
3753 mono_domain_lock (domain);
3754 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3757 /* this uses the first available slot */
3759 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3761 mono_domain_unlock (domain);
3764 if (pdata.found != 1) {
3766 GHashTableIter iter;
3767 MonoJitDynamicMethodInfo *ji;
3770 * This might be a dynamic method, search its code manager. We can only
3771 * use the dynamic method containing CODE, since the others might be freed later.
3775 mono_domain_lock (domain);
3776 hash = domain_jit_info (domain)->dynamic_code_hash;
3778 /* FIXME: Speed this up */
3779 g_hash_table_iter_init (&iter, hash);
3780 while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
3781 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
3782 if (pdata.found == 1)
3786 mono_domain_unlock (domain);
3788 if (pdata.found != 1)
3789 g_print ("thunk failed for %p from %p\n", target, code);
3790 g_assert (pdata.found == 1);
3794 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3796 guint32 *code32 = (void*)code;
3797 guint32 ins = *code32;
3798 guint32 prim = (ins >> 25) & 7;
3799 guint32 tval = GPOINTER_TO_UINT (target);
3801 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3802 if (prim == 5) { /* 101b */
3803 /* the diff starts 8 bytes from the branch opcode */
3804 gint diff = target - code - 8;
3806 gint tmask = 0xffffffff;
3807 if (tval & 1) { /* entering thumb mode */
3808 diff = target - 1 - code - 8;
3809 g_assert (thumb_supported);
3810 tbits = 0xf << 28; /* bl->blx bit pattern */
3811 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3812 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3816 tmask = ~(1 << 24); /* clear the link bit */
3817 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3822 if (diff <= 33554431) {
3824 ins = (ins & 0xff000000) | diff;
3826 *code32 = ins | tbits;
3830 /* diff between 0 and -33554432 */
3831 if (diff >= -33554432) {
3833 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3835 *code32 = ins | tbits;
3840 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3844 #ifdef USE_JUMP_TABLES
3846 gpointer *jte = mono_jumptable_get_entry (code);
3848 jte [0] = (gpointer) target;
3852 * The alternative call sequences looks like this:
3854 * ldr ip, [pc] // loads the address constant
3855 * b 1f // jumps around the constant
3856 * address constant embedded in the code
3861 * There are two cases for patching:
3862 * a) at the end of method emission: in this case code points to the start
3863 * of the call sequence
3864 * b) during runtime patching of the call site: in this case code points
3865 * to the mov pc, ip instruction
3867 * We have to handle also the thunk jump code sequence:
3871 * address constant // execution never reaches here
3873 if ((ins & 0x0ffffff0) == 0x12fff10) {
3874 /* Branch and exchange: the address is constructed in a reg
3875 * We can patch BX when the code sequence is the following:
3876 * ldr ip, [pc, #0] ; 0x8
3883 guint8 *emit = (guint8*)ccode;
3884 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3886 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3887 ARM_BX (emit, ARMREG_IP);
3889 /*patching from magic trampoline*/
3890 if (ins == ccode [3]) {
3891 g_assert (code32 [-4] == ccode [0]);
3892 g_assert (code32 [-3] == ccode [1]);
3893 g_assert (code32 [-1] == ccode [2]);
3894 code32 [-2] = (guint32)target;
3897 /*patching from JIT*/
3898 if (ins == ccode [0]) {
3899 g_assert (code32 [1] == ccode [1]);
3900 g_assert (code32 [3] == ccode [2]);
3901 g_assert (code32 [4] == ccode [3]);
3902 code32 [2] = (guint32)target;
3905 g_assert_not_reached ();
3906 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3914 guint8 *emit = (guint8*)ccode;
3915 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3917 ARM_BLX_REG (emit, ARMREG_IP);
3919 g_assert (code32 [-3] == ccode [0]);
3920 g_assert (code32 [-2] == ccode [1]);
3921 g_assert (code32 [0] == ccode [2]);
3923 code32 [-1] = (guint32)target;
3926 guint32 *tmp = ccode;
3927 guint8 *emit = (guint8*)tmp;
3928 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3929 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3930 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3931 ARM_BX (emit, ARMREG_IP);
3932 if (ins == ccode [2]) {
3933 g_assert_not_reached (); // should be -2 ...
3934 code32 [-1] = (guint32)target;
3937 if (ins == ccode [0]) {
3938 /* handles both thunk jump code and the far call sequence */
3939 code32 [2] = (guint32)target;
3942 g_assert_not_reached ();
3944 // g_print ("patched with 0x%08x\n", ins);
3949 arm_patch (guchar *code, const guchar *target)
3951 arm_patch_general (NULL, code, target, NULL);
3955 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3956 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3957 * to be used with the emit macros.
3958 * Return -1 otherwise.
3961 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3964 for (i = 0; i < 31; i+= 2) {
3965 res = (val << (32 - i)) | (val >> i);
3968 *rot_amount = i? 32 - i: 0;
3975 * Emits in code a sequence of instructions that load the value 'val'
3976 * into the dreg register. Uses at most 4 instructions.
3979 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3981 int imm8, rot_amount;
3983 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3984 /* skip the constant pool */
3990 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3991 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3992 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3993 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3996 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3998 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4002 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4004 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4006 if (val & 0xFF0000) {
4007 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4009 if (val & 0xFF000000) {
4010 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4012 } else if (val & 0xFF00) {
4013 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4014 if (val & 0xFF0000) {
4015 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4017 if (val & 0xFF000000) {
4018 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4020 } else if (val & 0xFF0000) {
4021 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4022 if (val & 0xFF000000) {
4023 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4026 //g_assert_not_reached ();
4032 mono_arm_thumb_supported (void)
4034 return thumb_supported;
4040 * emit_load_volatile_arguments:
4042 * Load volatile arguments from the stack to the original input registers.
4043 * Required before a tail call.
4046 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
4048 MonoMethod *method = cfg->method;
4049 MonoMethodSignature *sig;
4054 /* FIXME: Generate intermediate code instead */
4056 sig = mono_method_signature (method);
4058 /* This is the opposite of the code in emit_prolog */
4062 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
4064 if (cinfo->vtype_retaddr) {
4065 ArgInfo *ainfo = &cinfo->ret;
4066 inst = cfg->vret_addr;
4067 g_assert (arm_is_imm12 (inst->inst_offset));
4068 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4070 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4071 ArgInfo *ainfo = cinfo->args + i;
4072 inst = cfg->args [pos];
4074 if (cfg->verbose_level > 2)
4075 g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
4076 if (inst->opcode == OP_REGVAR) {
4077 if (ainfo->storage == RegTypeGeneral)
4078 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
4079 else if (ainfo->storage == RegTypeFP) {
4080 g_assert_not_reached ();
4081 } else if (ainfo->storage == RegTypeBase) {
4085 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
4086 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4088 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4089 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
4093 g_assert_not_reached ();
4095 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
4096 switch (ainfo->size) {
4103 g_assert (arm_is_imm12 (inst->inst_offset));
4104 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4105 g_assert (arm_is_imm12 (inst->inst_offset + 4));
4106 ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
4109 if (arm_is_imm12 (inst->inst_offset)) {
4110 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4112 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4113 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4117 } else if (ainfo->storage == RegTypeBaseGen) {
4120 } else if (ainfo->storage == RegTypeBase) {
4122 } else if (ainfo->storage == RegTypeFP) {
4123 g_assert_not_reached ();
4124 } else if (ainfo->storage == RegTypeStructByVal) {
4125 int doffset = inst->inst_offset;
4129 if (mono_class_from_mono_type (inst->inst_vtype))
4130 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
4131 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
4132 if (arm_is_imm12 (doffset)) {
4133 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
4135 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
4136 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
4138 soffset += sizeof (gpointer);
4139 doffset += sizeof (gpointer);
4144 } else if (ainfo->storage == RegTypeStructByAddr) {
4159 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4164 guint8 *code = cfg->native_code + cfg->code_len;
4165 MonoInst *last_ins = NULL;
4166 guint last_offset = 0;
4168 int imm8, rot_amount;
4170 /* we don't align basic blocks of loops on arm */
4172 if (cfg->verbose_level > 2)
4173 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4175 cpos = bb->max_offset;
4177 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4178 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4179 //g_assert (!mono_compile_aot);
4182 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4183 /* this is not thread save, but good enough */
4184 /* fixme: howto handle overflows? */
4185 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4188 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4189 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4190 (gpointer)"mono_break");
4191 code = emit_call_seq (cfg, code);
4194 MONO_BB_FOR_EACH_INS (bb, ins) {
4195 offset = code - cfg->native_code;
4197 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4199 if (offset > (cfg->code_size - max_len - 16)) {
4200 cfg->code_size *= 2;
4201 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4202 code = cfg->native_code + offset;
4204 // if (ins->cil_code)
4205 // g_print ("cil code\n");
4206 mono_debug_record_line_number (cfg, ins, offset);
4208 switch (ins->opcode) {
4209 case OP_MEMORY_BARRIER:
4211 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4212 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4216 #ifdef HAVE_AEABI_READ_TP
4217 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4218 (gpointer)"__aeabi_read_tp");
4219 code = emit_call_seq (cfg, code);
4221 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
4223 g_assert_not_reached ();
4226 case OP_ATOMIC_EXCHANGE_I4:
4227 case OP_ATOMIC_CAS_I4:
4228 case OP_ATOMIC_ADD_I4: {
4232 g_assert (v7_supported);
4235 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4237 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4239 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4243 g_assert (cfg->arch.atomic_tmp_offset != -1);
4244 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4246 switch (ins->opcode) {
4247 case OP_ATOMIC_EXCHANGE_I4:
4249 ARM_DMB (code, ARM_DMB_SY);
4250 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4251 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4252 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4254 ARM_B_COND (code, ARMCOND_NE, 0);
4255 arm_patch (buf [1], buf [0]);
4257 case OP_ATOMIC_CAS_I4:
4258 ARM_DMB (code, ARM_DMB_SY);
4260 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4261 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4263 ARM_B_COND (code, ARMCOND_NE, 0);
4264 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4265 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4267 ARM_B_COND (code, ARMCOND_NE, 0);
4268 arm_patch (buf [2], buf [0]);
4269 arm_patch (buf [1], code);
4271 case OP_ATOMIC_ADD_I4:
4273 ARM_DMB (code, ARM_DMB_SY);
4274 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4275 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4276 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4277 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4279 ARM_B_COND (code, ARMCOND_NE, 0);
4280 arm_patch (buf [1], buf [0]);
4283 g_assert_not_reached ();
4286 ARM_DMB (code, ARM_DMB_SY);
4287 if (tmpreg != ins->dreg)
4288 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4289 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4292 case OP_ATOMIC_LOAD_I1:
4293 case OP_ATOMIC_LOAD_U1:
4294 case OP_ATOMIC_LOAD_I2:
4295 case OP_ATOMIC_LOAD_U2:
4296 case OP_ATOMIC_LOAD_I4:
4297 case OP_ATOMIC_LOAD_U4:
4298 case OP_ATOMIC_LOAD_R4:
4299 case OP_ATOMIC_LOAD_R8: {
4300 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4301 ARM_DMB (code, ARM_DMB_SY);
4303 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4305 switch (ins->opcode) {
4306 case OP_ATOMIC_LOAD_I1:
4307 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4309 case OP_ATOMIC_LOAD_U1:
4310 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4312 case OP_ATOMIC_LOAD_I2:
4313 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4315 case OP_ATOMIC_LOAD_U2:
4316 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4318 case OP_ATOMIC_LOAD_I4:
4319 case OP_ATOMIC_LOAD_U4:
4320 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4322 case OP_ATOMIC_LOAD_R4:
4323 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4324 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4325 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4326 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4328 case OP_ATOMIC_LOAD_R8:
4329 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4330 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4334 ARM_DMB (code, ARM_DMB_SY);
4337 case OP_ATOMIC_STORE_I1:
4338 case OP_ATOMIC_STORE_U1:
4339 case OP_ATOMIC_STORE_I2:
4340 case OP_ATOMIC_STORE_U2:
4341 case OP_ATOMIC_STORE_I4:
4342 case OP_ATOMIC_STORE_U4:
4343 case OP_ATOMIC_STORE_R4:
4344 case OP_ATOMIC_STORE_R8: {
4345 ARM_DMB (code, ARM_DMB_SY);
4347 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4349 switch (ins->opcode) {
4350 case OP_ATOMIC_STORE_I1:
4351 case OP_ATOMIC_STORE_U1:
4352 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4354 case OP_ATOMIC_STORE_I2:
4355 case OP_ATOMIC_STORE_U2:
4356 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4358 case OP_ATOMIC_STORE_I4:
4359 case OP_ATOMIC_STORE_U4:
4360 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4362 case OP_ATOMIC_STORE_R4:
4363 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4364 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4365 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
4366 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4368 case OP_ATOMIC_STORE_R8:
4369 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4370 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4374 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4375 ARM_DMB (code, ARM_DMB_SY);
4379 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4380 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4383 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4384 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4386 case OP_STOREI1_MEMBASE_IMM:
4387 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4388 g_assert (arm_is_imm12 (ins->inst_offset));
4389 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4391 case OP_STOREI2_MEMBASE_IMM:
4392 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4393 g_assert (arm_is_imm8 (ins->inst_offset));
4394 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4396 case OP_STORE_MEMBASE_IMM:
4397 case OP_STOREI4_MEMBASE_IMM:
4398 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4399 g_assert (arm_is_imm12 (ins->inst_offset));
4400 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4402 case OP_STOREI1_MEMBASE_REG:
4403 g_assert (arm_is_imm12 (ins->inst_offset));
4404 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4406 case OP_STOREI2_MEMBASE_REG:
4407 g_assert (arm_is_imm8 (ins->inst_offset));
4408 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4410 case OP_STORE_MEMBASE_REG:
4411 case OP_STOREI4_MEMBASE_REG:
4412 /* this case is special, since it happens for spill code after lowering has been called */
4413 if (arm_is_imm12 (ins->inst_offset)) {
4414 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4416 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4417 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4420 case OP_STOREI1_MEMINDEX:
4421 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4423 case OP_STOREI2_MEMINDEX:
4424 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4426 case OP_STORE_MEMINDEX:
4427 case OP_STOREI4_MEMINDEX:
4428 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4431 g_assert_not_reached ();
4433 case OP_LOAD_MEMINDEX:
4434 case OP_LOADI4_MEMINDEX:
4435 case OP_LOADU4_MEMINDEX:
4436 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4438 case OP_LOADI1_MEMINDEX:
4439 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4441 case OP_LOADU1_MEMINDEX:
4442 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4444 case OP_LOADI2_MEMINDEX:
4445 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4447 case OP_LOADU2_MEMINDEX:
4448 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4450 case OP_LOAD_MEMBASE:
4451 case OP_LOADI4_MEMBASE:
4452 case OP_LOADU4_MEMBASE:
4453 /* this case is special, since it happens for spill code after lowering has been called */
4454 if (arm_is_imm12 (ins->inst_offset)) {
4455 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4457 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4458 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4461 case OP_LOADI1_MEMBASE:
4462 g_assert (arm_is_imm8 (ins->inst_offset));
4463 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4465 case OP_LOADU1_MEMBASE:
4466 g_assert (arm_is_imm12 (ins->inst_offset));
4467 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4469 case OP_LOADU2_MEMBASE:
4470 g_assert (arm_is_imm8 (ins->inst_offset));
4471 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4473 case OP_LOADI2_MEMBASE:
4474 g_assert (arm_is_imm8 (ins->inst_offset));
4475 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4477 case OP_ICONV_TO_I1:
4478 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4479 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4481 case OP_ICONV_TO_I2:
4482 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4483 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4485 case OP_ICONV_TO_U1:
4486 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4488 case OP_ICONV_TO_U2:
4489 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4490 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4494 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4496 case OP_COMPARE_IMM:
4497 case OP_ICOMPARE_IMM:
4498 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4499 g_assert (imm8 >= 0);
4500 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4504 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4505 * So instead of emitting a trap, we emit a call a C function and place a
4508 //*(int*)code = 0xef9f0001;
4511 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4512 (gpointer)"mono_break");
4513 code = emit_call_seq (cfg, code);
4515 case OP_RELAXED_NOP:
4520 case OP_DUMMY_STORE:
4521 case OP_DUMMY_ICONST:
4522 case OP_DUMMY_R8CONST:
4523 case OP_NOT_REACHED:
4526 case OP_IL_SEQ_POINT:
4527 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4529 case OP_SEQ_POINT: {
4531 MonoInst *info_var = cfg->arch.seq_point_info_var;
4532 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4533 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
4534 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4535 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4537 int dreg = ARMREG_LR;
4539 if (cfg->soft_breakpoints) {
4540 g_assert (!cfg->compile_aot);
4544 * For AOT, we use one got slot per method, which will point to a
4545 * SeqPointInfo structure, containing all the information required
4546 * by the code below.
4548 if (cfg->compile_aot) {
4549 g_assert (info_var);
4550 g_assert (info_var->opcode == OP_REGOFFSET);
4551 g_assert (arm_is_imm12 (info_var->inst_offset));
4554 if (!cfg->soft_breakpoints) {
4556 * Read from the single stepping trigger page. This will cause a
4557 * SIGSEGV when single stepping is enabled.
4558 * We do this _before_ the breakpoint, so single stepping after
4559 * a breakpoint is hit will step to the next IL offset.
4561 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4564 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4565 if (cfg->soft_breakpoints) {
4566 /* Load the address of the sequence point trigger variable. */
4569 g_assert (var->opcode == OP_REGOFFSET);
4570 g_assert (arm_is_imm12 (var->inst_offset));
4571 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4573 /* Read the value and check whether it is non-zero. */
4574 ARM_LDR_IMM (code, dreg, dreg, 0);
4575 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4577 /* Load the address of the sequence point method. */
4578 var = ss_method_var;
4580 g_assert (var->opcode == OP_REGOFFSET);
4581 g_assert (arm_is_imm12 (var->inst_offset));
4582 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4584 /* Call it conditionally. */
4585 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4587 if (cfg->compile_aot) {
4588 /* Load the trigger page addr from the variable initialized in the prolog */
4589 var = ss_trigger_page_var;
4591 g_assert (var->opcode == OP_REGOFFSET);
4592 g_assert (arm_is_imm12 (var->inst_offset));
4593 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4595 #ifdef USE_JUMP_TABLES
4596 gpointer *jte = mono_jumptable_add_entry ();
4597 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4598 jte [0] = ss_trigger_page;
4600 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4602 *(int*)code = (int)ss_trigger_page;
4606 ARM_LDR_IMM (code, dreg, dreg, 0);
4610 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4612 if (cfg->soft_breakpoints) {
4613 /* Load the address of the breakpoint method into ip. */
4614 var = bp_method_var;
4616 g_assert (var->opcode == OP_REGOFFSET);
4617 g_assert (arm_is_imm12 (var->inst_offset));
4618 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4621 * A placeholder for a possible breakpoint inserted by
4622 * mono_arch_set_breakpoint ().
4625 } else if (cfg->compile_aot) {
4626 guint32 offset = code - cfg->native_code;
4629 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4630 /* Add the offset */
4631 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4632 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4633 if (arm_is_imm12 ((int)val)) {
4634 ARM_LDR_IMM (code, dreg, dreg, val);
4636 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4638 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4640 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4641 g_assert (!(val & 0xFF000000));
4643 ARM_LDR_IMM (code, dreg, dreg, 0);
4645 /* What is faster, a branch or a load ? */
4646 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4647 /* The breakpoint instruction */
4648 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4651 * A placeholder for a possible breakpoint inserted by
4652 * mono_arch_set_breakpoint ().
4654 for (i = 0; i < 4; ++i)
4661 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4664 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4668 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4671 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4672 g_assert (imm8 >= 0);
4673 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4677 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4678 g_assert (imm8 >= 0);
4679 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4683 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4684 g_assert (imm8 >= 0);
4685 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4688 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4689 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4691 case OP_IADD_OVF_UN:
4692 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4693 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4696 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4697 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4699 case OP_ISUB_OVF_UN:
4700 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4701 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4703 case OP_ADD_OVF_CARRY:
4704 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4705 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4707 case OP_ADD_OVF_UN_CARRY:
4708 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4709 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4711 case OP_SUB_OVF_CARRY:
4712 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4713 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4715 case OP_SUB_OVF_UN_CARRY:
4716 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4717 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4721 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4724 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4725 g_assert (imm8 >= 0);
4726 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4729 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4733 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4737 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4738 g_assert (imm8 >= 0);
4739 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4743 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4744 g_assert (imm8 >= 0);
4745 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4747 case OP_ARM_RSBS_IMM:
4748 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4749 g_assert (imm8 >= 0);
4750 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4752 case OP_ARM_RSC_IMM:
4753 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4754 g_assert (imm8 >= 0);
4755 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4758 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4762 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4763 g_assert (imm8 >= 0);
4764 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4767 g_assert (v7s_supported);
4768 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4771 g_assert (v7s_supported);
4772 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4775 g_assert (v7s_supported);
4776 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4777 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4780 g_assert (v7s_supported);
4781 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4782 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4786 g_assert_not_reached ();
4788 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4792 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4793 g_assert (imm8 >= 0);
4794 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4797 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4801 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4802 g_assert (imm8 >= 0);
4803 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4806 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4811 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4812 else if (ins->dreg != ins->sreg1)
4813 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4816 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4821 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4822 else if (ins->dreg != ins->sreg1)
4823 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4826 case OP_ISHR_UN_IMM:
4828 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4829 else if (ins->dreg != ins->sreg1)
4830 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4833 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4836 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4839 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4842 if (ins->dreg == ins->sreg2)
4843 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4845 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4848 g_assert_not_reached ();
4851 /* FIXME: handle ovf/ sreg2 != dreg */
4852 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4853 /* FIXME: MUL doesn't set the C/O flags on ARM */
4855 case OP_IMUL_OVF_UN:
4856 /* FIXME: handle ovf/ sreg2 != dreg */
4857 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4858 /* FIXME: MUL doesn't set the C/O flags on ARM */
4861 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4864 /* Load the GOT offset */
4865 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4866 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4868 *(gpointer*)code = NULL;
4870 /* Load the value from the GOT */
4871 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4873 case OP_OBJC_GET_SELECTOR:
4874 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4875 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4877 *(gpointer*)code = NULL;
4879 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4881 case OP_ICONV_TO_I4:
4882 case OP_ICONV_TO_U4:
4884 if (ins->dreg != ins->sreg1)
4885 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4888 int saved = ins->sreg2;
4889 if (ins->sreg2 == ARM_LSW_REG) {
4890 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4893 if (ins->sreg1 != ARM_LSW_REG)
4894 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4895 if (saved != ARM_MSW_REG)
4896 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4900 if (IS_VFP && ins->dreg != ins->sreg1)
4901 ARM_CPYD (code, ins->dreg, ins->sreg1);
4903 case OP_MOVE_F_TO_I4:
4904 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4905 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4906 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4907 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4909 case OP_MOVE_I4_TO_F:
4910 ARM_FMSR (code, ins->dreg, ins->sreg1);
4911 ARM_CVTS (code, ins->dreg, ins->dreg);
4913 case OP_FCONV_TO_R4:
4916 ARM_CVTD (code, ins->dreg, ins->sreg1);
4918 ARM_CVTD (code, ins->dreg, ins->sreg1);
4919 ARM_CVTS (code, ins->dreg, ins->dreg);
4925 * Keep in sync with mono_arch_emit_epilog
4927 g_assert (!cfg->method->save_lmf);
4929 code = emit_load_volatile_arguments (cfg, code);
4931 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4933 if (cfg->used_int_regs)
4934 ARM_POP (code, cfg->used_int_regs);
4935 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4937 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4939 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4940 if (cfg->compile_aot) {
4941 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4943 *(gpointer*)code = NULL;
4945 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4947 code = mono_arm_patchable_b (code, ARMCOND_AL);
4951 MonoCallInst *call = (MonoCallInst*)ins;
4954 * The stack looks like the following:
4955 * <caller argument area>
4958 * <callee argument area>
4959 * Need to copy the arguments from the callee argument area to
4960 * the caller argument area, and pop the frame.
4962 if (call->stack_usage) {
4963 int i, prev_sp_offset = 0;
4965 /* Compute size of saved registers restored below */
4967 prev_sp_offset = 2 * 4;
4969 prev_sp_offset = 1 * 4;
4970 for (i = 0; i < 16; ++i) {
4971 if (cfg->used_int_regs & (1 << i))
4972 prev_sp_offset += 4;
4975 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4977 /* Copy arguments on the stack to our argument area */
4978 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4979 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4980 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4985 * Keep in sync with mono_arch_emit_epilog
4987 g_assert (!cfg->method->save_lmf);
4989 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4991 if (cfg->used_int_regs)
4992 ARM_POP (code, cfg->used_int_regs);
4993 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4995 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4998 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4999 if (cfg->compile_aot) {
5000 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5002 *(gpointer*)code = NULL;
5004 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5006 code = mono_arm_patchable_b (code, ARMCOND_AL);
5011 /* ensure ins->sreg1 is not NULL */
5012 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5015 g_assert (cfg->sig_cookie < 128);
5016 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5017 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5027 call = (MonoCallInst*)ins;
5030 code = emit_float_args (cfg, call, code, &max_len, &offset);
5032 if (ins->flags & MONO_INST_HAS_METHOD)
5033 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5035 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5036 code = emit_call_seq (cfg, code);
5037 ins->flags |= MONO_INST_GC_CALLSITE;
5038 ins->backend.pc_offset = code - cfg->native_code;
5039 code = emit_move_return_value (cfg, ins, code);
5046 case OP_VOIDCALL_REG:
5049 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5051 code = emit_call_reg (code, ins->sreg1);
5052 ins->flags |= MONO_INST_GC_CALLSITE;
5053 ins->backend.pc_offset = code - cfg->native_code;
5054 code = emit_move_return_value (cfg, ins, code);
5056 case OP_FCALL_MEMBASE:
5057 case OP_RCALL_MEMBASE:
5058 case OP_LCALL_MEMBASE:
5059 case OP_VCALL_MEMBASE:
5060 case OP_VCALL2_MEMBASE:
5061 case OP_VOIDCALL_MEMBASE:
5062 case OP_CALL_MEMBASE: {
5063 gboolean imt_arg = FALSE;
5065 g_assert (ins->sreg1 != ARMREG_LR);
5066 call = (MonoCallInst*)ins;
5069 code = emit_float_args (cfg, call, code, &max_len, &offset);
5071 if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE)
5073 if (!arm_is_imm12 (ins->inst_offset))
5074 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5075 #ifdef USE_JUMP_TABLES
5081 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, LR_BIAS);
5083 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5085 if (!arm_is_imm12 (ins->inst_offset))
5086 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5088 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5091 * We can't embed the method in the code stream in PIC code, or
5093 * Instead, we put it in V5 in code emitted by
5094 * mono_arch_emit_imt_argument (), and embed NULL here to
5095 * signal the IMT thunk that the value is in V5.
5097 #ifdef USE_JUMP_TABLES
5098 /* In case of jumptables we always use value in V5. */
5101 if (call->dynamic_imt_arg)
5102 *((gpointer*)code) = NULL;
5104 *((gpointer*)code) = (gpointer)call->method;
5108 ins->flags |= MONO_INST_GC_CALLSITE;
5109 ins->backend.pc_offset = code - cfg->native_code;
5110 code = emit_move_return_value (cfg, ins, code);
5114 /* round the size to 8 bytes */
5115 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
5116 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
5117 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5118 /* memzero the area: dreg holds the size, sp is the pointer */
5119 if (ins->flags & MONO_INST_INIT) {
5120 guint8 *start_loop, *branch_to_cond;
5121 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5122 branch_to_cond = code;
5125 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5126 arm_patch (branch_to_cond, code);
5127 /* decrement by 4 and set flags */
5128 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5129 ARM_B_COND (code, ARMCOND_GE, 0);
5130 arm_patch (code - 4, start_loop);
5132 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5133 if (cfg->param_area)
5134 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5139 MonoInst *var = cfg->dyn_call_var;
5141 g_assert (var->opcode == OP_REGOFFSET);
5142 g_assert (arm_is_imm12 (var->inst_offset));
5144 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5145 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5147 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5149 /* Save args buffer */
5150 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5152 /* Set stack slots using R0 as scratch reg */
5153 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5154 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5155 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5156 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5159 /* Set argument registers */
5160 for (i = 0; i < PARAM_REGS; ++i)
5161 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5164 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5165 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5168 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5169 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5170 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5174 if (ins->sreg1 != ARMREG_R0)
5175 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5176 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5177 (gpointer)"mono_arch_throw_exception");
5178 code = emit_call_seq (cfg, code);
5182 if (ins->sreg1 != ARMREG_R0)
5183 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5184 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5185 (gpointer)"mono_arch_rethrow_exception");
5186 code = emit_call_seq (cfg, code);
5189 case OP_START_HANDLER: {
5190 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5193 /* Reserve a param area, see filter-stack.exe */
5194 if (cfg->param_area) {
5195 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5196 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5198 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5199 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5203 if (arm_is_imm12 (spvar->inst_offset)) {
5204 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5206 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5207 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5211 case OP_ENDFILTER: {
5212 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5215 /* Free the param area */
5216 if (cfg->param_area) {
5217 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5218 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5220 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5221 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5225 if (ins->sreg1 != ARMREG_R0)
5226 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5227 if (arm_is_imm12 (spvar->inst_offset)) {
5228 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5230 g_assert (ARMREG_IP != spvar->inst_basereg);
5231 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5232 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5234 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5237 case OP_ENDFINALLY: {
5238 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5241 /* Free the param area */
5242 if (cfg->param_area) {
5243 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5244 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5246 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5247 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5251 if (arm_is_imm12 (spvar->inst_offset)) {
5252 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5254 g_assert (ARMREG_IP != spvar->inst_basereg);
5255 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5256 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5258 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5261 case OP_CALL_HANDLER:
5262 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5263 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5264 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5267 ins->inst_c0 = code - cfg->native_code;
5270 /*if (ins->inst_target_bb->native_offset) {
5272 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5274 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5275 code = mono_arm_patchable_b (code, ARMCOND_AL);
5279 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5283 * In the normal case we have:
5284 * ldr pc, [pc, ins->sreg1 << 2]
5287 * ldr lr, [pc, ins->sreg1 << 2]
5289 * After follows the data.
5290 * FIXME: add aot support.
5292 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5293 #ifdef USE_JUMP_TABLES
5295 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5296 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5297 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5301 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5302 if (offset + max_len > (cfg->code_size - 16)) {
5303 cfg->code_size += max_len;
5304 cfg->code_size *= 2;
5305 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5306 code = cfg->native_code + offset;
5308 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5310 code += 4 * GPOINTER_TO_INT (ins->klass);
5315 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5316 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5320 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5321 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5325 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5326 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5330 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5331 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5335 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5336 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5339 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5340 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5343 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5344 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5347 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5348 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5351 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5352 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5355 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5356 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5358 case OP_COND_EXC_EQ:
5359 case OP_COND_EXC_NE_UN:
5360 case OP_COND_EXC_LT:
5361 case OP_COND_EXC_LT_UN:
5362 case OP_COND_EXC_GT:
5363 case OP_COND_EXC_GT_UN:
5364 case OP_COND_EXC_GE:
5365 case OP_COND_EXC_GE_UN:
5366 case OP_COND_EXC_LE:
5367 case OP_COND_EXC_LE_UN:
5368 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5370 case OP_COND_EXC_IEQ:
5371 case OP_COND_EXC_INE_UN:
5372 case OP_COND_EXC_ILT:
5373 case OP_COND_EXC_ILT_UN:
5374 case OP_COND_EXC_IGT:
5375 case OP_COND_EXC_IGT_UN:
5376 case OP_COND_EXC_IGE:
5377 case OP_COND_EXC_IGE_UN:
5378 case OP_COND_EXC_ILE:
5379 case OP_COND_EXC_ILE_UN:
5380 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5383 case OP_COND_EXC_IC:
5384 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5386 case OP_COND_EXC_OV:
5387 case OP_COND_EXC_IOV:
5388 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5390 case OP_COND_EXC_NC:
5391 case OP_COND_EXC_INC:
5392 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5394 case OP_COND_EXC_NO:
5395 case OP_COND_EXC_INO:
5396 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5408 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5411 /* floating point opcodes */
5413 if (cfg->compile_aot) {
5414 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5416 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5418 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5421 /* FIXME: we can optimize the imm load by dealing with part of
5422 * the displacement in LDFD (aligning to 512).
5424 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5425 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5429 if (cfg->compile_aot) {
5430 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5432 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5435 ARM_CVTS (code, ins->dreg, ins->dreg);
5437 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5438 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5440 ARM_CVTS (code, ins->dreg, ins->dreg);
5443 case OP_STORER8_MEMBASE_REG:
5444 /* This is generated by the local regalloc pass which runs after the lowering pass */
5445 if (!arm_is_fpimm8 (ins->inst_offset)) {
5446 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5447 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5448 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5450 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5453 case OP_LOADR8_MEMBASE:
5454 /* This is generated by the local regalloc pass which runs after the lowering pass */
5455 if (!arm_is_fpimm8 (ins->inst_offset)) {
5456 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5457 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5458 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5460 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5463 case OP_STORER4_MEMBASE_REG:
5464 g_assert (arm_is_fpimm8 (ins->inst_offset));
5466 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5468 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5469 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5470 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5471 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5474 case OP_LOADR4_MEMBASE:
5476 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5478 g_assert (arm_is_fpimm8 (ins->inst_offset));
5479 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5480 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5481 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5482 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5485 case OP_ICONV_TO_R_UN: {
5486 g_assert_not_reached ();
5489 case OP_ICONV_TO_R4:
5491 ARM_FMSR (code, ins->dreg, ins->sreg1);
5492 ARM_FSITOS (code, ins->dreg, ins->dreg);
5494 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5495 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5496 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5497 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5498 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5501 case OP_ICONV_TO_R8:
5502 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5503 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5504 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5505 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5509 MonoType *sig_ret = mini_type_get_underlying_type (NULL, mono_method_signature (cfg->method)->ret);
5510 if (sig_ret->type == MONO_TYPE_R4) {
5512 g_assert (!IS_HARD_FLOAT);
5513 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5515 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5518 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5522 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5524 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5528 case OP_FCONV_TO_I1:
5529 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5531 case OP_FCONV_TO_U1:
5532 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5534 case OP_FCONV_TO_I2:
5535 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5537 case OP_FCONV_TO_U2:
5538 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5540 case OP_FCONV_TO_I4:
5542 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5544 case OP_FCONV_TO_U4:
5546 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5548 case OP_FCONV_TO_I8:
5549 case OP_FCONV_TO_U8:
5550 g_assert_not_reached ();
5551 /* Implemented as helper calls */
5553 case OP_LCONV_TO_R_UN:
5554 g_assert_not_reached ();
5555 /* Implemented as helper calls */
5557 case OP_LCONV_TO_OVF_I4_2: {
5558 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5560 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5563 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5564 high_bit_not_set = code;
5565 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5567 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5568 valid_negative = code;
5569 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5570 invalid_negative = code;
5571 ARM_B_COND (code, ARMCOND_AL, 0);
5573 arm_patch (high_bit_not_set, code);
5575 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5576 valid_positive = code;
5577 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5579 arm_patch (invalid_negative, code);
5580 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5582 arm_patch (valid_negative, code);
5583 arm_patch (valid_positive, code);
5585 if (ins->dreg != ins->sreg1)
5586 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5590 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5593 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5596 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5599 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5602 ARM_NEGD (code, ins->dreg, ins->sreg1);
5606 g_assert_not_reached ();
5610 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5616 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5621 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5624 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5625 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5629 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5632 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5633 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5637 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5640 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5641 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5642 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5646 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5649 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5650 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5654 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5657 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5658 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5659 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5663 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5666 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5667 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5671 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5674 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5675 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5679 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5682 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5683 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5686 /* ARM FPA flags table:
5687 * N Less than ARMCOND_MI
5688 * Z Equal ARMCOND_EQ
5689 * C Greater Than or Equal ARMCOND_CS
5690 * V Unordered ARMCOND_VS
5693 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5696 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5699 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5702 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5703 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5709 g_assert_not_reached ();
5713 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5715 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5716 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5717 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5721 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5722 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5727 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5728 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5730 #ifdef USE_JUMP_TABLES
5732 gpointer *jte = mono_jumptable_add_entries (2);
5733 jte [0] = GUINT_TO_POINTER (0xffffffff);
5734 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5735 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5736 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5739 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5740 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5742 *(guint32*)code = 0xffffffff;
5744 *(guint32*)code = 0x7fefffff;
5747 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5749 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5750 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5752 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5753 ARM_CPYD (code, ins->dreg, ins->sreg1);
5755 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5756 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5761 case OP_RCONV_TO_I1:
5762 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5764 case OP_RCONV_TO_U1:
5765 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5767 case OP_RCONV_TO_I2:
5768 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5770 case OP_RCONV_TO_U2:
5771 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5773 case OP_RCONV_TO_I4:
5774 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5776 case OP_RCONV_TO_U4:
5777 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5779 case OP_RCONV_TO_R4:
5781 if (ins->dreg != ins->sreg1)
5782 ARM_CPYS (code, ins->dreg, ins->sreg1);
5784 case OP_RCONV_TO_R8:
5786 ARM_CVTS (code, ins->dreg, ins->sreg1);
5789 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5792 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5795 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5798 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5801 ARM_NEGS (code, ins->dreg, ins->sreg1);
5805 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5808 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5809 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5813 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5816 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5817 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5821 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5824 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5825 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5826 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5830 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5833 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5834 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5838 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5841 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5842 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5843 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5847 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5850 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5851 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5855 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5858 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5859 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5863 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5866 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5867 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5870 case OP_GC_LIVENESS_DEF:
5871 case OP_GC_LIVENESS_USE:
5872 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5873 ins->backend.pc_offset = code - cfg->native_code;
5875 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5876 ins->backend.pc_offset = code - cfg->native_code;
5877 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5881 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5882 g_assert_not_reached ();
5885 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5886 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5887 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5888 g_assert_not_reached ();
5894 last_offset = offset;
5897 cfg->code_len = code - cfg->native_code;
5900 #endif /* DISABLE_JIT */
5902 #ifdef HAVE_AEABI_READ_TP
5903 void __aeabi_read_tp (void);
5907 mono_arch_register_lowlevel_calls (void)
5909 /* The signature doesn't matter */
5910 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5911 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5913 #ifndef MONO_CROSS_COMPILE
5914 #ifdef HAVE_AEABI_READ_TP
5915 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
5920 #define patch_lis_ori(ip,val) do {\
5921 guint16 *__lis_ori = (guint16*)(ip); \
5922 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5923 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5927 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5929 MonoJumpInfo *patch_info;
5930 gboolean compile_aot = !run_cctors;
5932 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5933 unsigned char *ip = patch_info->ip.i + code;
5934 const unsigned char *target;
5936 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
5937 #ifdef USE_JUMP_TABLES
5938 gpointer *jt = mono_jumptable_get_entry (ip);
5940 gpointer *jt = (gpointer*)(ip + 8);
5943 /* jt is the inlined jump table, 2 instructions after ip
5944 * In the normal case we store the absolute addresses,
5945 * otherwise the displacements.
5947 for (i = 0; i < patch_info->data.table->table_size; i++)
5948 jt [i] = code + (int)patch_info->data.table->table [i];
5953 switch (patch_info->type) {
5954 case MONO_PATCH_INFO_BB:
5955 case MONO_PATCH_INFO_LABEL:
5958 /* No need to patch these */
5963 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5965 switch (patch_info->type) {
5966 case MONO_PATCH_INFO_IP:
5967 g_assert_not_reached ();
5968 patch_lis_ori (ip, ip);
5970 case MONO_PATCH_INFO_METHOD_REL:
5971 g_assert_not_reached ();
5972 *((gpointer *)(ip)) = code + patch_info->data.offset;
5974 case MONO_PATCH_INFO_METHODCONST:
5975 case MONO_PATCH_INFO_CLASS:
5976 case MONO_PATCH_INFO_IMAGE:
5977 case MONO_PATCH_INFO_FIELD:
5978 case MONO_PATCH_INFO_VTABLE:
5979 case MONO_PATCH_INFO_IID:
5980 case MONO_PATCH_INFO_SFLDA:
5981 case MONO_PATCH_INFO_LDSTR:
5982 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5983 case MONO_PATCH_INFO_LDTOKEN:
5984 g_assert_not_reached ();
5985 /* from OP_AOTCONST : lis + ori */
5986 patch_lis_ori (ip, target);
5988 case MONO_PATCH_INFO_R4:
5989 case MONO_PATCH_INFO_R8:
5990 g_assert_not_reached ();
5991 *((gconstpointer *)(ip + 2)) = patch_info->data.target;
5993 case MONO_PATCH_INFO_EXC_NAME:
5994 g_assert_not_reached ();
5995 *((gconstpointer *)(ip + 1)) = patch_info->data.name;
5997 case MONO_PATCH_INFO_NONE:
5998 case MONO_PATCH_INFO_BB_OVF:
5999 case MONO_PATCH_INFO_EXC_OVF:
6000 /* everything is dealt with at epilog output time */
6005 arm_patch_general (domain, ip, target, dyn_code_mp);
6012 * Stack frame layout:
6014 * ------------------- fp
6015 * MonoLMF structure or saved registers
6016 * -------------------
6018 * -------------------
6020 * -------------------
6021 * optional 8 bytes for tracing
6022 * -------------------
6023 * param area size is cfg->param_area
6024 * ------------------- sp
6027 mono_arch_emit_prolog (MonoCompile *cfg)
6029 MonoMethod *method = cfg->method;
6031 MonoMethodSignature *sig;
6033 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount;
6038 int prev_sp_offset, reg_offset;
6040 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6043 sig = mono_method_signature (method);
6044 cfg->code_size = 256 + sig->param_count * 64;
6045 code = cfg->native_code = g_malloc (cfg->code_size);
6047 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6049 alloc_size = cfg->stack_offset;
6055 * The iphone uses R7 as the frame pointer, and it points at the saved
6060 * We can't use r7 as a frame pointer since it points into the middle of
6061 * the frame, so we keep using our own frame pointer.
6062 * FIXME: Optimize this.
6064 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6065 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6066 prev_sp_offset += 8; /* r7 and lr */
6067 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6068 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6071 if (!method->save_lmf) {
6073 /* No need to push LR again */
6074 if (cfg->used_int_regs)
6075 ARM_PUSH (code, cfg->used_int_regs);
6077 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6078 prev_sp_offset += 4;
6080 for (i = 0; i < 16; ++i) {
6081 if (cfg->used_int_regs & (1 << i))
6082 prev_sp_offset += 4;
6084 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6086 for (i = 0; i < 16; ++i) {
6087 if ((cfg->used_int_regs & (1 << i))) {
6088 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6089 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6094 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6095 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6097 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6098 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6101 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6102 ARM_PUSH (code, 0x5ff0);
6103 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6104 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6106 for (i = 0; i < 16; ++i) {
6107 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6108 /* The original r7 is saved at the start */
6109 if (!(iphone_abi && i == ARMREG_R7))
6110 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6114 g_assert (reg_offset == 4 * 10);
6115 pos += sizeof (MonoLMF) - (4 * 10);
6119 orig_alloc_size = alloc_size;
6120 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6121 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6122 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6123 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6126 /* the stack used in the pushed regs */
6127 if (prev_sp_offset & 4)
6129 cfg->stack_usage = alloc_size;
6131 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6132 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6134 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6135 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6137 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6139 if (cfg->frame_reg != ARMREG_SP) {
6140 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6141 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6143 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6144 prev_sp_offset += alloc_size;
6146 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6147 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6149 /* compute max_offset in order to use short forward jumps
6150 * we could skip do it on arm because the immediate displacement
6151 * for jumps is large enough, it may be useful later for constant pools
6154 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6155 MonoInst *ins = bb->code;
6156 bb->max_offset = max_offset;
6158 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6161 MONO_BB_FOR_EACH_INS (bb, ins)
6162 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6165 /* store runtime generic context */
6166 if (cfg->rgctx_var) {
6167 MonoInst *ins = cfg->rgctx_var;
6169 g_assert (ins->opcode == OP_REGOFFSET);
6171 if (arm_is_imm12 (ins->inst_offset)) {
6172 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6174 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6175 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6179 /* load arguments allocated to register from the stack */
6182 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
6184 if (cinfo->vtype_retaddr) {
6185 ArgInfo *ainfo = &cinfo->ret;
6186 inst = cfg->vret_addr;
6187 g_assert (arm_is_imm12 (inst->inst_offset));
6188 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6191 if (sig->call_convention == MONO_CALL_VARARG) {
6192 ArgInfo *cookie = &cinfo->sig_cookie;
6194 /* Save the sig cookie address */
6195 g_assert (cookie->storage == RegTypeBase);
6197 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6198 g_assert (arm_is_imm12 (cfg->sig_cookie));
6199 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6200 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6203 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6204 ArgInfo *ainfo = cinfo->args + i;
6205 inst = cfg->args [pos];
6207 if (cfg->verbose_level > 2)
6208 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6209 if (inst->opcode == OP_REGVAR) {
6210 if (ainfo->storage == RegTypeGeneral)
6211 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6212 else if (ainfo->storage == RegTypeFP) {
6213 g_assert_not_reached ();
6214 } else if (ainfo->storage == RegTypeBase) {
6215 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6216 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6218 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6219 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6222 g_assert_not_reached ();
6224 if (cfg->verbose_level > 2)
6225 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6227 /* the argument should be put on the stack: FIXME handle size != word */
6228 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeGSharedVtInReg) {
6229 switch (ainfo->size) {
6231 if (arm_is_imm12 (inst->inst_offset))
6232 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6234 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6235 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6239 if (arm_is_imm8 (inst->inst_offset)) {
6240 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6242 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6243 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6247 if (arm_is_imm12 (inst->inst_offset)) {
6248 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6250 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6251 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6253 if (arm_is_imm12 (inst->inst_offset + 4)) {
6254 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6256 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6257 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6261 if (arm_is_imm12 (inst->inst_offset)) {
6262 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6264 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6265 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6269 } else if (ainfo->storage == RegTypeBaseGen) {
6270 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6271 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6273 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6274 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6276 if (arm_is_imm12 (inst->inst_offset + 4)) {
6277 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6278 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6280 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6281 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6282 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6283 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6285 } else if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeGSharedVtOnStack) {
6286 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6287 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6289 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6290 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6293 switch (ainfo->size) {
6295 if (arm_is_imm8 (inst->inst_offset)) {
6296 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6298 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6299 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6303 if (arm_is_imm8 (inst->inst_offset)) {
6304 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6306 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6307 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6311 if (arm_is_imm12 (inst->inst_offset)) {
6312 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6314 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6315 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6317 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6318 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6320 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6321 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6323 if (arm_is_imm12 (inst->inst_offset + 4)) {
6324 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6326 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6327 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6331 if (arm_is_imm12 (inst->inst_offset)) {
6332 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6334 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6335 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6339 } else if (ainfo->storage == RegTypeFP) {
6340 int imm8, rot_amount;
6342 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6343 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6344 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6346 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6348 if (ainfo->size == 8)
6349 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6351 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6352 } else if (ainfo->storage == RegTypeStructByVal) {
6353 int doffset = inst->inst_offset;
6357 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
6358 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6359 if (arm_is_imm12 (doffset)) {
6360 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6362 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6363 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6365 soffset += sizeof (gpointer);
6366 doffset += sizeof (gpointer);
6368 if (ainfo->vtsize) {
6369 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6370 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6371 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6373 } else if (ainfo->storage == RegTypeStructByAddr) {
6374 g_assert_not_reached ();
6375 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6376 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6378 g_assert_not_reached ();
6383 if (method->save_lmf)
6384 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6387 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6389 if (cfg->arch.seq_point_info_var) {
6390 MonoInst *ins = cfg->arch.seq_point_info_var;
6392 /* Initialize the variable from a GOT slot */
6393 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6394 #ifdef USE_JUMP_TABLES
6396 gpointer *jte = mono_jumptable_add_entry ();
6397 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6398 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6400 /** XXX: is it correct? */
6402 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6404 *(gpointer*)code = NULL;
6407 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6409 g_assert (ins->opcode == OP_REGOFFSET);
6411 if (arm_is_imm12 (ins->inst_offset)) {
6412 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6414 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6415 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6419 /* Initialize ss_trigger_page_var */
6420 if (!cfg->soft_breakpoints) {
6421 MonoInst *info_var = cfg->arch.seq_point_info_var;
6422 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6423 int dreg = ARMREG_LR;
6426 g_assert (info_var->opcode == OP_REGOFFSET);
6427 g_assert (arm_is_imm12 (info_var->inst_offset));
6429 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6430 /* Load the trigger page addr */
6431 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6432 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6436 if (cfg->arch.seq_point_read_var) {
6437 MonoInst *read_ins = cfg->arch.seq_point_read_var;
6438 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6439 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6440 #ifdef USE_JUMP_TABLES
6443 g_assert (read_ins->opcode == OP_REGOFFSET);
6444 g_assert (arm_is_imm12 (read_ins->inst_offset));
6445 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6446 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6447 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6448 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6450 #ifdef USE_JUMP_TABLES
6451 jte = mono_jumptable_add_entries (3);
6452 jte [0] = (gpointer)&ss_trigger_var;
6453 jte [1] = single_step_func_wrapper;
6454 jte [2] = breakpoint_func_wrapper;
6455 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6457 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6459 *(volatile int **)code = &ss_trigger_var;
6461 *(gpointer*)code = single_step_func_wrapper;
6463 *(gpointer*)code = breakpoint_func_wrapper;
6467 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6468 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
6469 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6470 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6471 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
6472 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6475 cfg->code_len = code - cfg->native_code;
6476 g_assert (cfg->code_len < cfg->code_size);
6483 mono_arch_emit_epilog (MonoCompile *cfg)
6485 MonoMethod *method = cfg->method;
6486 int pos, i, rot_amount;
6487 int max_epilog_size = 16 + 20*4;
6491 if (cfg->method->save_lmf)
6492 max_epilog_size += 128;
6494 if (mono_jit_trace_calls != NULL)
6495 max_epilog_size += 50;
6497 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6498 max_epilog_size += 50;
6500 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6501 cfg->code_size *= 2;
6502 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6503 cfg->stat_code_reallocs++;
6507 * Keep in sync with OP_JMP
6509 code = cfg->native_code + cfg->code_len;
6511 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6512 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6516 /* Load returned vtypes into registers if needed */
6517 cinfo = cfg->arch.cinfo;
6518 if (cinfo->ret.storage == RegTypeStructByVal) {
6519 MonoInst *ins = cfg->ret;
6521 if (arm_is_imm12 (ins->inst_offset)) {
6522 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6524 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6525 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6529 if (method->save_lmf) {
6530 int lmf_offset, reg, sp_adj, regmask;
6531 /* all but r0-r3, sp and pc */
6532 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6535 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6537 /* This points to r4 inside MonoLMF->iregs */
6538 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6540 regmask = 0x9ff0; /* restore lr to pc */
6541 /* Skip caller saved registers not used by the method */
6542 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6543 regmask &= ~(1 << reg);
6548 /* Restored later */
6549 regmask &= ~(1 << ARMREG_PC);
6550 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6551 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6553 ARM_POP (code, regmask);
6555 /* Restore saved r7, restore LR to PC */
6556 /* Skip lr from the lmf */
6557 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6558 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6561 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6562 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6564 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6565 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6569 /* Restore saved gregs */
6570 if (cfg->used_int_regs)
6571 ARM_POP (code, cfg->used_int_regs);
6572 /* Restore saved r7, restore LR to PC */
6573 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6575 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6579 cfg->code_len = code - cfg->native_code;
6581 g_assert (cfg->code_len < cfg->code_size);
6586 mono_arch_emit_exceptions (MonoCompile *cfg)
6588 MonoJumpInfo *patch_info;
6591 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6592 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6593 int max_epilog_size = 50;
6595 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6596 exc_throw_pos [i] = NULL;
6597 exc_throw_found [i] = 0;
6600 /* count the number of exception infos */
6603 * make sure we have enough space for exceptions
6605 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6606 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6607 i = mini_exception_id_by_name (patch_info->data.target);
6608 if (!exc_throw_found [i]) {
6609 max_epilog_size += 32;
6610 exc_throw_found [i] = TRUE;
6615 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6616 cfg->code_size *= 2;
6617 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6618 cfg->stat_code_reallocs++;
6621 code = cfg->native_code + cfg->code_len;
6623 /* add code to raise exceptions */
6624 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6625 switch (patch_info->type) {
6626 case MONO_PATCH_INFO_EXC: {
6627 MonoClass *exc_class;
6628 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6630 i = mini_exception_id_by_name (patch_info->data.target);
6631 if (exc_throw_pos [i]) {
6632 arm_patch (ip, exc_throw_pos [i]);
6633 patch_info->type = MONO_PATCH_INFO_NONE;
6636 exc_throw_pos [i] = code;
6638 arm_patch (ip, code);
6640 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6641 g_assert (exc_class);
6643 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6644 #ifdef USE_JUMP_TABLES
6646 gpointer *jte = mono_jumptable_add_entries (2);
6647 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6648 patch_info->data.name = "mono_arch_throw_corlib_exception";
6649 patch_info->ip.i = code - cfg->native_code;
6650 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6651 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6652 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6653 ARM_BLX_REG (code, ARMREG_IP);
6654 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6657 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6658 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6659 patch_info->data.name = "mono_arch_throw_corlib_exception";
6660 patch_info->ip.i = code - cfg->native_code;
6662 *(guint32*)(gpointer)code = exc_class->type_token;
6673 cfg->code_len = code - cfg->native_code;
6675 g_assert (cfg->code_len < cfg->code_size);
6679 #endif /* #ifndef DISABLE_JIT */
6682 mono_arch_finish_init (void)
6687 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6692 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6699 mono_arch_print_tree (MonoInst *tree, int arity)
6709 mono_arch_get_patch_offset (guint8 *code)
6716 mono_arch_flush_register_windows (void)
6723 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
6725 int method_reg = mono_alloc_ireg (cfg);
6726 #ifdef USE_JUMP_TABLES
6727 int use_jumptables = TRUE;
6729 int use_jumptables = FALSE;
6732 if (cfg->compile_aot) {
6735 call->dynamic_imt_arg = TRUE;
6738 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, method_reg, imt_arg->dreg);
6740 MONO_INST_NEW (cfg, ins, OP_AOTCONST);
6741 ins->dreg = method_reg;
6742 ins->inst_p0 = call->method;
6743 ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
6744 MONO_ADD_INS (cfg->cbb, ins);
6746 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
6747 } else if (cfg->generic_context || imt_arg || mono_use_llvm || use_jumptables) {
6748 /* Always pass in a register for simplicity */
6749 call->dynamic_imt_arg = TRUE;
6751 cfg->uses_rgctx_reg = TRUE;
6754 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, method_reg, imt_arg->dreg);
6758 MONO_INST_NEW (cfg, ins, OP_PCONST);
6759 ins->inst_p0 = call->method;
6760 ins->dreg = method_reg;
6761 MONO_ADD_INS (cfg->cbb, ins);
6764 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
6768 #endif /* DISABLE_JIT */
6771 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6773 #ifdef USE_JUMP_TABLES
6774 return (MonoMethod*)regs [ARMREG_V5];
6777 guint32 *code_ptr = (guint32*)code;
6779 method = GUINT_TO_POINTER (code_ptr [1]);
6783 return (MonoMethod*)regs [ARMREG_V5];
6785 /* The IMT value is stored in the code stream right after the LDC instruction. */
6786 /* This is no longer true for the gsharedvt_in trampoline */
6788 if (!IS_LDR_PC (code_ptr [0])) {
6789 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
6790 g_assert (IS_LDR_PC (code_ptr [0]));
6794 /* This is AOTed code, or the gsharedvt trampoline, the IMT method is in V5 */
6795 return (MonoMethod*)regs [ARMREG_V5];
6797 return (MonoMethod*) method;
6802 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6804 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6807 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6808 #define BASE_SIZE (6 * 4)
6809 #define BSEARCH_ENTRY_SIZE (4 * 4)
6810 #define CMP_SIZE (3 * 4)
6811 #define BRANCH_SIZE (1 * 4)
6812 #define CALL_SIZE (2 * 4)
6813 #define WMC_SIZE (8 * 4)
6814 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6816 #ifdef USE_JUMP_TABLES
6818 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6820 g_assert (base [index] == NULL);
6821 base [index] = value;
6824 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6826 if (arm_is_imm12 (jti * 4)) {
6827 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6829 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6830 if ((jti * 4) >> 16)
6831 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6832 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6838 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6840 guint32 delta = DISTANCE (target, code);
6842 g_assert (delta >= 0 && delta <= 0xFFF);
6843 *target = *target | delta;
6849 #ifdef ENABLE_WRONG_METHOD_CHECK
6851 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6853 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6859 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6860 gpointer fail_tramp)
6863 arminstr_t *code, *start;
6864 #ifdef USE_JUMP_TABLES
6867 gboolean large_offsets = FALSE;
6868 guint32 **constant_pool_starts;
6869 arminstr_t *vtable_target = NULL;
6870 int extra_space = 0;
6872 #ifdef ENABLE_WRONG_METHOD_CHECK
6877 #ifdef USE_JUMP_TABLES
6878 for (i = 0; i < count; ++i) {
6879 MonoIMTCheckItem *item = imt_entries [i];
6880 item->chunk_size += 4 * 16;
6881 if (!item->is_equals)
6882 imt_entries [item->check_target_idx]->compare_done = TRUE;
6883 size += item->chunk_size;
6886 constant_pool_starts = g_new0 (guint32*, count);
6888 for (i = 0; i < count; ++i) {
6889 MonoIMTCheckItem *item = imt_entries [i];
6890 if (item->is_equals) {
6891 gboolean fail_case = !item->check_target_idx && fail_tramp;
6893 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6894 item->chunk_size += 32;
6895 large_offsets = TRUE;
6898 if (item->check_target_idx || fail_case) {
6899 if (!item->compare_done || fail_case)
6900 item->chunk_size += CMP_SIZE;
6901 item->chunk_size += BRANCH_SIZE;
6903 #ifdef ENABLE_WRONG_METHOD_CHECK
6904 item->chunk_size += WMC_SIZE;
6908 item->chunk_size += 16;
6909 large_offsets = TRUE;
6911 item->chunk_size += CALL_SIZE;
6913 item->chunk_size += BSEARCH_ENTRY_SIZE;
6914 imt_entries [item->check_target_idx]->compare_done = TRUE;
6916 size += item->chunk_size;
6920 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6924 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6926 code = mono_domain_code_reserve (domain, size);
6930 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6931 for (i = 0; i < count; ++i) {
6932 MonoIMTCheckItem *item = imt_entries [i];
6933 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6937 #ifdef USE_JUMP_TABLES
6938 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6939 /* If jumptables we always pass the IMT method in R5 */
6940 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6941 #define VTABLE_JTI 0
6942 #define IMT_METHOD_OFFSET 0
6943 #define TARGET_CODE_OFFSET 1
6944 #define JUMP_CODE_OFFSET 2
6945 #define RECORDS_PER_ENTRY 3
6946 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
6947 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
6948 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
6950 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
6951 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
6952 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
6953 set_jumptable_element (jte, VTABLE_JTI, vtable);
6956 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6958 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6959 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6960 vtable_target = code;
6961 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6963 if (mono_use_llvm) {
6964 /* LLVM always passes the IMT method in R5 */
6965 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6967 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
6968 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
6969 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
6973 for (i = 0; i < count; ++i) {
6974 MonoIMTCheckItem *item = imt_entries [i];
6975 #ifdef USE_JUMP_TABLES
6976 guint32 imt_method_jti = 0, target_code_jti = 0;
6978 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6980 gint32 vtable_offset;
6982 item->code_target = (guint8*)code;
6984 if (item->is_equals) {
6985 gboolean fail_case = !item->check_target_idx && fail_tramp;
6987 if (item->check_target_idx || fail_case) {
6988 if (!item->compare_done || fail_case) {
6989 #ifdef USE_JUMP_TABLES
6990 imt_method_jti = IMT_METHOD_JTI (i);
6991 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
6994 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6996 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6998 #ifdef USE_JUMP_TABLES
6999 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7000 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7001 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7003 item->jmp_code = (guint8*)code;
7004 ARM_B_COND (code, ARMCOND_NE, 0);
7007 /*Enable the commented code to assert on wrong method*/
7008 #ifdef ENABLE_WRONG_METHOD_CHECK
7009 #ifdef USE_JUMP_TABLES
7010 imt_method_jti = IMT_METHOD_JTI (i);
7011 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7014 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7016 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7018 ARM_B_COND (code, ARMCOND_EQ, 0);
7020 /* Define this if your system is so bad that gdb is failing. */
7021 #ifdef BROKEN_DEV_ENV
7022 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7024 arm_patch (code - 1, mini_dump_bad_imt);
7028 arm_patch (cond, code);
7032 if (item->has_target_code) {
7033 /* Load target address */
7034 #ifdef USE_JUMP_TABLES
7035 target_code_jti = TARGET_CODE_JTI (i);
7036 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7037 /* Restore registers */
7038 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7040 ARM_BX (code, ARMREG_R1);
7041 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7043 target_code_ins = code;
7044 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7045 /* Save it to the fourth slot */
7046 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7047 /* Restore registers and branch */
7048 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7050 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7053 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7054 if (!arm_is_imm12 (vtable_offset)) {
7056 * We need to branch to a computed address but we don't have
7057 * a free register to store it, since IP must contain the
7058 * vtable address. So we push the two values to the stack, and
7059 * load them both using LDM.
7061 /* Compute target address */
7062 #ifdef USE_JUMP_TABLES
7063 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7064 if (vtable_offset >> 16)
7065 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7066 /* IP had vtable base. */
7067 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7068 /* Restore registers and branch */
7069 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7070 ARM_BX (code, ARMREG_IP);
7072 vtable_offset_ins = code;
7073 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7074 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7075 /* Save it to the fourth slot */
7076 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7077 /* Restore registers and branch */
7078 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7080 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7083 #ifdef USE_JUMP_TABLES
7084 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7085 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7086 ARM_BX (code, ARMREG_IP);
7088 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7090 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7091 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7097 #ifdef USE_JUMP_TABLES
7098 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7099 target_code_jti = TARGET_CODE_JTI (i);
7100 /* Load target address */
7101 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7102 /* Restore registers */
7103 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7105 ARM_BX (code, ARMREG_R1);
7106 set_jumptable_element (jte, target_code_jti, fail_tramp);
7108 arm_patch (item->jmp_code, (guchar*)code);
7110 target_code_ins = code;
7111 /* Load target address */
7112 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7113 /* Save it to the fourth slot */
7114 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7115 /* Restore registers and branch */
7116 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7118 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7120 item->jmp_code = NULL;
7123 #ifdef USE_JUMP_TABLES
7125 set_jumptable_element (jte, imt_method_jti, item->key);
7128 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7130 /*must emit after unconditional branch*/
7131 if (vtable_target) {
7132 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7133 item->chunk_size += 4;
7134 vtable_target = NULL;
7137 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7138 constant_pool_starts [i] = code;
7140 code += extra_space;
7145 #ifdef USE_JUMP_TABLES
7146 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7147 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7148 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7149 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7150 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7152 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7153 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7155 item->jmp_code = (guint8*)code;
7156 ARM_B_COND (code, ARMCOND_HS, 0);
7162 for (i = 0; i < count; ++i) {
7163 MonoIMTCheckItem *item = imt_entries [i];
7164 if (item->jmp_code) {
7165 if (item->check_target_idx)
7166 #ifdef USE_JUMP_TABLES
7167 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7169 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7172 if (i > 0 && item->is_equals) {
7174 #ifdef USE_JUMP_TABLES
7175 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7176 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7178 arminstr_t *space_start = constant_pool_starts [i];
7179 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7180 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7188 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7189 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7194 #ifndef USE_JUMP_TABLES
7195 g_free (constant_pool_starts);
7198 mono_arch_flush_icache ((guint8*)start, size);
7199 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7200 mono_stats.imt_thunks_size += code - start;
7202 g_assert (DISTANCE (start, code) <= size);
7207 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7209 return ctx->regs [reg];
7213 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7215 ctx->regs [reg] = val;
7219 * mono_arch_get_trampolines:
7221 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7225 mono_arch_get_trampolines (gboolean aot)
7227 return mono_arm_get_exception_trampolines (aot);
7231 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7238 bp = MONO_CONTEXT_GET_BP (ctx);
7239 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7241 old_value = *lr_loc;
7242 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7245 *lr_loc = new_value;
7250 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7252 * mono_arch_set_breakpoint:
7254 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7255 * The location should contain code emitted by OP_SEQ_POINT.
7258 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7261 guint32 native_offset = ip - (guint8*)ji->code_start;
7262 MonoDebugOptions *opt = mini_get_debug_options ();
7264 if (opt->soft_breakpoints) {
7265 g_assert (!ji->from_aot);
7267 ARM_BLX_REG (code, ARMREG_LR);
7268 mono_arch_flush_icache (code - 4, 4);
7269 } else if (ji->from_aot) {
7270 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7272 g_assert (native_offset % 4 == 0);
7273 g_assert (info->bp_addrs [native_offset / 4] == 0);
7274 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7276 int dreg = ARMREG_LR;
7278 /* Read from another trigger page */
7279 #ifdef USE_JUMP_TABLES
7280 gpointer *jte = mono_jumptable_add_entry ();
7281 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7282 jte [0] = bp_trigger_page;
7284 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7286 *(int*)code = (int)bp_trigger_page;
7289 ARM_LDR_IMM (code, dreg, dreg, 0);
7291 mono_arch_flush_icache (code - 16, 16);
7294 /* This is currently implemented by emitting an SWI instruction, which
7295 * qemu/linux seems to convert to a SIGILL.
7297 *(int*)code = (0xef << 24) | 8;
7299 mono_arch_flush_icache (code - 4, 4);
7305 * mono_arch_clear_breakpoint:
7307 * Clear the breakpoint at IP.
7310 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7312 MonoDebugOptions *opt = mini_get_debug_options ();
7316 if (opt->soft_breakpoints) {
7317 g_assert (!ji->from_aot);
7320 mono_arch_flush_icache (code - 4, 4);
7321 } else if (ji->from_aot) {
7322 guint32 native_offset = ip - (guint8*)ji->code_start;
7323 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7325 g_assert (native_offset % 4 == 0);
7326 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7327 info->bp_addrs [native_offset / 4] = 0;
7329 for (i = 0; i < 4; ++i)
7332 mono_arch_flush_icache (ip, code - ip);
7337 * mono_arch_start_single_stepping:
7339 * Start single stepping.
7342 mono_arch_start_single_stepping (void)
7344 if (ss_trigger_page)
7345 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7351 * mono_arch_stop_single_stepping:
7353 * Stop single stepping.
7356 mono_arch_stop_single_stepping (void)
7358 if (ss_trigger_page)
7359 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7365 #define DBG_SIGNAL SIGBUS
7367 #define DBG_SIGNAL SIGSEGV
7371 * mono_arch_is_single_step_event:
7373 * Return whenever the machine state in SIGCTX corresponds to a single
7377 mono_arch_is_single_step_event (void *info, void *sigctx)
7379 siginfo_t *sinfo = info;
7381 if (!ss_trigger_page)
7384 /* Sometimes the address is off by 4 */
7385 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7392 * mono_arch_is_breakpoint_event:
7394 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7397 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7399 siginfo_t *sinfo = info;
7401 if (!ss_trigger_page)
7404 if (sinfo->si_signo == DBG_SIGNAL) {
7405 /* Sometimes the address is off by 4 */
7406 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7416 * mono_arch_skip_breakpoint:
7418 * See mini-amd64.c for docs.
7421 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7423 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7427 * mono_arch_skip_single_step:
7429 * See mini-amd64.c for docs.
7432 mono_arch_skip_single_step (MonoContext *ctx)
7434 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7437 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7440 * mono_arch_get_seq_point_info:
7442 * See mini-amd64.c for docs.
7445 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7450 // FIXME: Add a free function
7452 mono_domain_lock (domain);
7453 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7455 mono_domain_unlock (domain);
7458 ji = mono_jit_info_table_find (domain, (char*)code);
7461 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7463 info->ss_trigger_page = ss_trigger_page;
7464 info->bp_trigger_page = bp_trigger_page;
7466 mono_domain_lock (domain);
7467 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7469 mono_domain_unlock (domain);
7476 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7478 ext->lmf.previous_lmf = prev_lmf;
7479 /* Mark that this is a MonoLMFExt */
7480 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7481 ext->lmf.sp = (gssize)ext;
7485 * mono_arch_set_target:
7487 * Set the target architecture the JIT backend should generate code for, in the form
7488 * of a GNU target triplet. Only used in AOT mode.
7491 mono_arch_set_target (char *mtriple)
7493 /* The GNU target triple format is not very well documented */
7494 if (strstr (mtriple, "armv7")) {
7495 v5_supported = TRUE;
7496 v6_supported = TRUE;
7497 v7_supported = TRUE;
7499 if (strstr (mtriple, "armv6")) {
7500 v5_supported = TRUE;
7501 v6_supported = TRUE;
7503 if (strstr (mtriple, "armv7s")) {
7504 v7s_supported = TRUE;
7506 if (strstr (mtriple, "thumbv7s")) {
7507 v5_supported = TRUE;
7508 v6_supported = TRUE;
7509 v7_supported = TRUE;
7510 v7s_supported = TRUE;
7511 thumb_supported = TRUE;
7512 thumb2_supported = TRUE;
7514 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7515 v5_supported = TRUE;
7516 v6_supported = TRUE;
7517 thumb_supported = TRUE;
7520 if (strstr (mtriple, "gnueabi"))
7521 eabi_supported = TRUE;
7525 mono_arch_opcode_supported (int opcode)
7528 case OP_ATOMIC_ADD_I4:
7529 case OP_ATOMIC_EXCHANGE_I4:
7530 case OP_ATOMIC_CAS_I4:
7531 case OP_ATOMIC_LOAD_I1:
7532 case OP_ATOMIC_LOAD_I2:
7533 case OP_ATOMIC_LOAD_I4:
7534 case OP_ATOMIC_LOAD_U1:
7535 case OP_ATOMIC_LOAD_U2:
7536 case OP_ATOMIC_LOAD_U4:
7537 case OP_ATOMIC_STORE_I1:
7538 case OP_ATOMIC_STORE_I2:
7539 case OP_ATOMIC_STORE_I4:
7540 case OP_ATOMIC_STORE_U1:
7541 case OP_ATOMIC_STORE_U2:
7542 case OP_ATOMIC_STORE_U4:
7543 return v7_supported;
7544 case OP_ATOMIC_LOAD_R4:
7545 case OP_ATOMIC_LOAD_R8:
7546 case OP_ATOMIC_STORE_R4:
7547 case OP_ATOMIC_STORE_R8:
7548 return v7_supported && IS_VFP;
7554 #if defined(ENABLE_GSHAREDVT)
7556 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7558 #endif /* !MONOTOUCH */