2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
24 #include "mini-arm-tls.h"
28 #include "debugger-agent.h"
30 #include "mono/arch/arm/arm-vfp-codegen.h"
32 #if defined(HAVE_KW_THREAD) && defined(__linux__) \
33 || defined(TARGET_ANDROID) \
34 || defined(TARGET_IOS)
38 /* Sanity check: This makes no sense */
39 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
40 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
44 * IS_SOFT_FLOAT: Is full software floating point used?
45 * IS_HARD_FLOAT: Is full hardware floating point used?
46 * IS_VFP: Is hardware floating point with software ABI used?
48 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
49 * IS_VFP may delegate to mono_arch_is_soft_float ().
52 #if defined(ARM_FPU_VFP_HARD)
53 #define IS_SOFT_FLOAT (FALSE)
54 #define IS_HARD_FLOAT (TRUE)
56 #elif defined(ARM_FPU_NONE)
57 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
58 #define IS_HARD_FLOAT (FALSE)
59 #define IS_VFP (!mono_arch_is_soft_float ())
61 #define IS_SOFT_FLOAT (FALSE)
62 #define IS_HARD_FLOAT (FALSE)
66 #define THUNK_SIZE (3 * 4)
68 #ifdef __native_client_codegen__
69 const guint kNaClAlignment = kNaClAlignmentARM;
70 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
71 gint8 nacl_align_byte = -1; /* 0xff */
74 mono_arch_nacl_pad (guint8 *code, int pad)
76 /* Not yet properly implemented. */
77 g_assert_not_reached ();
82 mono_arch_nacl_skip_nops (guint8 *code)
84 /* Not yet properly implemented. */
85 g_assert_not_reached ();
89 #endif /* __native_client_codegen__ */
91 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
94 void sys_icache_invalidate (void *start, size_t len);
97 /* This mutex protects architecture specific caches */
98 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
99 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
100 static mono_mutex_t mini_arch_mutex;
102 static gboolean v5_supported = FALSE;
103 static gboolean v6_supported = FALSE;
104 static gboolean v7_supported = FALSE;
105 static gboolean v7s_supported = FALSE;
106 static gboolean thumb_supported = FALSE;
107 static gboolean thumb2_supported = FALSE;
109 * Whenever to use the ARM EABI
111 static gboolean eabi_supported = FALSE;
114 * Whenever to use the iphone ABI extensions:
115 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
116 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
117 * This is required for debugging/profiling tools to work, but it has some overhead so it should
118 * only be turned on in debug builds.
120 static gboolean iphone_abi = FALSE;
123 * The FPU we are generating code for. This is NOT runtime configurable right now,
124 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
126 static MonoArmFPU arm_fpu;
128 #if defined(ARM_FPU_VFP_HARD)
130 * On armhf, d0-d7 are used for argument passing and d8-d15
131 * must be preserved across calls, which leaves us no room
132 * for scratch registers. So we use d14-d15 but back up their
133 * previous contents to a stack slot before using them - see
134 * mono_arm_emit_vfp_scratch_save/_restore ().
136 static int vfp_scratch1 = ARM_VFP_D14;
137 static int vfp_scratch2 = ARM_VFP_D15;
140 * On armel, d0-d7 do not need to be preserved, so we can
141 * freely make use of them as scratch registers.
143 static int vfp_scratch1 = ARM_VFP_D0;
144 static int vfp_scratch2 = ARM_VFP_D1;
149 static volatile int ss_trigger_var = 0;
151 static gpointer single_step_tramp, breakpoint_tramp;
154 * The code generated for sequence points reads from this location, which is
155 * made read-only when single stepping is enabled.
157 static gpointer ss_trigger_page;
159 /* Enabled breakpoints read from this trigger page */
160 static gpointer bp_trigger_page;
164 * floating point support: on ARM it is a mess, there are at least 3
165 * different setups, each of which binary incompat with the other.
166 * 1) FPA: old and ugly, but unfortunately what current distros use
167 * the double binary format has the two words swapped. 8 double registers.
168 * Implemented usually by kernel emulation.
169 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
170 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
171 * 3) VFP: the new and actually sensible and useful FP support. Implemented
172 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
174 * We do not care about FPA. We will support soft float and VFP.
176 int mono_exc_esp_offset = 0;
178 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
179 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
180 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
182 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
183 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
184 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
186 //#define DEBUG_IMT 0
189 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
193 mono_arch_regname (int reg)
195 static const char * rnames[] = {
196 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
197 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
198 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
201 if (reg >= 0 && reg < 16)
207 mono_arch_fregname (int reg)
209 static const char * rnames[] = {
210 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
211 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
212 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
213 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
214 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
215 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
218 if (reg >= 0 && reg < 32)
226 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
228 int imm8, rot_amount;
229 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
230 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
234 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
235 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
237 code = mono_arm_emit_load_imm (code, dreg, imm);
238 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
243 /* If dreg == sreg, this clobbers IP */
245 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
247 int imm8, rot_amount;
248 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
249 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
253 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
254 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
256 code = mono_arm_emit_load_imm (code, dreg, imm);
257 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
263 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
265 /* we can use r0-r3, since this is called only for incoming args on the stack */
266 if (size > sizeof (gpointer) * 4) {
268 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
269 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
270 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
271 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
272 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
273 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
274 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
275 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
276 ARM_B_COND (code, ARMCOND_NE, 0);
277 arm_patch (code - 4, start_loop);
280 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
281 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
283 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
284 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
290 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
291 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
292 doffset = soffset = 0;
294 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
295 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
301 g_assert (size == 0);
306 emit_call_reg (guint8 *code, int reg)
309 ARM_BLX_REG (code, reg);
311 #ifdef USE_JUMP_TABLES
312 g_assert_not_reached ();
314 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
318 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
324 emit_call_seq (MonoCompile *cfg, guint8 *code)
326 #ifdef USE_JUMP_TABLES
327 code = mono_arm_patchable_bl (code, ARMCOND_AL);
329 if (cfg->method->dynamic) {
330 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
332 *(gpointer*)code = NULL;
334 code = emit_call_reg (code, ARMREG_IP);
338 cfg->thunk_area += THUNK_SIZE;
344 mono_arm_patchable_b (guint8 *code, int cond)
346 #ifdef USE_JUMP_TABLES
349 jte = mono_jumptable_add_entry ();
350 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
351 ARM_BX_COND (code, cond, ARMREG_IP);
353 ARM_B_COND (code, cond, 0);
359 mono_arm_patchable_bl (guint8 *code, int cond)
361 #ifdef USE_JUMP_TABLES
364 jte = mono_jumptable_add_entry ();
365 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
366 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
368 ARM_BL_COND (code, cond, 0);
373 #ifdef USE_JUMP_TABLES
375 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
377 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
378 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
383 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
385 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
386 ARM_LDR_IMM (code, reg, reg, 0);
392 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
395 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
396 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
398 code = emit_call_seq (cfg, code);
399 if (dreg != ARMREG_R0)
400 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
402 g_assert_not_reached ();
408 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
411 if (tls_offset_reg != ARMREG_R0)
412 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
413 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
415 code = emit_call_seq (cfg, code);
416 if (dreg != ARMREG_R0)
417 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
419 g_assert_not_reached ();
425 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
428 if (sreg != ARMREG_R1)
429 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
430 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
431 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
433 code = emit_call_seq (cfg, code);
435 g_assert_not_reached ();
441 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
444 /* Get sreg in R1 and tls_offset_reg in R0 */
445 if (tls_offset_reg == ARMREG_R1) {
446 if (sreg == ARMREG_R0) {
447 /* swap sreg and tls_offset_reg */
448 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
449 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
450 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
452 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
453 if (sreg != ARMREG_R1)
454 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
457 if (sreg != ARMREG_R1)
458 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
459 if (tls_offset_reg != ARMREG_R0)
460 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
462 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
464 code = emit_call_seq (cfg, code);
466 g_assert_not_reached ();
474 * Emit code to push an LMF structure on the LMF stack.
475 * On arm, this is intermixed with the initialization of other fields of the structure.
478 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
480 gboolean get_lmf_fast = FALSE;
483 if (mono_arm_have_tls_get ()) {
485 if (cfg->compile_aot) {
487 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
488 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
490 *(gpointer*)code = NULL;
492 /* Load the value from the GOT */
493 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
494 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
496 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
497 g_assert (lmf_addr_tls_offset != -1);
498 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
503 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
504 (gpointer)"mono_get_lmf_addr");
505 code = emit_call_seq (cfg, code);
507 /* we build the MonoLMF structure on the stack - see mini-arm.h */
508 /* lmf_offset is the offset from the previous stack pointer,
509 * alloc_size is the total stack space allocated, so the offset
510 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
511 * The pointer to the struct is put in r1 (new_lmf).
512 * ip is used as scratch
513 * The callee-saved registers are already in the MonoLMF structure
515 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
516 /* r0 is the result from mono_get_lmf_addr () */
517 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
518 /* new_lmf->previous_lmf = *lmf_addr */
519 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
520 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
521 /* *(lmf_addr) = r1 */
522 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
523 /* Skip method (only needed for trampoline LMF frames) */
524 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
525 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
526 /* save the current IP */
527 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
528 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
530 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
531 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
542 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
546 g_assert (!cfg->r4fp);
548 for (list = inst->float_args; list; list = list->next) {
549 FloatArgData *fad = list->data;
550 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
551 gboolean imm = arm_is_fpimm8 (var->inst_offset);
553 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
559 if (*offset + *max_len > cfg->code_size) {
560 cfg->code_size += *max_len;
561 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
563 code = cfg->native_code + *offset;
567 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
568 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
570 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
572 *offset = code - cfg->native_code;
579 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
583 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
585 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
588 if (!arm_is_fpimm8 (inst->inst_offset)) {
589 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
590 ARM_FSTD (code, reg, ARMREG_LR, 0);
592 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
599 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
603 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
605 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
608 if (!arm_is_fpimm8 (inst->inst_offset)) {
609 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
610 ARM_FLDD (code, reg, ARMREG_LR, 0);
612 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
621 * Emit code to pop an LMF structure from the LMF stack.
624 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
628 if (lmf_offset < 32) {
629 basereg = cfg->frame_reg;
634 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
637 /* ip = previous_lmf */
638 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
640 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
641 /* *(lmf_addr) = previous_lmf */
642 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
647 #endif /* #ifndef DISABLE_JIT */
649 #ifndef MONO_CROSS_COMPILE
651 mono_arm_have_fast_tls (void)
653 if (mini_get_debug_options ()->arm_use_fallback_tls)
655 #if (defined(HAVE_KW_THREAD) && defined(__linux__)) \
656 || defined(TARGET_ANDROID)
657 guint32* kuser_get_tls = (void*)0xffff0fe0;
658 guint32 expected [] = {0xee1d0f70, 0xe12fff1e};
660 /* Expecting mrc + bx lr in the kuser_get_tls kernel helper */
661 return memcmp (kuser_get_tls, expected, 8) == 0;
662 #elif defined(TARGET_IOS)
663 guint32 expected [] = {0x1f70ee1d, 0x0103f021, 0x0020f851, 0xbf004770};
664 /* Discard thumb bit */
665 guint32* pthread_getspecific_addr = (guint32*) ((guint32)pthread_getspecific & 0xfffffffe);
666 return memcmp ((void*)pthread_getspecific_addr, expected, 16) == 0;
674 * mono_arm_have_tls_get:
676 * Returns whether we have tls access implemented on the current
680 mono_arm_have_tls_get (void)
690 * mono_arch_get_argument_info:
691 * @csig: a method signature
692 * @param_count: the number of parameters to consider
693 * @arg_info: an array to store the result infos
695 * Gathers information on parameters such as size, alignment and
696 * padding. arg_info should be large enought to hold param_count + 1 entries.
698 * Returns the size of the activation frame.
701 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
703 int k, frame_size = 0;
704 guint32 size, align, pad;
708 t = mini_get_underlying_type (csig->ret);
709 if (MONO_TYPE_ISSTRUCT (t)) {
710 frame_size += sizeof (gpointer);
714 arg_info [0].offset = offset;
717 frame_size += sizeof (gpointer);
721 arg_info [0].size = frame_size;
723 for (k = 0; k < param_count; k++) {
724 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
726 /* ignore alignment for now */
729 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
730 arg_info [k].pad = pad;
732 arg_info [k + 1].pad = 0;
733 arg_info [k + 1].size = size;
735 arg_info [k + 1].offset = offset;
739 align = MONO_ARCH_FRAME_ALIGNMENT;
740 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
741 arg_info [k].pad = pad;
746 #define MAX_ARCH_DELEGATE_PARAMS 3
749 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
751 guint8 *code, *start;
752 GSList *unwind_ops = mono_arch_get_cie_program ();
755 start = code = mono_global_codeman_reserve (12);
757 /* Replace the this argument with the target */
758 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
759 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
760 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
762 g_assert ((code - start) <= 12);
764 mono_arch_flush_icache (start, 12);
768 size = 8 + param_count * 4;
769 start = code = mono_global_codeman_reserve (size);
771 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
772 /* slide down the arguments */
773 for (i = 0; i < param_count; ++i) {
774 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
776 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
778 g_assert ((code - start) <= size);
780 mono_arch_flush_icache (start, size);
784 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
786 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
787 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
791 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
797 * mono_arch_get_delegate_invoke_impls:
799 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
803 mono_arch_get_delegate_invoke_impls (void)
809 get_delegate_invoke_impl (&info, TRUE, 0);
810 res = g_slist_prepend (res, info);
812 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
813 get_delegate_invoke_impl (&info, FALSE, i);
814 res = g_slist_prepend (res, info);
821 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
823 guint8 *code, *start;
826 /* FIXME: Support more cases */
827 sig_ret = mini_get_underlying_type (sig->ret);
828 if (MONO_TYPE_ISSTRUCT (sig_ret))
832 static guint8* cached = NULL;
833 mono_mini_arch_lock ();
835 mono_mini_arch_unlock ();
840 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
843 start = get_delegate_invoke_impl (&info, TRUE, 0);
844 mono_tramp_info_register (info, NULL);
847 mono_mini_arch_unlock ();
850 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
853 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
855 for (i = 0; i < sig->param_count; ++i)
856 if (!mono_is_regsize_var (sig->params [i]))
859 mono_mini_arch_lock ();
860 code = cache [sig->param_count];
862 mono_mini_arch_unlock ();
867 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
868 start = mono_aot_get_trampoline (name);
872 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
873 mono_tramp_info_register (info, NULL);
875 cache [sig->param_count] = start;
876 mono_mini_arch_unlock ();
884 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
890 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
892 return (gpointer)regs [ARMREG_R0];
896 * Initialize the cpu to execute managed code.
899 mono_arch_cpu_init (void)
901 i8_align = MONO_ABI_ALIGNOF (gint64);
902 #ifdef MONO_CROSS_COMPILE
903 /* Need to set the alignment of i8 since it can different on the target */
904 #ifdef TARGET_ANDROID
906 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
912 * Initialize architecture specific code.
915 mono_arch_init (void)
917 const char *cpu_arch;
919 mono_mutex_init_recursive (&mini_arch_mutex);
920 if (mini_get_debug_options ()->soft_breakpoints) {
921 single_step_tramp = mini_get_single_step_trampoline ();
922 breakpoint_tramp = mini_get_breakpoint_trampoline ();
924 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
925 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
926 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
929 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
930 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
931 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
932 #if defined(ENABLE_GSHAREDVT)
933 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
935 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
937 #if defined(__ARM_EABI__)
938 eabi_supported = TRUE;
941 #if defined(ARM_FPU_VFP_HARD)
942 arm_fpu = MONO_ARM_FPU_VFP_HARD;
944 arm_fpu = MONO_ARM_FPU_VFP;
946 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
948 * If we're compiling with a soft float fallback and it
949 * turns out that no VFP unit is available, we need to
950 * switch to soft float. We don't do this for iOS, since
951 * iOS devices always have a VFP unit.
953 if (!mono_hwcap_arm_has_vfp)
954 arm_fpu = MONO_ARM_FPU_NONE;
957 * This environment variable can be useful in testing
958 * environments to make sure the soft float fallback
959 * works. Most ARM devices have VFP units these days, so
960 * normally soft float code would not be exercised much.
962 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
964 if (soft && !strncmp (soft, "1", 1))
965 arm_fpu = MONO_ARM_FPU_NONE;
969 v5_supported = mono_hwcap_arm_is_v5;
970 v6_supported = mono_hwcap_arm_is_v6;
971 v7_supported = mono_hwcap_arm_is_v7;
972 v7s_supported = mono_hwcap_arm_is_v7s;
974 #if defined(__APPLE__)
975 /* iOS is special-cased here because we don't yet
976 have a way to properly detect CPU features on it. */
977 thumb_supported = TRUE;
980 thumb_supported = mono_hwcap_arm_has_thumb;
981 thumb2_supported = mono_hwcap_arm_has_thumb2;
984 /* Format: armv(5|6|7[s])[-thumb[2]] */
985 cpu_arch = g_getenv ("MONO_CPU_ARCH");
987 /* Do this here so it overrides any detection. */
989 if (strncmp (cpu_arch, "armv", 4) == 0) {
990 v5_supported = cpu_arch [4] >= '5';
991 v6_supported = cpu_arch [4] >= '6';
992 v7_supported = cpu_arch [4] >= '7';
993 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
996 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
997 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
1002 * Cleanup architecture specific code.
1005 mono_arch_cleanup (void)
1010 * This function returns the optimizations supported on this cpu.
1013 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1015 /* no arm-specific optimizations yet */
1021 * This function test for all SIMD functions supported.
1023 * Returns a bitmask corresponding to all supported versions.
1027 mono_arch_cpu_enumerate_simd_versions (void)
1029 /* SIMD is currently unimplemented */
1037 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1039 if (v7s_supported) {
1053 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1055 mono_arch_is_soft_float (void)
1057 return arm_fpu == MONO_ARM_FPU_NONE;
1062 mono_arm_is_hard_float (void)
1064 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1068 is_regsize_var (MonoType *t)
1072 t = mini_get_underlying_type (t);
1079 case MONO_TYPE_FNPTR:
1081 case MONO_TYPE_OBJECT:
1082 case MONO_TYPE_STRING:
1083 case MONO_TYPE_CLASS:
1084 case MONO_TYPE_SZARRAY:
1085 case MONO_TYPE_ARRAY:
1087 case MONO_TYPE_GENERICINST:
1088 if (!mono_type_generic_inst_is_valuetype (t))
1091 case MONO_TYPE_VALUETYPE:
1098 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1103 for (i = 0; i < cfg->num_varinfo; i++) {
1104 MonoInst *ins = cfg->varinfo [i];
1105 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1108 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1111 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1114 /* we can only allocate 32 bit values */
1115 if (is_regsize_var (ins->inst_vtype)) {
1116 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1117 g_assert (i == vmv->idx);
1118 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1126 mono_arch_get_global_int_regs (MonoCompile *cfg)
1130 mono_arch_compute_omit_fp (cfg);
1133 * FIXME: Interface calls might go through a static rgctx trampoline which
1134 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1137 if (cfg->flags & MONO_CFG_HAS_CALLS)
1138 cfg->uses_rgctx_reg = TRUE;
1140 if (cfg->arch.omit_fp)
1141 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1142 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1143 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1144 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1146 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1147 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1149 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1150 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1151 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1152 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1153 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1154 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1160 * mono_arch_regalloc_cost:
1162 * Return the cost, in number of memory references, of the action of
1163 * allocating the variable VMV into a register during global register
1167 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1173 #endif /* #ifndef DISABLE_JIT */
1175 #ifndef __GNUC_PREREQ
1176 #define __GNUC_PREREQ(maj, min) (0)
1180 mono_arch_flush_icache (guint8 *code, gint size)
1182 #if defined(__native_client__)
1183 // For Native Client we don't have to flush i-cache here,
1184 // as it's being done by dyncode interface.
1187 #ifdef MONO_CROSS_COMPILE
1189 sys_icache_invalidate (code, size);
1190 #elif __GNUC_PREREQ(4, 3)
1191 __builtin___clear_cache (code, code + size);
1192 #elif __GNUC_PREREQ(4, 1)
1193 __clear_cache (code, code + size);
1194 #elif defined(PLATFORM_ANDROID)
1195 const int syscall = 0xf0002;
1203 : "r" (code), "r" (code + size), "r" (syscall)
1204 : "r0", "r1", "r7", "r2"
1207 __asm __volatile ("mov r0, %0\n"
1210 "swi 0x9f0002 @ sys_cacheflush"
1212 : "r" (code), "r" (code + size), "r" (0)
1213 : "r0", "r1", "r3" );
1215 #endif /* !__native_client__ */
1220 /* Passed/returned in an ireg */
1222 /* Passed/returned in a pair of iregs */
1224 /* Passed on the stack */
1226 /* First word in r3, second word on the stack */
1228 /* FP value passed in either an ireg or a vfp reg */
1231 RegTypeStructByAddr,
1232 /* gsharedvt argument passed by addr in greg */
1233 RegTypeGSharedVtInReg,
1234 /* gsharedvt argument passed by addr on stack */
1235 RegTypeGSharedVtOnStack,
1241 guint16 vtsize; /* in param area */
1249 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1254 guint32 stack_usage;
1255 /* The index of the vret arg in the argument list for RegTypeStructByAddr */
1265 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1268 if (*gr > ARMREG_R3) {
1270 ainfo->offset = *stack_size;
1271 ainfo->reg = ARMREG_SP; /* in the caller */
1272 ainfo->storage = RegTypeBase;
1275 ainfo->storage = RegTypeGeneral;
1282 split = i8_align == 4;
1287 if (*gr == ARMREG_R3 && split) {
1288 /* first word in r3 and the second on the stack */
1289 ainfo->offset = *stack_size;
1290 ainfo->reg = ARMREG_SP; /* in the caller */
1291 ainfo->storage = RegTypeBaseGen;
1293 } else if (*gr >= ARMREG_R3) {
1294 if (eabi_supported) {
1295 /* darwin aligns longs to 4 byte only */
1296 if (i8_align == 8) {
1301 ainfo->offset = *stack_size;
1302 ainfo->reg = ARMREG_SP; /* in the caller */
1303 ainfo->storage = RegTypeBase;
1306 if (eabi_supported) {
1307 if (i8_align == 8 && ((*gr) & 1))
1310 ainfo->storage = RegTypeIRegPair;
1319 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1322 * If we're calling a function like this:
1324 * void foo(float a, double b, float c)
1326 * We pass a in s0 and b in d1. That leaves us
1327 * with s1 being unused. The armhf ABI recognizes
1328 * this and requires register assignment to then
1329 * use that for the next single-precision arg,
1330 * i.e. c in this example. So float_spare either
1331 * tells us which reg to use for the next single-
1332 * precision arg, or it's -1, meaning use *fpr.
1334 * Note that even though most of the JIT speaks
1335 * double-precision, fpr represents single-
1336 * precision registers.
1338 * See parts 5.5 and 6.1.2 of the AAPCS for how
1342 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1343 ainfo->storage = RegTypeFP;
1347 * If we're passing a double-precision value
1348 * and *fpr is odd (e.g. it's s1, s3, ...)
1349 * we need to use the next even register. So
1350 * we mark the current *fpr as a spare that
1351 * can be used for the next single-precision
1355 *float_spare = *fpr;
1360 * At this point, we have an even register
1361 * so we assign that and move along.
1365 } else if (*float_spare >= 0) {
1367 * We're passing a single-precision value
1368 * and it looks like a spare single-
1369 * precision register is available. Let's
1373 ainfo->reg = *float_spare;
1377 * If we hit this branch, we're passing a
1378 * single-precision value and we can simply
1379 * use the next available register.
1387 * We've exhausted available floating point
1388 * regs, so pass the rest on the stack.
1396 ainfo->offset = *stack_size;
1397 ainfo->reg = ARMREG_SP;
1398 ainfo->storage = RegTypeBase;
1405 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1409 MonoClassField *field;
1410 MonoType *ftype, *prev_ftype = NULL;
1413 klass = mono_class_from_mono_type (t);
1415 while ((field = mono_class_get_fields (klass, &iter))) {
1416 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1418 ftype = mono_field_get_type (field);
1419 ftype = mini_get_underlying_type (ftype);
1421 if (MONO_TYPE_ISSTRUCT (ftype)) {
1422 int nested_nfields, nested_esize;
1424 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1426 if (nested_esize == 4)
1427 ftype = &mono_defaults.single_class->byval_arg;
1429 ftype = &mono_defaults.double_class->byval_arg;
1430 if (prev_ftype && prev_ftype->type != ftype->type)
1433 nfields += nested_nfields;
1435 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1437 if (prev_ftype && prev_ftype->type != ftype->type)
1443 if (nfields == 0 || nfields > 4)
1445 *out_nfields = nfields;
1446 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1451 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1453 guint i, gr, fpr, pstart;
1455 int n = sig->hasthis + sig->param_count;
1459 guint32 stack_size = 0;
1461 gboolean is_pinvoke = sig->pinvoke;
1462 gboolean vtype_retaddr = FALSE;
1465 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1467 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1474 t = mini_get_underlying_type (sig->ret);
1485 case MONO_TYPE_FNPTR:
1486 case MONO_TYPE_CLASS:
1487 case MONO_TYPE_OBJECT:
1488 case MONO_TYPE_SZARRAY:
1489 case MONO_TYPE_ARRAY:
1490 case MONO_TYPE_STRING:
1491 cinfo->ret.storage = RegTypeGeneral;
1492 cinfo->ret.reg = ARMREG_R0;
1496 cinfo->ret.storage = RegTypeIRegPair;
1497 cinfo->ret.reg = ARMREG_R0;
1501 cinfo->ret.storage = RegTypeFP;
1503 if (t->type == MONO_TYPE_R4)
1504 cinfo->ret.size = 4;
1506 cinfo->ret.size = 8;
1508 if (IS_HARD_FLOAT) {
1509 cinfo->ret.reg = ARM_VFP_F0;
1511 cinfo->ret.reg = ARMREG_R0;
1514 case MONO_TYPE_GENERICINST:
1515 if (!mono_type_generic_inst_is_valuetype (t)) {
1516 cinfo->ret.storage = RegTypeGeneral;
1517 cinfo->ret.reg = ARMREG_R0;
1520 if (mini_is_gsharedvt_variable_type (t)) {
1521 cinfo->ret.storage = RegTypeStructByAddr;
1525 case MONO_TYPE_VALUETYPE:
1526 case MONO_TYPE_TYPEDBYREF:
1527 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1528 cinfo->ret.storage = RegTypeHFA;
1530 cinfo->ret.nregs = nfields;
1531 cinfo->ret.esize = esize;
1533 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1534 cinfo->ret.storage = RegTypeStructByVal;
1536 cinfo->ret.storage = RegTypeStructByAddr;
1540 case MONO_TYPE_MVAR:
1541 g_assert (mini_is_gsharedvt_type (t));
1542 cinfo->ret.storage = RegTypeStructByAddr;
1544 case MONO_TYPE_VOID:
1547 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1550 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1555 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1556 * the first argument, allowing 'this' to be always passed in the first arg reg.
1557 * Also do this if the first argument is a reference type, since virtual calls
1558 * are sometimes made using calli without sig->hasthis set, like in the delegate
1561 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1563 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1565 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1569 cinfo->ret.reg = gr;
1571 cinfo->vret_arg_index = 1;
1575 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1578 if (vtype_retaddr) {
1579 cinfo->ret.reg = gr;
1584 DEBUG(printf("params: %d\n", sig->param_count));
1585 for (i = pstart; i < sig->param_count; ++i) {
1586 ArgInfo *ainfo = &cinfo->args [n];
1588 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1589 /* Prevent implicit arguments and sig_cookie from
1590 being passed in registers */
1593 /* Emit the signature cookie just before the implicit arguments */
1594 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1596 DEBUG(printf("param %d: ", i));
1597 if (sig->params [i]->byref) {
1598 DEBUG(printf("byref\n"));
1599 add_general (&gr, &stack_size, ainfo, TRUE);
1603 t = mini_get_underlying_type (sig->params [i]);
1607 cinfo->args [n].size = 1;
1608 add_general (&gr, &stack_size, ainfo, TRUE);
1612 cinfo->args [n].size = 2;
1613 add_general (&gr, &stack_size, ainfo, TRUE);
1617 cinfo->args [n].size = 4;
1618 add_general (&gr, &stack_size, ainfo, TRUE);
1623 case MONO_TYPE_FNPTR:
1624 case MONO_TYPE_CLASS:
1625 case MONO_TYPE_OBJECT:
1626 case MONO_TYPE_STRING:
1627 case MONO_TYPE_SZARRAY:
1628 case MONO_TYPE_ARRAY:
1629 cinfo->args [n].size = sizeof (gpointer);
1630 add_general (&gr, &stack_size, ainfo, TRUE);
1632 case MONO_TYPE_GENERICINST:
1633 if (!mono_type_generic_inst_is_valuetype (t)) {
1634 cinfo->args [n].size = sizeof (gpointer);
1635 add_general (&gr, &stack_size, ainfo, TRUE);
1638 if (mini_is_gsharedvt_variable_type (t)) {
1639 /* gsharedvt arguments are passed by ref */
1640 g_assert (mini_is_gsharedvt_type (t));
1641 add_general (&gr, &stack_size, ainfo, TRUE);
1642 switch (ainfo->storage) {
1643 case RegTypeGeneral:
1644 ainfo->storage = RegTypeGSharedVtInReg;
1647 ainfo->storage = RegTypeGSharedVtOnStack;
1650 g_assert_not_reached ();
1655 case MONO_TYPE_TYPEDBYREF:
1656 case MONO_TYPE_VALUETYPE: {
1659 int nwords, nfields, esize;
1662 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1663 if (fpr + nfields < ARM_VFP_F16) {
1664 ainfo->storage = RegTypeHFA;
1666 ainfo->nregs = nfields;
1667 ainfo->esize = esize;
1675 if (t->type == MONO_TYPE_TYPEDBYREF) {
1676 size = sizeof (MonoTypedRef);
1677 align = sizeof (gpointer);
1679 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1681 size = mono_class_native_size (klass, &align);
1683 size = mini_type_stack_size_full (t, &align, FALSE);
1685 DEBUG(printf ("load %d bytes struct\n", size));
1688 align_size += (sizeof (gpointer) - 1);
1689 align_size &= ~(sizeof (gpointer) - 1);
1690 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1691 ainfo->storage = RegTypeStructByVal;
1692 ainfo->struct_size = size;
1693 /* FIXME: align stack_size if needed */
1694 if (eabi_supported) {
1695 if (align >= 8 && (gr & 1))
1698 if (gr > ARMREG_R3) {
1700 ainfo->vtsize = nwords;
1702 int rest = ARMREG_R3 - gr + 1;
1703 int n_in_regs = rest >= nwords? nwords: rest;
1705 ainfo->size = n_in_regs;
1706 ainfo->vtsize = nwords - n_in_regs;
1709 nwords -= n_in_regs;
1711 if (sig->call_convention == MONO_CALL_VARARG)
1712 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1713 stack_size = ALIGN_TO (stack_size, align);
1714 ainfo->offset = stack_size;
1715 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1716 stack_size += nwords * sizeof (gpointer);
1722 add_general (&gr, &stack_size, ainfo, FALSE);
1728 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1730 add_general (&gr, &stack_size, ainfo, TRUE);
1736 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1738 add_general (&gr, &stack_size, ainfo, FALSE);
1741 case MONO_TYPE_MVAR:
1742 /* gsharedvt arguments are passed by ref */
1743 g_assert (mini_is_gsharedvt_type (t));
1744 add_general (&gr, &stack_size, ainfo, TRUE);
1745 switch (ainfo->storage) {
1746 case RegTypeGeneral:
1747 ainfo->storage = RegTypeGSharedVtInReg;
1750 ainfo->storage = RegTypeGSharedVtOnStack;
1753 g_assert_not_reached ();
1757 g_error ("Can't handle 0x%x", sig->params [i]->type);
1762 /* Handle the case where there are no implicit arguments */
1763 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1764 /* Prevent implicit arguments and sig_cookie from
1765 being passed in registers */
1768 /* Emit the signature cookie just before the implicit arguments */
1769 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1772 /* align stack size to 8 */
1773 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1774 stack_size = (stack_size + 7) & ~7;
1776 cinfo->stack_usage = stack_size;
1782 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1784 MonoType *callee_ret;
1788 c1 = get_call_info (NULL, caller_sig);
1789 c2 = get_call_info (NULL, callee_sig);
1792 * Tail calls with more callee stack usage than the caller cannot be supported, since
1793 * the extra stack space would be left on the stack after the tail call.
1795 res = c1->stack_usage >= c2->stack_usage;
1796 callee_ret = mini_get_underlying_type (callee_sig->ret);
1797 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1798 /* An address on the callee's stack is passed as the first argument */
1801 if (c2->stack_usage > 16 * 4)
1813 debug_omit_fp (void)
1816 return mono_debug_count ();
1823 * mono_arch_compute_omit_fp:
1825 * Determine whenever the frame pointer can be eliminated.
1828 mono_arch_compute_omit_fp (MonoCompile *cfg)
1830 MonoMethodSignature *sig;
1831 MonoMethodHeader *header;
1835 if (cfg->arch.omit_fp_computed)
1838 header = cfg->header;
1840 sig = mono_method_signature (cfg->method);
1842 if (!cfg->arch.cinfo)
1843 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1844 cinfo = cfg->arch.cinfo;
1847 * FIXME: Remove some of the restrictions.
1849 cfg->arch.omit_fp = TRUE;
1850 cfg->arch.omit_fp_computed = TRUE;
1852 if (cfg->disable_omit_fp)
1853 cfg->arch.omit_fp = FALSE;
1854 if (!debug_omit_fp ())
1855 cfg->arch.omit_fp = FALSE;
1857 if (cfg->method->save_lmf)
1858 cfg->arch.omit_fp = FALSE;
1860 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1861 cfg->arch.omit_fp = FALSE;
1862 if (header->num_clauses)
1863 cfg->arch.omit_fp = FALSE;
1864 if (cfg->param_area)
1865 cfg->arch.omit_fp = FALSE;
1866 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1867 cfg->arch.omit_fp = FALSE;
1868 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1869 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1870 cfg->arch.omit_fp = FALSE;
1871 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1872 ArgInfo *ainfo = &cinfo->args [i];
1874 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1876 * The stack offset can only be determined when the frame
1879 cfg->arch.omit_fp = FALSE;
1884 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1885 MonoInst *ins = cfg->varinfo [i];
1888 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1893 * Set var information according to the calling convention. arm version.
1894 * The locals var stuff should most likely be split in another method.
1897 mono_arch_allocate_vars (MonoCompile *cfg)
1899 MonoMethodSignature *sig;
1900 MonoMethodHeader *header;
1903 int i, offset, size, align, curinst;
1908 sig = mono_method_signature (cfg->method);
1910 if (!cfg->arch.cinfo)
1911 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1912 cinfo = cfg->arch.cinfo;
1913 sig_ret = mini_get_underlying_type (sig->ret);
1915 mono_arch_compute_omit_fp (cfg);
1917 if (cfg->arch.omit_fp)
1918 cfg->frame_reg = ARMREG_SP;
1920 cfg->frame_reg = ARMREG_FP;
1922 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1924 /* allow room for the vararg method args: void* and long/double */
1925 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1926 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1928 header = cfg->header;
1930 /* See mono_arch_get_global_int_regs () */
1931 if (cfg->flags & MONO_CFG_HAS_CALLS)
1932 cfg->uses_rgctx_reg = TRUE;
1934 if (cfg->frame_reg != ARMREG_SP)
1935 cfg->used_int_regs |= 1 << cfg->frame_reg;
1937 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1938 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1939 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1943 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1944 if (sig_ret->type != MONO_TYPE_VOID) {
1945 cfg->ret->opcode = OP_REGVAR;
1946 cfg->ret->inst_c0 = ARMREG_R0;
1949 /* local vars are at a positive offset from the stack pointer */
1951 * also note that if the function uses alloca, we use FP
1952 * to point at the local variables.
1954 offset = 0; /* linkage area */
1955 /* align the offset to 16 bytes: not sure this is needed here */
1957 //offset &= ~(8 - 1);
1959 /* add parameter area size for called functions */
1960 offset += cfg->param_area;
1963 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1966 /* allow room to save the return value */
1967 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1970 switch (cinfo->ret.storage) {
1971 case RegTypeStructByVal:
1972 cfg->ret->opcode = OP_REGOFFSET;
1973 cfg->ret->inst_basereg = cfg->frame_reg;
1974 offset += sizeof (gpointer) - 1;
1975 offset &= ~(sizeof (gpointer) - 1);
1976 cfg->ret->inst_offset = - offset;
1977 offset += sizeof(gpointer);
1980 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1981 offset = ALIGN_TO (offset, 8);
1982 cfg->ret->opcode = OP_REGOFFSET;
1983 cfg->ret->inst_basereg = cfg->frame_reg;
1984 cfg->ret->inst_offset = offset;
1988 case RegTypeStructByAddr:
1989 ins = cfg->vret_addr;
1990 offset += sizeof(gpointer) - 1;
1991 offset &= ~(sizeof(gpointer) - 1);
1992 ins->inst_offset = offset;
1993 ins->opcode = OP_REGOFFSET;
1994 ins->inst_basereg = cfg->frame_reg;
1995 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1996 printf ("vret_addr =");
1997 mono_print_ins (cfg->vret_addr);
1999 offset += sizeof(gpointer);
2005 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
2006 if (cfg->arch.seq_point_info_var) {
2009 ins = cfg->arch.seq_point_info_var;
2013 offset += align - 1;
2014 offset &= ~(align - 1);
2015 ins->opcode = OP_REGOFFSET;
2016 ins->inst_basereg = cfg->frame_reg;
2017 ins->inst_offset = offset;
2020 ins = cfg->arch.ss_trigger_page_var;
2023 offset += align - 1;
2024 offset &= ~(align - 1);
2025 ins->opcode = OP_REGOFFSET;
2026 ins->inst_basereg = cfg->frame_reg;
2027 ins->inst_offset = offset;
2031 if (cfg->arch.seq_point_read_var) {
2034 ins = cfg->arch.seq_point_read_var;
2038 offset += align - 1;
2039 offset &= ~(align - 1);
2040 ins->opcode = OP_REGOFFSET;
2041 ins->inst_basereg = cfg->frame_reg;
2042 ins->inst_offset = offset;
2045 ins = cfg->arch.seq_point_ss_method_var;
2048 offset += align - 1;
2049 offset &= ~(align - 1);
2050 ins->opcode = OP_REGOFFSET;
2051 ins->inst_basereg = cfg->frame_reg;
2052 ins->inst_offset = offset;
2055 ins = cfg->arch.seq_point_bp_method_var;
2058 offset += align - 1;
2059 offset &= ~(align - 1);
2060 ins->opcode = OP_REGOFFSET;
2061 ins->inst_basereg = cfg->frame_reg;
2062 ins->inst_offset = offset;
2066 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
2067 /* Allocate a temporary used by the atomic ops */
2071 /* Allocate a local slot to hold the sig cookie address */
2072 offset += align - 1;
2073 offset &= ~(align - 1);
2074 cfg->arch.atomic_tmp_offset = offset;
2077 cfg->arch.atomic_tmp_offset = -1;
2080 cfg->locals_min_stack_offset = offset;
2082 curinst = cfg->locals_start;
2083 for (i = curinst; i < cfg->num_varinfo; ++i) {
2086 ins = cfg->varinfo [i];
2087 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
2090 t = ins->inst_vtype;
2091 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
2094 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
2095 * pinvoke wrappers when they call functions returning structure */
2096 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2097 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
2101 size = mono_type_size (t, &align);
2103 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2104 * since it loads/stores misaligned words, which don't do the right thing.
2106 if (align < 4 && size >= 4)
2108 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2109 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2110 offset += align - 1;
2111 offset &= ~(align - 1);
2112 ins->opcode = OP_REGOFFSET;
2113 ins->inst_offset = offset;
2114 ins->inst_basereg = cfg->frame_reg;
2116 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2119 cfg->locals_max_stack_offset = offset;
2123 ins = cfg->args [curinst];
2124 if (ins->opcode != OP_REGVAR) {
2125 ins->opcode = OP_REGOFFSET;
2126 ins->inst_basereg = cfg->frame_reg;
2127 offset += sizeof (gpointer) - 1;
2128 offset &= ~(sizeof (gpointer) - 1);
2129 ins->inst_offset = offset;
2130 offset += sizeof (gpointer);
2135 if (sig->call_convention == MONO_CALL_VARARG) {
2139 /* Allocate a local slot to hold the sig cookie address */
2140 offset += align - 1;
2141 offset &= ~(align - 1);
2142 cfg->sig_cookie = offset;
2146 for (i = 0; i < sig->param_count; ++i) {
2147 ainfo = cinfo->args + i;
2149 ins = cfg->args [curinst];
2151 switch (ainfo->storage) {
2153 offset = ALIGN_TO (offset, 8);
2154 ins->opcode = OP_REGOFFSET;
2155 ins->inst_basereg = cfg->frame_reg;
2156 /* These arguments are saved to the stack in the prolog */
2157 ins->inst_offset = offset;
2158 if (cfg->verbose_level >= 2)
2159 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2167 if (ins->opcode != OP_REGVAR) {
2168 ins->opcode = OP_REGOFFSET;
2169 ins->inst_basereg = cfg->frame_reg;
2170 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2172 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2173 * since it loads/stores misaligned words, which don't do the right thing.
2175 if (align < 4 && size >= 4)
2177 /* The code in the prolog () stores words when storing vtypes received in a register */
2178 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2180 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2181 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2182 offset += align - 1;
2183 offset &= ~(align - 1);
2184 ins->inst_offset = offset;
2190 /* align the offset to 8 bytes */
2191 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2192 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2197 cfg->stack_offset = offset;
2201 mono_arch_create_vars (MonoCompile *cfg)
2203 MonoMethodSignature *sig;
2207 sig = mono_method_signature (cfg->method);
2209 if (!cfg->arch.cinfo)
2210 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2211 cinfo = cfg->arch.cinfo;
2213 if (IS_HARD_FLOAT) {
2214 for (i = 0; i < 2; i++) {
2215 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2216 inst->flags |= MONO_INST_VOLATILE;
2218 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2222 if (cinfo->ret.storage == RegTypeStructByVal)
2223 cfg->ret_var_is_local = TRUE;
2225 if (cinfo->ret.storage == RegTypeStructByAddr) {
2226 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2227 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2228 printf ("vret_addr = ");
2229 mono_print_ins (cfg->vret_addr);
2233 if (cfg->gen_sdb_seq_points) {
2234 if (cfg->soft_breakpoints) {
2235 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2236 ins->flags |= MONO_INST_VOLATILE;
2237 cfg->arch.seq_point_read_var = ins;
2239 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2240 ins->flags |= MONO_INST_VOLATILE;
2241 cfg->arch.seq_point_ss_method_var = ins;
2243 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2244 ins->flags |= MONO_INST_VOLATILE;
2245 cfg->arch.seq_point_bp_method_var = ins;
2247 g_assert (!cfg->compile_aot);
2248 } else if (cfg->compile_aot) {
2249 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2250 ins->flags |= MONO_INST_VOLATILE;
2251 cfg->arch.seq_point_info_var = ins;
2253 /* Allocate a separate variable for this to save 1 load per seq point */
2254 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2255 ins->flags |= MONO_INST_VOLATILE;
2256 cfg->arch.ss_trigger_page_var = ins;
2262 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2264 MonoMethodSignature *tmp_sig;
2267 if (call->tail_call)
2270 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2273 * mono_ArgIterator_Setup assumes the signature cookie is
2274 * passed first and all the arguments which were before it are
2275 * passed on the stack after the signature. So compensate by
2276 * passing a different signature.
2278 tmp_sig = mono_metadata_signature_dup (call->signature);
2279 tmp_sig->param_count -= call->signature->sentinelpos;
2280 tmp_sig->sentinelpos = 0;
2281 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2283 sig_reg = mono_alloc_ireg (cfg);
2284 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2286 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2291 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2296 LLVMCallInfo *linfo;
2298 n = sig->param_count + sig->hasthis;
2300 cinfo = get_call_info (cfg->mempool, sig);
2302 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2305 * LLVM always uses the native ABI while we use our own ABI, the
2306 * only difference is the handling of vtypes:
2307 * - we only pass/receive them in registers in some cases, and only
2308 * in 1 or 2 integer registers.
2310 switch (cinfo->ret.storage) {
2311 case RegTypeGeneral:
2314 case RegTypeIRegPair:
2316 case RegTypeStructByAddr:
2317 /* Vtype returned using a hidden argument */
2318 linfo->ret.storage = LLVMArgVtypeRetAddr;
2319 linfo->vret_arg_index = cinfo->vret_arg_index;
2322 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2323 cfg->disable_llvm = TRUE;
2327 for (i = 0; i < n; ++i) {
2328 ainfo = cinfo->args + i;
2330 linfo->args [i].storage = LLVMArgNone;
2332 switch (ainfo->storage) {
2333 case RegTypeGeneral:
2334 case RegTypeIRegPair:
2336 case RegTypeBaseGen:
2337 linfo->args [i].storage = LLVMArgInIReg;
2339 case RegTypeStructByVal:
2340 linfo->args [i].storage = LLVMArgAsIArgs;
2341 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2344 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2345 cfg->disable_llvm = TRUE;
2355 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2358 MonoMethodSignature *sig;
2362 sig = call->signature;
2363 n = sig->param_count + sig->hasthis;
2365 cinfo = get_call_info (cfg->mempool, sig);
2367 switch (cinfo->ret.storage) {
2368 case RegTypeStructByVal:
2369 /* The JIT will transform this into a normal call */
2370 call->vret_in_reg = TRUE;
2374 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2375 * the location pointed to by it after call in emit_move_return_value ().
2377 if (!cfg->arch.vret_addr_loc) {
2378 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2379 /* Prevent it from being register allocated or optimized away */
2380 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2383 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2385 case RegTypeStructByAddr: {
2387 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2388 vtarg->sreg1 = call->vret_var->dreg;
2389 vtarg->dreg = mono_alloc_preg (cfg);
2390 MONO_ADD_INS (cfg->cbb, vtarg);
2392 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2399 for (i = 0; i < n; ++i) {
2400 ArgInfo *ainfo = cinfo->args + i;
2403 if (i >= sig->hasthis)
2404 t = sig->params [i - sig->hasthis];
2406 t = &mono_defaults.int_class->byval_arg;
2407 t = mini_get_underlying_type (t);
2409 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2410 /* Emit the signature cookie just before the implicit arguments */
2411 emit_sig_cookie (cfg, call, cinfo);
2414 in = call->args [i];
2416 switch (ainfo->storage) {
2417 case RegTypeGeneral:
2418 case RegTypeIRegPair:
2419 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2420 MONO_INST_NEW (cfg, ins, OP_MOVE);
2421 ins->dreg = mono_alloc_ireg (cfg);
2422 ins->sreg1 = in->dreg + 1;
2423 MONO_ADD_INS (cfg->cbb, ins);
2424 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2426 MONO_INST_NEW (cfg, ins, OP_MOVE);
2427 ins->dreg = mono_alloc_ireg (cfg);
2428 ins->sreg1 = in->dreg + 2;
2429 MONO_ADD_INS (cfg->cbb, ins);
2430 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2431 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2432 if (ainfo->size == 4) {
2433 if (IS_SOFT_FLOAT) {
2434 /* mono_emit_call_args () have already done the r8->r4 conversion */
2435 /* The converted value is in an int vreg */
2436 MONO_INST_NEW (cfg, ins, OP_MOVE);
2437 ins->dreg = mono_alloc_ireg (cfg);
2438 ins->sreg1 = in->dreg;
2439 MONO_ADD_INS (cfg->cbb, ins);
2440 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2444 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2445 creg = mono_alloc_ireg (cfg);
2446 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2447 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2450 if (IS_SOFT_FLOAT) {
2451 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2452 ins->dreg = mono_alloc_ireg (cfg);
2453 ins->sreg1 = in->dreg;
2454 MONO_ADD_INS (cfg->cbb, ins);
2455 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2457 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2458 ins->dreg = mono_alloc_ireg (cfg);
2459 ins->sreg1 = in->dreg;
2460 MONO_ADD_INS (cfg->cbb, ins);
2461 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2465 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2466 creg = mono_alloc_ireg (cfg);
2467 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2468 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2469 creg = mono_alloc_ireg (cfg);
2470 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2471 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2474 cfg->flags |= MONO_CFG_HAS_FPOUT;
2476 MONO_INST_NEW (cfg, ins, OP_MOVE);
2477 ins->dreg = mono_alloc_ireg (cfg);
2478 ins->sreg1 = in->dreg;
2479 MONO_ADD_INS (cfg->cbb, ins);
2481 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2484 case RegTypeStructByAddr:
2487 /* FIXME: where si the data allocated? */
2488 arg->backend.reg3 = ainfo->reg;
2489 call->used_iregs |= 1 << ainfo->reg;
2490 g_assert_not_reached ();
2493 case RegTypeStructByVal:
2494 case RegTypeGSharedVtInReg:
2495 case RegTypeGSharedVtOnStack:
2497 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2498 ins->opcode = OP_OUTARG_VT;
2499 ins->sreg1 = in->dreg;
2500 ins->klass = in->klass;
2501 ins->inst_p0 = call;
2502 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2503 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2504 mono_call_inst_add_outarg_vt (cfg, call, ins);
2505 MONO_ADD_INS (cfg->cbb, ins);
2508 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2509 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2510 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2511 if (t->type == MONO_TYPE_R8) {
2512 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2515 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2517 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2520 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2523 case RegTypeBaseGen:
2524 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2525 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
2526 MONO_INST_NEW (cfg, ins, OP_MOVE);
2527 ins->dreg = mono_alloc_ireg (cfg);
2528 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
2529 MONO_ADD_INS (cfg->cbb, ins);
2530 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2531 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2534 /* This should work for soft-float as well */
2536 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2537 creg = mono_alloc_ireg (cfg);
2538 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2539 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2540 creg = mono_alloc_ireg (cfg);
2541 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2542 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2543 cfg->flags |= MONO_CFG_HAS_FPOUT;
2545 g_assert_not_reached ();
2549 int fdreg = mono_alloc_freg (cfg);
2551 if (ainfo->size == 8) {
2552 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2553 ins->sreg1 = in->dreg;
2555 MONO_ADD_INS (cfg->cbb, ins);
2557 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2562 * Mono's register allocator doesn't speak single-precision registers that
2563 * overlap double-precision registers (i.e. armhf). So we have to work around
2564 * the register allocator and load the value from memory manually.
2566 * So we create a variable for the float argument and an instruction to store
2567 * the argument into the variable. We then store the list of these arguments
2568 * in cfg->float_args. This list is then used by emit_float_args later to
2569 * pass the arguments in the various call opcodes.
2571 * This is not very nice, and we should really try to fix the allocator.
2574 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2576 /* Make sure the instruction isn't seen as pointless and removed.
2578 float_arg->flags |= MONO_INST_VOLATILE;
2580 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2582 /* We use the dreg to look up the instruction later. The hreg is used to
2583 * emit the instruction that loads the value into the FP reg.
2585 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2586 fad->vreg = float_arg->dreg;
2587 fad->hreg = ainfo->reg;
2589 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2592 call->used_iregs |= 1 << ainfo->reg;
2593 cfg->flags |= MONO_CFG_HAS_FPOUT;
2597 g_assert_not_reached ();
2601 /* Handle the case where there are no implicit arguments */
2602 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2603 emit_sig_cookie (cfg, call, cinfo);
2605 call->call_info = cinfo;
2606 call->stack_usage = cinfo->stack_usage;
2610 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2616 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2617 ins->dreg = mono_alloc_freg (cfg);
2618 ins->sreg1 = arg->dreg;
2619 MONO_ADD_INS (cfg->cbb, ins);
2620 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2623 g_assert_not_reached ();
2629 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2631 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2633 ArgInfo *ainfo = ins->inst_p1;
2634 int ovf_size = ainfo->vtsize;
2635 int doffset = ainfo->offset;
2636 int struct_size = ainfo->struct_size;
2637 int i, soffset, dreg, tmpreg;
2639 switch (ainfo->storage) {
2640 case RegTypeGSharedVtInReg:
2642 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2644 case RegTypeGSharedVtOnStack:
2645 /* Pass by addr on stack */
2646 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2649 for (i = 0; i < ainfo->nregs; ++i) {
2650 if (ainfo->esize == 4)
2651 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2653 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2654 load->dreg = mono_alloc_freg (cfg);
2655 load->inst_basereg = src->dreg;
2656 load->inst_offset = i * ainfo->esize;
2657 MONO_ADD_INS (cfg->cbb, load);
2659 if (ainfo->esize == 4) {
2662 /* See RegTypeFP in mono_arch_emit_call () */
2663 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2664 float_arg->flags |= MONO_INST_VOLATILE;
2665 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2667 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2668 fad->vreg = float_arg->dreg;
2669 fad->hreg = ainfo->reg + i;
2671 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2673 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + i, load);
2679 for (i = 0; i < ainfo->size; ++i) {
2680 dreg = mono_alloc_ireg (cfg);
2681 switch (struct_size) {
2683 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2686 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2689 tmpreg = mono_alloc_ireg (cfg);
2690 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2691 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2692 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2693 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2694 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2695 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2696 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2699 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2702 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2703 soffset += sizeof (gpointer);
2704 struct_size -= sizeof (gpointer);
2706 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2708 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2714 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2716 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2719 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2722 if (COMPILE_LLVM (cfg)) {
2723 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2725 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2726 ins->sreg1 = val->dreg + 1;
2727 ins->sreg2 = val->dreg + 2;
2728 MONO_ADD_INS (cfg->cbb, ins);
2733 case MONO_ARM_FPU_NONE:
2734 if (ret->type == MONO_TYPE_R8) {
2737 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2738 ins->dreg = cfg->ret->dreg;
2739 ins->sreg1 = val->dreg;
2740 MONO_ADD_INS (cfg->cbb, ins);
2743 if (ret->type == MONO_TYPE_R4) {
2744 /* Already converted to an int in method_to_ir () */
2745 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2749 case MONO_ARM_FPU_VFP:
2750 case MONO_ARM_FPU_VFP_HARD:
2751 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2754 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2755 ins->dreg = cfg->ret->dreg;
2756 ins->sreg1 = val->dreg;
2757 MONO_ADD_INS (cfg->cbb, ins);
2762 g_assert_not_reached ();
2766 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2769 #endif /* #ifndef DISABLE_JIT */
2772 mono_arch_is_inst_imm (gint64 imm)
2778 MonoMethodSignature *sig;
2781 MonoType **param_types;
2785 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2789 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2792 switch (cinfo->ret.storage) {
2794 case RegTypeGeneral:
2795 case RegTypeIRegPair:
2796 case RegTypeStructByAddr:
2807 for (i = 0; i < cinfo->nargs; ++i) {
2808 ArgInfo *ainfo = &cinfo->args [i];
2811 switch (ainfo->storage) {
2812 case RegTypeGeneral:
2813 case RegTypeIRegPair:
2814 case RegTypeBaseGen:
2817 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2820 case RegTypeStructByVal:
2821 if (ainfo->size == 0)
2822 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2824 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2825 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2833 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2834 for (i = 0; i < sig->param_count; ++i) {
2835 MonoType *t = sig->params [i];
2840 t = mini_get_underlying_type (t);
2863 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2865 ArchDynCallInfo *info;
2869 cinfo = get_call_info (NULL, sig);
2871 if (!dyn_call_supported (cinfo, sig)) {
2876 info = g_new0 (ArchDynCallInfo, 1);
2877 // FIXME: Preprocess the info to speed up start_dyn_call ()
2879 info->cinfo = cinfo;
2880 info->rtype = mini_get_underlying_type (sig->ret);
2881 info->param_types = g_new0 (MonoType*, sig->param_count);
2882 for (i = 0; i < sig->param_count; ++i)
2883 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2885 return (MonoDynCallInfo*)info;
2889 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2891 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2893 g_free (ainfo->cinfo);
2898 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2900 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2901 DynCallArgs *p = (DynCallArgs*)buf;
2902 int arg_index, greg, i, j, pindex;
2903 MonoMethodSignature *sig = dinfo->sig;
2905 g_assert (buf_len >= sizeof (DynCallArgs));
2914 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2915 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2920 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2921 p->regs [greg ++] = (mgreg_t)ret;
2923 for (i = pindex; i < sig->param_count; i++) {
2924 MonoType *t = dinfo->param_types [i];
2925 gpointer *arg = args [arg_index ++];
2926 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2929 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2931 } else if (ainfo->storage == RegTypeBase) {
2932 slot = PARAM_REGS + (ainfo->offset / 4);
2933 } else if (ainfo->storage == RegTypeBaseGen) {
2934 /* slot + 1 is the first stack slot, so the code below will work */
2937 g_assert_not_reached ();
2941 p->regs [slot] = (mgreg_t)*arg;
2946 case MONO_TYPE_STRING:
2947 case MONO_TYPE_CLASS:
2948 case MONO_TYPE_ARRAY:
2949 case MONO_TYPE_SZARRAY:
2950 case MONO_TYPE_OBJECT:
2954 p->regs [slot] = (mgreg_t)*arg;
2957 p->regs [slot] = *(guint8*)arg;
2960 p->regs [slot] = *(gint8*)arg;
2963 p->regs [slot] = *(gint16*)arg;
2966 p->regs [slot] = *(guint16*)arg;
2969 p->regs [slot] = *(gint32*)arg;
2972 p->regs [slot] = *(guint32*)arg;
2976 p->regs [slot ++] = (mgreg_t)arg [0];
2977 p->regs [slot] = (mgreg_t)arg [1];
2980 p->regs [slot] = *(mgreg_t*)arg;
2983 p->regs [slot ++] = (mgreg_t)arg [0];
2984 p->regs [slot] = (mgreg_t)arg [1];
2986 case MONO_TYPE_GENERICINST:
2987 if (MONO_TYPE_IS_REFERENCE (t)) {
2988 p->regs [slot] = (mgreg_t)*arg;
2991 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2992 MonoClass *klass = mono_class_from_mono_type (t);
2993 guint8 *nullable_buf;
2996 size = mono_class_value_size (klass, NULL);
2997 nullable_buf = g_alloca (size);
2998 g_assert (nullable_buf);
3000 /* The argument pointed to by arg is either a boxed vtype or null */
3001 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
3003 arg = (gpointer*)nullable_buf;
3009 case MONO_TYPE_VALUETYPE:
3010 g_assert (ainfo->storage == RegTypeStructByVal);
3012 if (ainfo->size == 0)
3013 slot = PARAM_REGS + (ainfo->offset / 4);
3017 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
3018 p->regs [slot ++] = ((mgreg_t*)arg) [j];
3021 g_assert_not_reached ();
3027 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
3029 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
3030 MonoType *ptype = ainfo->rtype;
3031 guint8 *ret = ((DynCallArgs*)buf)->ret;
3032 mgreg_t res = ((DynCallArgs*)buf)->res;
3033 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
3035 switch (ptype->type) {
3036 case MONO_TYPE_VOID:
3037 *(gpointer*)ret = NULL;
3039 case MONO_TYPE_STRING:
3040 case MONO_TYPE_CLASS:
3041 case MONO_TYPE_ARRAY:
3042 case MONO_TYPE_SZARRAY:
3043 case MONO_TYPE_OBJECT:
3047 *(gpointer*)ret = (gpointer)res;
3053 *(guint8*)ret = res;
3056 *(gint16*)ret = res;
3059 *(guint16*)ret = res;
3062 *(gint32*)ret = res;
3065 *(guint32*)ret = res;
3069 /* This handles endianness as well */
3070 ((gint32*)ret) [0] = res;
3071 ((gint32*)ret) [1] = res2;
3073 case MONO_TYPE_GENERICINST:
3074 if (MONO_TYPE_IS_REFERENCE (ptype)) {
3075 *(gpointer*)ret = (gpointer)res;
3080 case MONO_TYPE_VALUETYPE:
3081 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
3086 *(float*)ret = *(float*)&res;
3088 case MONO_TYPE_R8: {
3095 *(double*)ret = *(double*)®s;
3099 g_assert_not_reached ();
3106 * Allow tracing to work with this interface (with an optional argument)
3110 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3114 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3115 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3116 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3117 code = emit_call_reg (code, ARMREG_R2);
3131 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3134 int save_mode = SAVE_NONE;
3136 MonoMethod *method = cfg->method;
3137 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3138 int rtype = ret_type->type;
3139 int save_offset = cfg->param_area;
3143 offset = code - cfg->native_code;
3144 /* we need about 16 instructions */
3145 if (offset > (cfg->code_size - 16 * 4)) {
3146 cfg->code_size *= 2;
3147 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3148 code = cfg->native_code + offset;
3151 case MONO_TYPE_VOID:
3152 /* special case string .ctor icall */
3153 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3154 save_mode = SAVE_ONE;
3156 save_mode = SAVE_NONE;
3160 save_mode = SAVE_TWO;
3164 save_mode = SAVE_ONE_FP;
3166 save_mode = SAVE_ONE;
3170 save_mode = SAVE_TWO_FP;
3172 save_mode = SAVE_TWO;
3174 case MONO_TYPE_GENERICINST:
3175 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3176 save_mode = SAVE_ONE;
3180 case MONO_TYPE_VALUETYPE:
3181 save_mode = SAVE_STRUCT;
3184 save_mode = SAVE_ONE;
3188 switch (save_mode) {
3190 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3191 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3192 if (enable_arguments) {
3193 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3194 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3198 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3199 if (enable_arguments) {
3200 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3204 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3205 if (enable_arguments) {
3206 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3210 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3211 if (enable_arguments) {
3212 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3216 if (enable_arguments) {
3217 /* FIXME: get the actual address */
3218 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3226 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3227 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3228 code = emit_call_reg (code, ARMREG_IP);
3230 switch (save_mode) {
3232 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3233 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3236 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3239 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3242 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3253 * The immediate field for cond branches is big enough for all reasonable methods
3255 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3256 if (0 && ins->inst_true_bb->native_offset) { \
3257 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3259 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3260 ARM_B_COND (code, (condcode), 0); \
3263 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3265 /* emit an exception if condition is fail
3267 * We assign the extra code used to throw the implicit exceptions
3268 * to cfg->bb_exit as far as the big branch handling is concerned
3270 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3272 mono_add_patch_info (cfg, code - cfg->native_code, \
3273 MONO_PATCH_INFO_EXC, exc_name); \
3274 ARM_BL_COND (code, (condcode), 0); \
3277 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3280 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3285 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3289 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3290 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3292 switch (ins->opcode) {
3295 /* Already done by an arch-independent pass */
3297 case OP_LOAD_MEMBASE:
3298 case OP_LOADI4_MEMBASE:
3300 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3301 * OP_LOAD_MEMBASE offset(basereg), reg
3303 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3304 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3305 ins->inst_basereg == last_ins->inst_destbasereg &&
3306 ins->inst_offset == last_ins->inst_offset) {
3307 if (ins->dreg == last_ins->sreg1) {
3308 MONO_DELETE_INS (bb, ins);
3311 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3312 ins->opcode = OP_MOVE;
3313 ins->sreg1 = last_ins->sreg1;
3317 * Note: reg1 must be different from the basereg in the second load
3318 * OP_LOAD_MEMBASE offset(basereg), reg1
3319 * OP_LOAD_MEMBASE offset(basereg), reg2
3321 * OP_LOAD_MEMBASE offset(basereg), reg1
3322 * OP_MOVE reg1, reg2
3324 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3325 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3326 ins->inst_basereg != last_ins->dreg &&
3327 ins->inst_basereg == last_ins->inst_basereg &&
3328 ins->inst_offset == last_ins->inst_offset) {
3330 if (ins->dreg == last_ins->dreg) {
3331 MONO_DELETE_INS (bb, ins);
3334 ins->opcode = OP_MOVE;
3335 ins->sreg1 = last_ins->dreg;
3338 //g_assert_not_reached ();
3342 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3343 * OP_LOAD_MEMBASE offset(basereg), reg
3345 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3346 * OP_ICONST reg, imm
3348 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3349 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3350 ins->inst_basereg == last_ins->inst_destbasereg &&
3351 ins->inst_offset == last_ins->inst_offset) {
3352 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3353 ins->opcode = OP_ICONST;
3354 ins->inst_c0 = last_ins->inst_imm;
3355 g_assert_not_reached (); // check this rule
3359 case OP_LOADU1_MEMBASE:
3360 case OP_LOADI1_MEMBASE:
3361 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3362 ins->inst_basereg == last_ins->inst_destbasereg &&
3363 ins->inst_offset == last_ins->inst_offset) {
3364 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3365 ins->sreg1 = last_ins->sreg1;
3368 case OP_LOADU2_MEMBASE:
3369 case OP_LOADI2_MEMBASE:
3370 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3371 ins->inst_basereg == last_ins->inst_destbasereg &&
3372 ins->inst_offset == last_ins->inst_offset) {
3373 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3374 ins->sreg1 = last_ins->sreg1;
3378 ins->opcode = OP_MOVE;
3382 if (ins->dreg == ins->sreg1) {
3383 MONO_DELETE_INS (bb, ins);
3387 * OP_MOVE sreg, dreg
3388 * OP_MOVE dreg, sreg
3390 if (last_ins && last_ins->opcode == OP_MOVE &&
3391 ins->sreg1 == last_ins->dreg &&
3392 ins->dreg == last_ins->sreg1) {
3393 MONO_DELETE_INS (bb, ins);
3402 * the branch_cc_table should maintain the order of these
3416 branch_cc_table [] = {
3430 #define ADD_NEW_INS(cfg,dest,op) do { \
3431 MONO_INST_NEW ((cfg), (dest), (op)); \
3432 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3436 map_to_reg_reg_op (int op)
3445 case OP_COMPARE_IMM:
3447 case OP_ICOMPARE_IMM:
3461 case OP_LOAD_MEMBASE:
3462 return OP_LOAD_MEMINDEX;
3463 case OP_LOADI4_MEMBASE:
3464 return OP_LOADI4_MEMINDEX;
3465 case OP_LOADU4_MEMBASE:
3466 return OP_LOADU4_MEMINDEX;
3467 case OP_LOADU1_MEMBASE:
3468 return OP_LOADU1_MEMINDEX;
3469 case OP_LOADI2_MEMBASE:
3470 return OP_LOADI2_MEMINDEX;
3471 case OP_LOADU2_MEMBASE:
3472 return OP_LOADU2_MEMINDEX;
3473 case OP_LOADI1_MEMBASE:
3474 return OP_LOADI1_MEMINDEX;
3475 case OP_STOREI1_MEMBASE_REG:
3476 return OP_STOREI1_MEMINDEX;
3477 case OP_STOREI2_MEMBASE_REG:
3478 return OP_STOREI2_MEMINDEX;
3479 case OP_STOREI4_MEMBASE_REG:
3480 return OP_STOREI4_MEMINDEX;
3481 case OP_STORE_MEMBASE_REG:
3482 return OP_STORE_MEMINDEX;
3483 case OP_STORER4_MEMBASE_REG:
3484 return OP_STORER4_MEMINDEX;
3485 case OP_STORER8_MEMBASE_REG:
3486 return OP_STORER8_MEMINDEX;
3487 case OP_STORE_MEMBASE_IMM:
3488 return OP_STORE_MEMBASE_REG;
3489 case OP_STOREI1_MEMBASE_IMM:
3490 return OP_STOREI1_MEMBASE_REG;
3491 case OP_STOREI2_MEMBASE_IMM:
3492 return OP_STOREI2_MEMBASE_REG;
3493 case OP_STOREI4_MEMBASE_IMM:
3494 return OP_STOREI4_MEMBASE_REG;
3496 g_assert_not_reached ();
3500 * Remove from the instruction list the instructions that can't be
3501 * represented with very simple instructions with no register
3505 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3507 MonoInst *ins, *temp, *last_ins = NULL;
3508 int rot_amount, imm8, low_imm;
3510 MONO_BB_FOR_EACH_INS (bb, ins) {
3512 switch (ins->opcode) {
3516 case OP_COMPARE_IMM:
3517 case OP_ICOMPARE_IMM:
3531 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3532 ADD_NEW_INS (cfg, temp, OP_ICONST);
3533 temp->inst_c0 = ins->inst_imm;
3534 temp->dreg = mono_alloc_ireg (cfg);
3535 ins->sreg2 = temp->dreg;
3536 ins->opcode = mono_op_imm_to_op (ins->opcode);
3538 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3544 if (ins->inst_imm == 1) {
3545 ins->opcode = OP_MOVE;
3548 if (ins->inst_imm == 0) {
3549 ins->opcode = OP_ICONST;
3553 imm8 = mono_is_power_of_two (ins->inst_imm);
3555 ins->opcode = OP_SHL_IMM;
3556 ins->inst_imm = imm8;
3559 ADD_NEW_INS (cfg, temp, OP_ICONST);
3560 temp->inst_c0 = ins->inst_imm;
3561 temp->dreg = mono_alloc_ireg (cfg);
3562 ins->sreg2 = temp->dreg;
3563 ins->opcode = OP_IMUL;
3569 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3570 /* ARM sets the C flag to 1 if there was _no_ overflow */
3571 ins->next->opcode = OP_COND_EXC_NC;
3574 case OP_IDIV_UN_IMM:
3576 case OP_IREM_UN_IMM:
3577 ADD_NEW_INS (cfg, temp, OP_ICONST);
3578 temp->inst_c0 = ins->inst_imm;
3579 temp->dreg = mono_alloc_ireg (cfg);
3580 ins->sreg2 = temp->dreg;
3581 ins->opcode = mono_op_imm_to_op (ins->opcode);
3583 case OP_LOCALLOC_IMM:
3584 ADD_NEW_INS (cfg, temp, OP_ICONST);
3585 temp->inst_c0 = ins->inst_imm;
3586 temp->dreg = mono_alloc_ireg (cfg);
3587 ins->sreg1 = temp->dreg;
3588 ins->opcode = OP_LOCALLOC;
3590 case OP_LOAD_MEMBASE:
3591 case OP_LOADI4_MEMBASE:
3592 case OP_LOADU4_MEMBASE:
3593 case OP_LOADU1_MEMBASE:
3594 /* we can do two things: load the immed in a register
3595 * and use an indexed load, or see if the immed can be
3596 * represented as an ad_imm + a load with a smaller offset
3597 * that fits. We just do the first for now, optimize later.
3599 if (arm_is_imm12 (ins->inst_offset))
3601 ADD_NEW_INS (cfg, temp, OP_ICONST);
3602 temp->inst_c0 = ins->inst_offset;
3603 temp->dreg = mono_alloc_ireg (cfg);
3604 ins->sreg2 = temp->dreg;
3605 ins->opcode = map_to_reg_reg_op (ins->opcode);
3607 case OP_LOADI2_MEMBASE:
3608 case OP_LOADU2_MEMBASE:
3609 case OP_LOADI1_MEMBASE:
3610 if (arm_is_imm8 (ins->inst_offset))
3612 ADD_NEW_INS (cfg, temp, OP_ICONST);
3613 temp->inst_c0 = ins->inst_offset;
3614 temp->dreg = mono_alloc_ireg (cfg);
3615 ins->sreg2 = temp->dreg;
3616 ins->opcode = map_to_reg_reg_op (ins->opcode);
3618 case OP_LOADR4_MEMBASE:
3619 case OP_LOADR8_MEMBASE:
3620 if (arm_is_fpimm8 (ins->inst_offset))
3622 low_imm = ins->inst_offset & 0x1ff;
3623 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3624 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3625 temp->inst_imm = ins->inst_offset & ~0x1ff;
3626 temp->sreg1 = ins->inst_basereg;
3627 temp->dreg = mono_alloc_ireg (cfg);
3628 ins->inst_basereg = temp->dreg;
3629 ins->inst_offset = low_imm;
3633 ADD_NEW_INS (cfg, temp, OP_ICONST);
3634 temp->inst_c0 = ins->inst_offset;
3635 temp->dreg = mono_alloc_ireg (cfg);
3637 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3638 add_ins->sreg1 = ins->inst_basereg;
3639 add_ins->sreg2 = temp->dreg;
3640 add_ins->dreg = mono_alloc_ireg (cfg);
3642 ins->inst_basereg = add_ins->dreg;
3643 ins->inst_offset = 0;
3646 case OP_STORE_MEMBASE_REG:
3647 case OP_STOREI4_MEMBASE_REG:
3648 case OP_STOREI1_MEMBASE_REG:
3649 if (arm_is_imm12 (ins->inst_offset))
3651 ADD_NEW_INS (cfg, temp, OP_ICONST);
3652 temp->inst_c0 = ins->inst_offset;
3653 temp->dreg = mono_alloc_ireg (cfg);
3654 ins->sreg2 = temp->dreg;
3655 ins->opcode = map_to_reg_reg_op (ins->opcode);
3657 case OP_STOREI2_MEMBASE_REG:
3658 if (arm_is_imm8 (ins->inst_offset))
3660 ADD_NEW_INS (cfg, temp, OP_ICONST);
3661 temp->inst_c0 = ins->inst_offset;
3662 temp->dreg = mono_alloc_ireg (cfg);
3663 ins->sreg2 = temp->dreg;
3664 ins->opcode = map_to_reg_reg_op (ins->opcode);
3666 case OP_STORER4_MEMBASE_REG:
3667 case OP_STORER8_MEMBASE_REG:
3668 if (arm_is_fpimm8 (ins->inst_offset))
3670 low_imm = ins->inst_offset & 0x1ff;
3671 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3672 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3673 temp->inst_imm = ins->inst_offset & ~0x1ff;
3674 temp->sreg1 = ins->inst_destbasereg;
3675 temp->dreg = mono_alloc_ireg (cfg);
3676 ins->inst_destbasereg = temp->dreg;
3677 ins->inst_offset = low_imm;
3681 ADD_NEW_INS (cfg, temp, OP_ICONST);
3682 temp->inst_c0 = ins->inst_offset;
3683 temp->dreg = mono_alloc_ireg (cfg);
3685 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3686 add_ins->sreg1 = ins->inst_destbasereg;
3687 add_ins->sreg2 = temp->dreg;
3688 add_ins->dreg = mono_alloc_ireg (cfg);
3690 ins->inst_destbasereg = add_ins->dreg;
3691 ins->inst_offset = 0;
3694 case OP_STORE_MEMBASE_IMM:
3695 case OP_STOREI1_MEMBASE_IMM:
3696 case OP_STOREI2_MEMBASE_IMM:
3697 case OP_STOREI4_MEMBASE_IMM:
3698 ADD_NEW_INS (cfg, temp, OP_ICONST);
3699 temp->inst_c0 = ins->inst_imm;
3700 temp->dreg = mono_alloc_ireg (cfg);
3701 ins->sreg1 = temp->dreg;
3702 ins->opcode = map_to_reg_reg_op (ins->opcode);
3704 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3707 gboolean swap = FALSE;
3711 /* Optimized away */
3716 /* Some fp compares require swapped operands */
3717 switch (ins->next->opcode) {
3719 ins->next->opcode = OP_FBLT;
3723 ins->next->opcode = OP_FBLT_UN;
3727 ins->next->opcode = OP_FBGE;
3731 ins->next->opcode = OP_FBGE_UN;
3739 ins->sreg1 = ins->sreg2;
3748 bb->last_ins = last_ins;
3749 bb->max_vreg = cfg->next_vreg;
3753 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3757 if (long_ins->opcode == OP_LNEG) {
3759 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3760 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3766 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3768 /* sreg is a float, dreg is an integer reg */
3770 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3772 ARM_TOSIZD (code, vfp_scratch1, sreg);
3774 ARM_TOUIZD (code, vfp_scratch1, sreg);
3775 ARM_FMRS (code, dreg, vfp_scratch1);
3776 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3780 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3781 else if (size == 2) {
3782 ARM_SHL_IMM (code, dreg, dreg, 16);
3783 ARM_SHR_IMM (code, dreg, dreg, 16);
3787 ARM_SHL_IMM (code, dreg, dreg, 24);
3788 ARM_SAR_IMM (code, dreg, dreg, 24);
3789 } else if (size == 2) {
3790 ARM_SHL_IMM (code, dreg, dreg, 16);
3791 ARM_SAR_IMM (code, dreg, dreg, 16);
3798 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3800 /* sreg is a float, dreg is an integer reg */
3802 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3804 ARM_TOSIZS (code, vfp_scratch1, sreg);
3806 ARM_TOUIZS (code, vfp_scratch1, sreg);
3807 ARM_FMRS (code, dreg, vfp_scratch1);
3808 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3812 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3813 else if (size == 2) {
3814 ARM_SHL_IMM (code, dreg, dreg, 16);
3815 ARM_SHR_IMM (code, dreg, dreg, 16);
3819 ARM_SHL_IMM (code, dreg, dreg, 24);
3820 ARM_SAR_IMM (code, dreg, dreg, 24);
3821 } else if (size == 2) {
3822 ARM_SHL_IMM (code, dreg, dreg, 16);
3823 ARM_SAR_IMM (code, dreg, dreg, 16);
3829 #endif /* #ifndef DISABLE_JIT */
3831 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3834 emit_thunk (guint8 *code, gconstpointer target)
3838 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3839 if (thumb_supported)
3840 ARM_BX (code, ARMREG_IP);
3842 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3843 *(guint32*)code = (guint32)target;
3845 mono_arch_flush_icache (p, code - p);
3849 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3851 MonoJitInfo *ji = NULL;
3852 MonoThunkJitInfo *info;
3855 guint8 *orig_target;
3856 guint8 *target_thunk;
3859 domain = mono_domain_get ();
3863 * This can be called multiple times during JITting,
3864 * save the current position in cfg->arch to avoid
3865 * doing a O(n^2) search.
3867 if (!cfg->arch.thunks) {
3868 cfg->arch.thunks = cfg->thunks;
3869 cfg->arch.thunks_size = cfg->thunk_area;
3871 thunks = cfg->arch.thunks;
3872 thunks_size = cfg->arch.thunks_size;
3874 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3875 g_assert_not_reached ();
3878 g_assert (*(guint32*)thunks == 0);
3879 emit_thunk (thunks, target);
3880 arm_patch (code, thunks);
3882 cfg->arch.thunks += THUNK_SIZE;
3883 cfg->arch.thunks_size -= THUNK_SIZE;
3885 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3887 info = mono_jit_info_get_thunk_info (ji);
3890 thunks = (guint8*)ji->code_start + info->thunks_offset;
3891 thunks_size = info->thunks_size;
3893 orig_target = mono_arch_get_call_target (code + 4);
3895 mono_mini_arch_lock ();
3897 target_thunk = NULL;
3898 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3899 /* The call already points to a thunk, because of trampolines etc. */
3900 target_thunk = orig_target;
3902 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3903 if (((guint32*)p) [0] == 0) {
3907 } else if (((guint32*)p) [2] == (guint32)target) {
3908 /* Thunk already points to target */
3915 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
3917 if (!target_thunk) {
3918 mono_mini_arch_unlock ();
3919 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3920 g_assert_not_reached ();
3923 emit_thunk (target_thunk, target);
3924 arm_patch (code, target_thunk);
3925 mono_arch_flush_icache (code, 4);
3927 mono_mini_arch_unlock ();
3932 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3934 guint32 *code32 = (void*)code;
3935 guint32 ins = *code32;
3936 guint32 prim = (ins >> 25) & 7;
3937 guint32 tval = GPOINTER_TO_UINT (target);
3939 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3940 if (prim == 5) { /* 101b */
3941 /* the diff starts 8 bytes from the branch opcode */
3942 gint diff = target - code - 8;
3944 gint tmask = 0xffffffff;
3945 if (tval & 1) { /* entering thumb mode */
3946 diff = target - 1 - code - 8;
3947 g_assert (thumb_supported);
3948 tbits = 0xf << 28; /* bl->blx bit pattern */
3949 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3950 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3954 tmask = ~(1 << 24); /* clear the link bit */
3955 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3960 if (diff <= 33554431) {
3962 ins = (ins & 0xff000000) | diff;
3964 *code32 = ins | tbits;
3968 /* diff between 0 and -33554432 */
3969 if (diff >= -33554432) {
3971 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3973 *code32 = ins | tbits;
3978 handle_thunk (cfg, domain, code, target);
3982 #ifdef USE_JUMP_TABLES
3984 gpointer *jte = mono_jumptable_get_entry (code);
3986 jte [0] = (gpointer) target;
3990 * The alternative call sequences looks like this:
3992 * ldr ip, [pc] // loads the address constant
3993 * b 1f // jumps around the constant
3994 * address constant embedded in the code
3999 * There are two cases for patching:
4000 * a) at the end of method emission: in this case code points to the start
4001 * of the call sequence
4002 * b) during runtime patching of the call site: in this case code points
4003 * to the mov pc, ip instruction
4005 * We have to handle also the thunk jump code sequence:
4009 * address constant // execution never reaches here
4011 if ((ins & 0x0ffffff0) == 0x12fff10) {
4012 /* Branch and exchange: the address is constructed in a reg
4013 * We can patch BX when the code sequence is the following:
4014 * ldr ip, [pc, #0] ; 0x8
4021 guint8 *emit = (guint8*)ccode;
4022 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4024 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4025 ARM_BX (emit, ARMREG_IP);
4027 /*patching from magic trampoline*/
4028 if (ins == ccode [3]) {
4029 g_assert (code32 [-4] == ccode [0]);
4030 g_assert (code32 [-3] == ccode [1]);
4031 g_assert (code32 [-1] == ccode [2]);
4032 code32 [-2] = (guint32)target;
4035 /*patching from JIT*/
4036 if (ins == ccode [0]) {
4037 g_assert (code32 [1] == ccode [1]);
4038 g_assert (code32 [3] == ccode [2]);
4039 g_assert (code32 [4] == ccode [3]);
4040 code32 [2] = (guint32)target;
4043 g_assert_not_reached ();
4044 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
4052 guint8 *emit = (guint8*)ccode;
4053 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4055 ARM_BLX_REG (emit, ARMREG_IP);
4057 g_assert (code32 [-3] == ccode [0]);
4058 g_assert (code32 [-2] == ccode [1]);
4059 g_assert (code32 [0] == ccode [2]);
4061 code32 [-1] = (guint32)target;
4064 guint32 *tmp = ccode;
4065 guint8 *emit = (guint8*)tmp;
4066 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4067 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4068 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
4069 ARM_BX (emit, ARMREG_IP);
4070 if (ins == ccode [2]) {
4071 g_assert_not_reached (); // should be -2 ...
4072 code32 [-1] = (guint32)target;
4075 if (ins == ccode [0]) {
4076 /* handles both thunk jump code and the far call sequence */
4077 code32 [2] = (guint32)target;
4080 g_assert_not_reached ();
4082 // g_print ("patched with 0x%08x\n", ins);
4087 arm_patch (guchar *code, const guchar *target)
4089 arm_patch_general (NULL, NULL, code, target);
4093 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4094 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4095 * to be used with the emit macros.
4096 * Return -1 otherwise.
4099 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4102 for (i = 0; i < 31; i+= 2) {
4103 res = (val << (32 - i)) | (val >> i);
4106 *rot_amount = i? 32 - i: 0;
4113 * Emits in code a sequence of instructions that load the value 'val'
4114 * into the dreg register. Uses at most 4 instructions.
4117 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4119 int imm8, rot_amount;
4121 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4122 /* skip the constant pool */
4128 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4129 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4130 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4131 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4134 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4136 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4140 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4142 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4144 if (val & 0xFF0000) {
4145 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4147 if (val & 0xFF000000) {
4148 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4150 } else if (val & 0xFF00) {
4151 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4152 if (val & 0xFF0000) {
4153 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4155 if (val & 0xFF000000) {
4156 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4158 } else if (val & 0xFF0000) {
4159 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4160 if (val & 0xFF000000) {
4161 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4164 //g_assert_not_reached ();
4170 mono_arm_thumb_supported (void)
4172 return thumb_supported;
4178 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4183 call = (MonoCallInst*)ins;
4184 cinfo = call->call_info;
4186 switch (cinfo->ret.storage) {
4188 MonoInst *loc = cfg->arch.vret_addr_loc;
4191 /* Load the destination address */
4192 g_assert (loc && loc->opcode == OP_REGOFFSET);
4194 if (arm_is_imm12 (loc->inst_offset)) {
4195 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4197 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4198 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4200 for (i = 0; i < cinfo->ret.nregs; ++i) {
4201 if (cinfo->ret.esize == 4)
4202 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4204 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4212 switch (ins->opcode) {
4215 case OP_FCALL_MEMBASE:
4217 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4218 if (sig_ret->type == MONO_TYPE_R4) {
4219 if (IS_HARD_FLOAT) {
4220 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4222 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4223 ARM_CVTS (code, ins->dreg, ins->dreg);
4226 if (IS_HARD_FLOAT) {
4227 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4229 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4236 case OP_RCALL_MEMBASE: {
4241 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4242 g_assert (sig_ret->type == MONO_TYPE_R4);
4243 if (IS_HARD_FLOAT) {
4244 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4246 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4247 ARM_CPYS (code, ins->dreg, ins->dreg);
4259 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4264 guint8 *code = cfg->native_code + cfg->code_len;
4265 MonoInst *last_ins = NULL;
4266 guint last_offset = 0;
4268 int imm8, rot_amount;
4270 /* we don't align basic blocks of loops on arm */
4272 if (cfg->verbose_level > 2)
4273 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4275 cpos = bb->max_offset;
4277 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4278 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4279 //g_assert (!mono_compile_aot);
4282 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4283 /* this is not thread save, but good enough */
4284 /* fixme: howto handle overflows? */
4285 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4288 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4289 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4290 (gpointer)"mono_break");
4291 code = emit_call_seq (cfg, code);
4294 MONO_BB_FOR_EACH_INS (bb, ins) {
4295 offset = code - cfg->native_code;
4297 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4299 if (offset > (cfg->code_size - max_len - 16)) {
4300 cfg->code_size *= 2;
4301 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4302 code = cfg->native_code + offset;
4304 // if (ins->cil_code)
4305 // g_print ("cil code\n");
4306 mono_debug_record_line_number (cfg, ins, offset);
4308 switch (ins->opcode) {
4309 case OP_MEMORY_BARRIER:
4311 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4312 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4316 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4318 case OP_TLS_GET_REG:
4319 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4322 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4324 case OP_TLS_SET_REG:
4325 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4327 case OP_ATOMIC_EXCHANGE_I4:
4328 case OP_ATOMIC_CAS_I4:
4329 case OP_ATOMIC_ADD_I4: {
4333 g_assert (v7_supported);
4336 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4338 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4340 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4344 g_assert (cfg->arch.atomic_tmp_offset != -1);
4345 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4347 switch (ins->opcode) {
4348 case OP_ATOMIC_EXCHANGE_I4:
4350 ARM_DMB (code, ARM_DMB_SY);
4351 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4352 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4353 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4355 ARM_B_COND (code, ARMCOND_NE, 0);
4356 arm_patch (buf [1], buf [0]);
4358 case OP_ATOMIC_CAS_I4:
4359 ARM_DMB (code, ARM_DMB_SY);
4361 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4362 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4364 ARM_B_COND (code, ARMCOND_NE, 0);
4365 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4366 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4368 ARM_B_COND (code, ARMCOND_NE, 0);
4369 arm_patch (buf [2], buf [0]);
4370 arm_patch (buf [1], code);
4372 case OP_ATOMIC_ADD_I4:
4374 ARM_DMB (code, ARM_DMB_SY);
4375 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4376 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4377 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4378 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4380 ARM_B_COND (code, ARMCOND_NE, 0);
4381 arm_patch (buf [1], buf [0]);
4384 g_assert_not_reached ();
4387 ARM_DMB (code, ARM_DMB_SY);
4388 if (tmpreg != ins->dreg)
4389 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4390 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4393 case OP_ATOMIC_LOAD_I1:
4394 case OP_ATOMIC_LOAD_U1:
4395 case OP_ATOMIC_LOAD_I2:
4396 case OP_ATOMIC_LOAD_U2:
4397 case OP_ATOMIC_LOAD_I4:
4398 case OP_ATOMIC_LOAD_U4:
4399 case OP_ATOMIC_LOAD_R4:
4400 case OP_ATOMIC_LOAD_R8: {
4401 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4402 ARM_DMB (code, ARM_DMB_SY);
4404 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4406 switch (ins->opcode) {
4407 case OP_ATOMIC_LOAD_I1:
4408 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4410 case OP_ATOMIC_LOAD_U1:
4411 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4413 case OP_ATOMIC_LOAD_I2:
4414 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4416 case OP_ATOMIC_LOAD_U2:
4417 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4419 case OP_ATOMIC_LOAD_I4:
4420 case OP_ATOMIC_LOAD_U4:
4421 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4423 case OP_ATOMIC_LOAD_R4:
4425 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4426 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4428 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4429 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4430 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4431 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4432 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4435 case OP_ATOMIC_LOAD_R8:
4436 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4437 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4441 ARM_DMB (code, ARM_DMB_SY);
4444 case OP_ATOMIC_STORE_I1:
4445 case OP_ATOMIC_STORE_U1:
4446 case OP_ATOMIC_STORE_I2:
4447 case OP_ATOMIC_STORE_U2:
4448 case OP_ATOMIC_STORE_I4:
4449 case OP_ATOMIC_STORE_U4:
4450 case OP_ATOMIC_STORE_R4:
4451 case OP_ATOMIC_STORE_R8: {
4452 ARM_DMB (code, ARM_DMB_SY);
4454 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4456 switch (ins->opcode) {
4457 case OP_ATOMIC_STORE_I1:
4458 case OP_ATOMIC_STORE_U1:
4459 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4461 case OP_ATOMIC_STORE_I2:
4462 case OP_ATOMIC_STORE_U2:
4463 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4465 case OP_ATOMIC_STORE_I4:
4466 case OP_ATOMIC_STORE_U4:
4467 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4469 case OP_ATOMIC_STORE_R4:
4471 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4472 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4474 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4475 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4476 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4477 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4478 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4481 case OP_ATOMIC_STORE_R8:
4482 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4483 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4487 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4488 ARM_DMB (code, ARM_DMB_SY);
4492 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4493 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4496 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4497 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4499 case OP_STOREI1_MEMBASE_IMM:
4500 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4501 g_assert (arm_is_imm12 (ins->inst_offset));
4502 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4504 case OP_STOREI2_MEMBASE_IMM:
4505 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4506 g_assert (arm_is_imm8 (ins->inst_offset));
4507 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4509 case OP_STORE_MEMBASE_IMM:
4510 case OP_STOREI4_MEMBASE_IMM:
4511 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4512 g_assert (arm_is_imm12 (ins->inst_offset));
4513 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4515 case OP_STOREI1_MEMBASE_REG:
4516 g_assert (arm_is_imm12 (ins->inst_offset));
4517 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4519 case OP_STOREI2_MEMBASE_REG:
4520 g_assert (arm_is_imm8 (ins->inst_offset));
4521 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4523 case OP_STORE_MEMBASE_REG:
4524 case OP_STOREI4_MEMBASE_REG:
4525 /* this case is special, since it happens for spill code after lowering has been called */
4526 if (arm_is_imm12 (ins->inst_offset)) {
4527 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4529 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4530 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4533 case OP_STOREI1_MEMINDEX:
4534 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4536 case OP_STOREI2_MEMINDEX:
4537 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4539 case OP_STORE_MEMINDEX:
4540 case OP_STOREI4_MEMINDEX:
4541 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4544 g_assert_not_reached ();
4546 case OP_LOAD_MEMINDEX:
4547 case OP_LOADI4_MEMINDEX:
4548 case OP_LOADU4_MEMINDEX:
4549 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4551 case OP_LOADI1_MEMINDEX:
4552 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4554 case OP_LOADU1_MEMINDEX:
4555 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4557 case OP_LOADI2_MEMINDEX:
4558 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4560 case OP_LOADU2_MEMINDEX:
4561 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4563 case OP_LOAD_MEMBASE:
4564 case OP_LOADI4_MEMBASE:
4565 case OP_LOADU4_MEMBASE:
4566 /* this case is special, since it happens for spill code after lowering has been called */
4567 if (arm_is_imm12 (ins->inst_offset)) {
4568 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4570 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4571 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4574 case OP_LOADI1_MEMBASE:
4575 g_assert (arm_is_imm8 (ins->inst_offset));
4576 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4578 case OP_LOADU1_MEMBASE:
4579 g_assert (arm_is_imm12 (ins->inst_offset));
4580 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4582 case OP_LOADU2_MEMBASE:
4583 g_assert (arm_is_imm8 (ins->inst_offset));
4584 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4586 case OP_LOADI2_MEMBASE:
4587 g_assert (arm_is_imm8 (ins->inst_offset));
4588 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4590 case OP_ICONV_TO_I1:
4591 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4592 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4594 case OP_ICONV_TO_I2:
4595 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4596 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4598 case OP_ICONV_TO_U1:
4599 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4601 case OP_ICONV_TO_U2:
4602 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4603 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4607 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4609 case OP_COMPARE_IMM:
4610 case OP_ICOMPARE_IMM:
4611 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4612 g_assert (imm8 >= 0);
4613 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4617 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4618 * So instead of emitting a trap, we emit a call a C function and place a
4621 //*(int*)code = 0xef9f0001;
4624 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4625 (gpointer)"mono_break");
4626 code = emit_call_seq (cfg, code);
4628 case OP_RELAXED_NOP:
4633 case OP_DUMMY_STORE:
4634 case OP_DUMMY_ICONST:
4635 case OP_DUMMY_R8CONST:
4636 case OP_NOT_REACHED:
4639 case OP_IL_SEQ_POINT:
4640 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4642 case OP_SEQ_POINT: {
4644 MonoInst *info_var = cfg->arch.seq_point_info_var;
4645 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4646 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
4647 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4648 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4650 int dreg = ARMREG_LR;
4652 if (cfg->soft_breakpoints) {
4653 g_assert (!cfg->compile_aot);
4657 * For AOT, we use one got slot per method, which will point to a
4658 * SeqPointInfo structure, containing all the information required
4659 * by the code below.
4661 if (cfg->compile_aot) {
4662 g_assert (info_var);
4663 g_assert (info_var->opcode == OP_REGOFFSET);
4664 g_assert (arm_is_imm12 (info_var->inst_offset));
4667 if (!cfg->soft_breakpoints) {
4669 * Read from the single stepping trigger page. This will cause a
4670 * SIGSEGV when single stepping is enabled.
4671 * We do this _before_ the breakpoint, so single stepping after
4672 * a breakpoint is hit will step to the next IL offset.
4674 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4677 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4678 if (cfg->soft_breakpoints) {
4679 /* Load the address of the sequence point trigger variable. */
4682 g_assert (var->opcode == OP_REGOFFSET);
4683 g_assert (arm_is_imm12 (var->inst_offset));
4684 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4686 /* Read the value and check whether it is non-zero. */
4687 ARM_LDR_IMM (code, dreg, dreg, 0);
4688 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4690 /* Load the address of the sequence point method. */
4691 var = ss_method_var;
4693 g_assert (var->opcode == OP_REGOFFSET);
4694 g_assert (arm_is_imm12 (var->inst_offset));
4695 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4697 /* Call it conditionally. */
4698 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4700 if (cfg->compile_aot) {
4701 /* Load the trigger page addr from the variable initialized in the prolog */
4702 var = ss_trigger_page_var;
4704 g_assert (var->opcode == OP_REGOFFSET);
4705 g_assert (arm_is_imm12 (var->inst_offset));
4706 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4708 #ifdef USE_JUMP_TABLES
4709 gpointer *jte = mono_jumptable_add_entry ();
4710 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4711 jte [0] = ss_trigger_page;
4713 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4715 *(int*)code = (int)ss_trigger_page;
4719 ARM_LDR_IMM (code, dreg, dreg, 0);
4723 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4725 if (cfg->soft_breakpoints) {
4726 /* Load the address of the breakpoint method into ip. */
4727 var = bp_method_var;
4729 g_assert (var->opcode == OP_REGOFFSET);
4730 g_assert (arm_is_imm12 (var->inst_offset));
4731 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4734 * A placeholder for a possible breakpoint inserted by
4735 * mono_arch_set_breakpoint ().
4738 } else if (cfg->compile_aot) {
4739 guint32 offset = code - cfg->native_code;
4742 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4743 /* Add the offset */
4744 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4745 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4746 if (arm_is_imm12 ((int)val)) {
4747 ARM_LDR_IMM (code, dreg, dreg, val);
4749 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4751 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4753 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4754 g_assert (!(val & 0xFF000000));
4756 ARM_LDR_IMM (code, dreg, dreg, 0);
4758 /* What is faster, a branch or a load ? */
4759 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4760 /* The breakpoint instruction */
4761 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4764 * A placeholder for a possible breakpoint inserted by
4765 * mono_arch_set_breakpoint ().
4767 for (i = 0; i < 4; ++i)
4772 * Add an additional nop so skipping the bp doesn't cause the ip to point
4773 * to another IL offset.
4781 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4784 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4788 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4791 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4792 g_assert (imm8 >= 0);
4793 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4797 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4798 g_assert (imm8 >= 0);
4799 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4803 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4804 g_assert (imm8 >= 0);
4805 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4808 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4809 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4811 case OP_IADD_OVF_UN:
4812 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4813 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4816 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4817 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4819 case OP_ISUB_OVF_UN:
4820 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4821 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4823 case OP_ADD_OVF_CARRY:
4824 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4825 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4827 case OP_ADD_OVF_UN_CARRY:
4828 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4829 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4831 case OP_SUB_OVF_CARRY:
4832 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4833 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4835 case OP_SUB_OVF_UN_CARRY:
4836 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4837 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4841 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4844 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4845 g_assert (imm8 >= 0);
4846 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4849 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4853 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4857 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4858 g_assert (imm8 >= 0);
4859 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4863 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4864 g_assert (imm8 >= 0);
4865 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4867 case OP_ARM_RSBS_IMM:
4868 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4869 g_assert (imm8 >= 0);
4870 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4872 case OP_ARM_RSC_IMM:
4873 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4874 g_assert (imm8 >= 0);
4875 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4878 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4882 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4883 g_assert (imm8 >= 0);
4884 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4887 g_assert (v7s_supported);
4888 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4891 g_assert (v7s_supported);
4892 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4895 g_assert (v7s_supported);
4896 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4897 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4900 g_assert (v7s_supported);
4901 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4902 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4906 g_assert_not_reached ();
4908 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4912 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4913 g_assert (imm8 >= 0);
4914 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4917 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4921 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4922 g_assert (imm8 >= 0);
4923 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4926 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4931 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4932 else if (ins->dreg != ins->sreg1)
4933 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4936 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4941 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4942 else if (ins->dreg != ins->sreg1)
4943 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4946 case OP_ISHR_UN_IMM:
4948 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4949 else if (ins->dreg != ins->sreg1)
4950 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4953 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4956 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4959 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4962 if (ins->dreg == ins->sreg2)
4963 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4965 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4968 g_assert_not_reached ();
4971 /* FIXME: handle ovf/ sreg2 != dreg */
4972 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4973 /* FIXME: MUL doesn't set the C/O flags on ARM */
4975 case OP_IMUL_OVF_UN:
4976 /* FIXME: handle ovf/ sreg2 != dreg */
4977 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4978 /* FIXME: MUL doesn't set the C/O flags on ARM */
4981 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4984 /* Load the GOT offset */
4985 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4986 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4988 *(gpointer*)code = NULL;
4990 /* Load the value from the GOT */
4991 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4993 case OP_OBJC_GET_SELECTOR:
4994 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4995 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4997 *(gpointer*)code = NULL;
4999 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
5001 case OP_ICONV_TO_I4:
5002 case OP_ICONV_TO_U4:
5004 if (ins->dreg != ins->sreg1)
5005 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5008 int saved = ins->sreg2;
5009 if (ins->sreg2 == ARM_LSW_REG) {
5010 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
5013 if (ins->sreg1 != ARM_LSW_REG)
5014 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
5015 if (saved != ARM_MSW_REG)
5016 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
5020 if (IS_VFP && ins->dreg != ins->sreg1)
5021 ARM_CPYD (code, ins->dreg, ins->sreg1);
5024 if (IS_VFP && ins->dreg != ins->sreg1)
5025 ARM_CPYS (code, ins->dreg, ins->sreg1);
5027 case OP_MOVE_F_TO_I4:
5029 ARM_FMRS (code, ins->dreg, ins->sreg1);
5031 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5032 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5033 ARM_FMRS (code, ins->dreg, vfp_scratch1);
5034 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5037 case OP_MOVE_I4_TO_F:
5039 ARM_FMSR (code, ins->dreg, ins->sreg1);
5041 ARM_FMSR (code, ins->dreg, ins->sreg1);
5042 ARM_CVTS (code, ins->dreg, ins->dreg);
5045 case OP_FCONV_TO_R4:
5048 ARM_CVTD (code, ins->dreg, ins->sreg1);
5050 ARM_CVTD (code, ins->dreg, ins->sreg1);
5051 ARM_CVTS (code, ins->dreg, ins->dreg);
5056 MonoCallInst *call = (MonoCallInst*)ins;
5059 * The stack looks like the following:
5060 * <caller argument area>
5063 * <callee argument area>
5064 * Need to copy the arguments from the callee argument area to
5065 * the caller argument area, and pop the frame.
5067 if (call->stack_usage) {
5068 int i, prev_sp_offset = 0;
5070 /* Compute size of saved registers restored below */
5072 prev_sp_offset = 2 * 4;
5074 prev_sp_offset = 1 * 4;
5075 for (i = 0; i < 16; ++i) {
5076 if (cfg->used_int_regs & (1 << i))
5077 prev_sp_offset += 4;
5080 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5082 /* Copy arguments on the stack to our argument area */
5083 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5084 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5085 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5090 * Keep in sync with mono_arch_emit_epilog
5092 g_assert (!cfg->method->save_lmf);
5094 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5096 if (cfg->used_int_regs)
5097 ARM_POP (code, cfg->used_int_regs);
5098 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5100 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5103 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5104 if (cfg->compile_aot) {
5105 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5107 *(gpointer*)code = NULL;
5109 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5111 code = mono_arm_patchable_b (code, ARMCOND_AL);
5112 cfg->thunk_area += THUNK_SIZE;
5117 /* ensure ins->sreg1 is not NULL */
5118 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5121 g_assert (cfg->sig_cookie < 128);
5122 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5123 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5133 call = (MonoCallInst*)ins;
5136 code = emit_float_args (cfg, call, code, &max_len, &offset);
5138 if (ins->flags & MONO_INST_HAS_METHOD)
5139 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5141 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5142 code = emit_call_seq (cfg, code);
5143 ins->flags |= MONO_INST_GC_CALLSITE;
5144 ins->backend.pc_offset = code - cfg->native_code;
5145 code = emit_move_return_value (cfg, ins, code);
5152 case OP_VOIDCALL_REG:
5155 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5157 code = emit_call_reg (code, ins->sreg1);
5158 ins->flags |= MONO_INST_GC_CALLSITE;
5159 ins->backend.pc_offset = code - cfg->native_code;
5160 code = emit_move_return_value (cfg, ins, code);
5162 case OP_FCALL_MEMBASE:
5163 case OP_RCALL_MEMBASE:
5164 case OP_LCALL_MEMBASE:
5165 case OP_VCALL_MEMBASE:
5166 case OP_VCALL2_MEMBASE:
5167 case OP_VOIDCALL_MEMBASE:
5168 case OP_CALL_MEMBASE: {
5169 g_assert (ins->sreg1 != ARMREG_LR);
5170 call = (MonoCallInst*)ins;
5173 code = emit_float_args (cfg, call, code, &max_len, &offset);
5174 if (!arm_is_imm12 (ins->inst_offset))
5175 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5176 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5177 if (!arm_is_imm12 (ins->inst_offset))
5178 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5180 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5181 ins->flags |= MONO_INST_GC_CALLSITE;
5182 ins->backend.pc_offset = code - cfg->native_code;
5183 code = emit_move_return_value (cfg, ins, code);
5186 case OP_GENERIC_CLASS_INIT: {
5187 static int byte_offset = -1;
5188 static guint8 bitmask;
5192 if (byte_offset < 0)
5193 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5195 g_assert (arm_is_imm8 (byte_offset));
5196 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5197 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5198 g_assert (imm8 >= 0);
5199 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5200 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5202 ARM_B_COND (code, ARMCOND_NE, 0);
5204 /* Uninitialized case */
5205 g_assert (ins->sreg1 == ARMREG_R0);
5207 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5208 (gpointer)"mono_generic_class_init");
5209 code = emit_call_seq (cfg, code);
5211 /* Initialized case */
5212 arm_patch (jump, code);
5216 /* round the size to 8 bytes */
5217 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
5218 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
5219 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5220 /* memzero the area: dreg holds the size, sp is the pointer */
5221 if (ins->flags & MONO_INST_INIT) {
5222 guint8 *start_loop, *branch_to_cond;
5223 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5224 branch_to_cond = code;
5227 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5228 arm_patch (branch_to_cond, code);
5229 /* decrement by 4 and set flags */
5230 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5231 ARM_B_COND (code, ARMCOND_GE, 0);
5232 arm_patch (code - 4, start_loop);
5234 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5235 if (cfg->param_area)
5236 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5241 MonoInst *var = cfg->dyn_call_var;
5243 g_assert (var->opcode == OP_REGOFFSET);
5244 g_assert (arm_is_imm12 (var->inst_offset));
5246 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5247 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5249 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5251 /* Save args buffer */
5252 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5254 /* Set stack slots using R0 as scratch reg */
5255 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5256 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5257 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5258 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5261 /* Set argument registers */
5262 for (i = 0; i < PARAM_REGS; ++i)
5263 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5266 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5267 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5270 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5271 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5272 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5276 if (ins->sreg1 != ARMREG_R0)
5277 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5278 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5279 (gpointer)"mono_arch_throw_exception");
5280 code = emit_call_seq (cfg, code);
5284 if (ins->sreg1 != ARMREG_R0)
5285 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5286 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5287 (gpointer)"mono_arch_rethrow_exception");
5288 code = emit_call_seq (cfg, code);
5291 case OP_START_HANDLER: {
5292 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5295 /* Reserve a param area, see filter-stack.exe */
5296 if (cfg->param_area) {
5297 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5298 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5300 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5301 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5305 if (arm_is_imm12 (spvar->inst_offset)) {
5306 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5308 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5309 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5313 case OP_ENDFILTER: {
5314 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5317 /* Free the param area */
5318 if (cfg->param_area) {
5319 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5320 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5322 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5323 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5327 if (ins->sreg1 != ARMREG_R0)
5328 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5329 if (arm_is_imm12 (spvar->inst_offset)) {
5330 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5332 g_assert (ARMREG_IP != spvar->inst_basereg);
5333 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5334 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5336 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5339 case OP_ENDFINALLY: {
5340 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5343 /* Free the param area */
5344 if (cfg->param_area) {
5345 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5346 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5348 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5349 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5353 if (arm_is_imm12 (spvar->inst_offset)) {
5354 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5356 g_assert (ARMREG_IP != spvar->inst_basereg);
5357 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5358 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5360 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5363 case OP_CALL_HANDLER:
5364 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5365 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5366 cfg->thunk_area += THUNK_SIZE;
5367 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5370 if (ins->dreg != ARMREG_R0)
5371 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5375 ins->inst_c0 = code - cfg->native_code;
5378 /*if (ins->inst_target_bb->native_offset) {
5380 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5382 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5383 code = mono_arm_patchable_b (code, ARMCOND_AL);
5387 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5391 * In the normal case we have:
5392 * ldr pc, [pc, ins->sreg1 << 2]
5395 * ldr lr, [pc, ins->sreg1 << 2]
5397 * After follows the data.
5398 * FIXME: add aot support.
5400 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5401 #ifdef USE_JUMP_TABLES
5403 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5404 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5405 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5409 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5410 if (offset + max_len > (cfg->code_size - 16)) {
5411 cfg->code_size += max_len;
5412 cfg->code_size *= 2;
5413 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5414 code = cfg->native_code + offset;
5416 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5418 code += 4 * GPOINTER_TO_INT (ins->klass);
5423 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5424 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5428 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5429 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5433 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5434 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5438 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5439 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5443 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5444 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5447 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5448 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5451 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5452 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5455 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5456 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5459 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5460 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5463 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5464 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5466 case OP_COND_EXC_EQ:
5467 case OP_COND_EXC_NE_UN:
5468 case OP_COND_EXC_LT:
5469 case OP_COND_EXC_LT_UN:
5470 case OP_COND_EXC_GT:
5471 case OP_COND_EXC_GT_UN:
5472 case OP_COND_EXC_GE:
5473 case OP_COND_EXC_GE_UN:
5474 case OP_COND_EXC_LE:
5475 case OP_COND_EXC_LE_UN:
5476 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5478 case OP_COND_EXC_IEQ:
5479 case OP_COND_EXC_INE_UN:
5480 case OP_COND_EXC_ILT:
5481 case OP_COND_EXC_ILT_UN:
5482 case OP_COND_EXC_IGT:
5483 case OP_COND_EXC_IGT_UN:
5484 case OP_COND_EXC_IGE:
5485 case OP_COND_EXC_IGE_UN:
5486 case OP_COND_EXC_ILE:
5487 case OP_COND_EXC_ILE_UN:
5488 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5491 case OP_COND_EXC_IC:
5492 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5494 case OP_COND_EXC_OV:
5495 case OP_COND_EXC_IOV:
5496 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5498 case OP_COND_EXC_NC:
5499 case OP_COND_EXC_INC:
5500 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5502 case OP_COND_EXC_NO:
5503 case OP_COND_EXC_INO:
5504 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5516 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5519 /* floating point opcodes */
5521 if (cfg->compile_aot) {
5522 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5524 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5526 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5529 /* FIXME: we can optimize the imm load by dealing with part of
5530 * the displacement in LDFD (aligning to 512).
5532 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5533 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5537 if (cfg->compile_aot) {
5538 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5540 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5543 ARM_CVTS (code, ins->dreg, ins->dreg);
5545 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5546 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5548 ARM_CVTS (code, ins->dreg, ins->dreg);
5551 case OP_STORER8_MEMBASE_REG:
5552 /* This is generated by the local regalloc pass which runs after the lowering pass */
5553 if (!arm_is_fpimm8 (ins->inst_offset)) {
5554 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5555 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5556 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5558 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5561 case OP_LOADR8_MEMBASE:
5562 /* This is generated by the local regalloc pass which runs after the lowering pass */
5563 if (!arm_is_fpimm8 (ins->inst_offset)) {
5564 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5565 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5566 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5568 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5571 case OP_STORER4_MEMBASE_REG:
5572 g_assert (arm_is_fpimm8 (ins->inst_offset));
5574 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5576 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5577 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5578 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5579 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5582 case OP_LOADR4_MEMBASE:
5584 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5586 g_assert (arm_is_fpimm8 (ins->inst_offset));
5587 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5588 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5589 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5590 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5593 case OP_ICONV_TO_R_UN: {
5594 g_assert_not_reached ();
5597 case OP_ICONV_TO_R4:
5599 ARM_FMSR (code, ins->dreg, ins->sreg1);
5600 ARM_FSITOS (code, ins->dreg, ins->dreg);
5602 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5603 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5604 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5605 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5606 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5609 case OP_ICONV_TO_R8:
5610 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5611 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5612 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5613 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5617 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5618 if (sig_ret->type == MONO_TYPE_R4) {
5620 g_assert (!IS_HARD_FLOAT);
5621 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5623 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5626 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5630 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5632 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5636 case OP_FCONV_TO_I1:
5637 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5639 case OP_FCONV_TO_U1:
5640 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5642 case OP_FCONV_TO_I2:
5643 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5645 case OP_FCONV_TO_U2:
5646 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5648 case OP_FCONV_TO_I4:
5650 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5652 case OP_FCONV_TO_U4:
5654 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5656 case OP_FCONV_TO_I8:
5657 case OP_FCONV_TO_U8:
5658 g_assert_not_reached ();
5659 /* Implemented as helper calls */
5661 case OP_LCONV_TO_R_UN:
5662 g_assert_not_reached ();
5663 /* Implemented as helper calls */
5665 case OP_LCONV_TO_OVF_I4_2: {
5666 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5668 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5671 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5672 high_bit_not_set = code;
5673 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5675 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5676 valid_negative = code;
5677 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5678 invalid_negative = code;
5679 ARM_B_COND (code, ARMCOND_AL, 0);
5681 arm_patch (high_bit_not_set, code);
5683 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5684 valid_positive = code;
5685 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5687 arm_patch (invalid_negative, code);
5688 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5690 arm_patch (valid_negative, code);
5691 arm_patch (valid_positive, code);
5693 if (ins->dreg != ins->sreg1)
5694 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5698 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5701 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5704 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5707 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5710 ARM_NEGD (code, ins->dreg, ins->sreg1);
5714 g_assert_not_reached ();
5718 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5724 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5729 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5732 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5733 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5737 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5740 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5741 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5745 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5748 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5749 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5750 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5754 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5757 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5758 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5762 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5765 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5766 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5767 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5771 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5774 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5775 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5779 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5782 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5783 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5787 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5790 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5791 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5794 /* ARM FPA flags table:
5795 * N Less than ARMCOND_MI
5796 * Z Equal ARMCOND_EQ
5797 * C Greater Than or Equal ARMCOND_CS
5798 * V Unordered ARMCOND_VS
5801 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5804 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5807 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5810 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5811 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5817 g_assert_not_reached ();
5821 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5823 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5824 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5825 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5829 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5830 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5835 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5836 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5838 #ifdef USE_JUMP_TABLES
5840 gpointer *jte = mono_jumptable_add_entries (2);
5841 jte [0] = GUINT_TO_POINTER (0xffffffff);
5842 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5843 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5844 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5847 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5848 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5850 *(guint32*)code = 0xffffffff;
5852 *(guint32*)code = 0x7fefffff;
5855 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5857 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5858 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5860 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5861 ARM_CPYD (code, ins->dreg, ins->sreg1);
5863 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5864 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5869 case OP_RCONV_TO_I1:
5870 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5872 case OP_RCONV_TO_U1:
5873 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5875 case OP_RCONV_TO_I2:
5876 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5878 case OP_RCONV_TO_U2:
5879 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5881 case OP_RCONV_TO_I4:
5882 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5884 case OP_RCONV_TO_U4:
5885 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5887 case OP_RCONV_TO_R4:
5889 if (ins->dreg != ins->sreg1)
5890 ARM_CPYS (code, ins->dreg, ins->sreg1);
5892 case OP_RCONV_TO_R8:
5894 ARM_CVTS (code, ins->dreg, ins->sreg1);
5897 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5900 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5903 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5906 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5909 ARM_NEGS (code, ins->dreg, ins->sreg1);
5913 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5916 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5917 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5921 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5924 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5925 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5929 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5932 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5933 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5934 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5938 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5941 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5942 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5946 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5949 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5950 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5951 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5955 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5958 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5959 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5963 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5966 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5967 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5971 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5974 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5975 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5978 case OP_GC_LIVENESS_DEF:
5979 case OP_GC_LIVENESS_USE:
5980 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5981 ins->backend.pc_offset = code - cfg->native_code;
5983 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5984 ins->backend.pc_offset = code - cfg->native_code;
5985 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5987 case OP_GC_SAFE_POINT: {
5988 #if defined (USE_COOP_GC)
5989 const char *polling_func = NULL;
5992 polling_func = "mono_threads_state_poll";
5993 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5994 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5996 ARM_B_COND (code, ARMCOND_EQ, 0);
5997 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5998 code = emit_call_seq (cfg, code);
5999 arm_patch (buf [0], code);
6005 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6006 g_assert_not_reached ();
6009 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
6010 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
6011 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6012 g_assert_not_reached ();
6018 last_offset = offset;
6021 cfg->code_len = code - cfg->native_code;
6024 #endif /* DISABLE_JIT */
6027 mono_arch_register_lowlevel_calls (void)
6029 /* The signature doesn't matter */
6030 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
6031 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
6032 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
6034 #ifndef MONO_CROSS_COMPILE
6035 if (mono_arm_have_tls_get ()) {
6036 if (mono_arm_have_fast_tls ()) {
6037 mono_register_jit_icall (mono_fast_get_tls_key, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
6038 mono_register_jit_icall (mono_fast_set_tls_key, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
6040 mono_tramp_info_register (
6041 mono_tramp_info_create (
6043 (guint8*)mono_fast_get_tls_key,
6044 (guint8*)mono_fast_get_tls_key_end - (guint8*)mono_fast_get_tls_key,
6046 mono_arch_get_cie_program ()
6050 mono_tramp_info_register (
6051 mono_tramp_info_create (
6053 (guint8*)mono_fast_set_tls_key,
6054 (guint8*)mono_fast_set_tls_key_end - (guint8*)mono_fast_set_tls_key,
6056 mono_arch_get_cie_program ()
6061 g_warning ("No fast tls on device. Using fallbacks.");
6062 mono_register_jit_icall (mono_fallback_get_tls_key, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
6063 mono_register_jit_icall (mono_fallback_set_tls_key, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
6069 #define patch_lis_ori(ip,val) do {\
6070 guint16 *__lis_ori = (guint16*)(ip); \
6071 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
6072 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
6076 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6078 unsigned char *ip = ji->ip.i + code;
6080 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6084 case MONO_PATCH_INFO_SWITCH: {
6085 #ifdef USE_JUMP_TABLES
6086 gpointer *jt = mono_jumptable_get_entry (ip);
6088 gpointer *jt = (gpointer*)(ip + 8);
6091 /* jt is the inlined jump table, 2 instructions after ip
6092 * In the normal case we store the absolute addresses,
6093 * otherwise the displacements.
6095 for (i = 0; i < ji->data.table->table_size; i++)
6096 jt [i] = code + (int)ji->data.table->table [i];
6099 case MONO_PATCH_INFO_IP:
6100 g_assert_not_reached ();
6101 patch_lis_ori (ip, ip);
6103 case MONO_PATCH_INFO_METHOD_REL:
6104 g_assert_not_reached ();
6105 *((gpointer *)(ip)) = target;
6107 case MONO_PATCH_INFO_METHODCONST:
6108 case MONO_PATCH_INFO_CLASS:
6109 case MONO_PATCH_INFO_IMAGE:
6110 case MONO_PATCH_INFO_FIELD:
6111 case MONO_PATCH_INFO_VTABLE:
6112 case MONO_PATCH_INFO_IID:
6113 case MONO_PATCH_INFO_SFLDA:
6114 case MONO_PATCH_INFO_LDSTR:
6115 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6116 case MONO_PATCH_INFO_LDTOKEN:
6117 g_assert_not_reached ();
6118 /* from OP_AOTCONST : lis + ori */
6119 patch_lis_ori (ip, target);
6121 case MONO_PATCH_INFO_R4:
6122 case MONO_PATCH_INFO_R8:
6123 g_assert_not_reached ();
6124 *((gconstpointer *)(ip + 2)) = target;
6126 case MONO_PATCH_INFO_EXC_NAME:
6127 g_assert_not_reached ();
6128 *((gconstpointer *)(ip + 1)) = target;
6130 case MONO_PATCH_INFO_NONE:
6131 case MONO_PATCH_INFO_BB_OVF:
6132 case MONO_PATCH_INFO_EXC_OVF:
6133 /* everything is dealt with at epilog output time */
6136 arm_patch_general (cfg, domain, ip, target);
6142 mono_arm_unaligned_stack (MonoMethod *method)
6144 g_assert_not_reached ();
6150 * Stack frame layout:
6152 * ------------------- fp
6153 * MonoLMF structure or saved registers
6154 * -------------------
6156 * -------------------
6158 * -------------------
6159 * optional 8 bytes for tracing
6160 * -------------------
6161 * param area size is cfg->param_area
6162 * ------------------- sp
6165 mono_arch_emit_prolog (MonoCompile *cfg)
6167 MonoMethod *method = cfg->method;
6169 MonoMethodSignature *sig;
6171 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6176 int prev_sp_offset, reg_offset;
6178 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6181 sig = mono_method_signature (method);
6182 cfg->code_size = 256 + sig->param_count * 64;
6183 code = cfg->native_code = g_malloc (cfg->code_size);
6185 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6187 alloc_size = cfg->stack_offset;
6193 * The iphone uses R7 as the frame pointer, and it points at the saved
6198 * We can't use r7 as a frame pointer since it points into the middle of
6199 * the frame, so we keep using our own frame pointer.
6200 * FIXME: Optimize this.
6202 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6203 prev_sp_offset += 8; /* r7 and lr */
6204 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6205 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6206 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6209 if (!method->save_lmf) {
6211 /* No need to push LR again */
6212 if (cfg->used_int_regs)
6213 ARM_PUSH (code, cfg->used_int_regs);
6215 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6216 prev_sp_offset += 4;
6218 for (i = 0; i < 16; ++i) {
6219 if (cfg->used_int_regs & (1 << i))
6220 prev_sp_offset += 4;
6222 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6224 for (i = 0; i < 16; ++i) {
6225 if ((cfg->used_int_regs & (1 << i))) {
6226 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6227 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6232 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6233 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6235 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6236 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6239 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6240 ARM_PUSH (code, 0x5ff0);
6241 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6242 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6244 for (i = 0; i < 16; ++i) {
6245 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6246 /* The original r7 is saved at the start */
6247 if (!(iphone_abi && i == ARMREG_R7))
6248 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6252 g_assert (reg_offset == 4 * 10);
6253 pos += sizeof (MonoLMF) - (4 * 10);
6257 orig_alloc_size = alloc_size;
6258 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6259 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6260 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6261 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6264 /* the stack used in the pushed regs */
6265 if (prev_sp_offset & 4)
6267 cfg->stack_usage = alloc_size;
6269 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6270 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6272 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6273 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6275 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6277 if (cfg->frame_reg != ARMREG_SP) {
6278 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6279 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6281 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6282 prev_sp_offset += alloc_size;
6284 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6285 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6287 /* compute max_offset in order to use short forward jumps
6288 * we could skip do it on arm because the immediate displacement
6289 * for jumps is large enough, it may be useful later for constant pools
6292 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6293 MonoInst *ins = bb->code;
6294 bb->max_offset = max_offset;
6296 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6299 MONO_BB_FOR_EACH_INS (bb, ins)
6300 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6303 /* stack alignment check */
6307 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6308 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6309 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6310 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6312 ARM_B_COND (code, ARMCOND_EQ, 0);
6313 if (cfg->compile_aot)
6314 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6316 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6317 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6318 code = emit_call_seq (cfg, code);
6319 code = emit_call_reg (code, ARMREG_LR);
6320 arm_patch (buf [0], code);
6324 /* store runtime generic context */
6325 if (cfg->rgctx_var) {
6326 MonoInst *ins = cfg->rgctx_var;
6328 g_assert (ins->opcode == OP_REGOFFSET);
6330 if (arm_is_imm12 (ins->inst_offset)) {
6331 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6333 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6334 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6338 /* load arguments allocated to register from the stack */
6341 cinfo = get_call_info (NULL, sig);
6343 if (cinfo->ret.storage == RegTypeStructByAddr) {
6344 ArgInfo *ainfo = &cinfo->ret;
6345 inst = cfg->vret_addr;
6346 g_assert (arm_is_imm12 (inst->inst_offset));
6347 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6350 if (sig->call_convention == MONO_CALL_VARARG) {
6351 ArgInfo *cookie = &cinfo->sig_cookie;
6353 /* Save the sig cookie address */
6354 g_assert (cookie->storage == RegTypeBase);
6356 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6357 g_assert (arm_is_imm12 (cfg->sig_cookie));
6358 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6359 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6362 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6363 ArgInfo *ainfo = cinfo->args + i;
6364 inst = cfg->args [pos];
6366 if (cfg->verbose_level > 2)
6367 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6369 if (inst->opcode == OP_REGVAR) {
6370 if (ainfo->storage == RegTypeGeneral)
6371 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6372 else if (ainfo->storage == RegTypeFP) {
6373 g_assert_not_reached ();
6374 } else if (ainfo->storage == RegTypeBase) {
6375 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6376 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6378 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6379 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6382 g_assert_not_reached ();
6384 if (cfg->verbose_level > 2)
6385 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6387 switch (ainfo->storage) {
6389 for (part = 0; part < ainfo->nregs; part ++) {
6390 if (ainfo->esize == 4)
6391 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6393 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6396 case RegTypeGeneral:
6397 case RegTypeIRegPair:
6398 case RegTypeGSharedVtInReg:
6399 switch (ainfo->size) {
6401 if (arm_is_imm12 (inst->inst_offset))
6402 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6404 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6405 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6409 if (arm_is_imm8 (inst->inst_offset)) {
6410 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6412 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6413 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6417 if (arm_is_imm12 (inst->inst_offset)) {
6418 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6420 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6421 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6423 if (arm_is_imm12 (inst->inst_offset + 4)) {
6424 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6426 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6427 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6431 if (arm_is_imm12 (inst->inst_offset)) {
6432 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6434 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6435 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6440 case RegTypeBaseGen:
6441 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6442 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6444 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6445 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6447 if (arm_is_imm12 (inst->inst_offset + 4)) {
6448 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6449 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6451 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6452 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6453 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6454 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6458 case RegTypeGSharedVtOnStack:
6459 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6460 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6462 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6463 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6466 switch (ainfo->size) {
6468 if (arm_is_imm8 (inst->inst_offset)) {
6469 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6471 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6472 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6476 if (arm_is_imm8 (inst->inst_offset)) {
6477 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6479 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6480 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6484 if (arm_is_imm12 (inst->inst_offset)) {
6485 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6487 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6488 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6490 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6491 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6493 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6494 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6496 if (arm_is_imm12 (inst->inst_offset + 4)) {
6497 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6499 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6500 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6504 if (arm_is_imm12 (inst->inst_offset)) {
6505 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6507 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6508 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6514 int imm8, rot_amount;
6516 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6517 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6518 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6520 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6522 if (ainfo->size == 8)
6523 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6525 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6528 case RegTypeStructByVal: {
6529 int doffset = inst->inst_offset;
6533 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6534 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6535 if (arm_is_imm12 (doffset)) {
6536 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6538 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6539 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6541 soffset += sizeof (gpointer);
6542 doffset += sizeof (gpointer);
6544 if (ainfo->vtsize) {
6545 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6546 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6547 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6551 case RegTypeStructByAddr:
6552 g_assert_not_reached ();
6553 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6554 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6556 g_assert_not_reached ();
6563 if (method->save_lmf)
6564 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6567 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6569 if (cfg->arch.seq_point_info_var) {
6570 MonoInst *ins = cfg->arch.seq_point_info_var;
6572 /* Initialize the variable from a GOT slot */
6573 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6574 #ifdef USE_JUMP_TABLES
6576 gpointer *jte = mono_jumptable_add_entry ();
6577 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6578 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6580 /** XXX: is it correct? */
6582 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6584 *(gpointer*)code = NULL;
6587 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6589 g_assert (ins->opcode == OP_REGOFFSET);
6591 if (arm_is_imm12 (ins->inst_offset)) {
6592 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6594 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6595 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6599 /* Initialize ss_trigger_page_var */
6600 if (!cfg->soft_breakpoints) {
6601 MonoInst *info_var = cfg->arch.seq_point_info_var;
6602 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6603 int dreg = ARMREG_LR;
6606 g_assert (info_var->opcode == OP_REGOFFSET);
6607 g_assert (arm_is_imm12 (info_var->inst_offset));
6609 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6610 /* Load the trigger page addr */
6611 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6612 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6616 if (cfg->arch.seq_point_read_var) {
6617 MonoInst *read_ins = cfg->arch.seq_point_read_var;
6618 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6619 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6620 #ifdef USE_JUMP_TABLES
6623 g_assert (read_ins->opcode == OP_REGOFFSET);
6624 g_assert (arm_is_imm12 (read_ins->inst_offset));
6625 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6626 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6627 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6628 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6630 #ifdef USE_JUMP_TABLES
6631 jte = mono_jumptable_add_entries (3);
6632 jte [0] = (gpointer)&ss_trigger_var;
6633 jte [1] = single_step_tramp;
6634 jte [2] = breakpoint_tramp;
6635 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6637 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6639 *(volatile int **)code = &ss_trigger_var;
6641 *(gpointer*)code = single_step_tramp;
6643 *(gpointer*)code = breakpoint_tramp;
6647 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6648 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
6649 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6650 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6651 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
6652 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6655 cfg->code_len = code - cfg->native_code;
6656 g_assert (cfg->code_len < cfg->code_size);
6663 mono_arch_emit_epilog (MonoCompile *cfg)
6665 MonoMethod *method = cfg->method;
6666 int pos, i, rot_amount;
6667 int max_epilog_size = 16 + 20*4;
6671 if (cfg->method->save_lmf)
6672 max_epilog_size += 128;
6674 if (mono_jit_trace_calls != NULL)
6675 max_epilog_size += 50;
6677 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6678 max_epilog_size += 50;
6680 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6681 cfg->code_size *= 2;
6682 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6683 cfg->stat_code_reallocs++;
6687 * Keep in sync with OP_JMP
6689 code = cfg->native_code + cfg->code_len;
6691 /* Save the uwind state which is needed by the out-of-line code */
6692 mono_emit_unwind_op_remember_state (cfg, code);
6694 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6695 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6699 /* Load returned vtypes into registers if needed */
6700 cinfo = cfg->arch.cinfo;
6701 switch (cinfo->ret.storage) {
6702 case RegTypeStructByVal: {
6703 MonoInst *ins = cfg->ret;
6705 if (arm_is_imm12 (ins->inst_offset)) {
6706 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6708 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6709 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6714 MonoInst *ins = cfg->ret;
6716 for (i = 0; i < cinfo->ret.nregs; ++i) {
6717 if (cinfo->ret.esize == 4)
6718 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6720 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6728 if (method->save_lmf) {
6729 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6730 /* all but r0-r3, sp and pc */
6731 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6734 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6736 /* This points to r4 inside MonoLMF->iregs */
6737 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6739 regmask = 0x9ff0; /* restore lr to pc */
6740 /* Skip caller saved registers not used by the method */
6741 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6742 regmask &= ~(1 << reg);
6747 /* Restored later */
6748 regmask &= ~(1 << ARMREG_PC);
6749 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6750 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6751 for (i = 0; i < 16; i++) {
6752 if (regmask & (1 << i))
6755 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6757 ARM_POP (code, regmask);
6759 for (i = 0; i < 16; i++) {
6760 if (regmask & (1 << i))
6761 mono_emit_unwind_op_same_value (cfg, code, i);
6763 /* Restore saved r7, restore LR to PC */
6764 /* Skip lr from the lmf */
6765 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6766 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6767 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6768 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6771 int i, nused_int_regs = 0;
6773 for (i = 0; i < 16; i++) {
6774 if (cfg->used_int_regs & (1 << i))
6778 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6779 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6781 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6782 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6785 if (cfg->frame_reg != ARMREG_SP) {
6786 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6790 /* Restore saved gregs */
6791 if (cfg->used_int_regs) {
6792 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6793 ARM_POP (code, cfg->used_int_regs);
6794 for (i = 0; i < 16; i++) {
6795 if (cfg->used_int_regs & (1 << i))
6796 mono_emit_unwind_op_same_value (cfg, code, i);
6799 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6800 /* Restore saved r7, restore LR to PC */
6801 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6803 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6804 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6808 /* Restore the unwind state to be the same as before the epilog */
6809 mono_emit_unwind_op_restore_state (cfg, code);
6811 cfg->code_len = code - cfg->native_code;
6813 g_assert (cfg->code_len < cfg->code_size);
6818 mono_arch_emit_exceptions (MonoCompile *cfg)
6820 MonoJumpInfo *patch_info;
6823 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6824 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6825 int max_epilog_size = 50;
6827 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6828 exc_throw_pos [i] = NULL;
6829 exc_throw_found [i] = 0;
6832 /* count the number of exception infos */
6835 * make sure we have enough space for exceptions
6837 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6838 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6839 i = mini_exception_id_by_name (patch_info->data.target);
6840 if (!exc_throw_found [i]) {
6841 max_epilog_size += 32;
6842 exc_throw_found [i] = TRUE;
6847 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6848 cfg->code_size *= 2;
6849 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6850 cfg->stat_code_reallocs++;
6853 code = cfg->native_code + cfg->code_len;
6855 /* add code to raise exceptions */
6856 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6857 switch (patch_info->type) {
6858 case MONO_PATCH_INFO_EXC: {
6859 MonoClass *exc_class;
6860 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6862 i = mini_exception_id_by_name (patch_info->data.target);
6863 if (exc_throw_pos [i]) {
6864 arm_patch (ip, exc_throw_pos [i]);
6865 patch_info->type = MONO_PATCH_INFO_NONE;
6868 exc_throw_pos [i] = code;
6870 arm_patch (ip, code);
6872 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6873 g_assert (exc_class);
6875 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6876 #ifdef USE_JUMP_TABLES
6878 gpointer *jte = mono_jumptable_add_entries (2);
6879 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6880 patch_info->data.name = "mono_arch_throw_corlib_exception";
6881 patch_info->ip.i = code - cfg->native_code;
6882 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6883 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6884 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6885 ARM_BLX_REG (code, ARMREG_IP);
6886 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6889 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6890 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6891 patch_info->data.name = "mono_arch_throw_corlib_exception";
6892 patch_info->ip.i = code - cfg->native_code;
6894 cfg->thunk_area += THUNK_SIZE;
6895 *(guint32*)(gpointer)code = exc_class->type_token;
6906 cfg->code_len = code - cfg->native_code;
6908 g_assert (cfg->code_len < cfg->code_size);
6912 #endif /* #ifndef DISABLE_JIT */
6915 mono_arch_finish_init (void)
6920 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6925 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6932 mono_arch_print_tree (MonoInst *tree, int arity)
6942 mono_arch_get_patch_offset (guint8 *code)
6949 mono_arch_flush_register_windows (void)
6954 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6956 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6960 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6962 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6966 mono_arch_get_cie_program (void)
6970 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6975 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6976 #define BASE_SIZE (6 * 4)
6977 #define BSEARCH_ENTRY_SIZE (4 * 4)
6978 #define CMP_SIZE (3 * 4)
6979 #define BRANCH_SIZE (1 * 4)
6980 #define CALL_SIZE (2 * 4)
6981 #define WMC_SIZE (8 * 4)
6982 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6984 #ifdef USE_JUMP_TABLES
6986 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6988 g_assert (base [index] == NULL);
6989 base [index] = value;
6992 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6994 if (arm_is_imm12 (jti * 4)) {
6995 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6997 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6998 if ((jti * 4) >> 16)
6999 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
7000 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
7006 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
7008 guint32 delta = DISTANCE (target, code);
7010 g_assert (delta >= 0 && delta <= 0xFFF);
7011 *target = *target | delta;
7017 #ifdef ENABLE_WRONG_METHOD_CHECK
7019 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
7021 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
7027 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7028 gpointer fail_tramp)
7031 arminstr_t *code, *start;
7032 #ifdef USE_JUMP_TABLES
7035 gboolean large_offsets = FALSE;
7036 guint32 **constant_pool_starts;
7037 arminstr_t *vtable_target = NULL;
7038 int extra_space = 0;
7040 #ifdef ENABLE_WRONG_METHOD_CHECK
7046 #ifdef USE_JUMP_TABLES
7047 for (i = 0; i < count; ++i) {
7048 MonoIMTCheckItem *item = imt_entries [i];
7049 item->chunk_size += 4 * 16;
7050 if (!item->is_equals)
7051 imt_entries [item->check_target_idx]->compare_done = TRUE;
7052 size += item->chunk_size;
7055 constant_pool_starts = g_new0 (guint32*, count);
7057 for (i = 0; i < count; ++i) {
7058 MonoIMTCheckItem *item = imt_entries [i];
7059 if (item->is_equals) {
7060 gboolean fail_case = !item->check_target_idx && fail_tramp;
7062 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
7063 item->chunk_size += 32;
7064 large_offsets = TRUE;
7067 if (item->check_target_idx || fail_case) {
7068 if (!item->compare_done || fail_case)
7069 item->chunk_size += CMP_SIZE;
7070 item->chunk_size += BRANCH_SIZE;
7072 #ifdef ENABLE_WRONG_METHOD_CHECK
7073 item->chunk_size += WMC_SIZE;
7077 item->chunk_size += 16;
7078 large_offsets = TRUE;
7080 item->chunk_size += CALL_SIZE;
7082 item->chunk_size += BSEARCH_ENTRY_SIZE;
7083 imt_entries [item->check_target_idx]->compare_done = TRUE;
7085 size += item->chunk_size;
7089 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
7093 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7095 code = mono_domain_code_reserve (domain, size);
7098 unwind_ops = mono_arch_get_cie_program ();
7101 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
7102 for (i = 0; i < count; ++i) {
7103 MonoIMTCheckItem *item = imt_entries [i];
7104 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
7108 #ifdef USE_JUMP_TABLES
7109 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7110 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 3 * sizeof (mgreg_t));
7111 #define VTABLE_JTI 0
7112 #define IMT_METHOD_OFFSET 0
7113 #define TARGET_CODE_OFFSET 1
7114 #define JUMP_CODE_OFFSET 2
7115 #define RECORDS_PER_ENTRY 3
7116 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
7117 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
7118 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
7120 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
7121 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
7122 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
7123 set_jumptable_element (jte, VTABLE_JTI, vtable);
7125 if (large_offsets) {
7126 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7127 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
7129 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7130 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7132 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7133 vtable_target = code;
7134 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7136 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7138 for (i = 0; i < count; ++i) {
7139 MonoIMTCheckItem *item = imt_entries [i];
7140 #ifdef USE_JUMP_TABLES
7141 guint32 imt_method_jti = 0, target_code_jti = 0;
7143 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7145 gint32 vtable_offset;
7147 item->code_target = (guint8*)code;
7149 if (item->is_equals) {
7150 gboolean fail_case = !item->check_target_idx && fail_tramp;
7152 if (item->check_target_idx || fail_case) {
7153 if (!item->compare_done || fail_case) {
7154 #ifdef USE_JUMP_TABLES
7155 imt_method_jti = IMT_METHOD_JTI (i);
7156 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7159 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7161 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7163 #ifdef USE_JUMP_TABLES
7164 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7165 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7166 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7168 item->jmp_code = (guint8*)code;
7169 ARM_B_COND (code, ARMCOND_NE, 0);
7172 /*Enable the commented code to assert on wrong method*/
7173 #ifdef ENABLE_WRONG_METHOD_CHECK
7174 #ifdef USE_JUMP_TABLES
7175 imt_method_jti = IMT_METHOD_JTI (i);
7176 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7179 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7181 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7183 ARM_B_COND (code, ARMCOND_EQ, 0);
7185 /* Define this if your system is so bad that gdb is failing. */
7186 #ifdef BROKEN_DEV_ENV
7187 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7189 arm_patch (code - 1, mini_dump_bad_imt);
7193 arm_patch (cond, code);
7197 if (item->has_target_code) {
7198 /* Load target address */
7199 #ifdef USE_JUMP_TABLES
7200 target_code_jti = TARGET_CODE_JTI (i);
7201 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7202 /* Restore registers */
7203 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7204 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7206 ARM_BX (code, ARMREG_R1);
7207 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7209 target_code_ins = code;
7210 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7211 /* Save it to the fourth slot */
7212 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7213 /* Restore registers and branch */
7214 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7216 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7219 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7220 if (!arm_is_imm12 (vtable_offset)) {
7222 * We need to branch to a computed address but we don't have
7223 * a free register to store it, since IP must contain the
7224 * vtable address. So we push the two values to the stack, and
7225 * load them both using LDM.
7227 /* Compute target address */
7228 #ifdef USE_JUMP_TABLES
7229 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7230 if (vtable_offset >> 16)
7231 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7232 /* IP had vtable base. */
7233 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7234 /* Restore registers and branch */
7235 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7236 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7237 ARM_BX (code, ARMREG_IP);
7239 vtable_offset_ins = code;
7240 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7241 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7242 /* Save it to the fourth slot */
7243 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7244 /* Restore registers and branch */
7245 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7247 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7250 #ifdef USE_JUMP_TABLES
7251 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7252 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7253 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7254 ARM_BX (code, ARMREG_IP);
7256 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7257 if (large_offsets) {
7258 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7259 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7261 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7262 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7268 #ifdef USE_JUMP_TABLES
7269 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7270 target_code_jti = TARGET_CODE_JTI (i);
7271 /* Load target address */
7272 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7273 /* Restore registers */
7274 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7275 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7277 ARM_BX (code, ARMREG_R1);
7278 set_jumptable_element (jte, target_code_jti, fail_tramp);
7280 arm_patch (item->jmp_code, (guchar*)code);
7282 target_code_ins = code;
7283 /* Load target address */
7284 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7285 /* Save it to the fourth slot */
7286 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7287 /* Restore registers and branch */
7288 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7290 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7292 item->jmp_code = NULL;
7295 #ifdef USE_JUMP_TABLES
7297 set_jumptable_element (jte, imt_method_jti, item->key);
7300 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7302 /*must emit after unconditional branch*/
7303 if (vtable_target) {
7304 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7305 item->chunk_size += 4;
7306 vtable_target = NULL;
7309 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7310 constant_pool_starts [i] = code;
7312 code += extra_space;
7317 #ifdef USE_JUMP_TABLES
7318 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7319 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7320 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7321 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7322 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7324 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7325 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7327 item->jmp_code = (guint8*)code;
7328 ARM_B_COND (code, ARMCOND_HS, 0);
7334 for (i = 0; i < count; ++i) {
7335 MonoIMTCheckItem *item = imt_entries [i];
7336 if (item->jmp_code) {
7337 if (item->check_target_idx)
7338 #ifdef USE_JUMP_TABLES
7339 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7341 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7344 if (i > 0 && item->is_equals) {
7346 #ifdef USE_JUMP_TABLES
7347 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7348 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7350 arminstr_t *space_start = constant_pool_starts [i];
7351 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7352 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7360 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7361 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7366 #ifndef USE_JUMP_TABLES
7367 g_free (constant_pool_starts);
7370 mono_arch_flush_icache ((guint8*)start, size);
7371 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7372 mono_stats.imt_thunks_size += code - start;
7374 g_assert (DISTANCE (start, code) <= size);
7376 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7382 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7384 return ctx->regs [reg];
7388 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7390 ctx->regs [reg] = val;
7394 * mono_arch_get_trampolines:
7396 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7400 mono_arch_get_trampolines (gboolean aot)
7402 return mono_arm_get_exception_trampolines (aot);
7406 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7413 bp = MONO_CONTEXT_GET_BP (ctx);
7414 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7416 old_value = *lr_loc;
7417 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7420 *lr_loc = new_value;
7425 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7427 * mono_arch_set_breakpoint:
7429 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7430 * The location should contain code emitted by OP_SEQ_POINT.
7433 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7436 guint32 native_offset = ip - (guint8*)ji->code_start;
7437 MonoDebugOptions *opt = mini_get_debug_options ();
7439 if (opt->soft_breakpoints) {
7440 g_assert (!ji->from_aot);
7442 ARM_BLX_REG (code, ARMREG_LR);
7443 mono_arch_flush_icache (code - 4, 4);
7444 } else if (ji->from_aot) {
7445 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7447 g_assert (native_offset % 4 == 0);
7448 g_assert (info->bp_addrs [native_offset / 4] == 0);
7449 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7451 int dreg = ARMREG_LR;
7453 /* Read from another trigger page */
7454 #ifdef USE_JUMP_TABLES
7455 gpointer *jte = mono_jumptable_add_entry ();
7456 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7457 jte [0] = bp_trigger_page;
7459 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7461 *(int*)code = (int)bp_trigger_page;
7464 ARM_LDR_IMM (code, dreg, dreg, 0);
7466 mono_arch_flush_icache (code - 16, 16);
7469 /* This is currently implemented by emitting an SWI instruction, which
7470 * qemu/linux seems to convert to a SIGILL.
7472 *(int*)code = (0xef << 24) | 8;
7474 mono_arch_flush_icache (code - 4, 4);
7480 * mono_arch_clear_breakpoint:
7482 * Clear the breakpoint at IP.
7485 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7487 MonoDebugOptions *opt = mini_get_debug_options ();
7491 if (opt->soft_breakpoints) {
7492 g_assert (!ji->from_aot);
7495 mono_arch_flush_icache (code - 4, 4);
7496 } else if (ji->from_aot) {
7497 guint32 native_offset = ip - (guint8*)ji->code_start;
7498 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7500 g_assert (native_offset % 4 == 0);
7501 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7502 info->bp_addrs [native_offset / 4] = 0;
7504 for (i = 0; i < 4; ++i)
7507 mono_arch_flush_icache (ip, code - ip);
7512 * mono_arch_start_single_stepping:
7514 * Start single stepping.
7517 mono_arch_start_single_stepping (void)
7519 if (ss_trigger_page)
7520 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7526 * mono_arch_stop_single_stepping:
7528 * Stop single stepping.
7531 mono_arch_stop_single_stepping (void)
7533 if (ss_trigger_page)
7534 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7540 #define DBG_SIGNAL SIGBUS
7542 #define DBG_SIGNAL SIGSEGV
7546 * mono_arch_is_single_step_event:
7548 * Return whenever the machine state in SIGCTX corresponds to a single
7552 mono_arch_is_single_step_event (void *info, void *sigctx)
7554 siginfo_t *sinfo = info;
7556 if (!ss_trigger_page)
7559 /* Sometimes the address is off by 4 */
7560 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7567 * mono_arch_is_breakpoint_event:
7569 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7572 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7574 siginfo_t *sinfo = info;
7576 if (!ss_trigger_page)
7579 if (sinfo->si_signo == DBG_SIGNAL) {
7580 /* Sometimes the address is off by 4 */
7581 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7591 * mono_arch_skip_breakpoint:
7593 * See mini-amd64.c for docs.
7596 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7598 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7602 * mono_arch_skip_single_step:
7604 * See mini-amd64.c for docs.
7607 mono_arch_skip_single_step (MonoContext *ctx)
7609 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7612 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7615 * mono_arch_get_seq_point_info:
7617 * See mini-amd64.c for docs.
7620 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7625 // FIXME: Add a free function
7627 mono_domain_lock (domain);
7628 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7630 mono_domain_unlock (domain);
7633 ji = mono_jit_info_table_find (domain, (char*)code);
7636 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7638 info->ss_trigger_page = ss_trigger_page;
7639 info->bp_trigger_page = bp_trigger_page;
7641 mono_domain_lock (domain);
7642 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7644 mono_domain_unlock (domain);
7651 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7653 ext->lmf.previous_lmf = prev_lmf;
7654 /* Mark that this is a MonoLMFExt */
7655 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7656 ext->lmf.sp = (gssize)ext;
7660 * mono_arch_set_target:
7662 * Set the target architecture the JIT backend should generate code for, in the form
7663 * of a GNU target triplet. Only used in AOT mode.
7666 mono_arch_set_target (char *mtriple)
7668 /* The GNU target triple format is not very well documented */
7669 if (strstr (mtriple, "armv7")) {
7670 v5_supported = TRUE;
7671 v6_supported = TRUE;
7672 v7_supported = TRUE;
7674 if (strstr (mtriple, "armv6")) {
7675 v5_supported = TRUE;
7676 v6_supported = TRUE;
7678 if (strstr (mtriple, "armv7s")) {
7679 v7s_supported = TRUE;
7681 if (strstr (mtriple, "thumbv7s")) {
7682 v5_supported = TRUE;
7683 v6_supported = TRUE;
7684 v7_supported = TRUE;
7685 v7s_supported = TRUE;
7686 thumb_supported = TRUE;
7687 thumb2_supported = TRUE;
7689 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7690 v5_supported = TRUE;
7691 v6_supported = TRUE;
7692 thumb_supported = TRUE;
7695 if (strstr (mtriple, "gnueabi"))
7696 eabi_supported = TRUE;
7700 mono_arch_opcode_supported (int opcode)
7703 case OP_ATOMIC_ADD_I4:
7704 case OP_ATOMIC_EXCHANGE_I4:
7705 case OP_ATOMIC_CAS_I4:
7706 case OP_ATOMIC_LOAD_I1:
7707 case OP_ATOMIC_LOAD_I2:
7708 case OP_ATOMIC_LOAD_I4:
7709 case OP_ATOMIC_LOAD_U1:
7710 case OP_ATOMIC_LOAD_U2:
7711 case OP_ATOMIC_LOAD_U4:
7712 case OP_ATOMIC_STORE_I1:
7713 case OP_ATOMIC_STORE_I2:
7714 case OP_ATOMIC_STORE_I4:
7715 case OP_ATOMIC_STORE_U1:
7716 case OP_ATOMIC_STORE_U2:
7717 case OP_ATOMIC_STORE_U4:
7718 return v7_supported;
7719 case OP_ATOMIC_LOAD_R4:
7720 case OP_ATOMIC_LOAD_R8:
7721 case OP_ATOMIC_STORE_R4:
7722 case OP_ATOMIC_STORE_R8:
7723 return v7_supported && IS_VFP;
7729 #if defined(ENABLE_GSHAREDVT)
7731 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7733 #endif /* !MONOTOUCH */