2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
27 #include "debugger-agent.h"
29 #include "mono/arch/arm/arm-vfp-codegen.h"
31 /* Sanity check: This makes no sense */
32 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
33 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
37 * IS_SOFT_FLOAT: Is full software floating point used?
38 * IS_HARD_FLOAT: Is full hardware floating point used?
39 * IS_VFP: Is hardware floating point with software ABI used?
41 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
42 * IS_VFP may delegate to mono_arch_is_soft_float ().
45 #if defined(ARM_FPU_VFP_HARD)
46 #define IS_SOFT_FLOAT (FALSE)
47 #define IS_HARD_FLOAT (TRUE)
49 #elif defined(ARM_FPU_NONE)
50 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
51 #define IS_HARD_FLOAT (FALSE)
52 #define IS_VFP (!mono_arch_is_soft_float ())
54 #define IS_SOFT_FLOAT (FALSE)
55 #define IS_HARD_FLOAT (FALSE)
59 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(__native_client__)
60 #define HAVE_AEABI_READ_TP 1
63 #ifdef __native_client_codegen__
64 const guint kNaClAlignment = kNaClAlignmentARM;
65 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
66 gint8 nacl_align_byte = -1; /* 0xff */
69 mono_arch_nacl_pad (guint8 *code, int pad)
71 /* Not yet properly implemented. */
72 g_assert_not_reached ();
77 mono_arch_nacl_skip_nops (guint8 *code)
79 /* Not yet properly implemented. */
80 g_assert_not_reached ();
84 #endif /* __native_client_codegen__ */
86 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
89 void sys_icache_invalidate (void *start, size_t len);
92 /* This mutex protects architecture specific caches */
93 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
94 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
95 static mono_mutex_t mini_arch_mutex;
97 static gboolean v5_supported = FALSE;
98 static gboolean v6_supported = FALSE;
99 static gboolean v7_supported = FALSE;
100 static gboolean v7s_supported = FALSE;
101 static gboolean thumb_supported = FALSE;
102 static gboolean thumb2_supported = FALSE;
104 * Whenever to use the ARM EABI
106 static gboolean eabi_supported = FALSE;
109 * Whenever to use the iphone ABI extensions:
110 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
111 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
112 * This is required for debugging/profiling tools to work, but it has some overhead so it should
113 * only be turned on in debug builds.
115 static gboolean iphone_abi = FALSE;
118 * The FPU we are generating code for. This is NOT runtime configurable right now,
119 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
121 static MonoArmFPU arm_fpu;
123 #if defined(ARM_FPU_VFP_HARD)
125 * On armhf, d0-d7 are used for argument passing and d8-d15
126 * must be preserved across calls, which leaves us no room
127 * for scratch registers. So we use d14-d15 but back up their
128 * previous contents to a stack slot before using them - see
129 * mono_arm_emit_vfp_scratch_save/_restore ().
131 static int vfp_scratch1 = ARM_VFP_D14;
132 static int vfp_scratch2 = ARM_VFP_D15;
135 * On armel, d0-d7 do not need to be preserved, so we can
136 * freely make use of them as scratch registers.
138 static int vfp_scratch1 = ARM_VFP_D0;
139 static int vfp_scratch2 = ARM_VFP_D1;
144 static volatile int ss_trigger_var = 0;
146 static gpointer single_step_func_wrapper;
147 static gpointer breakpoint_func_wrapper;
150 * The code generated for sequence points reads from this location, which is
151 * made read-only when single stepping is enabled.
153 static gpointer ss_trigger_page;
155 /* Enabled breakpoints read from this trigger page */
156 static gpointer bp_trigger_page;
160 * floating point support: on ARM it is a mess, there are at least 3
161 * different setups, each of which binary incompat with the other.
162 * 1) FPA: old and ugly, but unfortunately what current distros use
163 * the double binary format has the two words swapped. 8 double registers.
164 * Implemented usually by kernel emulation.
165 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
166 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
167 * 3) VFP: the new and actually sensible and useful FP support. Implemented
168 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
170 * We do not care about FPA. We will support soft float and VFP.
172 int mono_exc_esp_offset = 0;
174 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
175 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
176 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
178 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
179 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
180 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
182 //#define DEBUG_IMT 0
185 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
189 mono_arch_regname (int reg)
191 static const char * rnames[] = {
192 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
193 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
194 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
197 if (reg >= 0 && reg < 16)
203 mono_arch_fregname (int reg)
205 static const char * rnames[] = {
206 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
207 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
208 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
209 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
210 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
211 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
214 if (reg >= 0 && reg < 32)
222 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
224 int imm8, rot_amount;
225 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
226 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
230 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
231 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
233 code = mono_arm_emit_load_imm (code, dreg, imm);
234 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
239 /* If dreg == sreg, this clobbers IP */
241 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
243 int imm8, rot_amount;
244 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
245 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
249 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
250 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
252 code = mono_arm_emit_load_imm (code, dreg, imm);
253 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
259 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
261 /* we can use r0-r3, since this is called only for incoming args on the stack */
262 if (size > sizeof (gpointer) * 4) {
264 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
265 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
266 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
267 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
268 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
269 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
270 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
271 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
272 ARM_B_COND (code, ARMCOND_NE, 0);
273 arm_patch (code - 4, start_loop);
276 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
277 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
279 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
280 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
286 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
287 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
288 doffset = soffset = 0;
290 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
291 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
297 g_assert (size == 0);
302 emit_call_reg (guint8 *code, int reg)
305 ARM_BLX_REG (code, reg);
307 #ifdef USE_JUMP_TABLES
308 g_assert_not_reached ();
310 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
314 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
320 emit_call_seq (MonoCompile *cfg, guint8 *code)
322 #ifdef USE_JUMP_TABLES
323 code = mono_arm_patchable_bl (code, ARMCOND_AL);
325 if (cfg->method->dynamic) {
326 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
328 *(gpointer*)code = NULL;
330 code = emit_call_reg (code, ARMREG_IP);
339 mono_arm_patchable_b (guint8 *code, int cond)
341 #ifdef USE_JUMP_TABLES
344 jte = mono_jumptable_add_entry ();
345 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
346 ARM_BX_COND (code, cond, ARMREG_IP);
348 ARM_B_COND (code, cond, 0);
354 mono_arm_patchable_bl (guint8 *code, int cond)
356 #ifdef USE_JUMP_TABLES
359 jte = mono_jumptable_add_entry ();
360 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
361 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
363 ARM_BL_COND (code, cond, 0);
368 #ifdef USE_JUMP_TABLES
370 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
372 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
373 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
378 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
380 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
381 ARM_LDR_IMM (code, reg, reg, 0);
387 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
389 switch (ins->opcode) {
392 case OP_FCALL_MEMBASE:
394 MonoType *sig_ret = mini_type_get_underlying_type (NULL, ((MonoCallInst*)ins)->signature->ret);
395 if (sig_ret->type == MONO_TYPE_R4) {
397 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
399 ARM_FMSR (code, ins->dreg, ARMREG_R0);
400 ARM_CVTS (code, ins->dreg, ins->dreg);
404 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
406 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
413 case OP_RCALL_MEMBASE: {
418 sig_ret = mini_type_get_underlying_type (NULL, ((MonoCallInst*)ins)->signature->ret);
419 g_assert (sig_ret->type == MONO_TYPE_R4);
421 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
423 ARM_FMSR (code, ins->dreg, ARMREG_R0);
424 ARM_CPYS (code, ins->dreg, ins->dreg);
438 * Emit code to push an LMF structure on the LMF stack.
439 * On arm, this is intermixed with the initialization of other fields of the structure.
442 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
444 gboolean get_lmf_fast = FALSE;
447 #ifdef HAVE_AEABI_READ_TP
448 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
450 if (lmf_addr_tls_offset != -1) {
453 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
454 (gpointer)"__aeabi_read_tp");
455 code = emit_call_seq (cfg, code);
457 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
463 if (cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) {
466 /* Inline mono_get_lmf_addr () */
467 /* jit_tls = pthread_getspecific (mono_jit_tls_id); lmf_addr = &jit_tls->lmf; */
469 /* Load mono_jit_tls_id */
471 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_TLS_ID, NULL);
472 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
474 *(gpointer*)code = NULL;
476 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
477 /* call pthread_getspecific () */
478 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
479 (gpointer)"pthread_getspecific");
480 code = emit_call_seq (cfg, code);
481 /* lmf_addr = &jit_tls->lmf */
482 lmf_offset = MONO_STRUCT_OFFSET (MonoJitTlsData, lmf);
483 g_assert (arm_is_imm8 (lmf_offset));
484 ARM_ADD_REG_IMM (code, ARMREG_R0, ARMREG_R0, lmf_offset, 0);
491 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
492 (gpointer)"mono_get_lmf_addr");
493 code = emit_call_seq (cfg, code);
495 /* we build the MonoLMF structure on the stack - see mini-arm.h */
496 /* lmf_offset is the offset from the previous stack pointer,
497 * alloc_size is the total stack space allocated, so the offset
498 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
499 * The pointer to the struct is put in r1 (new_lmf).
500 * ip is used as scratch
501 * The callee-saved registers are already in the MonoLMF structure
503 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
504 /* r0 is the result from mono_get_lmf_addr () */
505 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
506 /* new_lmf->previous_lmf = *lmf_addr */
507 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
508 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
509 /* *(lmf_addr) = r1 */
510 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
511 /* Skip method (only needed for trampoline LMF frames) */
512 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
513 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
514 /* save the current IP */
515 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
516 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
518 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
519 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
530 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
534 g_assert (!cfg->r4fp);
536 for (list = inst->float_args; list; list = list->next) {
537 FloatArgData *fad = list->data;
538 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
539 gboolean imm = arm_is_fpimm8 (var->inst_offset);
541 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
547 if (*offset + *max_len > cfg->code_size) {
548 cfg->code_size += *max_len;
549 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
551 code = cfg->native_code + *offset;
555 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
556 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
558 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
560 *offset = code - cfg->native_code;
567 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
571 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
573 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
576 if (!arm_is_fpimm8 (inst->inst_offset)) {
577 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
578 ARM_FSTD (code, reg, ARMREG_LR, 0);
580 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
587 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
591 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
593 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
596 if (!arm_is_fpimm8 (inst->inst_offset)) {
597 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
598 ARM_FLDD (code, reg, ARMREG_LR, 0);
600 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
609 * Emit code to pop an LMF structure from the LMF stack.
612 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
616 if (lmf_offset < 32) {
617 basereg = cfg->frame_reg;
622 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
625 /* ip = previous_lmf */
626 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
628 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
629 /* *(lmf_addr) = previous_lmf */
630 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
635 #endif /* #ifndef DISABLE_JIT */
638 * mono_arch_get_argument_info:
639 * @csig: a method signature
640 * @param_count: the number of parameters to consider
641 * @arg_info: an array to store the result infos
643 * Gathers information on parameters such as size, alignment and
644 * padding. arg_info should be large enought to hold param_count + 1 entries.
646 * Returns the size of the activation frame.
649 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
651 int k, frame_size = 0;
652 guint32 size, align, pad;
656 t = mini_type_get_underlying_type (gsctx, csig->ret);
657 if (MONO_TYPE_ISSTRUCT (t)) {
658 frame_size += sizeof (gpointer);
662 arg_info [0].offset = offset;
665 frame_size += sizeof (gpointer);
669 arg_info [0].size = frame_size;
671 for (k = 0; k < param_count; k++) {
672 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
674 /* ignore alignment for now */
677 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
678 arg_info [k].pad = pad;
680 arg_info [k + 1].pad = 0;
681 arg_info [k + 1].size = size;
683 arg_info [k + 1].offset = offset;
687 align = MONO_ARCH_FRAME_ALIGNMENT;
688 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
689 arg_info [k].pad = pad;
694 #define MAX_ARCH_DELEGATE_PARAMS 3
697 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
699 guint8 *code, *start;
702 start = code = mono_global_codeman_reserve (12);
704 /* Replace the this argument with the target */
705 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
706 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
707 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
709 g_assert ((code - start) <= 12);
711 mono_arch_flush_icache (start, 12);
715 size = 8 + param_count * 4;
716 start = code = mono_global_codeman_reserve (size);
718 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
719 /* slide down the arguments */
720 for (i = 0; i < param_count; ++i) {
721 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
723 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
725 g_assert ((code - start) <= size);
727 mono_arch_flush_icache (start, size);
730 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
732 *code_size = code - start;
738 * mono_arch_get_delegate_invoke_impls:
740 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
744 mono_arch_get_delegate_invoke_impls (void)
752 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
753 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
755 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
756 code = get_delegate_invoke_impl (FALSE, i, &code_len);
757 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
758 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
766 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
768 guint8 *code, *start;
771 /* FIXME: Support more cases */
772 sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
773 if (MONO_TYPE_ISSTRUCT (sig_ret))
777 static guint8* cached = NULL;
778 mono_mini_arch_lock ();
780 mono_mini_arch_unlock ();
785 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
787 start = get_delegate_invoke_impl (TRUE, 0, NULL);
789 mono_mini_arch_unlock ();
792 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
795 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
797 for (i = 0; i < sig->param_count; ++i)
798 if (!mono_is_regsize_var (sig->params [i]))
801 mono_mini_arch_lock ();
802 code = cache [sig->param_count];
804 mono_mini_arch_unlock ();
809 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
810 start = mono_aot_get_trampoline (name);
813 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
815 cache [sig->param_count] = start;
816 mono_mini_arch_unlock ();
824 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
830 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
832 return (gpointer)regs [ARMREG_R0];
836 * Initialize the cpu to execute managed code.
839 mono_arch_cpu_init (void)
841 i8_align = MONO_ABI_ALIGNOF (gint64);
842 #ifdef MONO_CROSS_COMPILE
843 /* Need to set the alignment of i8 since it can different on the target */
844 #ifdef TARGET_ANDROID
846 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
852 create_function_wrapper (gpointer function)
854 guint8 *start, *code;
856 start = code = mono_global_codeman_reserve (96);
859 * Construct the MonoContext structure on the stack.
862 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, sizeof (MonoContext));
864 /* save ip, lr and pc into their correspodings ctx.regs slots. */
865 ARM_STR_IMM (code, ARMREG_IP, ARMREG_SP, MONO_STRUCT_OFFSET (MonoContext, regs) + sizeof (mgreg_t) * ARMREG_IP);
866 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, MONO_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
867 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, MONO_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
869 /* save r0..r10 and fp */
870 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_SP, MONO_STRUCT_OFFSET (MonoContext, regs));
871 ARM_STM (code, ARMREG_IP, 0x0fff);
873 /* now we can update fp. */
874 ARM_MOV_REG_REG (code, ARMREG_FP, ARMREG_SP);
876 /* make ctx.esp hold the actual value of sp at the beginning of this method. */
877 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_FP, sizeof (MonoContext));
878 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, 4 * ARMREG_SP);
879 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, MONO_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_SP);
881 /* make ctx.eip hold the address of the call. */
882 ARM_SUB_REG_IMM8 (code, ARMREG_LR, ARMREG_LR, 4);
883 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, MONO_STRUCT_OFFSET (MonoContext, pc));
885 /* r0 now points to the MonoContext */
886 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_FP);
889 #ifdef USE_JUMP_TABLES
891 gpointer *jte = mono_jumptable_add_entry ();
892 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
896 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
898 *(gpointer*)code = function;
901 ARM_BLX_REG (code, ARMREG_IP);
903 /* we're back; save ctx.eip and ctx.esp into the corresponding regs slots. */
904 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, MONO_STRUCT_OFFSET (MonoContext, pc));
905 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, MONO_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
906 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, MONO_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
908 /* make ip point to the regs array, then restore everything, including pc. */
909 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_FP, MONO_STRUCT_OFFSET (MonoContext, regs));
910 ARM_LDM (code, ARMREG_IP, 0xffff);
912 mono_arch_flush_icache (start, code - start);
913 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_HELPER, NULL);
919 * Initialize architecture specific code.
922 mono_arch_init (void)
924 const char *cpu_arch;
926 mono_mutex_init_recursive (&mini_arch_mutex);
927 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
928 if (mini_get_debug_options ()->soft_breakpoints) {
929 single_step_func_wrapper = create_function_wrapper (debugger_agent_single_step_from_context);
930 breakpoint_func_wrapper = create_function_wrapper (debugger_agent_breakpoint_from_context);
935 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
936 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
937 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
940 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
941 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
942 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
943 #if defined(ENABLE_GSHAREDVT)
944 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
947 #if defined(__ARM_EABI__)
948 eabi_supported = TRUE;
951 #if defined(ARM_FPU_VFP_HARD)
952 arm_fpu = MONO_ARM_FPU_VFP_HARD;
954 arm_fpu = MONO_ARM_FPU_VFP;
956 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
958 * If we're compiling with a soft float fallback and it
959 * turns out that no VFP unit is available, we need to
960 * switch to soft float. We don't do this for iOS, since
961 * iOS devices always have a VFP unit.
963 if (!mono_hwcap_arm_has_vfp)
964 arm_fpu = MONO_ARM_FPU_NONE;
967 * This environment variable can be useful in testing
968 * environments to make sure the soft float fallback
969 * works. Most ARM devices have VFP units these days, so
970 * normally soft float code would not be exercised much.
972 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
974 if (soft && !strncmp (soft, "1", 1))
975 arm_fpu = MONO_ARM_FPU_NONE;
979 v5_supported = mono_hwcap_arm_is_v5;
980 v6_supported = mono_hwcap_arm_is_v6;
981 v7_supported = mono_hwcap_arm_is_v7;
982 v7s_supported = mono_hwcap_arm_is_v7s;
984 #if defined(__APPLE__)
985 /* iOS is special-cased here because we don't yet
986 have a way to properly detect CPU features on it. */
987 thumb_supported = TRUE;
990 thumb_supported = mono_hwcap_arm_has_thumb;
991 thumb2_supported = mono_hwcap_arm_has_thumb2;
994 /* Format: armv(5|6|7[s])[-thumb[2]] */
995 cpu_arch = g_getenv ("MONO_CPU_ARCH");
997 /* Do this here so it overrides any detection. */
999 if (strncmp (cpu_arch, "armv", 4) == 0) {
1000 v5_supported = cpu_arch [4] >= '5';
1001 v6_supported = cpu_arch [4] >= '6';
1002 v7_supported = cpu_arch [4] >= '7';
1003 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
1006 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
1007 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
1012 * Cleanup architecture specific code.
1015 mono_arch_cleanup (void)
1020 * This function returns the optimizations supported on this cpu.
1023 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1025 /* no arm-specific optimizations yet */
1031 * This function test for all SIMD functions supported.
1033 * Returns a bitmask corresponding to all supported versions.
1037 mono_arch_cpu_enumerate_simd_versions (void)
1039 /* SIMD is currently unimplemented */
1047 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1049 if (v7s_supported) {
1063 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1065 mono_arch_is_soft_float (void)
1067 return arm_fpu == MONO_ARM_FPU_NONE;
1072 mono_arm_is_hard_float (void)
1074 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1078 is_regsize_var (MonoGenericSharingContext *gsctx, MonoType *t) {
1081 t = mini_type_get_underlying_type (gsctx, t);
1088 case MONO_TYPE_FNPTR:
1090 case MONO_TYPE_OBJECT:
1091 case MONO_TYPE_STRING:
1092 case MONO_TYPE_CLASS:
1093 case MONO_TYPE_SZARRAY:
1094 case MONO_TYPE_ARRAY:
1096 case MONO_TYPE_GENERICINST:
1097 if (!mono_type_generic_inst_is_valuetype (t))
1100 case MONO_TYPE_VALUETYPE:
1107 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1112 for (i = 0; i < cfg->num_varinfo; i++) {
1113 MonoInst *ins = cfg->varinfo [i];
1114 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1117 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1120 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1123 /* we can only allocate 32 bit values */
1124 if (is_regsize_var (cfg->generic_sharing_context, ins->inst_vtype)) {
1125 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1126 g_assert (i == vmv->idx);
1127 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1135 mono_arch_get_global_int_regs (MonoCompile *cfg)
1139 mono_arch_compute_omit_fp (cfg);
1142 * FIXME: Interface calls might go through a static rgctx trampoline which
1143 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1146 if (cfg->flags & MONO_CFG_HAS_CALLS)
1147 cfg->uses_rgctx_reg = TRUE;
1149 if (cfg->arch.omit_fp)
1150 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1151 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1152 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1153 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1155 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1156 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1158 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1159 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1160 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1161 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1162 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1163 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1169 * mono_arch_regalloc_cost:
1171 * Return the cost, in number of memory references, of the action of
1172 * allocating the variable VMV into a register during global register
1176 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1182 #endif /* #ifndef DISABLE_JIT */
1184 #ifndef __GNUC_PREREQ
1185 #define __GNUC_PREREQ(maj, min) (0)
1189 mono_arch_flush_icache (guint8 *code, gint size)
1191 #if defined(__native_client__)
1192 // For Native Client we don't have to flush i-cache here,
1193 // as it's being done by dyncode interface.
1196 #ifdef MONO_CROSS_COMPILE
1198 sys_icache_invalidate (code, size);
1199 #elif __GNUC_PREREQ(4, 3)
1200 __builtin___clear_cache (code, code + size);
1201 #elif __GNUC_PREREQ(4, 1)
1202 __clear_cache (code, code + size);
1203 #elif defined(PLATFORM_ANDROID)
1204 const int syscall = 0xf0002;
1212 : "r" (code), "r" (code + size), "r" (syscall)
1213 : "r0", "r1", "r7", "r2"
1216 __asm __volatile ("mov r0, %0\n"
1219 "swi 0x9f0002 @ sys_cacheflush"
1221 : "r" (code), "r" (code + size), "r" (0)
1222 : "r0", "r1", "r3" );
1224 #endif /* !__native_client__ */
1235 RegTypeStructByAddr,
1236 /* gsharedvt argument passed by addr in greg */
1237 RegTypeGSharedVtInReg,
1238 /* gsharedvt argument passed by addr on stack */
1239 RegTypeGSharedVtOnStack,
1244 guint16 vtsize; /* in param area */
1248 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1253 guint32 stack_usage;
1254 gboolean vtype_retaddr;
1255 /* The index of the vret arg in the argument list */
1265 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1268 if (*gr > ARMREG_R3) {
1270 ainfo->offset = *stack_size;
1271 ainfo->reg = ARMREG_SP; /* in the caller */
1272 ainfo->storage = RegTypeBase;
1275 ainfo->storage = RegTypeGeneral;
1282 split = i8_align == 4;
1287 if (*gr == ARMREG_R3 && split) {
1288 /* first word in r3 and the second on the stack */
1289 ainfo->offset = *stack_size;
1290 ainfo->reg = ARMREG_SP; /* in the caller */
1291 ainfo->storage = RegTypeBaseGen;
1293 } else if (*gr >= ARMREG_R3) {
1294 if (eabi_supported) {
1295 /* darwin aligns longs to 4 byte only */
1296 if (i8_align == 8) {
1301 ainfo->offset = *stack_size;
1302 ainfo->reg = ARMREG_SP; /* in the caller */
1303 ainfo->storage = RegTypeBase;
1306 if (eabi_supported) {
1307 if (i8_align == 8 && ((*gr) & 1))
1310 ainfo->storage = RegTypeIRegPair;
1319 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1322 * If we're calling a function like this:
1324 * void foo(float a, double b, float c)
1326 * We pass a in s0 and b in d1. That leaves us
1327 * with s1 being unused. The armhf ABI recognizes
1328 * this and requires register assignment to then
1329 * use that for the next single-precision arg,
1330 * i.e. c in this example. So float_spare either
1331 * tells us which reg to use for the next single-
1332 * precision arg, or it's -1, meaning use *fpr.
1334 * Note that even though most of the JIT speaks
1335 * double-precision, fpr represents single-
1336 * precision registers.
1338 * See parts 5.5 and 6.1.2 of the AAPCS for how
1342 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1343 ainfo->storage = RegTypeFP;
1347 * If we're passing a double-precision value
1348 * and *fpr is odd (e.g. it's s1, s3, ...)
1349 * we need to use the next even register. So
1350 * we mark the current *fpr as a spare that
1351 * can be used for the next single-precision
1355 *float_spare = *fpr;
1360 * At this point, we have an even register
1361 * so we assign that and move along.
1365 } else if (*float_spare >= 0) {
1367 * We're passing a single-precision value
1368 * and it looks like a spare single-
1369 * precision register is available. Let's
1373 ainfo->reg = *float_spare;
1377 * If we hit this branch, we're passing a
1378 * single-precision value and we can simply
1379 * use the next available register.
1387 * We've exhausted available floating point
1388 * regs, so pass the rest on the stack.
1396 ainfo->offset = *stack_size;
1397 ainfo->reg = ARMREG_SP;
1398 ainfo->storage = RegTypeBase;
1405 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
1407 guint i, gr, fpr, pstart;
1409 int n = sig->hasthis + sig->param_count;
1410 MonoType *simpletype;
1411 guint32 stack_size = 0;
1413 gboolean is_pinvoke = sig->pinvoke;
1417 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1419 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1426 t = mini_type_get_underlying_type (gsctx, sig->ret);
1427 if (MONO_TYPE_ISSTRUCT (t)) {
1430 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer)) {
1431 cinfo->ret.storage = RegTypeStructByVal;
1433 cinfo->vtype_retaddr = TRUE;
1435 } else if (!(t->type == MONO_TYPE_GENERICINST && !mono_type_generic_inst_is_valuetype (t)) && mini_is_gsharedvt_type_gsctx (gsctx, t)) {
1436 cinfo->vtype_retaddr = TRUE;
1442 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1443 * the first argument, allowing 'this' to be always passed in the first arg reg.
1444 * Also do this if the first argument is a reference type, since virtual calls
1445 * are sometimes made using calli without sig->hasthis set, like in the delegate
1448 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1450 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1452 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1456 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1457 cinfo->vret_arg_index = 1;
1461 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1465 if (cinfo->vtype_retaddr)
1466 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1469 DEBUG(printf("params: %d\n", sig->param_count));
1470 for (i = pstart; i < sig->param_count; ++i) {
1471 ArgInfo *ainfo = &cinfo->args [n];
1473 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1474 /* Prevent implicit arguments and sig_cookie from
1475 being passed in registers */
1478 /* Emit the signature cookie just before the implicit arguments */
1479 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1481 DEBUG(printf("param %d: ", i));
1482 if (sig->params [i]->byref) {
1483 DEBUG(printf("byref\n"));
1484 add_general (&gr, &stack_size, ainfo, TRUE);
1488 simpletype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1489 switch (simpletype->type) {
1492 cinfo->args [n].size = 1;
1493 add_general (&gr, &stack_size, ainfo, TRUE);
1498 cinfo->args [n].size = 2;
1499 add_general (&gr, &stack_size, ainfo, TRUE);
1504 cinfo->args [n].size = 4;
1505 add_general (&gr, &stack_size, ainfo, TRUE);
1511 case MONO_TYPE_FNPTR:
1512 case MONO_TYPE_CLASS:
1513 case MONO_TYPE_OBJECT:
1514 case MONO_TYPE_STRING:
1515 case MONO_TYPE_SZARRAY:
1516 case MONO_TYPE_ARRAY:
1517 cinfo->args [n].size = sizeof (gpointer);
1518 add_general (&gr, &stack_size, ainfo, TRUE);
1521 case MONO_TYPE_GENERICINST:
1522 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1523 cinfo->args [n].size = sizeof (gpointer);
1524 add_general (&gr, &stack_size, ainfo, TRUE);
1528 if (mini_is_gsharedvt_type_gsctx (gsctx, simpletype)) {
1529 /* gsharedvt arguments are passed by ref */
1530 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, simpletype));
1531 add_general (&gr, &stack_size, ainfo, TRUE);
1532 switch (ainfo->storage) {
1533 case RegTypeGeneral:
1534 ainfo->storage = RegTypeGSharedVtInReg;
1537 ainfo->storage = RegTypeGSharedVtOnStack;
1540 g_assert_not_reached ();
1546 case MONO_TYPE_TYPEDBYREF:
1547 case MONO_TYPE_VALUETYPE: {
1553 if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1554 size = sizeof (MonoTypedRef);
1555 align = sizeof (gpointer);
1557 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1559 size = mono_class_native_size (klass, &align);
1561 size = mini_type_stack_size_full (gsctx, simpletype, &align, FALSE);
1563 DEBUG(printf ("load %d bytes struct\n", size));
1566 align_size += (sizeof (gpointer) - 1);
1567 align_size &= ~(sizeof (gpointer) - 1);
1568 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1569 ainfo->storage = RegTypeStructByVal;
1570 ainfo->struct_size = size;
1571 /* FIXME: align stack_size if needed */
1572 if (eabi_supported) {
1573 if (align >= 8 && (gr & 1))
1576 if (gr > ARMREG_R3) {
1578 ainfo->vtsize = nwords;
1580 int rest = ARMREG_R3 - gr + 1;
1581 int n_in_regs = rest >= nwords? nwords: rest;
1583 ainfo->size = n_in_regs;
1584 ainfo->vtsize = nwords - n_in_regs;
1587 nwords -= n_in_regs;
1589 if (sig->call_convention == MONO_CALL_VARARG)
1590 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1591 stack_size = ALIGN_TO (stack_size, align);
1592 ainfo->offset = stack_size;
1593 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1594 stack_size += nwords * sizeof (gpointer);
1601 add_general (&gr, &stack_size, ainfo, FALSE);
1608 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1610 add_general (&gr, &stack_size, ainfo, TRUE);
1618 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1620 add_general (&gr, &stack_size, ainfo, FALSE);
1625 case MONO_TYPE_MVAR:
1626 /* gsharedvt arguments are passed by ref */
1627 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, simpletype));
1628 add_general (&gr, &stack_size, ainfo, TRUE);
1629 switch (ainfo->storage) {
1630 case RegTypeGeneral:
1631 ainfo->storage = RegTypeGSharedVtInReg;
1634 ainfo->storage = RegTypeGSharedVtOnStack;
1637 g_assert_not_reached ();
1642 g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1646 /* Handle the case where there are no implicit arguments */
1647 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1648 /* Prevent implicit arguments and sig_cookie from
1649 being passed in registers */
1652 /* Emit the signature cookie just before the implicit arguments */
1653 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1657 simpletype = mini_type_get_underlying_type (gsctx, sig->ret);
1658 switch (simpletype->type) {
1668 case MONO_TYPE_FNPTR:
1669 case MONO_TYPE_CLASS:
1670 case MONO_TYPE_OBJECT:
1671 case MONO_TYPE_SZARRAY:
1672 case MONO_TYPE_ARRAY:
1673 case MONO_TYPE_STRING:
1674 cinfo->ret.storage = RegTypeGeneral;
1675 cinfo->ret.reg = ARMREG_R0;
1679 cinfo->ret.storage = RegTypeIRegPair;
1680 cinfo->ret.reg = ARMREG_R0;
1684 cinfo->ret.storage = RegTypeFP;
1686 if (IS_HARD_FLOAT) {
1687 cinfo->ret.reg = ARM_VFP_F0;
1689 cinfo->ret.reg = ARMREG_R0;
1693 case MONO_TYPE_GENERICINST:
1694 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1695 cinfo->ret.storage = RegTypeGeneral;
1696 cinfo->ret.reg = ARMREG_R0;
1699 // FIXME: Only for variable types
1700 if (mini_is_gsharedvt_type_gsctx (gsctx, simpletype)) {
1701 cinfo->ret.storage = RegTypeStructByAddr;
1702 g_assert (cinfo->vtype_retaddr);
1706 case MONO_TYPE_VALUETYPE:
1707 case MONO_TYPE_TYPEDBYREF:
1708 if (cinfo->ret.storage != RegTypeStructByVal)
1709 cinfo->ret.storage = RegTypeStructByAddr;
1712 case MONO_TYPE_MVAR:
1713 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, simpletype));
1714 cinfo->ret.storage = RegTypeStructByAddr;
1715 g_assert (cinfo->vtype_retaddr);
1717 case MONO_TYPE_VOID:
1720 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1724 /* align stack size to 8 */
1725 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1726 stack_size = (stack_size + 7) & ~7;
1728 cinfo->stack_usage = stack_size;
1734 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1736 MonoType *callee_ret;
1740 if (cfg->compile_aot && !cfg->full_aot)
1741 /* OP_TAILCALL doesn't work with AOT */
1744 c1 = get_call_info (NULL, NULL, caller_sig);
1745 c2 = get_call_info (NULL, NULL, callee_sig);
1748 * Tail calls with more callee stack usage than the caller cannot be supported, since
1749 * the extra stack space would be left on the stack after the tail call.
1751 res = c1->stack_usage >= c2->stack_usage;
1752 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1753 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1754 /* An address on the callee's stack is passed as the first argument */
1757 if (c2->stack_usage > 16 * 4)
1769 debug_omit_fp (void)
1772 return mono_debug_count ();
1779 * mono_arch_compute_omit_fp:
1781 * Determine whenever the frame pointer can be eliminated.
1784 mono_arch_compute_omit_fp (MonoCompile *cfg)
1786 MonoMethodSignature *sig;
1787 MonoMethodHeader *header;
1791 if (cfg->arch.omit_fp_computed)
1794 header = cfg->header;
1796 sig = mono_method_signature (cfg->method);
1798 if (!cfg->arch.cinfo)
1799 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1800 cinfo = cfg->arch.cinfo;
1803 * FIXME: Remove some of the restrictions.
1805 cfg->arch.omit_fp = TRUE;
1806 cfg->arch.omit_fp_computed = TRUE;
1808 if (cfg->disable_omit_fp)
1809 cfg->arch.omit_fp = FALSE;
1810 if (!debug_omit_fp ())
1811 cfg->arch.omit_fp = FALSE;
1813 if (cfg->method->save_lmf)
1814 cfg->arch.omit_fp = FALSE;
1816 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1817 cfg->arch.omit_fp = FALSE;
1818 if (header->num_clauses)
1819 cfg->arch.omit_fp = FALSE;
1820 if (cfg->param_area)
1821 cfg->arch.omit_fp = FALSE;
1822 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1823 cfg->arch.omit_fp = FALSE;
1824 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1825 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1826 cfg->arch.omit_fp = FALSE;
1827 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1828 ArgInfo *ainfo = &cinfo->args [i];
1830 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1832 * The stack offset can only be determined when the frame
1835 cfg->arch.omit_fp = FALSE;
1840 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1841 MonoInst *ins = cfg->varinfo [i];
1844 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1849 * Set var information according to the calling convention. arm version.
1850 * The locals var stuff should most likely be split in another method.
1853 mono_arch_allocate_vars (MonoCompile *cfg)
1855 MonoMethodSignature *sig;
1856 MonoMethodHeader *header;
1859 int i, offset, size, align, curinst;
1863 sig = mono_method_signature (cfg->method);
1865 if (!cfg->arch.cinfo)
1866 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1867 cinfo = cfg->arch.cinfo;
1868 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1870 mono_arch_compute_omit_fp (cfg);
1872 if (cfg->arch.omit_fp)
1873 cfg->frame_reg = ARMREG_SP;
1875 cfg->frame_reg = ARMREG_FP;
1877 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1879 /* allow room for the vararg method args: void* and long/double */
1880 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1881 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1883 header = cfg->header;
1885 /* See mono_arch_get_global_int_regs () */
1886 if (cfg->flags & MONO_CFG_HAS_CALLS)
1887 cfg->uses_rgctx_reg = TRUE;
1889 if (cfg->frame_reg != ARMREG_SP)
1890 cfg->used_int_regs |= 1 << cfg->frame_reg;
1892 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1893 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1894 cfg->used_int_regs |= (1 << ARMREG_V5);
1898 if (!MONO_TYPE_ISSTRUCT (sig_ret) && !cinfo->vtype_retaddr) {
1899 if (sig_ret->type != MONO_TYPE_VOID) {
1900 cfg->ret->opcode = OP_REGVAR;
1901 cfg->ret->inst_c0 = ARMREG_R0;
1904 /* local vars are at a positive offset from the stack pointer */
1906 * also note that if the function uses alloca, we use FP
1907 * to point at the local variables.
1909 offset = 0; /* linkage area */
1910 /* align the offset to 16 bytes: not sure this is needed here */
1912 //offset &= ~(8 - 1);
1914 /* add parameter area size for called functions */
1915 offset += cfg->param_area;
1918 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1921 /* allow room to save the return value */
1922 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1925 /* the MonoLMF structure is stored just below the stack pointer */
1926 if (cinfo->ret.storage == RegTypeStructByVal) {
1927 cfg->ret->opcode = OP_REGOFFSET;
1928 cfg->ret->inst_basereg = cfg->frame_reg;
1929 offset += sizeof (gpointer) - 1;
1930 offset &= ~(sizeof (gpointer) - 1);
1931 cfg->ret->inst_offset = - offset;
1932 offset += sizeof(gpointer);
1933 } else if (cinfo->vtype_retaddr) {
1934 ins = cfg->vret_addr;
1935 offset += sizeof(gpointer) - 1;
1936 offset &= ~(sizeof(gpointer) - 1);
1937 ins->inst_offset = offset;
1938 ins->opcode = OP_REGOFFSET;
1939 ins->inst_basereg = cfg->frame_reg;
1940 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1941 printf ("vret_addr =");
1942 mono_print_ins (cfg->vret_addr);
1944 offset += sizeof(gpointer);
1947 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1948 if (cfg->arch.seq_point_info_var) {
1951 ins = cfg->arch.seq_point_info_var;
1955 offset += align - 1;
1956 offset &= ~(align - 1);
1957 ins->opcode = OP_REGOFFSET;
1958 ins->inst_basereg = cfg->frame_reg;
1959 ins->inst_offset = offset;
1962 ins = cfg->arch.ss_trigger_page_var;
1965 offset += align - 1;
1966 offset &= ~(align - 1);
1967 ins->opcode = OP_REGOFFSET;
1968 ins->inst_basereg = cfg->frame_reg;
1969 ins->inst_offset = offset;
1973 if (cfg->arch.seq_point_read_var) {
1976 ins = cfg->arch.seq_point_read_var;
1980 offset += align - 1;
1981 offset &= ~(align - 1);
1982 ins->opcode = OP_REGOFFSET;
1983 ins->inst_basereg = cfg->frame_reg;
1984 ins->inst_offset = offset;
1987 ins = cfg->arch.seq_point_ss_method_var;
1990 offset += align - 1;
1991 offset &= ~(align - 1);
1992 ins->opcode = OP_REGOFFSET;
1993 ins->inst_basereg = cfg->frame_reg;
1994 ins->inst_offset = offset;
1997 ins = cfg->arch.seq_point_bp_method_var;
2000 offset += align - 1;
2001 offset &= ~(align - 1);
2002 ins->opcode = OP_REGOFFSET;
2003 ins->inst_basereg = cfg->frame_reg;
2004 ins->inst_offset = offset;
2008 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
2009 /* Allocate a temporary used by the atomic ops */
2013 /* Allocate a local slot to hold the sig cookie address */
2014 offset += align - 1;
2015 offset &= ~(align - 1);
2016 cfg->arch.atomic_tmp_offset = offset;
2019 cfg->arch.atomic_tmp_offset = -1;
2022 cfg->locals_min_stack_offset = offset;
2024 curinst = cfg->locals_start;
2025 for (i = curinst; i < cfg->num_varinfo; ++i) {
2028 ins = cfg->varinfo [i];
2029 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
2032 t = ins->inst_vtype;
2033 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (cfg, t))
2036 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
2037 * pinvoke wrappers when they call functions returning structure */
2038 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2039 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
2043 size = mono_type_size (t, &align);
2045 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2046 * since it loads/stores misaligned words, which don't do the right thing.
2048 if (align < 4 && size >= 4)
2050 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2051 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2052 offset += align - 1;
2053 offset &= ~(align - 1);
2054 ins->opcode = OP_REGOFFSET;
2055 ins->inst_offset = offset;
2056 ins->inst_basereg = cfg->frame_reg;
2058 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2061 cfg->locals_max_stack_offset = offset;
2065 ins = cfg->args [curinst];
2066 if (ins->opcode != OP_REGVAR) {
2067 ins->opcode = OP_REGOFFSET;
2068 ins->inst_basereg = cfg->frame_reg;
2069 offset += sizeof (gpointer) - 1;
2070 offset &= ~(sizeof (gpointer) - 1);
2071 ins->inst_offset = offset;
2072 offset += sizeof (gpointer);
2077 if (sig->call_convention == MONO_CALL_VARARG) {
2081 /* Allocate a local slot to hold the sig cookie address */
2082 offset += align - 1;
2083 offset &= ~(align - 1);
2084 cfg->sig_cookie = offset;
2088 for (i = 0; i < sig->param_count; ++i) {
2089 ins = cfg->args [curinst];
2091 if (ins->opcode != OP_REGVAR) {
2092 ins->opcode = OP_REGOFFSET;
2093 ins->inst_basereg = cfg->frame_reg;
2094 size = mini_type_stack_size_full (cfg->generic_sharing_context, sig->params [i], &ualign, sig->pinvoke);
2096 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2097 * since it loads/stores misaligned words, which don't do the right thing.
2099 if (align < 4 && size >= 4)
2101 /* The code in the prolog () stores words when storing vtypes received in a register */
2102 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2104 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2105 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2106 offset += align - 1;
2107 offset &= ~(align - 1);
2108 ins->inst_offset = offset;
2114 /* align the offset to 8 bytes */
2115 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2116 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2121 cfg->stack_offset = offset;
2125 mono_arch_create_vars (MonoCompile *cfg)
2127 MonoMethodSignature *sig;
2131 sig = mono_method_signature (cfg->method);
2133 if (!cfg->arch.cinfo)
2134 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2135 cinfo = cfg->arch.cinfo;
2137 if (IS_HARD_FLOAT) {
2138 for (i = 0; i < 2; i++) {
2139 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2140 inst->flags |= MONO_INST_VOLATILE;
2142 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2146 if (cinfo->ret.storage == RegTypeStructByVal)
2147 cfg->ret_var_is_local = TRUE;
2149 if (cinfo->vtype_retaddr) {
2150 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2151 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2152 printf ("vret_addr = ");
2153 mono_print_ins (cfg->vret_addr);
2157 if (cfg->gen_sdb_seq_points) {
2158 if (cfg->soft_breakpoints) {
2159 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2160 ins->flags |= MONO_INST_VOLATILE;
2161 cfg->arch.seq_point_read_var = ins;
2163 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2164 ins->flags |= MONO_INST_VOLATILE;
2165 cfg->arch.seq_point_ss_method_var = ins;
2167 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2168 ins->flags |= MONO_INST_VOLATILE;
2169 cfg->arch.seq_point_bp_method_var = ins;
2171 g_assert (!cfg->compile_aot);
2172 } else if (cfg->compile_aot) {
2173 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2174 ins->flags |= MONO_INST_VOLATILE;
2175 cfg->arch.seq_point_info_var = ins;
2177 /* Allocate a separate variable for this to save 1 load per seq point */
2178 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2179 ins->flags |= MONO_INST_VOLATILE;
2180 cfg->arch.ss_trigger_page_var = ins;
2186 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2188 MonoMethodSignature *tmp_sig;
2191 if (call->tail_call)
2194 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2197 * mono_ArgIterator_Setup assumes the signature cookie is
2198 * passed first and all the arguments which were before it are
2199 * passed on the stack after the signature. So compensate by
2200 * passing a different signature.
2202 tmp_sig = mono_metadata_signature_dup (call->signature);
2203 tmp_sig->param_count -= call->signature->sentinelpos;
2204 tmp_sig->sentinelpos = 0;
2205 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2207 sig_reg = mono_alloc_ireg (cfg);
2208 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2210 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2215 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2220 LLVMCallInfo *linfo;
2222 n = sig->param_count + sig->hasthis;
2224 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2226 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2229 * LLVM always uses the native ABI while we use our own ABI, the
2230 * only difference is the handling of vtypes:
2231 * - we only pass/receive them in registers in some cases, and only
2232 * in 1 or 2 integer registers.
2234 if (cinfo->vtype_retaddr) {
2235 /* Vtype returned using a hidden argument */
2236 linfo->ret.storage = LLVMArgVtypeRetAddr;
2237 linfo->vret_arg_index = cinfo->vret_arg_index;
2238 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
2239 cfg->exception_message = g_strdup ("unknown ret conv");
2240 cfg->disable_llvm = TRUE;
2244 for (i = 0; i < n; ++i) {
2245 ainfo = cinfo->args + i;
2247 linfo->args [i].storage = LLVMArgNone;
2249 switch (ainfo->storage) {
2250 case RegTypeGeneral:
2251 case RegTypeIRegPair:
2253 linfo->args [i].storage = LLVMArgInIReg;
2255 case RegTypeStructByVal:
2256 linfo->args [i].storage = LLVMArgAsIArgs;
2257 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2260 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2261 cfg->disable_llvm = TRUE;
2271 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2274 MonoMethodSignature *sig;
2278 sig = call->signature;
2279 n = sig->param_count + sig->hasthis;
2281 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
2283 for (i = 0; i < n; ++i) {
2284 ArgInfo *ainfo = cinfo->args + i;
2287 if (i >= sig->hasthis)
2288 t = sig->params [i - sig->hasthis];
2290 t = &mono_defaults.int_class->byval_arg;
2291 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
2293 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2294 /* Emit the signature cookie just before the implicit arguments */
2295 emit_sig_cookie (cfg, call, cinfo);
2298 in = call->args [i];
2300 switch (ainfo->storage) {
2301 case RegTypeGeneral:
2302 case RegTypeIRegPair:
2303 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2304 MONO_INST_NEW (cfg, ins, OP_MOVE);
2305 ins->dreg = mono_alloc_ireg (cfg);
2306 ins->sreg1 = in->dreg + 1;
2307 MONO_ADD_INS (cfg->cbb, ins);
2308 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2310 MONO_INST_NEW (cfg, ins, OP_MOVE);
2311 ins->dreg = mono_alloc_ireg (cfg);
2312 ins->sreg1 = in->dreg + 2;
2313 MONO_ADD_INS (cfg->cbb, ins);
2314 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2315 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2316 if (ainfo->size == 4) {
2317 if (IS_SOFT_FLOAT) {
2318 /* mono_emit_call_args () have already done the r8->r4 conversion */
2319 /* The converted value is in an int vreg */
2320 MONO_INST_NEW (cfg, ins, OP_MOVE);
2321 ins->dreg = mono_alloc_ireg (cfg);
2322 ins->sreg1 = in->dreg;
2323 MONO_ADD_INS (cfg->cbb, ins);
2324 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2328 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2329 creg = mono_alloc_ireg (cfg);
2330 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2331 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2334 if (IS_SOFT_FLOAT) {
2335 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2336 ins->dreg = mono_alloc_ireg (cfg);
2337 ins->sreg1 = in->dreg;
2338 MONO_ADD_INS (cfg->cbb, ins);
2339 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2341 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2342 ins->dreg = mono_alloc_ireg (cfg);
2343 ins->sreg1 = in->dreg;
2344 MONO_ADD_INS (cfg->cbb, ins);
2345 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2349 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2350 creg = mono_alloc_ireg (cfg);
2351 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2352 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2353 creg = mono_alloc_ireg (cfg);
2354 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2355 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2358 cfg->flags |= MONO_CFG_HAS_FPOUT;
2360 MONO_INST_NEW (cfg, ins, OP_MOVE);
2361 ins->dreg = mono_alloc_ireg (cfg);
2362 ins->sreg1 = in->dreg;
2363 MONO_ADD_INS (cfg->cbb, ins);
2365 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2368 case RegTypeStructByAddr:
2371 /* FIXME: where si the data allocated? */
2372 arg->backend.reg3 = ainfo->reg;
2373 call->used_iregs |= 1 << ainfo->reg;
2374 g_assert_not_reached ();
2377 case RegTypeStructByVal:
2378 case RegTypeGSharedVtInReg:
2379 case RegTypeGSharedVtOnStack:
2380 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2381 ins->opcode = OP_OUTARG_VT;
2382 ins->sreg1 = in->dreg;
2383 ins->klass = in->klass;
2384 ins->inst_p0 = call;
2385 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2386 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2387 mono_call_inst_add_outarg_vt (cfg, call, ins);
2388 MONO_ADD_INS (cfg->cbb, ins);
2391 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2392 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2393 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2394 if (t->type == MONO_TYPE_R8) {
2395 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2398 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2400 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2403 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2406 case RegTypeBaseGen:
2407 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2408 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
2409 MONO_INST_NEW (cfg, ins, OP_MOVE);
2410 ins->dreg = mono_alloc_ireg (cfg);
2411 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
2412 MONO_ADD_INS (cfg->cbb, ins);
2413 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2414 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2417 /* This should work for soft-float as well */
2419 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2420 creg = mono_alloc_ireg (cfg);
2421 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2422 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2423 creg = mono_alloc_ireg (cfg);
2424 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2425 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2426 cfg->flags |= MONO_CFG_HAS_FPOUT;
2428 g_assert_not_reached ();
2432 int fdreg = mono_alloc_freg (cfg);
2434 if (ainfo->size == 8) {
2435 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2436 ins->sreg1 = in->dreg;
2438 MONO_ADD_INS (cfg->cbb, ins);
2440 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2445 * Mono's register allocator doesn't speak single-precision registers that
2446 * overlap double-precision registers (i.e. armhf). So we have to work around
2447 * the register allocator and load the value from memory manually.
2449 * So we create a variable for the float argument and an instruction to store
2450 * the argument into the variable. We then store the list of these arguments
2451 * in cfg->float_args. This list is then used by emit_float_args later to
2452 * pass the arguments in the various call opcodes.
2454 * This is not very nice, and we should really try to fix the allocator.
2457 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2459 /* Make sure the instruction isn't seen as pointless and removed.
2461 float_arg->flags |= MONO_INST_VOLATILE;
2463 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2465 /* We use the dreg to look up the instruction later. The hreg is used to
2466 * emit the instruction that loads the value into the FP reg.
2468 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2469 fad->vreg = float_arg->dreg;
2470 fad->hreg = ainfo->reg;
2472 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2475 call->used_iregs |= 1 << ainfo->reg;
2476 cfg->flags |= MONO_CFG_HAS_FPOUT;
2480 g_assert_not_reached ();
2484 /* Handle the case where there are no implicit arguments */
2485 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2486 emit_sig_cookie (cfg, call, cinfo);
2488 if (cinfo->ret.storage == RegTypeStructByVal) {
2489 /* The JIT will transform this into a normal call */
2490 call->vret_in_reg = TRUE;
2491 } else if (cinfo->vtype_retaddr) {
2493 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2494 vtarg->sreg1 = call->vret_var->dreg;
2495 vtarg->dreg = mono_alloc_preg (cfg);
2496 MONO_ADD_INS (cfg->cbb, vtarg);
2498 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2501 call->stack_usage = cinfo->stack_usage;
2507 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2509 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2510 ArgInfo *ainfo = ins->inst_p1;
2511 int ovf_size = ainfo->vtsize;
2512 int doffset = ainfo->offset;
2513 int struct_size = ainfo->struct_size;
2514 int i, soffset, dreg, tmpreg;
2516 if (ainfo->storage == RegTypeGSharedVtInReg) {
2518 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2521 if (ainfo->storage == RegTypeGSharedVtOnStack) {
2522 /* Pass by addr on stack */
2523 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2528 for (i = 0; i < ainfo->size; ++i) {
2529 dreg = mono_alloc_ireg (cfg);
2530 switch (struct_size) {
2532 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2535 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2538 tmpreg = mono_alloc_ireg (cfg);
2539 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2540 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2541 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2542 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2543 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2544 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2545 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2548 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2551 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2552 soffset += sizeof (gpointer);
2553 struct_size -= sizeof (gpointer);
2555 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2557 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2561 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2563 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2566 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2569 if (COMPILE_LLVM (cfg)) {
2570 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2572 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2573 ins->sreg1 = val->dreg + 1;
2574 ins->sreg2 = val->dreg + 2;
2575 MONO_ADD_INS (cfg->cbb, ins);
2580 case MONO_ARM_FPU_NONE:
2581 if (ret->type == MONO_TYPE_R8) {
2584 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2585 ins->dreg = cfg->ret->dreg;
2586 ins->sreg1 = val->dreg;
2587 MONO_ADD_INS (cfg->cbb, ins);
2590 if (ret->type == MONO_TYPE_R4) {
2591 /* Already converted to an int in method_to_ir () */
2592 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2596 case MONO_ARM_FPU_VFP:
2597 case MONO_ARM_FPU_VFP_HARD:
2598 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2601 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2602 ins->dreg = cfg->ret->dreg;
2603 ins->sreg1 = val->dreg;
2604 MONO_ADD_INS (cfg->cbb, ins);
2609 g_assert_not_reached ();
2613 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2616 #endif /* #ifndef DISABLE_JIT */
2619 mono_arch_is_inst_imm (gint64 imm)
2625 MonoMethodSignature *sig;
2628 MonoType **param_types;
2632 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2636 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2639 switch (cinfo->ret.storage) {
2641 case RegTypeGeneral:
2642 case RegTypeIRegPair:
2643 case RegTypeStructByAddr:
2654 for (i = 0; i < cinfo->nargs; ++i) {
2655 ArgInfo *ainfo = &cinfo->args [i];
2658 switch (ainfo->storage) {
2659 case RegTypeGeneral:
2661 case RegTypeIRegPair:
2664 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2667 case RegTypeStructByVal:
2668 if (ainfo->size == 0)
2669 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2671 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2672 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2680 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2681 for (i = 0; i < sig->param_count; ++i) {
2682 MonoType *t = sig->params [i];
2687 t = mini_replace_type (t);
2710 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2712 ArchDynCallInfo *info;
2716 cinfo = get_call_info (NULL, NULL, sig);
2718 if (!dyn_call_supported (cinfo, sig)) {
2723 info = g_new0 (ArchDynCallInfo, 1);
2724 // FIXME: Preprocess the info to speed up start_dyn_call ()
2726 info->cinfo = cinfo;
2727 info->rtype = mini_type_get_underlying_type (NULL, sig->ret);
2728 info->param_types = g_new0 (MonoType*, sig->param_count);
2729 for (i = 0; i < sig->param_count; ++i)
2730 info->param_types [i] = mini_type_get_underlying_type (NULL, sig->params [i]);
2732 return (MonoDynCallInfo*)info;
2736 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2738 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2740 g_free (ainfo->cinfo);
2745 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2747 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2748 DynCallArgs *p = (DynCallArgs*)buf;
2749 int arg_index, greg, i, j, pindex;
2750 MonoMethodSignature *sig = dinfo->sig;
2752 g_assert (buf_len >= sizeof (DynCallArgs));
2761 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2762 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2767 if (dinfo->cinfo->vtype_retaddr)
2768 p->regs [greg ++] = (mgreg_t)ret;
2770 for (i = pindex; i < sig->param_count; i++) {
2771 MonoType *t = dinfo->param_types [i];
2772 gpointer *arg = args [arg_index ++];
2773 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2776 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2778 else if (ainfo->storage == RegTypeBase)
2779 slot = PARAM_REGS + (ainfo->offset / 4);
2781 g_assert_not_reached ();
2784 p->regs [slot] = (mgreg_t)*arg;
2789 case MONO_TYPE_STRING:
2790 case MONO_TYPE_CLASS:
2791 case MONO_TYPE_ARRAY:
2792 case MONO_TYPE_SZARRAY:
2793 case MONO_TYPE_OBJECT:
2797 p->regs [slot] = (mgreg_t)*arg;
2800 p->regs [slot] = *(guint8*)arg;
2803 p->regs [slot] = *(gint8*)arg;
2806 p->regs [slot] = *(gint16*)arg;
2809 p->regs [slot] = *(guint16*)arg;
2812 p->regs [slot] = *(gint32*)arg;
2815 p->regs [slot] = *(guint32*)arg;
2819 p->regs [slot ++] = (mgreg_t)arg [0];
2820 p->regs [slot] = (mgreg_t)arg [1];
2823 p->regs [slot] = *(mgreg_t*)arg;
2826 p->regs [slot ++] = (mgreg_t)arg [0];
2827 p->regs [slot] = (mgreg_t)arg [1];
2829 case MONO_TYPE_GENERICINST:
2830 if (MONO_TYPE_IS_REFERENCE (t)) {
2831 p->regs [slot] = (mgreg_t)*arg;
2836 case MONO_TYPE_VALUETYPE:
2837 g_assert (ainfo->storage == RegTypeStructByVal);
2839 if (ainfo->size == 0)
2840 slot = PARAM_REGS + (ainfo->offset / 4);
2844 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2845 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2848 g_assert_not_reached ();
2854 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2856 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2857 MonoType *ptype = ainfo->rtype;
2858 guint8 *ret = ((DynCallArgs*)buf)->ret;
2859 mgreg_t res = ((DynCallArgs*)buf)->res;
2860 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2862 switch (ptype->type) {
2863 case MONO_TYPE_VOID:
2864 *(gpointer*)ret = NULL;
2866 case MONO_TYPE_STRING:
2867 case MONO_TYPE_CLASS:
2868 case MONO_TYPE_ARRAY:
2869 case MONO_TYPE_SZARRAY:
2870 case MONO_TYPE_OBJECT:
2874 *(gpointer*)ret = (gpointer)res;
2880 *(guint8*)ret = res;
2883 *(gint16*)ret = res;
2886 *(guint16*)ret = res;
2889 *(gint32*)ret = res;
2892 *(guint32*)ret = res;
2896 /* This handles endianness as well */
2897 ((gint32*)ret) [0] = res;
2898 ((gint32*)ret) [1] = res2;
2900 case MONO_TYPE_GENERICINST:
2901 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2902 *(gpointer*)ret = (gpointer)res;
2907 case MONO_TYPE_VALUETYPE:
2908 g_assert (ainfo->cinfo->vtype_retaddr);
2913 *(float*)ret = *(float*)&res;
2915 case MONO_TYPE_R8: {
2922 *(double*)ret = *(double*)®s;
2926 g_assert_not_reached ();
2933 * Allow tracing to work with this interface (with an optional argument)
2937 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2941 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2942 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2943 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2944 code = emit_call_reg (code, ARMREG_R2);
2958 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2961 int save_mode = SAVE_NONE;
2963 MonoMethod *method = cfg->method;
2964 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2965 int rtype = ret_type->type;
2966 int save_offset = cfg->param_area;
2970 offset = code - cfg->native_code;
2971 /* we need about 16 instructions */
2972 if (offset > (cfg->code_size - 16 * 4)) {
2973 cfg->code_size *= 2;
2974 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2975 code = cfg->native_code + offset;
2978 case MONO_TYPE_VOID:
2979 /* special case string .ctor icall */
2980 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2981 save_mode = SAVE_ONE;
2983 save_mode = SAVE_NONE;
2987 save_mode = SAVE_TWO;
2991 save_mode = SAVE_ONE_FP;
2993 save_mode = SAVE_ONE;
2997 save_mode = SAVE_TWO_FP;
2999 save_mode = SAVE_TWO;
3001 case MONO_TYPE_GENERICINST:
3002 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3003 save_mode = SAVE_ONE;
3007 case MONO_TYPE_VALUETYPE:
3008 save_mode = SAVE_STRUCT;
3011 save_mode = SAVE_ONE;
3015 switch (save_mode) {
3017 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3018 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3019 if (enable_arguments) {
3020 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3021 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3025 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3026 if (enable_arguments) {
3027 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3031 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3032 if (enable_arguments) {
3033 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3037 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3038 if (enable_arguments) {
3039 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3043 if (enable_arguments) {
3044 /* FIXME: get the actual address */
3045 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3053 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3054 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3055 code = emit_call_reg (code, ARMREG_IP);
3057 switch (save_mode) {
3059 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3060 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3063 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3066 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3069 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3080 * The immediate field for cond branches is big enough for all reasonable methods
3082 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3083 if (0 && ins->inst_true_bb->native_offset) { \
3084 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3086 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3087 ARM_B_COND (code, (condcode), 0); \
3090 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3092 /* emit an exception if condition is fail
3094 * We assign the extra code used to throw the implicit exceptions
3095 * to cfg->bb_exit as far as the big branch handling is concerned
3097 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3099 mono_add_patch_info (cfg, code - cfg->native_code, \
3100 MONO_PATCH_INFO_EXC, exc_name); \
3101 ARM_BL_COND (code, (condcode), 0); \
3104 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3107 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3112 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3116 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3117 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3119 switch (ins->opcode) {
3122 /* Already done by an arch-independent pass */
3124 case OP_LOAD_MEMBASE:
3125 case OP_LOADI4_MEMBASE:
3127 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3128 * OP_LOAD_MEMBASE offset(basereg), reg
3130 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3131 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3132 ins->inst_basereg == last_ins->inst_destbasereg &&
3133 ins->inst_offset == last_ins->inst_offset) {
3134 if (ins->dreg == last_ins->sreg1) {
3135 MONO_DELETE_INS (bb, ins);
3138 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3139 ins->opcode = OP_MOVE;
3140 ins->sreg1 = last_ins->sreg1;
3144 * Note: reg1 must be different from the basereg in the second load
3145 * OP_LOAD_MEMBASE offset(basereg), reg1
3146 * OP_LOAD_MEMBASE offset(basereg), reg2
3148 * OP_LOAD_MEMBASE offset(basereg), reg1
3149 * OP_MOVE reg1, reg2
3151 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3152 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3153 ins->inst_basereg != last_ins->dreg &&
3154 ins->inst_basereg == last_ins->inst_basereg &&
3155 ins->inst_offset == last_ins->inst_offset) {
3157 if (ins->dreg == last_ins->dreg) {
3158 MONO_DELETE_INS (bb, ins);
3161 ins->opcode = OP_MOVE;
3162 ins->sreg1 = last_ins->dreg;
3165 //g_assert_not_reached ();
3169 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3170 * OP_LOAD_MEMBASE offset(basereg), reg
3172 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3173 * OP_ICONST reg, imm
3175 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3176 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3177 ins->inst_basereg == last_ins->inst_destbasereg &&
3178 ins->inst_offset == last_ins->inst_offset) {
3179 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3180 ins->opcode = OP_ICONST;
3181 ins->inst_c0 = last_ins->inst_imm;
3182 g_assert_not_reached (); // check this rule
3186 case OP_LOADU1_MEMBASE:
3187 case OP_LOADI1_MEMBASE:
3188 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3189 ins->inst_basereg == last_ins->inst_destbasereg &&
3190 ins->inst_offset == last_ins->inst_offset) {
3191 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3192 ins->sreg1 = last_ins->sreg1;
3195 case OP_LOADU2_MEMBASE:
3196 case OP_LOADI2_MEMBASE:
3197 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3198 ins->inst_basereg == last_ins->inst_destbasereg &&
3199 ins->inst_offset == last_ins->inst_offset) {
3200 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3201 ins->sreg1 = last_ins->sreg1;
3205 ins->opcode = OP_MOVE;
3209 if (ins->dreg == ins->sreg1) {
3210 MONO_DELETE_INS (bb, ins);
3214 * OP_MOVE sreg, dreg
3215 * OP_MOVE dreg, sreg
3217 if (last_ins && last_ins->opcode == OP_MOVE &&
3218 ins->sreg1 == last_ins->dreg &&
3219 ins->dreg == last_ins->sreg1) {
3220 MONO_DELETE_INS (bb, ins);
3229 * the branch_cc_table should maintain the order of these
3243 branch_cc_table [] = {
3257 #define ADD_NEW_INS(cfg,dest,op) do { \
3258 MONO_INST_NEW ((cfg), (dest), (op)); \
3259 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3263 map_to_reg_reg_op (int op)
3272 case OP_COMPARE_IMM:
3274 case OP_ICOMPARE_IMM:
3288 case OP_LOAD_MEMBASE:
3289 return OP_LOAD_MEMINDEX;
3290 case OP_LOADI4_MEMBASE:
3291 return OP_LOADI4_MEMINDEX;
3292 case OP_LOADU4_MEMBASE:
3293 return OP_LOADU4_MEMINDEX;
3294 case OP_LOADU1_MEMBASE:
3295 return OP_LOADU1_MEMINDEX;
3296 case OP_LOADI2_MEMBASE:
3297 return OP_LOADI2_MEMINDEX;
3298 case OP_LOADU2_MEMBASE:
3299 return OP_LOADU2_MEMINDEX;
3300 case OP_LOADI1_MEMBASE:
3301 return OP_LOADI1_MEMINDEX;
3302 case OP_STOREI1_MEMBASE_REG:
3303 return OP_STOREI1_MEMINDEX;
3304 case OP_STOREI2_MEMBASE_REG:
3305 return OP_STOREI2_MEMINDEX;
3306 case OP_STOREI4_MEMBASE_REG:
3307 return OP_STOREI4_MEMINDEX;
3308 case OP_STORE_MEMBASE_REG:
3309 return OP_STORE_MEMINDEX;
3310 case OP_STORER4_MEMBASE_REG:
3311 return OP_STORER4_MEMINDEX;
3312 case OP_STORER8_MEMBASE_REG:
3313 return OP_STORER8_MEMINDEX;
3314 case OP_STORE_MEMBASE_IMM:
3315 return OP_STORE_MEMBASE_REG;
3316 case OP_STOREI1_MEMBASE_IMM:
3317 return OP_STOREI1_MEMBASE_REG;
3318 case OP_STOREI2_MEMBASE_IMM:
3319 return OP_STOREI2_MEMBASE_REG;
3320 case OP_STOREI4_MEMBASE_IMM:
3321 return OP_STOREI4_MEMBASE_REG;
3323 g_assert_not_reached ();
3327 * Remove from the instruction list the instructions that can't be
3328 * represented with very simple instructions with no register
3332 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3334 MonoInst *ins, *temp, *last_ins = NULL;
3335 int rot_amount, imm8, low_imm;
3337 MONO_BB_FOR_EACH_INS (bb, ins) {
3339 switch (ins->opcode) {
3343 case OP_COMPARE_IMM:
3344 case OP_ICOMPARE_IMM:
3358 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3359 ADD_NEW_INS (cfg, temp, OP_ICONST);
3360 temp->inst_c0 = ins->inst_imm;
3361 temp->dreg = mono_alloc_ireg (cfg);
3362 ins->sreg2 = temp->dreg;
3363 ins->opcode = mono_op_imm_to_op (ins->opcode);
3365 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3371 if (ins->inst_imm == 1) {
3372 ins->opcode = OP_MOVE;
3375 if (ins->inst_imm == 0) {
3376 ins->opcode = OP_ICONST;
3380 imm8 = mono_is_power_of_two (ins->inst_imm);
3382 ins->opcode = OP_SHL_IMM;
3383 ins->inst_imm = imm8;
3386 ADD_NEW_INS (cfg, temp, OP_ICONST);
3387 temp->inst_c0 = ins->inst_imm;
3388 temp->dreg = mono_alloc_ireg (cfg);
3389 ins->sreg2 = temp->dreg;
3390 ins->opcode = OP_IMUL;
3396 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3397 /* ARM sets the C flag to 1 if there was _no_ overflow */
3398 ins->next->opcode = OP_COND_EXC_NC;
3401 case OP_IDIV_UN_IMM:
3403 case OP_IREM_UN_IMM:
3404 ADD_NEW_INS (cfg, temp, OP_ICONST);
3405 temp->inst_c0 = ins->inst_imm;
3406 temp->dreg = mono_alloc_ireg (cfg);
3407 ins->sreg2 = temp->dreg;
3408 ins->opcode = mono_op_imm_to_op (ins->opcode);
3410 case OP_LOCALLOC_IMM:
3411 ADD_NEW_INS (cfg, temp, OP_ICONST);
3412 temp->inst_c0 = ins->inst_imm;
3413 temp->dreg = mono_alloc_ireg (cfg);
3414 ins->sreg1 = temp->dreg;
3415 ins->opcode = OP_LOCALLOC;
3417 case OP_LOAD_MEMBASE:
3418 case OP_LOADI4_MEMBASE:
3419 case OP_LOADU4_MEMBASE:
3420 case OP_LOADU1_MEMBASE:
3421 /* we can do two things: load the immed in a register
3422 * and use an indexed load, or see if the immed can be
3423 * represented as an ad_imm + a load with a smaller offset
3424 * that fits. We just do the first for now, optimize later.
3426 if (arm_is_imm12 (ins->inst_offset))
3428 ADD_NEW_INS (cfg, temp, OP_ICONST);
3429 temp->inst_c0 = ins->inst_offset;
3430 temp->dreg = mono_alloc_ireg (cfg);
3431 ins->sreg2 = temp->dreg;
3432 ins->opcode = map_to_reg_reg_op (ins->opcode);
3434 case OP_LOADI2_MEMBASE:
3435 case OP_LOADU2_MEMBASE:
3436 case OP_LOADI1_MEMBASE:
3437 if (arm_is_imm8 (ins->inst_offset))
3439 ADD_NEW_INS (cfg, temp, OP_ICONST);
3440 temp->inst_c0 = ins->inst_offset;
3441 temp->dreg = mono_alloc_ireg (cfg);
3442 ins->sreg2 = temp->dreg;
3443 ins->opcode = map_to_reg_reg_op (ins->opcode);
3445 case OP_LOADR4_MEMBASE:
3446 case OP_LOADR8_MEMBASE:
3447 if (arm_is_fpimm8 (ins->inst_offset))
3449 low_imm = ins->inst_offset & 0x1ff;
3450 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3451 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3452 temp->inst_imm = ins->inst_offset & ~0x1ff;
3453 temp->sreg1 = ins->inst_basereg;
3454 temp->dreg = mono_alloc_ireg (cfg);
3455 ins->inst_basereg = temp->dreg;
3456 ins->inst_offset = low_imm;
3460 ADD_NEW_INS (cfg, temp, OP_ICONST);
3461 temp->inst_c0 = ins->inst_offset;
3462 temp->dreg = mono_alloc_ireg (cfg);
3464 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3465 add_ins->sreg1 = ins->inst_basereg;
3466 add_ins->sreg2 = temp->dreg;
3467 add_ins->dreg = mono_alloc_ireg (cfg);
3469 ins->inst_basereg = add_ins->dreg;
3470 ins->inst_offset = 0;
3473 case OP_STORE_MEMBASE_REG:
3474 case OP_STOREI4_MEMBASE_REG:
3475 case OP_STOREI1_MEMBASE_REG:
3476 if (arm_is_imm12 (ins->inst_offset))
3478 ADD_NEW_INS (cfg, temp, OP_ICONST);
3479 temp->inst_c0 = ins->inst_offset;
3480 temp->dreg = mono_alloc_ireg (cfg);
3481 ins->sreg2 = temp->dreg;
3482 ins->opcode = map_to_reg_reg_op (ins->opcode);
3484 case OP_STOREI2_MEMBASE_REG:
3485 if (arm_is_imm8 (ins->inst_offset))
3487 ADD_NEW_INS (cfg, temp, OP_ICONST);
3488 temp->inst_c0 = ins->inst_offset;
3489 temp->dreg = mono_alloc_ireg (cfg);
3490 ins->sreg2 = temp->dreg;
3491 ins->opcode = map_to_reg_reg_op (ins->opcode);
3493 case OP_STORER4_MEMBASE_REG:
3494 case OP_STORER8_MEMBASE_REG:
3495 if (arm_is_fpimm8 (ins->inst_offset))
3497 low_imm = ins->inst_offset & 0x1ff;
3498 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3499 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3500 temp->inst_imm = ins->inst_offset & ~0x1ff;
3501 temp->sreg1 = ins->inst_destbasereg;
3502 temp->dreg = mono_alloc_ireg (cfg);
3503 ins->inst_destbasereg = temp->dreg;
3504 ins->inst_offset = low_imm;
3508 ADD_NEW_INS (cfg, temp, OP_ICONST);
3509 temp->inst_c0 = ins->inst_offset;
3510 temp->dreg = mono_alloc_ireg (cfg);
3512 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3513 add_ins->sreg1 = ins->inst_destbasereg;
3514 add_ins->sreg2 = temp->dreg;
3515 add_ins->dreg = mono_alloc_ireg (cfg);
3517 ins->inst_destbasereg = add_ins->dreg;
3518 ins->inst_offset = 0;
3521 case OP_STORE_MEMBASE_IMM:
3522 case OP_STOREI1_MEMBASE_IMM:
3523 case OP_STOREI2_MEMBASE_IMM:
3524 case OP_STOREI4_MEMBASE_IMM:
3525 ADD_NEW_INS (cfg, temp, OP_ICONST);
3526 temp->inst_c0 = ins->inst_imm;
3527 temp->dreg = mono_alloc_ireg (cfg);
3528 ins->sreg1 = temp->dreg;
3529 ins->opcode = map_to_reg_reg_op (ins->opcode);
3531 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3534 gboolean swap = FALSE;
3538 /* Optimized away */
3543 /* Some fp compares require swapped operands */
3544 switch (ins->next->opcode) {
3546 ins->next->opcode = OP_FBLT;
3550 ins->next->opcode = OP_FBLT_UN;
3554 ins->next->opcode = OP_FBGE;
3558 ins->next->opcode = OP_FBGE_UN;
3566 ins->sreg1 = ins->sreg2;
3575 bb->last_ins = last_ins;
3576 bb->max_vreg = cfg->next_vreg;
3580 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3584 if (long_ins->opcode == OP_LNEG) {
3586 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3587 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3593 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3595 /* sreg is a float, dreg is an integer reg */
3597 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3599 ARM_TOSIZD (code, vfp_scratch1, sreg);
3601 ARM_TOUIZD (code, vfp_scratch1, sreg);
3602 ARM_FMRS (code, dreg, vfp_scratch1);
3603 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3607 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3608 else if (size == 2) {
3609 ARM_SHL_IMM (code, dreg, dreg, 16);
3610 ARM_SHR_IMM (code, dreg, dreg, 16);
3614 ARM_SHL_IMM (code, dreg, dreg, 24);
3615 ARM_SAR_IMM (code, dreg, dreg, 24);
3616 } else if (size == 2) {
3617 ARM_SHL_IMM (code, dreg, dreg, 16);
3618 ARM_SAR_IMM (code, dreg, dreg, 16);
3625 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3627 /* sreg is a float, dreg is an integer reg */
3629 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3631 ARM_TOSIZS (code, vfp_scratch1, sreg);
3633 ARM_TOUIZS (code, vfp_scratch1, sreg);
3634 ARM_FMRS (code, dreg, vfp_scratch1);
3635 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3639 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3640 else if (size == 2) {
3641 ARM_SHL_IMM (code, dreg, dreg, 16);
3642 ARM_SHR_IMM (code, dreg, dreg, 16);
3646 ARM_SHL_IMM (code, dreg, dreg, 24);
3647 ARM_SAR_IMM (code, dreg, dreg, 24);
3648 } else if (size == 2) {
3649 ARM_SHL_IMM (code, dreg, dreg, 16);
3650 ARM_SAR_IMM (code, dreg, dreg, 16);
3656 #endif /* #ifndef DISABLE_JIT */
3660 const guchar *target;
3665 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3668 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
3669 PatchData *pdata = (PatchData*)user_data;
3670 guchar *code = data;
3671 guint32 *thunks = data;
3672 guint32 *endthunks = (guint32*)(code + bsize);
3674 int difflow, diffhigh;
3676 /* always ensure a call from pdata->code can reach to the thunks without further thunks */
3677 difflow = (char*)pdata->code - (char*)thunks;
3678 diffhigh = (char*)pdata->code - (char*)endthunks;
3679 if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
3683 * The thunk is composed of 3 words:
3684 * load constant from thunks [2] into ARM_IP
3687 * Note that the LR register is already setup
3689 //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
3690 if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
3691 while (thunks < endthunks) {
3692 //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
3693 if (thunks [2] == (guint32)pdata->target) {
3694 arm_patch (pdata->code, (guchar*)thunks);
3695 mono_arch_flush_icache (pdata->code, 4);
3698 } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
3699 /* found a free slot instead: emit thunk */
3700 /* ARMREG_IP is fine to use since this can't be an IMT call
3703 code = (guchar*)thunks;
3704 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3705 if (thumb_supported)
3706 ARM_BX (code, ARMREG_IP);
3708 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3709 thunks [2] = (guint32)pdata->target;
3710 mono_arch_flush_icache ((guchar*)thunks, 12);
3712 arm_patch (pdata->code, (guchar*)thunks);
3713 mono_arch_flush_icache (pdata->code, 4);
3717 /* skip 12 bytes, the size of the thunk */
3721 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
3727 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3732 domain = mono_domain_get ();
3735 pdata.target = target;
3736 pdata.absolute = absolute;
3740 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
3743 if (pdata.found != 1) {
3744 mono_domain_lock (domain);
3745 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3748 /* this uses the first available slot */
3750 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3752 mono_domain_unlock (domain);
3755 if (pdata.found != 1) {
3757 GHashTableIter iter;
3758 MonoJitDynamicMethodInfo *ji;
3761 * This might be a dynamic method, search its code manager. We can only
3762 * use the dynamic method containing CODE, since the others might be freed later.
3766 mono_domain_lock (domain);
3767 hash = domain_jit_info (domain)->dynamic_code_hash;
3769 /* FIXME: Speed this up */
3770 g_hash_table_iter_init (&iter, hash);
3771 while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
3772 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
3773 if (pdata.found == 1)
3777 mono_domain_unlock (domain);
3779 if (pdata.found != 1)
3780 g_print ("thunk failed for %p from %p\n", target, code);
3781 g_assert (pdata.found == 1);
3785 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3787 guint32 *code32 = (void*)code;
3788 guint32 ins = *code32;
3789 guint32 prim = (ins >> 25) & 7;
3790 guint32 tval = GPOINTER_TO_UINT (target);
3792 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3793 if (prim == 5) { /* 101b */
3794 /* the diff starts 8 bytes from the branch opcode */
3795 gint diff = target - code - 8;
3797 gint tmask = 0xffffffff;
3798 if (tval & 1) { /* entering thumb mode */
3799 diff = target - 1 - code - 8;
3800 g_assert (thumb_supported);
3801 tbits = 0xf << 28; /* bl->blx bit pattern */
3802 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3803 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3807 tmask = ~(1 << 24); /* clear the link bit */
3808 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3813 if (diff <= 33554431) {
3815 ins = (ins & 0xff000000) | diff;
3817 *code32 = ins | tbits;
3821 /* diff between 0 and -33554432 */
3822 if (diff >= -33554432) {
3824 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3826 *code32 = ins | tbits;
3831 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3835 #ifdef USE_JUMP_TABLES
3837 gpointer *jte = mono_jumptable_get_entry (code);
3839 jte [0] = (gpointer) target;
3843 * The alternative call sequences looks like this:
3845 * ldr ip, [pc] // loads the address constant
3846 * b 1f // jumps around the constant
3847 * address constant embedded in the code
3852 * There are two cases for patching:
3853 * a) at the end of method emission: in this case code points to the start
3854 * of the call sequence
3855 * b) during runtime patching of the call site: in this case code points
3856 * to the mov pc, ip instruction
3858 * We have to handle also the thunk jump code sequence:
3862 * address constant // execution never reaches here
3864 if ((ins & 0x0ffffff0) == 0x12fff10) {
3865 /* Branch and exchange: the address is constructed in a reg
3866 * We can patch BX when the code sequence is the following:
3867 * ldr ip, [pc, #0] ; 0x8
3874 guint8 *emit = (guint8*)ccode;
3875 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3877 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3878 ARM_BX (emit, ARMREG_IP);
3880 /*patching from magic trampoline*/
3881 if (ins == ccode [3]) {
3882 g_assert (code32 [-4] == ccode [0]);
3883 g_assert (code32 [-3] == ccode [1]);
3884 g_assert (code32 [-1] == ccode [2]);
3885 code32 [-2] = (guint32)target;
3888 /*patching from JIT*/
3889 if (ins == ccode [0]) {
3890 g_assert (code32 [1] == ccode [1]);
3891 g_assert (code32 [3] == ccode [2]);
3892 g_assert (code32 [4] == ccode [3]);
3893 code32 [2] = (guint32)target;
3896 g_assert_not_reached ();
3897 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3905 guint8 *emit = (guint8*)ccode;
3906 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3908 ARM_BLX_REG (emit, ARMREG_IP);
3910 g_assert (code32 [-3] == ccode [0]);
3911 g_assert (code32 [-2] == ccode [1]);
3912 g_assert (code32 [0] == ccode [2]);
3914 code32 [-1] = (guint32)target;
3917 guint32 *tmp = ccode;
3918 guint8 *emit = (guint8*)tmp;
3919 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3920 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3921 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3922 ARM_BX (emit, ARMREG_IP);
3923 if (ins == ccode [2]) {
3924 g_assert_not_reached (); // should be -2 ...
3925 code32 [-1] = (guint32)target;
3928 if (ins == ccode [0]) {
3929 /* handles both thunk jump code and the far call sequence */
3930 code32 [2] = (guint32)target;
3933 g_assert_not_reached ();
3935 // g_print ("patched with 0x%08x\n", ins);
3940 arm_patch (guchar *code, const guchar *target)
3942 arm_patch_general (NULL, code, target, NULL);
3946 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3947 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3948 * to be used with the emit macros.
3949 * Return -1 otherwise.
3952 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3955 for (i = 0; i < 31; i+= 2) {
3956 res = (val << (32 - i)) | (val >> i);
3959 *rot_amount = i? 32 - i: 0;
3966 * Emits in code a sequence of instructions that load the value 'val'
3967 * into the dreg register. Uses at most 4 instructions.
3970 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3972 int imm8, rot_amount;
3974 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3975 /* skip the constant pool */
3981 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3982 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3983 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3984 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3987 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3989 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3993 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3995 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3997 if (val & 0xFF0000) {
3998 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4000 if (val & 0xFF000000) {
4001 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4003 } else if (val & 0xFF00) {
4004 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4005 if (val & 0xFF0000) {
4006 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4008 if (val & 0xFF000000) {
4009 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4011 } else if (val & 0xFF0000) {
4012 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4013 if (val & 0xFF000000) {
4014 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4017 //g_assert_not_reached ();
4023 mono_arm_thumb_supported (void)
4025 return thumb_supported;
4031 * emit_load_volatile_arguments:
4033 * Load volatile arguments from the stack to the original input registers.
4034 * Required before a tail call.
4037 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
4039 MonoMethod *method = cfg->method;
4040 MonoMethodSignature *sig;
4045 /* FIXME: Generate intermediate code instead */
4047 sig = mono_method_signature (method);
4049 /* This is the opposite of the code in emit_prolog */
4053 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
4055 if (cinfo->vtype_retaddr) {
4056 ArgInfo *ainfo = &cinfo->ret;
4057 inst = cfg->vret_addr;
4058 g_assert (arm_is_imm12 (inst->inst_offset));
4059 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4061 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4062 ArgInfo *ainfo = cinfo->args + i;
4063 inst = cfg->args [pos];
4065 if (cfg->verbose_level > 2)
4066 g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
4067 if (inst->opcode == OP_REGVAR) {
4068 if (ainfo->storage == RegTypeGeneral)
4069 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
4070 else if (ainfo->storage == RegTypeFP) {
4071 g_assert_not_reached ();
4072 } else if (ainfo->storage == RegTypeBase) {
4076 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
4077 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4079 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4080 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
4084 g_assert_not_reached ();
4086 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
4087 switch (ainfo->size) {
4094 g_assert (arm_is_imm12 (inst->inst_offset));
4095 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4096 g_assert (arm_is_imm12 (inst->inst_offset + 4));
4097 ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
4100 if (arm_is_imm12 (inst->inst_offset)) {
4101 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4103 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4104 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4108 } else if (ainfo->storage == RegTypeBaseGen) {
4111 } else if (ainfo->storage == RegTypeBase) {
4113 } else if (ainfo->storage == RegTypeFP) {
4114 g_assert_not_reached ();
4115 } else if (ainfo->storage == RegTypeStructByVal) {
4116 int doffset = inst->inst_offset;
4120 if (mono_class_from_mono_type (inst->inst_vtype))
4121 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
4122 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
4123 if (arm_is_imm12 (doffset)) {
4124 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
4126 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
4127 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
4129 soffset += sizeof (gpointer);
4130 doffset += sizeof (gpointer);
4135 } else if (ainfo->storage == RegTypeStructByAddr) {
4150 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4155 guint8 *code = cfg->native_code + cfg->code_len;
4156 MonoInst *last_ins = NULL;
4157 guint last_offset = 0;
4159 int imm8, rot_amount;
4161 /* we don't align basic blocks of loops on arm */
4163 if (cfg->verbose_level > 2)
4164 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4166 cpos = bb->max_offset;
4168 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4169 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4170 //g_assert (!mono_compile_aot);
4173 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4174 /* this is not thread save, but good enough */
4175 /* fixme: howto handle overflows? */
4176 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4179 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4180 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4181 (gpointer)"mono_break");
4182 code = emit_call_seq (cfg, code);
4185 MONO_BB_FOR_EACH_INS (bb, ins) {
4186 offset = code - cfg->native_code;
4188 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4190 if (offset > (cfg->code_size - max_len - 16)) {
4191 cfg->code_size *= 2;
4192 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4193 code = cfg->native_code + offset;
4195 // if (ins->cil_code)
4196 // g_print ("cil code\n");
4197 mono_debug_record_line_number (cfg, ins, offset);
4199 switch (ins->opcode) {
4200 case OP_MEMORY_BARRIER:
4202 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4203 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4207 #ifdef HAVE_AEABI_READ_TP
4208 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4209 (gpointer)"__aeabi_read_tp");
4210 code = emit_call_seq (cfg, code);
4212 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
4214 g_assert_not_reached ();
4217 case OP_ATOMIC_EXCHANGE_I4:
4218 case OP_ATOMIC_CAS_I4:
4219 case OP_ATOMIC_ADD_I4: {
4223 g_assert (v7_supported);
4226 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4228 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4230 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4234 g_assert (cfg->arch.atomic_tmp_offset != -1);
4235 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4237 switch (ins->opcode) {
4238 case OP_ATOMIC_EXCHANGE_I4:
4240 ARM_DMB (code, ARM_DMB_SY);
4241 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4242 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4243 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4245 ARM_B_COND (code, ARMCOND_NE, 0);
4246 arm_patch (buf [1], buf [0]);
4248 case OP_ATOMIC_CAS_I4:
4249 ARM_DMB (code, ARM_DMB_SY);
4251 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4252 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4254 ARM_B_COND (code, ARMCOND_NE, 0);
4255 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4256 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4258 ARM_B_COND (code, ARMCOND_NE, 0);
4259 arm_patch (buf [2], buf [0]);
4260 arm_patch (buf [1], code);
4262 case OP_ATOMIC_ADD_I4:
4264 ARM_DMB (code, ARM_DMB_SY);
4265 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4266 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4267 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4268 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4270 ARM_B_COND (code, ARMCOND_NE, 0);
4271 arm_patch (buf [1], buf [0]);
4274 g_assert_not_reached ();
4277 ARM_DMB (code, ARM_DMB_SY);
4278 if (tmpreg != ins->dreg)
4279 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4280 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4283 case OP_ATOMIC_LOAD_I1:
4284 case OP_ATOMIC_LOAD_U1:
4285 case OP_ATOMIC_LOAD_I2:
4286 case OP_ATOMIC_LOAD_U2:
4287 case OP_ATOMIC_LOAD_I4:
4288 case OP_ATOMIC_LOAD_U4:
4289 case OP_ATOMIC_LOAD_R4:
4290 case OP_ATOMIC_LOAD_R8: {
4291 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4292 ARM_DMB (code, ARM_DMB_SY);
4294 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4296 switch (ins->opcode) {
4297 case OP_ATOMIC_LOAD_I1:
4298 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4300 case OP_ATOMIC_LOAD_U1:
4301 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4303 case OP_ATOMIC_LOAD_I2:
4304 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4306 case OP_ATOMIC_LOAD_U2:
4307 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4309 case OP_ATOMIC_LOAD_I4:
4310 case OP_ATOMIC_LOAD_U4:
4311 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4313 case OP_ATOMIC_LOAD_R4:
4314 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4315 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4316 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4317 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4318 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4320 case OP_ATOMIC_LOAD_R8:
4321 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4322 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4326 ARM_DMB (code, ARM_DMB_SY);
4329 case OP_ATOMIC_STORE_I1:
4330 case OP_ATOMIC_STORE_U1:
4331 case OP_ATOMIC_STORE_I2:
4332 case OP_ATOMIC_STORE_U2:
4333 case OP_ATOMIC_STORE_I4:
4334 case OP_ATOMIC_STORE_U4:
4335 case OP_ATOMIC_STORE_R4:
4336 case OP_ATOMIC_STORE_R8: {
4337 ARM_DMB (code, ARM_DMB_SY);
4339 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4341 switch (ins->opcode) {
4342 case OP_ATOMIC_STORE_I1:
4343 case OP_ATOMIC_STORE_U1:
4344 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4346 case OP_ATOMIC_STORE_I2:
4347 case OP_ATOMIC_STORE_U2:
4348 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4350 case OP_ATOMIC_STORE_I4:
4351 case OP_ATOMIC_STORE_U4:
4352 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4354 case OP_ATOMIC_STORE_R4:
4355 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4356 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4357 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4358 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4359 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4361 case OP_ATOMIC_STORE_R8:
4362 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4363 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4367 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4368 ARM_DMB (code, ARM_DMB_SY);
4372 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4373 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4376 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4377 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4379 case OP_STOREI1_MEMBASE_IMM:
4380 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4381 g_assert (arm_is_imm12 (ins->inst_offset));
4382 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4384 case OP_STOREI2_MEMBASE_IMM:
4385 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4386 g_assert (arm_is_imm8 (ins->inst_offset));
4387 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4389 case OP_STORE_MEMBASE_IMM:
4390 case OP_STOREI4_MEMBASE_IMM:
4391 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4392 g_assert (arm_is_imm12 (ins->inst_offset));
4393 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4395 case OP_STOREI1_MEMBASE_REG:
4396 g_assert (arm_is_imm12 (ins->inst_offset));
4397 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4399 case OP_STOREI2_MEMBASE_REG:
4400 g_assert (arm_is_imm8 (ins->inst_offset));
4401 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4403 case OP_STORE_MEMBASE_REG:
4404 case OP_STOREI4_MEMBASE_REG:
4405 /* this case is special, since it happens for spill code after lowering has been called */
4406 if (arm_is_imm12 (ins->inst_offset)) {
4407 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4409 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4410 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4413 case OP_STOREI1_MEMINDEX:
4414 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4416 case OP_STOREI2_MEMINDEX:
4417 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4419 case OP_STORE_MEMINDEX:
4420 case OP_STOREI4_MEMINDEX:
4421 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4424 g_assert_not_reached ();
4426 case OP_LOAD_MEMINDEX:
4427 case OP_LOADI4_MEMINDEX:
4428 case OP_LOADU4_MEMINDEX:
4429 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4431 case OP_LOADI1_MEMINDEX:
4432 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4434 case OP_LOADU1_MEMINDEX:
4435 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4437 case OP_LOADI2_MEMINDEX:
4438 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4440 case OP_LOADU2_MEMINDEX:
4441 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4443 case OP_LOAD_MEMBASE:
4444 case OP_LOADI4_MEMBASE:
4445 case OP_LOADU4_MEMBASE:
4446 /* this case is special, since it happens for spill code after lowering has been called */
4447 if (arm_is_imm12 (ins->inst_offset)) {
4448 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4450 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4451 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4454 case OP_LOADI1_MEMBASE:
4455 g_assert (arm_is_imm8 (ins->inst_offset));
4456 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4458 case OP_LOADU1_MEMBASE:
4459 g_assert (arm_is_imm12 (ins->inst_offset));
4460 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4462 case OP_LOADU2_MEMBASE:
4463 g_assert (arm_is_imm8 (ins->inst_offset));
4464 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4466 case OP_LOADI2_MEMBASE:
4467 g_assert (arm_is_imm8 (ins->inst_offset));
4468 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4470 case OP_ICONV_TO_I1:
4471 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4472 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4474 case OP_ICONV_TO_I2:
4475 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4476 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4478 case OP_ICONV_TO_U1:
4479 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4481 case OP_ICONV_TO_U2:
4482 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4483 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4487 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4489 case OP_COMPARE_IMM:
4490 case OP_ICOMPARE_IMM:
4491 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4492 g_assert (imm8 >= 0);
4493 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4497 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4498 * So instead of emitting a trap, we emit a call a C function and place a
4501 //*(int*)code = 0xef9f0001;
4504 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4505 (gpointer)"mono_break");
4506 code = emit_call_seq (cfg, code);
4508 case OP_RELAXED_NOP:
4513 case OP_DUMMY_STORE:
4514 case OP_DUMMY_ICONST:
4515 case OP_DUMMY_R8CONST:
4516 case OP_NOT_REACHED:
4519 case OP_IL_SEQ_POINT:
4520 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4522 case OP_SEQ_POINT: {
4524 MonoInst *info_var = cfg->arch.seq_point_info_var;
4525 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4526 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
4527 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4528 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4530 int dreg = ARMREG_LR;
4532 if (cfg->soft_breakpoints) {
4533 g_assert (!cfg->compile_aot);
4537 * For AOT, we use one got slot per method, which will point to a
4538 * SeqPointInfo structure, containing all the information required
4539 * by the code below.
4541 if (cfg->compile_aot) {
4542 g_assert (info_var);
4543 g_assert (info_var->opcode == OP_REGOFFSET);
4544 g_assert (arm_is_imm12 (info_var->inst_offset));
4547 if (!cfg->soft_breakpoints) {
4549 * Read from the single stepping trigger page. This will cause a
4550 * SIGSEGV when single stepping is enabled.
4551 * We do this _before_ the breakpoint, so single stepping after
4552 * a breakpoint is hit will step to the next IL offset.
4554 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4557 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4558 if (cfg->soft_breakpoints) {
4559 /* Load the address of the sequence point trigger variable. */
4562 g_assert (var->opcode == OP_REGOFFSET);
4563 g_assert (arm_is_imm12 (var->inst_offset));
4564 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4566 /* Read the value and check whether it is non-zero. */
4567 ARM_LDR_IMM (code, dreg, dreg, 0);
4568 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4570 /* Load the address of the sequence point method. */
4571 var = ss_method_var;
4573 g_assert (var->opcode == OP_REGOFFSET);
4574 g_assert (arm_is_imm12 (var->inst_offset));
4575 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4577 /* Call it conditionally. */
4578 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4580 if (cfg->compile_aot) {
4581 /* Load the trigger page addr from the variable initialized in the prolog */
4582 var = ss_trigger_page_var;
4584 g_assert (var->opcode == OP_REGOFFSET);
4585 g_assert (arm_is_imm12 (var->inst_offset));
4586 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4588 #ifdef USE_JUMP_TABLES
4589 gpointer *jte = mono_jumptable_add_entry ();
4590 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4591 jte [0] = ss_trigger_page;
4593 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4595 *(int*)code = (int)ss_trigger_page;
4599 ARM_LDR_IMM (code, dreg, dreg, 0);
4603 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4605 if (cfg->soft_breakpoints) {
4606 /* Load the address of the breakpoint method into ip. */
4607 var = bp_method_var;
4609 g_assert (var->opcode == OP_REGOFFSET);
4610 g_assert (arm_is_imm12 (var->inst_offset));
4611 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4614 * A placeholder for a possible breakpoint inserted by
4615 * mono_arch_set_breakpoint ().
4618 } else if (cfg->compile_aot) {
4619 guint32 offset = code - cfg->native_code;
4622 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4623 /* Add the offset */
4624 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4625 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4626 if (arm_is_imm12 ((int)val)) {
4627 ARM_LDR_IMM (code, dreg, dreg, val);
4629 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4631 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4633 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4634 g_assert (!(val & 0xFF000000));
4636 ARM_LDR_IMM (code, dreg, dreg, 0);
4638 /* What is faster, a branch or a load ? */
4639 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4640 /* The breakpoint instruction */
4641 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4644 * A placeholder for a possible breakpoint inserted by
4645 * mono_arch_set_breakpoint ().
4647 for (i = 0; i < 4; ++i)
4654 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4657 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4661 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4664 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4665 g_assert (imm8 >= 0);
4666 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4670 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4671 g_assert (imm8 >= 0);
4672 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4676 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4677 g_assert (imm8 >= 0);
4678 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4681 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4682 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4684 case OP_IADD_OVF_UN:
4685 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4686 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4689 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4690 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4692 case OP_ISUB_OVF_UN:
4693 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4694 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4696 case OP_ADD_OVF_CARRY:
4697 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4698 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4700 case OP_ADD_OVF_UN_CARRY:
4701 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4702 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4704 case OP_SUB_OVF_CARRY:
4705 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4706 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4708 case OP_SUB_OVF_UN_CARRY:
4709 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4710 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4714 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4717 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4718 g_assert (imm8 >= 0);
4719 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4722 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4726 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4730 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4731 g_assert (imm8 >= 0);
4732 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4736 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4737 g_assert (imm8 >= 0);
4738 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4740 case OP_ARM_RSBS_IMM:
4741 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4742 g_assert (imm8 >= 0);
4743 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4745 case OP_ARM_RSC_IMM:
4746 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4747 g_assert (imm8 >= 0);
4748 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4751 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4755 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4756 g_assert (imm8 >= 0);
4757 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4760 g_assert (v7s_supported);
4761 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4764 g_assert (v7s_supported);
4765 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4768 g_assert (v7s_supported);
4769 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4770 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4773 g_assert (v7s_supported);
4774 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4775 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4779 g_assert_not_reached ();
4781 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4785 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4786 g_assert (imm8 >= 0);
4787 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4790 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4794 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4795 g_assert (imm8 >= 0);
4796 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4799 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4804 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4805 else if (ins->dreg != ins->sreg1)
4806 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4809 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4814 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4815 else if (ins->dreg != ins->sreg1)
4816 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4819 case OP_ISHR_UN_IMM:
4821 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4822 else if (ins->dreg != ins->sreg1)
4823 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4826 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4829 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4832 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4835 if (ins->dreg == ins->sreg2)
4836 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4838 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4841 g_assert_not_reached ();
4844 /* FIXME: handle ovf/ sreg2 != dreg */
4845 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4846 /* FIXME: MUL doesn't set the C/O flags on ARM */
4848 case OP_IMUL_OVF_UN:
4849 /* FIXME: handle ovf/ sreg2 != dreg */
4850 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4851 /* FIXME: MUL doesn't set the C/O flags on ARM */
4854 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4857 /* Load the GOT offset */
4858 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4859 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4861 *(gpointer*)code = NULL;
4863 /* Load the value from the GOT */
4864 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4866 case OP_OBJC_GET_SELECTOR:
4867 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4868 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4870 *(gpointer*)code = NULL;
4872 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4874 case OP_ICONV_TO_I4:
4875 case OP_ICONV_TO_U4:
4877 if (ins->dreg != ins->sreg1)
4878 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4881 int saved = ins->sreg2;
4882 if (ins->sreg2 == ARM_LSW_REG) {
4883 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4886 if (ins->sreg1 != ARM_LSW_REG)
4887 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4888 if (saved != ARM_MSW_REG)
4889 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4893 if (IS_VFP && ins->dreg != ins->sreg1)
4894 ARM_CPYD (code, ins->dreg, ins->sreg1);
4896 case OP_MOVE_F_TO_I4:
4897 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4898 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4899 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4900 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4902 case OP_MOVE_I4_TO_F:
4903 ARM_FMSR (code, ins->dreg, ins->sreg1);
4904 ARM_CVTS (code, ins->dreg, ins->dreg);
4906 case OP_FCONV_TO_R4:
4909 ARM_CVTD (code, ins->dreg, ins->sreg1);
4911 ARM_CVTD (code, ins->dreg, ins->sreg1);
4912 ARM_CVTS (code, ins->dreg, ins->dreg);
4918 * Keep in sync with mono_arch_emit_epilog
4920 g_assert (!cfg->method->save_lmf);
4922 code = emit_load_volatile_arguments (cfg, code);
4924 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4926 if (cfg->used_int_regs)
4927 ARM_POP (code, cfg->used_int_regs);
4928 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4930 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4932 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4933 if (cfg->compile_aot) {
4934 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4936 *(gpointer*)code = NULL;
4938 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4940 code = mono_arm_patchable_b (code, ARMCOND_AL);
4944 MonoCallInst *call = (MonoCallInst*)ins;
4947 * The stack looks like the following:
4948 * <caller argument area>
4951 * <callee argument area>
4952 * Need to copy the arguments from the callee argument area to
4953 * the caller argument area, and pop the frame.
4955 if (call->stack_usage) {
4956 int i, prev_sp_offset = 0;
4958 /* Compute size of saved registers restored below */
4960 prev_sp_offset = 2 * 4;
4962 prev_sp_offset = 1 * 4;
4963 for (i = 0; i < 16; ++i) {
4964 if (cfg->used_int_regs & (1 << i))
4965 prev_sp_offset += 4;
4968 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4970 /* Copy arguments on the stack to our argument area */
4971 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4972 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4973 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4978 * Keep in sync with mono_arch_emit_epilog
4980 g_assert (!cfg->method->save_lmf);
4982 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4984 if (cfg->used_int_regs)
4985 ARM_POP (code, cfg->used_int_regs);
4986 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4988 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4991 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4992 if (cfg->compile_aot) {
4993 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4995 *(gpointer*)code = NULL;
4997 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4999 code = mono_arm_patchable_b (code, ARMCOND_AL);
5004 /* ensure ins->sreg1 is not NULL */
5005 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5008 g_assert (cfg->sig_cookie < 128);
5009 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5010 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5020 call = (MonoCallInst*)ins;
5023 code = emit_float_args (cfg, call, code, &max_len, &offset);
5025 if (ins->flags & MONO_INST_HAS_METHOD)
5026 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5028 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5029 code = emit_call_seq (cfg, code);
5030 ins->flags |= MONO_INST_GC_CALLSITE;
5031 ins->backend.pc_offset = code - cfg->native_code;
5032 code = emit_move_return_value (cfg, ins, code);
5039 case OP_VOIDCALL_REG:
5042 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5044 code = emit_call_reg (code, ins->sreg1);
5045 ins->flags |= MONO_INST_GC_CALLSITE;
5046 ins->backend.pc_offset = code - cfg->native_code;
5047 code = emit_move_return_value (cfg, ins, code);
5049 case OP_FCALL_MEMBASE:
5050 case OP_RCALL_MEMBASE:
5051 case OP_LCALL_MEMBASE:
5052 case OP_VCALL_MEMBASE:
5053 case OP_VCALL2_MEMBASE:
5054 case OP_VOIDCALL_MEMBASE:
5055 case OP_CALL_MEMBASE: {
5056 gboolean imt_arg = FALSE;
5058 g_assert (ins->sreg1 != ARMREG_LR);
5059 call = (MonoCallInst*)ins;
5062 code = emit_float_args (cfg, call, code, &max_len, &offset);
5064 if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE)
5066 if (!arm_is_imm12 (ins->inst_offset))
5067 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5068 #ifdef USE_JUMP_TABLES
5074 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, LR_BIAS);
5076 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5078 if (!arm_is_imm12 (ins->inst_offset))
5079 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5081 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5084 * We can't embed the method in the code stream in PIC code, or
5086 * Instead, we put it in V5 in code emitted by
5087 * mono_arch_emit_imt_argument (), and embed NULL here to
5088 * signal the IMT thunk that the value is in V5.
5090 #ifdef USE_JUMP_TABLES
5091 /* In case of jumptables we always use value in V5. */
5094 if (call->dynamic_imt_arg)
5095 *((gpointer*)code) = NULL;
5097 *((gpointer*)code) = (gpointer)call->method;
5101 ins->flags |= MONO_INST_GC_CALLSITE;
5102 ins->backend.pc_offset = code - cfg->native_code;
5103 code = emit_move_return_value (cfg, ins, code);
5107 /* round the size to 8 bytes */
5108 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
5109 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
5110 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5111 /* memzero the area: dreg holds the size, sp is the pointer */
5112 if (ins->flags & MONO_INST_INIT) {
5113 guint8 *start_loop, *branch_to_cond;
5114 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5115 branch_to_cond = code;
5118 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5119 arm_patch (branch_to_cond, code);
5120 /* decrement by 4 and set flags */
5121 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5122 ARM_B_COND (code, ARMCOND_GE, 0);
5123 arm_patch (code - 4, start_loop);
5125 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5126 if (cfg->param_area)
5127 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5132 MonoInst *var = cfg->dyn_call_var;
5134 g_assert (var->opcode == OP_REGOFFSET);
5135 g_assert (arm_is_imm12 (var->inst_offset));
5137 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5138 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5140 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5142 /* Save args buffer */
5143 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5145 /* Set stack slots using R0 as scratch reg */
5146 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5147 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5148 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5149 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5152 /* Set argument registers */
5153 for (i = 0; i < PARAM_REGS; ++i)
5154 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5157 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5158 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5161 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5162 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5163 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5167 if (ins->sreg1 != ARMREG_R0)
5168 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5169 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5170 (gpointer)"mono_arch_throw_exception");
5171 code = emit_call_seq (cfg, code);
5175 if (ins->sreg1 != ARMREG_R0)
5176 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5177 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5178 (gpointer)"mono_arch_rethrow_exception");
5179 code = emit_call_seq (cfg, code);
5182 case OP_START_HANDLER: {
5183 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5186 /* Reserve a param area, see filter-stack.exe */
5187 if (cfg->param_area) {
5188 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5189 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5191 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5192 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5196 if (arm_is_imm12 (spvar->inst_offset)) {
5197 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5199 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5200 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5204 case OP_ENDFILTER: {
5205 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5208 /* Free the param area */
5209 if (cfg->param_area) {
5210 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5211 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5213 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5214 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5218 if (ins->sreg1 != ARMREG_R0)
5219 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5220 if (arm_is_imm12 (spvar->inst_offset)) {
5221 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5223 g_assert (ARMREG_IP != spvar->inst_basereg);
5224 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5225 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5227 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5230 case OP_ENDFINALLY: {
5231 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5234 /* Free the param area */
5235 if (cfg->param_area) {
5236 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5237 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5239 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5240 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5244 if (arm_is_imm12 (spvar->inst_offset)) {
5245 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5247 g_assert (ARMREG_IP != spvar->inst_basereg);
5248 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5249 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5251 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5254 case OP_CALL_HANDLER:
5255 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5256 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5257 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5260 if (ins->dreg != ARMREG_R0)
5261 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5265 ins->inst_c0 = code - cfg->native_code;
5268 /*if (ins->inst_target_bb->native_offset) {
5270 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5272 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5273 code = mono_arm_patchable_b (code, ARMCOND_AL);
5277 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5281 * In the normal case we have:
5282 * ldr pc, [pc, ins->sreg1 << 2]
5285 * ldr lr, [pc, ins->sreg1 << 2]
5287 * After follows the data.
5288 * FIXME: add aot support.
5290 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5291 #ifdef USE_JUMP_TABLES
5293 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5294 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5295 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5299 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5300 if (offset + max_len > (cfg->code_size - 16)) {
5301 cfg->code_size += max_len;
5302 cfg->code_size *= 2;
5303 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5304 code = cfg->native_code + offset;
5306 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5308 code += 4 * GPOINTER_TO_INT (ins->klass);
5313 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5314 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5318 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5319 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5323 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5324 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5328 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5329 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5333 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5334 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5337 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5338 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5341 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5342 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5345 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5346 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5349 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5350 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5353 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5354 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5356 case OP_COND_EXC_EQ:
5357 case OP_COND_EXC_NE_UN:
5358 case OP_COND_EXC_LT:
5359 case OP_COND_EXC_LT_UN:
5360 case OP_COND_EXC_GT:
5361 case OP_COND_EXC_GT_UN:
5362 case OP_COND_EXC_GE:
5363 case OP_COND_EXC_GE_UN:
5364 case OP_COND_EXC_LE:
5365 case OP_COND_EXC_LE_UN:
5366 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5368 case OP_COND_EXC_IEQ:
5369 case OP_COND_EXC_INE_UN:
5370 case OP_COND_EXC_ILT:
5371 case OP_COND_EXC_ILT_UN:
5372 case OP_COND_EXC_IGT:
5373 case OP_COND_EXC_IGT_UN:
5374 case OP_COND_EXC_IGE:
5375 case OP_COND_EXC_IGE_UN:
5376 case OP_COND_EXC_ILE:
5377 case OP_COND_EXC_ILE_UN:
5378 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5381 case OP_COND_EXC_IC:
5382 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5384 case OP_COND_EXC_OV:
5385 case OP_COND_EXC_IOV:
5386 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5388 case OP_COND_EXC_NC:
5389 case OP_COND_EXC_INC:
5390 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5392 case OP_COND_EXC_NO:
5393 case OP_COND_EXC_INO:
5394 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5406 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5409 /* floating point opcodes */
5411 if (cfg->compile_aot) {
5412 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5414 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5416 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5419 /* FIXME: we can optimize the imm load by dealing with part of
5420 * the displacement in LDFD (aligning to 512).
5422 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5423 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5427 if (cfg->compile_aot) {
5428 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5430 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5433 ARM_CVTS (code, ins->dreg, ins->dreg);
5435 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5436 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5438 ARM_CVTS (code, ins->dreg, ins->dreg);
5441 case OP_STORER8_MEMBASE_REG:
5442 /* This is generated by the local regalloc pass which runs after the lowering pass */
5443 if (!arm_is_fpimm8 (ins->inst_offset)) {
5444 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5445 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5446 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5448 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5451 case OP_LOADR8_MEMBASE:
5452 /* This is generated by the local regalloc pass which runs after the lowering pass */
5453 if (!arm_is_fpimm8 (ins->inst_offset)) {
5454 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5455 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5456 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5458 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5461 case OP_STORER4_MEMBASE_REG:
5462 g_assert (arm_is_fpimm8 (ins->inst_offset));
5464 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5466 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5467 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5468 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5469 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5472 case OP_LOADR4_MEMBASE:
5474 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5476 g_assert (arm_is_fpimm8 (ins->inst_offset));
5477 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5478 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5479 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5480 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5483 case OP_ICONV_TO_R_UN: {
5484 g_assert_not_reached ();
5487 case OP_ICONV_TO_R4:
5489 ARM_FMSR (code, ins->dreg, ins->sreg1);
5490 ARM_FSITOS (code, ins->dreg, ins->dreg);
5492 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5493 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5494 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5495 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5496 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5499 case OP_ICONV_TO_R8:
5500 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5501 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5502 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5503 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5507 MonoType *sig_ret = mini_type_get_underlying_type (NULL, mono_method_signature (cfg->method)->ret);
5508 if (sig_ret->type == MONO_TYPE_R4) {
5510 g_assert (!IS_HARD_FLOAT);
5511 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5513 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5516 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5520 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5522 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5526 case OP_FCONV_TO_I1:
5527 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5529 case OP_FCONV_TO_U1:
5530 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5532 case OP_FCONV_TO_I2:
5533 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5535 case OP_FCONV_TO_U2:
5536 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5538 case OP_FCONV_TO_I4:
5540 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5542 case OP_FCONV_TO_U4:
5544 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5546 case OP_FCONV_TO_I8:
5547 case OP_FCONV_TO_U8:
5548 g_assert_not_reached ();
5549 /* Implemented as helper calls */
5551 case OP_LCONV_TO_R_UN:
5552 g_assert_not_reached ();
5553 /* Implemented as helper calls */
5555 case OP_LCONV_TO_OVF_I4_2: {
5556 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5558 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5561 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5562 high_bit_not_set = code;
5563 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5565 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5566 valid_negative = code;
5567 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5568 invalid_negative = code;
5569 ARM_B_COND (code, ARMCOND_AL, 0);
5571 arm_patch (high_bit_not_set, code);
5573 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5574 valid_positive = code;
5575 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5577 arm_patch (invalid_negative, code);
5578 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5580 arm_patch (valid_negative, code);
5581 arm_patch (valid_positive, code);
5583 if (ins->dreg != ins->sreg1)
5584 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5588 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5591 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5594 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5597 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5600 ARM_NEGD (code, ins->dreg, ins->sreg1);
5604 g_assert_not_reached ();
5608 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5614 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5619 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5622 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5623 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5627 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5630 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5631 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5635 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5638 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5639 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5640 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5644 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5647 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5648 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5652 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5655 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5656 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5657 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5661 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5664 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5665 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5669 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5672 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5673 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5677 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5680 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5681 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5684 /* ARM FPA flags table:
5685 * N Less than ARMCOND_MI
5686 * Z Equal ARMCOND_EQ
5687 * C Greater Than or Equal ARMCOND_CS
5688 * V Unordered ARMCOND_VS
5691 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5694 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5697 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5700 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5701 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5707 g_assert_not_reached ();
5711 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5713 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5714 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5715 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5719 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5720 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5725 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5726 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5728 #ifdef USE_JUMP_TABLES
5730 gpointer *jte = mono_jumptable_add_entries (2);
5731 jte [0] = GUINT_TO_POINTER (0xffffffff);
5732 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5733 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5734 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5737 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5738 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5740 *(guint32*)code = 0xffffffff;
5742 *(guint32*)code = 0x7fefffff;
5745 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5747 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5748 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5750 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5751 ARM_CPYD (code, ins->dreg, ins->sreg1);
5753 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5754 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5759 case OP_RCONV_TO_I1:
5760 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5762 case OP_RCONV_TO_U1:
5763 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5765 case OP_RCONV_TO_I2:
5766 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5768 case OP_RCONV_TO_U2:
5769 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5771 case OP_RCONV_TO_I4:
5772 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5774 case OP_RCONV_TO_U4:
5775 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5777 case OP_RCONV_TO_R4:
5779 if (ins->dreg != ins->sreg1)
5780 ARM_CPYS (code, ins->dreg, ins->sreg1);
5782 case OP_RCONV_TO_R8:
5784 ARM_CVTS (code, ins->dreg, ins->sreg1);
5787 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5790 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5793 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5796 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5799 ARM_NEGS (code, ins->dreg, ins->sreg1);
5803 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5806 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5807 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5811 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5814 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5815 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5819 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5822 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5823 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5824 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5828 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5831 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5832 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5836 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5839 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5840 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5841 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5845 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5848 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5849 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5853 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5856 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5857 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5861 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5864 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5865 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5868 case OP_GC_LIVENESS_DEF:
5869 case OP_GC_LIVENESS_USE:
5870 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5871 ins->backend.pc_offset = code - cfg->native_code;
5873 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5874 ins->backend.pc_offset = code - cfg->native_code;
5875 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5879 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5880 g_assert_not_reached ();
5883 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5884 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5885 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5886 g_assert_not_reached ();
5892 last_offset = offset;
5895 cfg->code_len = code - cfg->native_code;
5898 #endif /* DISABLE_JIT */
5900 #ifdef HAVE_AEABI_READ_TP
5901 void __aeabi_read_tp (void);
5905 mono_arch_register_lowlevel_calls (void)
5907 /* The signature doesn't matter */
5908 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5909 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5911 #ifndef MONO_CROSS_COMPILE
5912 #ifdef HAVE_AEABI_READ_TP
5913 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
5918 #define patch_lis_ori(ip,val) do {\
5919 guint16 *__lis_ori = (guint16*)(ip); \
5920 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5921 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5925 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5927 MonoJumpInfo *patch_info;
5928 gboolean compile_aot = !run_cctors;
5930 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5931 unsigned char *ip = patch_info->ip.i + code;
5932 const unsigned char *target;
5934 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
5935 #ifdef USE_JUMP_TABLES
5936 gpointer *jt = mono_jumptable_get_entry (ip);
5938 gpointer *jt = (gpointer*)(ip + 8);
5941 /* jt is the inlined jump table, 2 instructions after ip
5942 * In the normal case we store the absolute addresses,
5943 * otherwise the displacements.
5945 for (i = 0; i < patch_info->data.table->table_size; i++)
5946 jt [i] = code + (int)patch_info->data.table->table [i];
5951 switch (patch_info->type) {
5952 case MONO_PATCH_INFO_BB:
5953 case MONO_PATCH_INFO_LABEL:
5956 /* No need to patch these */
5961 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5963 switch (patch_info->type) {
5964 case MONO_PATCH_INFO_IP:
5965 g_assert_not_reached ();
5966 patch_lis_ori (ip, ip);
5968 case MONO_PATCH_INFO_METHOD_REL:
5969 g_assert_not_reached ();
5970 *((gpointer *)(ip)) = code + patch_info->data.offset;
5972 case MONO_PATCH_INFO_METHODCONST:
5973 case MONO_PATCH_INFO_CLASS:
5974 case MONO_PATCH_INFO_IMAGE:
5975 case MONO_PATCH_INFO_FIELD:
5976 case MONO_PATCH_INFO_VTABLE:
5977 case MONO_PATCH_INFO_IID:
5978 case MONO_PATCH_INFO_SFLDA:
5979 case MONO_PATCH_INFO_LDSTR:
5980 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5981 case MONO_PATCH_INFO_LDTOKEN:
5982 g_assert_not_reached ();
5983 /* from OP_AOTCONST : lis + ori */
5984 patch_lis_ori (ip, target);
5986 case MONO_PATCH_INFO_R4:
5987 case MONO_PATCH_INFO_R8:
5988 g_assert_not_reached ();
5989 *((gconstpointer *)(ip + 2)) = patch_info->data.target;
5991 case MONO_PATCH_INFO_EXC_NAME:
5992 g_assert_not_reached ();
5993 *((gconstpointer *)(ip + 1)) = patch_info->data.name;
5995 case MONO_PATCH_INFO_NONE:
5996 case MONO_PATCH_INFO_BB_OVF:
5997 case MONO_PATCH_INFO_EXC_OVF:
5998 /* everything is dealt with at epilog output time */
6003 arm_patch_general (domain, ip, target, dyn_code_mp);
6010 * Stack frame layout:
6012 * ------------------- fp
6013 * MonoLMF structure or saved registers
6014 * -------------------
6016 * -------------------
6018 * -------------------
6019 * optional 8 bytes for tracing
6020 * -------------------
6021 * param area size is cfg->param_area
6022 * ------------------- sp
6025 mono_arch_emit_prolog (MonoCompile *cfg)
6027 MonoMethod *method = cfg->method;
6029 MonoMethodSignature *sig;
6031 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount;
6036 int prev_sp_offset, reg_offset;
6038 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6041 sig = mono_method_signature (method);
6042 cfg->code_size = 256 + sig->param_count * 64;
6043 code = cfg->native_code = g_malloc (cfg->code_size);
6045 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6047 alloc_size = cfg->stack_offset;
6053 * The iphone uses R7 as the frame pointer, and it points at the saved
6058 * We can't use r7 as a frame pointer since it points into the middle of
6059 * the frame, so we keep using our own frame pointer.
6060 * FIXME: Optimize this.
6062 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6063 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6064 prev_sp_offset += 8; /* r7 and lr */
6065 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6066 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6069 if (!method->save_lmf) {
6071 /* No need to push LR again */
6072 if (cfg->used_int_regs)
6073 ARM_PUSH (code, cfg->used_int_regs);
6075 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6076 prev_sp_offset += 4;
6078 for (i = 0; i < 16; ++i) {
6079 if (cfg->used_int_regs & (1 << i))
6080 prev_sp_offset += 4;
6082 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6084 for (i = 0; i < 16; ++i) {
6085 if ((cfg->used_int_regs & (1 << i))) {
6086 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6087 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6092 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6093 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6095 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6096 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6099 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6100 ARM_PUSH (code, 0x5ff0);
6101 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6102 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6104 for (i = 0; i < 16; ++i) {
6105 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6106 /* The original r7 is saved at the start */
6107 if (!(iphone_abi && i == ARMREG_R7))
6108 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6112 g_assert (reg_offset == 4 * 10);
6113 pos += sizeof (MonoLMF) - (4 * 10);
6117 orig_alloc_size = alloc_size;
6118 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6119 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6120 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6121 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6124 /* the stack used in the pushed regs */
6125 if (prev_sp_offset & 4)
6127 cfg->stack_usage = alloc_size;
6129 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6130 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6132 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6133 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6135 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6137 if (cfg->frame_reg != ARMREG_SP) {
6138 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6139 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6141 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6142 prev_sp_offset += alloc_size;
6144 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6145 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6147 /* compute max_offset in order to use short forward jumps
6148 * we could skip do it on arm because the immediate displacement
6149 * for jumps is large enough, it may be useful later for constant pools
6152 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6153 MonoInst *ins = bb->code;
6154 bb->max_offset = max_offset;
6156 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6159 MONO_BB_FOR_EACH_INS (bb, ins)
6160 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6163 /* store runtime generic context */
6164 if (cfg->rgctx_var) {
6165 MonoInst *ins = cfg->rgctx_var;
6167 g_assert (ins->opcode == OP_REGOFFSET);
6169 if (arm_is_imm12 (ins->inst_offset)) {
6170 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6172 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6173 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6177 /* load arguments allocated to register from the stack */
6180 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
6182 if (cinfo->vtype_retaddr) {
6183 ArgInfo *ainfo = &cinfo->ret;
6184 inst = cfg->vret_addr;
6185 g_assert (arm_is_imm12 (inst->inst_offset));
6186 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6189 if (sig->call_convention == MONO_CALL_VARARG) {
6190 ArgInfo *cookie = &cinfo->sig_cookie;
6192 /* Save the sig cookie address */
6193 g_assert (cookie->storage == RegTypeBase);
6195 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6196 g_assert (arm_is_imm12 (cfg->sig_cookie));
6197 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6198 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6201 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6202 ArgInfo *ainfo = cinfo->args + i;
6203 inst = cfg->args [pos];
6205 if (cfg->verbose_level > 2)
6206 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6207 if (inst->opcode == OP_REGVAR) {
6208 if (ainfo->storage == RegTypeGeneral)
6209 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6210 else if (ainfo->storage == RegTypeFP) {
6211 g_assert_not_reached ();
6212 } else if (ainfo->storage == RegTypeBase) {
6213 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6214 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6216 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6217 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6220 g_assert_not_reached ();
6222 if (cfg->verbose_level > 2)
6223 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6225 /* the argument should be put on the stack: FIXME handle size != word */
6226 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeGSharedVtInReg) {
6227 switch (ainfo->size) {
6229 if (arm_is_imm12 (inst->inst_offset))
6230 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6232 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6233 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6237 if (arm_is_imm8 (inst->inst_offset)) {
6238 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6240 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6241 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6245 if (arm_is_imm12 (inst->inst_offset)) {
6246 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6248 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6249 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6251 if (arm_is_imm12 (inst->inst_offset + 4)) {
6252 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6254 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6255 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6259 if (arm_is_imm12 (inst->inst_offset)) {
6260 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6262 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6263 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6267 } else if (ainfo->storage == RegTypeBaseGen) {
6268 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6269 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6271 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6272 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6274 if (arm_is_imm12 (inst->inst_offset + 4)) {
6275 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6276 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6278 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6279 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6280 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6281 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6283 } else if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeGSharedVtOnStack) {
6284 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6285 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6287 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6288 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6291 switch (ainfo->size) {
6293 if (arm_is_imm8 (inst->inst_offset)) {
6294 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6296 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6297 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6301 if (arm_is_imm8 (inst->inst_offset)) {
6302 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6304 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6305 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6309 if (arm_is_imm12 (inst->inst_offset)) {
6310 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6312 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6313 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6315 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6316 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6318 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6319 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6321 if (arm_is_imm12 (inst->inst_offset + 4)) {
6322 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6324 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6325 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6329 if (arm_is_imm12 (inst->inst_offset)) {
6330 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6332 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6333 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6337 } else if (ainfo->storage == RegTypeFP) {
6338 int imm8, rot_amount;
6340 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6341 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6342 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6344 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6346 if (ainfo->size == 8)
6347 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6349 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6350 } else if (ainfo->storage == RegTypeStructByVal) {
6351 int doffset = inst->inst_offset;
6355 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
6356 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6357 if (arm_is_imm12 (doffset)) {
6358 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6360 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6361 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6363 soffset += sizeof (gpointer);
6364 doffset += sizeof (gpointer);
6366 if (ainfo->vtsize) {
6367 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6368 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6369 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6371 } else if (ainfo->storage == RegTypeStructByAddr) {
6372 g_assert_not_reached ();
6373 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6374 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6376 g_assert_not_reached ();
6381 if (method->save_lmf)
6382 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6385 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6387 if (cfg->arch.seq_point_info_var) {
6388 MonoInst *ins = cfg->arch.seq_point_info_var;
6390 /* Initialize the variable from a GOT slot */
6391 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6392 #ifdef USE_JUMP_TABLES
6394 gpointer *jte = mono_jumptable_add_entry ();
6395 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6396 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6398 /** XXX: is it correct? */
6400 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6402 *(gpointer*)code = NULL;
6405 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6407 g_assert (ins->opcode == OP_REGOFFSET);
6409 if (arm_is_imm12 (ins->inst_offset)) {
6410 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6412 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6413 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6417 /* Initialize ss_trigger_page_var */
6418 if (!cfg->soft_breakpoints) {
6419 MonoInst *info_var = cfg->arch.seq_point_info_var;
6420 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6421 int dreg = ARMREG_LR;
6424 g_assert (info_var->opcode == OP_REGOFFSET);
6425 g_assert (arm_is_imm12 (info_var->inst_offset));
6427 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6428 /* Load the trigger page addr */
6429 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6430 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6434 if (cfg->arch.seq_point_read_var) {
6435 MonoInst *read_ins = cfg->arch.seq_point_read_var;
6436 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6437 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6438 #ifdef USE_JUMP_TABLES
6441 g_assert (read_ins->opcode == OP_REGOFFSET);
6442 g_assert (arm_is_imm12 (read_ins->inst_offset));
6443 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6444 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6445 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6446 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6448 #ifdef USE_JUMP_TABLES
6449 jte = mono_jumptable_add_entries (3);
6450 jte [0] = (gpointer)&ss_trigger_var;
6451 jte [1] = single_step_func_wrapper;
6452 jte [2] = breakpoint_func_wrapper;
6453 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6455 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6457 *(volatile int **)code = &ss_trigger_var;
6459 *(gpointer*)code = single_step_func_wrapper;
6461 *(gpointer*)code = breakpoint_func_wrapper;
6465 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6466 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
6467 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6468 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6469 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
6470 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6473 cfg->code_len = code - cfg->native_code;
6474 g_assert (cfg->code_len < cfg->code_size);
6481 mono_arch_emit_epilog (MonoCompile *cfg)
6483 MonoMethod *method = cfg->method;
6484 int pos, i, rot_amount;
6485 int max_epilog_size = 16 + 20*4;
6489 if (cfg->method->save_lmf)
6490 max_epilog_size += 128;
6492 if (mono_jit_trace_calls != NULL)
6493 max_epilog_size += 50;
6495 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6496 max_epilog_size += 50;
6498 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6499 cfg->code_size *= 2;
6500 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6501 cfg->stat_code_reallocs++;
6505 * Keep in sync with OP_JMP
6507 code = cfg->native_code + cfg->code_len;
6509 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6510 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6514 /* Load returned vtypes into registers if needed */
6515 cinfo = cfg->arch.cinfo;
6516 if (cinfo->ret.storage == RegTypeStructByVal) {
6517 MonoInst *ins = cfg->ret;
6519 if (arm_is_imm12 (ins->inst_offset)) {
6520 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6522 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6523 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6527 if (method->save_lmf) {
6528 int lmf_offset, reg, sp_adj, regmask;
6529 /* all but r0-r3, sp and pc */
6530 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6533 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6535 /* This points to r4 inside MonoLMF->iregs */
6536 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6538 regmask = 0x9ff0; /* restore lr to pc */
6539 /* Skip caller saved registers not used by the method */
6540 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6541 regmask &= ~(1 << reg);
6546 /* Restored later */
6547 regmask &= ~(1 << ARMREG_PC);
6548 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6549 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6551 ARM_POP (code, regmask);
6553 /* Restore saved r7, restore LR to PC */
6554 /* Skip lr from the lmf */
6555 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6556 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6559 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6560 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6562 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6563 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6567 /* Restore saved gregs */
6568 if (cfg->used_int_regs)
6569 ARM_POP (code, cfg->used_int_regs);
6570 /* Restore saved r7, restore LR to PC */
6571 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6573 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6577 cfg->code_len = code - cfg->native_code;
6579 g_assert (cfg->code_len < cfg->code_size);
6584 mono_arch_emit_exceptions (MonoCompile *cfg)
6586 MonoJumpInfo *patch_info;
6589 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6590 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6591 int max_epilog_size = 50;
6593 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6594 exc_throw_pos [i] = NULL;
6595 exc_throw_found [i] = 0;
6598 /* count the number of exception infos */
6601 * make sure we have enough space for exceptions
6603 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6604 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6605 i = mini_exception_id_by_name (patch_info->data.target);
6606 if (!exc_throw_found [i]) {
6607 max_epilog_size += 32;
6608 exc_throw_found [i] = TRUE;
6613 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6614 cfg->code_size *= 2;
6615 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6616 cfg->stat_code_reallocs++;
6619 code = cfg->native_code + cfg->code_len;
6621 /* add code to raise exceptions */
6622 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6623 switch (patch_info->type) {
6624 case MONO_PATCH_INFO_EXC: {
6625 MonoClass *exc_class;
6626 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6628 i = mini_exception_id_by_name (patch_info->data.target);
6629 if (exc_throw_pos [i]) {
6630 arm_patch (ip, exc_throw_pos [i]);
6631 patch_info->type = MONO_PATCH_INFO_NONE;
6634 exc_throw_pos [i] = code;
6636 arm_patch (ip, code);
6638 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6639 g_assert (exc_class);
6641 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6642 #ifdef USE_JUMP_TABLES
6644 gpointer *jte = mono_jumptable_add_entries (2);
6645 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6646 patch_info->data.name = "mono_arch_throw_corlib_exception";
6647 patch_info->ip.i = code - cfg->native_code;
6648 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6649 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6650 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6651 ARM_BLX_REG (code, ARMREG_IP);
6652 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6655 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6656 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6657 patch_info->data.name = "mono_arch_throw_corlib_exception";
6658 patch_info->ip.i = code - cfg->native_code;
6660 *(guint32*)(gpointer)code = exc_class->type_token;
6671 cfg->code_len = code - cfg->native_code;
6673 g_assert (cfg->code_len < cfg->code_size);
6677 #endif /* #ifndef DISABLE_JIT */
6680 mono_arch_finish_init (void)
6685 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6690 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6697 mono_arch_print_tree (MonoInst *tree, int arity)
6707 mono_arch_get_patch_offset (guint8 *code)
6714 mono_arch_flush_register_windows (void)
6721 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
6723 int method_reg = mono_alloc_ireg (cfg);
6724 #ifdef USE_JUMP_TABLES
6725 int use_jumptables = TRUE;
6727 int use_jumptables = FALSE;
6730 if (cfg->compile_aot) {
6733 call->dynamic_imt_arg = TRUE;
6736 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, method_reg, imt_arg->dreg);
6738 MONO_INST_NEW (cfg, ins, OP_AOTCONST);
6739 ins->dreg = method_reg;
6740 ins->inst_p0 = call->method;
6741 ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
6742 MONO_ADD_INS (cfg->cbb, ins);
6744 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
6745 } else if (cfg->generic_context || imt_arg || mono_use_llvm || use_jumptables) {
6746 /* Always pass in a register for simplicity */
6747 call->dynamic_imt_arg = TRUE;
6749 cfg->uses_rgctx_reg = TRUE;
6752 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, method_reg, imt_arg->dreg);
6756 MONO_INST_NEW (cfg, ins, OP_PCONST);
6757 ins->inst_p0 = call->method;
6758 ins->dreg = method_reg;
6759 MONO_ADD_INS (cfg->cbb, ins);
6762 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
6766 #endif /* DISABLE_JIT */
6769 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6771 #ifdef USE_JUMP_TABLES
6772 return (MonoMethod*)regs [ARMREG_V5];
6775 guint32 *code_ptr = (guint32*)code;
6777 method = GUINT_TO_POINTER (code_ptr [1]);
6781 return (MonoMethod*)regs [ARMREG_V5];
6783 /* The IMT value is stored in the code stream right after the LDC instruction. */
6784 /* This is no longer true for the gsharedvt_in trampoline */
6786 if (!IS_LDR_PC (code_ptr [0])) {
6787 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
6788 g_assert (IS_LDR_PC (code_ptr [0]));
6792 /* This is AOTed code, or the gsharedvt trampoline, the IMT method is in V5 */
6793 return (MonoMethod*)regs [ARMREG_V5];
6795 return (MonoMethod*) method;
6800 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6802 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6805 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6806 #define BASE_SIZE (6 * 4)
6807 #define BSEARCH_ENTRY_SIZE (4 * 4)
6808 #define CMP_SIZE (3 * 4)
6809 #define BRANCH_SIZE (1 * 4)
6810 #define CALL_SIZE (2 * 4)
6811 #define WMC_SIZE (8 * 4)
6812 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6814 #ifdef USE_JUMP_TABLES
6816 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6818 g_assert (base [index] == NULL);
6819 base [index] = value;
6822 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6824 if (arm_is_imm12 (jti * 4)) {
6825 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6827 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6828 if ((jti * 4) >> 16)
6829 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6830 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6836 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6838 guint32 delta = DISTANCE (target, code);
6840 g_assert (delta >= 0 && delta <= 0xFFF);
6841 *target = *target | delta;
6847 #ifdef ENABLE_WRONG_METHOD_CHECK
6849 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6851 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6857 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6858 gpointer fail_tramp)
6861 arminstr_t *code, *start;
6862 #ifdef USE_JUMP_TABLES
6865 gboolean large_offsets = FALSE;
6866 guint32 **constant_pool_starts;
6867 arminstr_t *vtable_target = NULL;
6868 int extra_space = 0;
6870 #ifdef ENABLE_WRONG_METHOD_CHECK
6875 #ifdef USE_JUMP_TABLES
6876 for (i = 0; i < count; ++i) {
6877 MonoIMTCheckItem *item = imt_entries [i];
6878 item->chunk_size += 4 * 16;
6879 if (!item->is_equals)
6880 imt_entries [item->check_target_idx]->compare_done = TRUE;
6881 size += item->chunk_size;
6884 constant_pool_starts = g_new0 (guint32*, count);
6886 for (i = 0; i < count; ++i) {
6887 MonoIMTCheckItem *item = imt_entries [i];
6888 if (item->is_equals) {
6889 gboolean fail_case = !item->check_target_idx && fail_tramp;
6891 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6892 item->chunk_size += 32;
6893 large_offsets = TRUE;
6896 if (item->check_target_idx || fail_case) {
6897 if (!item->compare_done || fail_case)
6898 item->chunk_size += CMP_SIZE;
6899 item->chunk_size += BRANCH_SIZE;
6901 #ifdef ENABLE_WRONG_METHOD_CHECK
6902 item->chunk_size += WMC_SIZE;
6906 item->chunk_size += 16;
6907 large_offsets = TRUE;
6909 item->chunk_size += CALL_SIZE;
6911 item->chunk_size += BSEARCH_ENTRY_SIZE;
6912 imt_entries [item->check_target_idx]->compare_done = TRUE;
6914 size += item->chunk_size;
6918 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6922 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6924 code = mono_domain_code_reserve (domain, size);
6928 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6929 for (i = 0; i < count; ++i) {
6930 MonoIMTCheckItem *item = imt_entries [i];
6931 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6935 #ifdef USE_JUMP_TABLES
6936 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6937 /* If jumptables we always pass the IMT method in R5 */
6938 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6939 #define VTABLE_JTI 0
6940 #define IMT_METHOD_OFFSET 0
6941 #define TARGET_CODE_OFFSET 1
6942 #define JUMP_CODE_OFFSET 2
6943 #define RECORDS_PER_ENTRY 3
6944 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
6945 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
6946 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
6948 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
6949 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
6950 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
6951 set_jumptable_element (jte, VTABLE_JTI, vtable);
6954 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6956 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6957 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6958 vtable_target = code;
6959 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6961 if (mono_use_llvm) {
6962 /* LLVM always passes the IMT method in R5 */
6963 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6965 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
6966 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
6967 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
6971 for (i = 0; i < count; ++i) {
6972 MonoIMTCheckItem *item = imt_entries [i];
6973 #ifdef USE_JUMP_TABLES
6974 guint32 imt_method_jti = 0, target_code_jti = 0;
6976 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6978 gint32 vtable_offset;
6980 item->code_target = (guint8*)code;
6982 if (item->is_equals) {
6983 gboolean fail_case = !item->check_target_idx && fail_tramp;
6985 if (item->check_target_idx || fail_case) {
6986 if (!item->compare_done || fail_case) {
6987 #ifdef USE_JUMP_TABLES
6988 imt_method_jti = IMT_METHOD_JTI (i);
6989 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
6992 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6994 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6996 #ifdef USE_JUMP_TABLES
6997 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
6998 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
6999 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7001 item->jmp_code = (guint8*)code;
7002 ARM_B_COND (code, ARMCOND_NE, 0);
7005 /*Enable the commented code to assert on wrong method*/
7006 #ifdef ENABLE_WRONG_METHOD_CHECK
7007 #ifdef USE_JUMP_TABLES
7008 imt_method_jti = IMT_METHOD_JTI (i);
7009 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7012 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7014 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7016 ARM_B_COND (code, ARMCOND_EQ, 0);
7018 /* Define this if your system is so bad that gdb is failing. */
7019 #ifdef BROKEN_DEV_ENV
7020 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7022 arm_patch (code - 1, mini_dump_bad_imt);
7026 arm_patch (cond, code);
7030 if (item->has_target_code) {
7031 /* Load target address */
7032 #ifdef USE_JUMP_TABLES
7033 target_code_jti = TARGET_CODE_JTI (i);
7034 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7035 /* Restore registers */
7036 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7038 ARM_BX (code, ARMREG_R1);
7039 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7041 target_code_ins = code;
7042 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7043 /* Save it to the fourth slot */
7044 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7045 /* Restore registers and branch */
7046 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7048 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7051 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7052 if (!arm_is_imm12 (vtable_offset)) {
7054 * We need to branch to a computed address but we don't have
7055 * a free register to store it, since IP must contain the
7056 * vtable address. So we push the two values to the stack, and
7057 * load them both using LDM.
7059 /* Compute target address */
7060 #ifdef USE_JUMP_TABLES
7061 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7062 if (vtable_offset >> 16)
7063 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7064 /* IP had vtable base. */
7065 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7066 /* Restore registers and branch */
7067 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7068 ARM_BX (code, ARMREG_IP);
7070 vtable_offset_ins = code;
7071 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7072 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7073 /* Save it to the fourth slot */
7074 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7075 /* Restore registers and branch */
7076 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7078 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7081 #ifdef USE_JUMP_TABLES
7082 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7083 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7084 ARM_BX (code, ARMREG_IP);
7086 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7088 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7089 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7095 #ifdef USE_JUMP_TABLES
7096 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7097 target_code_jti = TARGET_CODE_JTI (i);
7098 /* Load target address */
7099 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7100 /* Restore registers */
7101 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7103 ARM_BX (code, ARMREG_R1);
7104 set_jumptable_element (jte, target_code_jti, fail_tramp);
7106 arm_patch (item->jmp_code, (guchar*)code);
7108 target_code_ins = code;
7109 /* Load target address */
7110 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7111 /* Save it to the fourth slot */
7112 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7113 /* Restore registers and branch */
7114 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7116 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7118 item->jmp_code = NULL;
7121 #ifdef USE_JUMP_TABLES
7123 set_jumptable_element (jte, imt_method_jti, item->key);
7126 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7128 /*must emit after unconditional branch*/
7129 if (vtable_target) {
7130 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7131 item->chunk_size += 4;
7132 vtable_target = NULL;
7135 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7136 constant_pool_starts [i] = code;
7138 code += extra_space;
7143 #ifdef USE_JUMP_TABLES
7144 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7145 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7146 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7147 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7148 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7150 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7151 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7153 item->jmp_code = (guint8*)code;
7154 ARM_B_COND (code, ARMCOND_HS, 0);
7160 for (i = 0; i < count; ++i) {
7161 MonoIMTCheckItem *item = imt_entries [i];
7162 if (item->jmp_code) {
7163 if (item->check_target_idx)
7164 #ifdef USE_JUMP_TABLES
7165 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7167 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7170 if (i > 0 && item->is_equals) {
7172 #ifdef USE_JUMP_TABLES
7173 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7174 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7176 arminstr_t *space_start = constant_pool_starts [i];
7177 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7178 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7186 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7187 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7192 #ifndef USE_JUMP_TABLES
7193 g_free (constant_pool_starts);
7196 mono_arch_flush_icache ((guint8*)start, size);
7197 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7198 mono_stats.imt_thunks_size += code - start;
7200 g_assert (DISTANCE (start, code) <= size);
7205 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7207 return ctx->regs [reg];
7211 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7213 ctx->regs [reg] = val;
7217 * mono_arch_get_trampolines:
7219 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7223 mono_arch_get_trampolines (gboolean aot)
7225 return mono_arm_get_exception_trampolines (aot);
7229 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7236 bp = MONO_CONTEXT_GET_BP (ctx);
7237 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7239 old_value = *lr_loc;
7240 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7243 *lr_loc = new_value;
7248 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7250 * mono_arch_set_breakpoint:
7252 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7253 * The location should contain code emitted by OP_SEQ_POINT.
7256 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7259 guint32 native_offset = ip - (guint8*)ji->code_start;
7260 MonoDebugOptions *opt = mini_get_debug_options ();
7262 if (opt->soft_breakpoints) {
7263 g_assert (!ji->from_aot);
7265 ARM_BLX_REG (code, ARMREG_LR);
7266 mono_arch_flush_icache (code - 4, 4);
7267 } else if (ji->from_aot) {
7268 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7270 g_assert (native_offset % 4 == 0);
7271 g_assert (info->bp_addrs [native_offset / 4] == 0);
7272 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7274 int dreg = ARMREG_LR;
7276 /* Read from another trigger page */
7277 #ifdef USE_JUMP_TABLES
7278 gpointer *jte = mono_jumptable_add_entry ();
7279 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7280 jte [0] = bp_trigger_page;
7282 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7284 *(int*)code = (int)bp_trigger_page;
7287 ARM_LDR_IMM (code, dreg, dreg, 0);
7289 mono_arch_flush_icache (code - 16, 16);
7292 /* This is currently implemented by emitting an SWI instruction, which
7293 * qemu/linux seems to convert to a SIGILL.
7295 *(int*)code = (0xef << 24) | 8;
7297 mono_arch_flush_icache (code - 4, 4);
7303 * mono_arch_clear_breakpoint:
7305 * Clear the breakpoint at IP.
7308 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7310 MonoDebugOptions *opt = mini_get_debug_options ();
7314 if (opt->soft_breakpoints) {
7315 g_assert (!ji->from_aot);
7318 mono_arch_flush_icache (code - 4, 4);
7319 } else if (ji->from_aot) {
7320 guint32 native_offset = ip - (guint8*)ji->code_start;
7321 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7323 g_assert (native_offset % 4 == 0);
7324 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7325 info->bp_addrs [native_offset / 4] = 0;
7327 for (i = 0; i < 4; ++i)
7330 mono_arch_flush_icache (ip, code - ip);
7335 * mono_arch_start_single_stepping:
7337 * Start single stepping.
7340 mono_arch_start_single_stepping (void)
7342 if (ss_trigger_page)
7343 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7349 * mono_arch_stop_single_stepping:
7351 * Stop single stepping.
7354 mono_arch_stop_single_stepping (void)
7356 if (ss_trigger_page)
7357 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7363 #define DBG_SIGNAL SIGBUS
7365 #define DBG_SIGNAL SIGSEGV
7369 * mono_arch_is_single_step_event:
7371 * Return whenever the machine state in SIGCTX corresponds to a single
7375 mono_arch_is_single_step_event (void *info, void *sigctx)
7377 siginfo_t *sinfo = info;
7379 if (!ss_trigger_page)
7382 /* Sometimes the address is off by 4 */
7383 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7390 * mono_arch_is_breakpoint_event:
7392 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7395 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7397 siginfo_t *sinfo = info;
7399 if (!ss_trigger_page)
7402 if (sinfo->si_signo == DBG_SIGNAL) {
7403 /* Sometimes the address is off by 4 */
7404 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7414 * mono_arch_skip_breakpoint:
7416 * See mini-amd64.c for docs.
7419 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7421 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7425 * mono_arch_skip_single_step:
7427 * See mini-amd64.c for docs.
7430 mono_arch_skip_single_step (MonoContext *ctx)
7432 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7435 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7438 * mono_arch_get_seq_point_info:
7440 * See mini-amd64.c for docs.
7443 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7448 // FIXME: Add a free function
7450 mono_domain_lock (domain);
7451 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7453 mono_domain_unlock (domain);
7456 ji = mono_jit_info_table_find (domain, (char*)code);
7459 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7461 info->ss_trigger_page = ss_trigger_page;
7462 info->bp_trigger_page = bp_trigger_page;
7464 mono_domain_lock (domain);
7465 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7467 mono_domain_unlock (domain);
7474 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7476 ext->lmf.previous_lmf = prev_lmf;
7477 /* Mark that this is a MonoLMFExt */
7478 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7479 ext->lmf.sp = (gssize)ext;
7483 * mono_arch_set_target:
7485 * Set the target architecture the JIT backend should generate code for, in the form
7486 * of a GNU target triplet. Only used in AOT mode.
7489 mono_arch_set_target (char *mtriple)
7491 /* The GNU target triple format is not very well documented */
7492 if (strstr (mtriple, "armv7")) {
7493 v5_supported = TRUE;
7494 v6_supported = TRUE;
7495 v7_supported = TRUE;
7497 if (strstr (mtriple, "armv6")) {
7498 v5_supported = TRUE;
7499 v6_supported = TRUE;
7501 if (strstr (mtriple, "armv7s")) {
7502 v7s_supported = TRUE;
7504 if (strstr (mtriple, "thumbv7s")) {
7505 v5_supported = TRUE;
7506 v6_supported = TRUE;
7507 v7_supported = TRUE;
7508 v7s_supported = TRUE;
7509 thumb_supported = TRUE;
7510 thumb2_supported = TRUE;
7512 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7513 v5_supported = TRUE;
7514 v6_supported = TRUE;
7515 thumb_supported = TRUE;
7518 if (strstr (mtriple, "gnueabi"))
7519 eabi_supported = TRUE;
7523 mono_arch_opcode_supported (int opcode)
7526 case OP_ATOMIC_ADD_I4:
7527 case OP_ATOMIC_EXCHANGE_I4:
7528 case OP_ATOMIC_CAS_I4:
7529 case OP_ATOMIC_LOAD_I1:
7530 case OP_ATOMIC_LOAD_I2:
7531 case OP_ATOMIC_LOAD_I4:
7532 case OP_ATOMIC_LOAD_U1:
7533 case OP_ATOMIC_LOAD_U2:
7534 case OP_ATOMIC_LOAD_U4:
7535 case OP_ATOMIC_STORE_I1:
7536 case OP_ATOMIC_STORE_I2:
7537 case OP_ATOMIC_STORE_I4:
7538 case OP_ATOMIC_STORE_U1:
7539 case OP_ATOMIC_STORE_U2:
7540 case OP_ATOMIC_STORE_U4:
7541 return v7_supported;
7542 case OP_ATOMIC_LOAD_R4:
7543 case OP_ATOMIC_LOAD_R8:
7544 case OP_ATOMIC_STORE_R4:
7545 case OP_ATOMIC_STORE_R8:
7546 return v7_supported && IS_VFP;
7552 #if defined(ENABLE_GSHAREDVT)
7554 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7556 #endif /* !MONOTOUCH */