2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
16 #include <mono/metadata/abi-details.h>
17 #include <mono/metadata/appdomain.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/utils/mono-mmap.h>
21 #include <mono/utils/mono-hwcap.h>
22 #include <mono/utils/mono-memory-model.h>
23 #include <mono/utils/mono-threads-coop.h>
29 #include "debugger-agent.h"
31 #include "mono/arch/arm/arm-vfp-codegen.h"
33 /* Sanity check: This makes no sense */
34 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
35 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
39 * IS_SOFT_FLOAT: Is full software floating point used?
40 * IS_HARD_FLOAT: Is full hardware floating point used?
41 * IS_VFP: Is hardware floating point with software ABI used?
43 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
44 * IS_VFP may delegate to mono_arch_is_soft_float ().
47 #if defined(ARM_FPU_VFP_HARD)
48 #define IS_SOFT_FLOAT (FALSE)
49 #define IS_HARD_FLOAT (TRUE)
51 #elif defined(ARM_FPU_NONE)
52 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
53 #define IS_HARD_FLOAT (FALSE)
54 #define IS_VFP (!mono_arch_is_soft_float ())
56 #define IS_SOFT_FLOAT (FALSE)
57 #define IS_HARD_FLOAT (FALSE)
61 #define THUNK_SIZE (3 * 4)
63 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
66 void sys_icache_invalidate (void *start, size_t len);
69 /* This mutex protects architecture specific caches */
70 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
71 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
72 static mono_mutex_t mini_arch_mutex;
74 static gboolean v5_supported = FALSE;
75 static gboolean v6_supported = FALSE;
76 static gboolean v7_supported = FALSE;
77 static gboolean v7s_supported = FALSE;
78 static gboolean v7k_supported = FALSE;
79 static gboolean thumb_supported = FALSE;
80 static gboolean thumb2_supported = FALSE;
82 * Whenever to use the ARM EABI
84 static gboolean eabi_supported = FALSE;
87 * Whenever to use the iphone ABI extensions:
88 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
89 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
90 * This is required for debugging/profiling tools to work, but it has some overhead so it should
91 * only be turned on in debug builds.
93 static gboolean iphone_abi = FALSE;
96 * The FPU we are generating code for. This is NOT runtime configurable right now,
97 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
99 static MonoArmFPU arm_fpu;
101 #if defined(ARM_FPU_VFP_HARD)
103 * On armhf, d0-d7 are used for argument passing and d8-d15
104 * must be preserved across calls, which leaves us no room
105 * for scratch registers. So we use d14-d15 but back up their
106 * previous contents to a stack slot before using them - see
107 * mono_arm_emit_vfp_scratch_save/_restore ().
109 static int vfp_scratch1 = ARM_VFP_D14;
110 static int vfp_scratch2 = ARM_VFP_D15;
113 * On armel, d0-d7 do not need to be preserved, so we can
114 * freely make use of them as scratch registers.
116 static int vfp_scratch1 = ARM_VFP_D0;
117 static int vfp_scratch2 = ARM_VFP_D1;
122 static gpointer single_step_tramp, breakpoint_tramp;
123 static gpointer get_tls_tramp;
126 * The code generated for sequence points reads from this location, which is
127 * made read-only when single stepping is enabled.
129 static gpointer ss_trigger_page;
131 /* Enabled breakpoints read from this trigger page */
132 static gpointer bp_trigger_page;
136 * floating point support: on ARM it is a mess, there are at least 3
137 * different setups, each of which binary incompat with the other.
138 * 1) FPA: old and ugly, but unfortunately what current distros use
139 * the double binary format has the two words swapped. 8 double registers.
140 * Implemented usually by kernel emulation.
141 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
142 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
143 * 3) VFP: the new and actually sensible and useful FP support. Implemented
144 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
146 * We do not care about FPA. We will support soft float and VFP.
148 int mono_exc_esp_offset = 0;
150 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
151 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
152 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
154 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
155 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
156 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
158 //#define DEBUG_IMT 0
161 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
165 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data);
168 mono_arch_regname (int reg)
170 static const char * rnames[] = {
171 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
172 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
173 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
176 if (reg >= 0 && reg < 16)
182 mono_arch_fregname (int reg)
184 static const char * rnames[] = {
185 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
186 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
187 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
188 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
189 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
190 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
193 if (reg >= 0 && reg < 32)
201 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
203 int imm8, rot_amount;
204 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
205 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
209 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
210 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
212 code = mono_arm_emit_load_imm (code, dreg, imm);
213 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
218 /* If dreg == sreg, this clobbers IP */
220 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
222 int imm8, rot_amount;
223 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
224 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
228 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
229 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
231 code = mono_arm_emit_load_imm (code, dreg, imm);
232 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
238 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
240 /* we can use r0-r3, since this is called only for incoming args on the stack */
241 if (size > sizeof (gpointer) * 4) {
243 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
244 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
245 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
246 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
247 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
248 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
249 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
250 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
251 ARM_B_COND (code, ARMCOND_NE, 0);
252 arm_patch (code - 4, start_loop);
255 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
256 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
258 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
259 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
265 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
266 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
267 doffset = soffset = 0;
269 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
270 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
276 g_assert (size == 0);
281 emit_call_reg (guint8 *code, int reg)
284 ARM_BLX_REG (code, reg);
286 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
290 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
296 emit_call_seq (MonoCompile *cfg, guint8 *code)
298 if (cfg->method->dynamic) {
299 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
301 *(gpointer*)code = NULL;
303 code = emit_call_reg (code, ARMREG_IP);
307 cfg->thunk_area += THUNK_SIZE;
312 mono_arm_patchable_b (guint8 *code, int cond)
314 ARM_B_COND (code, cond, 0);
319 mono_arm_patchable_bl (guint8 *code, int cond)
321 ARM_BL_COND (code, cond, 0);
325 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(__native_client__)
326 #define HAVE_AEABI_READ_TP 1
329 #ifdef HAVE_AEABI_READ_TP
330 gpointer __aeabi_read_tp (void);
334 mono_arch_have_fast_tls (void)
336 #ifdef HAVE_AEABI_READ_TP
337 static gboolean have_fast_tls = FALSE;
338 static gboolean inited = FALSE;
341 if (mini_get_debug_options ()->use_fallback_tls)
345 return have_fast_tls;
347 tp1 = __aeabi_read_tp ();
348 asm volatile("mrc p15, 0, %0, c13, c0, 3" : "=r" (tp2));
350 have_fast_tls = tp1 && tp1 == tp2;
352 return have_fast_tls;
359 emit_tls_get (guint8 *code, int dreg, int tls_offset)
361 ARM_MRC (code, 15, 0, dreg, 13, 0, 3);
362 ARM_LDR_IMM (code, dreg, dreg, tls_offset);
367 emit_tls_set (guint8 *code, int sreg, int tls_offset)
369 int tp_reg = (sreg != ARMREG_R0) ? ARMREG_R0 : ARMREG_R1;
370 ARM_MRC (code, 15, 0, tp_reg, 13, 0, 3);
371 ARM_STR_IMM (code, sreg, tp_reg, tls_offset);
378 * Emit code to push an LMF structure on the LMF stack.
379 * On arm, this is intermixed with the initialization of other fields of the structure.
382 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
386 if (mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR) != -1) {
387 code = emit_tls_get (code, ARMREG_R0, mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR));
389 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
390 (gpointer)"mono_tls_get_lmf_addr");
391 code = emit_call_seq (cfg, code);
393 /* we build the MonoLMF structure on the stack - see mini-arm.h */
394 /* lmf_offset is the offset from the previous stack pointer,
395 * alloc_size is the total stack space allocated, so the offset
396 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
397 * The pointer to the struct is put in r1 (new_lmf).
398 * ip is used as scratch
399 * The callee-saved registers are already in the MonoLMF structure
401 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
402 /* r0 is the result from mono_get_lmf_addr () */
403 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
404 /* new_lmf->previous_lmf = *lmf_addr */
405 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
406 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
407 /* *(lmf_addr) = r1 */
408 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
409 /* Skip method (only needed for trampoline LMF frames) */
410 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
411 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
412 /* save the current IP */
413 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
414 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
416 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
417 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
428 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
432 for (list = inst->float_args; list; list = list->next) {
433 FloatArgData *fad = list->data;
434 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
435 gboolean imm = arm_is_fpimm8 (var->inst_offset);
437 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
443 if (*offset + *max_len > cfg->code_size) {
444 cfg->code_size += *max_len;
445 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
447 code = cfg->native_code + *offset;
451 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
452 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
454 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
456 *offset = code - cfg->native_code;
463 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
467 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
469 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
472 if (!arm_is_fpimm8 (inst->inst_offset)) {
473 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
474 ARM_FSTD (code, reg, ARMREG_LR, 0);
476 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
483 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
487 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
489 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
492 if (!arm_is_fpimm8 (inst->inst_offset)) {
493 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
494 ARM_FLDD (code, reg, ARMREG_LR, 0);
496 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
505 * Emit code to pop an LMF structure from the LMF stack.
508 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
512 if (lmf_offset < 32) {
513 basereg = cfg->frame_reg;
518 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
521 /* ip = previous_lmf */
522 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
524 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
525 /* *(lmf_addr) = previous_lmf */
526 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
531 #endif /* #ifndef DISABLE_JIT */
534 * mono_arch_get_argument_info:
535 * @csig: a method signature
536 * @param_count: the number of parameters to consider
537 * @arg_info: an array to store the result infos
539 * Gathers information on parameters such as size, alignment and
540 * padding. arg_info should be large enought to hold param_count + 1 entries.
542 * Returns the size of the activation frame.
545 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
547 int k, frame_size = 0;
548 guint32 size, align, pad;
552 t = mini_get_underlying_type (csig->ret);
553 if (MONO_TYPE_ISSTRUCT (t)) {
554 frame_size += sizeof (gpointer);
558 arg_info [0].offset = offset;
561 frame_size += sizeof (gpointer);
565 arg_info [0].size = frame_size;
567 for (k = 0; k < param_count; k++) {
568 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
570 /* ignore alignment for now */
573 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
574 arg_info [k].pad = pad;
576 arg_info [k + 1].pad = 0;
577 arg_info [k + 1].size = size;
579 arg_info [k + 1].offset = offset;
583 align = MONO_ARCH_FRAME_ALIGNMENT;
584 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
585 arg_info [k].pad = pad;
590 #define MAX_ARCH_DELEGATE_PARAMS 3
593 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
595 guint8 *code, *start;
596 GSList *unwind_ops = mono_arch_get_cie_program ();
599 start = code = mono_global_codeman_reserve (12);
601 /* Replace the this argument with the target */
602 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
603 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
604 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
606 g_assert ((code - start) <= 12);
608 mono_arch_flush_icache (start, 12);
612 size = 8 + param_count * 4;
613 start = code = mono_global_codeman_reserve (size);
615 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
616 /* slide down the arguments */
617 for (i = 0; i < param_count; ++i) {
618 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
620 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
622 g_assert ((code - start) <= size);
624 mono_arch_flush_icache (start, size);
628 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
630 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
631 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
635 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
641 * mono_arch_get_delegate_invoke_impls:
643 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
647 mono_arch_get_delegate_invoke_impls (void)
653 get_delegate_invoke_impl (&info, TRUE, 0);
654 res = g_slist_prepend (res, info);
656 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
657 get_delegate_invoke_impl (&info, FALSE, i);
658 res = g_slist_prepend (res, info);
665 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
667 guint8 *code, *start;
670 /* FIXME: Support more cases */
671 sig_ret = mini_get_underlying_type (sig->ret);
672 if (MONO_TYPE_ISSTRUCT (sig_ret))
676 static guint8* cached = NULL;
677 mono_mini_arch_lock ();
679 mono_mini_arch_unlock ();
684 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
687 start = get_delegate_invoke_impl (&info, TRUE, 0);
688 mono_tramp_info_register (info, NULL);
691 mono_mini_arch_unlock ();
694 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
697 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
699 for (i = 0; i < sig->param_count; ++i)
700 if (!mono_is_regsize_var (sig->params [i]))
703 mono_mini_arch_lock ();
704 code = cache [sig->param_count];
706 mono_mini_arch_unlock ();
711 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
712 start = mono_aot_get_trampoline (name);
716 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
717 mono_tramp_info_register (info, NULL);
719 cache [sig->param_count] = start;
720 mono_mini_arch_unlock ();
728 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
734 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
736 return (gpointer)regs [ARMREG_R0];
740 * Initialize the cpu to execute managed code.
743 mono_arch_cpu_init (void)
745 i8_align = MONO_ABI_ALIGNOF (gint64);
746 #ifdef MONO_CROSS_COMPILE
747 /* Need to set the alignment of i8 since it can different on the target */
748 #ifdef TARGET_ANDROID
750 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
756 * Initialize architecture specific code.
759 mono_arch_init (void)
761 const char *cpu_arch;
763 #ifdef TARGET_WATCHOS
764 mini_get_debug_options ()->soft_breakpoints = TRUE;
767 mono_os_mutex_init_recursive (&mini_arch_mutex);
768 if (mini_get_debug_options ()->soft_breakpoints) {
770 breakpoint_tramp = mini_get_breakpoint_trampoline ();
772 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
773 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
774 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
777 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
778 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
779 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
780 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
781 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
783 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
785 #if defined(__ARM_EABI__)
786 eabi_supported = TRUE;
789 #if defined(ARM_FPU_VFP_HARD)
790 arm_fpu = MONO_ARM_FPU_VFP_HARD;
792 arm_fpu = MONO_ARM_FPU_VFP;
794 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
796 * If we're compiling with a soft float fallback and it
797 * turns out that no VFP unit is available, we need to
798 * switch to soft float. We don't do this for iOS, since
799 * iOS devices always have a VFP unit.
801 if (!mono_hwcap_arm_has_vfp)
802 arm_fpu = MONO_ARM_FPU_NONE;
805 * This environment variable can be useful in testing
806 * environments to make sure the soft float fallback
807 * works. Most ARM devices have VFP units these days, so
808 * normally soft float code would not be exercised much.
810 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
812 if (soft && !strncmp (soft, "1", 1))
813 arm_fpu = MONO_ARM_FPU_NONE;
817 v5_supported = mono_hwcap_arm_is_v5;
818 v6_supported = mono_hwcap_arm_is_v6;
819 v7_supported = mono_hwcap_arm_is_v7;
822 * On weird devices, the hwcap code may fail to detect
823 * the ARM version. In that case, we can at least safely
824 * assume the version the runtime was compiled for.
836 #if defined(__APPLE__)
837 /* iOS is special-cased here because we don't yet
838 have a way to properly detect CPU features on it. */
839 thumb_supported = TRUE;
842 thumb_supported = mono_hwcap_arm_has_thumb;
843 thumb2_supported = mono_hwcap_arm_has_thumb2;
846 /* Format: armv(5|6|7[s])[-thumb[2]] */
847 cpu_arch = g_getenv ("MONO_CPU_ARCH");
849 /* Do this here so it overrides any detection. */
851 if (strncmp (cpu_arch, "armv", 4) == 0) {
852 v5_supported = cpu_arch [4] >= '5';
853 v6_supported = cpu_arch [4] >= '6';
854 v7_supported = cpu_arch [4] >= '7';
855 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
856 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
859 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
860 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
865 * Cleanup architecture specific code.
868 mono_arch_cleanup (void)
873 * This function returns the optimizations supported on this cpu.
876 mono_arch_cpu_optimizations (guint32 *exclude_mask)
878 /* no arm-specific optimizations yet */
884 * This function test for all SIMD functions supported.
886 * Returns a bitmask corresponding to all supported versions.
890 mono_arch_cpu_enumerate_simd_versions (void)
892 /* SIMD is currently unimplemented */
897 mono_arm_is_hard_float (void)
899 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
905 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
907 if (v7s_supported || v7k_supported) {
921 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
923 mono_arch_is_soft_float (void)
925 return arm_fpu == MONO_ARM_FPU_NONE;
930 is_regsize_var (MonoType *t)
934 t = mini_get_underlying_type (t);
941 case MONO_TYPE_FNPTR:
943 case MONO_TYPE_OBJECT:
944 case MONO_TYPE_STRING:
945 case MONO_TYPE_CLASS:
946 case MONO_TYPE_SZARRAY:
947 case MONO_TYPE_ARRAY:
949 case MONO_TYPE_GENERICINST:
950 if (!mono_type_generic_inst_is_valuetype (t))
953 case MONO_TYPE_VALUETYPE:
960 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
965 for (i = 0; i < cfg->num_varinfo; i++) {
966 MonoInst *ins = cfg->varinfo [i];
967 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
970 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
973 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
976 /* we can only allocate 32 bit values */
977 if (is_regsize_var (ins->inst_vtype)) {
978 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
979 g_assert (i == vmv->idx);
980 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
988 mono_arch_get_global_int_regs (MonoCompile *cfg)
992 mono_arch_compute_omit_fp (cfg);
995 * FIXME: Interface calls might go through a static rgctx trampoline which
996 * sets V5, but it doesn't save it, so we need to save it ourselves, and
999 if (cfg->flags & MONO_CFG_HAS_CALLS)
1000 cfg->uses_rgctx_reg = TRUE;
1002 if (cfg->arch.omit_fp)
1003 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1004 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1005 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1006 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1008 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1009 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1011 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1012 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1013 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1014 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1015 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1016 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1022 * mono_arch_regalloc_cost:
1024 * Return the cost, in number of memory references, of the action of
1025 * allocating the variable VMV into a register during global register
1029 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1035 #endif /* #ifndef DISABLE_JIT */
1038 mono_arch_flush_icache (guint8 *code, gint size)
1040 #if defined(MONO_CROSS_COMPILE)
1042 sys_icache_invalidate (code, size);
1044 __builtin___clear_cache (code, code + size);
1051 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1054 if (*gr > ARMREG_R3) {
1056 ainfo->offset = *stack_size;
1057 ainfo->reg = ARMREG_SP; /* in the caller */
1058 ainfo->storage = RegTypeBase;
1061 ainfo->storage = RegTypeGeneral;
1068 split = i8_align == 4;
1073 if (*gr == ARMREG_R3 && split) {
1074 /* first word in r3 and the second on the stack */
1075 ainfo->offset = *stack_size;
1076 ainfo->reg = ARMREG_SP; /* in the caller */
1077 ainfo->storage = RegTypeBaseGen;
1079 } else if (*gr >= ARMREG_R3) {
1080 if (eabi_supported) {
1081 /* darwin aligns longs to 4 byte only */
1082 if (i8_align == 8) {
1087 ainfo->offset = *stack_size;
1088 ainfo->reg = ARMREG_SP; /* in the caller */
1089 ainfo->storage = RegTypeBase;
1092 if (eabi_supported) {
1093 if (i8_align == 8 && ((*gr) & 1))
1096 ainfo->storage = RegTypeIRegPair;
1105 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1108 * If we're calling a function like this:
1110 * void foo(float a, double b, float c)
1112 * We pass a in s0 and b in d1. That leaves us
1113 * with s1 being unused. The armhf ABI recognizes
1114 * this and requires register assignment to then
1115 * use that for the next single-precision arg,
1116 * i.e. c in this example. So float_spare either
1117 * tells us which reg to use for the next single-
1118 * precision arg, or it's -1, meaning use *fpr.
1120 * Note that even though most of the JIT speaks
1121 * double-precision, fpr represents single-
1122 * precision registers.
1124 * See parts 5.5 and 6.1.2 of the AAPCS for how
1128 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1129 ainfo->storage = RegTypeFP;
1133 * If we're passing a double-precision value
1134 * and *fpr is odd (e.g. it's s1, s3, ...)
1135 * we need to use the next even register. So
1136 * we mark the current *fpr as a spare that
1137 * can be used for the next single-precision
1141 *float_spare = *fpr;
1146 * At this point, we have an even register
1147 * so we assign that and move along.
1151 } else if (*float_spare >= 0) {
1153 * We're passing a single-precision value
1154 * and it looks like a spare single-
1155 * precision register is available. Let's
1159 ainfo->reg = *float_spare;
1163 * If we hit this branch, we're passing a
1164 * single-precision value and we can simply
1165 * use the next available register.
1173 * We've exhausted available floating point
1174 * regs, so pass the rest on the stack.
1182 ainfo->offset = *stack_size;
1183 ainfo->reg = ARMREG_SP;
1184 ainfo->storage = RegTypeBase;
1191 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1195 MonoClassField *field;
1196 MonoType *ftype, *prev_ftype = NULL;
1199 klass = mono_class_from_mono_type (t);
1201 while ((field = mono_class_get_fields (klass, &iter))) {
1202 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1204 ftype = mono_field_get_type (field);
1205 ftype = mini_get_underlying_type (ftype);
1207 if (MONO_TYPE_ISSTRUCT (ftype)) {
1208 int nested_nfields, nested_esize;
1210 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1212 if (nested_esize == 4)
1213 ftype = &mono_defaults.single_class->byval_arg;
1215 ftype = &mono_defaults.double_class->byval_arg;
1216 if (prev_ftype && prev_ftype->type != ftype->type)
1219 nfields += nested_nfields;
1221 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1223 if (prev_ftype && prev_ftype->type != ftype->type)
1229 if (nfields == 0 || nfields > 4)
1231 *out_nfields = nfields;
1232 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1237 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1239 guint i, gr, fpr, pstart;
1241 int n = sig->hasthis + sig->param_count;
1245 guint32 stack_size = 0;
1247 gboolean is_pinvoke = sig->pinvoke;
1248 gboolean vtype_retaddr = FALSE;
1251 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1253 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1260 t = mini_get_underlying_type (sig->ret);
1271 case MONO_TYPE_FNPTR:
1272 case MONO_TYPE_CLASS:
1273 case MONO_TYPE_OBJECT:
1274 case MONO_TYPE_SZARRAY:
1275 case MONO_TYPE_ARRAY:
1276 case MONO_TYPE_STRING:
1277 cinfo->ret.storage = RegTypeGeneral;
1278 cinfo->ret.reg = ARMREG_R0;
1282 cinfo->ret.storage = RegTypeIRegPair;
1283 cinfo->ret.reg = ARMREG_R0;
1287 cinfo->ret.storage = RegTypeFP;
1289 if (t->type == MONO_TYPE_R4)
1290 cinfo->ret.size = 4;
1292 cinfo->ret.size = 8;
1294 if (IS_HARD_FLOAT) {
1295 cinfo->ret.reg = ARM_VFP_F0;
1297 cinfo->ret.reg = ARMREG_R0;
1300 case MONO_TYPE_GENERICINST:
1301 if (!mono_type_generic_inst_is_valuetype (t)) {
1302 cinfo->ret.storage = RegTypeGeneral;
1303 cinfo->ret.reg = ARMREG_R0;
1306 if (mini_is_gsharedvt_variable_type (t)) {
1307 cinfo->ret.storage = RegTypeStructByAddr;
1311 case MONO_TYPE_VALUETYPE:
1312 case MONO_TYPE_TYPEDBYREF:
1313 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1314 cinfo->ret.storage = RegTypeHFA;
1316 cinfo->ret.nregs = nfields;
1317 cinfo->ret.esize = esize;
1320 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1323 #ifdef TARGET_WATCHOS
1328 if (native_size <= max_size) {
1329 cinfo->ret.storage = RegTypeStructByVal;
1330 cinfo->ret.struct_size = native_size;
1331 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1333 cinfo->ret.storage = RegTypeStructByAddr;
1336 cinfo->ret.storage = RegTypeStructByAddr;
1341 case MONO_TYPE_MVAR:
1342 g_assert (mini_is_gsharedvt_type (t));
1343 cinfo->ret.storage = RegTypeStructByAddr;
1345 case MONO_TYPE_VOID:
1348 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1351 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1356 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1357 * the first argument, allowing 'this' to be always passed in the first arg reg.
1358 * Also do this if the first argument is a reference type, since virtual calls
1359 * are sometimes made using calli without sig->hasthis set, like in the delegate
1362 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1364 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1366 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1370 cinfo->ret.reg = gr;
1372 cinfo->vret_arg_index = 1;
1376 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1379 if (vtype_retaddr) {
1380 cinfo->ret.reg = gr;
1385 DEBUG(g_print("params: %d\n", sig->param_count));
1386 for (i = pstart; i < sig->param_count; ++i) {
1387 ArgInfo *ainfo = &cinfo->args [n];
1389 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1390 /* Prevent implicit arguments and sig_cookie from
1391 being passed in registers */
1394 /* Emit the signature cookie just before the implicit arguments */
1395 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1397 DEBUG(g_print("param %d: ", i));
1398 if (sig->params [i]->byref) {
1399 DEBUG(g_print("byref\n"));
1400 add_general (&gr, &stack_size, ainfo, TRUE);
1404 t = mini_get_underlying_type (sig->params [i]);
1408 cinfo->args [n].size = 1;
1409 add_general (&gr, &stack_size, ainfo, TRUE);
1413 cinfo->args [n].size = 2;
1414 add_general (&gr, &stack_size, ainfo, TRUE);
1418 cinfo->args [n].size = 4;
1419 add_general (&gr, &stack_size, ainfo, TRUE);
1424 case MONO_TYPE_FNPTR:
1425 case MONO_TYPE_CLASS:
1426 case MONO_TYPE_OBJECT:
1427 case MONO_TYPE_STRING:
1428 case MONO_TYPE_SZARRAY:
1429 case MONO_TYPE_ARRAY:
1430 cinfo->args [n].size = sizeof (gpointer);
1431 add_general (&gr, &stack_size, ainfo, TRUE);
1433 case MONO_TYPE_GENERICINST:
1434 if (!mono_type_generic_inst_is_valuetype (t)) {
1435 cinfo->args [n].size = sizeof (gpointer);
1436 add_general (&gr, &stack_size, ainfo, TRUE);
1439 if (mini_is_gsharedvt_variable_type (t)) {
1440 /* gsharedvt arguments are passed by ref */
1441 g_assert (mini_is_gsharedvt_type (t));
1442 add_general (&gr, &stack_size, ainfo, TRUE);
1443 switch (ainfo->storage) {
1444 case RegTypeGeneral:
1445 ainfo->storage = RegTypeGSharedVtInReg;
1448 ainfo->storage = RegTypeGSharedVtOnStack;
1451 g_assert_not_reached ();
1456 case MONO_TYPE_TYPEDBYREF:
1457 case MONO_TYPE_VALUETYPE: {
1460 int nwords, nfields, esize;
1463 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1464 if (fpr + nfields < ARM_VFP_F16) {
1465 ainfo->storage = RegTypeHFA;
1467 ainfo->nregs = nfields;
1468 ainfo->esize = esize;
1479 if (t->type == MONO_TYPE_TYPEDBYREF) {
1480 size = sizeof (MonoTypedRef);
1481 align = sizeof (gpointer);
1483 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1485 size = mono_class_native_size (klass, &align);
1487 size = mini_type_stack_size_full (t, &align, FALSE);
1489 DEBUG(g_print ("load %d bytes struct\n", size));
1491 #ifdef TARGET_WATCHOS
1492 /* Watchos pass large structures by ref */
1493 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1494 if (sig->pinvoke && size > 16) {
1495 add_general (&gr, &stack_size, ainfo, TRUE);
1496 switch (ainfo->storage) {
1497 case RegTypeGeneral:
1498 ainfo->storage = RegTypeStructByAddr;
1501 ainfo->storage = RegTypeStructByAddrOnStack;
1504 g_assert_not_reached ();
1513 align_size += (sizeof (gpointer) - 1);
1514 align_size &= ~(sizeof (gpointer) - 1);
1515 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1516 ainfo->storage = RegTypeStructByVal;
1517 ainfo->struct_size = size;
1518 /* FIXME: align stack_size if needed */
1519 if (eabi_supported) {
1520 if (align >= 8 && (gr & 1))
1523 if (gr > ARMREG_R3) {
1525 ainfo->vtsize = nwords;
1527 int rest = ARMREG_R3 - gr + 1;
1528 int n_in_regs = rest >= nwords? nwords: rest;
1530 ainfo->size = n_in_regs;
1531 ainfo->vtsize = nwords - n_in_regs;
1534 nwords -= n_in_regs;
1536 if (sig->call_convention == MONO_CALL_VARARG)
1537 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1538 stack_size = ALIGN_TO (stack_size, align);
1539 ainfo->offset = stack_size;
1540 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1541 stack_size += nwords * sizeof (gpointer);
1547 add_general (&gr, &stack_size, ainfo, FALSE);
1553 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1555 add_general (&gr, &stack_size, ainfo, TRUE);
1561 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1563 add_general (&gr, &stack_size, ainfo, FALSE);
1566 case MONO_TYPE_MVAR:
1567 /* gsharedvt arguments are passed by ref */
1568 g_assert (mini_is_gsharedvt_type (t));
1569 add_general (&gr, &stack_size, ainfo, TRUE);
1570 switch (ainfo->storage) {
1571 case RegTypeGeneral:
1572 ainfo->storage = RegTypeGSharedVtInReg;
1575 ainfo->storage = RegTypeGSharedVtOnStack;
1578 g_assert_not_reached ();
1582 g_error ("Can't handle 0x%x", sig->params [i]->type);
1587 /* Handle the case where there are no implicit arguments */
1588 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1589 /* Prevent implicit arguments and sig_cookie from
1590 being passed in registers */
1593 /* Emit the signature cookie just before the implicit arguments */
1594 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1597 /* align stack size to 8 */
1598 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1599 stack_size = (stack_size + 7) & ~7;
1601 cinfo->stack_usage = stack_size;
1607 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1609 MonoType *callee_ret;
1613 c1 = get_call_info (NULL, caller_sig);
1614 c2 = get_call_info (NULL, callee_sig);
1617 * Tail calls with more callee stack usage than the caller cannot be supported, since
1618 * the extra stack space would be left on the stack after the tail call.
1620 res = c1->stack_usage >= c2->stack_usage;
1621 callee_ret = mini_get_underlying_type (callee_sig->ret);
1622 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1623 /* An address on the callee's stack is passed as the first argument */
1626 if (c2->stack_usage > 16 * 4)
1638 debug_omit_fp (void)
1641 return mono_debug_count ();
1648 * mono_arch_compute_omit_fp:
1650 * Determine whenever the frame pointer can be eliminated.
1653 mono_arch_compute_omit_fp (MonoCompile *cfg)
1655 MonoMethodSignature *sig;
1656 MonoMethodHeader *header;
1660 if (cfg->arch.omit_fp_computed)
1663 header = cfg->header;
1665 sig = mono_method_signature (cfg->method);
1667 if (!cfg->arch.cinfo)
1668 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1669 cinfo = cfg->arch.cinfo;
1672 * FIXME: Remove some of the restrictions.
1674 cfg->arch.omit_fp = TRUE;
1675 cfg->arch.omit_fp_computed = TRUE;
1677 if (cfg->disable_omit_fp)
1678 cfg->arch.omit_fp = FALSE;
1679 if (!debug_omit_fp ())
1680 cfg->arch.omit_fp = FALSE;
1682 if (cfg->method->save_lmf)
1683 cfg->arch.omit_fp = FALSE;
1685 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1686 cfg->arch.omit_fp = FALSE;
1687 if (header->num_clauses)
1688 cfg->arch.omit_fp = FALSE;
1689 if (cfg->param_area)
1690 cfg->arch.omit_fp = FALSE;
1691 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1692 cfg->arch.omit_fp = FALSE;
1693 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1694 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1695 cfg->arch.omit_fp = FALSE;
1696 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1697 ArgInfo *ainfo = &cinfo->args [i];
1699 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1701 * The stack offset can only be determined when the frame
1704 cfg->arch.omit_fp = FALSE;
1709 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1710 MonoInst *ins = cfg->varinfo [i];
1713 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1718 * Set var information according to the calling convention. arm version.
1719 * The locals var stuff should most likely be split in another method.
1722 mono_arch_allocate_vars (MonoCompile *cfg)
1724 MonoMethodSignature *sig;
1725 MonoMethodHeader *header;
1728 int i, offset, size, align, curinst;
1733 sig = mono_method_signature (cfg->method);
1735 if (!cfg->arch.cinfo)
1736 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1737 cinfo = cfg->arch.cinfo;
1738 sig_ret = mini_get_underlying_type (sig->ret);
1740 mono_arch_compute_omit_fp (cfg);
1742 if (cfg->arch.omit_fp)
1743 cfg->frame_reg = ARMREG_SP;
1745 cfg->frame_reg = ARMREG_FP;
1747 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1749 /* allow room for the vararg method args: void* and long/double */
1750 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1751 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1753 header = cfg->header;
1755 /* See mono_arch_get_global_int_regs () */
1756 if (cfg->flags & MONO_CFG_HAS_CALLS)
1757 cfg->uses_rgctx_reg = TRUE;
1759 if (cfg->frame_reg != ARMREG_SP)
1760 cfg->used_int_regs |= 1 << cfg->frame_reg;
1762 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1763 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1764 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1768 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1769 if (sig_ret->type != MONO_TYPE_VOID) {
1770 cfg->ret->opcode = OP_REGVAR;
1771 cfg->ret->inst_c0 = ARMREG_R0;
1774 /* local vars are at a positive offset from the stack pointer */
1776 * also note that if the function uses alloca, we use FP
1777 * to point at the local variables.
1779 offset = 0; /* linkage area */
1780 /* align the offset to 16 bytes: not sure this is needed here */
1782 //offset &= ~(8 - 1);
1784 /* add parameter area size for called functions */
1785 offset += cfg->param_area;
1788 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1791 /* allow room to save the return value */
1792 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1795 switch (cinfo->ret.storage) {
1796 case RegTypeStructByVal:
1798 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1799 offset = ALIGN_TO (offset, 8);
1800 cfg->ret->opcode = OP_REGOFFSET;
1801 cfg->ret->inst_basereg = cfg->frame_reg;
1802 cfg->ret->inst_offset = offset;
1803 if (cinfo->ret.storage == RegTypeStructByVal)
1804 offset += cinfo->ret.nregs * sizeof (gpointer);
1808 case RegTypeStructByAddr:
1809 ins = cfg->vret_addr;
1810 offset += sizeof(gpointer) - 1;
1811 offset &= ~(sizeof(gpointer) - 1);
1812 ins->inst_offset = offset;
1813 ins->opcode = OP_REGOFFSET;
1814 ins->inst_basereg = cfg->frame_reg;
1815 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1816 g_print ("vret_addr =");
1817 mono_print_ins (cfg->vret_addr);
1819 offset += sizeof(gpointer);
1825 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1826 if (cfg->arch.seq_point_info_var) {
1829 ins = cfg->arch.seq_point_info_var;
1833 offset += align - 1;
1834 offset &= ~(align - 1);
1835 ins->opcode = OP_REGOFFSET;
1836 ins->inst_basereg = cfg->frame_reg;
1837 ins->inst_offset = offset;
1840 if (cfg->arch.ss_trigger_page_var) {
1843 ins = cfg->arch.ss_trigger_page_var;
1846 offset += align - 1;
1847 offset &= ~(align - 1);
1848 ins->opcode = OP_REGOFFSET;
1849 ins->inst_basereg = cfg->frame_reg;
1850 ins->inst_offset = offset;
1854 if (cfg->arch.seq_point_ss_method_var) {
1857 ins = cfg->arch.seq_point_ss_method_var;
1860 offset += align - 1;
1861 offset &= ~(align - 1);
1862 ins->opcode = OP_REGOFFSET;
1863 ins->inst_basereg = cfg->frame_reg;
1864 ins->inst_offset = offset;
1867 if (cfg->arch.seq_point_bp_method_var) {
1870 ins = cfg->arch.seq_point_bp_method_var;
1873 offset += align - 1;
1874 offset &= ~(align - 1);
1875 ins->opcode = OP_REGOFFSET;
1876 ins->inst_basereg = cfg->frame_reg;
1877 ins->inst_offset = offset;
1881 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1882 /* Allocate a temporary used by the atomic ops */
1886 /* Allocate a local slot to hold the sig cookie address */
1887 offset += align - 1;
1888 offset &= ~(align - 1);
1889 cfg->arch.atomic_tmp_offset = offset;
1892 cfg->arch.atomic_tmp_offset = -1;
1895 cfg->locals_min_stack_offset = offset;
1897 curinst = cfg->locals_start;
1898 for (i = curinst; i < cfg->num_varinfo; ++i) {
1901 ins = cfg->varinfo [i];
1902 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1905 t = ins->inst_vtype;
1906 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1909 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1910 * pinvoke wrappers when they call functions returning structure */
1911 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1912 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1916 size = mono_type_size (t, &align);
1918 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1919 * since it loads/stores misaligned words, which don't do the right thing.
1921 if (align < 4 && size >= 4)
1923 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1924 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1925 offset += align - 1;
1926 offset &= ~(align - 1);
1927 ins->opcode = OP_REGOFFSET;
1928 ins->inst_offset = offset;
1929 ins->inst_basereg = cfg->frame_reg;
1931 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1934 cfg->locals_max_stack_offset = offset;
1938 ins = cfg->args [curinst];
1939 if (ins->opcode != OP_REGVAR) {
1940 ins->opcode = OP_REGOFFSET;
1941 ins->inst_basereg = cfg->frame_reg;
1942 offset += sizeof (gpointer) - 1;
1943 offset &= ~(sizeof (gpointer) - 1);
1944 ins->inst_offset = offset;
1945 offset += sizeof (gpointer);
1950 if (sig->call_convention == MONO_CALL_VARARG) {
1954 /* Allocate a local slot to hold the sig cookie address */
1955 offset += align - 1;
1956 offset &= ~(align - 1);
1957 cfg->sig_cookie = offset;
1961 for (i = 0; i < sig->param_count; ++i) {
1962 ainfo = cinfo->args + i;
1964 ins = cfg->args [curinst];
1966 switch (ainfo->storage) {
1968 offset = ALIGN_TO (offset, 8);
1969 ins->opcode = OP_REGOFFSET;
1970 ins->inst_basereg = cfg->frame_reg;
1971 /* These arguments are saved to the stack in the prolog */
1972 ins->inst_offset = offset;
1973 if (cfg->verbose_level >= 2)
1974 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
1982 if (ins->opcode != OP_REGVAR) {
1983 ins->opcode = OP_REGOFFSET;
1984 ins->inst_basereg = cfg->frame_reg;
1985 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
1987 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1988 * since it loads/stores misaligned words, which don't do the right thing.
1990 if (align < 4 && size >= 4)
1992 /* The code in the prolog () stores words when storing vtypes received in a register */
1993 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1995 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1996 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1997 offset += align - 1;
1998 offset &= ~(align - 1);
1999 ins->inst_offset = offset;
2005 /* align the offset to 8 bytes */
2006 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2007 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2012 cfg->stack_offset = offset;
2016 mono_arch_create_vars (MonoCompile *cfg)
2018 MonoMethodSignature *sig;
2022 sig = mono_method_signature (cfg->method);
2024 if (!cfg->arch.cinfo)
2025 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2026 cinfo = cfg->arch.cinfo;
2028 if (IS_HARD_FLOAT) {
2029 for (i = 0; i < 2; i++) {
2030 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2031 inst->flags |= MONO_INST_VOLATILE;
2033 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2037 if (cinfo->ret.storage == RegTypeStructByVal)
2038 cfg->ret_var_is_local = TRUE;
2040 if (cinfo->ret.storage == RegTypeStructByAddr) {
2041 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2042 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2043 g_print ("vret_addr = ");
2044 mono_print_ins (cfg->vret_addr);
2048 if (cfg->gen_sdb_seq_points) {
2049 if (cfg->compile_aot) {
2050 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2051 ins->flags |= MONO_INST_VOLATILE;
2052 cfg->arch.seq_point_info_var = ins;
2054 if (!cfg->soft_breakpoints) {
2055 /* Allocate a separate variable for this to save 1 load per seq point */
2056 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2057 ins->flags |= MONO_INST_VOLATILE;
2058 cfg->arch.ss_trigger_page_var = ins;
2061 if (cfg->soft_breakpoints) {
2064 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2065 ins->flags |= MONO_INST_VOLATILE;
2066 cfg->arch.seq_point_ss_method_var = ins;
2068 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2069 ins->flags |= MONO_INST_VOLATILE;
2070 cfg->arch.seq_point_bp_method_var = ins;
2076 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2078 MonoMethodSignature *tmp_sig;
2081 if (call->tail_call)
2084 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2087 * mono_ArgIterator_Setup assumes the signature cookie is
2088 * passed first and all the arguments which were before it are
2089 * passed on the stack after the signature. So compensate by
2090 * passing a different signature.
2092 tmp_sig = mono_metadata_signature_dup (call->signature);
2093 tmp_sig->param_count -= call->signature->sentinelpos;
2094 tmp_sig->sentinelpos = 0;
2095 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2097 sig_reg = mono_alloc_ireg (cfg);
2098 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2100 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2105 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2110 LLVMCallInfo *linfo;
2112 n = sig->param_count + sig->hasthis;
2114 cinfo = get_call_info (cfg->mempool, sig);
2116 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2119 * LLVM always uses the native ABI while we use our own ABI, the
2120 * only difference is the handling of vtypes:
2121 * - we only pass/receive them in registers in some cases, and only
2122 * in 1 or 2 integer registers.
2124 switch (cinfo->ret.storage) {
2125 case RegTypeGeneral:
2128 case RegTypeIRegPair:
2130 case RegTypeStructByAddr:
2131 /* Vtype returned using a hidden argument */
2132 linfo->ret.storage = LLVMArgVtypeRetAddr;
2133 linfo->vret_arg_index = cinfo->vret_arg_index;
2136 case RegTypeStructByVal:
2137 /* LLVM models this by returning an int array */
2138 linfo->ret.storage = LLVMArgAsIArgs;
2139 linfo->ret.nslots = cinfo->ret.nregs;
2143 linfo->ret.storage = LLVMArgFpStruct;
2144 linfo->ret.nslots = cinfo->ret.nregs;
2145 linfo->ret.esize = cinfo->ret.esize;
2148 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2149 cfg->disable_llvm = TRUE;
2153 for (i = 0; i < n; ++i) {
2154 LLVMArgInfo *lainfo = &linfo->args [i];
2155 ainfo = cinfo->args + i;
2157 lainfo->storage = LLVMArgNone;
2159 switch (ainfo->storage) {
2160 case RegTypeGeneral:
2161 case RegTypeIRegPair:
2163 case RegTypeBaseGen:
2165 lainfo->storage = LLVMArgNormal;
2167 case RegTypeStructByVal:
2168 lainfo->storage = LLVMArgAsIArgs;
2169 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2171 case RegTypeStructByAddr:
2172 case RegTypeStructByAddrOnStack:
2173 lainfo->storage = LLVMArgVtypeByRef;
2178 lainfo->storage = LLVMArgAsFpArgs;
2179 lainfo->nslots = ainfo->nregs;
2180 lainfo->esize = ainfo->esize;
2181 for (j = 0; j < ainfo->nregs; ++j)
2182 lainfo->pair_storage [j] = LLVMArgInFPReg;
2186 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2187 cfg->disable_llvm = TRUE;
2197 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2200 MonoMethodSignature *sig;
2204 sig = call->signature;
2205 n = sig->param_count + sig->hasthis;
2207 cinfo = get_call_info (cfg->mempool, sig);
2209 switch (cinfo->ret.storage) {
2210 case RegTypeStructByVal:
2212 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2213 /* The JIT will transform this into a normal call */
2214 call->vret_in_reg = TRUE;
2217 if (call->inst.opcode == OP_TAILCALL)
2220 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2221 * the location pointed to by it after call in emit_move_return_value ().
2223 if (!cfg->arch.vret_addr_loc) {
2224 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2225 /* Prevent it from being register allocated or optimized away */
2226 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2229 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2231 case RegTypeStructByAddr: {
2233 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2234 vtarg->sreg1 = call->vret_var->dreg;
2235 vtarg->dreg = mono_alloc_preg (cfg);
2236 MONO_ADD_INS (cfg->cbb, vtarg);
2238 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2245 for (i = 0; i < n; ++i) {
2246 ArgInfo *ainfo = cinfo->args + i;
2249 if (i >= sig->hasthis)
2250 t = sig->params [i - sig->hasthis];
2252 t = &mono_defaults.int_class->byval_arg;
2253 t = mini_get_underlying_type (t);
2255 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2256 /* Emit the signature cookie just before the implicit arguments */
2257 emit_sig_cookie (cfg, call, cinfo);
2260 in = call->args [i];
2262 switch (ainfo->storage) {
2263 case RegTypeGeneral:
2264 case RegTypeIRegPair:
2265 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2266 MONO_INST_NEW (cfg, ins, OP_MOVE);
2267 ins->dreg = mono_alloc_ireg (cfg);
2268 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2269 MONO_ADD_INS (cfg->cbb, ins);
2270 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2272 MONO_INST_NEW (cfg, ins, OP_MOVE);
2273 ins->dreg = mono_alloc_ireg (cfg);
2274 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2275 MONO_ADD_INS (cfg->cbb, ins);
2276 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2277 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2278 if (ainfo->size == 4) {
2279 if (IS_SOFT_FLOAT) {
2280 /* mono_emit_call_args () have already done the r8->r4 conversion */
2281 /* The converted value is in an int vreg */
2282 MONO_INST_NEW (cfg, ins, OP_MOVE);
2283 ins->dreg = mono_alloc_ireg (cfg);
2284 ins->sreg1 = in->dreg;
2285 MONO_ADD_INS (cfg->cbb, ins);
2286 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2290 cfg->param_area = MAX (cfg->param_area, 8);
2291 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2292 creg = mono_alloc_ireg (cfg);
2293 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2294 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2297 if (IS_SOFT_FLOAT) {
2298 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2299 ins->dreg = mono_alloc_ireg (cfg);
2300 ins->sreg1 = in->dreg;
2301 MONO_ADD_INS (cfg->cbb, ins);
2302 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2304 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2305 ins->dreg = mono_alloc_ireg (cfg);
2306 ins->sreg1 = in->dreg;
2307 MONO_ADD_INS (cfg->cbb, ins);
2308 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2312 cfg->param_area = MAX (cfg->param_area, 8);
2313 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2314 creg = mono_alloc_ireg (cfg);
2315 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2316 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2317 creg = mono_alloc_ireg (cfg);
2318 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2319 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2322 cfg->flags |= MONO_CFG_HAS_FPOUT;
2324 MONO_INST_NEW (cfg, ins, OP_MOVE);
2325 ins->dreg = mono_alloc_ireg (cfg);
2326 ins->sreg1 = in->dreg;
2327 MONO_ADD_INS (cfg->cbb, ins);
2329 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2332 case RegTypeStructByVal:
2333 case RegTypeGSharedVtInReg:
2334 case RegTypeGSharedVtOnStack:
2336 case RegTypeStructByAddr:
2337 case RegTypeStructByAddrOnStack:
2338 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2339 ins->opcode = OP_OUTARG_VT;
2340 ins->sreg1 = in->dreg;
2341 ins->klass = in->klass;
2342 ins->inst_p0 = call;
2343 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2344 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2345 mono_call_inst_add_outarg_vt (cfg, call, ins);
2346 MONO_ADD_INS (cfg->cbb, ins);
2349 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2350 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2351 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2352 if (t->type == MONO_TYPE_R8) {
2353 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2356 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2358 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2361 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2364 case RegTypeBaseGen:
2365 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2366 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2367 MONO_INST_NEW (cfg, ins, OP_MOVE);
2368 ins->dreg = mono_alloc_ireg (cfg);
2369 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2370 MONO_ADD_INS (cfg->cbb, ins);
2371 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2372 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2375 /* This should work for soft-float as well */
2377 cfg->param_area = MAX (cfg->param_area, 8);
2378 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2379 creg = mono_alloc_ireg (cfg);
2380 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2381 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2382 creg = mono_alloc_ireg (cfg);
2383 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2384 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2385 cfg->flags |= MONO_CFG_HAS_FPOUT;
2387 g_assert_not_reached ();
2391 int fdreg = mono_alloc_freg (cfg);
2393 if (ainfo->size == 8) {
2394 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2395 ins->sreg1 = in->dreg;
2397 MONO_ADD_INS (cfg->cbb, ins);
2399 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2404 * Mono's register allocator doesn't speak single-precision registers that
2405 * overlap double-precision registers (i.e. armhf). So we have to work around
2406 * the register allocator and load the value from memory manually.
2408 * So we create a variable for the float argument and an instruction to store
2409 * the argument into the variable. We then store the list of these arguments
2410 * in call->float_args. This list is then used by emit_float_args later to
2411 * pass the arguments in the various call opcodes.
2413 * This is not very nice, and we should really try to fix the allocator.
2416 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2418 /* Make sure the instruction isn't seen as pointless and removed.
2420 float_arg->flags |= MONO_INST_VOLATILE;
2422 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2424 /* We use the dreg to look up the instruction later. The hreg is used to
2425 * emit the instruction that loads the value into the FP reg.
2427 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2428 fad->vreg = float_arg->dreg;
2429 fad->hreg = ainfo->reg;
2431 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2434 call->used_iregs |= 1 << ainfo->reg;
2435 cfg->flags |= MONO_CFG_HAS_FPOUT;
2439 g_assert_not_reached ();
2443 /* Handle the case where there are no implicit arguments */
2444 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2445 emit_sig_cookie (cfg, call, cinfo);
2447 call->call_info = cinfo;
2448 call->stack_usage = cinfo->stack_usage;
2452 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2458 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2459 ins->dreg = mono_alloc_freg (cfg);
2460 ins->sreg1 = arg->dreg;
2461 MONO_ADD_INS (cfg->cbb, ins);
2462 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2465 g_assert_not_reached ();
2471 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2473 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2475 ArgInfo *ainfo = ins->inst_p1;
2476 int ovf_size = ainfo->vtsize;
2477 int doffset = ainfo->offset;
2478 int struct_size = ainfo->struct_size;
2479 int i, soffset, dreg, tmpreg;
2481 switch (ainfo->storage) {
2482 case RegTypeGSharedVtInReg:
2483 case RegTypeStructByAddr:
2485 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2487 case RegTypeGSharedVtOnStack:
2488 case RegTypeStructByAddrOnStack:
2489 /* Pass by addr on stack */
2490 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2493 for (i = 0; i < ainfo->nregs; ++i) {
2494 if (ainfo->esize == 4)
2495 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2497 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2498 load->dreg = mono_alloc_freg (cfg);
2499 load->inst_basereg = src->dreg;
2500 load->inst_offset = i * ainfo->esize;
2501 MONO_ADD_INS (cfg->cbb, load);
2503 if (ainfo->esize == 4) {
2506 /* See RegTypeFP in mono_arch_emit_call () */
2507 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2508 float_arg->flags |= MONO_INST_VOLATILE;
2509 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2511 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2512 fad->vreg = float_arg->dreg;
2513 fad->hreg = ainfo->reg + i;
2515 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2517 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2523 for (i = 0; i < ainfo->size; ++i) {
2524 dreg = mono_alloc_ireg (cfg);
2525 switch (struct_size) {
2527 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2530 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2533 tmpreg = mono_alloc_ireg (cfg);
2534 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2535 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2536 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2537 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2538 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2539 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2540 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2543 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2546 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2547 soffset += sizeof (gpointer);
2548 struct_size -= sizeof (gpointer);
2550 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2552 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2558 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2560 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2563 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2566 if (COMPILE_LLVM (cfg)) {
2567 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2569 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2570 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2571 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2572 MONO_ADD_INS (cfg->cbb, ins);
2577 case MONO_ARM_FPU_NONE:
2578 if (ret->type == MONO_TYPE_R8) {
2581 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2582 ins->dreg = cfg->ret->dreg;
2583 ins->sreg1 = val->dreg;
2584 MONO_ADD_INS (cfg->cbb, ins);
2587 if (ret->type == MONO_TYPE_R4) {
2588 /* Already converted to an int in method_to_ir () */
2589 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2593 case MONO_ARM_FPU_VFP:
2594 case MONO_ARM_FPU_VFP_HARD:
2595 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2598 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2599 ins->dreg = cfg->ret->dreg;
2600 ins->sreg1 = val->dreg;
2601 MONO_ADD_INS (cfg->cbb, ins);
2606 g_assert_not_reached ();
2610 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2613 #endif /* #ifndef DISABLE_JIT */
2616 mono_arch_is_inst_imm (gint64 imm)
2622 MonoMethodSignature *sig;
2625 MonoType **param_types;
2629 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2633 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2636 switch (cinfo->ret.storage) {
2638 case RegTypeGeneral:
2639 case RegTypeIRegPair:
2640 case RegTypeStructByAddr:
2651 for (i = 0; i < cinfo->nargs; ++i) {
2652 ArgInfo *ainfo = &cinfo->args [i];
2655 switch (ainfo->storage) {
2656 case RegTypeGeneral:
2657 case RegTypeIRegPair:
2658 case RegTypeBaseGen:
2662 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2665 case RegTypeStructByVal:
2666 if (ainfo->size == 0)
2667 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2669 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2670 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2678 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2679 for (i = 0; i < sig->param_count; ++i) {
2680 MonoType *t = sig->params [i];
2685 t = mini_get_underlying_type (t);
2708 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2710 ArchDynCallInfo *info;
2714 cinfo = get_call_info (NULL, sig);
2716 if (!dyn_call_supported (cinfo, sig)) {
2721 info = g_new0 (ArchDynCallInfo, 1);
2722 // FIXME: Preprocess the info to speed up start_dyn_call ()
2724 info->cinfo = cinfo;
2725 info->rtype = mini_get_underlying_type (sig->ret);
2726 info->param_types = g_new0 (MonoType*, sig->param_count);
2727 for (i = 0; i < sig->param_count; ++i)
2728 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2730 return (MonoDynCallInfo*)info;
2734 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2736 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2738 g_free (ainfo->cinfo);
2743 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2745 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2746 DynCallArgs *p = (DynCallArgs*)buf;
2747 int arg_index, greg, i, j, pindex;
2748 MonoMethodSignature *sig = dinfo->sig;
2750 g_assert (buf_len >= sizeof (DynCallArgs));
2760 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2761 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2766 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2767 p->regs [greg ++] = (mgreg_t)ret;
2769 for (i = pindex; i < sig->param_count; i++) {
2770 MonoType *t = dinfo->param_types [i];
2771 gpointer *arg = args [arg_index ++];
2772 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2775 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2777 } else if (ainfo->storage == RegTypeFP) {
2778 } else if (ainfo->storage == RegTypeBase) {
2779 slot = PARAM_REGS + (ainfo->offset / 4);
2780 } else if (ainfo->storage == RegTypeBaseGen) {
2781 /* slot + 1 is the first stack slot, so the code below will work */
2784 g_assert_not_reached ();
2788 p->regs [slot] = (mgreg_t)*arg;
2793 case MONO_TYPE_STRING:
2794 case MONO_TYPE_CLASS:
2795 case MONO_TYPE_ARRAY:
2796 case MONO_TYPE_SZARRAY:
2797 case MONO_TYPE_OBJECT:
2801 p->regs [slot] = (mgreg_t)*arg;
2804 p->regs [slot] = *(guint8*)arg;
2807 p->regs [slot] = *(gint8*)arg;
2810 p->regs [slot] = *(gint16*)arg;
2813 p->regs [slot] = *(guint16*)arg;
2816 p->regs [slot] = *(gint32*)arg;
2819 p->regs [slot] = *(guint32*)arg;
2823 p->regs [slot ++] = (mgreg_t)arg [0];
2824 p->regs [slot] = (mgreg_t)arg [1];
2827 if (ainfo->storage == RegTypeFP) {
2828 float f = *(float*)arg;
2829 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2832 p->regs [slot] = *(mgreg_t*)arg;
2836 if (ainfo->storage == RegTypeFP) {
2837 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2840 p->regs [slot ++] = (mgreg_t)arg [0];
2841 p->regs [slot] = (mgreg_t)arg [1];
2844 case MONO_TYPE_GENERICINST:
2845 if (MONO_TYPE_IS_REFERENCE (t)) {
2846 p->regs [slot] = (mgreg_t)*arg;
2849 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2850 MonoClass *klass = mono_class_from_mono_type (t);
2851 guint8 *nullable_buf;
2854 size = mono_class_value_size (klass, NULL);
2855 nullable_buf = g_alloca (size);
2856 g_assert (nullable_buf);
2858 /* The argument pointed to by arg is either a boxed vtype or null */
2859 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2861 arg = (gpointer*)nullable_buf;
2867 case MONO_TYPE_VALUETYPE:
2868 g_assert (ainfo->storage == RegTypeStructByVal);
2870 if (ainfo->size == 0)
2871 slot = PARAM_REGS + (ainfo->offset / 4);
2875 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2876 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2879 g_assert_not_reached ();
2885 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2887 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2888 DynCallArgs *p = (DynCallArgs*)buf;
2889 MonoType *ptype = ainfo->rtype;
2890 guint8 *ret = p->ret;
2891 mgreg_t res = p->res;
2892 mgreg_t res2 = p->res2;
2894 switch (ptype->type) {
2895 case MONO_TYPE_VOID:
2896 *(gpointer*)ret = NULL;
2898 case MONO_TYPE_STRING:
2899 case MONO_TYPE_CLASS:
2900 case MONO_TYPE_ARRAY:
2901 case MONO_TYPE_SZARRAY:
2902 case MONO_TYPE_OBJECT:
2906 *(gpointer*)ret = (gpointer)res;
2912 *(guint8*)ret = res;
2915 *(gint16*)ret = res;
2918 *(guint16*)ret = res;
2921 *(gint32*)ret = res;
2924 *(guint32*)ret = res;
2928 /* This handles endianness as well */
2929 ((gint32*)ret) [0] = res;
2930 ((gint32*)ret) [1] = res2;
2932 case MONO_TYPE_GENERICINST:
2933 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2934 *(gpointer*)ret = (gpointer)res;
2939 case MONO_TYPE_VALUETYPE:
2940 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2946 *(float*)ret = *(float*)&p->fpregs [0];
2948 *(float*)ret = *(float*)&res;
2950 case MONO_TYPE_R8: {
2954 if (IS_HARD_FLOAT) {
2955 *(double*)ret = p->fpregs [0];
2960 *(double*)ret = *(double*)®s;
2965 g_assert_not_reached ();
2972 * Allow tracing to work with this interface (with an optional argument)
2976 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2980 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2981 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2982 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2983 code = emit_call_reg (code, ARMREG_R2);
2997 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3000 int save_mode = SAVE_NONE;
3002 MonoMethod *method = cfg->method;
3003 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3004 int rtype = ret_type->type;
3005 int save_offset = cfg->param_area;
3009 offset = code - cfg->native_code;
3010 /* we need about 16 instructions */
3011 if (offset > (cfg->code_size - 16 * 4)) {
3012 cfg->code_size *= 2;
3013 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3014 code = cfg->native_code + offset;
3017 case MONO_TYPE_VOID:
3018 /* special case string .ctor icall */
3019 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3020 save_mode = SAVE_ONE;
3022 save_mode = SAVE_NONE;
3026 save_mode = SAVE_TWO;
3030 save_mode = SAVE_ONE_FP;
3032 save_mode = SAVE_ONE;
3036 save_mode = SAVE_TWO_FP;
3038 save_mode = SAVE_TWO;
3040 case MONO_TYPE_GENERICINST:
3041 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3042 save_mode = SAVE_ONE;
3046 case MONO_TYPE_VALUETYPE:
3047 save_mode = SAVE_STRUCT;
3050 save_mode = SAVE_ONE;
3054 switch (save_mode) {
3056 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3057 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3058 if (enable_arguments) {
3059 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3060 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3064 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3065 if (enable_arguments) {
3066 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3070 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3071 if (enable_arguments) {
3072 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3076 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3077 if (enable_arguments) {
3078 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3082 if (enable_arguments) {
3083 /* FIXME: get the actual address */
3084 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3092 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3093 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3094 code = emit_call_reg (code, ARMREG_IP);
3096 switch (save_mode) {
3098 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3099 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3102 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3105 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3108 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3119 * The immediate field for cond branches is big enough for all reasonable methods
3121 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3122 if (0 && ins->inst_true_bb->native_offset) { \
3123 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3125 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3126 ARM_B_COND (code, (condcode), 0); \
3129 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3131 /* emit an exception if condition is fail
3133 * We assign the extra code used to throw the implicit exceptions
3134 * to cfg->bb_exit as far as the big branch handling is concerned
3136 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3138 mono_add_patch_info (cfg, code - cfg->native_code, \
3139 MONO_PATCH_INFO_EXC, exc_name); \
3140 ARM_BL_COND (code, (condcode), 0); \
3143 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3146 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3151 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3155 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3156 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3158 switch (ins->opcode) {
3161 /* Already done by an arch-independent pass */
3163 case OP_LOAD_MEMBASE:
3164 case OP_LOADI4_MEMBASE:
3166 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3167 * OP_LOAD_MEMBASE offset(basereg), reg
3169 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3170 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3171 ins->inst_basereg == last_ins->inst_destbasereg &&
3172 ins->inst_offset == last_ins->inst_offset) {
3173 if (ins->dreg == last_ins->sreg1) {
3174 MONO_DELETE_INS (bb, ins);
3177 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3178 ins->opcode = OP_MOVE;
3179 ins->sreg1 = last_ins->sreg1;
3183 * Note: reg1 must be different from the basereg in the second load
3184 * OP_LOAD_MEMBASE offset(basereg), reg1
3185 * OP_LOAD_MEMBASE offset(basereg), reg2
3187 * OP_LOAD_MEMBASE offset(basereg), reg1
3188 * OP_MOVE reg1, reg2
3190 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3191 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3192 ins->inst_basereg != last_ins->dreg &&
3193 ins->inst_basereg == last_ins->inst_basereg &&
3194 ins->inst_offset == last_ins->inst_offset) {
3196 if (ins->dreg == last_ins->dreg) {
3197 MONO_DELETE_INS (bb, ins);
3200 ins->opcode = OP_MOVE;
3201 ins->sreg1 = last_ins->dreg;
3204 //g_assert_not_reached ();
3208 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3209 * OP_LOAD_MEMBASE offset(basereg), reg
3211 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3212 * OP_ICONST reg, imm
3214 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3215 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3216 ins->inst_basereg == last_ins->inst_destbasereg &&
3217 ins->inst_offset == last_ins->inst_offset) {
3218 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3219 ins->opcode = OP_ICONST;
3220 ins->inst_c0 = last_ins->inst_imm;
3221 g_assert_not_reached (); // check this rule
3225 case OP_LOADU1_MEMBASE:
3226 case OP_LOADI1_MEMBASE:
3227 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3228 ins->inst_basereg == last_ins->inst_destbasereg &&
3229 ins->inst_offset == last_ins->inst_offset) {
3230 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3231 ins->sreg1 = last_ins->sreg1;
3234 case OP_LOADU2_MEMBASE:
3235 case OP_LOADI2_MEMBASE:
3236 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3237 ins->inst_basereg == last_ins->inst_destbasereg &&
3238 ins->inst_offset == last_ins->inst_offset) {
3239 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3240 ins->sreg1 = last_ins->sreg1;
3244 ins->opcode = OP_MOVE;
3248 if (ins->dreg == ins->sreg1) {
3249 MONO_DELETE_INS (bb, ins);
3253 * OP_MOVE sreg, dreg
3254 * OP_MOVE dreg, sreg
3256 if (last_ins && last_ins->opcode == OP_MOVE &&
3257 ins->sreg1 == last_ins->dreg &&
3258 ins->dreg == last_ins->sreg1) {
3259 MONO_DELETE_INS (bb, ins);
3268 * the branch_cc_table should maintain the order of these
3282 branch_cc_table [] = {
3296 #define ADD_NEW_INS(cfg,dest,op) do { \
3297 MONO_INST_NEW ((cfg), (dest), (op)); \
3298 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3302 map_to_reg_reg_op (int op)
3311 case OP_COMPARE_IMM:
3313 case OP_ICOMPARE_IMM:
3327 case OP_LOAD_MEMBASE:
3328 return OP_LOAD_MEMINDEX;
3329 case OP_LOADI4_MEMBASE:
3330 return OP_LOADI4_MEMINDEX;
3331 case OP_LOADU4_MEMBASE:
3332 return OP_LOADU4_MEMINDEX;
3333 case OP_LOADU1_MEMBASE:
3334 return OP_LOADU1_MEMINDEX;
3335 case OP_LOADI2_MEMBASE:
3336 return OP_LOADI2_MEMINDEX;
3337 case OP_LOADU2_MEMBASE:
3338 return OP_LOADU2_MEMINDEX;
3339 case OP_LOADI1_MEMBASE:
3340 return OP_LOADI1_MEMINDEX;
3341 case OP_STOREI1_MEMBASE_REG:
3342 return OP_STOREI1_MEMINDEX;
3343 case OP_STOREI2_MEMBASE_REG:
3344 return OP_STOREI2_MEMINDEX;
3345 case OP_STOREI4_MEMBASE_REG:
3346 return OP_STOREI4_MEMINDEX;
3347 case OP_STORE_MEMBASE_REG:
3348 return OP_STORE_MEMINDEX;
3349 case OP_STORER4_MEMBASE_REG:
3350 return OP_STORER4_MEMINDEX;
3351 case OP_STORER8_MEMBASE_REG:
3352 return OP_STORER8_MEMINDEX;
3353 case OP_STORE_MEMBASE_IMM:
3354 return OP_STORE_MEMBASE_REG;
3355 case OP_STOREI1_MEMBASE_IMM:
3356 return OP_STOREI1_MEMBASE_REG;
3357 case OP_STOREI2_MEMBASE_IMM:
3358 return OP_STOREI2_MEMBASE_REG;
3359 case OP_STOREI4_MEMBASE_IMM:
3360 return OP_STOREI4_MEMBASE_REG;
3362 g_assert_not_reached ();
3366 * Remove from the instruction list the instructions that can't be
3367 * represented with very simple instructions with no register
3371 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3373 MonoInst *ins, *temp, *last_ins = NULL;
3374 int rot_amount, imm8, low_imm;
3376 MONO_BB_FOR_EACH_INS (bb, ins) {
3378 switch (ins->opcode) {
3382 case OP_COMPARE_IMM:
3383 case OP_ICOMPARE_IMM:
3397 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3398 int opcode2 = mono_op_imm_to_op (ins->opcode);
3399 ADD_NEW_INS (cfg, temp, OP_ICONST);
3400 temp->inst_c0 = ins->inst_imm;
3401 temp->dreg = mono_alloc_ireg (cfg);
3402 ins->sreg2 = temp->dreg;
3404 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3405 ins->opcode = opcode2;
3407 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3413 if (ins->inst_imm == 1) {
3414 ins->opcode = OP_MOVE;
3417 if (ins->inst_imm == 0) {
3418 ins->opcode = OP_ICONST;
3422 imm8 = mono_is_power_of_two (ins->inst_imm);
3424 ins->opcode = OP_SHL_IMM;
3425 ins->inst_imm = imm8;
3428 ADD_NEW_INS (cfg, temp, OP_ICONST);
3429 temp->inst_c0 = ins->inst_imm;
3430 temp->dreg = mono_alloc_ireg (cfg);
3431 ins->sreg2 = temp->dreg;
3432 ins->opcode = OP_IMUL;
3438 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3439 /* ARM sets the C flag to 1 if there was _no_ overflow */
3440 ins->next->opcode = OP_COND_EXC_NC;
3443 case OP_IDIV_UN_IMM:
3445 case OP_IREM_UN_IMM: {
3446 int opcode2 = mono_op_imm_to_op (ins->opcode);
3447 ADD_NEW_INS (cfg, temp, OP_ICONST);
3448 temp->inst_c0 = ins->inst_imm;
3449 temp->dreg = mono_alloc_ireg (cfg);
3450 ins->sreg2 = temp->dreg;
3452 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3453 ins->opcode = opcode2;
3456 case OP_LOCALLOC_IMM:
3457 ADD_NEW_INS (cfg, temp, OP_ICONST);
3458 temp->inst_c0 = ins->inst_imm;
3459 temp->dreg = mono_alloc_ireg (cfg);
3460 ins->sreg1 = temp->dreg;
3461 ins->opcode = OP_LOCALLOC;
3463 case OP_LOAD_MEMBASE:
3464 case OP_LOADI4_MEMBASE:
3465 case OP_LOADU4_MEMBASE:
3466 case OP_LOADU1_MEMBASE:
3467 /* we can do two things: load the immed in a register
3468 * and use an indexed load, or see if the immed can be
3469 * represented as an ad_imm + a load with a smaller offset
3470 * that fits. We just do the first for now, optimize later.
3472 if (arm_is_imm12 (ins->inst_offset))
3474 ADD_NEW_INS (cfg, temp, OP_ICONST);
3475 temp->inst_c0 = ins->inst_offset;
3476 temp->dreg = mono_alloc_ireg (cfg);
3477 ins->sreg2 = temp->dreg;
3478 ins->opcode = map_to_reg_reg_op (ins->opcode);
3480 case OP_LOADI2_MEMBASE:
3481 case OP_LOADU2_MEMBASE:
3482 case OP_LOADI1_MEMBASE:
3483 if (arm_is_imm8 (ins->inst_offset))
3485 ADD_NEW_INS (cfg, temp, OP_ICONST);
3486 temp->inst_c0 = ins->inst_offset;
3487 temp->dreg = mono_alloc_ireg (cfg);
3488 ins->sreg2 = temp->dreg;
3489 ins->opcode = map_to_reg_reg_op (ins->opcode);
3491 case OP_LOADR4_MEMBASE:
3492 case OP_LOADR8_MEMBASE:
3493 if (arm_is_fpimm8 (ins->inst_offset))
3495 low_imm = ins->inst_offset & 0x1ff;
3496 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3497 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3498 temp->inst_imm = ins->inst_offset & ~0x1ff;
3499 temp->sreg1 = ins->inst_basereg;
3500 temp->dreg = mono_alloc_ireg (cfg);
3501 ins->inst_basereg = temp->dreg;
3502 ins->inst_offset = low_imm;
3506 ADD_NEW_INS (cfg, temp, OP_ICONST);
3507 temp->inst_c0 = ins->inst_offset;
3508 temp->dreg = mono_alloc_ireg (cfg);
3510 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3511 add_ins->sreg1 = ins->inst_basereg;
3512 add_ins->sreg2 = temp->dreg;
3513 add_ins->dreg = mono_alloc_ireg (cfg);
3515 ins->inst_basereg = add_ins->dreg;
3516 ins->inst_offset = 0;
3519 case OP_STORE_MEMBASE_REG:
3520 case OP_STOREI4_MEMBASE_REG:
3521 case OP_STOREI1_MEMBASE_REG:
3522 if (arm_is_imm12 (ins->inst_offset))
3524 ADD_NEW_INS (cfg, temp, OP_ICONST);
3525 temp->inst_c0 = ins->inst_offset;
3526 temp->dreg = mono_alloc_ireg (cfg);
3527 ins->sreg2 = temp->dreg;
3528 ins->opcode = map_to_reg_reg_op (ins->opcode);
3530 case OP_STOREI2_MEMBASE_REG:
3531 if (arm_is_imm8 (ins->inst_offset))
3533 ADD_NEW_INS (cfg, temp, OP_ICONST);
3534 temp->inst_c0 = ins->inst_offset;
3535 temp->dreg = mono_alloc_ireg (cfg);
3536 ins->sreg2 = temp->dreg;
3537 ins->opcode = map_to_reg_reg_op (ins->opcode);
3539 case OP_STORER4_MEMBASE_REG:
3540 case OP_STORER8_MEMBASE_REG:
3541 if (arm_is_fpimm8 (ins->inst_offset))
3543 low_imm = ins->inst_offset & 0x1ff;
3544 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3545 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3546 temp->inst_imm = ins->inst_offset & ~0x1ff;
3547 temp->sreg1 = ins->inst_destbasereg;
3548 temp->dreg = mono_alloc_ireg (cfg);
3549 ins->inst_destbasereg = temp->dreg;
3550 ins->inst_offset = low_imm;
3554 ADD_NEW_INS (cfg, temp, OP_ICONST);
3555 temp->inst_c0 = ins->inst_offset;
3556 temp->dreg = mono_alloc_ireg (cfg);
3558 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3559 add_ins->sreg1 = ins->inst_destbasereg;
3560 add_ins->sreg2 = temp->dreg;
3561 add_ins->dreg = mono_alloc_ireg (cfg);
3563 ins->inst_destbasereg = add_ins->dreg;
3564 ins->inst_offset = 0;
3567 case OP_STORE_MEMBASE_IMM:
3568 case OP_STOREI1_MEMBASE_IMM:
3569 case OP_STOREI2_MEMBASE_IMM:
3570 case OP_STOREI4_MEMBASE_IMM:
3571 ADD_NEW_INS (cfg, temp, OP_ICONST);
3572 temp->inst_c0 = ins->inst_imm;
3573 temp->dreg = mono_alloc_ireg (cfg);
3574 ins->sreg1 = temp->dreg;
3575 ins->opcode = map_to_reg_reg_op (ins->opcode);
3577 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3580 gboolean swap = FALSE;
3584 /* Optimized away */
3589 /* Some fp compares require swapped operands */
3590 switch (ins->next->opcode) {
3592 ins->next->opcode = OP_FBLT;
3596 ins->next->opcode = OP_FBLT_UN;
3600 ins->next->opcode = OP_FBGE;
3604 ins->next->opcode = OP_FBGE_UN;
3612 ins->sreg1 = ins->sreg2;
3621 bb->last_ins = last_ins;
3622 bb->max_vreg = cfg->next_vreg;
3626 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3630 if (long_ins->opcode == OP_LNEG) {
3632 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3633 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3639 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3641 /* sreg is a float, dreg is an integer reg */
3643 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3645 ARM_TOSIZD (code, vfp_scratch1, sreg);
3647 ARM_TOUIZD (code, vfp_scratch1, sreg);
3648 ARM_FMRS (code, dreg, vfp_scratch1);
3649 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3653 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3654 else if (size == 2) {
3655 ARM_SHL_IMM (code, dreg, dreg, 16);
3656 ARM_SHR_IMM (code, dreg, dreg, 16);
3660 ARM_SHL_IMM (code, dreg, dreg, 24);
3661 ARM_SAR_IMM (code, dreg, dreg, 24);
3662 } else if (size == 2) {
3663 ARM_SHL_IMM (code, dreg, dreg, 16);
3664 ARM_SAR_IMM (code, dreg, dreg, 16);
3671 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3673 /* sreg is a float, dreg is an integer reg */
3675 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3677 ARM_TOSIZS (code, vfp_scratch1, sreg);
3679 ARM_TOUIZS (code, vfp_scratch1, sreg);
3680 ARM_FMRS (code, dreg, vfp_scratch1);
3681 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3685 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3686 else if (size == 2) {
3687 ARM_SHL_IMM (code, dreg, dreg, 16);
3688 ARM_SHR_IMM (code, dreg, dreg, 16);
3692 ARM_SHL_IMM (code, dreg, dreg, 24);
3693 ARM_SAR_IMM (code, dreg, dreg, 24);
3694 } else if (size == 2) {
3695 ARM_SHL_IMM (code, dreg, dreg, 16);
3696 ARM_SAR_IMM (code, dreg, dreg, 16);
3702 #endif /* #ifndef DISABLE_JIT */
3704 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3707 emit_thunk (guint8 *code, gconstpointer target)
3711 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3712 if (thumb_supported)
3713 ARM_BX (code, ARMREG_IP);
3715 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3716 *(guint32*)code = (guint32)target;
3718 mono_arch_flush_icache (p, code - p);
3722 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3724 MonoJitInfo *ji = NULL;
3725 MonoThunkJitInfo *info;
3728 guint8 *orig_target;
3729 guint8 *target_thunk;
3732 domain = mono_domain_get ();
3736 * This can be called multiple times during JITting,
3737 * save the current position in cfg->arch to avoid
3738 * doing a O(n^2) search.
3740 if (!cfg->arch.thunks) {
3741 cfg->arch.thunks = cfg->thunks;
3742 cfg->arch.thunks_size = cfg->thunk_area;
3744 thunks = cfg->arch.thunks;
3745 thunks_size = cfg->arch.thunks_size;
3747 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3748 g_assert_not_reached ();
3751 g_assert (*(guint32*)thunks == 0);
3752 emit_thunk (thunks, target);
3753 arm_patch (code, thunks);
3755 cfg->arch.thunks += THUNK_SIZE;
3756 cfg->arch.thunks_size -= THUNK_SIZE;
3758 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3760 info = mono_jit_info_get_thunk_info (ji);
3763 thunks = (guint8*)ji->code_start + info->thunks_offset;
3764 thunks_size = info->thunks_size;
3766 orig_target = mono_arch_get_call_target (code + 4);
3768 mono_mini_arch_lock ();
3770 target_thunk = NULL;
3771 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3772 /* The call already points to a thunk, because of trampolines etc. */
3773 target_thunk = orig_target;
3775 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3776 if (((guint32*)p) [0] == 0) {
3780 } else if (((guint32*)p) [2] == (guint32)target) {
3781 /* Thunk already points to target */
3788 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3790 if (!target_thunk) {
3791 mono_mini_arch_unlock ();
3792 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3793 g_assert_not_reached ();
3796 emit_thunk (target_thunk, target);
3797 arm_patch (code, target_thunk);
3798 mono_arch_flush_icache (code, 4);
3800 mono_mini_arch_unlock ();
3805 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3807 guint32 *code32 = (void*)code;
3808 guint32 ins = *code32;
3809 guint32 prim = (ins >> 25) & 7;
3810 guint32 tval = GPOINTER_TO_UINT (target);
3812 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3813 if (prim == 5) { /* 101b */
3814 /* the diff starts 8 bytes from the branch opcode */
3815 gint diff = target - code - 8;
3817 gint tmask = 0xffffffff;
3818 if (tval & 1) { /* entering thumb mode */
3819 diff = target - 1 - code - 8;
3820 g_assert (thumb_supported);
3821 tbits = 0xf << 28; /* bl->blx bit pattern */
3822 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3823 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3827 tmask = ~(1 << 24); /* clear the link bit */
3828 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3833 if (diff <= 33554431) {
3835 ins = (ins & 0xff000000) | diff;
3837 *code32 = ins | tbits;
3841 /* diff between 0 and -33554432 */
3842 if (diff >= -33554432) {
3844 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3846 *code32 = ins | tbits;
3851 handle_thunk (cfg, domain, code, target);
3856 * The alternative call sequences looks like this:
3858 * ldr ip, [pc] // loads the address constant
3859 * b 1f // jumps around the constant
3860 * address constant embedded in the code
3865 * There are two cases for patching:
3866 * a) at the end of method emission: in this case code points to the start
3867 * of the call sequence
3868 * b) during runtime patching of the call site: in this case code points
3869 * to the mov pc, ip instruction
3871 * We have to handle also the thunk jump code sequence:
3875 * address constant // execution never reaches here
3877 if ((ins & 0x0ffffff0) == 0x12fff10) {
3878 /* Branch and exchange: the address is constructed in a reg
3879 * We can patch BX when the code sequence is the following:
3880 * ldr ip, [pc, #0] ; 0x8
3887 guint8 *emit = (guint8*)ccode;
3888 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3890 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3891 ARM_BX (emit, ARMREG_IP);
3893 /*patching from magic trampoline*/
3894 if (ins == ccode [3]) {
3895 g_assert (code32 [-4] == ccode [0]);
3896 g_assert (code32 [-3] == ccode [1]);
3897 g_assert (code32 [-1] == ccode [2]);
3898 code32 [-2] = (guint32)target;
3901 /*patching from JIT*/
3902 if (ins == ccode [0]) {
3903 g_assert (code32 [1] == ccode [1]);
3904 g_assert (code32 [3] == ccode [2]);
3905 g_assert (code32 [4] == ccode [3]);
3906 code32 [2] = (guint32)target;
3909 g_assert_not_reached ();
3910 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3918 guint8 *emit = (guint8*)ccode;
3919 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3921 ARM_BLX_REG (emit, ARMREG_IP);
3923 g_assert (code32 [-3] == ccode [0]);
3924 g_assert (code32 [-2] == ccode [1]);
3925 g_assert (code32 [0] == ccode [2]);
3927 code32 [-1] = (guint32)target;
3930 guint32 *tmp = ccode;
3931 guint8 *emit = (guint8*)tmp;
3932 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3933 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3934 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3935 ARM_BX (emit, ARMREG_IP);
3936 if (ins == ccode [2]) {
3937 g_assert_not_reached (); // should be -2 ...
3938 code32 [-1] = (guint32)target;
3941 if (ins == ccode [0]) {
3942 /* handles both thunk jump code and the far call sequence */
3943 code32 [2] = (guint32)target;
3946 g_assert_not_reached ();
3948 // g_print ("patched with 0x%08x\n", ins);
3952 arm_patch (guchar *code, const guchar *target)
3954 arm_patch_general (NULL, NULL, code, target);
3958 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3959 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3960 * to be used with the emit macros.
3961 * Return -1 otherwise.
3964 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3967 for (i = 0; i < 31; i+= 2) {
3968 res = (val << (32 - i)) | (val >> i);
3971 *rot_amount = i? 32 - i: 0;
3978 * Emits in code a sequence of instructions that load the value 'val'
3979 * into the dreg register. Uses at most 4 instructions.
3982 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3984 int imm8, rot_amount;
3986 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3987 /* skip the constant pool */
3993 if (mini_get_debug_options()->single_imm_size && v7_supported) {
3994 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3995 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3999 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4000 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4001 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4002 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4005 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4007 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4011 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4013 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4015 if (val & 0xFF0000) {
4016 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4018 if (val & 0xFF000000) {
4019 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4021 } else if (val & 0xFF00) {
4022 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4023 if (val & 0xFF0000) {
4024 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4026 if (val & 0xFF000000) {
4027 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4029 } else if (val & 0xFF0000) {
4030 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4031 if (val & 0xFF000000) {
4032 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4035 //g_assert_not_reached ();
4041 mono_arm_thumb_supported (void)
4043 return thumb_supported;
4049 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4054 call = (MonoCallInst*)ins;
4055 cinfo = call->call_info;
4057 switch (cinfo->ret.storage) {
4058 case RegTypeStructByVal:
4060 MonoInst *loc = cfg->arch.vret_addr_loc;
4063 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4064 /* The JIT treats this as a normal call */
4068 /* Load the destination address */
4069 g_assert (loc && loc->opcode == OP_REGOFFSET);
4071 if (arm_is_imm12 (loc->inst_offset)) {
4072 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4074 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4075 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4078 if (cinfo->ret.storage == RegTypeStructByVal) {
4079 int rsize = cinfo->ret.struct_size;
4081 for (i = 0; i < cinfo->ret.nregs; ++i) {
4082 g_assert (rsize >= 0);
4087 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4090 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4093 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4099 for (i = 0; i < cinfo->ret.nregs; ++i) {
4100 if (cinfo->ret.esize == 4)
4101 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4103 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4112 switch (ins->opcode) {
4115 case OP_FCALL_MEMBASE:
4117 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4118 if (sig_ret->type == MONO_TYPE_R4) {
4119 if (IS_HARD_FLOAT) {
4120 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4122 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4123 ARM_CVTS (code, ins->dreg, ins->dreg);
4126 if (IS_HARD_FLOAT) {
4127 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4129 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4136 case OP_RCALL_MEMBASE: {
4141 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4142 g_assert (sig_ret->type == MONO_TYPE_R4);
4143 if (IS_HARD_FLOAT) {
4144 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4146 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4147 ARM_CPYS (code, ins->dreg, ins->dreg);
4159 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4164 guint8 *code = cfg->native_code + cfg->code_len;
4165 MonoInst *last_ins = NULL;
4166 guint last_offset = 0;
4168 int imm8, rot_amount;
4170 /* we don't align basic blocks of loops on arm */
4172 if (cfg->verbose_level > 2)
4173 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4175 cpos = bb->max_offset;
4177 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4178 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4179 //g_assert (!mono_compile_aot);
4182 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4183 /* this is not thread save, but good enough */
4184 /* fixme: howto handle overflows? */
4185 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4188 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4189 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4190 (gpointer)"mono_break");
4191 code = emit_call_seq (cfg, code);
4194 MONO_BB_FOR_EACH_INS (bb, ins) {
4195 offset = code - cfg->native_code;
4197 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4199 if (offset > (cfg->code_size - max_len - 16)) {
4200 cfg->code_size *= 2;
4201 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4202 code = cfg->native_code + offset;
4204 // if (ins->cil_code)
4205 // g_print ("cil code\n");
4206 mono_debug_record_line_number (cfg, ins, offset);
4208 switch (ins->opcode) {
4209 case OP_MEMORY_BARRIER:
4211 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4212 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4216 code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4219 code = emit_tls_set (code, ins->sreg1, ins->inst_offset);
4221 case OP_ATOMIC_EXCHANGE_I4:
4222 case OP_ATOMIC_CAS_I4:
4223 case OP_ATOMIC_ADD_I4: {
4227 g_assert (v7_supported);
4230 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4232 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4234 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4238 g_assert (cfg->arch.atomic_tmp_offset != -1);
4239 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4241 switch (ins->opcode) {
4242 case OP_ATOMIC_EXCHANGE_I4:
4244 ARM_DMB (code, ARM_DMB_SY);
4245 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4246 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4247 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4249 ARM_B_COND (code, ARMCOND_NE, 0);
4250 arm_patch (buf [1], buf [0]);
4252 case OP_ATOMIC_CAS_I4:
4253 ARM_DMB (code, ARM_DMB_SY);
4255 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4256 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4258 ARM_B_COND (code, ARMCOND_NE, 0);
4259 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4260 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4262 ARM_B_COND (code, ARMCOND_NE, 0);
4263 arm_patch (buf [2], buf [0]);
4264 arm_patch (buf [1], code);
4266 case OP_ATOMIC_ADD_I4:
4268 ARM_DMB (code, ARM_DMB_SY);
4269 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4270 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4271 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4272 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4274 ARM_B_COND (code, ARMCOND_NE, 0);
4275 arm_patch (buf [1], buf [0]);
4278 g_assert_not_reached ();
4281 ARM_DMB (code, ARM_DMB_SY);
4282 if (tmpreg != ins->dreg)
4283 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4284 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4287 case OP_ATOMIC_LOAD_I1:
4288 case OP_ATOMIC_LOAD_U1:
4289 case OP_ATOMIC_LOAD_I2:
4290 case OP_ATOMIC_LOAD_U2:
4291 case OP_ATOMIC_LOAD_I4:
4292 case OP_ATOMIC_LOAD_U4:
4293 case OP_ATOMIC_LOAD_R4:
4294 case OP_ATOMIC_LOAD_R8: {
4295 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4296 ARM_DMB (code, ARM_DMB_SY);
4298 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4300 switch (ins->opcode) {
4301 case OP_ATOMIC_LOAD_I1:
4302 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4304 case OP_ATOMIC_LOAD_U1:
4305 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4307 case OP_ATOMIC_LOAD_I2:
4308 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4310 case OP_ATOMIC_LOAD_U2:
4311 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4313 case OP_ATOMIC_LOAD_I4:
4314 case OP_ATOMIC_LOAD_U4:
4315 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4317 case OP_ATOMIC_LOAD_R4:
4319 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4320 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4322 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4323 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4324 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4325 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4326 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4329 case OP_ATOMIC_LOAD_R8:
4330 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4331 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4335 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4336 ARM_DMB (code, ARM_DMB_SY);
4339 case OP_ATOMIC_STORE_I1:
4340 case OP_ATOMIC_STORE_U1:
4341 case OP_ATOMIC_STORE_I2:
4342 case OP_ATOMIC_STORE_U2:
4343 case OP_ATOMIC_STORE_I4:
4344 case OP_ATOMIC_STORE_U4:
4345 case OP_ATOMIC_STORE_R4:
4346 case OP_ATOMIC_STORE_R8: {
4347 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4348 ARM_DMB (code, ARM_DMB_SY);
4350 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4352 switch (ins->opcode) {
4353 case OP_ATOMIC_STORE_I1:
4354 case OP_ATOMIC_STORE_U1:
4355 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4357 case OP_ATOMIC_STORE_I2:
4358 case OP_ATOMIC_STORE_U2:
4359 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4361 case OP_ATOMIC_STORE_I4:
4362 case OP_ATOMIC_STORE_U4:
4363 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4365 case OP_ATOMIC_STORE_R4:
4367 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4368 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4370 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4371 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4372 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4373 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4374 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4377 case OP_ATOMIC_STORE_R8:
4378 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4379 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4383 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4384 ARM_DMB (code, ARM_DMB_SY);
4388 ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4391 ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4393 case OP_STOREI1_MEMBASE_IMM:
4394 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4395 g_assert (arm_is_imm12 (ins->inst_offset));
4396 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4398 case OP_STOREI2_MEMBASE_IMM:
4399 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4400 g_assert (arm_is_imm8 (ins->inst_offset));
4401 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4403 case OP_STORE_MEMBASE_IMM:
4404 case OP_STOREI4_MEMBASE_IMM:
4405 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4406 g_assert (arm_is_imm12 (ins->inst_offset));
4407 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4409 case OP_STOREI1_MEMBASE_REG:
4410 g_assert (arm_is_imm12 (ins->inst_offset));
4411 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4413 case OP_STOREI2_MEMBASE_REG:
4414 g_assert (arm_is_imm8 (ins->inst_offset));
4415 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4417 case OP_STORE_MEMBASE_REG:
4418 case OP_STOREI4_MEMBASE_REG:
4419 /* this case is special, since it happens for spill code after lowering has been called */
4420 if (arm_is_imm12 (ins->inst_offset)) {
4421 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4423 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4424 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4427 case OP_STOREI1_MEMINDEX:
4428 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4430 case OP_STOREI2_MEMINDEX:
4431 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4433 case OP_STORE_MEMINDEX:
4434 case OP_STOREI4_MEMINDEX:
4435 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4438 g_assert_not_reached ();
4440 case OP_LOAD_MEMINDEX:
4441 case OP_LOADI4_MEMINDEX:
4442 case OP_LOADU4_MEMINDEX:
4443 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4445 case OP_LOADI1_MEMINDEX:
4446 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4448 case OP_LOADU1_MEMINDEX:
4449 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4451 case OP_LOADI2_MEMINDEX:
4452 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4454 case OP_LOADU2_MEMINDEX:
4455 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4457 case OP_LOAD_MEMBASE:
4458 case OP_LOADI4_MEMBASE:
4459 case OP_LOADU4_MEMBASE:
4460 /* this case is special, since it happens for spill code after lowering has been called */
4461 if (arm_is_imm12 (ins->inst_offset)) {
4462 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4464 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4465 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4468 case OP_LOADI1_MEMBASE:
4469 g_assert (arm_is_imm8 (ins->inst_offset));
4470 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4472 case OP_LOADU1_MEMBASE:
4473 g_assert (arm_is_imm12 (ins->inst_offset));
4474 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4476 case OP_LOADU2_MEMBASE:
4477 g_assert (arm_is_imm8 (ins->inst_offset));
4478 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4480 case OP_LOADI2_MEMBASE:
4481 g_assert (arm_is_imm8 (ins->inst_offset));
4482 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4484 case OP_ICONV_TO_I1:
4485 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4486 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4488 case OP_ICONV_TO_I2:
4489 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4490 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4492 case OP_ICONV_TO_U1:
4493 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4495 case OP_ICONV_TO_U2:
4496 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4497 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4501 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4503 case OP_COMPARE_IMM:
4504 case OP_ICOMPARE_IMM:
4505 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4506 g_assert (imm8 >= 0);
4507 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4511 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4512 * So instead of emitting a trap, we emit a call a C function and place a
4515 //*(int*)code = 0xef9f0001;
4518 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4519 (gpointer)"mono_break");
4520 code = emit_call_seq (cfg, code);
4522 case OP_RELAXED_NOP:
4527 case OP_DUMMY_STORE:
4528 case OP_DUMMY_ICONST:
4529 case OP_DUMMY_R8CONST:
4530 case OP_NOT_REACHED:
4533 case OP_IL_SEQ_POINT:
4534 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4536 case OP_SEQ_POINT: {
4538 MonoInst *info_var = cfg->arch.seq_point_info_var;
4539 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4540 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4541 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4543 int dreg = ARMREG_LR;
4546 if (cfg->soft_breakpoints) {
4547 g_assert (!cfg->compile_aot);
4552 * For AOT, we use one got slot per method, which will point to a
4553 * SeqPointInfo structure, containing all the information required
4554 * by the code below.
4556 if (cfg->compile_aot) {
4557 g_assert (info_var);
4558 g_assert (info_var->opcode == OP_REGOFFSET);
4559 g_assert (arm_is_imm12 (info_var->inst_offset));
4562 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4564 * Read from the single stepping trigger page. This will cause a
4565 * SIGSEGV when single stepping is enabled.
4566 * We do this _before_ the breakpoint, so single stepping after
4567 * a breakpoint is hit will step to the next IL offset.
4569 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4572 /* Single step check */
4573 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4574 if (cfg->soft_breakpoints) {
4575 /* Load the address of the sequence point method variable. */
4576 var = ss_method_var;
4578 g_assert (var->opcode == OP_REGOFFSET);
4579 g_assert (arm_is_imm12 (var->inst_offset));
4580 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4582 /* Read the value and check whether it is non-zero. */
4583 ARM_LDR_IMM (code, dreg, dreg, 0);
4584 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4585 /* Call it conditionally. */
4586 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4588 if (cfg->compile_aot) {
4589 /* Load the trigger page addr from the variable initialized in the prolog */
4590 var = ss_trigger_page_var;
4592 g_assert (var->opcode == OP_REGOFFSET);
4593 g_assert (arm_is_imm12 (var->inst_offset));
4594 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4596 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4598 *(int*)code = (int)ss_trigger_page;
4601 ARM_LDR_IMM (code, dreg, dreg, 0);
4605 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4607 /* Breakpoint check */
4608 if (cfg->compile_aot) {
4609 guint32 offset = code - cfg->native_code;
4612 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4613 /* Add the offset */
4614 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4615 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4616 if (arm_is_imm12 ((int)val)) {
4617 ARM_LDR_IMM (code, dreg, dreg, val);
4619 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4621 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4623 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4624 g_assert (!(val & 0xFF000000));
4626 ARM_LDR_IMM (code, dreg, dreg, 0);
4628 /* What is faster, a branch or a load ? */
4629 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4630 /* The breakpoint instruction */
4631 if (cfg->soft_breakpoints)
4632 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4634 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4635 } else if (cfg->soft_breakpoints) {
4636 /* Load the address of the breakpoint method into ip. */
4637 var = bp_method_var;
4639 g_assert (var->opcode == OP_REGOFFSET);
4640 g_assert (arm_is_imm12 (var->inst_offset));
4641 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4644 * A placeholder for a possible breakpoint inserted by
4645 * mono_arch_set_breakpoint ().
4650 * A placeholder for a possible breakpoint inserted by
4651 * mono_arch_set_breakpoint ().
4653 for (i = 0; i < 4; ++i)
4658 * Add an additional nop so skipping the bp doesn't cause the ip to point
4659 * to another IL offset.
4667 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4670 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4674 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4677 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4678 g_assert (imm8 >= 0);
4679 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4683 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4684 g_assert (imm8 >= 0);
4685 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4689 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4690 g_assert (imm8 >= 0);
4691 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4694 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4695 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4697 case OP_IADD_OVF_UN:
4698 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4699 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4702 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4703 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4705 case OP_ISUB_OVF_UN:
4706 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4707 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4709 case OP_ADD_OVF_CARRY:
4710 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4711 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4713 case OP_ADD_OVF_UN_CARRY:
4714 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4715 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4717 case OP_SUB_OVF_CARRY:
4718 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4719 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4721 case OP_SUB_OVF_UN_CARRY:
4722 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4723 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4727 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4730 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4731 g_assert (imm8 >= 0);
4732 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4735 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4739 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4743 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4744 g_assert (imm8 >= 0);
4745 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4749 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4750 g_assert (imm8 >= 0);
4751 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4753 case OP_ARM_RSBS_IMM:
4754 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4755 g_assert (imm8 >= 0);
4756 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4758 case OP_ARM_RSC_IMM:
4759 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4760 g_assert (imm8 >= 0);
4761 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4764 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4768 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4769 g_assert (imm8 >= 0);
4770 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4773 g_assert (v7s_supported || v7k_supported);
4774 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4777 g_assert (v7s_supported || v7k_supported);
4778 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4781 g_assert (v7s_supported || v7k_supported);
4782 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4783 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4786 g_assert (v7s_supported || v7k_supported);
4787 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4788 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4792 g_assert_not_reached ();
4794 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4798 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4799 g_assert (imm8 >= 0);
4800 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4803 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4807 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4808 g_assert (imm8 >= 0);
4809 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4812 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4817 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4818 else if (ins->dreg != ins->sreg1)
4819 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4822 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4827 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4828 else if (ins->dreg != ins->sreg1)
4829 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4832 case OP_ISHR_UN_IMM:
4834 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4835 else if (ins->dreg != ins->sreg1)
4836 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4839 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4842 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4845 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4848 if (ins->dreg == ins->sreg2)
4849 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4851 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4854 g_assert_not_reached ();
4857 /* FIXME: handle ovf/ sreg2 != dreg */
4858 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4859 /* FIXME: MUL doesn't set the C/O flags on ARM */
4861 case OP_IMUL_OVF_UN:
4862 /* FIXME: handle ovf/ sreg2 != dreg */
4863 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4864 /* FIXME: MUL doesn't set the C/O flags on ARM */
4867 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4870 /* Load the GOT offset */
4871 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4872 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4874 *(gpointer*)code = NULL;
4876 /* Load the value from the GOT */
4877 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4879 case OP_OBJC_GET_SELECTOR:
4880 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4881 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4883 *(gpointer*)code = NULL;
4885 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4887 case OP_ICONV_TO_I4:
4888 case OP_ICONV_TO_U4:
4890 if (ins->dreg != ins->sreg1)
4891 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4894 int saved = ins->sreg2;
4895 if (ins->sreg2 == ARM_LSW_REG) {
4896 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4899 if (ins->sreg1 != ARM_LSW_REG)
4900 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4901 if (saved != ARM_MSW_REG)
4902 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4906 if (IS_VFP && ins->dreg != ins->sreg1)
4907 ARM_CPYD (code, ins->dreg, ins->sreg1);
4910 if (IS_VFP && ins->dreg != ins->sreg1)
4911 ARM_CPYS (code, ins->dreg, ins->sreg1);
4913 case OP_MOVE_F_TO_I4:
4915 ARM_FMRS (code, ins->dreg, ins->sreg1);
4917 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4918 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4919 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4920 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4923 case OP_MOVE_I4_TO_F:
4925 ARM_FMSR (code, ins->dreg, ins->sreg1);
4927 ARM_FMSR (code, ins->dreg, ins->sreg1);
4928 ARM_CVTS (code, ins->dreg, ins->dreg);
4931 case OP_FCONV_TO_R4:
4934 ARM_CVTD (code, ins->dreg, ins->sreg1);
4936 ARM_CVTD (code, ins->dreg, ins->sreg1);
4937 ARM_CVTS (code, ins->dreg, ins->dreg);
4942 MonoCallInst *call = (MonoCallInst*)ins;
4945 * The stack looks like the following:
4946 * <caller argument area>
4949 * <callee argument area>
4950 * Need to copy the arguments from the callee argument area to
4951 * the caller argument area, and pop the frame.
4953 if (call->stack_usage) {
4954 int i, prev_sp_offset = 0;
4956 /* Compute size of saved registers restored below */
4958 prev_sp_offset = 2 * 4;
4960 prev_sp_offset = 1 * 4;
4961 for (i = 0; i < 16; ++i) {
4962 if (cfg->used_int_regs & (1 << i))
4963 prev_sp_offset += 4;
4966 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4968 /* Copy arguments on the stack to our argument area */
4969 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4970 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4971 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4976 * Keep in sync with mono_arch_emit_epilog
4978 g_assert (!cfg->method->save_lmf);
4980 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4982 if (cfg->used_int_regs)
4983 ARM_POP (code, cfg->used_int_regs);
4984 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4986 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4989 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4990 if (cfg->compile_aot) {
4991 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4993 *(gpointer*)code = NULL;
4995 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4997 code = mono_arm_patchable_b (code, ARMCOND_AL);
4998 cfg->thunk_area += THUNK_SIZE;
5003 /* ensure ins->sreg1 is not NULL */
5004 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5007 g_assert (cfg->sig_cookie < 128);
5008 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5009 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5019 call = (MonoCallInst*)ins;
5022 code = emit_float_args (cfg, call, code, &max_len, &offset);
5024 if (ins->flags & MONO_INST_HAS_METHOD)
5025 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5027 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5028 code = emit_call_seq (cfg, code);
5029 ins->flags |= MONO_INST_GC_CALLSITE;
5030 ins->backend.pc_offset = code - cfg->native_code;
5031 code = emit_move_return_value (cfg, ins, code);
5038 case OP_VOIDCALL_REG:
5041 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5043 code = emit_call_reg (code, ins->sreg1);
5044 ins->flags |= MONO_INST_GC_CALLSITE;
5045 ins->backend.pc_offset = code - cfg->native_code;
5046 code = emit_move_return_value (cfg, ins, code);
5048 case OP_FCALL_MEMBASE:
5049 case OP_RCALL_MEMBASE:
5050 case OP_LCALL_MEMBASE:
5051 case OP_VCALL_MEMBASE:
5052 case OP_VCALL2_MEMBASE:
5053 case OP_VOIDCALL_MEMBASE:
5054 case OP_CALL_MEMBASE: {
5055 g_assert (ins->sreg1 != ARMREG_LR);
5056 call = (MonoCallInst*)ins;
5059 code = emit_float_args (cfg, call, code, &max_len, &offset);
5060 if (!arm_is_imm12 (ins->inst_offset)) {
5061 /* sreg1 might be IP */
5062 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5063 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5064 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5065 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5066 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5068 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5069 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5071 ins->flags |= MONO_INST_GC_CALLSITE;
5072 ins->backend.pc_offset = code - cfg->native_code;
5073 code = emit_move_return_value (cfg, ins, code);
5076 case OP_GENERIC_CLASS_INIT: {
5080 byte_offset = MONO_STRUCT_OFFSET (MonoVTable, initialized);
5082 g_assert (arm_is_imm8 (byte_offset));
5083 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5084 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5086 ARM_B_COND (code, ARMCOND_NE, 0);
5088 /* Uninitialized case */
5089 g_assert (ins->sreg1 == ARMREG_R0);
5091 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5092 (gpointer)"mono_generic_class_init");
5093 code = emit_call_seq (cfg, code);
5095 /* Initialized case */
5096 arm_patch (jump, code);
5100 /* round the size to 8 bytes */
5101 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5102 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5103 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5104 /* memzero the area: dreg holds the size, sp is the pointer */
5105 if (ins->flags & MONO_INST_INIT) {
5106 guint8 *start_loop, *branch_to_cond;
5107 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5108 branch_to_cond = code;
5111 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5112 arm_patch (branch_to_cond, code);
5113 /* decrement by 4 and set flags */
5114 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5115 ARM_B_COND (code, ARMCOND_GE, 0);
5116 arm_patch (code - 4, start_loop);
5118 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5119 if (cfg->param_area)
5120 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5125 MonoInst *var = cfg->dyn_call_var;
5128 g_assert (var->opcode == OP_REGOFFSET);
5129 g_assert (arm_is_imm12 (var->inst_offset));
5131 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5132 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5134 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5136 /* Save args buffer */
5137 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5139 /* Set stack slots using R0 as scratch reg */
5140 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5141 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5142 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5143 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5146 /* Set fp argument registers */
5147 if (IS_HARD_FLOAT) {
5148 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5149 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5151 ARM_B_COND (code, ARMCOND_EQ, 0);
5152 for (i = 0; i < FP_PARAM_REGS; ++i) {
5153 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5154 g_assert (arm_is_fpimm8 (offset));
5155 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5157 arm_patch (buf [0], code);
5160 /* Set argument registers */
5161 for (i = 0; i < PARAM_REGS; ++i)
5162 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5165 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5166 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5169 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5170 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5171 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5173 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5177 if (ins->sreg1 != ARMREG_R0)
5178 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5179 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5180 (gpointer)"mono_arch_throw_exception");
5181 code = emit_call_seq (cfg, code);
5185 if (ins->sreg1 != ARMREG_R0)
5186 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5187 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5188 (gpointer)"mono_arch_rethrow_exception");
5189 code = emit_call_seq (cfg, code);
5192 case OP_START_HANDLER: {
5193 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5194 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5197 /* Reserve a param area, see filter-stack.exe */
5199 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5200 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5202 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5203 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5207 if (arm_is_imm12 (spvar->inst_offset)) {
5208 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5210 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5211 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5215 case OP_ENDFILTER: {
5216 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5217 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5220 /* Free the param area */
5222 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5223 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5225 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5226 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5230 if (ins->sreg1 != ARMREG_R0)
5231 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5232 if (arm_is_imm12 (spvar->inst_offset)) {
5233 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5235 g_assert (ARMREG_IP != spvar->inst_basereg);
5236 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5237 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5239 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5242 case OP_ENDFINALLY: {
5243 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5244 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5247 /* Free the param area */
5249 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5250 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5252 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5253 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5257 if (arm_is_imm12 (spvar->inst_offset)) {
5258 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5260 g_assert (ARMREG_IP != spvar->inst_basereg);
5261 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5262 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5264 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5267 case OP_CALL_HANDLER:
5268 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5269 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5270 cfg->thunk_area += THUNK_SIZE;
5271 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5274 if (ins->dreg != ARMREG_R0)
5275 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5279 ins->inst_c0 = code - cfg->native_code;
5282 /*if (ins->inst_target_bb->native_offset) {
5284 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5286 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5287 code = mono_arm_patchable_b (code, ARMCOND_AL);
5291 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5295 * In the normal case we have:
5296 * ldr pc, [pc, ins->sreg1 << 2]
5299 * ldr lr, [pc, ins->sreg1 << 2]
5301 * After follows the data.
5302 * FIXME: add aot support.
5304 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5305 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5306 if (offset + max_len > (cfg->code_size - 16)) {
5307 cfg->code_size += max_len;
5308 cfg->code_size *= 2;
5309 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5310 code = cfg->native_code + offset;
5312 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5314 code += 4 * GPOINTER_TO_INT (ins->klass);
5318 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5319 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5323 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5324 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5328 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5329 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5333 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5334 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5338 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5339 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5342 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5343 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5346 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5347 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5350 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5351 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5354 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5355 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5358 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5359 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5361 case OP_COND_EXC_EQ:
5362 case OP_COND_EXC_NE_UN:
5363 case OP_COND_EXC_LT:
5364 case OP_COND_EXC_LT_UN:
5365 case OP_COND_EXC_GT:
5366 case OP_COND_EXC_GT_UN:
5367 case OP_COND_EXC_GE:
5368 case OP_COND_EXC_GE_UN:
5369 case OP_COND_EXC_LE:
5370 case OP_COND_EXC_LE_UN:
5371 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5373 case OP_COND_EXC_IEQ:
5374 case OP_COND_EXC_INE_UN:
5375 case OP_COND_EXC_ILT:
5376 case OP_COND_EXC_ILT_UN:
5377 case OP_COND_EXC_IGT:
5378 case OP_COND_EXC_IGT_UN:
5379 case OP_COND_EXC_IGE:
5380 case OP_COND_EXC_IGE_UN:
5381 case OP_COND_EXC_ILE:
5382 case OP_COND_EXC_ILE_UN:
5383 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5386 case OP_COND_EXC_IC:
5387 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5389 case OP_COND_EXC_OV:
5390 case OP_COND_EXC_IOV:
5391 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5393 case OP_COND_EXC_NC:
5394 case OP_COND_EXC_INC:
5395 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5397 case OP_COND_EXC_NO:
5398 case OP_COND_EXC_INO:
5399 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5411 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5414 /* floating point opcodes */
5416 if (cfg->compile_aot) {
5417 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5419 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5421 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5424 /* FIXME: we can optimize the imm load by dealing with part of
5425 * the displacement in LDFD (aligning to 512).
5427 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5428 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5432 if (cfg->compile_aot) {
5433 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5435 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5438 ARM_CVTS (code, ins->dreg, ins->dreg);
5440 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5441 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5443 ARM_CVTS (code, ins->dreg, ins->dreg);
5446 case OP_STORER8_MEMBASE_REG:
5447 /* This is generated by the local regalloc pass which runs after the lowering pass */
5448 if (!arm_is_fpimm8 (ins->inst_offset)) {
5449 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5450 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5451 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5453 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5456 case OP_LOADR8_MEMBASE:
5457 /* This is generated by the local regalloc pass which runs after the lowering pass */
5458 if (!arm_is_fpimm8 (ins->inst_offset)) {
5459 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5460 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5461 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5463 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5466 case OP_STORER4_MEMBASE_REG:
5467 g_assert (arm_is_fpimm8 (ins->inst_offset));
5469 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5471 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5472 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5473 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5474 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5477 case OP_LOADR4_MEMBASE:
5479 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5481 g_assert (arm_is_fpimm8 (ins->inst_offset));
5482 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5483 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5484 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5485 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5488 case OP_ICONV_TO_R_UN: {
5489 g_assert_not_reached ();
5492 case OP_ICONV_TO_R4:
5494 ARM_FMSR (code, ins->dreg, ins->sreg1);
5495 ARM_FSITOS (code, ins->dreg, ins->dreg);
5497 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5498 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5499 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5500 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5501 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5504 case OP_ICONV_TO_R8:
5505 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5506 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5507 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5508 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5512 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5513 if (sig_ret->type == MONO_TYPE_R4) {
5515 if (IS_HARD_FLOAT) {
5516 if (ins->sreg1 != ARM_VFP_D0)
5517 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5519 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5522 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5525 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5529 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5531 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5535 case OP_FCONV_TO_I1:
5536 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5538 case OP_FCONV_TO_U1:
5539 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5541 case OP_FCONV_TO_I2:
5542 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5544 case OP_FCONV_TO_U2:
5545 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5547 case OP_FCONV_TO_I4:
5549 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5551 case OP_FCONV_TO_U4:
5553 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5555 case OP_FCONV_TO_I8:
5556 case OP_FCONV_TO_U8:
5557 g_assert_not_reached ();
5558 /* Implemented as helper calls */
5560 case OP_LCONV_TO_R_UN:
5561 g_assert_not_reached ();
5562 /* Implemented as helper calls */
5564 case OP_LCONV_TO_OVF_I4_2: {
5565 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5567 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5570 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5571 high_bit_not_set = code;
5572 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5574 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5575 valid_negative = code;
5576 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5577 invalid_negative = code;
5578 ARM_B_COND (code, ARMCOND_AL, 0);
5580 arm_patch (high_bit_not_set, code);
5582 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5583 valid_positive = code;
5584 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5586 arm_patch (invalid_negative, code);
5587 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5589 arm_patch (valid_negative, code);
5590 arm_patch (valid_positive, code);
5592 if (ins->dreg != ins->sreg1)
5593 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5597 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5600 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5603 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5606 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5609 ARM_NEGD (code, ins->dreg, ins->sreg1);
5613 g_assert_not_reached ();
5617 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5623 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5628 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5631 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5632 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5636 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5639 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5640 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5644 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5647 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5648 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5649 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5653 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5656 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5657 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5661 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5664 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5665 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5666 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5670 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5673 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5674 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5678 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5681 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5682 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5686 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5689 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5690 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5693 /* ARM FPA flags table:
5694 * N Less than ARMCOND_MI
5695 * Z Equal ARMCOND_EQ
5696 * C Greater Than or Equal ARMCOND_CS
5697 * V Unordered ARMCOND_VS
5700 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5703 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5706 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5709 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5710 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5716 g_assert_not_reached ();
5720 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5722 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5723 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5724 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5728 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5729 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5734 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5735 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5737 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5738 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5740 *(guint32*)code = 0xffffffff;
5742 *(guint32*)code = 0x7fefffff;
5744 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5746 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5747 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5749 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5750 ARM_CPYD (code, ins->dreg, ins->sreg1);
5752 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5753 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5758 case OP_RCONV_TO_I1:
5759 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5761 case OP_RCONV_TO_U1:
5762 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5764 case OP_RCONV_TO_I2:
5765 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5767 case OP_RCONV_TO_U2:
5768 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5770 case OP_RCONV_TO_I4:
5771 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5773 case OP_RCONV_TO_U4:
5774 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5776 case OP_RCONV_TO_R4:
5778 if (ins->dreg != ins->sreg1)
5779 ARM_CPYS (code, ins->dreg, ins->sreg1);
5781 case OP_RCONV_TO_R8:
5783 ARM_CVTS (code, ins->dreg, ins->sreg1);
5786 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5789 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5792 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5795 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5798 ARM_NEGS (code, ins->dreg, ins->sreg1);
5802 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5805 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5806 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5810 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5813 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5814 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5818 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5821 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5822 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5823 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5827 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5830 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5831 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5835 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5838 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5839 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5840 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5844 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5847 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5848 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5852 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5855 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5856 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5860 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5863 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5864 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5867 case OP_GC_LIVENESS_DEF:
5868 case OP_GC_LIVENESS_USE:
5869 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5870 ins->backend.pc_offset = code - cfg->native_code;
5872 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5873 ins->backend.pc_offset = code - cfg->native_code;
5874 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5876 case OP_GC_SAFE_POINT: {
5879 g_assert (mono_threads_is_coop_enabled ());
5881 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5882 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5884 ARM_B_COND (code, ARMCOND_EQ, 0);
5885 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5886 code = emit_call_seq (cfg, code);
5887 arm_patch (buf [0], code);
5892 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5893 g_assert_not_reached ();
5896 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5897 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5898 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5899 g_assert_not_reached ();
5905 last_offset = offset;
5908 cfg->code_len = code - cfg->native_code;
5911 #endif /* DISABLE_JIT */
5914 mono_arch_register_lowlevel_calls (void)
5916 /* The signature doesn't matter */
5917 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5918 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5919 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5922 #define patch_lis_ori(ip,val) do {\
5923 guint16 *__lis_ori = (guint16*)(ip); \
5924 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5925 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5929 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5931 unsigned char *ip = ji->ip.i + code;
5933 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5937 case MONO_PATCH_INFO_SWITCH: {
5938 gpointer *jt = (gpointer*)(ip + 8);
5940 /* jt is the inlined jump table, 2 instructions after ip
5941 * In the normal case we store the absolute addresses,
5942 * otherwise the displacements.
5944 for (i = 0; i < ji->data.table->table_size; i++)
5945 jt [i] = code + (int)ji->data.table->table [i];
5948 case MONO_PATCH_INFO_IP:
5949 g_assert_not_reached ();
5950 patch_lis_ori (ip, ip);
5952 case MONO_PATCH_INFO_METHOD_REL:
5953 g_assert_not_reached ();
5954 *((gpointer *)(ip)) = target;
5956 case MONO_PATCH_INFO_METHODCONST:
5957 case MONO_PATCH_INFO_CLASS:
5958 case MONO_PATCH_INFO_IMAGE:
5959 case MONO_PATCH_INFO_FIELD:
5960 case MONO_PATCH_INFO_VTABLE:
5961 case MONO_PATCH_INFO_IID:
5962 case MONO_PATCH_INFO_SFLDA:
5963 case MONO_PATCH_INFO_LDSTR:
5964 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5965 case MONO_PATCH_INFO_LDTOKEN:
5966 g_assert_not_reached ();
5967 /* from OP_AOTCONST : lis + ori */
5968 patch_lis_ori (ip, target);
5970 case MONO_PATCH_INFO_R4:
5971 case MONO_PATCH_INFO_R8:
5972 g_assert_not_reached ();
5973 *((gconstpointer *)(ip + 2)) = target;
5975 case MONO_PATCH_INFO_EXC_NAME:
5976 g_assert_not_reached ();
5977 *((gconstpointer *)(ip + 1)) = target;
5979 case MONO_PATCH_INFO_NONE:
5980 case MONO_PATCH_INFO_BB_OVF:
5981 case MONO_PATCH_INFO_EXC_OVF:
5982 /* everything is dealt with at epilog output time */
5985 arm_patch_general (cfg, domain, ip, target);
5991 mono_arm_unaligned_stack (MonoMethod *method)
5993 g_assert_not_reached ();
5999 * Stack frame layout:
6001 * ------------------- fp
6002 * MonoLMF structure or saved registers
6003 * -------------------
6005 * -------------------
6007 * -------------------
6008 * optional 8 bytes for tracing
6009 * -------------------
6010 * param area size is cfg->param_area
6011 * ------------------- sp
6014 mono_arch_emit_prolog (MonoCompile *cfg)
6016 MonoMethod *method = cfg->method;
6018 MonoMethodSignature *sig;
6020 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6025 int prev_sp_offset, reg_offset;
6027 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6030 sig = mono_method_signature (method);
6031 cfg->code_size = 256 + sig->param_count * 64;
6032 code = cfg->native_code = g_malloc (cfg->code_size);
6034 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6036 alloc_size = cfg->stack_offset;
6042 * The iphone uses R7 as the frame pointer, and it points at the saved
6047 * We can't use r7 as a frame pointer since it points into the middle of
6048 * the frame, so we keep using our own frame pointer.
6049 * FIXME: Optimize this.
6051 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6052 prev_sp_offset += 8; /* r7 and lr */
6053 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6054 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6055 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6058 if (!method->save_lmf) {
6060 /* No need to push LR again */
6061 if (cfg->used_int_regs)
6062 ARM_PUSH (code, cfg->used_int_regs);
6064 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6065 prev_sp_offset += 4;
6067 for (i = 0; i < 16; ++i) {
6068 if (cfg->used_int_regs & (1 << i))
6069 prev_sp_offset += 4;
6071 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6073 for (i = 0; i < 16; ++i) {
6074 if ((cfg->used_int_regs & (1 << i))) {
6075 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6076 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6080 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6081 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6083 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6084 ARM_PUSH (code, 0x5ff0);
6085 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6086 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6088 for (i = 0; i < 16; ++i) {
6089 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6090 /* The original r7 is saved at the start */
6091 if (!(iphone_abi && i == ARMREG_R7))
6092 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6096 g_assert (reg_offset == 4 * 10);
6097 pos += sizeof (MonoLMF) - (4 * 10);
6101 orig_alloc_size = alloc_size;
6102 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6103 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6104 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6105 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6108 /* the stack used in the pushed regs */
6109 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6110 cfg->stack_usage = alloc_size;
6112 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6113 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6115 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6116 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6118 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6120 if (cfg->frame_reg != ARMREG_SP) {
6121 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6122 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6124 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6125 prev_sp_offset += alloc_size;
6127 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6128 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6130 /* compute max_offset in order to use short forward jumps
6131 * we could skip do it on arm because the immediate displacement
6132 * for jumps is large enough, it may be useful later for constant pools
6135 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6136 MonoInst *ins = bb->code;
6137 bb->max_offset = max_offset;
6139 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6142 MONO_BB_FOR_EACH_INS (bb, ins)
6143 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6146 /* stack alignment check */
6150 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6151 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6152 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6153 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6155 ARM_B_COND (code, ARMCOND_EQ, 0);
6156 if (cfg->compile_aot)
6157 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6159 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6160 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6161 code = emit_call_seq (cfg, code);
6162 arm_patch (buf [0], code);
6166 /* store runtime generic context */
6167 if (cfg->rgctx_var) {
6168 MonoInst *ins = cfg->rgctx_var;
6170 g_assert (ins->opcode == OP_REGOFFSET);
6172 if (arm_is_imm12 (ins->inst_offset)) {
6173 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6175 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6176 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6180 /* load arguments allocated to register from the stack */
6183 cinfo = get_call_info (NULL, sig);
6185 if (cinfo->ret.storage == RegTypeStructByAddr) {
6186 ArgInfo *ainfo = &cinfo->ret;
6187 inst = cfg->vret_addr;
6188 g_assert (arm_is_imm12 (inst->inst_offset));
6189 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6192 if (sig->call_convention == MONO_CALL_VARARG) {
6193 ArgInfo *cookie = &cinfo->sig_cookie;
6195 /* Save the sig cookie address */
6196 g_assert (cookie->storage == RegTypeBase);
6198 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6199 g_assert (arm_is_imm12 (cfg->sig_cookie));
6200 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6201 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6204 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6205 ArgInfo *ainfo = cinfo->args + i;
6206 inst = cfg->args [pos];
6208 if (cfg->verbose_level > 2)
6209 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6211 if (inst->opcode == OP_REGVAR) {
6212 if (ainfo->storage == RegTypeGeneral)
6213 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6214 else if (ainfo->storage == RegTypeFP) {
6215 g_assert_not_reached ();
6216 } else if (ainfo->storage == RegTypeBase) {
6217 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6218 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6220 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6221 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6224 g_assert_not_reached ();
6226 if (cfg->verbose_level > 2)
6227 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6229 switch (ainfo->storage) {
6231 for (part = 0; part < ainfo->nregs; part ++) {
6232 if (ainfo->esize == 4)
6233 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6235 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6238 case RegTypeGeneral:
6239 case RegTypeIRegPair:
6240 case RegTypeGSharedVtInReg:
6241 case RegTypeStructByAddr:
6242 switch (ainfo->size) {
6244 if (arm_is_imm12 (inst->inst_offset))
6245 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6247 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6248 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6252 if (arm_is_imm8 (inst->inst_offset)) {
6253 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6255 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6256 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6260 if (arm_is_imm12 (inst->inst_offset)) {
6261 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6263 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6264 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6266 if (arm_is_imm12 (inst->inst_offset + 4)) {
6267 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6269 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6270 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6274 if (arm_is_imm12 (inst->inst_offset)) {
6275 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6277 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6278 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6283 case RegTypeBaseGen:
6284 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6285 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6287 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6288 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6290 if (arm_is_imm12 (inst->inst_offset + 4)) {
6291 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6292 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6294 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6295 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6296 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6297 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6301 case RegTypeGSharedVtOnStack:
6302 case RegTypeStructByAddrOnStack:
6303 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6304 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6306 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6307 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6310 switch (ainfo->size) {
6312 if (arm_is_imm8 (inst->inst_offset)) {
6313 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6315 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6316 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6320 if (arm_is_imm8 (inst->inst_offset)) {
6321 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6323 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6324 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6328 if (arm_is_imm12 (inst->inst_offset)) {
6329 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6331 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6332 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6334 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6335 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6337 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6338 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6340 if (arm_is_imm12 (inst->inst_offset + 4)) {
6341 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6343 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6344 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6348 if (arm_is_imm12 (inst->inst_offset)) {
6349 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6351 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6352 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6358 int imm8, rot_amount;
6360 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6361 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6362 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6364 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6366 if (ainfo->size == 8)
6367 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6369 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6372 case RegTypeStructByVal: {
6373 int doffset = inst->inst_offset;
6377 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6378 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6379 if (arm_is_imm12 (doffset)) {
6380 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6382 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6383 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6385 soffset += sizeof (gpointer);
6386 doffset += sizeof (gpointer);
6388 if (ainfo->vtsize) {
6389 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6390 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6391 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6396 g_assert_not_reached ();
6403 if (method->save_lmf)
6404 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6407 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6409 if (cfg->arch.seq_point_info_var) {
6410 MonoInst *ins = cfg->arch.seq_point_info_var;
6412 /* Initialize the variable from a GOT slot */
6413 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6414 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6416 *(gpointer*)code = NULL;
6418 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6420 g_assert (ins->opcode == OP_REGOFFSET);
6422 if (arm_is_imm12 (ins->inst_offset)) {
6423 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6425 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6426 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6430 /* Initialize ss_trigger_page_var */
6431 if (!cfg->soft_breakpoints) {
6432 MonoInst *info_var = cfg->arch.seq_point_info_var;
6433 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6434 int dreg = ARMREG_LR;
6437 g_assert (info_var->opcode == OP_REGOFFSET);
6438 g_assert (arm_is_imm12 (info_var->inst_offset));
6440 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6441 /* Load the trigger page addr */
6442 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6443 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6447 if (cfg->arch.seq_point_ss_method_var) {
6448 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6449 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6451 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6452 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6454 if (cfg->compile_aot) {
6455 MonoInst *info_var = cfg->arch.seq_point_info_var;
6456 int dreg = ARMREG_LR;
6458 g_assert (info_var->opcode == OP_REGOFFSET);
6459 g_assert (arm_is_imm12 (info_var->inst_offset));
6461 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6462 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
6463 ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6465 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6466 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6468 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6470 *(gpointer*)code = &single_step_tramp;
6472 *(gpointer*)code = breakpoint_tramp;
6475 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6476 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6477 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6478 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6482 cfg->code_len = code - cfg->native_code;
6483 g_assert (cfg->code_len < cfg->code_size);
6490 mono_arch_emit_epilog (MonoCompile *cfg)
6492 MonoMethod *method = cfg->method;
6493 int pos, i, rot_amount;
6494 int max_epilog_size = 16 + 20*4;
6498 if (cfg->method->save_lmf)
6499 max_epilog_size += 128;
6501 if (mono_jit_trace_calls != NULL)
6502 max_epilog_size += 50;
6504 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6505 max_epilog_size += 50;
6507 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6508 cfg->code_size *= 2;
6509 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6510 cfg->stat_code_reallocs++;
6514 * Keep in sync with OP_JMP
6516 code = cfg->native_code + cfg->code_len;
6518 /* Save the uwind state which is needed by the out-of-line code */
6519 mono_emit_unwind_op_remember_state (cfg, code);
6521 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6522 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6526 /* Load returned vtypes into registers if needed */
6527 cinfo = cfg->arch.cinfo;
6528 switch (cinfo->ret.storage) {
6529 case RegTypeStructByVal: {
6530 MonoInst *ins = cfg->ret;
6532 if (cinfo->ret.nregs == 1) {
6533 if (arm_is_imm12 (ins->inst_offset)) {
6534 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6536 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6537 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6540 for (i = 0; i < cinfo->ret.nregs; ++i) {
6541 int offset = ins->inst_offset + (i * 4);
6542 if (arm_is_imm12 (offset)) {
6543 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6545 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6546 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6553 MonoInst *ins = cfg->ret;
6555 for (i = 0; i < cinfo->ret.nregs; ++i) {
6556 if (cinfo->ret.esize == 4)
6557 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6559 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6567 if (method->save_lmf) {
6568 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6569 /* all but r0-r3, sp and pc */
6570 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6573 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6575 /* This points to r4 inside MonoLMF->iregs */
6576 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6578 regmask = 0x9ff0; /* restore lr to pc */
6579 /* Skip caller saved registers not used by the method */
6580 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6581 regmask &= ~(1 << reg);
6586 /* Restored later */
6587 regmask &= ~(1 << ARMREG_PC);
6588 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6589 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6590 for (i = 0; i < 16; i++) {
6591 if (regmask & (1 << i))
6594 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6596 ARM_POP (code, regmask);
6598 for (i = 0; i < 16; i++) {
6599 if (regmask & (1 << i))
6600 mono_emit_unwind_op_same_value (cfg, code, i);
6602 /* Restore saved r7, restore LR to PC */
6603 /* Skip lr from the lmf */
6604 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6605 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6606 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6607 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6610 int i, nused_int_regs = 0;
6612 for (i = 0; i < 16; i++) {
6613 if (cfg->used_int_regs & (1 << i))
6617 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6618 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6620 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6621 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6624 if (cfg->frame_reg != ARMREG_SP) {
6625 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6629 /* Restore saved gregs */
6630 if (cfg->used_int_regs) {
6631 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6632 ARM_POP (code, cfg->used_int_regs);
6633 for (i = 0; i < 16; i++) {
6634 if (cfg->used_int_regs & (1 << i))
6635 mono_emit_unwind_op_same_value (cfg, code, i);
6638 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6639 /* Restore saved r7, restore LR to PC */
6640 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6642 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6643 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6647 /* Restore the unwind state to be the same as before the epilog */
6648 mono_emit_unwind_op_restore_state (cfg, code);
6650 cfg->code_len = code - cfg->native_code;
6652 g_assert (cfg->code_len < cfg->code_size);
6657 mono_arch_emit_exceptions (MonoCompile *cfg)
6659 MonoJumpInfo *patch_info;
6662 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6663 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6664 int max_epilog_size = 50;
6666 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6667 exc_throw_pos [i] = NULL;
6668 exc_throw_found [i] = 0;
6671 /* count the number of exception infos */
6674 * make sure we have enough space for exceptions
6676 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6677 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6678 i = mini_exception_id_by_name (patch_info->data.target);
6679 if (!exc_throw_found [i]) {
6680 max_epilog_size += 32;
6681 exc_throw_found [i] = TRUE;
6686 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6687 cfg->code_size *= 2;
6688 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6689 cfg->stat_code_reallocs++;
6692 code = cfg->native_code + cfg->code_len;
6694 /* add code to raise exceptions */
6695 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6696 switch (patch_info->type) {
6697 case MONO_PATCH_INFO_EXC: {
6698 MonoClass *exc_class;
6699 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6701 i = mini_exception_id_by_name (patch_info->data.target);
6702 if (exc_throw_pos [i]) {
6703 arm_patch (ip, exc_throw_pos [i]);
6704 patch_info->type = MONO_PATCH_INFO_NONE;
6707 exc_throw_pos [i] = code;
6709 arm_patch (ip, code);
6711 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6713 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6714 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6715 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6716 patch_info->data.name = "mono_arch_throw_corlib_exception";
6717 patch_info->ip.i = code - cfg->native_code;
6719 cfg->thunk_area += THUNK_SIZE;
6720 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6730 cfg->code_len = code - cfg->native_code;
6732 g_assert (cfg->code_len < cfg->code_size);
6736 #endif /* #ifndef DISABLE_JIT */
6739 mono_arch_finish_init (void)
6744 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6749 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6756 mono_arch_print_tree (MonoInst *tree, int arity)
6766 mono_arch_get_patch_offset (guint8 *code)
6773 mono_arch_flush_register_windows (void)
6778 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6780 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6784 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6786 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6790 mono_arch_get_cie_program (void)
6794 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6799 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6800 #define BASE_SIZE (6 * 4)
6801 #define BSEARCH_ENTRY_SIZE (4 * 4)
6802 #define CMP_SIZE (3 * 4)
6803 #define BRANCH_SIZE (1 * 4)
6804 #define CALL_SIZE (2 * 4)
6805 #define WMC_SIZE (8 * 4)
6806 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6809 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6811 guint32 delta = DISTANCE (target, code);
6813 g_assert (delta >= 0 && delta <= 0xFFF);
6814 *target = *target | delta;
6819 #ifdef ENABLE_WRONG_METHOD_CHECK
6821 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6823 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6829 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6830 gpointer fail_tramp)
6833 arminstr_t *code, *start;
6834 gboolean large_offsets = FALSE;
6835 guint32 **constant_pool_starts;
6836 arminstr_t *vtable_target = NULL;
6837 int extra_space = 0;
6838 #ifdef ENABLE_WRONG_METHOD_CHECK
6844 constant_pool_starts = g_new0 (guint32*, count);
6846 for (i = 0; i < count; ++i) {
6847 MonoIMTCheckItem *item = imt_entries [i];
6848 if (item->is_equals) {
6849 gboolean fail_case = !item->check_target_idx && fail_tramp;
6851 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6852 item->chunk_size += 32;
6853 large_offsets = TRUE;
6856 if (item->check_target_idx || fail_case) {
6857 if (!item->compare_done || fail_case)
6858 item->chunk_size += CMP_SIZE;
6859 item->chunk_size += BRANCH_SIZE;
6861 #ifdef ENABLE_WRONG_METHOD_CHECK
6862 item->chunk_size += WMC_SIZE;
6866 item->chunk_size += 16;
6867 large_offsets = TRUE;
6869 item->chunk_size += CALL_SIZE;
6871 item->chunk_size += BSEARCH_ENTRY_SIZE;
6872 imt_entries [item->check_target_idx]->compare_done = TRUE;
6874 size += item->chunk_size;
6878 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6881 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
6883 code = mono_domain_code_reserve (domain, size);
6886 unwind_ops = mono_arch_get_cie_program ();
6889 g_print ("Building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6890 for (i = 0; i < count; ++i) {
6891 MonoIMTCheckItem *item = imt_entries [i];
6892 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6896 if (large_offsets) {
6897 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6898 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6900 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6901 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6903 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6904 vtable_target = code;
6905 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6906 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6908 for (i = 0; i < count; ++i) {
6909 MonoIMTCheckItem *item = imt_entries [i];
6910 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6911 gint32 vtable_offset;
6913 item->code_target = (guint8*)code;
6915 if (item->is_equals) {
6916 gboolean fail_case = !item->check_target_idx && fail_tramp;
6918 if (item->check_target_idx || fail_case) {
6919 if (!item->compare_done || fail_case) {
6921 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6922 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6924 item->jmp_code = (guint8*)code;
6925 ARM_B_COND (code, ARMCOND_NE, 0);
6927 /*Enable the commented code to assert on wrong method*/
6928 #ifdef ENABLE_WRONG_METHOD_CHECK
6930 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6931 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6933 ARM_B_COND (code, ARMCOND_EQ, 0);
6935 /* Define this if your system is so bad that gdb is failing. */
6936 #ifdef BROKEN_DEV_ENV
6937 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6939 arm_patch (code - 1, mini_dump_bad_imt);
6943 arm_patch (cond, code);
6947 if (item->has_target_code) {
6948 /* Load target address */
6949 target_code_ins = code;
6950 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6951 /* Save it to the fourth slot */
6952 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6953 /* Restore registers and branch */
6954 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6956 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
6958 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
6959 if (!arm_is_imm12 (vtable_offset)) {
6961 * We need to branch to a computed address but we don't have
6962 * a free register to store it, since IP must contain the
6963 * vtable address. So we push the two values to the stack, and
6964 * load them both using LDM.
6966 /* Compute target address */
6967 vtable_offset_ins = code;
6968 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6969 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
6970 /* Save it to the fourth slot */
6971 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6972 /* Restore registers and branch */
6973 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6975 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
6977 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
6978 if (large_offsets) {
6979 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6980 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
6982 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
6983 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
6988 arm_patch (item->jmp_code, (guchar*)code);
6990 target_code_ins = code;
6991 /* Load target address */
6992 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6993 /* Save it to the fourth slot */
6994 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6995 /* Restore registers and branch */
6996 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6998 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
6999 item->jmp_code = NULL;
7003 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7005 /*must emit after unconditional branch*/
7006 if (vtable_target) {
7007 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7008 item->chunk_size += 4;
7009 vtable_target = NULL;
7012 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7013 constant_pool_starts [i] = code;
7015 code += extra_space;
7019 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7020 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7022 item->jmp_code = (guint8*)code;
7023 ARM_B_COND (code, ARMCOND_HS, 0);
7028 for (i = 0; i < count; ++i) {
7029 MonoIMTCheckItem *item = imt_entries [i];
7030 if (item->jmp_code) {
7031 if (item->check_target_idx)
7032 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7034 if (i > 0 && item->is_equals) {
7036 arminstr_t *space_start = constant_pool_starts [i];
7037 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7038 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7045 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7046 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7051 g_free (constant_pool_starts);
7053 mono_arch_flush_icache ((guint8*)start, size);
7054 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7055 mono_stats.imt_trampolines_size += code - start;
7057 g_assert (DISTANCE (start, code) <= size);
7059 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7065 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7067 return ctx->regs [reg];
7071 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7073 ctx->regs [reg] = val;
7077 * mono_arch_get_trampolines:
7079 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7083 mono_arch_get_trampolines (gboolean aot)
7085 return mono_arm_get_exception_trampolines (aot);
7089 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7096 bp = MONO_CONTEXT_GET_BP (ctx);
7097 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7099 old_value = *lr_loc;
7100 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7103 *lr_loc = new_value;
7108 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7110 * mono_arch_set_breakpoint:
7112 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7113 * The location should contain code emitted by OP_SEQ_POINT.
7116 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7119 guint32 native_offset = ip - (guint8*)ji->code_start;
7120 MonoDebugOptions *opt = mini_get_debug_options ();
7123 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7125 if (!breakpoint_tramp)
7126 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7128 g_assert (native_offset % 4 == 0);
7129 g_assert (info->bp_addrs [native_offset / 4] == 0);
7130 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7131 } else if (opt->soft_breakpoints) {
7133 ARM_BLX_REG (code, ARMREG_LR);
7134 mono_arch_flush_icache (code - 4, 4);
7136 int dreg = ARMREG_LR;
7138 /* Read from another trigger page */
7139 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7141 *(int*)code = (int)bp_trigger_page;
7143 ARM_LDR_IMM (code, dreg, dreg, 0);
7145 mono_arch_flush_icache (code - 16, 16);
7148 /* This is currently implemented by emitting an SWI instruction, which
7149 * qemu/linux seems to convert to a SIGILL.
7151 *(int*)code = (0xef << 24) | 8;
7153 mono_arch_flush_icache (code - 4, 4);
7159 * mono_arch_clear_breakpoint:
7161 * Clear the breakpoint at IP.
7164 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7166 MonoDebugOptions *opt = mini_get_debug_options ();
7171 guint32 native_offset = ip - (guint8*)ji->code_start;
7172 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7174 if (!breakpoint_tramp)
7175 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7177 g_assert (native_offset % 4 == 0);
7178 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7179 info->bp_addrs [native_offset / 4] = 0;
7180 } else if (opt->soft_breakpoints) {
7183 mono_arch_flush_icache (code - 4, 4);
7185 for (i = 0; i < 4; ++i)
7188 mono_arch_flush_icache (ip, code - ip);
7193 * mono_arch_start_single_stepping:
7195 * Start single stepping.
7198 mono_arch_start_single_stepping (void)
7200 if (ss_trigger_page)
7201 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7203 single_step_tramp = mini_get_single_step_trampoline ();
7207 * mono_arch_stop_single_stepping:
7209 * Stop single stepping.
7212 mono_arch_stop_single_stepping (void)
7214 if (ss_trigger_page)
7215 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7217 single_step_tramp = NULL;
7221 #define DBG_SIGNAL SIGBUS
7223 #define DBG_SIGNAL SIGSEGV
7227 * mono_arch_is_single_step_event:
7229 * Return whenever the machine state in SIGCTX corresponds to a single
7233 mono_arch_is_single_step_event (void *info, void *sigctx)
7235 siginfo_t *sinfo = info;
7237 if (!ss_trigger_page)
7240 /* Sometimes the address is off by 4 */
7241 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7248 * mono_arch_is_breakpoint_event:
7250 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7253 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7255 siginfo_t *sinfo = info;
7257 if (!ss_trigger_page)
7260 if (sinfo->si_signo == DBG_SIGNAL) {
7261 /* Sometimes the address is off by 4 */
7262 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7272 * mono_arch_skip_breakpoint:
7274 * See mini-amd64.c for docs.
7277 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7279 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7283 * mono_arch_skip_single_step:
7285 * See mini-amd64.c for docs.
7288 mono_arch_skip_single_step (MonoContext *ctx)
7290 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7293 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7296 * mono_arch_get_seq_point_info:
7298 * See mini-amd64.c for docs.
7301 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7306 // FIXME: Add a free function
7308 mono_domain_lock (domain);
7309 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7311 mono_domain_unlock (domain);
7314 ji = mono_jit_info_table_find (domain, (char*)code);
7317 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7319 info->ss_trigger_page = ss_trigger_page;
7320 info->bp_trigger_page = bp_trigger_page;
7321 info->ss_tramp_addr = &single_step_tramp;
7323 mono_domain_lock (domain);
7324 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7326 mono_domain_unlock (domain);
7333 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7335 ext->lmf.previous_lmf = prev_lmf;
7336 /* Mark that this is a MonoLMFExt */
7337 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7338 ext->lmf.sp = (gssize)ext;
7342 * mono_arch_set_target:
7344 * Set the target architecture the JIT backend should generate code for, in the form
7345 * of a GNU target triplet. Only used in AOT mode.
7348 mono_arch_set_target (char *mtriple)
7350 /* The GNU target triple format is not very well documented */
7351 if (strstr (mtriple, "armv7")) {
7352 v5_supported = TRUE;
7353 v6_supported = TRUE;
7354 v7_supported = TRUE;
7356 if (strstr (mtriple, "armv6")) {
7357 v5_supported = TRUE;
7358 v6_supported = TRUE;
7360 if (strstr (mtriple, "armv7s")) {
7361 v7s_supported = TRUE;
7363 if (strstr (mtriple, "armv7k")) {
7364 v7k_supported = TRUE;
7366 if (strstr (mtriple, "thumbv7s")) {
7367 v5_supported = TRUE;
7368 v6_supported = TRUE;
7369 v7_supported = TRUE;
7370 v7s_supported = TRUE;
7371 thumb_supported = TRUE;
7372 thumb2_supported = TRUE;
7374 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7375 v5_supported = TRUE;
7376 v6_supported = TRUE;
7377 thumb_supported = TRUE;
7380 if (strstr (mtriple, "gnueabi"))
7381 eabi_supported = TRUE;
7385 mono_arch_opcode_supported (int opcode)
7388 case OP_ATOMIC_ADD_I4:
7389 case OP_ATOMIC_EXCHANGE_I4:
7390 case OP_ATOMIC_CAS_I4:
7391 case OP_ATOMIC_LOAD_I1:
7392 case OP_ATOMIC_LOAD_I2:
7393 case OP_ATOMIC_LOAD_I4:
7394 case OP_ATOMIC_LOAD_U1:
7395 case OP_ATOMIC_LOAD_U2:
7396 case OP_ATOMIC_LOAD_U4:
7397 case OP_ATOMIC_STORE_I1:
7398 case OP_ATOMIC_STORE_I2:
7399 case OP_ATOMIC_STORE_I4:
7400 case OP_ATOMIC_STORE_U1:
7401 case OP_ATOMIC_STORE_U2:
7402 case OP_ATOMIC_STORE_U4:
7403 return v7_supported;
7404 case OP_ATOMIC_LOAD_R4:
7405 case OP_ATOMIC_LOAD_R8:
7406 case OP_ATOMIC_STORE_R4:
7407 case OP_ATOMIC_STORE_R8:
7408 return v7_supported && IS_VFP;
7415 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7417 return get_call_info (mp, sig);
7421 mono_arch_get_get_tls_tramp (void)
7427 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data)
7430 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
7431 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7433 *(gpointer*)code = NULL;
7435 /* Load the value from the GOT */
7436 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);