mono/mini/mini-arm.c

   1 /*
   2  * mini-arm.c: ARM backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *
   8  * (C) 2003 Ximian, Inc.
   9  */
  10 #include "mini.h"
  11 #include <string.h>
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/utils/mono-mmap.h>
  16
  17 #include "mini-arm.h"
  18 #include "cpu-arm.h"
  19 #include "trace.h"
  20 #include "ir-emit.h"
  21 #ifdef ARM_FPU_FPA
  22 #include "mono/arch/arm/arm-fpa-codegen.h"
  23 #elif defined(ARM_FPU_VFP)
  24 #include "mono/arch/arm/arm-vfp-codegen.h"
  25 #endif
  26
  27 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
  28 #define HAVE_AEABI_READ_TP 1
  29 #endif
  30
  31 static gint lmf_tls_offset = -1;
  32 static gint lmf_addr_tls_offset = -1;
  33
  34 /* This mutex protects architecture specific caches */
  35 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  36 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  37 static CRITICAL_SECTION mini_arch_mutex;
  38
  39 static int v5_supported = 0;
  40 static int v7_supported = 0;
  41 static int thumb_supported = 0;
  42
  43 /*
  44  * The code generated for sequence points reads from this location, which is
  45  * made read-only when single stepping is enabled.
  46  */
  47 static gpointer ss_trigger_page;
  48
  49 /* Enabled breakpoints read from this trigger page */
  50 static gpointer bp_trigger_page;
  51
  52 /* Structure used by the sequence points in AOTed code */
  53 typedef struct {
  54         gpointer ss_trigger_page;
  55         gpointer bp_trigger_page;
  56         guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
  57 } SeqPointInfo;
  58
  59 /*
  60  * TODO:
  61  * floating point support: on ARM it is a mess, there are at least 3
  62  * different setups, each of which binary incompat with the other.
  63  * 1) FPA: old and ugly, but unfortunately what current distros use
  64  *    the double binary format has the two words swapped. 8 double registers.
  65  *    Implemented usually by kernel emulation.
  66  * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
  67  *    ugly swapped double format (I guess a softfloat-vfp exists, too, though).
  68  * 3) VFP: the new and actually sensible and useful FP support. Implemented
  69  *    in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
  70  *
  71  * The plan is to write the FPA support first. softfloat can be tested in a chroot.
  72  */
  73 int mono_exc_esp_offset = 0;
  74
  75 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
  76 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
  77 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
  78
  79 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
  80 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
  81 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
  82
  83 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
  84 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) |  (ARMREG_LR << 12) | ARMREG_PC)
  85 #define DEBUG_IMT 0
  86
  87 /* A variant of ARM_LDR_IMM which can handle large offsets */
  88 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
  89         if (arm_is_imm12 ((offset))) { \
  90                 ARM_LDR_IMM (code, (dreg), (basereg), (offset));        \
  91         } else {                                                                                                \
  92                 g_assert ((scratch_reg) != (basereg));                                     \
  93                 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset));  \
  94                 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg));               \
  95         }                                                                                                                                       \
  96         } while (0)
  97
  98 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do {      \
  99         if (arm_is_imm12 ((offset))) { \
 100                 ARM_STR_IMM (code, (dreg), (basereg), (offset));        \
 101         } else {                                                                                                \
 102                 g_assert ((scratch_reg) != (basereg));                                     \
 103                 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset));  \
 104                 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg));               \
 105         }                                                                                                                                       \
 106         } while (0)
 107
 108 const char*
 109 mono_arch_regname (int reg)
 110 {
 111         static const char * rnames[] = {
 112                 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
 113                 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
 114                 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
 115                 "arm_pc"
 116         };
 117         if (reg >= 0 && reg < 16)
 118                 return rnames [reg];
 119         return "unknown";
 120 }
 121
 122 const char*
 123 mono_arch_fregname (int reg)
 124 {
 125         static const char * rnames[] = {
 126                 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
 127                 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
 128                 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
 129                 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
 130                 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
 131                 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
 132                 "arm_f30", "arm_f31"
 133         };
 134         if (reg >= 0 && reg < 32)
 135                 return rnames [reg];
 136         return "unknown";
 137 }
 138
 139 #ifndef DISABLE_JIT
 140
 141 static guint8*
 142 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
 143 {
 144         int imm8, rot_amount;
 145         if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
 146                 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
 147                 return code;
 148         }
 149         g_assert (dreg != sreg);
 150         code = mono_arm_emit_load_imm (code, dreg, imm);
 151         ARM_ADD_REG_REG (code, dreg, dreg, sreg);
 152         return code;
 153 }
 154
 155 static guint8*
 156 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
 157 {
 158         /* we can use r0-r3, since this is called only for incoming args on the stack */
 159         if (size > sizeof (gpointer) * 4) {
 160                 guint8 *start_loop;
 161                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
 162                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
 163                 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
 164                 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
 165                 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
 166                 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
 167                 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
 168                 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
 169                 ARM_B_COND (code, ARMCOND_NE, 0);
 170                 arm_patch (code - 4, start_loop);
 171                 return code;
 172         }
 173         if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
 174                         arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
 175                 while (size >= 4) {
 176                         ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
 177                         ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
 178                         doffset += 4;
 179                         soffset += 4;
 180                         size -= 4;
 181                 }
 182         } else if (size) {
 183                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
 184                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
 185                 doffset = soffset = 0;
 186                 while (size >= 4) {
 187                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
 188                         ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
 189                         doffset += 4;
 190                         soffset += 4;
 191                         size -= 4;
 192                 }
 193         }
 194         g_assert (size == 0);
 195         return code;
 196 }
 197
 198 static guint8*
 199 emit_call_reg (guint8 *code, int reg)
 200 {
 201         if (v5_supported) {
 202                 ARM_BLX_REG (code, reg);
 203         } else {
 204                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
 205                 if (thumb_supported)
 206                         ARM_BX (code, reg);
 207                 else
 208                         ARM_MOV_REG_REG (code, ARMREG_PC, reg);
 209         }
 210         return code;
 211 }
 212
 213 static guint8*
 214 emit_call_seq (MonoCompile *cfg, guint8 *code)
 215 {
 216         if (cfg->method->dynamic) {
 217                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
 218                 ARM_B (code, 0);
 219                 *(gpointer*)code = NULL;
 220                 code += 4;
 221                 code = emit_call_reg (code, ARMREG_IP);
 222         } else {
 223                 ARM_BL (code, 0);
 224         }
 225         return code;
 226 }
 227
 228 static guint8*
 229 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
 230 {
 231         switch (ins->opcode) {
 232         case OP_FCALL:
 233         case OP_FCALL_REG:
 234         case OP_FCALL_MEMBASE:
 235 #ifdef ARM_FPU_FPA
 236                 if (ins->dreg != ARM_FPA_F0)
 237                         ARM_MVFD (code, ins->dreg, ARM_FPA_F0);
 238 #elif defined(ARM_FPU_VFP)
 239                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
 240                         ARM_FMSR (code, ins->dreg, ARMREG_R0);
 241                         ARM_CVTS (code, ins->dreg, ins->dreg);
 242                 } else {
 243                         ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
 244                 }
 245 #endif
 246                 break;
 247         }
 248
 249         return code;
 250 }
 251
 252 #endif /* #ifndef DISABLE_JIT */
 253
 254 /*
 255  * mono_arch_get_argument_info:
 256  * @csig:  a method signature
 257  * @param_count: the number of parameters to consider
 258  * @arg_info: an array to store the result infos
 259  *
 260  * Gathers information on parameters such as size, alignment and
 261  * padding. arg_info should be large enought to hold param_count + 1 entries.
 262  *
 263  * Returns the size of the activation frame.
 264  */
 265 int
 266 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 267 {
 268         int k, frame_size = 0;
 269         guint32 size, align, pad;
 270         int offset = 8;
 271
 272         if (MONO_TYPE_ISSTRUCT (csig->ret)) {
 273                 frame_size += sizeof (gpointer);
 274                 offset += 4;
 275         }
 276
 277         arg_info [0].offset = offset;
 278
 279         if (csig->hasthis) {
 280                 frame_size += sizeof (gpointer);
 281                 offset += 4;
 282         }
 283
 284         arg_info [0].size = frame_size;
 285
 286         for (k = 0; k < param_count; k++) {
 287                 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
 288
 289                 /* ignore alignment for now */
 290                 align = 1;
 291
 292                 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 293                 arg_info [k].pad = pad;
 294                 frame_size += size;
 295                 arg_info [k + 1].pad = 0;
 296                 arg_info [k + 1].size = size;
 297                 offset += pad;
 298                 arg_info [k + 1].offset = offset;
 299                 offset += size;
 300         }
 301
 302         align = MONO_ARCH_FRAME_ALIGNMENT;
 303         frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 304         arg_info [k].pad = pad;
 305
 306         return frame_size;
 307 }
 308
 309 #define MAX_ARCH_DELEGATE_PARAMS 3
 310
 311 static gpointer
 312 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
 313 {
 314         guint8 *code, *start;
 315
 316         if (has_target) {
 317                 start = code = mono_global_codeman_reserve (12);
 318
 319                 /* Replace the this argument with the target */
 320                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
 321                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
 322                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 323
 324                 g_assert ((code - start) <= 12);
 325
 326                 mono_arch_flush_icache (start, 12);
 327         } else {
 328                 int size, i;
 329
 330                 size = 8 + param_count * 4;
 331                 start = code = mono_global_codeman_reserve (size);
 332
 333                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
 334                 /* slide down the arguments */
 335                 for (i = 0; i < param_count; ++i) {
 336                         ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
 337                 }
 338                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 339
 340                 g_assert ((code - start) <= size);
 341
 342                 mono_arch_flush_icache (start, size);
 343         }
 344
 345         if (code_size)
 346                 *code_size = code - start;
 347
 348         return start;
 349 }
 350
 351 /*
 352  * mono_arch_get_delegate_invoke_impls:
 353  *
 354  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
 355  * trampolines.
 356  */
 357 GSList*
 358 mono_arch_get_delegate_invoke_impls (void)
 359 {
 360         GSList *res = NULL;
 361         guint8 *code;
 362         guint32 code_len;
 363         int i;
 364
 365         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
 366         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
 367
 368         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
 369                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
 370                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
 371         }
 372
 373         return res;
 374 }
 375
 376 gpointer
 377 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
 378 {
 379         guint8 *code, *start;
 380
 381         /* FIXME: Support more cases */
 382         if (MONO_TYPE_ISSTRUCT (sig->ret))
 383                 return NULL;
 384
 385         if (has_target) {
 386                 static guint8* cached = NULL;
 387                 mono_mini_arch_lock ();
 388                 if (cached) {
 389                         mono_mini_arch_unlock ();
 390                         return cached;
 391                 }
 392
 393                 if (mono_aot_only)
 394                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
 395                 else
 396                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
 397                 cached = start;
 398                 mono_mini_arch_unlock ();
 399                 return cached;
 400         } else {
 401                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
 402                 int i;
 403
 404                 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
 405                         return NULL;
 406                 for (i = 0; i < sig->param_count; ++i)
 407                         if (!mono_is_regsize_var (sig->params [i]))
 408                                 return NULL;
 409
 410                 mono_mini_arch_lock ();
 411                 code = cache [sig->param_count];
 412                 if (code) {
 413                         mono_mini_arch_unlock ();
 414                         return code;
 415                 }
 416
 417                 if (mono_aot_only) {
 418                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
 419                         start = mono_aot_get_trampoline (name);
 420                         g_free (name);
 421                 } else {
 422                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
 423                 }
 424                 cache [sig->param_count] = start;
 425                 mono_mini_arch_unlock ();
 426                 return start;
 427         }
 428
 429         return NULL;
 430 }
 431
 432 gpointer
 433 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
 434 {
 435         return (gpointer)regs [ARMREG_R0];
 436 }
 437
 438 /*
 439  * Initialize the cpu to execute managed code.
 440  */
 441 void
 442 mono_arch_cpu_init (void)
 443 {
 444 }
 445
 446 /*
 447  * Initialize architecture specific code.
 448  */
 449 void
 450 mono_arch_init (void)
 451 {
 452         InitializeCriticalSection (&mini_arch_mutex);
 453
 454         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 455         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 456         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 457
 458         mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
 459         mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
 460 }
 461
 462 /*
 463  * Cleanup architecture specific code.
 464  */
 465 void
 466 mono_arch_cleanup (void)
 467 {
 468 }
 469
 470 /*
 471  * This function returns the optimizations supported on this cpu.
 472  */
 473 guint32
 474 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 475 {
 476         guint32 opts = 0;
 477         const char *cpu_arch = getenv ("MONO_CPU_ARCH");
 478         if (cpu_arch != NULL) {
 479                 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
 480                 if (strncmp (cpu_arch, "armv", 4) == 0) {
 481                         v5_supported = cpu_arch [4] >= '5';
 482                         v7_supported = cpu_arch [4] >= '7';
 483                 }
 484         } else {
 485 #if __APPLE__
 486         thumb_supported = TRUE;
 487         v5_supported = TRUE;
 488 #else
 489         char buf [512];
 490         char *line;
 491         FILE *file = fopen ("/proc/cpuinfo", "r");
 492         if (file) {
 493                 while ((line = fgets (buf, 512, file))) {
 494                         if (strncmp (line, "Processor", 9) == 0) {
 495                                 char *ver = strstr (line, "(v");
 496                                 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
 497                                         v5_supported = TRUE;
 498                                 if (ver && (ver [2] == '7'))
 499                                         v7_supported = TRUE;
 500                                 continue;
 501                         }
 502                         if (strncmp (line, "Features", 8) == 0) {
 503                                 char *th = strstr (line, "thumb");
 504                                 if (th) {
 505                                         thumb_supported = TRUE;
 506                                         if (v5_supported)
 507                                                 break;
 508                                 }
 509                                 continue;
 510                         }
 511                 }
 512                 fclose (file);
 513                 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
 514         }
 515 #endif
 516         }
 517
 518         /* no arm-specific optimizations yet */
 519         *exclude_mask = 0;
 520         return opts;
 521 }
 522
 523 #ifndef DISABLE_JIT
 524
 525 static gboolean
 526 is_regsize_var (MonoType *t) {
 527         if (t->byref)
 528                 return TRUE;
 529         t = mini_type_get_underlying_type (NULL, t);
 530         switch (t->type) {
 531         case MONO_TYPE_I4:
 532         case MONO_TYPE_U4:
 533         case MONO_TYPE_I:
 534         case MONO_TYPE_U:
 535         case MONO_TYPE_PTR:
 536         case MONO_TYPE_FNPTR:
 537                 return TRUE;
 538         case MONO_TYPE_OBJECT:
 539         case MONO_TYPE_STRING:
 540         case MONO_TYPE_CLASS:
 541         case MONO_TYPE_SZARRAY:
 542         case MONO_TYPE_ARRAY:
 543                 return TRUE;
 544         case MONO_TYPE_GENERICINST:
 545                 if (!mono_type_generic_inst_is_valuetype (t))
 546                         return TRUE;
 547                 return FALSE;
 548         case MONO_TYPE_VALUETYPE:
 549                 return FALSE;
 550         }
 551         return FALSE;
 552 }
 553
 554 GList *
 555 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 556 {
 557         GList *vars = NULL;
 558         int i;
 559
 560         for (i = 0; i < cfg->num_varinfo; i++) {
 561                 MonoInst *ins = cfg->varinfo [i];
 562                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 563
 564                 /* unused vars */
 565                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 566                         continue;
 567
 568                 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 569                         continue;
 570
 571                 /* we can only allocate 32 bit values */
 572                 if (is_regsize_var (ins->inst_vtype)) {
 573                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 574                         g_assert (i == vmv->idx);
 575                         vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
 576                 }
 577         }
 578
 579         return vars;
 580 }
 581
 582 #define USE_EXTRA_TEMPS 0
 583
 584 GList *
 585 mono_arch_get_global_int_regs (MonoCompile *cfg)
 586 {
 587         GList *regs = NULL;
 588
 589         /*
 590          * FIXME: Interface calls might go through a static rgctx trampoline which
 591          * sets V5, but it doesn't save it, so we need to save it ourselves, and
 592          * avoid using it.
 593          */
 594         if (cfg->flags & MONO_CFG_HAS_CALLS)
 595                 cfg->uses_rgctx_reg = TRUE;
 596
 597         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
 598         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
 599         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
 600         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
 601         if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
 602                 /* V5 is reserved for passing the vtable/rgctx/IMT method */
 603                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
 604         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
 605         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
 606
 607         return regs;
 608 }
 609
 610 /*
 611  * mono_arch_regalloc_cost:
 612  *
 613  *  Return the cost, in number of memory references, of the action of
 614  * allocating the variable VMV into a register during global register
 615  * allocation.
 616  */
 617 guint32
 618 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 619 {
 620         /* FIXME: */
 621         return 2;
 622 }
 623
 624 #endif /* #ifndef DISABLE_JIT */
 625
 626 #ifndef __GNUC_PREREQ
 627 #define __GNUC_PREREQ(maj, min) (0)
 628 #endif
 629
 630 void
 631 mono_arch_flush_icache (guint8 *code, gint size)
 632 {
 633 #if __APPLE__
 634         sys_icache_invalidate (code, size);
 635 #elif __GNUC_PREREQ(4, 1)
 636         __clear_cache (code, code + size);
 637 #elif defined(PLATFORM_ANDROID)
 638         const int syscall = 0xf0002;
 639         __asm __volatile (
 640                 "mov     r0, %0\n"
 641                 "mov     r1, %1\n"
 642                 "mov     r7, %2\n"
 643                 "mov     r2, #0x0\n"
 644                 "svc     0x00000000\n"
 645                 :
 646                 :       "r" (code), "r" (code + size), "r" (syscall)
 647                 :       "r0", "r1", "r7", "r2"
 648                 );
 649 #else
 650         __asm __volatile ("mov r0, %0\n"
 651                         "mov r1, %1\n"
 652                         "mov r2, %2\n"
 653                         "swi 0x9f0002       @ sys_cacheflush"
 654                         : /* no outputs */
 655                         : "r" (code), "r" (code + size), "r" (0)
 656                         : "r0", "r1", "r3" );
 657 #endif
 658 }
 659
 660 typedef enum {
 661         RegTypeNone,
 662         RegTypeGeneral,
 663         RegTypeIRegPair,
 664         RegTypeBase,
 665         RegTypeBaseGen,
 666         RegTypeFP,
 667         RegTypeStructByVal,
 668         RegTypeStructByAddr
 669 } ArgStorage;
 670
 671 typedef struct {
 672         gint32  offset;
 673         guint16 vtsize; /* in param area */
 674         guint8  reg;
 675         ArgStorage  storage;
 676         guint8  size    : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
 677 } ArgInfo;
 678
 679 typedef struct {
 680         int nargs;
 681         guint32 stack_usage;
 682         gboolean vtype_retaddr;
 683         /* The index of the vret arg in the argument list */
 684         int vret_arg_index;
 685         ArgInfo ret;
 686         ArgInfo sig_cookie;
 687         ArgInfo args [1];
 688 } CallInfo;
 689
 690 #define DEBUG(a)
 691
 692 #ifndef __GNUC__
 693 /*#define __alignof__(a) sizeof(a)*/
 694 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
 695 #endif
 696
 697 #define PARAM_REGS 4
 698
 699 static void inline
 700 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
 701 {
 702         if (simple) {
 703                 if (*gr > ARMREG_R3) {
 704                         ainfo->offset = *stack_size;
 705                         ainfo->reg = ARMREG_SP; /* in the caller */
 706                         ainfo->storage = RegTypeBase;
 707                         *stack_size += 4;
 708                 } else {
 709                         ainfo->storage = RegTypeGeneral;
 710                         ainfo->reg = *gr;
 711                 }
 712         } else {
 713 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
 714                 int i8_align = 4;
 715 #else
 716                 int i8_align = __alignof__ (gint64);
 717 #endif
 718
 719 #if __ARM_EABI__
 720                 gboolean split = i8_align == 4;
 721 #else
 722                 gboolean split = TRUE;
 723 #endif
 724
 725                 if (*gr == ARMREG_R3 && split) {
 726                         /* first word in r3 and the second on the stack */
 727                         ainfo->offset = *stack_size;
 728                         ainfo->reg = ARMREG_SP; /* in the caller */
 729                         ainfo->storage = RegTypeBaseGen;
 730                         *stack_size += 4;
 731                 } else if (*gr >= ARMREG_R3) {
 732 #ifdef __ARM_EABI__
 733                         /* darwin aligns longs to 4 byte only */
 734                         if (i8_align == 8) {
 735                                 *stack_size += 7;
 736                                 *stack_size &= ~7;
 737                         }
 738 #endif
 739                         ainfo->offset = *stack_size;
 740                         ainfo->reg = ARMREG_SP; /* in the caller */
 741                         ainfo->storage = RegTypeBase;
 742                         *stack_size += 8;
 743                 } else {
 744 #ifdef __ARM_EABI__
 745                         if (i8_align == 8 && ((*gr) & 1))
 746                                 (*gr) ++;
 747 #endif
 748                         ainfo->storage = RegTypeIRegPair;
 749                         ainfo->reg = *gr;
 750                 }
 751                 (*gr) ++;
 752         }
 753         (*gr) ++;
 754 }
 755
 756 static CallInfo*
 757 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 758 {
 759         guint i, gr, pstart;
 760         int n = sig->hasthis + sig->param_count;
 761         MonoType *simpletype;
 762         guint32 stack_size = 0;
 763         CallInfo *cinfo;
 764
 765         if (mp)
 766                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 767         else
 768                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 769
 770         cinfo->nargs = n;
 771         gr = ARMREG_R0;
 772
 773         /* FIXME: handle returning a struct */
 774         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 775                 guint32 align;
 776
 777                 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (sig->ret), &align) <= sizeof (gpointer)) {
 778                         cinfo->ret.storage = RegTypeStructByVal;
 779                 } else {
 780                         cinfo->vtype_retaddr = TRUE;
 781                 }
 782         }
 783
 784         pstart = 0;
 785         n = 0;
 786         /*
 787          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 788          * the first argument, allowing 'this' to be always passed in the first arg reg.
 789          * Also do this if the first argument is a reference type, since virtual calls
 790          * are sometimes made using calli without sig->hasthis set, like in the delegate
 791          * invoke wrappers.
 792          */
 793         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
 794                 if (sig->hasthis) {
 795                         add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
 796                 } else {
 797                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
 798                         pstart = 1;
 799                 }
 800                 n ++;
 801                 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
 802                 cinfo->vret_arg_index = 1;
 803         } else {
 804                 /* this */
 805                 if (sig->hasthis) {
 806                         add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
 807                         n ++;
 808                 }
 809
 810                 if (cinfo->vtype_retaddr)
 811                         add_general (&gr, &stack_size, &cinfo->ret, TRUE);
 812         }
 813
 814         DEBUG(printf("params: %d\n", sig->param_count));
 815         for (i = pstart; i < sig->param_count; ++i) {
 816                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 817                         /* Prevent implicit arguments and sig_cookie from
 818                            being passed in registers */
 819                         gr = ARMREG_R3 + 1;
 820                         /* Emit the signature cookie just before the implicit arguments */
 821                         add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
 822                 }
 823                 DEBUG(printf("param %d: ", i));
 824                 if (sig->params [i]->byref) {
 825                         DEBUG(printf("byref\n"));
 826                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 827                         n++;
 828                         continue;
 829                 }
 830                 simpletype = mini_type_get_underlying_type (NULL, sig->params [i]);
 831                 switch (simpletype->type) {
 832                 case MONO_TYPE_BOOLEAN:
 833                 case MONO_TYPE_I1:
 834                 case MONO_TYPE_U1:
 835                         cinfo->args [n].size = 1;
 836                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 837                         n++;
 838                         break;
 839                 case MONO_TYPE_CHAR:
 840                 case MONO_TYPE_I2:
 841                 case MONO_TYPE_U2:
 842                         cinfo->args [n].size = 2;
 843                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 844                         n++;
 845                         break;
 846                 case MONO_TYPE_I4:
 847                 case MONO_TYPE_U4:
 848                         cinfo->args [n].size = 4;
 849                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 850                         n++;
 851                         break;
 852                 case MONO_TYPE_I:
 853                 case MONO_TYPE_U:
 854                 case MONO_TYPE_PTR:
 855                 case MONO_TYPE_FNPTR:
 856                 case MONO_TYPE_CLASS:
 857                 case MONO_TYPE_OBJECT:
 858                 case MONO_TYPE_STRING:
 859                 case MONO_TYPE_SZARRAY:
 860                 case MONO_TYPE_ARRAY:
 861                 case MONO_TYPE_R4:
 862                         cinfo->args [n].size = sizeof (gpointer);
 863                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 864                         n++;
 865                         break;
 866                 case MONO_TYPE_GENERICINST:
 867                         if (!mono_type_generic_inst_is_valuetype (simpletype)) {
 868                                 cinfo->args [n].size = sizeof (gpointer);
 869                                 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 870                                 n++;
 871                                 break;
 872                         }
 873                         /* Fall through */
 874                 case MONO_TYPE_TYPEDBYREF:
 875                 case MONO_TYPE_VALUETYPE: {
 876                         gint size;
 877                         int align_size;
 878                         int nwords;
 879                         guint32 align;
 880
 881                         if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
 882                                 size = sizeof (MonoTypedRef);
 883                                 align = sizeof (gpointer);
 884                         } else {
 885                                 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
 886                                 if (is_pinvoke)
 887                                         size = mono_class_native_size (klass, &align);
 888                                 else
 889                                         size = mono_class_value_size (klass, &align);
 890                         }
 891                         DEBUG(printf ("load %d bytes struct\n",
 892                                       mono_class_native_size (sig->params [i]->data.klass, NULL)));
 893                         align_size = size;
 894                         nwords = 0;
 895                         align_size += (sizeof (gpointer) - 1);
 896                         align_size &= ~(sizeof (gpointer) - 1);
 897                         nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
 898                         cinfo->args [n].storage = RegTypeStructByVal;
 899                         /* FIXME: align stack_size if needed */
 900 #ifdef __ARM_EABI__
 901                         if (align >= 8 && (gr & 1))
 902                                 gr ++;
 903 #endif
 904                         if (gr > ARMREG_R3) {
 905                                 cinfo->args [n].size = 0;
 906                                 cinfo->args [n].vtsize = nwords;
 907                         } else {
 908                                 int rest = ARMREG_R3 - gr + 1;
 909                                 int n_in_regs = rest >= nwords? nwords: rest;
 910
 911                                 cinfo->args [n].size = n_in_regs;
 912                                 cinfo->args [n].vtsize = nwords - n_in_regs;
 913                                 cinfo->args [n].reg = gr;
 914                                 gr += n_in_regs;
 915                                 nwords -= n_in_regs;
 916                         }
 917                         cinfo->args [n].offset = stack_size;
 918                         /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
 919                         stack_size += nwords * sizeof (gpointer);
 920                         n++;
 921                         break;
 922                 }
 923                 case MONO_TYPE_U8:
 924                 case MONO_TYPE_I8:
 925                 case MONO_TYPE_R8:
 926                         cinfo->args [n].size = 8;
 927                         add_general (&gr, &stack_size, cinfo->args + n, FALSE);
 928                         n++;
 929                         break;
 930                 default:
 931                         g_error ("Can't trampoline 0x%x", sig->params [i]->type);
 932                 }
 933         }
 934
 935         /* Handle the case where there are no implicit arguments */
 936         if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 937                 /* Prevent implicit arguments and sig_cookie from
 938                    being passed in registers */
 939                 gr = ARMREG_R3 + 1;
 940                 /* Emit the signature cookie just before the implicit arguments */
 941                 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
 942         }
 943
 944         {
 945                 simpletype = mini_type_get_underlying_type (NULL, sig->ret);
 946                 switch (simpletype->type) {
 947                 case MONO_TYPE_BOOLEAN:
 948                 case MONO_TYPE_I1:
 949                 case MONO_TYPE_U1:
 950                 case MONO_TYPE_I2:
 951                 case MONO_TYPE_U2:
 952                 case MONO_TYPE_CHAR:
 953                 case MONO_TYPE_I4:
 954                 case MONO_TYPE_U4:
 955                 case MONO_TYPE_I:
 956                 case MONO_TYPE_U:
 957                 case MONO_TYPE_PTR:
 958                 case MONO_TYPE_FNPTR:
 959                 case MONO_TYPE_CLASS:
 960                 case MONO_TYPE_OBJECT:
 961                 case MONO_TYPE_SZARRAY:
 962                 case MONO_TYPE_ARRAY:
 963                 case MONO_TYPE_STRING:
 964                         cinfo->ret.storage = RegTypeGeneral;
 965                         cinfo->ret.reg = ARMREG_R0;
 966                         break;
 967                 case MONO_TYPE_U8:
 968                 case MONO_TYPE_I8:
 969                         cinfo->ret.storage = RegTypeIRegPair;
 970                         cinfo->ret.reg = ARMREG_R0;
 971                         break;
 972                 case MONO_TYPE_R4:
 973                 case MONO_TYPE_R8:
 974                         cinfo->ret.storage = RegTypeFP;
 975                         cinfo->ret.reg = ARMREG_R0;
 976                         /* FIXME: cinfo->ret.reg = ???;
 977                         cinfo->ret.storage = RegTypeFP;*/
 978                         break;
 979                 case MONO_TYPE_GENERICINST:
 980                         if (!mono_type_generic_inst_is_valuetype (simpletype)) {
 981                                 cinfo->ret.storage = RegTypeGeneral;
 982                                 cinfo->ret.reg = ARMREG_R0;
 983                                 break;
 984                         }
 985                         /* Fall through */
 986                 case MONO_TYPE_VALUETYPE:
 987                 case MONO_TYPE_TYPEDBYREF:
 988                         if (cinfo->ret.storage != RegTypeStructByVal)
 989                                 cinfo->ret.storage = RegTypeStructByAddr;
 990                         break;
 991                 case MONO_TYPE_VOID:
 992                         break;
 993                 default:
 994                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 995                 }
 996         }
 997
 998         /* align stack size to 8 */
 999         DEBUG (printf ("      stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1000         stack_size = (stack_size + 7) & ~7;
1001
1002         cinfo->stack_usage = stack_size;
1003         return cinfo;
1004 }
1005
1006 #ifndef DISABLE_JIT
1007
1008 /*
1009  * Set var information according to the calling convention. arm version.
1010  * The locals var stuff should most likely be split in another method.
1011  */
1012 void
1013 mono_arch_allocate_vars (MonoCompile *cfg)
1014 {
1015         MonoMethodSignature *sig;
1016         MonoMethodHeader *header;
1017         MonoInst *ins;
1018         int i, offset, size, align, curinst;
1019         int frame_reg = ARMREG_FP;
1020         CallInfo *cinfo;
1021         guint32 ualign;
1022
1023         sig = mono_method_signature (cfg->method);
1024
1025         if (!cfg->arch.cinfo)
1026                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1027         cinfo = cfg->arch.cinfo;
1028
1029         /* FIXME: this will change when we use FP as gcc does */
1030         cfg->flags |= MONO_CFG_HAS_SPILLUP;
1031
1032         /* allow room for the vararg method args: void* and long/double */
1033         if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1034                 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1035
1036         header = cfg->header;
1037
1038         /*
1039          * We use the frame register also for any method that has
1040          * exception clauses. This way, when the handlers are called,
1041          * the code will reference local variables using the frame reg instead of
1042          * the stack pointer: if we had to restore the stack pointer, we'd
1043          * corrupt the method frames that are already on the stack (since
1044          * filters get called before stack unwinding happens) when the filter
1045          * code would call any method (this also applies to finally etc.).
1046          */
1047         if ((cfg->flags & MONO_CFG_HAS_ALLOCA) || header->num_clauses)
1048                 frame_reg = ARMREG_FP;
1049         cfg->frame_reg = frame_reg;
1050         if (frame_reg != ARMREG_SP) {
1051                 cfg->used_int_regs |= 1 << frame_reg;
1052         }
1053
1054         if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1055                 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1056                 cfg->used_int_regs |= (1 << ARMREG_V5);
1057
1058         offset = 0;
1059         curinst = 0;
1060         if (!MONO_TYPE_ISSTRUCT (sig->ret)) {
1061                 switch (mini_type_get_underlying_type (NULL, sig->ret)->type) {
1062                 case MONO_TYPE_VOID:
1063                         break;
1064                 default:
1065                         cfg->ret->opcode = OP_REGVAR;
1066                         cfg->ret->inst_c0 = ARMREG_R0;
1067                         break;
1068                 }
1069         }
1070         /* local vars are at a positive offset from the stack pointer */
1071         /*
1072          * also note that if the function uses alloca, we use FP
1073          * to point at the local variables.
1074          */
1075         offset = 0; /* linkage area */
1076         /* align the offset to 16 bytes: not sure this is needed here  */
1077         //offset += 8 - 1;
1078         //offset &= ~(8 - 1);
1079
1080         /* add parameter area size for called functions */
1081         offset += cfg->param_area;
1082         offset += 8 - 1;
1083         offset &= ~(8 - 1);
1084         if (cfg->flags & MONO_CFG_HAS_FPOUT)
1085                 offset += 8;
1086
1087         /* allow room to save the return value */
1088         if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1089                 offset += 8;
1090
1091         /* the MonoLMF structure is stored just below the stack pointer */
1092         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1093                 if (cinfo->ret.storage == RegTypeStructByVal) {
1094                         cfg->ret->opcode = OP_REGOFFSET;
1095                         cfg->ret->inst_basereg = cfg->frame_reg;
1096                         offset += sizeof (gpointer) - 1;
1097                         offset &= ~(sizeof (gpointer) - 1);
1098                         cfg->ret->inst_offset = - offset;
1099                 } else {
1100                         ins = cfg->vret_addr;
1101                         offset += sizeof(gpointer) - 1;
1102                         offset &= ~(sizeof(gpointer) - 1);
1103                         ins->inst_offset = offset;
1104                         ins->opcode = OP_REGOFFSET;
1105                         ins->inst_basereg = frame_reg;
1106                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1107                                 printf ("vret_addr =");
1108                                 mono_print_ins (cfg->vret_addr);
1109                         }
1110                 }
1111                 offset += sizeof(gpointer);
1112         }
1113
1114         /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1115         if (cfg->arch.seq_point_info_var) {
1116                 MonoInst *ins;
1117
1118                 ins = cfg->arch.seq_point_info_var;
1119
1120                 size = 4;
1121                 align = 4;
1122                 offset += align - 1;
1123                 offset &= ~(align - 1);
1124                 ins->opcode = OP_REGOFFSET;
1125                 ins->inst_basereg = frame_reg;
1126                 ins->inst_offset = offset;
1127                 offset += size;
1128
1129                 ins = cfg->arch.ss_trigger_page_var;
1130                 size = 4;
1131                 align = 4;
1132                 offset += align - 1;
1133                 offset &= ~(align - 1);
1134                 ins->opcode = OP_REGOFFSET;
1135                 ins->inst_basereg = frame_reg;
1136                 ins->inst_offset = offset;
1137                 offset += size;
1138         }
1139
1140         curinst = cfg->locals_start;
1141         for (i = curinst; i < cfg->num_varinfo; ++i) {
1142                 ins = cfg->varinfo [i];
1143                 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1144                         continue;
1145
1146                 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1147                 * pinvoke wrappers when they call functions returning structure */
1148                 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (ins->inst_vtype) && ins->inst_vtype->type != MONO_TYPE_TYPEDBYREF) {
1149                         size = mono_class_native_size (mono_class_from_mono_type (ins->inst_vtype), &ualign);
1150                         align = ualign;
1151                 }
1152                 else
1153                         size = mono_type_size (ins->inst_vtype, &align);
1154
1155                 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1156                  * since it loads/stores misaligned words, which don't do the right thing.
1157                  */
1158                 if (align < 4 && size >= 4)
1159                         align = 4;
1160                 offset += align - 1;
1161                 offset &= ~(align - 1);
1162                 ins->opcode = OP_REGOFFSET;
1163                 ins->inst_offset = offset;
1164                 ins->inst_basereg = frame_reg;
1165                 offset += size;
1166                 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1167         }
1168
1169         curinst = 0;
1170         if (sig->hasthis) {
1171                 ins = cfg->args [curinst];
1172                 if (ins->opcode != OP_REGVAR) {
1173                         ins->opcode = OP_REGOFFSET;
1174                         ins->inst_basereg = frame_reg;
1175                         offset += sizeof (gpointer) - 1;
1176                         offset &= ~(sizeof (gpointer) - 1);
1177                         ins->inst_offset = offset;
1178                         offset += sizeof (gpointer);
1179                 }
1180                 curinst++;
1181         }
1182
1183         if (sig->call_convention == MONO_CALL_VARARG) {
1184                 size = 4;
1185                 align = 4;
1186
1187                 /* Allocate a local slot to hold the sig cookie address */
1188                 offset += align - 1;
1189                 offset &= ~(align - 1);
1190                 cfg->sig_cookie = offset;
1191                 offset += size;
1192         }
1193
1194         for (i = 0; i < sig->param_count; ++i) {
1195                 ins = cfg->args [curinst];
1196
1197                 if (ins->opcode != OP_REGVAR) {
1198                         ins->opcode = OP_REGOFFSET;
1199                         ins->inst_basereg = frame_reg;
1200                         size = mini_type_stack_size_full (NULL, sig->params [i], &ualign, sig->pinvoke);
1201                         align = ualign;
1202                         /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1203                          * since it loads/stores misaligned words, which don't do the right thing.
1204                          */
1205                         if (align < 4 && size >= 4)
1206                                 align = 4;
1207                         /* The code in the prolog () stores words when storing vtypes received in a register */
1208                         if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1209                                 align = 4;
1210                         offset += align - 1;
1211                         offset &= ~(align - 1);
1212                         ins->inst_offset = offset;
1213                         offset += size;
1214                 }
1215                 curinst++;
1216         }
1217
1218         /* align the offset to 8 bytes */
1219         offset += 8 - 1;
1220         offset &= ~(8 - 1);
1221
1222         /* change sign? */
1223         cfg->stack_offset = offset;
1224 }
1225
1226 void
1227 mono_arch_create_vars (MonoCompile *cfg)
1228 {
1229         MonoMethodSignature *sig;
1230         CallInfo *cinfo;
1231
1232         sig = mono_method_signature (cfg->method);
1233
1234         if (!cfg->arch.cinfo)
1235                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1236         cinfo = cfg->arch.cinfo;
1237
1238         if (cinfo->ret.storage == RegTypeStructByVal)
1239                 cfg->ret_var_is_local = TRUE;
1240
1241         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
1242                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1243                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1244                         printf ("vret_addr = ");
1245                         mono_print_ins (cfg->vret_addr);
1246                 }
1247         }
1248
1249         if (cfg->gen_seq_points && cfg->compile_aot) {
1250             MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1251                 ins->flags |= MONO_INST_VOLATILE;
1252                 cfg->arch.seq_point_info_var = ins;
1253
1254                 /* Allocate a separate variable for this to save 1 load per seq point */
1255             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1256                 ins->flags |= MONO_INST_VOLATILE;
1257                 cfg->arch.ss_trigger_page_var = ins;
1258         }
1259 }
1260
1261 static void
1262 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1263 {
1264         MonoMethodSignature *tmp_sig;
1265         MonoInst *sig_arg;
1266
1267         if (call->tail_call)
1268                 NOT_IMPLEMENTED;
1269
1270         /* FIXME: Add support for signature tokens to AOT */
1271         cfg->disable_aot = TRUE;
1272
1273         g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1274
1275         /*
1276          * mono_ArgIterator_Setup assumes the signature cookie is
1277          * passed first and all the arguments which were before it are
1278          * passed on the stack after the signature. So compensate by
1279          * passing a different signature.
1280          */
1281         tmp_sig = mono_metadata_signature_dup (call->signature);
1282         tmp_sig->param_count -= call->signature->sentinelpos;
1283         tmp_sig->sentinelpos = 0;
1284         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1285
1286         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1287         sig_arg->dreg = mono_alloc_ireg (cfg);
1288         sig_arg->inst_p0 = tmp_sig;
1289         MONO_ADD_INS (cfg->cbb, sig_arg);
1290
1291         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_arg->dreg);
1292 }
1293
1294 #ifdef ENABLE_LLVM
1295 LLVMCallInfo*
1296 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1297 {
1298         int i, n;
1299         CallInfo *cinfo;
1300         ArgInfo *ainfo;
1301         LLVMCallInfo *linfo;
1302
1303         n = sig->param_count + sig->hasthis;
1304
1305         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1306
1307         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1308
1309         /*
1310          * LLVM always uses the native ABI while we use our own ABI, the
1311          * only difference is the handling of vtypes:
1312          * - we only pass/receive them in registers in some cases, and only
1313          *   in 1 or 2 integer registers.
1314          */
1315         if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1316                 cfg->exception_message = g_strdup ("unknown ret conv");
1317                 cfg->disable_llvm = TRUE;
1318                 return linfo;
1319         }
1320
1321         for (i = 0; i < n; ++i) {
1322                 ainfo = cinfo->args + i;
1323
1324                 linfo->args [i].storage = LLVMArgNone;
1325
1326                 switch (ainfo->storage) {
1327                 case RegTypeGeneral:
1328                 case RegTypeIRegPair:
1329                 case RegTypeBase:
1330                         linfo->args [i].storage = LLVMArgInIReg;
1331                         break;
1332                 default:
1333                         cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1334                         cfg->disable_llvm = TRUE;
1335                         break;
1336                 }
1337         }
1338
1339         return linfo;
1340 }
1341 #endif
1342
1343 void
1344 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1345 {
1346         MonoInst *in, *ins;
1347         MonoMethodSignature *sig;
1348         int i, n;
1349         CallInfo *cinfo;
1350
1351         sig = call->signature;
1352         n = sig->param_count + sig->hasthis;
1353
1354         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig, sig->pinvoke);
1355
1356         for (i = 0; i < n; ++i) {
1357                 ArgInfo *ainfo = cinfo->args + i;
1358                 MonoType *t;
1359
1360                 if (i >= sig->hasthis)
1361                         t = sig->params [i - sig->hasthis];
1362                 else
1363                         t = &mono_defaults.int_class->byval_arg;
1364                 t = mini_type_get_underlying_type (NULL, t);
1365
1366                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1367                         /* Emit the signature cookie just before the implicit arguments */
1368                         emit_sig_cookie (cfg, call, cinfo);
1369                 }
1370
1371                 in = call->args [i];
1372
1373                 switch (ainfo->storage) {
1374                 case RegTypeGeneral:
1375                 case RegTypeIRegPair:
1376                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1377                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1378                                 ins->dreg = mono_alloc_ireg (cfg);
1379                                 ins->sreg1 = in->dreg + 1;
1380                                 MONO_ADD_INS (cfg->cbb, ins);
1381                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1382
1383                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1384                                 ins->dreg = mono_alloc_ireg (cfg);
1385                                 ins->sreg1 = in->dreg + 2;
1386                                 MONO_ADD_INS (cfg->cbb, ins);
1387                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1388                         } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1389 #ifndef MONO_ARCH_SOFT_FLOAT
1390                                 int creg;
1391 #endif
1392
1393                                 if (ainfo->size == 4) {
1394 #ifdef MONO_ARCH_SOFT_FLOAT
1395                                         /* mono_emit_call_args () have already done the r8->r4 conversion */
1396                                         /* The converted value is in an int vreg */
1397                                         MONO_INST_NEW (cfg, ins, OP_MOVE);
1398                                         ins->dreg = mono_alloc_ireg (cfg);
1399                                         ins->sreg1 = in->dreg;
1400                                         MONO_ADD_INS (cfg->cbb, ins);
1401                                         mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1402 #else
1403                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1404                                         creg = mono_alloc_ireg (cfg);
1405                                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1406                                         mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1407 #endif
1408                                 } else {
1409 #ifdef MONO_ARCH_SOFT_FLOAT
1410                                         MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1411                                         ins->dreg = mono_alloc_ireg (cfg);
1412                                         ins->sreg1 = in->dreg;
1413                                         MONO_ADD_INS (cfg->cbb, ins);
1414                                         mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1415
1416                                         MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1417                                         ins->dreg = mono_alloc_ireg (cfg);
1418                                         ins->sreg1 = in->dreg;
1419                                         MONO_ADD_INS (cfg->cbb, ins);
1420                                         mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1421 #else
1422                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1423                                         creg = mono_alloc_ireg (cfg);
1424                                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1425                                         mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1426                                         creg = mono_alloc_ireg (cfg);
1427                                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1428                                         mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1429 #endif
1430                                 }
1431                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
1432                         } else {
1433                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1434                                 ins->dreg = mono_alloc_ireg (cfg);
1435                                 ins->sreg1 = in->dreg;
1436                                 MONO_ADD_INS (cfg->cbb, ins);
1437
1438                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1439                         }
1440                         break;
1441                 case RegTypeStructByAddr:
1442                         NOT_IMPLEMENTED;
1443 #if 0
1444                         /* FIXME: where si the data allocated? */
1445                         arg->backend.reg3 = ainfo->reg;
1446                         call->used_iregs |= 1 << ainfo->reg;
1447                         g_assert_not_reached ();
1448 #endif
1449                         break;
1450                 case RegTypeStructByVal:
1451                         MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1452                         ins->opcode = OP_OUTARG_VT;
1453                         ins->sreg1 = in->dreg;
1454                         ins->klass = in->klass;
1455                         ins->inst_p0 = call;
1456                         ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1457                         memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1458                         MONO_ADD_INS (cfg->cbb, ins);
1459                         break;
1460                 case RegTypeBase:
1461                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1462                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1463                         } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1464                                 if (t->type == MONO_TYPE_R8) {
1465                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1466                                 } else {
1467 #ifdef MONO_ARCH_SOFT_FLOAT
1468                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1469 #else
1470                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1471 #endif
1472                                 }
1473                         } else {
1474                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1475                         }
1476                         break;
1477                 case RegTypeBaseGen:
1478                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1479                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1480                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1481                                 ins->dreg = mono_alloc_ireg (cfg);
1482                                 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1483                                 MONO_ADD_INS (cfg->cbb, ins);
1484                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1485                         } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1486                                 int creg;
1487
1488 #ifdef MONO_ARCH_SOFT_FLOAT
1489                                 g_assert_not_reached ();
1490 #endif
1491
1492                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1493                                 creg = mono_alloc_ireg (cfg);
1494                                 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1495                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1496                                 creg = mono_alloc_ireg (cfg);
1497                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1498                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1499                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
1500                         } else {
1501                                 g_assert_not_reached ();
1502                         }
1503                         break;
1504                 case RegTypeFP: {
1505                         /* FIXME: */
1506                         NOT_IMPLEMENTED;
1507 #if 0
1508                         arg->backend.reg3 = ainfo->reg;
1509                         /* FP args are passed in int regs */
1510                         call->used_iregs |= 1 << ainfo->reg;
1511                         if (ainfo->size == 8) {
1512                                 arg->opcode = OP_OUTARG_R8;
1513                                 call->used_iregs |= 1 << (ainfo->reg + 1);
1514                         } else {
1515                                 arg->opcode = OP_OUTARG_R4;
1516                         }
1517 #endif
1518                         cfg->flags |= MONO_CFG_HAS_FPOUT;
1519                         break;
1520                 }
1521                 default:
1522                         g_assert_not_reached ();
1523                 }
1524         }
1525
1526         /* Handle the case where there are no implicit arguments */
1527         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1528                 emit_sig_cookie (cfg, call, cinfo);
1529
1530         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1531                 MonoInst *vtarg;
1532
1533                 if (cinfo->ret.storage == RegTypeStructByVal) {
1534                         /* The JIT will transform this into a normal call */
1535                         call->vret_in_reg = TRUE;
1536                 } else {
1537                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1538                         vtarg->sreg1 = call->vret_var->dreg;
1539                         vtarg->dreg = mono_alloc_preg (cfg);
1540                         MONO_ADD_INS (cfg->cbb, vtarg);
1541
1542                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1543                 }
1544         }
1545
1546         call->stack_usage = cinfo->stack_usage;
1547
1548         g_free (cinfo);
1549 }
1550
1551 void
1552 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1553 {
1554         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1555         ArgInfo *ainfo = ins->inst_p1;
1556         int ovf_size = ainfo->vtsize;
1557         int doffset = ainfo->offset;
1558         int i, soffset, dreg;
1559
1560         soffset = 0;
1561         for (i = 0; i < ainfo->size; ++i) {
1562                 dreg = mono_alloc_ireg (cfg);
1563                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1564                 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
1565                 soffset += sizeof (gpointer);
1566         }
1567         //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
1568         if (ovf_size != 0)
1569                 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, ovf_size * sizeof (gpointer), 0);
1570 }
1571
1572 void
1573 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1574 {
1575         MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1576
1577         if (!ret->byref) {
1578                 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1579                         MonoInst *ins;
1580
1581                         if (COMPILE_LLVM (cfg)) {
1582                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1583                         } else {
1584                                 MONO_INST_NEW (cfg, ins, OP_SETLRET);
1585                                 ins->sreg1 = val->dreg + 1;
1586                                 ins->sreg2 = val->dreg + 2;
1587                                 MONO_ADD_INS (cfg->cbb, ins);
1588                         }
1589                         return;
1590                 }
1591 #ifdef MONO_ARCH_SOFT_FLOAT
1592                 if (ret->type == MONO_TYPE_R8) {
1593                         MonoInst *ins;
1594
1595                         MONO_INST_NEW (cfg, ins, OP_SETFRET);
1596                         ins->dreg = cfg->ret->dreg;
1597                         ins->sreg1 = val->dreg;
1598                         MONO_ADD_INS (cfg->cbb, ins);
1599                         return;
1600                 }
1601                 if (ret->type == MONO_TYPE_R4) {
1602                         /* Already converted to an int in method_to_ir () */
1603                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1604                         return;
1605                 }
1606 #elif defined(ARM_FPU_VFP)
1607                 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
1608                         MonoInst *ins;
1609
1610                         MONO_INST_NEW (cfg, ins, OP_SETFRET);
1611                         ins->dreg = cfg->ret->dreg;
1612                         ins->sreg1 = val->dreg;
1613                         MONO_ADD_INS (cfg->cbb, ins);
1614                         return;
1615                 }
1616 #else
1617                 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
1618                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1619                         return;
1620                 }
1621 #endif
1622         }
1623
1624         /* FIXME: */
1625         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1626 }
1627
1628 #endif /* #ifndef DISABLE_JIT */
1629
1630 gboolean
1631 mono_arch_is_inst_imm (gint64 imm)
1632 {
1633         return TRUE;
1634 }
1635
1636 #define DYN_CALL_STACK_ARGS 6
1637
1638 typedef struct {
1639         MonoMethodSignature *sig;
1640         CallInfo *cinfo;
1641 } ArchDynCallInfo;
1642
1643 typedef struct {
1644         mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
1645         mgreg_t res, res2;
1646         guint8 *ret;
1647 } DynCallArgs;
1648
1649 static gboolean
1650 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
1651 {
1652         int i;
1653
1654         if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
1655                 return FALSE;
1656
1657         switch (cinfo->ret.storage) {
1658         case RegTypeNone:
1659         case RegTypeGeneral:
1660         case RegTypeIRegPair:
1661         case RegTypeStructByAddr:
1662                 break;
1663         case RegTypeFP:
1664 #ifdef ARM_FPU_FPA
1665                 return FALSE;
1666 #elif defined(ARM_FPU_VFP)
1667                 break;
1668 #else
1669                 return FALSE;
1670 #endif
1671         default:
1672                 return FALSE;
1673         }
1674
1675         for (i = 0; i < cinfo->nargs; ++i) {
1676                 switch (cinfo->args [i].storage) {
1677                 case RegTypeGeneral:
1678                         break;
1679                 case RegTypeIRegPair:
1680                         break;
1681                 case RegTypeBase:
1682                         if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
1683                                 return FALSE;
1684                         break;
1685                 case RegTypeStructByVal:
1686                         if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
1687                                 return FALSE;
1688                         break;
1689                 default:
1690                         return FALSE;
1691                 }
1692         }
1693
1694         // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
1695         for (i = 0; i < sig->param_count; ++i) {
1696                 MonoType *t = sig->params [i];
1697
1698                 if (t->byref)
1699                         continue;
1700
1701                 switch (t->type) {
1702                 case MONO_TYPE_R4:
1703                 case MONO_TYPE_R8:
1704 #ifdef MONO_ARCH_SOFT_FLOAT
1705                         return FALSE;
1706 #else
1707                         break;
1708 #endif
1709                         /*
1710                 case MONO_TYPE_I8:
1711                 case MONO_TYPE_U8:
1712                         return FALSE;
1713                         */
1714                 default:
1715                         break;
1716                 }
1717         }
1718
1719         return TRUE;
1720 }
1721
1722 MonoDynCallInfo*
1723 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
1724 {
1725         ArchDynCallInfo *info;
1726         CallInfo *cinfo;
1727
1728         cinfo = get_call_info (NULL, NULL, sig, FALSE);
1729
1730         if (!dyn_call_supported (cinfo, sig)) {
1731                 g_free (cinfo);
1732                 return NULL;
1733         }
1734
1735         info = g_new0 (ArchDynCallInfo, 1);
1736         // FIXME: Preprocess the info to speed up start_dyn_call ()
1737         info->sig = sig;
1738         info->cinfo = cinfo;
1739
1740         return (MonoDynCallInfo*)info;
1741 }
1742
1743 void
1744 mono_arch_dyn_call_free (MonoDynCallInfo *info)
1745 {
1746         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1747
1748         g_free (ainfo->cinfo);
1749         g_free (ainfo);
1750 }
1751
1752 void
1753 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
1754 {
1755         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
1756         DynCallArgs *p = (DynCallArgs*)buf;
1757         int arg_index, greg, i, j;
1758         MonoMethodSignature *sig = dinfo->sig;
1759
1760         g_assert (buf_len >= sizeof (DynCallArgs));
1761
1762         p->res = 0;
1763         p->ret = ret;
1764
1765         arg_index = 0;
1766         greg = 0;
1767
1768         if (dinfo->cinfo->vtype_retaddr)
1769                 p->regs [greg ++] = (mgreg_t)ret;
1770
1771         if (sig->hasthis)
1772                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
1773
1774         for (i = 0; i < sig->param_count; i++) {
1775                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
1776                 gpointer *arg = args [arg_index ++];
1777                 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
1778                 int slot = -1;
1779
1780                 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
1781                         slot = ainfo->reg;
1782                 else if (ainfo->storage == RegTypeBase)
1783                         slot = PARAM_REGS + (ainfo->offset / 4);
1784                 else
1785                         g_assert_not_reached ();
1786
1787                 if (t->byref) {
1788                         p->regs [slot] = (mgreg_t)*arg;
1789                         continue;
1790                 }
1791
1792                 switch (t->type) {
1793                 case MONO_TYPE_STRING:
1794                 case MONO_TYPE_CLASS:
1795                 case MONO_TYPE_ARRAY:
1796                 case MONO_TYPE_SZARRAY:
1797                 case MONO_TYPE_OBJECT:
1798                 case MONO_TYPE_PTR:
1799                 case MONO_TYPE_I:
1800                 case MONO_TYPE_U:
1801                         p->regs [slot] = (mgreg_t)*arg;
1802                         break;
1803                 case MONO_TYPE_BOOLEAN:
1804                 case MONO_TYPE_U1:
1805                         p->regs [slot] = *(guint8*)arg;
1806                         break;
1807                 case MONO_TYPE_I1:
1808                         p->regs [slot] = *(gint8*)arg;
1809                         break;
1810                 case MONO_TYPE_I2:
1811                         p->regs [slot] = *(gint16*)arg;
1812                         break;
1813                 case MONO_TYPE_U2:
1814                 case MONO_TYPE_CHAR:
1815                         p->regs [slot] = *(guint16*)arg;
1816                         break;
1817                 case MONO_TYPE_I4:
1818                         p->regs [slot] = *(gint32*)arg;
1819                         break;
1820                 case MONO_TYPE_U4:
1821                         p->regs [slot] = *(guint32*)arg;
1822                         break;
1823                 case MONO_TYPE_I8:
1824                 case MONO_TYPE_U8:
1825                         p->regs [slot ++] = (mgreg_t)arg [0];
1826                         p->regs [slot] = (mgreg_t)arg [1];
1827                         break;
1828                 case MONO_TYPE_R4:
1829                         p->regs [slot] = *(mgreg_t*)arg;
1830                         break;
1831                 case MONO_TYPE_R8:
1832                         p->regs [slot ++] = (mgreg_t)arg [0];
1833                         p->regs [slot] = (mgreg_t)arg [1];
1834                         break;
1835                 case MONO_TYPE_GENERICINST:
1836                         if (MONO_TYPE_IS_REFERENCE (t)) {
1837                                 p->regs [slot] = (mgreg_t)*arg;
1838                                 break;
1839                         } else {
1840                                 /* Fall though */
1841                         }
1842                 case MONO_TYPE_VALUETYPE:
1843                         g_assert (ainfo->storage == RegTypeStructByVal);
1844
1845                         if (ainfo->size == 0)
1846                                 slot = PARAM_REGS + (ainfo->offset / 4);
1847                         else
1848                                 slot = ainfo->reg;
1849
1850                         for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
1851                                 p->regs [slot ++] = ((mgreg_t*)arg) [j];
1852                         break;
1853                 default:
1854                         g_assert_not_reached ();
1855                 }
1856         }
1857 }
1858
1859 void
1860 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
1861 {
1862         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1863         MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
1864         guint8 *ret = ((DynCallArgs*)buf)->ret;
1865         mgreg_t res = ((DynCallArgs*)buf)->res;
1866         mgreg_t res2 = ((DynCallArgs*)buf)->res2;
1867
1868         switch (mono_type_get_underlying_type (sig->ret)->type) {
1869         case MONO_TYPE_VOID:
1870                 *(gpointer*)ret = NULL;
1871                 break;
1872         case MONO_TYPE_STRING:
1873         case MONO_TYPE_CLASS:
1874         case MONO_TYPE_ARRAY:
1875         case MONO_TYPE_SZARRAY:
1876         case MONO_TYPE_OBJECT:
1877         case MONO_TYPE_I:
1878         case MONO_TYPE_U:
1879         case MONO_TYPE_PTR:
1880                 *(gpointer*)ret = (gpointer)res;
1881                 break;
1882         case MONO_TYPE_I1:
1883                 *(gint8*)ret = res;
1884                 break;
1885         case MONO_TYPE_U1:
1886         case MONO_TYPE_BOOLEAN:
1887                 *(guint8*)ret = res;
1888                 break;
1889         case MONO_TYPE_I2:
1890                 *(gint16*)ret = res;
1891                 break;
1892         case MONO_TYPE_U2:
1893         case MONO_TYPE_CHAR:
1894                 *(guint16*)ret = res;
1895                 break;
1896         case MONO_TYPE_I4:
1897                 *(gint32*)ret = res;
1898                 break;
1899         case MONO_TYPE_U4:
1900                 *(guint32*)ret = res;
1901                 break;
1902         case MONO_TYPE_I8:
1903         case MONO_TYPE_U8:
1904                 /* This handles endianness as well */
1905                 ((gint32*)ret) [0] = res;
1906                 ((gint32*)ret) [1] = res2;
1907                 break;
1908         case MONO_TYPE_GENERICINST:
1909                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
1910                         *(gpointer*)ret = (gpointer)res;
1911                         break;
1912                 } else {
1913                         /* Fall though */
1914                 }
1915         case MONO_TYPE_VALUETYPE:
1916                 g_assert (ainfo->cinfo->vtype_retaddr);
1917                 /* Nothing to do */
1918                 break;
1919 #if defined(ARM_FPU_VFP)
1920         case MONO_TYPE_R4:
1921                 *(float*)ret = *(float*)&res;
1922                 break;
1923         case MONO_TYPE_R8: {
1924                 mgreg_t regs [2];
1925
1926                 regs [0] = res;
1927                 regs [1] = res2;
1928
1929                 *(double*)ret = *(double*)&regs;
1930                 break;
1931         }
1932 #endif
1933         default:
1934                 g_assert_not_reached ();
1935         }
1936 }
1937
1938 #ifndef DISABLE_JIT
1939
1940 /*
1941  * Allow tracing to work with this interface (with an optional argument)
1942  */
1943
1944 void*
1945 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1946 {
1947         guchar *code = p;
1948
1949         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
1950         ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
1951         code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
1952         code = emit_call_reg (code, ARMREG_R2);
1953         return code;
1954 }
1955
1956 enum {
1957         SAVE_NONE,
1958         SAVE_STRUCT,
1959         SAVE_ONE,
1960         SAVE_TWO,
1961         SAVE_FP
1962 };
1963
1964 void*
1965 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1966 {
1967         guchar *code = p;
1968         int save_mode = SAVE_NONE;
1969         int offset;
1970         MonoMethod *method = cfg->method;
1971         int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
1972         int save_offset = cfg->param_area;
1973         save_offset += 7;
1974         save_offset &= ~7;
1975
1976         offset = code - cfg->native_code;
1977         /* we need about 16 instructions */
1978         if (offset > (cfg->code_size - 16 * 4)) {
1979                 cfg->code_size *= 2;
1980                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
1981                 code = cfg->native_code + offset;
1982         }
1983         switch (rtype) {
1984         case MONO_TYPE_VOID:
1985                 /* special case string .ctor icall */
1986                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
1987                         save_mode = SAVE_ONE;
1988                 else
1989                         save_mode = SAVE_NONE;
1990                 break;
1991         case MONO_TYPE_I8:
1992         case MONO_TYPE_U8:
1993                 save_mode = SAVE_TWO;
1994                 break;
1995         case MONO_TYPE_R4:
1996         case MONO_TYPE_R8:
1997                 save_mode = SAVE_FP;
1998                 break;
1999         case MONO_TYPE_VALUETYPE:
2000                 save_mode = SAVE_STRUCT;
2001                 break;
2002         default:
2003                 save_mode = SAVE_ONE;
2004                 break;
2005         }
2006
2007         switch (save_mode) {
2008         case SAVE_TWO:
2009                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2010                 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2011                 if (enable_arguments) {
2012                         ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2013                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2014                 }
2015                 break;
2016         case SAVE_ONE:
2017                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2018                 if (enable_arguments) {
2019                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2020                 }
2021                 break;
2022         case SAVE_FP:
2023                 /* FIXME: what reg?  */
2024                 if (enable_arguments) {
2025                         /* FIXME: what reg?  */
2026                 }
2027                 break;
2028         case SAVE_STRUCT:
2029                 if (enable_arguments) {
2030                         /* FIXME: get the actual address  */
2031                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2032                 }
2033                 break;
2034         case SAVE_NONE:
2035         default:
2036                 break;
2037         }
2038
2039         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2040         code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2041         code = emit_call_reg (code, ARMREG_IP);
2042
2043         switch (save_mode) {
2044         case SAVE_TWO:
2045                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2046                 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2047                 break;
2048         case SAVE_ONE:
2049                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2050                 break;
2051         case SAVE_FP:
2052                 /* FIXME */
2053                 break;
2054         case SAVE_NONE:
2055         default:
2056                 break;
2057         }
2058
2059         return code;
2060 }
2061
2062 /*
2063  * The immediate field for cond branches is big enough for all reasonable methods
2064  */
2065 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2066 if (0 && ins->inst_true_bb->native_offset) { \
2067         ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2068 } else { \
2069         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2070         ARM_B_COND (code, (condcode), 0);       \
2071 }
2072
2073 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2074
2075 /* emit an exception if condition is fail
2076  *
2077  * We assign the extra code used to throw the implicit exceptions
2078  * to cfg->bb_exit as far as the big branch handling is concerned
2079  */
2080 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name)            \
2081         do {                                                        \
2082                 mono_add_patch_info (cfg, code - cfg->native_code,   \
2083                                     MONO_PATCH_INFO_EXC, exc_name);  \
2084                 ARM_BL_COND (code, (condcode), 0);      \
2085         } while (0);
2086
2087 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2088
2089 void
2090 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2091 {
2092 }
2093
2094 void
2095 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2096 {
2097         MonoInst *ins, *n, *last_ins = NULL;
2098
2099         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2100                 switch (ins->opcode) {
2101                 case OP_MUL_IMM:
2102                 case OP_IMUL_IMM:
2103                         /* Already done by an arch-independent pass */
2104                         break;
2105                 case OP_LOAD_MEMBASE:
2106                 case OP_LOADI4_MEMBASE:
2107                         /*
2108                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2109                          * OP_LOAD_MEMBASE offset(basereg), reg
2110                          */
2111                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2112                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2113                             ins->inst_basereg == last_ins->inst_destbasereg &&
2114                             ins->inst_offset == last_ins->inst_offset) {
2115                                 if (ins->dreg == last_ins->sreg1) {
2116                                         MONO_DELETE_INS (bb, ins);
2117                                         continue;
2118                                 } else {
2119                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2120                                         ins->opcode = OP_MOVE;
2121                                         ins->sreg1 = last_ins->sreg1;
2122                                 }
2123
2124                         /*
2125                          * Note: reg1 must be different from the basereg in the second load
2126                          * OP_LOAD_MEMBASE offset(basereg), reg1
2127                          * OP_LOAD_MEMBASE offset(basereg), reg2
2128                          * -->
2129                          * OP_LOAD_MEMBASE offset(basereg), reg1
2130                          * OP_MOVE reg1, reg2
2131                          */
2132                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2133                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
2134                               ins->inst_basereg != last_ins->dreg &&
2135                               ins->inst_basereg == last_ins->inst_basereg &&
2136                               ins->inst_offset == last_ins->inst_offset) {
2137
2138                                 if (ins->dreg == last_ins->dreg) {
2139                                         MONO_DELETE_INS (bb, ins);
2140                                         continue;
2141                                 } else {
2142                                         ins->opcode = OP_MOVE;
2143                                         ins->sreg1 = last_ins->dreg;
2144                                 }
2145
2146                                 //g_assert_not_reached ();
2147
2148 #if 0
2149                         /*
2150                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2151                          * OP_LOAD_MEMBASE offset(basereg), reg
2152                          * -->
2153                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2154                          * OP_ICONST reg, imm
2155                          */
2156                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2157                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2158                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2159                                    ins->inst_offset == last_ins->inst_offset) {
2160                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2161                                 ins->opcode = OP_ICONST;
2162                                 ins->inst_c0 = last_ins->inst_imm;
2163                                 g_assert_not_reached (); // check this rule
2164 #endif
2165                         }
2166                         break;
2167                 case OP_LOADU1_MEMBASE:
2168                 case OP_LOADI1_MEMBASE:
2169                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2170                                         ins->inst_basereg == last_ins->inst_destbasereg &&
2171                                         ins->inst_offset == last_ins->inst_offset) {
2172                                 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2173                                 ins->sreg1 = last_ins->sreg1;
2174                         }
2175                         break;
2176                 case OP_LOADU2_MEMBASE:
2177                 case OP_LOADI2_MEMBASE:
2178                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2179                                         ins->inst_basereg == last_ins->inst_destbasereg &&
2180                                         ins->inst_offset == last_ins->inst_offset) {
2181                                 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2182                                 ins->sreg1 = last_ins->sreg1;
2183                         }
2184                         break;
2185                 case OP_MOVE:
2186                         ins->opcode = OP_MOVE;
2187                         /*
2188                          * OP_MOVE reg, reg
2189                          */
2190                         if (ins->dreg == ins->sreg1) {
2191                                 MONO_DELETE_INS (bb, ins);
2192                                 continue;
2193                         }
2194                         /*
2195                          * OP_MOVE sreg, dreg
2196                          * OP_MOVE dreg, sreg
2197                          */
2198                         if (last_ins && last_ins->opcode == OP_MOVE &&
2199                             ins->sreg1 == last_ins->dreg &&
2200                             ins->dreg == last_ins->sreg1) {
2201                                 MONO_DELETE_INS (bb, ins);
2202                                 continue;
2203                         }
2204                         break;
2205                 }
2206                 last_ins = ins;
2207                 ins = ins->next;
2208         }
2209         bb->last_ins = last_ins;
2210 }
2211
2212 /*
2213  * the branch_cc_table should maintain the order of these
2214  * opcodes.
2215 case CEE_BEQ:
2216 case CEE_BGE:
2217 case CEE_BGT:
2218 case CEE_BLE:
2219 case CEE_BLT:
2220 case CEE_BNE_UN:
2221 case CEE_BGE_UN:
2222 case CEE_BGT_UN:
2223 case CEE_BLE_UN:
2224 case CEE_BLT_UN:
2225  */
2226 static const guchar
2227 branch_cc_table [] = {
2228         ARMCOND_EQ,
2229         ARMCOND_GE,
2230         ARMCOND_GT,
2231         ARMCOND_LE,
2232         ARMCOND_LT,
2233
2234         ARMCOND_NE,
2235         ARMCOND_HS,
2236         ARMCOND_HI,
2237         ARMCOND_LS,
2238         ARMCOND_LO
2239 };
2240
2241 #define NEW_INS(cfg,dest,op) do {       \
2242                 MONO_INST_NEW ((cfg), (dest), (op)); \
2243         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2244         } while (0)
2245
2246 static int
2247 map_to_reg_reg_op (int op)
2248 {
2249         switch (op) {
2250         case OP_ADD_IMM:
2251                 return OP_IADD;
2252         case OP_SUB_IMM:
2253                 return OP_ISUB;
2254         case OP_AND_IMM:
2255                 return OP_IAND;
2256         case OP_COMPARE_IMM:
2257                 return OP_COMPARE;
2258         case OP_ICOMPARE_IMM:
2259                 return OP_ICOMPARE;
2260         case OP_ADDCC_IMM:
2261                 return OP_ADDCC;
2262         case OP_ADC_IMM:
2263                 return OP_ADC;
2264         case OP_SUBCC_IMM:
2265                 return OP_SUBCC;
2266         case OP_SBB_IMM:
2267                 return OP_SBB;
2268         case OP_OR_IMM:
2269                 return OP_IOR;
2270         case OP_XOR_IMM:
2271                 return OP_IXOR;
2272         case OP_LOAD_MEMBASE:
2273                 return OP_LOAD_MEMINDEX;
2274         case OP_LOADI4_MEMBASE:
2275                 return OP_LOADI4_MEMINDEX;
2276         case OP_LOADU4_MEMBASE:
2277                 return OP_LOADU4_MEMINDEX;
2278         case OP_LOADU1_MEMBASE:
2279                 return OP_LOADU1_MEMINDEX;
2280         case OP_LOADI2_MEMBASE:
2281                 return OP_LOADI2_MEMINDEX;
2282         case OP_LOADU2_MEMBASE:
2283                 return OP_LOADU2_MEMINDEX;
2284         case OP_LOADI1_MEMBASE:
2285                 return OP_LOADI1_MEMINDEX;
2286         case OP_STOREI1_MEMBASE_REG:
2287                 return OP_STOREI1_MEMINDEX;
2288         case OP_STOREI2_MEMBASE_REG:
2289                 return OP_STOREI2_MEMINDEX;
2290         case OP_STOREI4_MEMBASE_REG:
2291                 return OP_STOREI4_MEMINDEX;
2292         case OP_STORE_MEMBASE_REG:
2293                 return OP_STORE_MEMINDEX;
2294         case OP_STORER4_MEMBASE_REG:
2295                 return OP_STORER4_MEMINDEX;
2296         case OP_STORER8_MEMBASE_REG:
2297                 return OP_STORER8_MEMINDEX;
2298         case OP_STORE_MEMBASE_IMM:
2299                 return OP_STORE_MEMBASE_REG;
2300         case OP_STOREI1_MEMBASE_IMM:
2301                 return OP_STOREI1_MEMBASE_REG;
2302         case OP_STOREI2_MEMBASE_IMM:
2303                 return OP_STOREI2_MEMBASE_REG;
2304         case OP_STOREI4_MEMBASE_IMM:
2305                 return OP_STOREI4_MEMBASE_REG;
2306         }
2307         g_assert_not_reached ();
2308 }
2309
2310 /*
2311  * Remove from the instruction list the instructions that can't be
2312  * represented with very simple instructions with no register
2313  * requirements.
2314  */
2315 void
2316 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2317 {
2318         MonoInst *ins, *temp, *last_ins = NULL;
2319         int rot_amount, imm8, low_imm;
2320
2321         MONO_BB_FOR_EACH_INS (bb, ins) {
2322 loop_start:
2323                 switch (ins->opcode) {
2324                 case OP_ADD_IMM:
2325                 case OP_SUB_IMM:
2326                 case OP_AND_IMM:
2327                 case OP_COMPARE_IMM:
2328                 case OP_ICOMPARE_IMM:
2329                 case OP_ADDCC_IMM:
2330                 case OP_ADC_IMM:
2331                 case OP_SUBCC_IMM:
2332                 case OP_SBB_IMM:
2333                 case OP_OR_IMM:
2334                 case OP_XOR_IMM:
2335                 case OP_IADD_IMM:
2336                 case OP_ISUB_IMM:
2337                 case OP_IAND_IMM:
2338                 case OP_IADC_IMM:
2339                 case OP_ISBB_IMM:
2340                 case OP_IOR_IMM:
2341                 case OP_IXOR_IMM:
2342                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2343                                 NEW_INS (cfg, temp, OP_ICONST);
2344                                 temp->inst_c0 = ins->inst_imm;
2345                                 temp->dreg = mono_alloc_ireg (cfg);
2346                                 ins->sreg2 = temp->dreg;
2347                                 ins->opcode = mono_op_imm_to_op (ins->opcode);
2348                         }
2349                         if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2350                                 goto loop_start;
2351                         else
2352                                 break;
2353                 case OP_MUL_IMM:
2354                 case OP_IMUL_IMM:
2355                         if (ins->inst_imm == 1) {
2356                                 ins->opcode = OP_MOVE;
2357                                 break;
2358                         }
2359                         if (ins->inst_imm == 0) {
2360                                 ins->opcode = OP_ICONST;
2361                                 ins->inst_c0 = 0;
2362                                 break;
2363                         }
2364                         imm8 = mono_is_power_of_two (ins->inst_imm);
2365                         if (imm8 > 0) {
2366                                 ins->opcode = OP_SHL_IMM;
2367                                 ins->inst_imm = imm8;
2368                                 break;
2369                         }
2370                         NEW_INS (cfg, temp, OP_ICONST);
2371                         temp->inst_c0 = ins->inst_imm;
2372                         temp->dreg = mono_alloc_ireg (cfg);
2373                         ins->sreg2 = temp->dreg;
2374                         ins->opcode = OP_IMUL;
2375                         break;
2376                 case OP_SBB:
2377                 case OP_ISBB:
2378                 case OP_SUBCC:
2379                 case OP_ISUBCC:
2380                         if (ins->next  && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2381                                 /* ARM sets the C flag to 1 if there was _no_ overflow */
2382                                 ins->next->opcode = OP_COND_EXC_NC;
2383                         break;
2384                 case OP_LOCALLOC_IMM:
2385                         NEW_INS (cfg, temp, OP_ICONST);
2386                         temp->inst_c0 = ins->inst_imm;
2387                         temp->dreg = mono_alloc_ireg (cfg);
2388                         ins->sreg1 = temp->dreg;
2389                         ins->opcode = OP_LOCALLOC;
2390                         break;
2391                 case OP_LOAD_MEMBASE:
2392                 case OP_LOADI4_MEMBASE:
2393                 case OP_LOADU4_MEMBASE:
2394                 case OP_LOADU1_MEMBASE:
2395                         /* we can do two things: load the immed in a register
2396                          * and use an indexed load, or see if the immed can be
2397                          * represented as an ad_imm + a load with a smaller offset
2398                          * that fits. We just do the first for now, optimize later.
2399                          */
2400                         if (arm_is_imm12 (ins->inst_offset))
2401                                 break;
2402                         NEW_INS (cfg, temp, OP_ICONST);
2403                         temp->inst_c0 = ins->inst_offset;
2404                         temp->dreg = mono_alloc_ireg (cfg);
2405                         ins->sreg2 = temp->dreg;
2406                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2407                         break;
2408                 case OP_LOADI2_MEMBASE:
2409                 case OP_LOADU2_MEMBASE:
2410                 case OP_LOADI1_MEMBASE:
2411                         if (arm_is_imm8 (ins->inst_offset))
2412                                 break;
2413                         NEW_INS (cfg, temp, OP_ICONST);
2414                         temp->inst_c0 = ins->inst_offset;
2415                         temp->dreg = mono_alloc_ireg (cfg);
2416                         ins->sreg2 = temp->dreg;
2417                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2418                         break;
2419                 case OP_LOADR4_MEMBASE:
2420                 case OP_LOADR8_MEMBASE:
2421                         if (arm_is_fpimm8 (ins->inst_offset))
2422                                 break;
2423                         low_imm = ins->inst_offset & 0x1ff;
2424                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2425                                 NEW_INS (cfg, temp, OP_ADD_IMM);
2426                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
2427                                 temp->sreg1 = ins->inst_basereg;
2428                                 temp->dreg = mono_alloc_ireg (cfg);
2429                                 ins->inst_basereg = temp->dreg;
2430                                 ins->inst_offset = low_imm;
2431                                 break;
2432                         }
2433                         /* VFP/FPA doesn't have indexed load instructions */
2434                         g_assert_not_reached ();
2435                         break;
2436                 case OP_STORE_MEMBASE_REG:
2437                 case OP_STOREI4_MEMBASE_REG:
2438                 case OP_STOREI1_MEMBASE_REG:
2439                         if (arm_is_imm12 (ins->inst_offset))
2440                                 break;
2441                         NEW_INS (cfg, temp, OP_ICONST);
2442                         temp->inst_c0 = ins->inst_offset;
2443                         temp->dreg = mono_alloc_ireg (cfg);
2444                         ins->sreg2 = temp->dreg;
2445                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2446                         break;
2447                 case OP_STOREI2_MEMBASE_REG:
2448                         if (arm_is_imm8 (ins->inst_offset))
2449                                 break;
2450                         NEW_INS (cfg, temp, OP_ICONST);
2451                         temp->inst_c0 = ins->inst_offset;
2452                         temp->dreg = mono_alloc_ireg (cfg);
2453                         ins->sreg2 = temp->dreg;
2454                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2455                         break;
2456                 case OP_STORER4_MEMBASE_REG:
2457                 case OP_STORER8_MEMBASE_REG:
2458                         if (arm_is_fpimm8 (ins->inst_offset))
2459                                 break;
2460                         low_imm = ins->inst_offset & 0x1ff;
2461                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2462                                 NEW_INS (cfg, temp, OP_ADD_IMM);
2463                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
2464                                 temp->sreg1 = ins->inst_destbasereg;
2465                                 temp->dreg = mono_alloc_ireg (cfg);
2466                                 ins->inst_destbasereg = temp->dreg;
2467                                 ins->inst_offset = low_imm;
2468                                 break;
2469                         }
2470                         /*g_print ("fail with: %d (%d, %d)\n", ins->inst_offset, ins->inst_offset & ~0x1ff, low_imm);*/
2471                         /* VFP/FPA doesn't have indexed store instructions */
2472                         g_assert_not_reached ();
2473                         break;
2474                 case OP_STORE_MEMBASE_IMM:
2475                 case OP_STOREI1_MEMBASE_IMM:
2476                 case OP_STOREI2_MEMBASE_IMM:
2477                 case OP_STOREI4_MEMBASE_IMM:
2478                         NEW_INS (cfg, temp, OP_ICONST);
2479                         temp->inst_c0 = ins->inst_imm;
2480                         temp->dreg = mono_alloc_ireg (cfg);
2481                         ins->sreg1 = temp->dreg;
2482                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2483                         last_ins = temp;
2484                         goto loop_start; /* make it handle the possibly big ins->inst_offset */
2485                 case OP_FCOMPARE: {
2486                         gboolean swap = FALSE;
2487                         int reg;
2488
2489                         if (!ins->next) {
2490                                 /* Optimized away */
2491                                 NULLIFY_INS (ins);
2492                                 break;
2493                         }
2494
2495                         /* Some fp compares require swapped operands */
2496                         switch (ins->next->opcode) {
2497                         case OP_FBGT:
2498                                 ins->next->opcode = OP_FBLT;
2499                                 swap = TRUE;
2500                                 break;
2501                         case OP_FBGT_UN:
2502                                 ins->next->opcode = OP_FBLT_UN;
2503                                 swap = TRUE;
2504                                 break;
2505                         case OP_FBLE:
2506                                 ins->next->opcode = OP_FBGE;
2507                                 swap = TRUE;
2508                                 break;
2509                         case OP_FBLE_UN:
2510                                 ins->next->opcode = OP_FBGE_UN;
2511                                 swap = TRUE;
2512                                 break;
2513                         default:
2514                                 break;
2515                         }
2516                         if (swap) {
2517                                 reg = ins->sreg1;
2518                                 ins->sreg1 = ins->sreg2;
2519                                 ins->sreg2 = reg;
2520                         }
2521                         break;
2522                 }
2523                 }
2524
2525                 last_ins = ins;
2526         }
2527         bb->last_ins = last_ins;
2528         bb->max_vreg = cfg->next_vreg;
2529 }
2530
2531 void
2532 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2533 {
2534         MonoInst *ins;
2535
2536         if (long_ins->opcode == OP_LNEG) {
2537                 ins = long_ins;
2538                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
2539                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
2540                 NULLIFY_INS (ins);
2541         }
2542 }
2543
2544 static guchar*
2545 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2546 {
2547         /* sreg is a float, dreg is an integer reg  */
2548 #ifdef ARM_FPU_FPA
2549         ARM_FIXZ (code, dreg, sreg);
2550 #elif defined(ARM_FPU_VFP)
2551         if (is_signed)
2552                 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
2553         else
2554                 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
2555         ARM_FMRS (code, dreg, ARM_VFP_F0);
2556 #endif
2557         if (!is_signed) {
2558                 if (size == 1)
2559                         ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
2560                 else if (size == 2) {
2561                         ARM_SHL_IMM (code, dreg, dreg, 16);
2562                         ARM_SHR_IMM (code, dreg, dreg, 16);
2563                 }
2564         } else {
2565                 if (size == 1) {
2566                         ARM_SHL_IMM (code, dreg, dreg, 24);
2567                         ARM_SAR_IMM (code, dreg, dreg, 24);
2568                 } else if (size == 2) {
2569                         ARM_SHL_IMM (code, dreg, dreg, 16);
2570                         ARM_SAR_IMM (code, dreg, dreg, 16);
2571                 }
2572         }
2573         return code;
2574 }
2575
2576 #endif /* #ifndef DISABLE_JIT */
2577
2578 typedef struct {
2579         guchar *code;
2580         const guchar *target;
2581         int absolute;
2582         int found;
2583 } PatchData;
2584
2585 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
2586
2587 static int
2588 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
2589         PatchData *pdata = (PatchData*)user_data;
2590         guchar *code = data;
2591         guint32 *thunks = data;
2592         guint32 *endthunks = (guint32*)(code + bsize);
2593         int count = 0;
2594         int difflow, diffhigh;
2595
2596         /* always ensure a call from pdata->code can reach to the thunks without further thunks */
2597         difflow = (char*)pdata->code - (char*)thunks;
2598         diffhigh = (char*)pdata->code - (char*)endthunks;
2599         if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
2600                 return 0;
2601
2602         /*
2603          * The thunk is composed of 3 words:
2604          * load constant from thunks [2] into ARM_IP
2605          * bx to ARM_IP
2606          * address constant
2607          * Note that the LR register is already setup
2608          */
2609         //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
2610         if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
2611                 while (thunks < endthunks) {
2612                         //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
2613                         if (thunks [2] == (guint32)pdata->target) {
2614                                 arm_patch (pdata->code, (guchar*)thunks);
2615                                 mono_arch_flush_icache (pdata->code, 4);
2616                                 pdata->found = 1;
2617                                 return 1;
2618                         } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
2619                                 /* found a free slot instead: emit thunk */
2620                                 /* ARMREG_IP is fine to use since this can't be an IMT call
2621                                  * which is indirect
2622                                  */
2623                                 code = (guchar*)thunks;
2624                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2625                                 if (thumb_supported)
2626                                         ARM_BX (code, ARMREG_IP);
2627                                 else
2628                                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2629                                 thunks [2] = (guint32)pdata->target;
2630                                 mono_arch_flush_icache ((guchar*)thunks, 12);
2631
2632                                 arm_patch (pdata->code, (guchar*)thunks);
2633                                 mono_arch_flush_icache (pdata->code, 4);
2634                                 pdata->found = 1;
2635                                 return 1;
2636                         }
2637                         /* skip 12 bytes, the size of the thunk */
2638                         thunks += 3;
2639                         count++;
2640                 }
2641                 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
2642         }
2643         return 0;
2644 }
2645
2646 static void
2647 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target)
2648 {
2649         PatchData pdata;
2650
2651         if (!domain)
2652                 domain = mono_domain_get ();
2653
2654         pdata.code = code;
2655         pdata.target = target;
2656         pdata.absolute = absolute;
2657         pdata.found = 0;
2658
2659         mono_domain_lock (domain);
2660         mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
2661
2662         if (!pdata.found) {
2663                 /* this uses the first available slot */
2664                 pdata.found = 2;
2665                 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
2666         }
2667         mono_domain_unlock (domain);
2668
2669         if (pdata.found != 1)
2670                 g_print ("thunk failed for %p from %p\n", target, code);
2671         g_assert (pdata.found == 1);
2672 }
2673
2674 static void
2675 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target)
2676 {
2677         guint32 *code32 = (void*)code;
2678         guint32 ins = *code32;
2679         guint32 prim = (ins >> 25) & 7;
2680         guint32 tval = GPOINTER_TO_UINT (target);
2681
2682         //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
2683         if (prim == 5) { /* 101b */
2684                 /* the diff starts 8 bytes from the branch opcode */
2685                 gint diff = target - code - 8;
2686                 gint tbits;
2687                 gint tmask = 0xffffffff;
2688                 if (tval & 1) { /* entering thumb mode */
2689                         diff = target - 1 - code - 8;
2690                         g_assert (thumb_supported);
2691                         tbits = 0xf << 28; /* bl->blx bit pattern */
2692                         g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
2693                         /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
2694                         if (diff & 2) {
2695                                 tbits |= 1 << 24;
2696                         }
2697                         tmask = ~(1 << 24); /* clear the link bit */
2698                         /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
2699                 } else {
2700                         tbits = 0;
2701                 }
2702                 if (diff >= 0) {
2703                         if (diff <= 33554431) {
2704                                 diff >>= 2;
2705                                 ins = (ins & 0xff000000) | diff;
2706                                 ins &= tmask;
2707                                 *code32 = ins | tbits;
2708                                 return;
2709                         }
2710                 } else {
2711                         /* diff between 0 and -33554432 */
2712                         if (diff >= -33554432) {
2713                                 diff >>= 2;
2714                                 ins = (ins & 0xff000000) | (diff & ~0xff000000);
2715                                 ins &= tmask;
2716                                 *code32 = ins | tbits;
2717                                 return;
2718                         }
2719                 }
2720
2721                 handle_thunk (domain, TRUE, code, target);
2722                 return;
2723         }
2724
2725         /*
2726          * The alternative call sequences looks like this:
2727          *
2728          *      ldr ip, [pc] // loads the address constant
2729          *      b 1f         // jumps around the constant
2730          *      address constant embedded in the code
2731          *   1f:
2732          *      mov lr, pc
2733          *      mov pc, ip
2734          *
2735          * There are two cases for patching:
2736          * a) at the end of method emission: in this case code points to the start
2737          *    of the call sequence
2738          * b) during runtime patching of the call site: in this case code points
2739          *    to the mov pc, ip instruction
2740          *
2741          * We have to handle also the thunk jump code sequence:
2742          *
2743          *      ldr ip, [pc]
2744          *      mov pc, ip
2745          *      address constant // execution never reaches here
2746          */
2747         if ((ins & 0x0ffffff0) == 0x12fff10) {
2748                 /* Branch and exchange: the address is constructed in a reg
2749                  * We can patch BX when the code sequence is the following:
2750                  *  ldr     ip, [pc, #0]    ; 0x8
2751                  *  b       0xc
2752                  *  .word code_ptr
2753                  *  mov     lr, pc
2754                  *  bx      ips
2755                  * */
2756                 guint32 ccode [4];
2757                 guint8 *emit = (guint8*)ccode;
2758                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
2759                 ARM_B (emit, 0);
2760                 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
2761                 ARM_BX (emit, ARMREG_IP);
2762
2763                 /*patching from magic trampoline*/
2764                 if (ins == ccode [3]) {
2765                         g_assert (code32 [-4] == ccode [0]);
2766                         g_assert (code32 [-3] == ccode [1]);
2767                         g_assert (code32 [-1] == ccode [2]);
2768                         code32 [-2] = (guint32)target;
2769                         return;
2770                 }
2771                 /*patching from JIT*/
2772                 if (ins == ccode [0]) {
2773                         g_assert (code32 [1] == ccode [1]);
2774                         g_assert (code32 [3] == ccode [2]);
2775                         g_assert (code32 [4] == ccode [3]);
2776                         code32 [2] = (guint32)target;
2777                         return;
2778                 }
2779                 g_assert_not_reached ();
2780         } else if ((ins & 0x0ffffff0) == 0x12fff30) {
2781                 /*
2782                  * ldr ip, [pc, #0]
2783                  * b 0xc
2784                  * .word code_ptr
2785                  * blx ip
2786                  */
2787                 guint32 ccode [4];
2788                 guint8 *emit = (guint8*)ccode;
2789                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
2790                 ARM_B (emit, 0);
2791                 ARM_BLX_REG (emit, ARMREG_IP);
2792
2793                 g_assert (code32 [-3] == ccode [0]);
2794                 g_assert (code32 [-2] == ccode [1]);
2795                 g_assert (code32 [0] == ccode [2]);
2796
2797                 code32 [-1] = (guint32)target;
2798         } else {
2799                 guint32 ccode [4];
2800                 guint32 *tmp = ccode;
2801                 guint8 *emit = (guint8*)tmp;
2802                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
2803                 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
2804                 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
2805                 ARM_BX (emit, ARMREG_IP);
2806                 if (ins == ccode [2]) {
2807                         g_assert_not_reached (); // should be -2 ...
2808                         code32 [-1] = (guint32)target;
2809                         return;
2810                 }
2811                 if (ins == ccode [0]) {
2812                         /* handles both thunk jump code and the far call sequence */
2813                         code32 [2] = (guint32)target;
2814                         return;
2815                 }
2816                 g_assert_not_reached ();
2817         }
2818 //      g_print ("patched with 0x%08x\n", ins);
2819 }
2820
2821 void
2822 arm_patch (guchar *code, const guchar *target)
2823 {
2824         arm_patch_general (NULL, code, target);
2825 }
2826
2827 /*
2828  * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
2829  * (with the rotation amount in *rot_amount. rot_amount is already adjusted
2830  * to be used with the emit macros.
2831  * Return -1 otherwise.
2832  */
2833 int
2834 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
2835 {
2836         guint32 res, i;
2837         for (i = 0; i < 31; i+= 2) {
2838                 res = (val << (32 - i)) | (val >> i);
2839                 if (res & ~0xff)
2840                         continue;
2841                 *rot_amount = i? 32 - i: 0;
2842                 return res;
2843         }
2844         return -1;
2845 }
2846
2847 /*
2848  * Emits in code a sequence of instructions that load the value 'val'
2849  * into the dreg register. Uses at most 4 instructions.
2850  */
2851 guint8*
2852 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
2853 {
2854         int imm8, rot_amount;
2855 #if 0
2856         ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
2857         /* skip the constant pool */
2858         ARM_B (code, 0);
2859         *(int*)code = val;
2860         code += 4;
2861         return code;
2862 #endif
2863         if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
2864                 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
2865         } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
2866                 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
2867         } else {
2868                 if (v7_supported) {
2869                         ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
2870                         if (val >> 16)
2871                                 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
2872                         return code;
2873                 }
2874                 if (val & 0xFF) {
2875                         ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
2876                         if (val & 0xFF00) {
2877                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
2878                         }
2879                         if (val & 0xFF0000) {
2880                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
2881                         }
2882                         if (val & 0xFF000000) {
2883                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
2884                         }
2885                 } else if (val & 0xFF00) {
2886                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
2887                         if (val & 0xFF0000) {
2888                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
2889                         }
2890                         if (val & 0xFF000000) {
2891                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
2892                         }
2893                 } else if (val & 0xFF0000) {
2894                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
2895                         if (val & 0xFF000000) {
2896                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
2897                         }
2898                 }
2899                 //g_assert_not_reached ();
2900         }
2901         return code;
2902 }
2903
2904 gboolean
2905 mono_arm_thumb_supported (void)
2906 {
2907         return thumb_supported;
2908 }
2909
2910 #ifndef DISABLE_JIT
2911
2912 /*
2913  * emit_load_volatile_arguments:
2914  *
2915  *  Load volatile arguments from the stack to the original input registers.
2916  * Required before a tail call.
2917  */
2918 static guint8*
2919 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2920 {
2921         MonoMethod *method = cfg->method;
2922         MonoMethodSignature *sig;
2923         MonoInst *inst;
2924         CallInfo *cinfo;
2925         guint32 i, pos;
2926
2927         /* FIXME: Generate intermediate code instead */
2928
2929         sig = mono_method_signature (method);
2930
2931         /* This is the opposite of the code in emit_prolog */
2932
2933         pos = 0;
2934
2935         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig, sig->pinvoke);
2936
2937         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
2938                 ArgInfo *ainfo = &cinfo->ret;
2939                 inst = cfg->vret_addr;
2940                 g_assert (arm_is_imm12 (inst->inst_offset));
2941                 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2942         }
2943         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2944                 ArgInfo *ainfo = cinfo->args + i;
2945                 inst = cfg->args [pos];
2946
2947                 if (cfg->verbose_level > 2)
2948                         g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
2949                 if (inst->opcode == OP_REGVAR) {
2950                         if (ainfo->storage == RegTypeGeneral)
2951                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
2952                         else if (ainfo->storage == RegTypeFP) {
2953                                 g_assert_not_reached ();
2954                         } else if (ainfo->storage == RegTypeBase) {
2955                                 // FIXME:
2956                                 NOT_IMPLEMENTED;
2957                                 /*
2958                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
2959                                         ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2960                                 } else {
2961                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
2962                                         ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
2963                                 }
2964                                 */
2965                         } else
2966                                 g_assert_not_reached ();
2967                 } else {
2968                         if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
2969                                 switch (ainfo->size) {
2970                                 case 1:
2971                                 case 2:
2972                                         // FIXME:
2973                                         NOT_IMPLEMENTED;
2974                                         break;
2975                                 case 8:
2976                                         g_assert (arm_is_imm12 (inst->inst_offset));
2977                                         ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2978                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
2979                                         ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
2980                                         break;
2981                                 default:
2982                                         if (arm_is_imm12 (inst->inst_offset)) {
2983                                                 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2984                                         } else {
2985                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
2986                                                 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
2987                                         }
2988                                         break;
2989                                 }
2990                         } else if (ainfo->storage == RegTypeBaseGen) {
2991                                 // FIXME:
2992                                 NOT_IMPLEMENTED;
2993                         } else if (ainfo->storage == RegTypeBase) {
2994                                 /* Nothing to do */
2995                         } else if (ainfo->storage == RegTypeFP) {
2996                                 g_assert_not_reached ();
2997                         } else if (ainfo->storage == RegTypeStructByVal) {
2998                                 int doffset = inst->inst_offset;
2999                                 int soffset = 0;
3000                                 int cur_reg;
3001                                 int size = 0;
3002                                 if (mono_class_from_mono_type (inst->inst_vtype))
3003                                         size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3004                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3005                                         if (arm_is_imm12 (doffset)) {
3006                                                 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3007                                         } else {
3008                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3009                                                 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3010                                         }
3011                                         soffset += sizeof (gpointer);
3012                                         doffset += sizeof (gpointer);
3013                                 }
3014                                 if (ainfo->vtsize)
3015                                         // FIXME:
3016                                         NOT_IMPLEMENTED;
3017                         } else if (ainfo->storage == RegTypeStructByAddr) {
3018                         } else {
3019                                 // FIXME:
3020                                 NOT_IMPLEMENTED;
3021                         }
3022                 }
3023                 pos ++;
3024         }
3025
3026         g_free (cinfo);
3027
3028         return code;
3029 }
3030
3031 void
3032 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3033 {
3034         MonoInst *ins;
3035         MonoCallInst *call;
3036         guint offset;
3037         guint8 *code = cfg->native_code + cfg->code_len;
3038         MonoInst *last_ins = NULL;
3039         guint last_offset = 0;
3040         int max_len, cpos;
3041         int imm8, rot_amount;
3042
3043         /* we don't align basic blocks of loops on arm */
3044
3045         if (cfg->verbose_level > 2)
3046                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3047
3048         cpos = bb->max_offset;
3049
3050         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3051                 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3052                 //g_assert (!mono_compile_aot);
3053                 //cpos += 6;
3054                 //if (bb->cil_code)
3055                 //      cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3056                 /* this is not thread save, but good enough */
3057                 /* fixme: howto handle overflows? */
3058                 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3059         }
3060
3061     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3062                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3063                                                          (gpointer)"mono_break");
3064                 code = emit_call_seq (cfg, code);
3065         }
3066
3067         MONO_BB_FOR_EACH_INS (bb, ins) {
3068                 offset = code - cfg->native_code;
3069
3070                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3071
3072                 if (offset > (cfg->code_size - max_len - 16)) {
3073                         cfg->code_size *= 2;
3074                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3075                         code = cfg->native_code + offset;
3076                 }
3077         //      if (ins->cil_code)
3078         //              g_print ("cil code\n");
3079                 mono_debug_record_line_number (cfg, ins, offset);
3080
3081                 switch (ins->opcode) {
3082                 case OP_MEMORY_BARRIER:
3083                         break;
3084                 case OP_TLS_GET:
3085 #ifdef HAVE_AEABI_READ_TP
3086                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3087                                                                  (gpointer)"__aeabi_read_tp");
3088                         code = emit_call_seq (cfg, code);
3089
3090                         ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3091 #else
3092                         g_assert_not_reached ();
3093 #endif
3094                         break;
3095                 /*case OP_BIGMUL:
3096                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3097                         ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3098                         break;
3099                 case OP_BIGMUL_UN:
3100                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3101                         ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3102                         break;*/
3103                 case OP_STOREI1_MEMBASE_IMM:
3104                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3105                         g_assert (arm_is_imm12 (ins->inst_offset));
3106                         ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3107                         break;
3108                 case OP_STOREI2_MEMBASE_IMM:
3109                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3110                         g_assert (arm_is_imm8 (ins->inst_offset));
3111                         ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3112                         break;
3113                 case OP_STORE_MEMBASE_IMM:
3114                 case OP_STOREI4_MEMBASE_IMM:
3115                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3116                         g_assert (arm_is_imm12 (ins->inst_offset));
3117                         ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3118                         break;
3119                 case OP_STOREI1_MEMBASE_REG:
3120                         g_assert (arm_is_imm12 (ins->inst_offset));
3121                         ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3122                         break;
3123                 case OP_STOREI2_MEMBASE_REG:
3124                         g_assert (arm_is_imm8 (ins->inst_offset));
3125                         ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3126                         break;
3127                 case OP_STORE_MEMBASE_REG:
3128                 case OP_STOREI4_MEMBASE_REG:
3129                         /* this case is special, since it happens for spill code after lowering has been called */
3130                         if (arm_is_imm12 (ins->inst_offset)) {
3131                                 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3132                         } else {
3133                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3134                                 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3135                         }
3136                         break;
3137                 case OP_STOREI1_MEMINDEX:
3138                         ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3139                         break;
3140                 case OP_STOREI2_MEMINDEX:
3141                         ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3142                         break;
3143                 case OP_STORE_MEMINDEX:
3144                 case OP_STOREI4_MEMINDEX:
3145                         ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3146                         break;
3147                 case OP_LOADU4_MEM:
3148                         g_assert_not_reached ();
3149                         break;
3150                 case OP_LOAD_MEMINDEX:
3151                 case OP_LOADI4_MEMINDEX:
3152                 case OP_LOADU4_MEMINDEX:
3153                         ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3154                         break;
3155                 case OP_LOADI1_MEMINDEX:
3156                         ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3157                         break;
3158                 case OP_LOADU1_MEMINDEX:
3159                         ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3160                         break;
3161                 case OP_LOADI2_MEMINDEX:
3162                         ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3163                         break;
3164                 case OP_LOADU2_MEMINDEX:
3165                         ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3166                         break;
3167                 case OP_LOAD_MEMBASE:
3168                 case OP_LOADI4_MEMBASE:
3169                 case OP_LOADU4_MEMBASE:
3170                         /* this case is special, since it happens for spill code after lowering has been called */
3171                         if (arm_is_imm12 (ins->inst_offset)) {
3172                                 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3173                         } else {
3174                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3175                                 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3176                         }
3177                         break;
3178                 case OP_LOADI1_MEMBASE:
3179                         g_assert (arm_is_imm8 (ins->inst_offset));
3180                         ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3181                         break;
3182                 case OP_LOADU1_MEMBASE:
3183                         g_assert (arm_is_imm12 (ins->inst_offset));
3184                         ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3185                         break;
3186                 case OP_LOADU2_MEMBASE:
3187                         g_assert (arm_is_imm8 (ins->inst_offset));
3188                         ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3189                         break;
3190                 case OP_LOADI2_MEMBASE:
3191                         g_assert (arm_is_imm8 (ins->inst_offset));
3192                         ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3193                         break;
3194                 case OP_ICONV_TO_I1:
3195                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3196                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3197                         break;
3198                 case OP_ICONV_TO_I2:
3199                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3200                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3201                         break;
3202                 case OP_ICONV_TO_U1:
3203                         ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3204                         break;
3205                 case OP_ICONV_TO_U2:
3206                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3207                         ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3208                         break;
3209                 case OP_COMPARE:
3210                 case OP_ICOMPARE:
3211                         ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3212                         break;
3213                 case OP_COMPARE_IMM:
3214                 case OP_ICOMPARE_IMM:
3215                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3216                         g_assert (imm8 >= 0);
3217                         ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3218                         break;
3219                 case OP_BREAK:
3220                         /*
3221                          * gdb does not like encountering the hw breakpoint ins in the debugged code.
3222                          * So instead of emitting a trap, we emit a call a C function and place a
3223                          * breakpoint there.
3224                          */
3225                         //*(int*)code = 0xef9f0001;
3226                         //code += 4;
3227                         //ARM_DBRK (code);
3228                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3229                                                                  (gpointer)"mono_break");
3230                         code = emit_call_seq (cfg, code);
3231                         break;
3232                 case OP_RELAXED_NOP:
3233                         ARM_NOP (code);
3234                         break;
3235                 case OP_NOP:
3236                 case OP_DUMMY_USE:
3237                 case OP_DUMMY_STORE:
3238                 case OP_NOT_REACHED:
3239                 case OP_NOT_NULL:
3240                         break;
3241                 case OP_SEQ_POINT: {
3242                         int i;
3243                         MonoInst *info_var = cfg->arch.seq_point_info_var;
3244                         MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3245                         MonoInst *var;
3246                         int dreg = ARMREG_LR;
3247
3248                         /*
3249                          * For AOT, we use one got slot per method, which will point to a
3250                          * SeqPointInfo structure, containing all the information required
3251                          * by the code below.
3252                          */
3253                         if (cfg->compile_aot) {
3254                                 g_assert (info_var);
3255                                 g_assert (info_var->opcode == OP_REGOFFSET);
3256                                 g_assert (arm_is_imm12 (info_var->inst_offset));
3257                         }
3258
3259                         /*
3260                          * Read from the single stepping trigger page. This will cause a
3261                          * SIGSEGV when single stepping is enabled.
3262                          * We do this _before_ the breakpoint, so single stepping after
3263                          * a breakpoint is hit will step to the next IL offset.
3264                          */
3265                         g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3266
3267                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3268                                 if (cfg->compile_aot) {
3269                                         /* Load the trigger page addr from the variable initialized in the prolog */
3270                                         var = ss_trigger_page_var;
3271                                         g_assert (var);
3272                                         g_assert (var->opcode == OP_REGOFFSET);
3273                                         g_assert (arm_is_imm12 (var->inst_offset));
3274                                         ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3275                                 } else {
3276                                         ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3277                                         ARM_B (code, 0);
3278                                         *(int*)code = (int)ss_trigger_page;
3279                                         code += 4;
3280                                 }
3281                                 ARM_LDR_IMM (code, dreg, dreg, 0);
3282                         }
3283
3284                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3285
3286                         if (cfg->compile_aot) {
3287                                 guint32 offset = code - cfg->native_code;
3288                                 guint32 val;
3289
3290                                 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3291                                 /* Add the offset */
3292                                 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3293                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3294                                 /*
3295                                  * Have to emit nops to keep the difference between the offset
3296                                  * stored in seq_points and breakpoint instruction constant,
3297                                  * mono_arch_get_ip_for_breakpoint () depends on this.
3298                                  */
3299                                 if (val & 0xFF00)
3300                                         ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3301                                 else
3302                                         ARM_NOP (code);
3303                                 if (val & 0xFF0000)
3304                                         ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3305                                 else
3306                                         ARM_NOP (code);
3307                                 g_assert (!(val & 0xFF000000));
3308                                 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3309                                 ARM_LDR_IMM (code, dreg, dreg, 0);
3310
3311                                 /* What is faster, a branch or a load ? */
3312                                 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3313                                 /* The breakpoint instruction */
3314                                 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3315                         } else {
3316                                 /*
3317                                  * A placeholder for a possible breakpoint inserted by
3318                                  * mono_arch_set_breakpoint ().
3319                                  */
3320                                 for (i = 0; i < 4; ++i)
3321                                         ARM_NOP (code);
3322                         }
3323                         break;
3324                 }
3325                 case OP_ADDCC:
3326                 case OP_IADDCC:
3327                         ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3328                         break;
3329                 case OP_IADD:
3330                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3331                         break;
3332                 case OP_ADC:
3333                 case OP_IADC:
3334                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3335                         break;
3336                 case OP_ADDCC_IMM:
3337                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3338                         g_assert (imm8 >= 0);
3339                         ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3340                         break;
3341                 case OP_ADD_IMM:
3342                 case OP_IADD_IMM:
3343                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3344                         g_assert (imm8 >= 0);
3345                         ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3346                         break;
3347                 case OP_ADC_IMM:
3348                 case OP_IADC_IMM:
3349                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3350                         g_assert (imm8 >= 0);
3351                         ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3352                         break;
3353                 case OP_IADD_OVF:
3354                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3355                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3356                         break;
3357                 case OP_IADD_OVF_UN:
3358                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3359                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3360                         break;
3361                 case OP_ISUB_OVF:
3362                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3363                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3364                         break;
3365                 case OP_ISUB_OVF_UN:
3366                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3367                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3368                         break;
3369                 case OP_ADD_OVF_CARRY:
3370                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3371                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3372                         break;
3373                 case OP_ADD_OVF_UN_CARRY:
3374                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3375                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3376                         break;
3377                 case OP_SUB_OVF_CARRY:
3378                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3379                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3380                         break;
3381                 case OP_SUB_OVF_UN_CARRY:
3382                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3383                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3384                         break;
3385                 case OP_SUBCC:
3386                 case OP_ISUBCC:
3387                         ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3388                         break;
3389                 case OP_SUBCC_IMM:
3390                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3391                         g_assert (imm8 >= 0);
3392                         ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3393                         break;
3394                 case OP_ISUB:
3395                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3396                         break;
3397                 case OP_SBB:
3398                 case OP_ISBB:
3399                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3400                         break;
3401                 case OP_SUB_IMM:
3402                 case OP_ISUB_IMM:
3403                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3404                         g_assert (imm8 >= 0);
3405                         ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3406                         break;
3407                 case OP_SBB_IMM:
3408                 case OP_ISBB_IMM:
3409                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3410                         g_assert (imm8 >= 0);
3411                         ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3412                         break;
3413                 case OP_ARM_RSBS_IMM:
3414                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3415                         g_assert (imm8 >= 0);
3416                         ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3417                         break;
3418                 case OP_ARM_RSC_IMM:
3419                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3420                         g_assert (imm8 >= 0);
3421                         ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3422                         break;
3423                 case OP_IAND:
3424                         ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3425                         break;
3426                 case OP_AND_IMM:
3427                 case OP_IAND_IMM:
3428                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3429                         g_assert (imm8 >= 0);
3430                         ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3431                         break;
3432                 case OP_IDIV:
3433                 case OP_IDIV_UN:
3434                 case OP_DIV_IMM:
3435                 case OP_IREM:
3436                 case OP_IREM_UN:
3437                 case OP_REM_IMM:
3438                         /* crappy ARM arch doesn't have a DIV instruction */
3439                         g_assert_not_reached ();
3440                 case OP_IOR:
3441                         ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3442                         break;
3443                 case OP_OR_IMM:
3444                 case OP_IOR_IMM:
3445                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3446                         g_assert (imm8 >= 0);
3447                         ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3448                         break;
3449                 case OP_IXOR:
3450                         ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3451                         break;
3452                 case OP_XOR_IMM:
3453                 case OP_IXOR_IMM:
3454                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3455                         g_assert (imm8 >= 0);
3456                         ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3457                         break;
3458                 case OP_ISHL:
3459                         ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3460                         break;
3461                 case OP_SHL_IMM:
3462                 case OP_ISHL_IMM:
3463                         if (ins->inst_imm)
3464                                 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3465                         else if (ins->dreg != ins->sreg1)
3466                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3467                         break;
3468                 case OP_ISHR:
3469                         ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3470                         break;
3471                 case OP_SHR_IMM:
3472                 case OP_ISHR_IMM:
3473                         if (ins->inst_imm)
3474                                 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3475                         else if (ins->dreg != ins->sreg1)
3476                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3477                         break;
3478                 case OP_SHR_UN_IMM:
3479                 case OP_ISHR_UN_IMM:
3480                         if (ins->inst_imm)
3481                                 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3482                         else if (ins->dreg != ins->sreg1)
3483                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3484                         break;
3485                 case OP_ISHR_UN:
3486                         ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3487                         break;
3488                 case OP_INOT:
3489                         ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
3490                         break;
3491                 case OP_INEG:
3492                         ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
3493                         break;
3494                 case OP_IMUL:
3495                         if (ins->dreg == ins->sreg2)
3496                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3497                         else
3498                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
3499                         break;
3500                 case OP_MUL_IMM:
3501                         g_assert_not_reached ();
3502                         break;
3503                 case OP_IMUL_OVF:
3504                         /* FIXME: handle ovf/ sreg2 != dreg */
3505                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3506                         /* FIXME: MUL doesn't set the C/O flags on ARM */
3507                         break;
3508                 case OP_IMUL_OVF_UN:
3509                         /* FIXME: handle ovf/ sreg2 != dreg */
3510                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3511                         /* FIXME: MUL doesn't set the C/O flags on ARM */
3512                         break;
3513                 case OP_ICONST:
3514                         code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
3515                         break;
3516                 case OP_AOTCONST:
3517                         /* Load the GOT offset */
3518                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3519                         ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
3520                         ARM_B (code, 0);
3521                         *(gpointer*)code = NULL;
3522                         code += 4;
3523                         /* Load the value from the GOT */
3524                         ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
3525                         break;
3526                 case OP_ICONV_TO_I4:
3527                 case OP_ICONV_TO_U4:
3528                 case OP_MOVE:
3529                         if (ins->dreg != ins->sreg1)
3530                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3531                         break;
3532                 case OP_SETLRET: {
3533                         int saved = ins->sreg2;
3534                         if (ins->sreg2 == ARM_LSW_REG) {
3535                                 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
3536                                 saved = ARMREG_LR;
3537                         }
3538                         if (ins->sreg1 != ARM_LSW_REG)
3539                                 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
3540                         if (saved != ARM_MSW_REG)
3541                                 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
3542                         break;
3543                 }
3544                 case OP_FMOVE:
3545 #ifdef ARM_FPU_FPA
3546                         ARM_MVFD (code, ins->dreg, ins->sreg1);
3547 #elif defined(ARM_FPU_VFP)
3548                         ARM_CPYD (code, ins->dreg, ins->sreg1);
3549 #endif
3550                         break;
3551                 case OP_FCONV_TO_R4:
3552 #ifdef ARM_FPU_FPA
3553                         ARM_MVFS (code, ins->dreg, ins->sreg1);
3554 #elif defined(ARM_FPU_VFP)
3555                         ARM_CVTD (code, ins->dreg, ins->sreg1);
3556                         ARM_CVTS (code, ins->dreg, ins->dreg);
3557 #endif
3558                         break;
3559                 case OP_JMP:
3560                         /*
3561                          * Keep in sync with mono_arch_emit_epilog
3562                          */
3563                         g_assert (!cfg->method->save_lmf);
3564
3565                         code = emit_load_volatile_arguments (cfg, code);
3566
3567                         code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
3568                         ARM_POP_NWB (code, cfg->used_int_regs | ((1 << ARMREG_SP)) | ((1 << ARMREG_LR)));
3569                         mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3570                         if (cfg->compile_aot) {
3571                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3572                                 ARM_B (code, 0);
3573                                 *(gpointer*)code = NULL;
3574                                 code += 4;
3575                                 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
3576                         } else {
3577                                 ARM_B (code, 0);
3578                         }
3579                         break;
3580                 case OP_CHECK_THIS:
3581                         /* ensure ins->sreg1 is not NULL */
3582                         ARM_LDR_IMM (code, ARMREG_LR, ins->sreg1, 0);
3583                         break;
3584                 case OP_ARGLIST: {
3585                         g_assert (cfg->sig_cookie < 128);
3586                         ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
3587                         ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
3588                         break;
3589                 }
3590                 case OP_FCALL:
3591                 case OP_LCALL:
3592                 case OP_VCALL:
3593                 case OP_VCALL2:
3594                 case OP_VOIDCALL:
3595                 case OP_CALL:
3596                         call = (MonoCallInst*)ins;
3597                         if (ins->flags & MONO_INST_HAS_METHOD)
3598                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
3599                         else
3600                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
3601                         code = emit_call_seq (cfg, code);
3602                         code = emit_move_return_value (cfg, ins, code);
3603                         break;
3604                 case OP_FCALL_REG:
3605                 case OP_LCALL_REG:
3606                 case OP_VCALL_REG:
3607                 case OP_VCALL2_REG:
3608                 case OP_VOIDCALL_REG:
3609                 case OP_CALL_REG:
3610                         code = emit_call_reg (code, ins->sreg1);
3611                         code = emit_move_return_value (cfg, ins, code);
3612                         break;
3613                 case OP_FCALL_MEMBASE:
3614                 case OP_LCALL_MEMBASE:
3615                 case OP_VCALL_MEMBASE:
3616                 case OP_VCALL2_MEMBASE:
3617                 case OP_VOIDCALL_MEMBASE:
3618                 case OP_CALL_MEMBASE:
3619                         g_assert (arm_is_imm12 (ins->inst_offset));
3620                         g_assert (ins->sreg1 != ARMREG_LR);
3621                         call = (MonoCallInst*)ins;
3622                         if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE) {
3623                                 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
3624                                 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
3625                                 /*
3626                                  * We can't embed the method in the code stream in PIC code, or
3627                                  * in gshared code.
3628                                  * Instead, we put it in V5 in code emitted by
3629                                  * mono_arch_emit_imt_argument (), and embed NULL here to
3630                                  * signal the IMT thunk that the value is in V5.
3631                                  */
3632                                 if (call->dynamic_imt_arg)
3633                                         *((gpointer*)code) = NULL;
3634                                 else
3635                                         *((gpointer*)code) = (gpointer)call->method;
3636                                 code += 4;
3637                         } else {
3638                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
3639                                 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
3640                         }
3641                         code = emit_move_return_value (cfg, ins, code);
3642                         break;
3643                 case OP_LOCALLOC: {
3644                         /* keep alignment */
3645                         int alloca_waste = cfg->param_area;
3646                         alloca_waste += 7;
3647                         alloca_waste &= ~7;
3648                         /* round the size to 8 bytes */
3649                         ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
3650                         ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
3651                         if (alloca_waste)
3652                                 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
3653                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
3654                         /* memzero the area: dreg holds the size, sp is the pointer */
3655                         if (ins->flags & MONO_INST_INIT) {
3656                                 guint8 *start_loop, *branch_to_cond;
3657                                 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
3658                                 branch_to_cond = code;
3659                                 ARM_B (code, 0);
3660                                 start_loop = code;
3661                                 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
3662                                 arm_patch (branch_to_cond, code);
3663                                 /* decrement by 4 and set flags */
3664                                 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, 4);
3665                                 ARM_B_COND (code, ARMCOND_GE, 0);
3666                                 arm_patch (code - 4, start_loop);
3667                         }
3668                         ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
3669                         break;
3670                 }
3671                 case OP_DYN_CALL: {
3672                         int i;
3673                         MonoInst *var = cfg->dyn_call_var;
3674
3675                         g_assert (var->opcode == OP_REGOFFSET);
3676                         g_assert (arm_is_imm12 (var->inst_offset));
3677
3678                         /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
3679                         ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
3680                         /* ip = ftn */
3681                         ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
3682
3683                         /* Save args buffer */
3684                         ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
3685
3686                         /* Set stack slots using R0 as scratch reg */
3687                         /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
3688                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
3689                                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (gpointer));
3690                                 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (gpointer));
3691                         }
3692
3693                         /* Set argument registers */
3694                         for (i = 0; i < PARAM_REGS; ++i)
3695                                 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (gpointer));
3696
3697                         /* Make the call */
3698                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
3699                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3700
3701                         /* Save result */
3702                         ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
3703                         ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
3704                         ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
3705                         break;
3706                 }
3707                 case OP_THROW: {
3708                         if (ins->sreg1 != ARMREG_R0)
3709                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
3710                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3711                                              (gpointer)"mono_arch_throw_exception");
3712                         code = emit_call_seq (cfg, code);
3713                         break;
3714                 }
3715                 case OP_RETHROW: {
3716                         if (ins->sreg1 != ARMREG_R0)
3717                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
3718                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3719                                              (gpointer)"mono_arch_rethrow_exception");
3720                         code = emit_call_seq (cfg, code);
3721                         break;
3722                 }
3723                 case OP_START_HANDLER: {
3724                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3725
3726                         if (arm_is_imm12 (spvar->inst_offset)) {
3727                                 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
3728                         } else {
3729                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
3730                                 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
3731                         }
3732                         break;
3733                 }
3734                 case OP_ENDFILTER: {
3735                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3736
3737                         if (ins->sreg1 != ARMREG_R0)
3738                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
3739                         if (arm_is_imm12 (spvar->inst_offset)) {
3740                                 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
3741                         } else {
3742                                 g_assert (ARMREG_IP != spvar->inst_basereg);
3743                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
3744                                 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
3745                         }
3746                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3747                         break;
3748                 }
3749                 case OP_ENDFINALLY: {
3750                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3751
3752                         if (arm_is_imm12 (spvar->inst_offset)) {
3753                                 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
3754                         } else {
3755                                 g_assert (ARMREG_IP != spvar->inst_basereg);
3756                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
3757                                 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
3758                         }
3759                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3760                         break;
3761                 }
3762                 case OP_CALL_HANDLER:
3763                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3764                         ARM_BL (code, 0);
3765                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3766                         break;
3767                 case OP_LABEL:
3768                         ins->inst_c0 = code - cfg->native_code;
3769                         break;
3770                 case OP_BR:
3771                         /*if (ins->inst_target_bb->native_offset) {
3772                                 ARM_B (code, 0);
3773                                 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3774                         } else*/ {
3775                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3776                                 ARM_B (code, 0);
3777                         }
3778                         break;
3779                 case OP_BR_REG:
3780                         ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
3781                         break;
3782                 case OP_SWITCH:
3783                         /*
3784                          * In the normal case we have:
3785                          *      ldr pc, [pc, ins->sreg1 << 2]
3786                          *      nop
3787                          * If aot, we have:
3788                          *      ldr lr, [pc, ins->sreg1 << 2]
3789                          *      add pc, pc, lr
3790                          * After follows the data.
3791                          * FIXME: add aot support.
3792                          */
3793                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
3794                         max_len += 4 * GPOINTER_TO_INT (ins->klass);
3795                         if (offset + max_len > (cfg->code_size - 16)) {
3796                                 cfg->code_size += max_len;
3797                                 cfg->code_size *= 2;
3798                                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3799                                 code = cfg->native_code + offset;
3800                         }
3801                         ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
3802                         ARM_NOP (code);
3803                         code += 4 * GPOINTER_TO_INT (ins->klass);
3804                         break;
3805                 case OP_CEQ:
3806                 case OP_ICEQ:
3807                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
3808                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
3809                         break;
3810                 case OP_CLT:
3811                 case OP_ICLT:
3812                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
3813                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
3814                         break;
3815                 case OP_CLT_UN:
3816                 case OP_ICLT_UN:
3817                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
3818                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
3819                         break;
3820                 case OP_CGT:
3821                 case OP_ICGT:
3822                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
3823                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
3824                         break;
3825                 case OP_CGT_UN:
3826                 case OP_ICGT_UN:
3827                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
3828                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
3829                         break;
3830                 case OP_COND_EXC_EQ:
3831                 case OP_COND_EXC_NE_UN:
3832                 case OP_COND_EXC_LT:
3833                 case OP_COND_EXC_LT_UN:
3834                 case OP_COND_EXC_GT:
3835                 case OP_COND_EXC_GT_UN:
3836                 case OP_COND_EXC_GE:
3837                 case OP_COND_EXC_GE_UN:
3838                 case OP_COND_EXC_LE:
3839                 case OP_COND_EXC_LE_UN:
3840                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
3841                         break;
3842                 case OP_COND_EXC_IEQ:
3843                 case OP_COND_EXC_INE_UN:
3844                 case OP_COND_EXC_ILT:
3845                 case OP_COND_EXC_ILT_UN:
3846                 case OP_COND_EXC_IGT:
3847                 case OP_COND_EXC_IGT_UN:
3848                 case OP_COND_EXC_IGE:
3849                 case OP_COND_EXC_IGE_UN:
3850                 case OP_COND_EXC_ILE:
3851                 case OP_COND_EXC_ILE_UN:
3852                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
3853                         break;
3854                 case OP_COND_EXC_C:
3855                 case OP_COND_EXC_IC:
3856                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
3857                         break;
3858                 case OP_COND_EXC_OV:
3859                 case OP_COND_EXC_IOV:
3860                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
3861                         break;
3862                 case OP_COND_EXC_NC:
3863                 case OP_COND_EXC_INC:
3864                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
3865                         break;
3866                 case OP_COND_EXC_NO:
3867                 case OP_COND_EXC_INO:
3868                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
3869                         break;
3870                 case OP_IBEQ:
3871                 case OP_IBNE_UN:
3872                 case OP_IBLT:
3873                 case OP_IBLT_UN:
3874                 case OP_IBGT:
3875                 case OP_IBGT_UN:
3876                 case OP_IBGE:
3877                 case OP_IBGE_UN:
3878                 case OP_IBLE:
3879                 case OP_IBLE_UN:
3880                         EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
3881                         break;
3882
3883                 /* floating point opcodes */
3884 #ifdef ARM_FPU_FPA
3885                 case OP_R8CONST:
3886                         if (cfg->compile_aot) {
3887                                 ARM_LDFD (code, ins->dreg, ARMREG_PC, 0);
3888                                 ARM_B (code, 1);
3889                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
3890                                 code += 4;
3891                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
3892                                 code += 4;
3893                         } else {
3894                                 /* FIXME: we can optimize the imm load by dealing with part of
3895                                  * the displacement in LDFD (aligning to 512).
3896                                  */
3897                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
3898                                 ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
3899                         }
3900                         break;
3901                 case OP_R4CONST:
3902                         if (cfg->compile_aot) {
3903                                 ARM_LDFS (code, ins->dreg, ARMREG_PC, 0);
3904                                 ARM_B (code, 0);
3905                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
3906                                 code += 4;
3907                         } else {
3908                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
3909                                 ARM_LDFS (code, ins->dreg, ARMREG_LR, 0);
3910                         }
3911                         break;
3912                 case OP_STORER8_MEMBASE_REG:
3913                         /* This is generated by the local regalloc pass which runs after the lowering pass */
3914                         if (!arm_is_fpimm8 (ins->inst_offset)) {
3915                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3916                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
3917                                 ARM_STFD (code, ins->sreg1, ARMREG_LR, 0);
3918                         } else {
3919                                 ARM_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3920                         }
3921                         break;
3922                 case OP_LOADR8_MEMBASE:
3923                         /* This is generated by the local regalloc pass which runs after the lowering pass */
3924                         if (!arm_is_fpimm8 (ins->inst_offset)) {
3925                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3926                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
3927                                 ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
3928                         } else {
3929                                 ARM_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3930                         }
3931                         break;
3932                 case OP_STORER4_MEMBASE_REG:
3933                         g_assert (arm_is_fpimm8 (ins->inst_offset));
3934                         ARM_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3935                         break;
3936                 case OP_LOADR4_MEMBASE:
3937                         g_assert (arm_is_fpimm8 (ins->inst_offset));
3938                         ARM_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3939                         break;
3940                 case OP_ICONV_TO_R_UN: {
3941                         int tmpreg;
3942                         tmpreg = ins->dreg == 0? 1: 0;
3943                         ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
3944                         ARM_FLTD (code, ins->dreg, ins->sreg1);
3945                         ARM_B_COND (code, ARMCOND_GE, 8);
3946                         /* save the temp register */
3947                         ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
3948                         ARM_STFD (code, tmpreg, ARMREG_SP, 0);
3949                         ARM_LDFD (code, tmpreg, ARMREG_PC, 12);
3950                         ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
3951                         ARM_LDFD (code, tmpreg, ARMREG_SP, 0);
3952                         ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
3953                         /* skip the constant pool */
3954                         ARM_B (code, 8);
3955                         code += 4;
3956                         *(int*)code = 0x41f00000;
3957                         code += 4;
3958                         *(int*)code = 0;
3959                         code += 4;
3960                         /* FIXME: adjust:
3961                          * ldfltd  ftemp, [pc, #8] 0x41f00000 0x00000000
3962                          * adfltd  fdest, fdest, ftemp
3963                          */
3964                         break;
3965                 }
3966                 case OP_ICONV_TO_R4:
3967                         ARM_FLTS (code, ins->dreg, ins->sreg1);
3968                         break;
3969                 case OP_ICONV_TO_R8:
3970                         ARM_FLTD (code, ins->dreg, ins->sreg1);
3971                         break;
3972
3973 #elif defined(ARM_FPU_VFP)
3974
3975                 case OP_R8CONST:
3976                         if (cfg->compile_aot) {
3977                                 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
3978                                 ARM_B (code, 1);
3979                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
3980                                 code += 4;
3981                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
3982                                 code += 4;
3983                         } else {
3984                                 /* FIXME: we can optimize the imm load by dealing with part of
3985                                  * the displacement in LDFD (aligning to 512).
3986                                  */
3987                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
3988                                 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
3989                         }
3990                         break;
3991                 case OP_R4CONST:
3992                         if (cfg->compile_aot) {
3993                                 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
3994                                 ARM_B (code, 0);
3995                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
3996                                 code += 4;
3997                                 ARM_CVTS (code, ins->dreg, ins->dreg);
3998                         } else {
3999                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4000                                 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4001                                 ARM_CVTS (code, ins->dreg, ins->dreg);
4002                         }
4003                         break;
4004                 case OP_STORER8_MEMBASE_REG:
4005                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4006                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4007                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4008                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4009                                 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4010                         } else {
4011                                 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4012                         }
4013                         break;
4014                 case OP_LOADR8_MEMBASE:
4015                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4016                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4017                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4018                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4019                                 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4020                         } else {
4021                                 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4022                         }
4023                         break;
4024                 case OP_STORER4_MEMBASE_REG:
4025                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4026                         ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4027                         ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4028                         break;
4029                 case OP_LOADR4_MEMBASE:
4030                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4031                         ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4032                         ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4033                         break;
4034                 case OP_ICONV_TO_R_UN: {
4035                         g_assert_not_reached ();
4036                         break;
4037                 }
4038                 case OP_ICONV_TO_R4:
4039                         ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4040                         ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4041                         ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4042                         break;
4043                 case OP_ICONV_TO_R8:
4044                         ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4045                         ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4046                         break;
4047
4048                 case OP_SETFRET:
4049                         if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4050                                 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4051                                 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4052                         } else {
4053                                 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4054                         }
4055                         break;
4056
4057 #endif
4058
4059                 case OP_FCONV_TO_I1:
4060                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4061                         break;
4062                 case OP_FCONV_TO_U1:
4063                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4064                         break;
4065                 case OP_FCONV_TO_I2:
4066                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4067                         break;
4068                 case OP_FCONV_TO_U2:
4069                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4070                         break;
4071                 case OP_FCONV_TO_I4:
4072                 case OP_FCONV_TO_I:
4073                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4074                         break;
4075                 case OP_FCONV_TO_U4:
4076                 case OP_FCONV_TO_U:
4077                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4078                         break;
4079                 case OP_FCONV_TO_I8:
4080                 case OP_FCONV_TO_U8:
4081                         g_assert_not_reached ();
4082                         /* Implemented as helper calls */
4083                         break;
4084                 case OP_LCONV_TO_R_UN:
4085                         g_assert_not_reached ();
4086                         /* Implemented as helper calls */
4087                         break;
4088                 case OP_LCONV_TO_OVF_I4_2: {
4089                         guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4090                         /*
4091                          * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4092                          */
4093
4094                         ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4095                         high_bit_not_set = code;
4096                         ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4097
4098                         ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4099                         valid_negative = code;
4100                         ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4101                         invalid_negative = code;
4102                         ARM_B_COND (code, ARMCOND_AL, 0);
4103
4104                         arm_patch (high_bit_not_set, code);
4105
4106                         ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4107                         valid_positive = code;
4108                         ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4109
4110                         arm_patch (invalid_negative, code);
4111                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4112
4113                         arm_patch (valid_negative, code);
4114                         arm_patch (valid_positive, code);
4115
4116                         if (ins->dreg != ins->sreg1)
4117                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4118                         break;
4119                 }
4120 #ifdef ARM_FPU_FPA
4121                 case OP_FADD:
4122                         ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4123                         break;
4124                 case OP_FSUB:
4125                         ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4126                         break;
4127                 case OP_FMUL:
4128                         ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4129                         break;
4130                 case OP_FDIV:
4131                         ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4132                         break;
4133                 case OP_FNEG:
4134                         ARM_MNFD (code, ins->dreg, ins->sreg1);
4135                         break;
4136 #elif defined(ARM_FPU_VFP)
4137                 case OP_FADD:
4138                         ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4139                         break;
4140                 case OP_FSUB:
4141                         ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4142                         break;
4143                 case OP_FMUL:
4144                         ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4145                         break;
4146                 case OP_FDIV:
4147                         ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4148                         break;
4149                 case OP_FNEG:
4150                         ARM_NEGD (code, ins->dreg, ins->sreg1);
4151                         break;
4152 #endif
4153                 case OP_FREM:
4154                         /* emulated */
4155                         g_assert_not_reached ();
4156                         break;
4157                 case OP_FCOMPARE:
4158 #ifdef ARM_FPU_FPA
4159                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4160 #elif defined(ARM_FPU_VFP)
4161                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4162                         ARM_FMSTAT (code);
4163 #endif
4164                         break;
4165                 case OP_FCEQ:
4166 #ifdef ARM_FPU_FPA
4167                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4168 #elif defined(ARM_FPU_VFP)
4169                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4170                         ARM_FMSTAT (code);
4171 #endif
4172                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4173                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4174                         break;
4175                 case OP_FCLT:
4176 #ifdef ARM_FPU_FPA
4177                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4178 #elif defined(ARM_FPU_VFP)
4179                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4180                         ARM_FMSTAT (code);
4181 #endif
4182                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4183                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4184                         break;
4185                 case OP_FCLT_UN:
4186 #ifdef ARM_FPU_FPA
4187                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4188 #elif defined(ARM_FPU_VFP)
4189                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4190                         ARM_FMSTAT (code);
4191 #endif
4192                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4193                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4194                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4195                         break;
4196                 case OP_FCGT:
4197                         /* swapped */
4198 #ifdef ARM_FPU_FPA
4199                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4200 #elif defined(ARM_FPU_VFP)
4201                         ARM_CMPD (code, ins->sreg2, ins->sreg1);
4202                         ARM_FMSTAT (code);
4203 #endif
4204                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4205                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4206                         break;
4207                 case OP_FCGT_UN:
4208                         /* swapped */
4209 #ifdef ARM_FPU_FPA
4210                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4211 #elif defined(ARM_FPU_VFP)
4212                         ARM_CMPD (code, ins->sreg2, ins->sreg1);
4213                         ARM_FMSTAT (code);
4214 #endif
4215                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4216                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4217                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4218                         break;
4219                 /* ARM FPA flags table:
4220                  * N        Less than               ARMCOND_MI
4221                  * Z        Equal                   ARMCOND_EQ
4222                  * C        Greater Than or Equal   ARMCOND_CS
4223                  * V        Unordered               ARMCOND_VS
4224                  */
4225                 case OP_FBEQ:
4226                         EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4227                         break;
4228                 case OP_FBNE_UN:
4229                         EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4230                         break;
4231                 case OP_FBLT:
4232                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4233                         break;
4234                 case OP_FBLT_UN:
4235                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4236                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4237                         break;
4238                 case OP_FBGT:
4239                 case OP_FBGT_UN:
4240                 case OP_FBLE:
4241                 case OP_FBLE_UN:
4242                         g_assert_not_reached ();
4243                         break;
4244                 case OP_FBGE:
4245 #ifdef ARM_FPU_VFP
4246                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4247 #else
4248                         /* FPA requires EQ even thou the docs suggests that just CS is enough */
4249                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4250                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4251 #endif
4252                         break;
4253                 case OP_FBGE_UN:
4254                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4255                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4256                         break;
4257
4258                 case OP_CKFINITE: {
4259 #ifdef ARM_FPU_FPA
4260                         if (ins->dreg != ins->sreg1)
4261                                 ARM_MVFD (code, ins->dreg, ins->sreg1);
4262 #elif defined(ARM_FPU_VFP)
4263                         ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4264                         ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4265                         ARM_B (code, 1);
4266                         *(guint32*)code = 0xffffffff;
4267                         code += 4;
4268                         *(guint32*)code = 0x7fefffff;
4269                         code += 4;
4270                         ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4271                         ARM_FMSTAT (code);
4272                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4273                         ARM_CMPD (code, ins->sreg1, ins->sreg1);
4274                         ARM_FMSTAT (code);
4275                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4276
4277                         ARM_CPYD (code, ins->dreg, ins->sreg1);
4278 #endif
4279                         break;
4280                 }
4281                 default:
4282                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4283                         g_assert_not_reached ();
4284                 }
4285
4286                 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4287                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4288                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4289                         g_assert_not_reached ();
4290                 }
4291
4292                 cpos += max_len;
4293
4294                 last_ins = ins;
4295                 last_offset = offset;
4296         }
4297
4298         cfg->code_len = code - cfg->native_code;
4299 }
4300
4301 #endif /* DISABLE_JIT */
4302
4303 #ifdef HAVE_AEABI_READ_TP
4304 void __aeabi_read_tp (void);
4305 #endif
4306
4307 void
4308 mono_arch_register_lowlevel_calls (void)
4309 {
4310         /* The signature doesn't matter */
4311         mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4312         mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4313
4314 #ifndef MONO_CROSS_COMPILE
4315 #ifdef HAVE_AEABI_READ_TP
4316         mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4317 #endif
4318 #endif
4319 }
4320
4321 #define patch_lis_ori(ip,val) do {\
4322                 guint16 *__lis_ori = (guint16*)(ip);    \
4323                 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff;      \
4324                 __lis_ori [3] = ((guint32)(val)) & 0xffff;      \
4325         } while (0)
4326
4327 void
4328 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4329 {
4330         MonoJumpInfo *patch_info;
4331         gboolean compile_aot = !run_cctors;
4332
4333         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4334                 unsigned char *ip = patch_info->ip.i + code;
4335                 const unsigned char *target;
4336
4337                 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4338                         gpointer *jt = (gpointer*)(ip + 8);
4339                         int i;
4340                         /* jt is the inlined jump table, 2 instructions after ip
4341                          * In the normal case we store the absolute addresses,
4342                          * otherwise the displacements.
4343                          */
4344                         for (i = 0; i < patch_info->data.table->table_size; i++)
4345                                 jt [i] = code + (int)patch_info->data.table->table [i];
4346                         continue;
4347                 }
4348                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4349
4350                 if (compile_aot) {
4351                         switch (patch_info->type) {
4352                         case MONO_PATCH_INFO_BB:
4353                         case MONO_PATCH_INFO_LABEL:
4354                                 break;
4355                         default:
4356                                 /* No need to patch these */
4357                                 continue;
4358                         }
4359                 }
4360
4361                 switch (patch_info->type) {
4362                 case MONO_PATCH_INFO_IP:
4363                         g_assert_not_reached ();
4364                         patch_lis_ori (ip, ip);
4365                         continue;
4366                 case MONO_PATCH_INFO_METHOD_REL:
4367                         g_assert_not_reached ();
4368                         *((gpointer *)(ip)) = code + patch_info->data.offset;
4369                         continue;
4370                 case MONO_PATCH_INFO_METHODCONST:
4371                 case MONO_PATCH_INFO_CLASS:
4372                 case MONO_PATCH_INFO_IMAGE:
4373                 case MONO_PATCH_INFO_FIELD:
4374                 case MONO_PATCH_INFO_VTABLE:
4375                 case MONO_PATCH_INFO_IID:
4376                 case MONO_PATCH_INFO_SFLDA:
4377                 case MONO_PATCH_INFO_LDSTR:
4378                 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4379                 case MONO_PATCH_INFO_LDTOKEN:
4380                         g_assert_not_reached ();
4381                         /* from OP_AOTCONST : lis + ori */
4382                         patch_lis_ori (ip, target);
4383                         continue;
4384                 case MONO_PATCH_INFO_R4:
4385                 case MONO_PATCH_INFO_R8:
4386                         g_assert_not_reached ();
4387                         *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4388                         continue;
4389                 case MONO_PATCH_INFO_EXC_NAME:
4390                         g_assert_not_reached ();
4391                         *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4392                         continue;
4393                 case MONO_PATCH_INFO_NONE:
4394                 case MONO_PATCH_INFO_BB_OVF:
4395                 case MONO_PATCH_INFO_EXC_OVF:
4396                         /* everything is dealt with at epilog output time */
4397                         continue;
4398                 default:
4399                         break;
4400                 }
4401                 arm_patch_general (domain, ip, target);
4402         }
4403 }
4404
4405 #ifndef DISABLE_JIT
4406
4407 /*
4408  * Stack frame layout:
4409  *
4410  *   ------------------- fp
4411  *      MonoLMF structure or saved registers
4412  *   -------------------
4413  *      locals
4414  *   -------------------
4415  *      spilled regs
4416  *   -------------------
4417  *      optional 8 bytes for tracing
4418  *   -------------------
4419  *      param area             size is cfg->param_area
4420  *   ------------------- sp
4421  */
4422 guint8 *
4423 mono_arch_emit_prolog (MonoCompile *cfg)
4424 {
4425         MonoMethod *method = cfg->method;
4426         MonoBasicBlock *bb;
4427         MonoMethodSignature *sig;
4428         MonoInst *inst;
4429         int alloc_size, pos, max_offset, i, rot_amount;
4430         guint8 *code;
4431         CallInfo *cinfo;
4432         int tracing = 0;
4433         int lmf_offset = 0;
4434         int prev_sp_offset, reg_offset;
4435
4436         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4437                 tracing = 1;
4438
4439         sig = mono_method_signature (method);
4440         cfg->code_size = 256 + sig->param_count * 20;
4441         code = cfg->native_code = g_malloc (cfg->code_size);
4442
4443         mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
4444
4445         ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
4446
4447         alloc_size = cfg->stack_offset;
4448         pos = 0;
4449
4450         if (!method->save_lmf) {
4451                 /* We save SP by storing it into IP and saving IP */
4452                 ARM_PUSH (code, (cfg->used_int_regs | (1 << ARMREG_IP) | (1 << ARMREG_LR)));
4453                 prev_sp_offset = 8; /* ip and lr */
4454                 for (i = 0; i < 16; ++i) {
4455                         if (cfg->used_int_regs & (1 << i))
4456                                 prev_sp_offset += 4;
4457                 }
4458                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4459                 reg_offset = 0;
4460                 for (i = 0; i < 16; ++i) {
4461                         if ((cfg->used_int_regs & (1 << i)) || (i == ARMREG_IP) || (i == ARMREG_LR)) {
4462                                 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
4463                                 reg_offset += 4;
4464                         }
4465                 }
4466         } else {
4467                 ARM_PUSH (code, 0x5ff0);
4468                 prev_sp_offset = 4 * 10; /* all but r0-r3, sp and pc */
4469                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4470                 reg_offset = 0;
4471                 for (i = 0; i < 16; ++i) {
4472                         if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
4473                                 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
4474                                 reg_offset += 4;
4475                         }
4476                 }
4477                 pos += sizeof (MonoLMF) - prev_sp_offset;
4478                 lmf_offset = pos;
4479         }
4480         alloc_size += pos;
4481         // align to MONO_ARCH_FRAME_ALIGNMENT bytes
4482         if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
4483                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
4484                 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
4485         }
4486
4487         /* the stack used in the pushed regs */
4488         if (prev_sp_offset & 4)
4489                 alloc_size += 4;
4490         cfg->stack_usage = alloc_size;
4491         if (alloc_size) {
4492                 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
4493                         ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4494                 } else {
4495                         code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
4496                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4497                 }
4498                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
4499         }
4500         if (cfg->frame_reg != ARMREG_SP) {
4501                 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
4502                 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
4503         }
4504         //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
4505         prev_sp_offset += alloc_size;
4506
4507         /* compute max_offset in order to use short forward jumps
4508          * we could skip do it on arm because the immediate displacement
4509          * for jumps is large enough, it may be useful later for constant pools
4510          */
4511         max_offset = 0;
4512         for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4513                 MonoInst *ins = bb->code;
4514                 bb->max_offset = max_offset;
4515
4516                 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4517                         max_offset += 6;
4518
4519                 MONO_BB_FOR_EACH_INS (bb, ins)
4520                         max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4521         }
4522
4523         /* store runtime generic context */
4524         if (cfg->rgctx_var) {
4525                 MonoInst *ins = cfg->rgctx_var;
4526
4527                 g_assert (ins->opcode == OP_REGOFFSET);
4528
4529                 if (arm_is_imm12 (ins->inst_offset)) {
4530                         ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
4531                 } else {
4532                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4533                         ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
4534                 }
4535         }
4536
4537         /* load arguments allocated to register from the stack */
4538         pos = 0;
4539
4540         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig, sig->pinvoke);
4541
4542         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
4543                 ArgInfo *ainfo = &cinfo->ret;
4544                 inst = cfg->vret_addr;
4545                 g_assert (arm_is_imm12 (inst->inst_offset));
4546                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4547         }
4548
4549         if (sig->call_convention == MONO_CALL_VARARG) {
4550                 ArgInfo *cookie = &cinfo->sig_cookie;
4551
4552                 /* Save the sig cookie address */
4553                 g_assert (cookie->storage == RegTypeBase);
4554
4555                 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
4556                 g_assert (arm_is_imm12 (cfg->sig_cookie));
4557                 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
4558                 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4559         }
4560
4561         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4562                 ArgInfo *ainfo = cinfo->args + i;
4563                 inst = cfg->args [pos];
4564
4565                 if (cfg->verbose_level > 2)
4566                         g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
4567                 if (inst->opcode == OP_REGVAR) {
4568                         if (ainfo->storage == RegTypeGeneral)
4569                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
4570                         else if (ainfo->storage == RegTypeFP) {
4571                                 g_assert_not_reached ();
4572                         } else if (ainfo->storage == RegTypeBase) {
4573                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
4574                                         ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4575                                 } else {
4576                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4577                                         ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
4578                                 }
4579                         } else
4580                                 g_assert_not_reached ();
4581
4582                         if (cfg->verbose_level > 2)
4583                                 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
4584                 } else {
4585                         /* the argument should be put on the stack: FIXME handle size != word  */
4586                         if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
4587                                 switch (ainfo->size) {
4588                                 case 1:
4589                                         if (arm_is_imm12 (inst->inst_offset))
4590                                                 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4591                                         else {
4592                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4593                                                 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4594                                         }
4595                                         break;
4596                                 case 2:
4597                                         if (arm_is_imm8 (inst->inst_offset)) {
4598                                                 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4599                                         } else {
4600                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4601                                                 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4602                                         }
4603                                         break;
4604                                 case 8:
4605                                         g_assert (arm_is_imm12 (inst->inst_offset));
4606                                         ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4607                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
4608                                         ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
4609                                         break;
4610                                 default:
4611                                         if (arm_is_imm12 (inst->inst_offset)) {
4612                                                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4613                                         } else {
4614                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4615                                                 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4616                                         }
4617                                         break;
4618                                 }
4619                         } else if (ainfo->storage == RegTypeBaseGen) {
4620                                 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
4621                                 g_assert (arm_is_imm12 (inst->inst_offset));
4622                                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4623                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
4624                                 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
4625                         } else if (ainfo->storage == RegTypeBase) {
4626                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
4627                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4628                                 } else {
4629                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
4630                                         ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
4631                                 }
4632
4633                                 switch (ainfo->size) {
4634                                 case 1:
4635                                         if (arm_is_imm8 (inst->inst_offset)) {
4636                                                 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4637                                         } else {
4638                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4639                                                 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4640                                         }
4641                                         break;
4642                                 case 2:
4643                                         if (arm_is_imm8 (inst->inst_offset)) {
4644                                                 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4645                                         } else {
4646                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4647                                                 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4648                                         }
4649                                         break;
4650                                 case 8:
4651                                         if (arm_is_imm12 (inst->inst_offset)) {
4652                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4653                                         } else {
4654                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4655                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4656                                         }
4657                                         if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
4658                                                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
4659                                         } else {
4660                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
4661                                                 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
4662                                         }
4663                                         if (arm_is_imm12 (inst->inst_offset + 4)) {
4664                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
4665                                         } else {
4666                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
4667                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4668                                         }
4669                                         break;
4670                                 default:
4671                                         if (arm_is_imm12 (inst->inst_offset)) {
4672                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4673                                         } else {
4674                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4675                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4676                                         }
4677                                         break;
4678                                 }
4679                         } else if (ainfo->storage == RegTypeFP) {
4680                                 g_assert_not_reached ();
4681                         } else if (ainfo->storage == RegTypeStructByVal) {
4682                                 int doffset = inst->inst_offset;
4683                                 int soffset = 0;
4684                                 int cur_reg;
4685                                 int size = 0;
4686                                 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
4687                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
4688                                         if (arm_is_imm12 (doffset)) {
4689                                                 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
4690                                         } else {
4691                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
4692                                                 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
4693                                         }
4694                                         soffset += sizeof (gpointer);
4695                                         doffset += sizeof (gpointer);
4696                                 }
4697                                 if (ainfo->vtsize) {
4698                                         /* FIXME: handle overrun! with struct sizes not multiple of 4 */
4699                                         //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
4700                                         code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
4701                                 }
4702                         } else if (ainfo->storage == RegTypeStructByAddr) {
4703                                 g_assert_not_reached ();
4704                                 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
4705                                 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
4706                         } else
4707                                 g_assert_not_reached ();
4708                 }
4709                 pos++;
4710         }
4711
4712         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4713                 if (cfg->compile_aot)
4714                         /* AOT code is only used in the root domain */
4715                         code = mono_arm_emit_load_imm (code, ARMREG_R0, 0);
4716                 else
4717                         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->domain);
4718                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4719                              (gpointer)"mono_jit_thread_attach");
4720                 code = emit_call_seq (cfg, code);
4721         }
4722
4723         if (method->save_lmf) {
4724                 gboolean get_lmf_fast = FALSE;
4725
4726 #ifdef HAVE_AEABI_READ_TP
4727                 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
4728
4729                 if (lmf_addr_tls_offset != -1) {
4730                         get_lmf_fast = TRUE;
4731
4732                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4733                                                                  (gpointer)"__aeabi_read_tp");
4734                         code = emit_call_seq (cfg, code);
4735
4736                         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
4737                         get_lmf_fast = TRUE;
4738                 }
4739 #endif
4740                 if (!get_lmf_fast) {
4741                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4742                                                                  (gpointer)"mono_get_lmf_addr");
4743                         code = emit_call_seq (cfg, code);
4744                 }
4745                 /* we build the MonoLMF structure on the stack - see mini-arm.h */
4746                 /* lmf_offset is the offset from the previous stack pointer,
4747                  * alloc_size is the total stack space allocated, so the offset
4748                  * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
4749                  * The pointer to the struct is put in r1 (new_lmf).
4750                  * r2 is used as scratch
4751                  * The callee-saved registers are already in the MonoLMF structure
4752                  */
4753                 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, alloc_size - lmf_offset);
4754                 /* r0 is the result from mono_get_lmf_addr () */
4755                 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
4756                 /* new_lmf->previous_lmf = *lmf_addr */
4757                 ARM_LDR_IMM (code, ARMREG_R2, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
4758                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
4759                 /* *(lmf_addr) = r1 */
4760                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
4761                 /* Skip method (only needed for trampoline LMF frames) */
4762                 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, esp));
4763                 /* save the current IP */
4764                 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
4765                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, eip));
4766         }
4767
4768         if (tracing)
4769                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4770
4771         if (cfg->arch.seq_point_info_var) {
4772                 MonoInst *ins = cfg->arch.seq_point_info_var;
4773
4774                 /* Initialize the variable from a GOT slot */
4775                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
4776                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
4777                 ARM_B (code, 0);
4778                 *(gpointer*)code = NULL;
4779                 code += 4;
4780                 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
4781
4782                 g_assert (ins->opcode == OP_REGOFFSET);
4783
4784                 if (arm_is_imm12 (ins->inst_offset)) {
4785                         ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
4786                 } else {
4787                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4788                         ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
4789                 }
4790         }
4791
4792         /* Initialize ss_trigger_page_var */
4793         {
4794                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4795                 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4796                 int dreg = ARMREG_LR;
4797
4798                 if (info_var) {
4799                         g_assert (info_var->opcode == OP_REGOFFSET);
4800                         g_assert (arm_is_imm12 (info_var->inst_offset));
4801
4802                         ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4803                         /* Load the trigger page addr */
4804                         ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
4805                         ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
4806                 }
4807         }
4808
4809         cfg->code_len = code - cfg->native_code;
4810         g_assert (cfg->code_len < cfg->code_size);
4811         g_free (cinfo);
4812
4813         return code;
4814 }
4815
4816 void
4817 mono_arch_emit_epilog (MonoCompile *cfg)
4818 {
4819         MonoMethod *method = cfg->method;
4820         int pos, i, rot_amount;
4821         int max_epilog_size = 16 + 20*4;
4822         guint8 *code;
4823         CallInfo *cinfo;
4824
4825         if (cfg->method->save_lmf)
4826                 max_epilog_size += 128;
4827
4828         if (mono_jit_trace_calls != NULL)
4829                 max_epilog_size += 50;
4830
4831         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4832                 max_epilog_size += 50;
4833
4834         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4835                 cfg->code_size *= 2;
4836                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4837                 mono_jit_stats.code_reallocs++;
4838         }
4839
4840         /*
4841          * Keep in sync with OP_JMP
4842          */
4843         code = cfg->native_code + cfg->code_len;
4844
4845         if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
4846                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4847         }
4848         pos = 0;
4849
4850         /* Load returned vtypes into registers if needed */
4851         cinfo = cfg->arch.cinfo;
4852         if (cinfo->ret.storage == RegTypeStructByVal) {
4853                 MonoInst *ins = cfg->ret;
4854
4855                 if (arm_is_imm12 (ins->inst_offset)) {
4856                         ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
4857                 } else {
4858                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4859                         ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
4860                 }
4861         }
4862
4863         if (method->save_lmf) {
4864                 int lmf_offset;
4865                 /* all but r0-r3, sp and pc */
4866                 pos += sizeof (MonoLMF) - (4 * 10);
4867                 lmf_offset = pos;
4868                 /* r2 contains the pointer to the current LMF */
4869                 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, cfg->stack_usage - lmf_offset);
4870                 /* ip = previous_lmf */
4871                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
4872                 /* lr = lmf_addr */
4873                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
4874                 /* *(lmf_addr) = previous_lmf */
4875                 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
4876                 /* FIXME: speedup: there is no actual need to restore the registers if
4877                  * we didn't actually change them (idea from Zoltan).
4878                  */
4879                 /* restore iregs */
4880                 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
4881                 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_R2, (sizeof (MonoLMF) - 10 * sizeof (gulong)));
4882                 ARM_POP_NWB (code, 0xaff0); /* restore ip to sp and lr to pc */
4883         } else {
4884                 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
4885                         ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
4886                 } else {
4887                         code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
4888                         ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4889                 }
4890                 /* FIXME: add v4 thumb interworking support */
4891                 ARM_POP_NWB (code, cfg->used_int_regs | ((1 << ARMREG_SP) | (1 << ARMREG_PC)));
4892         }
4893
4894         cfg->code_len = code - cfg->native_code;
4895
4896         g_assert (cfg->code_len < cfg->code_size);
4897
4898 }
4899
4900 /* remove once throw_exception_by_name is eliminated */
4901 static int
4902 exception_id_by_name (const char *name)
4903 {
4904         if (strcmp (name, "IndexOutOfRangeException") == 0)
4905                 return MONO_EXC_INDEX_OUT_OF_RANGE;
4906         if (strcmp (name, "OverflowException") == 0)
4907                 return MONO_EXC_OVERFLOW;
4908         if (strcmp (name, "ArithmeticException") == 0)
4909                 return MONO_EXC_ARITHMETIC;
4910         if (strcmp (name, "DivideByZeroException") == 0)
4911                 return MONO_EXC_DIVIDE_BY_ZERO;
4912         if (strcmp (name, "InvalidCastException") == 0)
4913                 return MONO_EXC_INVALID_CAST;
4914         if (strcmp (name, "NullReferenceException") == 0)
4915                 return MONO_EXC_NULL_REF;
4916         if (strcmp (name, "ArrayTypeMismatchException") == 0)
4917                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
4918         if (strcmp (name, "ArgumentException") == 0)
4919                 return MONO_EXC_ARGUMENT;
4920         g_error ("Unknown intrinsic exception %s\n", name);
4921         return -1;
4922 }
4923
4924 void
4925 mono_arch_emit_exceptions (MonoCompile *cfg)
4926 {
4927         MonoJumpInfo *patch_info;
4928         int i;
4929         guint8 *code;
4930         guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
4931         guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
4932         int max_epilog_size = 50;
4933
4934         for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
4935                 exc_throw_pos [i] = NULL;
4936                 exc_throw_found [i] = 0;
4937         }
4938
4939         /* count the number of exception infos */
4940
4941         /*
4942          * make sure we have enough space for exceptions
4943          */
4944         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4945                 if (patch_info->type == MONO_PATCH_INFO_EXC) {
4946                         i = exception_id_by_name (patch_info->data.target);
4947                         if (!exc_throw_found [i]) {
4948                                 max_epilog_size += 32;
4949                                 exc_throw_found [i] = TRUE;
4950                         }
4951                 }
4952         }
4953
4954         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4955                 cfg->code_size *= 2;
4956                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4957                 mono_jit_stats.code_reallocs++;
4958         }
4959
4960         code = cfg->native_code + cfg->code_len;
4961
4962         /* add code to raise exceptions */
4963         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4964                 switch (patch_info->type) {
4965                 case MONO_PATCH_INFO_EXC: {
4966                         MonoClass *exc_class;
4967                         unsigned char *ip = patch_info->ip.i + cfg->native_code;
4968
4969                         i = exception_id_by_name (patch_info->data.target);
4970                         if (exc_throw_pos [i]) {
4971                                 arm_patch (ip, exc_throw_pos [i]);
4972                                 patch_info->type = MONO_PATCH_INFO_NONE;
4973                                 break;
4974                         } else {
4975                                 exc_throw_pos [i] = code;
4976                         }
4977                         arm_patch (ip, code);
4978
4979                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4980                         g_assert (exc_class);
4981
4982                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
4983                         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
4984                         patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4985                         patch_info->data.name = "mono_arch_throw_corlib_exception";
4986                         patch_info->ip.i = code - cfg->native_code;
4987                         ARM_BL (code, 0);
4988                         *(guint32*)(gpointer)code = exc_class->type_token;
4989                         code += 4;
4990                         break;
4991                 }
4992                 default:
4993                         /* do nothing */
4994                         break;
4995                 }
4996         }
4997
4998         cfg->code_len = code - cfg->native_code;
4999
5000         g_assert (cfg->code_len < cfg->code_size);
5001
5002 }
5003
5004 #endif /* #ifndef DISABLE_JIT */
5005
5006 static gboolean tls_offset_inited = FALSE;
5007
5008 void
5009 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5010 {
5011         if (!tls_offset_inited) {
5012                 tls_offset_inited = TRUE;
5013
5014                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5015                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5016         }
5017 }
5018
5019 void
5020 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5021 {
5022 }
5023
5024 MonoInst*
5025 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5026 {
5027         /* FIXME: */
5028         return NULL;
5029 }
5030
5031 gboolean
5032 mono_arch_print_tree (MonoInst *tree, int arity)
5033 {
5034         return 0;
5035 }
5036
5037 MonoInst*
5038 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5039 {
5040         return mono_get_domain_intrinsic (cfg);
5041 }
5042
5043 guint32
5044 mono_arch_get_patch_offset (guint8 *code)
5045 {
5046         /* OP_AOTCONST */
5047         return 8;
5048 }
5049
5050 void
5051 mono_arch_flush_register_windows (void)
5052 {
5053 }
5054
5055 #ifdef MONO_ARCH_HAVE_IMT
5056
5057 #ifndef DISABLE_JIT
5058
5059 void
5060 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5061 {
5062         if (cfg->compile_aot) {
5063                 int method_reg = mono_alloc_ireg (cfg);
5064                 MonoInst *ins;
5065
5066                 call->dynamic_imt_arg = TRUE;
5067
5068                 if (imt_arg) {
5069                         mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5070                 } else {
5071                         MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5072                         ins->dreg = method_reg;
5073                         ins->inst_p0 = call->method;
5074                         ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5075                         MONO_ADD_INS (cfg->cbb, ins);
5076
5077                         mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5078                 }
5079         } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5080
5081                 /* Always pass in a register for simplicity */
5082                 call->dynamic_imt_arg = TRUE;
5083
5084                 cfg->uses_rgctx_reg = TRUE;
5085
5086                 if (imt_arg) {
5087                         mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5088                 } else {
5089                         MonoInst *ins;
5090                         int method_reg = mono_alloc_preg (cfg);
5091
5092                         MONO_INST_NEW (cfg, ins, OP_PCONST);
5093                         ins->inst_p0 = call->method;
5094                         ins->dreg = method_reg;
5095                         MONO_ADD_INS (cfg->cbb, ins);
5096
5097                         mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5098                 }
5099         }
5100 }
5101
5102 #endif /* DISABLE_JIT */
5103
5104 MonoMethod*
5105 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5106 {
5107         guint32 *code_ptr = (guint32*)code;
5108         code_ptr -= 2;
5109
5110         if (mono_use_llvm)
5111                 /* Passed in V5 */
5112                 return (MonoMethod*)regs [ARMREG_V5];
5113
5114         /* The IMT value is stored in the code stream right after the LDC instruction. */
5115         if (!IS_LDR_PC (code_ptr [0])) {
5116                 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5117                 g_assert (IS_LDR_PC (code_ptr [0]));
5118         }
5119         if (code_ptr [1] == 0)
5120                 /* This is AOTed code, the IMT method is in V5 */
5121                 return (MonoMethod*)regs [ARMREG_V5];
5122         else
5123                 return (MonoMethod*) code_ptr [1];
5124 }
5125
5126 MonoVTable*
5127 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5128 {
5129         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5130 }
5131
5132 #define ENABLE_WRONG_METHOD_CHECK 0
5133 #define BASE_SIZE (6 * 4)
5134 #define BSEARCH_ENTRY_SIZE (4 * 4)
5135 #define CMP_SIZE (3 * 4)
5136 #define BRANCH_SIZE (1 * 4)
5137 #define CALL_SIZE (2 * 4)
5138 #define WMC_SIZE (5 * 4)
5139 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5140
5141 static arminstr_t *
5142 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5143 {
5144         guint32 delta = DISTANCE (target, code);
5145         delta -= 8;
5146         g_assert (delta >= 0 && delta <= 0xFFF);
5147         *target = *target | delta;
5148         *code = value;
5149         return code + 1;
5150 }
5151
5152 gpointer
5153 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5154         gpointer fail_tramp)
5155 {
5156         int size, i, extra_space = 0;
5157         arminstr_t *code, *start, *vtable_target = NULL;
5158         gboolean large_offsets = FALSE;
5159         guint32 **constant_pool_starts;
5160
5161         size = BASE_SIZE;
5162         constant_pool_starts = g_new0 (guint32*, count);
5163
5164         for (i = 0; i < count; ++i) {
5165                 MonoIMTCheckItem *item = imt_entries [i];
5166                 if (item->is_equals) {
5167                         gboolean fail_case = !item->check_target_idx && fail_tramp;
5168
5169                         if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5170                                 item->chunk_size += 32;
5171                                 large_offsets = TRUE;
5172                         }
5173
5174                         if (item->check_target_idx || fail_case) {
5175                                 if (!item->compare_done || fail_case)
5176                                         item->chunk_size += CMP_SIZE;
5177                                 item->chunk_size += BRANCH_SIZE;
5178                         } else {
5179 #if ENABLE_WRONG_METHOD_CHECK
5180                                 item->chunk_size += WMC_SIZE;
5181 #endif
5182                         }
5183                         if (fail_case) {
5184                                 item->chunk_size += 16;
5185                                 large_offsets = TRUE;
5186                         }
5187                         item->chunk_size += CALL_SIZE;
5188                 } else {
5189                         item->chunk_size += BSEARCH_ENTRY_SIZE;
5190                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5191                 }
5192                 size += item->chunk_size;
5193         }
5194
5195         if (large_offsets)
5196                 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5197
5198         if (fail_tramp)
5199                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5200         else
5201                 code = mono_domain_code_reserve (domain, size);
5202         start = code;
5203
5204 #if DEBUG_IMT
5205         printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5206         for (i = 0; i < count; ++i) {
5207                 MonoIMTCheckItem *item = imt_entries [i];
5208                 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5209         }
5210 #endif
5211
5212         if (large_offsets)
5213                 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5214         else
5215                 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5216         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5217         vtable_target = code;
5218         ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5219
5220         if (mono_use_llvm) {
5221                 /* LLVM always passes the IMT method in R5 */
5222                 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5223         } else {
5224                 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5225                 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5226                 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5227         }
5228
5229         for (i = 0; i < count; ++i) {
5230                 MonoIMTCheckItem *item = imt_entries [i];
5231                 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5232                 gint32 vtable_offset;
5233
5234                 item->code_target = (guint8*)code;
5235
5236                 if (item->is_equals) {
5237                         gboolean fail_case = !item->check_target_idx && fail_tramp;
5238
5239                         if (item->check_target_idx || fail_case) {
5240                                 if (!item->compare_done || fail_case) {
5241                                         imt_method = code;
5242                                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5243                                         ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5244                                 }
5245                                 item->jmp_code = (guint8*)code;
5246                                 ARM_B_COND (code, ARMCOND_NE, 0);
5247                         } else {
5248                                 /*Enable the commented code to assert on wrong method*/
5249 #if ENABLE_WRONG_METHOD_CHECK
5250                                 imt_method = code;
5251                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5252                                 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5253                                 ARM_B_COND (code, ARMCOND_NE, 1);
5254
5255                                 ARM_DBRK (code);
5256 #endif
5257                         }
5258
5259                         if (item->has_target_code) {
5260                                 target_code_ins = code;
5261                                 /* Load target address */
5262                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5263                                 /* Save it to the fourth slot */
5264                                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5265                                 /* Restore registers and branch */
5266                                 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5267
5268                                 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5269                         } else {
5270                                 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5271                                 if (!arm_is_imm12 (vtable_offset)) {
5272                                         /*
5273                                          * We need to branch to a computed address but we don't have
5274                                          * a free register to store it, since IP must contain the
5275                                          * vtable address. So we push the two values to the stack, and
5276                                          * load them both using LDM.
5277                                          */
5278                                         /* Compute target address */
5279                                         vtable_offset_ins = code;
5280                                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5281                                         ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5282                                         /* Save it to the fourth slot */
5283                                         ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5284                                         /* Restore registers and branch */
5285                                         ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5286
5287                                         code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5288                                 } else {
5289                                         ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5290                                         if (large_offsets)
5291                                                 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5292                                         ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5293                                 }
5294                         }
5295
5296                         if (fail_case) {
5297                                 arm_patch (item->jmp_code, (guchar*)code);
5298
5299                                 target_code_ins = code;
5300                                 /* Load target address */
5301                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5302                                 /* Save it to the fourth slot */
5303                                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5304                                 /* Restore registers and branch */
5305                                 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5306
5307                                 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5308                                 item->jmp_code = NULL;
5309                         }
5310
5311                         if (imt_method)
5312                                 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5313
5314                         /*must emit after unconditional branch*/
5315                         if (vtable_target) {
5316                                 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5317                                 item->chunk_size += 4;
5318                                 vtable_target = NULL;
5319                         }
5320
5321                         /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5322                         constant_pool_starts [i] = code;
5323                         if (extra_space) {
5324                                 code += extra_space;
5325                                 extra_space = 0;
5326                         }
5327                 } else {
5328                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5329                         ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5330
5331                         item->jmp_code = (guint8*)code;
5332                         ARM_B_COND (code, ARMCOND_GE, 0);
5333                         ++extra_space;
5334                 }
5335         }
5336
5337         for (i = 0; i < count; ++i) {
5338                 MonoIMTCheckItem *item = imt_entries [i];
5339                 if (item->jmp_code) {
5340                         if (item->check_target_idx)
5341                                 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5342                 }
5343                 if (i > 0 && item->is_equals) {
5344                         int j;
5345                         arminstr_t *space_start = constant_pool_starts [i];
5346                         for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5347                                 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5348                         }
5349                 }
5350         }
5351
5352 #if DEBUG_IMT
5353         {
5354                 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5355                 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5356                 g_free (buff);
5357         }
5358 #endif
5359
5360         g_free (constant_pool_starts);
5361
5362         mono_arch_flush_icache ((guint8*)start, size);
5363         mono_stats.imt_thunks_size += code - start;
5364
5365         g_assert (DISTANCE (start, code) <= size);
5366         return start;
5367 }
5368
5369 #endif
5370
5371 gpointer
5372 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5373 {
5374         if (reg == ARMREG_SP)
5375                 return (gpointer)ctx->esp;
5376         else
5377                 return (gpointer)ctx->regs [reg];
5378 }
5379
5380 /*
5381  * mono_arch_set_breakpoint:
5382  *
5383  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
5384  * The location should contain code emitted by OP_SEQ_POINT.
5385  */
5386 void
5387 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5388 {
5389         guint8 *code = ip;
5390         guint32 native_offset = ip - (guint8*)ji->code_start;
5391
5392         if (ji->from_aot) {
5393                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5394
5395                 g_assert (native_offset % 4 == 0);
5396                 g_assert (info->bp_addrs [native_offset / 4] == 0);
5397                 info->bp_addrs [native_offset / 4] = bp_trigger_page;
5398         } else {
5399                 int dreg = ARMREG_LR;
5400
5401                 /* Read from another trigger page */
5402                 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
5403                 ARM_B (code, 0);
5404                 *(int*)code = (int)bp_trigger_page;
5405                 code += 4;
5406                 ARM_LDR_IMM (code, dreg, dreg, 0);
5407
5408                 mono_arch_flush_icache (code - 16, 16);
5409
5410 #if 0
5411                 /* This is currently implemented by emitting an SWI instruction, which
5412                  * qemu/linux seems to convert to a SIGILL.
5413                  */
5414                 *(int*)code = (0xef << 24) | 8;
5415                 code += 4;
5416                 mono_arch_flush_icache (code - 4, 4);
5417 #endif
5418         }
5419 }
5420
5421 /*
5422  * mono_arch_clear_breakpoint:
5423  *
5424  *   Clear the breakpoint at IP.
5425  */
5426 void
5427 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5428 {
5429         guint8 *code = ip;
5430         int i;
5431
5432         if (ji->from_aot) {
5433                 guint32 native_offset = ip - (guint8*)ji->code_start;
5434                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5435
5436                 g_assert (native_offset % 4 == 0);
5437                 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
5438                 info->bp_addrs [native_offset / 4] = 0;
5439         } else {
5440                 for (i = 0; i < 4; ++i)
5441                         ARM_NOP (code);
5442
5443                 mono_arch_flush_icache (ip, code - ip);
5444         }
5445 }
5446
5447 /*
5448  * mono_arch_start_single_stepping:
5449  *
5450  *   Start single stepping.
5451  */
5452 void
5453 mono_arch_start_single_stepping (void)
5454 {
5455         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
5456 }
5457
5458 /*
5459  * mono_arch_stop_single_stepping:
5460  *
5461  *   Stop single stepping.
5462  */
5463 void
5464 mono_arch_stop_single_stepping (void)
5465 {
5466         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
5467 }
5468
5469 #if __APPLE__
5470 #define DBG_SIGNAL SIGBUS
5471 #else
5472 #define DBG_SIGNAL SIGSEGV
5473 #endif
5474
5475 /*
5476  * mono_arch_is_single_step_event:
5477  *
5478  *   Return whenever the machine state in SIGCTX corresponds to a single
5479  * step event.
5480  */
5481 gboolean
5482 mono_arch_is_single_step_event (void *info, void *sigctx)
5483 {
5484         siginfo_t *sinfo = info;
5485
5486         /* Sometimes the address is off by 4 */
5487         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
5488                 return TRUE;
5489         else
5490                 return FALSE;
5491 }
5492
5493 /*
5494  * mono_arch_is_breakpoint_event:
5495  *
5496  *   Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
5497  */
5498 gboolean
5499 mono_arch_is_breakpoint_event (void *info, void *sigctx)
5500 {
5501         siginfo_t *sinfo = info;
5502
5503         if (sinfo->si_signo == DBG_SIGNAL) {
5504                 /* Sometimes the address is off by 4 */
5505                 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
5506                         return TRUE;
5507                 else
5508                         return FALSE;
5509         } else {
5510                 return FALSE;
5511         }
5512 }
5513
5514 guint8*
5515 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
5516 {
5517         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
5518
5519         if (ji->from_aot)
5520                 ip -= 6 * 4;
5521         else
5522                 ip -= 12;
5523
5524         return ip;
5525 }
5526
5527 guint8*
5528 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
5529 {
5530         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
5531
5532         ip += 4;
5533
5534         return ip;
5535 }
5536
5537 /*
5538  * mono_arch_skip_breakpoint:
5539  *
5540  *   See mini-amd64.c for docs.
5541  */
5542 void
5543 mono_arch_skip_breakpoint (MonoContext *ctx)
5544 {
5545         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
5546 }
5547
5548 /*
5549  * mono_arch_skip_single_step:
5550  *
5551  *   See mini-amd64.c for docs.
5552  */
5553 void
5554 mono_arch_skip_single_step (MonoContext *ctx)
5555 {
5556         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
5557 }
5558
5559 /*
5560  * mono_arch_get_seq_point_info:
5561  *
5562  *   See mini-amd64.c for docs.
5563  */
5564 gpointer
5565 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
5566 {
5567         SeqPointInfo *info;
5568         MonoJitInfo *ji;
5569
5570         // FIXME: Add a free function
5571
5572         mono_domain_lock (domain);
5573         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
5574                                                                 code);
5575         mono_domain_unlock (domain);
5576
5577         if (!info) {
5578                 ji = mono_jit_info_table_find (domain, (char*)code);
5579                 g_assert (ji);
5580
5581                 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
5582
5583                 info->ss_trigger_page = ss_trigger_page;
5584                 info->bp_trigger_page = bp_trigger_page;
5585
5586                 mono_domain_lock (domain);
5587                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
5588                                                          code, info);
5589                 mono_domain_unlock (domain);
5590         }
5591
5592         return info;
5593 }