2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
24 #include "mini-arm-tls.h"
28 #include "debugger-agent.h"
30 #include "mono/arch/arm/arm-vfp-codegen.h"
32 #if defined(HAVE_KW_THREAD) && defined(__linux__) \
33 || defined(TARGET_ANDROID) \
34 || defined(TARGET_IOS)
38 /* Sanity check: This makes no sense */
39 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
40 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
44 * IS_SOFT_FLOAT: Is full software floating point used?
45 * IS_HARD_FLOAT: Is full hardware floating point used?
46 * IS_VFP: Is hardware floating point with software ABI used?
48 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
49 * IS_VFP may delegate to mono_arch_is_soft_float ().
52 #if defined(ARM_FPU_VFP_HARD)
53 #define IS_SOFT_FLOAT (FALSE)
54 #define IS_HARD_FLOAT (TRUE)
56 #elif defined(ARM_FPU_NONE)
57 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
58 #define IS_HARD_FLOAT (FALSE)
59 #define IS_VFP (!mono_arch_is_soft_float ())
61 #define IS_SOFT_FLOAT (FALSE)
62 #define IS_HARD_FLOAT (FALSE)
66 #define THUNK_SIZE (3 * 4)
68 #ifdef __native_client_codegen__
69 const guint kNaClAlignment = kNaClAlignmentARM;
70 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
71 gint8 nacl_align_byte = -1; /* 0xff */
74 mono_arch_nacl_pad (guint8 *code, int pad)
76 /* Not yet properly implemented. */
77 g_assert_not_reached ();
82 mono_arch_nacl_skip_nops (guint8 *code)
84 /* Not yet properly implemented. */
85 g_assert_not_reached ();
89 #endif /* __native_client_codegen__ */
91 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
94 void sys_icache_invalidate (void *start, size_t len);
97 /* This mutex protects architecture specific caches */
98 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
99 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
100 static mono_mutex_t mini_arch_mutex;
102 static gboolean v5_supported = FALSE;
103 static gboolean v6_supported = FALSE;
104 static gboolean v7_supported = FALSE;
105 static gboolean v7s_supported = FALSE;
106 static gboolean thumb_supported = FALSE;
107 static gboolean thumb2_supported = FALSE;
109 * Whenever to use the ARM EABI
111 static gboolean eabi_supported = FALSE;
114 * Whenever to use the iphone ABI extensions:
115 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
116 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
117 * This is required for debugging/profiling tools to work, but it has some overhead so it should
118 * only be turned on in debug builds.
120 static gboolean iphone_abi = FALSE;
123 * The FPU we are generating code for. This is NOT runtime configurable right now,
124 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
126 static MonoArmFPU arm_fpu;
128 #if defined(ARM_FPU_VFP_HARD)
130 * On armhf, d0-d7 are used for argument passing and d8-d15
131 * must be preserved across calls, which leaves us no room
132 * for scratch registers. So we use d14-d15 but back up their
133 * previous contents to a stack slot before using them - see
134 * mono_arm_emit_vfp_scratch_save/_restore ().
136 static int vfp_scratch1 = ARM_VFP_D14;
137 static int vfp_scratch2 = ARM_VFP_D15;
140 * On armel, d0-d7 do not need to be preserved, so we can
141 * freely make use of them as scratch registers.
143 static int vfp_scratch1 = ARM_VFP_D0;
144 static int vfp_scratch2 = ARM_VFP_D1;
149 static volatile int ss_trigger_var = 0;
151 static gpointer single_step_tramp, breakpoint_tramp;
154 * The code generated for sequence points reads from this location, which is
155 * made read-only when single stepping is enabled.
157 static gpointer ss_trigger_page;
159 /* Enabled breakpoints read from this trigger page */
160 static gpointer bp_trigger_page;
164 * floating point support: on ARM it is a mess, there are at least 3
165 * different setups, each of which binary incompat with the other.
166 * 1) FPA: old and ugly, but unfortunately what current distros use
167 * the double binary format has the two words swapped. 8 double registers.
168 * Implemented usually by kernel emulation.
169 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
170 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
171 * 3) VFP: the new and actually sensible and useful FP support. Implemented
172 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
174 * We do not care about FPA. We will support soft float and VFP.
176 int mono_exc_esp_offset = 0;
178 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
179 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
180 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
182 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
183 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
184 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
186 //#define DEBUG_IMT 0
189 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
193 mono_arch_regname (int reg)
195 static const char * rnames[] = {
196 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
197 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
198 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
201 if (reg >= 0 && reg < 16)
207 mono_arch_fregname (int reg)
209 static const char * rnames[] = {
210 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
211 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
212 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
213 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
214 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
215 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
218 if (reg >= 0 && reg < 32)
226 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
228 int imm8, rot_amount;
229 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
230 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
234 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
235 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
237 code = mono_arm_emit_load_imm (code, dreg, imm);
238 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
243 /* If dreg == sreg, this clobbers IP */
245 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
247 int imm8, rot_amount;
248 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
249 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
253 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
254 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
256 code = mono_arm_emit_load_imm (code, dreg, imm);
257 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
263 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
265 /* we can use r0-r3, since this is called only for incoming args on the stack */
266 if (size > sizeof (gpointer) * 4) {
268 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
269 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
270 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
271 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
272 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
273 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
274 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
275 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
276 ARM_B_COND (code, ARMCOND_NE, 0);
277 arm_patch (code - 4, start_loop);
280 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
281 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
283 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
284 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
290 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
291 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
292 doffset = soffset = 0;
294 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
295 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
301 g_assert (size == 0);
306 emit_call_reg (guint8 *code, int reg)
309 ARM_BLX_REG (code, reg);
311 #ifdef USE_JUMP_TABLES
312 g_assert_not_reached ();
314 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
318 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
324 emit_call_seq (MonoCompile *cfg, guint8 *code)
326 #ifdef USE_JUMP_TABLES
327 code = mono_arm_patchable_bl (code, ARMCOND_AL);
329 if (cfg->method->dynamic) {
330 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
332 *(gpointer*)code = NULL;
334 code = emit_call_reg (code, ARMREG_IP);
338 cfg->thunk_area += THUNK_SIZE;
344 mono_arm_patchable_b (guint8 *code, int cond)
346 #ifdef USE_JUMP_TABLES
349 jte = mono_jumptable_add_entry ();
350 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
351 ARM_BX_COND (code, cond, ARMREG_IP);
353 ARM_B_COND (code, cond, 0);
359 mono_arm_patchable_bl (guint8 *code, int cond)
361 #ifdef USE_JUMP_TABLES
364 jte = mono_jumptable_add_entry ();
365 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
366 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
368 ARM_BL_COND (code, cond, 0);
373 #ifdef USE_JUMP_TABLES
375 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
377 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
378 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
383 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
385 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
386 ARM_LDR_IMM (code, reg, reg, 0);
392 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
395 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
396 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
398 code = emit_call_seq (cfg, code);
399 if (dreg != ARMREG_R0)
400 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
402 g_assert_not_reached ();
408 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
411 if (tls_offset_reg != ARMREG_R0)
412 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
413 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
415 code = emit_call_seq (cfg, code);
416 if (dreg != ARMREG_R0)
417 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
419 g_assert_not_reached ();
425 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
428 if (sreg != ARMREG_R1)
429 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
430 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
431 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
433 code = emit_call_seq (cfg, code);
435 g_assert_not_reached ();
441 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
444 /* Get sreg in R1 and tls_offset_reg in R0 */
445 if (tls_offset_reg == ARMREG_R1) {
446 if (sreg == ARMREG_R0) {
447 /* swap sreg and tls_offset_reg */
448 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
449 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
450 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
452 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
453 if (sreg != ARMREG_R1)
454 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
457 if (sreg != ARMREG_R1)
458 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
459 if (tls_offset_reg != ARMREG_R0)
460 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
462 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
464 code = emit_call_seq (cfg, code);
466 g_assert_not_reached ();
474 * Emit code to push an LMF structure on the LMF stack.
475 * On arm, this is intermixed with the initialization of other fields of the structure.
478 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
480 gboolean get_lmf_fast = FALSE;
483 if (mono_arm_have_tls_get ()) {
485 if (cfg->compile_aot) {
487 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
488 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
490 *(gpointer*)code = NULL;
492 /* Load the value from the GOT */
493 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
494 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
496 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
497 g_assert (lmf_addr_tls_offset != -1);
498 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
503 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
504 (gpointer)"mono_get_lmf_addr");
505 code = emit_call_seq (cfg, code);
507 /* we build the MonoLMF structure on the stack - see mini-arm.h */
508 /* lmf_offset is the offset from the previous stack pointer,
509 * alloc_size is the total stack space allocated, so the offset
510 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
511 * The pointer to the struct is put in r1 (new_lmf).
512 * ip is used as scratch
513 * The callee-saved registers are already in the MonoLMF structure
515 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
516 /* r0 is the result from mono_get_lmf_addr () */
517 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
518 /* new_lmf->previous_lmf = *lmf_addr */
519 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
520 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
521 /* *(lmf_addr) = r1 */
522 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
523 /* Skip method (only needed for trampoline LMF frames) */
524 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
525 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
526 /* save the current IP */
527 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
528 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
530 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
531 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
542 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
546 g_assert (!cfg->r4fp);
548 for (list = inst->float_args; list; list = list->next) {
549 FloatArgData *fad = list->data;
550 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
551 gboolean imm = arm_is_fpimm8 (var->inst_offset);
553 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
559 if (*offset + *max_len > cfg->code_size) {
560 cfg->code_size += *max_len;
561 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
563 code = cfg->native_code + *offset;
567 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
568 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
570 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
572 *offset = code - cfg->native_code;
579 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
583 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
585 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
588 if (!arm_is_fpimm8 (inst->inst_offset)) {
589 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
590 ARM_FSTD (code, reg, ARMREG_LR, 0);
592 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
599 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
603 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
605 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
608 if (!arm_is_fpimm8 (inst->inst_offset)) {
609 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
610 ARM_FLDD (code, reg, ARMREG_LR, 0);
612 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
621 * Emit code to pop an LMF structure from the LMF stack.
624 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
628 if (lmf_offset < 32) {
629 basereg = cfg->frame_reg;
634 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
637 /* ip = previous_lmf */
638 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
640 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
641 /* *(lmf_addr) = previous_lmf */
642 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
647 #endif /* #ifndef DISABLE_JIT */
649 #ifndef MONO_CROSS_COMPILE
651 mono_arm_have_fast_tls (void)
653 if (mini_get_debug_options ()->arm_use_fallback_tls)
655 #if (defined(HAVE_KW_THREAD) && defined(__linux__)) \
656 || defined(TARGET_ANDROID)
657 guint32* kuser_get_tls = (void*)0xffff0fe0;
658 guint32 expected [] = {0xee1d0f70, 0xe12fff1e};
660 /* Expecting mrc + bx lr in the kuser_get_tls kernel helper */
661 return memcmp (kuser_get_tls, expected, 8) == 0;
662 #elif defined(TARGET_IOS)
663 guint32 expected [] = {0x1f70ee1d, 0x0103f021, 0x0020f851, 0xbf004770};
664 /* Discard thumb bit */
665 guint32* pthread_getspecific_addr = (guint32*) ((guint32)pthread_getspecific & 0xfffffffe);
666 return memcmp ((void*)pthread_getspecific_addr, expected, 16) == 0;
674 * mono_arm_have_tls_get:
676 * Returns whether we have tls access implemented on the current
680 mono_arm_have_tls_get (void)
690 * mono_arch_get_argument_info:
691 * @csig: a method signature
692 * @param_count: the number of parameters to consider
693 * @arg_info: an array to store the result infos
695 * Gathers information on parameters such as size, alignment and
696 * padding. arg_info should be large enought to hold param_count + 1 entries.
698 * Returns the size of the activation frame.
701 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
703 int k, frame_size = 0;
704 guint32 size, align, pad;
708 t = mini_get_underlying_type (csig->ret);
709 if (MONO_TYPE_ISSTRUCT (t)) {
710 frame_size += sizeof (gpointer);
714 arg_info [0].offset = offset;
717 frame_size += sizeof (gpointer);
721 arg_info [0].size = frame_size;
723 for (k = 0; k < param_count; k++) {
724 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
726 /* ignore alignment for now */
729 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
730 arg_info [k].pad = pad;
732 arg_info [k + 1].pad = 0;
733 arg_info [k + 1].size = size;
735 arg_info [k + 1].offset = offset;
739 align = MONO_ARCH_FRAME_ALIGNMENT;
740 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
741 arg_info [k].pad = pad;
746 #define MAX_ARCH_DELEGATE_PARAMS 3
749 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
751 guint8 *code, *start;
752 GSList *unwind_ops = mono_arch_get_cie_program ();
755 start = code = mono_global_codeman_reserve (12);
757 /* Replace the this argument with the target */
758 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
759 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
760 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
762 g_assert ((code - start) <= 12);
764 mono_arch_flush_icache (start, 12);
768 size = 8 + param_count * 4;
769 start = code = mono_global_codeman_reserve (size);
771 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
772 /* slide down the arguments */
773 for (i = 0; i < param_count; ++i) {
774 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
776 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
778 g_assert ((code - start) <= size);
780 mono_arch_flush_icache (start, size);
784 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
786 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
787 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
791 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
797 * mono_arch_get_delegate_invoke_impls:
799 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
803 mono_arch_get_delegate_invoke_impls (void)
809 get_delegate_invoke_impl (&info, TRUE, 0);
810 res = g_slist_prepend (res, info);
812 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
813 get_delegate_invoke_impl (&info, FALSE, i);
814 res = g_slist_prepend (res, info);
821 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
823 guint8 *code, *start;
826 /* FIXME: Support more cases */
827 sig_ret = mini_get_underlying_type (sig->ret);
828 if (MONO_TYPE_ISSTRUCT (sig_ret))
832 static guint8* cached = NULL;
833 mono_mini_arch_lock ();
835 mono_mini_arch_unlock ();
840 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
843 start = get_delegate_invoke_impl (&info, TRUE, 0);
844 mono_tramp_info_register (info, NULL);
847 mono_mini_arch_unlock ();
850 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
853 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
855 for (i = 0; i < sig->param_count; ++i)
856 if (!mono_is_regsize_var (sig->params [i]))
859 mono_mini_arch_lock ();
860 code = cache [sig->param_count];
862 mono_mini_arch_unlock ();
867 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
868 start = mono_aot_get_trampoline (name);
872 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
873 mono_tramp_info_register (info, NULL);
875 cache [sig->param_count] = start;
876 mono_mini_arch_unlock ();
884 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
890 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
892 return (gpointer)regs [ARMREG_R0];
896 * Initialize the cpu to execute managed code.
899 mono_arch_cpu_init (void)
901 i8_align = MONO_ABI_ALIGNOF (gint64);
902 #ifdef MONO_CROSS_COMPILE
903 /* Need to set the alignment of i8 since it can different on the target */
904 #ifdef TARGET_ANDROID
906 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
912 * Initialize architecture specific code.
915 mono_arch_init (void)
917 const char *cpu_arch;
919 mono_mutex_init_recursive (&mini_arch_mutex);
920 if (mini_get_debug_options ()->soft_breakpoints) {
921 single_step_tramp = mini_get_single_step_trampoline ();
922 breakpoint_tramp = mini_get_breakpoint_trampoline ();
924 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
925 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
926 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
929 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
930 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
931 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
932 #if defined(ENABLE_GSHAREDVT)
933 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
936 #if defined(__ARM_EABI__)
937 eabi_supported = TRUE;
940 #if defined(ARM_FPU_VFP_HARD)
941 arm_fpu = MONO_ARM_FPU_VFP_HARD;
943 arm_fpu = MONO_ARM_FPU_VFP;
945 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
947 * If we're compiling with a soft float fallback and it
948 * turns out that no VFP unit is available, we need to
949 * switch to soft float. We don't do this for iOS, since
950 * iOS devices always have a VFP unit.
952 if (!mono_hwcap_arm_has_vfp)
953 arm_fpu = MONO_ARM_FPU_NONE;
956 * This environment variable can be useful in testing
957 * environments to make sure the soft float fallback
958 * works. Most ARM devices have VFP units these days, so
959 * normally soft float code would not be exercised much.
961 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
963 if (soft && !strncmp (soft, "1", 1))
964 arm_fpu = MONO_ARM_FPU_NONE;
968 v5_supported = mono_hwcap_arm_is_v5;
969 v6_supported = mono_hwcap_arm_is_v6;
970 v7_supported = mono_hwcap_arm_is_v7;
971 v7s_supported = mono_hwcap_arm_is_v7s;
973 #if defined(__APPLE__)
974 /* iOS is special-cased here because we don't yet
975 have a way to properly detect CPU features on it. */
976 thumb_supported = TRUE;
979 thumb_supported = mono_hwcap_arm_has_thumb;
980 thumb2_supported = mono_hwcap_arm_has_thumb2;
983 /* Format: armv(5|6|7[s])[-thumb[2]] */
984 cpu_arch = g_getenv ("MONO_CPU_ARCH");
986 /* Do this here so it overrides any detection. */
988 if (strncmp (cpu_arch, "armv", 4) == 0) {
989 v5_supported = cpu_arch [4] >= '5';
990 v6_supported = cpu_arch [4] >= '6';
991 v7_supported = cpu_arch [4] >= '7';
992 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
995 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
996 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
1001 * Cleanup architecture specific code.
1004 mono_arch_cleanup (void)
1009 * This function returns the optimizations supported on this cpu.
1012 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1014 /* no arm-specific optimizations yet */
1020 * This function test for all SIMD functions supported.
1022 * Returns a bitmask corresponding to all supported versions.
1026 mono_arch_cpu_enumerate_simd_versions (void)
1028 /* SIMD is currently unimplemented */
1036 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1038 if (v7s_supported) {
1052 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1054 mono_arch_is_soft_float (void)
1056 return arm_fpu == MONO_ARM_FPU_NONE;
1061 mono_arm_is_hard_float (void)
1063 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1067 is_regsize_var (MonoType *t)
1071 t = mini_get_underlying_type (t);
1078 case MONO_TYPE_FNPTR:
1080 case MONO_TYPE_OBJECT:
1081 case MONO_TYPE_STRING:
1082 case MONO_TYPE_CLASS:
1083 case MONO_TYPE_SZARRAY:
1084 case MONO_TYPE_ARRAY:
1086 case MONO_TYPE_GENERICINST:
1087 if (!mono_type_generic_inst_is_valuetype (t))
1090 case MONO_TYPE_VALUETYPE:
1097 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1102 for (i = 0; i < cfg->num_varinfo; i++) {
1103 MonoInst *ins = cfg->varinfo [i];
1104 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1107 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1110 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1113 /* we can only allocate 32 bit values */
1114 if (is_regsize_var (ins->inst_vtype)) {
1115 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1116 g_assert (i == vmv->idx);
1117 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1125 mono_arch_get_global_int_regs (MonoCompile *cfg)
1129 mono_arch_compute_omit_fp (cfg);
1132 * FIXME: Interface calls might go through a static rgctx trampoline which
1133 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1136 if (cfg->flags & MONO_CFG_HAS_CALLS)
1137 cfg->uses_rgctx_reg = TRUE;
1139 if (cfg->arch.omit_fp)
1140 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1141 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1142 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1143 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1145 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1146 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1148 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1149 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1150 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1151 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1152 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1153 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1159 * mono_arch_regalloc_cost:
1161 * Return the cost, in number of memory references, of the action of
1162 * allocating the variable VMV into a register during global register
1166 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1172 #endif /* #ifndef DISABLE_JIT */
1174 #ifndef __GNUC_PREREQ
1175 #define __GNUC_PREREQ(maj, min) (0)
1179 mono_arch_flush_icache (guint8 *code, gint size)
1181 #if defined(__native_client__)
1182 // For Native Client we don't have to flush i-cache here,
1183 // as it's being done by dyncode interface.
1186 #ifdef MONO_CROSS_COMPILE
1188 sys_icache_invalidate (code, size);
1189 #elif __GNUC_PREREQ(4, 3)
1190 __builtin___clear_cache (code, code + size);
1191 #elif __GNUC_PREREQ(4, 1)
1192 __clear_cache (code, code + size);
1193 #elif defined(PLATFORM_ANDROID)
1194 const int syscall = 0xf0002;
1202 : "r" (code), "r" (code + size), "r" (syscall)
1203 : "r0", "r1", "r7", "r2"
1206 __asm __volatile ("mov r0, %0\n"
1209 "swi 0x9f0002 @ sys_cacheflush"
1211 : "r" (code), "r" (code + size), "r" (0)
1212 : "r0", "r1", "r3" );
1214 #endif /* !__native_client__ */
1219 /* Passed/returned in an ireg */
1221 /* Passed/returned in a pair of iregs */
1223 /* Passed on the stack */
1225 /* First word in r3, second word on the stack */
1227 /* FP value passed in either an ireg or a vfp reg */
1230 RegTypeStructByAddr,
1231 /* gsharedvt argument passed by addr in greg */
1232 RegTypeGSharedVtInReg,
1233 /* gsharedvt argument passed by addr on stack */
1234 RegTypeGSharedVtOnStack,
1240 guint16 vtsize; /* in param area */
1248 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1253 guint32 stack_usage;
1254 /* The index of the vret arg in the argument list for RegTypeStructByAddr */
1264 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1267 if (*gr > ARMREG_R3) {
1269 ainfo->offset = *stack_size;
1270 ainfo->reg = ARMREG_SP; /* in the caller */
1271 ainfo->storage = RegTypeBase;
1274 ainfo->storage = RegTypeGeneral;
1281 split = i8_align == 4;
1286 if (*gr == ARMREG_R3 && split) {
1287 /* first word in r3 and the second on the stack */
1288 ainfo->offset = *stack_size;
1289 ainfo->reg = ARMREG_SP; /* in the caller */
1290 ainfo->storage = RegTypeBaseGen;
1292 } else if (*gr >= ARMREG_R3) {
1293 if (eabi_supported) {
1294 /* darwin aligns longs to 4 byte only */
1295 if (i8_align == 8) {
1300 ainfo->offset = *stack_size;
1301 ainfo->reg = ARMREG_SP; /* in the caller */
1302 ainfo->storage = RegTypeBase;
1305 if (eabi_supported) {
1306 if (i8_align == 8 && ((*gr) & 1))
1309 ainfo->storage = RegTypeIRegPair;
1318 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1321 * If we're calling a function like this:
1323 * void foo(float a, double b, float c)
1325 * We pass a in s0 and b in d1. That leaves us
1326 * with s1 being unused. The armhf ABI recognizes
1327 * this and requires register assignment to then
1328 * use that for the next single-precision arg,
1329 * i.e. c in this example. So float_spare either
1330 * tells us which reg to use for the next single-
1331 * precision arg, or it's -1, meaning use *fpr.
1333 * Note that even though most of the JIT speaks
1334 * double-precision, fpr represents single-
1335 * precision registers.
1337 * See parts 5.5 and 6.1.2 of the AAPCS for how
1341 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1342 ainfo->storage = RegTypeFP;
1346 * If we're passing a double-precision value
1347 * and *fpr is odd (e.g. it's s1, s3, ...)
1348 * we need to use the next even register. So
1349 * we mark the current *fpr as a spare that
1350 * can be used for the next single-precision
1354 *float_spare = *fpr;
1359 * At this point, we have an even register
1360 * so we assign that and move along.
1364 } else if (*float_spare >= 0) {
1366 * We're passing a single-precision value
1367 * and it looks like a spare single-
1368 * precision register is available. Let's
1372 ainfo->reg = *float_spare;
1376 * If we hit this branch, we're passing a
1377 * single-precision value and we can simply
1378 * use the next available register.
1386 * We've exhausted available floating point
1387 * regs, so pass the rest on the stack.
1395 ainfo->offset = *stack_size;
1396 ainfo->reg = ARMREG_SP;
1397 ainfo->storage = RegTypeBase;
1404 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1408 MonoClassField *field;
1409 MonoType *ftype, *prev_ftype = NULL;
1412 klass = mono_class_from_mono_type (t);
1414 while ((field = mono_class_get_fields (klass, &iter))) {
1415 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1417 ftype = mono_field_get_type (field);
1418 ftype = mini_get_underlying_type (ftype);
1420 if (MONO_TYPE_ISSTRUCT (ftype)) {
1421 int nested_nfields, nested_esize;
1423 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1425 if (nested_esize == 4)
1426 ftype = &mono_defaults.single_class->byval_arg;
1428 ftype = &mono_defaults.double_class->byval_arg;
1429 if (prev_ftype && prev_ftype->type != ftype->type)
1432 nfields += nested_nfields;
1434 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1436 if (prev_ftype && prev_ftype->type != ftype->type)
1442 if (nfields == 0 || nfields > 4)
1444 *out_nfields = nfields;
1445 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1450 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1452 guint i, gr, fpr, pstart;
1454 int n = sig->hasthis + sig->param_count;
1458 guint32 stack_size = 0;
1460 gboolean is_pinvoke = sig->pinvoke;
1461 gboolean vtype_retaddr = FALSE;
1464 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1466 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1473 t = mini_get_underlying_type (sig->ret);
1484 case MONO_TYPE_FNPTR:
1485 case MONO_TYPE_CLASS:
1486 case MONO_TYPE_OBJECT:
1487 case MONO_TYPE_SZARRAY:
1488 case MONO_TYPE_ARRAY:
1489 case MONO_TYPE_STRING:
1490 cinfo->ret.storage = RegTypeGeneral;
1491 cinfo->ret.reg = ARMREG_R0;
1495 cinfo->ret.storage = RegTypeIRegPair;
1496 cinfo->ret.reg = ARMREG_R0;
1500 cinfo->ret.storage = RegTypeFP;
1502 if (t->type == MONO_TYPE_R4)
1503 cinfo->ret.size = 4;
1505 cinfo->ret.size = 8;
1507 if (IS_HARD_FLOAT) {
1508 cinfo->ret.reg = ARM_VFP_F0;
1510 cinfo->ret.reg = ARMREG_R0;
1513 case MONO_TYPE_GENERICINST:
1514 if (!mono_type_generic_inst_is_valuetype (t)) {
1515 cinfo->ret.storage = RegTypeGeneral;
1516 cinfo->ret.reg = ARMREG_R0;
1519 if (mini_is_gsharedvt_variable_type (t)) {
1520 cinfo->ret.storage = RegTypeStructByAddr;
1524 case MONO_TYPE_VALUETYPE:
1525 case MONO_TYPE_TYPEDBYREF:
1526 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1527 cinfo->ret.storage = RegTypeHFA;
1529 cinfo->ret.nregs = nfields;
1530 cinfo->ret.esize = esize;
1532 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1533 cinfo->ret.storage = RegTypeStructByVal;
1535 cinfo->ret.storage = RegTypeStructByAddr;
1539 case MONO_TYPE_MVAR:
1540 g_assert (mini_is_gsharedvt_type (t));
1541 cinfo->ret.storage = RegTypeStructByAddr;
1543 case MONO_TYPE_VOID:
1546 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1549 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1554 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1555 * the first argument, allowing 'this' to be always passed in the first arg reg.
1556 * Also do this if the first argument is a reference type, since virtual calls
1557 * are sometimes made using calli without sig->hasthis set, like in the delegate
1560 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1562 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1564 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1568 cinfo->ret.reg = gr;
1570 cinfo->vret_arg_index = 1;
1574 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1577 if (vtype_retaddr) {
1578 cinfo->ret.reg = gr;
1583 DEBUG(printf("params: %d\n", sig->param_count));
1584 for (i = pstart; i < sig->param_count; ++i) {
1585 ArgInfo *ainfo = &cinfo->args [n];
1587 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1588 /* Prevent implicit arguments and sig_cookie from
1589 being passed in registers */
1592 /* Emit the signature cookie just before the implicit arguments */
1593 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1595 DEBUG(printf("param %d: ", i));
1596 if (sig->params [i]->byref) {
1597 DEBUG(printf("byref\n"));
1598 add_general (&gr, &stack_size, ainfo, TRUE);
1602 t = mini_get_underlying_type (sig->params [i]);
1606 cinfo->args [n].size = 1;
1607 add_general (&gr, &stack_size, ainfo, TRUE);
1611 cinfo->args [n].size = 2;
1612 add_general (&gr, &stack_size, ainfo, TRUE);
1616 cinfo->args [n].size = 4;
1617 add_general (&gr, &stack_size, ainfo, TRUE);
1622 case MONO_TYPE_FNPTR:
1623 case MONO_TYPE_CLASS:
1624 case MONO_TYPE_OBJECT:
1625 case MONO_TYPE_STRING:
1626 case MONO_TYPE_SZARRAY:
1627 case MONO_TYPE_ARRAY:
1628 cinfo->args [n].size = sizeof (gpointer);
1629 add_general (&gr, &stack_size, ainfo, TRUE);
1631 case MONO_TYPE_GENERICINST:
1632 if (!mono_type_generic_inst_is_valuetype (t)) {
1633 cinfo->args [n].size = sizeof (gpointer);
1634 add_general (&gr, &stack_size, ainfo, TRUE);
1637 if (mini_is_gsharedvt_variable_type (t)) {
1638 /* gsharedvt arguments are passed by ref */
1639 g_assert (mini_is_gsharedvt_type (t));
1640 add_general (&gr, &stack_size, ainfo, TRUE);
1641 switch (ainfo->storage) {
1642 case RegTypeGeneral:
1643 ainfo->storage = RegTypeGSharedVtInReg;
1646 ainfo->storage = RegTypeGSharedVtOnStack;
1649 g_assert_not_reached ();
1654 case MONO_TYPE_TYPEDBYREF:
1655 case MONO_TYPE_VALUETYPE: {
1658 int nwords, nfields, esize;
1661 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1662 if (fpr + nfields < ARM_VFP_F16) {
1663 ainfo->storage = RegTypeHFA;
1665 ainfo->nregs = nfields;
1666 ainfo->esize = esize;
1674 if (t->type == MONO_TYPE_TYPEDBYREF) {
1675 size = sizeof (MonoTypedRef);
1676 align = sizeof (gpointer);
1678 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1680 size = mono_class_native_size (klass, &align);
1682 size = mini_type_stack_size_full (t, &align, FALSE);
1684 DEBUG(printf ("load %d bytes struct\n", size));
1687 align_size += (sizeof (gpointer) - 1);
1688 align_size &= ~(sizeof (gpointer) - 1);
1689 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1690 ainfo->storage = RegTypeStructByVal;
1691 ainfo->struct_size = size;
1692 /* FIXME: align stack_size if needed */
1693 if (eabi_supported) {
1694 if (align >= 8 && (gr & 1))
1697 if (gr > ARMREG_R3) {
1699 ainfo->vtsize = nwords;
1701 int rest = ARMREG_R3 - gr + 1;
1702 int n_in_regs = rest >= nwords? nwords: rest;
1704 ainfo->size = n_in_regs;
1705 ainfo->vtsize = nwords - n_in_regs;
1708 nwords -= n_in_regs;
1710 if (sig->call_convention == MONO_CALL_VARARG)
1711 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1712 stack_size = ALIGN_TO (stack_size, align);
1713 ainfo->offset = stack_size;
1714 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1715 stack_size += nwords * sizeof (gpointer);
1721 add_general (&gr, &stack_size, ainfo, FALSE);
1727 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1729 add_general (&gr, &stack_size, ainfo, TRUE);
1735 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1737 add_general (&gr, &stack_size, ainfo, FALSE);
1740 case MONO_TYPE_MVAR:
1741 /* gsharedvt arguments are passed by ref */
1742 g_assert (mini_is_gsharedvt_type (t));
1743 add_general (&gr, &stack_size, ainfo, TRUE);
1744 switch (ainfo->storage) {
1745 case RegTypeGeneral:
1746 ainfo->storage = RegTypeGSharedVtInReg;
1749 ainfo->storage = RegTypeGSharedVtOnStack;
1752 g_assert_not_reached ();
1756 g_error ("Can't handle 0x%x", sig->params [i]->type);
1761 /* Handle the case where there are no implicit arguments */
1762 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1763 /* Prevent implicit arguments and sig_cookie from
1764 being passed in registers */
1767 /* Emit the signature cookie just before the implicit arguments */
1768 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1771 /* align stack size to 8 */
1772 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1773 stack_size = (stack_size + 7) & ~7;
1775 cinfo->stack_usage = stack_size;
1781 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1783 MonoType *callee_ret;
1787 c1 = get_call_info (NULL, caller_sig);
1788 c2 = get_call_info (NULL, callee_sig);
1791 * Tail calls with more callee stack usage than the caller cannot be supported, since
1792 * the extra stack space would be left on the stack after the tail call.
1794 res = c1->stack_usage >= c2->stack_usage;
1795 callee_ret = mini_get_underlying_type (callee_sig->ret);
1796 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1797 /* An address on the callee's stack is passed as the first argument */
1800 if (c2->stack_usage > 16 * 4)
1812 debug_omit_fp (void)
1815 return mono_debug_count ();
1822 * mono_arch_compute_omit_fp:
1824 * Determine whenever the frame pointer can be eliminated.
1827 mono_arch_compute_omit_fp (MonoCompile *cfg)
1829 MonoMethodSignature *sig;
1830 MonoMethodHeader *header;
1834 if (cfg->arch.omit_fp_computed)
1837 header = cfg->header;
1839 sig = mono_method_signature (cfg->method);
1841 if (!cfg->arch.cinfo)
1842 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1843 cinfo = cfg->arch.cinfo;
1846 * FIXME: Remove some of the restrictions.
1848 cfg->arch.omit_fp = TRUE;
1849 cfg->arch.omit_fp_computed = TRUE;
1851 if (cfg->disable_omit_fp)
1852 cfg->arch.omit_fp = FALSE;
1853 if (!debug_omit_fp ())
1854 cfg->arch.omit_fp = FALSE;
1856 if (cfg->method->save_lmf)
1857 cfg->arch.omit_fp = FALSE;
1859 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1860 cfg->arch.omit_fp = FALSE;
1861 if (header->num_clauses)
1862 cfg->arch.omit_fp = FALSE;
1863 if (cfg->param_area)
1864 cfg->arch.omit_fp = FALSE;
1865 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1866 cfg->arch.omit_fp = FALSE;
1867 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1868 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1869 cfg->arch.omit_fp = FALSE;
1870 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1871 ArgInfo *ainfo = &cinfo->args [i];
1873 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1875 * The stack offset can only be determined when the frame
1878 cfg->arch.omit_fp = FALSE;
1883 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1884 MonoInst *ins = cfg->varinfo [i];
1887 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1892 * Set var information according to the calling convention. arm version.
1893 * The locals var stuff should most likely be split in another method.
1896 mono_arch_allocate_vars (MonoCompile *cfg)
1898 MonoMethodSignature *sig;
1899 MonoMethodHeader *header;
1902 int i, offset, size, align, curinst;
1907 sig = mono_method_signature (cfg->method);
1909 if (!cfg->arch.cinfo)
1910 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1911 cinfo = cfg->arch.cinfo;
1912 sig_ret = mini_get_underlying_type (sig->ret);
1914 mono_arch_compute_omit_fp (cfg);
1916 if (cfg->arch.omit_fp)
1917 cfg->frame_reg = ARMREG_SP;
1919 cfg->frame_reg = ARMREG_FP;
1921 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1923 /* allow room for the vararg method args: void* and long/double */
1924 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1925 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1927 header = cfg->header;
1929 /* See mono_arch_get_global_int_regs () */
1930 if (cfg->flags & MONO_CFG_HAS_CALLS)
1931 cfg->uses_rgctx_reg = TRUE;
1933 if (cfg->frame_reg != ARMREG_SP)
1934 cfg->used_int_regs |= 1 << cfg->frame_reg;
1936 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1937 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1938 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1942 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1943 if (sig_ret->type != MONO_TYPE_VOID) {
1944 cfg->ret->opcode = OP_REGVAR;
1945 cfg->ret->inst_c0 = ARMREG_R0;
1948 /* local vars are at a positive offset from the stack pointer */
1950 * also note that if the function uses alloca, we use FP
1951 * to point at the local variables.
1953 offset = 0; /* linkage area */
1954 /* align the offset to 16 bytes: not sure this is needed here */
1956 //offset &= ~(8 - 1);
1958 /* add parameter area size for called functions */
1959 offset += cfg->param_area;
1962 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1965 /* allow room to save the return value */
1966 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1969 switch (cinfo->ret.storage) {
1970 case RegTypeStructByVal:
1971 cfg->ret->opcode = OP_REGOFFSET;
1972 cfg->ret->inst_basereg = cfg->frame_reg;
1973 offset += sizeof (gpointer) - 1;
1974 offset &= ~(sizeof (gpointer) - 1);
1975 cfg->ret->inst_offset = - offset;
1976 offset += sizeof(gpointer);
1979 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1980 offset = ALIGN_TO (offset, 8);
1981 cfg->ret->opcode = OP_REGOFFSET;
1982 cfg->ret->inst_basereg = cfg->frame_reg;
1983 cfg->ret->inst_offset = offset;
1987 case RegTypeStructByAddr:
1988 ins = cfg->vret_addr;
1989 offset += sizeof(gpointer) - 1;
1990 offset &= ~(sizeof(gpointer) - 1);
1991 ins->inst_offset = offset;
1992 ins->opcode = OP_REGOFFSET;
1993 ins->inst_basereg = cfg->frame_reg;
1994 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1995 printf ("vret_addr =");
1996 mono_print_ins (cfg->vret_addr);
1998 offset += sizeof(gpointer);
2004 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
2005 if (cfg->arch.seq_point_info_var) {
2008 ins = cfg->arch.seq_point_info_var;
2012 offset += align - 1;
2013 offset &= ~(align - 1);
2014 ins->opcode = OP_REGOFFSET;
2015 ins->inst_basereg = cfg->frame_reg;
2016 ins->inst_offset = offset;
2019 ins = cfg->arch.ss_trigger_page_var;
2022 offset += align - 1;
2023 offset &= ~(align - 1);
2024 ins->opcode = OP_REGOFFSET;
2025 ins->inst_basereg = cfg->frame_reg;
2026 ins->inst_offset = offset;
2030 if (cfg->arch.seq_point_read_var) {
2033 ins = cfg->arch.seq_point_read_var;
2037 offset += align - 1;
2038 offset &= ~(align - 1);
2039 ins->opcode = OP_REGOFFSET;
2040 ins->inst_basereg = cfg->frame_reg;
2041 ins->inst_offset = offset;
2044 ins = cfg->arch.seq_point_ss_method_var;
2047 offset += align - 1;
2048 offset &= ~(align - 1);
2049 ins->opcode = OP_REGOFFSET;
2050 ins->inst_basereg = cfg->frame_reg;
2051 ins->inst_offset = offset;
2054 ins = cfg->arch.seq_point_bp_method_var;
2057 offset += align - 1;
2058 offset &= ~(align - 1);
2059 ins->opcode = OP_REGOFFSET;
2060 ins->inst_basereg = cfg->frame_reg;
2061 ins->inst_offset = offset;
2065 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
2066 /* Allocate a temporary used by the atomic ops */
2070 /* Allocate a local slot to hold the sig cookie address */
2071 offset += align - 1;
2072 offset &= ~(align - 1);
2073 cfg->arch.atomic_tmp_offset = offset;
2076 cfg->arch.atomic_tmp_offset = -1;
2079 cfg->locals_min_stack_offset = offset;
2081 curinst = cfg->locals_start;
2082 for (i = curinst; i < cfg->num_varinfo; ++i) {
2085 ins = cfg->varinfo [i];
2086 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
2089 t = ins->inst_vtype;
2090 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
2093 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
2094 * pinvoke wrappers when they call functions returning structure */
2095 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2096 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
2100 size = mono_type_size (t, &align);
2102 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2103 * since it loads/stores misaligned words, which don't do the right thing.
2105 if (align < 4 && size >= 4)
2107 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2108 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2109 offset += align - 1;
2110 offset &= ~(align - 1);
2111 ins->opcode = OP_REGOFFSET;
2112 ins->inst_offset = offset;
2113 ins->inst_basereg = cfg->frame_reg;
2115 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2118 cfg->locals_max_stack_offset = offset;
2122 ins = cfg->args [curinst];
2123 if (ins->opcode != OP_REGVAR) {
2124 ins->opcode = OP_REGOFFSET;
2125 ins->inst_basereg = cfg->frame_reg;
2126 offset += sizeof (gpointer) - 1;
2127 offset &= ~(sizeof (gpointer) - 1);
2128 ins->inst_offset = offset;
2129 offset += sizeof (gpointer);
2134 if (sig->call_convention == MONO_CALL_VARARG) {
2138 /* Allocate a local slot to hold the sig cookie address */
2139 offset += align - 1;
2140 offset &= ~(align - 1);
2141 cfg->sig_cookie = offset;
2145 for (i = 0; i < sig->param_count; ++i) {
2146 ainfo = cinfo->args + i;
2148 ins = cfg->args [curinst];
2150 switch (ainfo->storage) {
2152 offset = ALIGN_TO (offset, 8);
2153 ins->opcode = OP_REGOFFSET;
2154 ins->inst_basereg = cfg->frame_reg;
2155 /* These arguments are saved to the stack in the prolog */
2156 ins->inst_offset = offset;
2157 if (cfg->verbose_level >= 2)
2158 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2166 if (ins->opcode != OP_REGVAR) {
2167 ins->opcode = OP_REGOFFSET;
2168 ins->inst_basereg = cfg->frame_reg;
2169 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2171 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2172 * since it loads/stores misaligned words, which don't do the right thing.
2174 if (align < 4 && size >= 4)
2176 /* The code in the prolog () stores words when storing vtypes received in a register */
2177 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2179 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2180 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2181 offset += align - 1;
2182 offset &= ~(align - 1);
2183 ins->inst_offset = offset;
2189 /* align the offset to 8 bytes */
2190 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2191 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2196 cfg->stack_offset = offset;
2200 mono_arch_create_vars (MonoCompile *cfg)
2202 MonoMethodSignature *sig;
2206 sig = mono_method_signature (cfg->method);
2208 if (!cfg->arch.cinfo)
2209 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2210 cinfo = cfg->arch.cinfo;
2212 if (IS_HARD_FLOAT) {
2213 for (i = 0; i < 2; i++) {
2214 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2215 inst->flags |= MONO_INST_VOLATILE;
2217 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2221 if (cinfo->ret.storage == RegTypeStructByVal)
2222 cfg->ret_var_is_local = TRUE;
2224 if (cinfo->ret.storage == RegTypeStructByAddr) {
2225 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2226 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2227 printf ("vret_addr = ");
2228 mono_print_ins (cfg->vret_addr);
2232 if (cfg->gen_sdb_seq_points) {
2233 if (cfg->soft_breakpoints) {
2234 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2235 ins->flags |= MONO_INST_VOLATILE;
2236 cfg->arch.seq_point_read_var = ins;
2238 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2239 ins->flags |= MONO_INST_VOLATILE;
2240 cfg->arch.seq_point_ss_method_var = ins;
2242 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2243 ins->flags |= MONO_INST_VOLATILE;
2244 cfg->arch.seq_point_bp_method_var = ins;
2246 g_assert (!cfg->compile_aot);
2247 } else if (cfg->compile_aot) {
2248 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2249 ins->flags |= MONO_INST_VOLATILE;
2250 cfg->arch.seq_point_info_var = ins;
2252 /* Allocate a separate variable for this to save 1 load per seq point */
2253 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2254 ins->flags |= MONO_INST_VOLATILE;
2255 cfg->arch.ss_trigger_page_var = ins;
2261 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2263 MonoMethodSignature *tmp_sig;
2266 if (call->tail_call)
2269 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2272 * mono_ArgIterator_Setup assumes the signature cookie is
2273 * passed first and all the arguments which were before it are
2274 * passed on the stack after the signature. So compensate by
2275 * passing a different signature.
2277 tmp_sig = mono_metadata_signature_dup (call->signature);
2278 tmp_sig->param_count -= call->signature->sentinelpos;
2279 tmp_sig->sentinelpos = 0;
2280 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2282 sig_reg = mono_alloc_ireg (cfg);
2283 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2285 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2290 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2295 LLVMCallInfo *linfo;
2297 n = sig->param_count + sig->hasthis;
2299 cinfo = get_call_info (cfg->mempool, sig);
2301 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2304 * LLVM always uses the native ABI while we use our own ABI, the
2305 * only difference is the handling of vtypes:
2306 * - we only pass/receive them in registers in some cases, and only
2307 * in 1 or 2 integer registers.
2309 switch (cinfo->ret.storage) {
2310 case RegTypeGeneral:
2313 case RegTypeIRegPair:
2315 case RegTypeStructByAddr:
2316 /* Vtype returned using a hidden argument */
2317 linfo->ret.storage = LLVMArgVtypeRetAddr;
2318 linfo->vret_arg_index = cinfo->vret_arg_index;
2321 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2322 cfg->disable_llvm = TRUE;
2326 for (i = 0; i < n; ++i) {
2327 ainfo = cinfo->args + i;
2329 linfo->args [i].storage = LLVMArgNone;
2331 switch (ainfo->storage) {
2332 case RegTypeGeneral:
2333 case RegTypeIRegPair:
2335 case RegTypeBaseGen:
2336 linfo->args [i].storage = LLVMArgInIReg;
2338 case RegTypeStructByVal:
2339 linfo->args [i].storage = LLVMArgAsIArgs;
2340 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2343 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2344 cfg->disable_llvm = TRUE;
2354 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2357 MonoMethodSignature *sig;
2361 sig = call->signature;
2362 n = sig->param_count + sig->hasthis;
2364 cinfo = get_call_info (cfg->mempool, sig);
2366 switch (cinfo->ret.storage) {
2367 case RegTypeStructByVal:
2368 /* The JIT will transform this into a normal call */
2369 call->vret_in_reg = TRUE;
2373 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2374 * the location pointed to by it after call in emit_move_return_value ().
2376 if (!cfg->arch.vret_addr_loc) {
2377 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2378 /* Prevent it from being register allocated or optimized away */
2379 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2382 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2384 case RegTypeStructByAddr: {
2386 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2387 vtarg->sreg1 = call->vret_var->dreg;
2388 vtarg->dreg = mono_alloc_preg (cfg);
2389 MONO_ADD_INS (cfg->cbb, vtarg);
2391 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2398 for (i = 0; i < n; ++i) {
2399 ArgInfo *ainfo = cinfo->args + i;
2402 if (i >= sig->hasthis)
2403 t = sig->params [i - sig->hasthis];
2405 t = &mono_defaults.int_class->byval_arg;
2406 t = mini_get_underlying_type (t);
2408 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2409 /* Emit the signature cookie just before the implicit arguments */
2410 emit_sig_cookie (cfg, call, cinfo);
2413 in = call->args [i];
2415 switch (ainfo->storage) {
2416 case RegTypeGeneral:
2417 case RegTypeIRegPair:
2418 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2419 MONO_INST_NEW (cfg, ins, OP_MOVE);
2420 ins->dreg = mono_alloc_ireg (cfg);
2421 ins->sreg1 = in->dreg + 1;
2422 MONO_ADD_INS (cfg->cbb, ins);
2423 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2425 MONO_INST_NEW (cfg, ins, OP_MOVE);
2426 ins->dreg = mono_alloc_ireg (cfg);
2427 ins->sreg1 = in->dreg + 2;
2428 MONO_ADD_INS (cfg->cbb, ins);
2429 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2430 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2431 if (ainfo->size == 4) {
2432 if (IS_SOFT_FLOAT) {
2433 /* mono_emit_call_args () have already done the r8->r4 conversion */
2434 /* The converted value is in an int vreg */
2435 MONO_INST_NEW (cfg, ins, OP_MOVE);
2436 ins->dreg = mono_alloc_ireg (cfg);
2437 ins->sreg1 = in->dreg;
2438 MONO_ADD_INS (cfg->cbb, ins);
2439 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2443 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2444 creg = mono_alloc_ireg (cfg);
2445 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2446 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2449 if (IS_SOFT_FLOAT) {
2450 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2451 ins->dreg = mono_alloc_ireg (cfg);
2452 ins->sreg1 = in->dreg;
2453 MONO_ADD_INS (cfg->cbb, ins);
2454 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2456 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2457 ins->dreg = mono_alloc_ireg (cfg);
2458 ins->sreg1 = in->dreg;
2459 MONO_ADD_INS (cfg->cbb, ins);
2460 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2464 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2465 creg = mono_alloc_ireg (cfg);
2466 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2467 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2468 creg = mono_alloc_ireg (cfg);
2469 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2470 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2473 cfg->flags |= MONO_CFG_HAS_FPOUT;
2475 MONO_INST_NEW (cfg, ins, OP_MOVE);
2476 ins->dreg = mono_alloc_ireg (cfg);
2477 ins->sreg1 = in->dreg;
2478 MONO_ADD_INS (cfg->cbb, ins);
2480 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2483 case RegTypeStructByAddr:
2486 /* FIXME: where si the data allocated? */
2487 arg->backend.reg3 = ainfo->reg;
2488 call->used_iregs |= 1 << ainfo->reg;
2489 g_assert_not_reached ();
2492 case RegTypeStructByVal:
2493 case RegTypeGSharedVtInReg:
2494 case RegTypeGSharedVtOnStack:
2496 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2497 ins->opcode = OP_OUTARG_VT;
2498 ins->sreg1 = in->dreg;
2499 ins->klass = in->klass;
2500 ins->inst_p0 = call;
2501 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2502 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2503 mono_call_inst_add_outarg_vt (cfg, call, ins);
2504 MONO_ADD_INS (cfg->cbb, ins);
2507 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2508 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2509 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2510 if (t->type == MONO_TYPE_R8) {
2511 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2514 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2516 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2519 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2522 case RegTypeBaseGen:
2523 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2524 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
2525 MONO_INST_NEW (cfg, ins, OP_MOVE);
2526 ins->dreg = mono_alloc_ireg (cfg);
2527 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
2528 MONO_ADD_INS (cfg->cbb, ins);
2529 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2530 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2533 /* This should work for soft-float as well */
2535 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2536 creg = mono_alloc_ireg (cfg);
2537 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2538 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2539 creg = mono_alloc_ireg (cfg);
2540 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2541 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2542 cfg->flags |= MONO_CFG_HAS_FPOUT;
2544 g_assert_not_reached ();
2548 int fdreg = mono_alloc_freg (cfg);
2550 if (ainfo->size == 8) {
2551 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2552 ins->sreg1 = in->dreg;
2554 MONO_ADD_INS (cfg->cbb, ins);
2556 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2561 * Mono's register allocator doesn't speak single-precision registers that
2562 * overlap double-precision registers (i.e. armhf). So we have to work around
2563 * the register allocator and load the value from memory manually.
2565 * So we create a variable for the float argument and an instruction to store
2566 * the argument into the variable. We then store the list of these arguments
2567 * in cfg->float_args. This list is then used by emit_float_args later to
2568 * pass the arguments in the various call opcodes.
2570 * This is not very nice, and we should really try to fix the allocator.
2573 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2575 /* Make sure the instruction isn't seen as pointless and removed.
2577 float_arg->flags |= MONO_INST_VOLATILE;
2579 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2581 /* We use the dreg to look up the instruction later. The hreg is used to
2582 * emit the instruction that loads the value into the FP reg.
2584 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2585 fad->vreg = float_arg->dreg;
2586 fad->hreg = ainfo->reg;
2588 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2591 call->used_iregs |= 1 << ainfo->reg;
2592 cfg->flags |= MONO_CFG_HAS_FPOUT;
2596 g_assert_not_reached ();
2600 /* Handle the case where there are no implicit arguments */
2601 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2602 emit_sig_cookie (cfg, call, cinfo);
2604 call->call_info = cinfo;
2605 call->stack_usage = cinfo->stack_usage;
2609 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2615 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2616 ins->dreg = mono_alloc_freg (cfg);
2617 ins->sreg1 = arg->dreg;
2618 MONO_ADD_INS (cfg->cbb, ins);
2619 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2622 g_assert_not_reached ();
2628 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2630 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2632 ArgInfo *ainfo = ins->inst_p1;
2633 int ovf_size = ainfo->vtsize;
2634 int doffset = ainfo->offset;
2635 int struct_size = ainfo->struct_size;
2636 int i, soffset, dreg, tmpreg;
2638 switch (ainfo->storage) {
2639 case RegTypeGSharedVtInReg:
2641 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2643 case RegTypeGSharedVtOnStack:
2644 /* Pass by addr on stack */
2645 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2648 for (i = 0; i < ainfo->nregs; ++i) {
2649 if (ainfo->esize == 4)
2650 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2652 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2653 load->dreg = mono_alloc_freg (cfg);
2654 load->inst_basereg = src->dreg;
2655 load->inst_offset = i * ainfo->esize;
2656 MONO_ADD_INS (cfg->cbb, load);
2658 if (ainfo->esize == 4) {
2661 /* See RegTypeFP in mono_arch_emit_call () */
2662 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2663 float_arg->flags |= MONO_INST_VOLATILE;
2664 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2666 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2667 fad->vreg = float_arg->dreg;
2668 fad->hreg = ainfo->reg + i;
2670 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2672 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + i, load);
2678 for (i = 0; i < ainfo->size; ++i) {
2679 dreg = mono_alloc_ireg (cfg);
2680 switch (struct_size) {
2682 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2685 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2688 tmpreg = mono_alloc_ireg (cfg);
2689 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2690 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2691 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2692 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2693 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2694 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2695 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2698 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2701 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2702 soffset += sizeof (gpointer);
2703 struct_size -= sizeof (gpointer);
2705 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2707 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2713 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2715 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2718 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2721 if (COMPILE_LLVM (cfg)) {
2722 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2724 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2725 ins->sreg1 = val->dreg + 1;
2726 ins->sreg2 = val->dreg + 2;
2727 MONO_ADD_INS (cfg->cbb, ins);
2732 case MONO_ARM_FPU_NONE:
2733 if (ret->type == MONO_TYPE_R8) {
2736 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2737 ins->dreg = cfg->ret->dreg;
2738 ins->sreg1 = val->dreg;
2739 MONO_ADD_INS (cfg->cbb, ins);
2742 if (ret->type == MONO_TYPE_R4) {
2743 /* Already converted to an int in method_to_ir () */
2744 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2748 case MONO_ARM_FPU_VFP:
2749 case MONO_ARM_FPU_VFP_HARD:
2750 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2753 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2754 ins->dreg = cfg->ret->dreg;
2755 ins->sreg1 = val->dreg;
2756 MONO_ADD_INS (cfg->cbb, ins);
2761 g_assert_not_reached ();
2765 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2768 #endif /* #ifndef DISABLE_JIT */
2771 mono_arch_is_inst_imm (gint64 imm)
2777 MonoMethodSignature *sig;
2780 MonoType **param_types;
2784 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2788 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2791 switch (cinfo->ret.storage) {
2793 case RegTypeGeneral:
2794 case RegTypeIRegPair:
2795 case RegTypeStructByAddr:
2806 for (i = 0; i < cinfo->nargs; ++i) {
2807 ArgInfo *ainfo = &cinfo->args [i];
2810 switch (ainfo->storage) {
2811 case RegTypeGeneral:
2812 case RegTypeIRegPair:
2813 case RegTypeBaseGen:
2816 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2819 case RegTypeStructByVal:
2820 if (ainfo->size == 0)
2821 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2823 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2824 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2832 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2833 for (i = 0; i < sig->param_count; ++i) {
2834 MonoType *t = sig->params [i];
2839 t = mini_get_underlying_type (t);
2862 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2864 ArchDynCallInfo *info;
2868 cinfo = get_call_info (NULL, sig);
2870 if (!dyn_call_supported (cinfo, sig)) {
2875 info = g_new0 (ArchDynCallInfo, 1);
2876 // FIXME: Preprocess the info to speed up start_dyn_call ()
2878 info->cinfo = cinfo;
2879 info->rtype = mini_get_underlying_type (sig->ret);
2880 info->param_types = g_new0 (MonoType*, sig->param_count);
2881 for (i = 0; i < sig->param_count; ++i)
2882 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2884 return (MonoDynCallInfo*)info;
2888 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2890 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2892 g_free (ainfo->cinfo);
2897 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2899 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2900 DynCallArgs *p = (DynCallArgs*)buf;
2901 int arg_index, greg, i, j, pindex;
2902 MonoMethodSignature *sig = dinfo->sig;
2904 g_assert (buf_len >= sizeof (DynCallArgs));
2913 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2914 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2919 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2920 p->regs [greg ++] = (mgreg_t)ret;
2922 for (i = pindex; i < sig->param_count; i++) {
2923 MonoType *t = dinfo->param_types [i];
2924 gpointer *arg = args [arg_index ++];
2925 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2928 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2930 } else if (ainfo->storage == RegTypeBase) {
2931 slot = PARAM_REGS + (ainfo->offset / 4);
2932 } else if (ainfo->storage == RegTypeBaseGen) {
2933 /* slot + 1 is the first stack slot, so the code below will work */
2936 g_assert_not_reached ();
2940 p->regs [slot] = (mgreg_t)*arg;
2945 case MONO_TYPE_STRING:
2946 case MONO_TYPE_CLASS:
2947 case MONO_TYPE_ARRAY:
2948 case MONO_TYPE_SZARRAY:
2949 case MONO_TYPE_OBJECT:
2953 p->regs [slot] = (mgreg_t)*arg;
2956 p->regs [slot] = *(guint8*)arg;
2959 p->regs [slot] = *(gint8*)arg;
2962 p->regs [slot] = *(gint16*)arg;
2965 p->regs [slot] = *(guint16*)arg;
2968 p->regs [slot] = *(gint32*)arg;
2971 p->regs [slot] = *(guint32*)arg;
2975 p->regs [slot ++] = (mgreg_t)arg [0];
2976 p->regs [slot] = (mgreg_t)arg [1];
2979 p->regs [slot] = *(mgreg_t*)arg;
2982 p->regs [slot ++] = (mgreg_t)arg [0];
2983 p->regs [slot] = (mgreg_t)arg [1];
2985 case MONO_TYPE_GENERICINST:
2986 if (MONO_TYPE_IS_REFERENCE (t)) {
2987 p->regs [slot] = (mgreg_t)*arg;
2990 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2991 MonoClass *klass = mono_class_from_mono_type (t);
2992 guint8 *nullable_buf;
2995 size = mono_class_value_size (klass, NULL);
2996 nullable_buf = g_alloca (size);
2997 g_assert (nullable_buf);
2999 /* The argument pointed to by arg is either a boxed vtype or null */
3000 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
3002 arg = (gpointer*)nullable_buf;
3008 case MONO_TYPE_VALUETYPE:
3009 g_assert (ainfo->storage == RegTypeStructByVal);
3011 if (ainfo->size == 0)
3012 slot = PARAM_REGS + (ainfo->offset / 4);
3016 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
3017 p->regs [slot ++] = ((mgreg_t*)arg) [j];
3020 g_assert_not_reached ();
3026 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
3028 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
3029 MonoType *ptype = ainfo->rtype;
3030 guint8 *ret = ((DynCallArgs*)buf)->ret;
3031 mgreg_t res = ((DynCallArgs*)buf)->res;
3032 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
3034 switch (ptype->type) {
3035 case MONO_TYPE_VOID:
3036 *(gpointer*)ret = NULL;
3038 case MONO_TYPE_STRING:
3039 case MONO_TYPE_CLASS:
3040 case MONO_TYPE_ARRAY:
3041 case MONO_TYPE_SZARRAY:
3042 case MONO_TYPE_OBJECT:
3046 *(gpointer*)ret = (gpointer)res;
3052 *(guint8*)ret = res;
3055 *(gint16*)ret = res;
3058 *(guint16*)ret = res;
3061 *(gint32*)ret = res;
3064 *(guint32*)ret = res;
3068 /* This handles endianness as well */
3069 ((gint32*)ret) [0] = res;
3070 ((gint32*)ret) [1] = res2;
3072 case MONO_TYPE_GENERICINST:
3073 if (MONO_TYPE_IS_REFERENCE (ptype)) {
3074 *(gpointer*)ret = (gpointer)res;
3079 case MONO_TYPE_VALUETYPE:
3080 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
3085 *(float*)ret = *(float*)&res;
3087 case MONO_TYPE_R8: {
3094 *(double*)ret = *(double*)®s;
3098 g_assert_not_reached ();
3105 * Allow tracing to work with this interface (with an optional argument)
3109 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3113 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3114 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3115 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3116 code = emit_call_reg (code, ARMREG_R2);
3130 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3133 int save_mode = SAVE_NONE;
3135 MonoMethod *method = cfg->method;
3136 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3137 int rtype = ret_type->type;
3138 int save_offset = cfg->param_area;
3142 offset = code - cfg->native_code;
3143 /* we need about 16 instructions */
3144 if (offset > (cfg->code_size - 16 * 4)) {
3145 cfg->code_size *= 2;
3146 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3147 code = cfg->native_code + offset;
3150 case MONO_TYPE_VOID:
3151 /* special case string .ctor icall */
3152 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3153 save_mode = SAVE_ONE;
3155 save_mode = SAVE_NONE;
3159 save_mode = SAVE_TWO;
3163 save_mode = SAVE_ONE_FP;
3165 save_mode = SAVE_ONE;
3169 save_mode = SAVE_TWO_FP;
3171 save_mode = SAVE_TWO;
3173 case MONO_TYPE_GENERICINST:
3174 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3175 save_mode = SAVE_ONE;
3179 case MONO_TYPE_VALUETYPE:
3180 save_mode = SAVE_STRUCT;
3183 save_mode = SAVE_ONE;
3187 switch (save_mode) {
3189 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3190 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3191 if (enable_arguments) {
3192 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3193 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3197 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3198 if (enable_arguments) {
3199 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3203 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3204 if (enable_arguments) {
3205 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3209 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3210 if (enable_arguments) {
3211 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3215 if (enable_arguments) {
3216 /* FIXME: get the actual address */
3217 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3225 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3226 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3227 code = emit_call_reg (code, ARMREG_IP);
3229 switch (save_mode) {
3231 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3232 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3235 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3238 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3241 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3252 * The immediate field for cond branches is big enough for all reasonable methods
3254 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3255 if (0 && ins->inst_true_bb->native_offset) { \
3256 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3258 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3259 ARM_B_COND (code, (condcode), 0); \
3262 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3264 /* emit an exception if condition is fail
3266 * We assign the extra code used to throw the implicit exceptions
3267 * to cfg->bb_exit as far as the big branch handling is concerned
3269 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3271 mono_add_patch_info (cfg, code - cfg->native_code, \
3272 MONO_PATCH_INFO_EXC, exc_name); \
3273 ARM_BL_COND (code, (condcode), 0); \
3276 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3279 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3284 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3288 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3289 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3291 switch (ins->opcode) {
3294 /* Already done by an arch-independent pass */
3296 case OP_LOAD_MEMBASE:
3297 case OP_LOADI4_MEMBASE:
3299 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3300 * OP_LOAD_MEMBASE offset(basereg), reg
3302 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3303 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3304 ins->inst_basereg == last_ins->inst_destbasereg &&
3305 ins->inst_offset == last_ins->inst_offset) {
3306 if (ins->dreg == last_ins->sreg1) {
3307 MONO_DELETE_INS (bb, ins);
3310 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3311 ins->opcode = OP_MOVE;
3312 ins->sreg1 = last_ins->sreg1;
3316 * Note: reg1 must be different from the basereg in the second load
3317 * OP_LOAD_MEMBASE offset(basereg), reg1
3318 * OP_LOAD_MEMBASE offset(basereg), reg2
3320 * OP_LOAD_MEMBASE offset(basereg), reg1
3321 * OP_MOVE reg1, reg2
3323 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3324 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3325 ins->inst_basereg != last_ins->dreg &&
3326 ins->inst_basereg == last_ins->inst_basereg &&
3327 ins->inst_offset == last_ins->inst_offset) {
3329 if (ins->dreg == last_ins->dreg) {
3330 MONO_DELETE_INS (bb, ins);
3333 ins->opcode = OP_MOVE;
3334 ins->sreg1 = last_ins->dreg;
3337 //g_assert_not_reached ();
3341 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3342 * OP_LOAD_MEMBASE offset(basereg), reg
3344 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3345 * OP_ICONST reg, imm
3347 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3348 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3349 ins->inst_basereg == last_ins->inst_destbasereg &&
3350 ins->inst_offset == last_ins->inst_offset) {
3351 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3352 ins->opcode = OP_ICONST;
3353 ins->inst_c0 = last_ins->inst_imm;
3354 g_assert_not_reached (); // check this rule
3358 case OP_LOADU1_MEMBASE:
3359 case OP_LOADI1_MEMBASE:
3360 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3361 ins->inst_basereg == last_ins->inst_destbasereg &&
3362 ins->inst_offset == last_ins->inst_offset) {
3363 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3364 ins->sreg1 = last_ins->sreg1;
3367 case OP_LOADU2_MEMBASE:
3368 case OP_LOADI2_MEMBASE:
3369 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3370 ins->inst_basereg == last_ins->inst_destbasereg &&
3371 ins->inst_offset == last_ins->inst_offset) {
3372 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3373 ins->sreg1 = last_ins->sreg1;
3377 ins->opcode = OP_MOVE;
3381 if (ins->dreg == ins->sreg1) {
3382 MONO_DELETE_INS (bb, ins);
3386 * OP_MOVE sreg, dreg
3387 * OP_MOVE dreg, sreg
3389 if (last_ins && last_ins->opcode == OP_MOVE &&
3390 ins->sreg1 == last_ins->dreg &&
3391 ins->dreg == last_ins->sreg1) {
3392 MONO_DELETE_INS (bb, ins);
3401 * the branch_cc_table should maintain the order of these
3415 branch_cc_table [] = {
3429 #define ADD_NEW_INS(cfg,dest,op) do { \
3430 MONO_INST_NEW ((cfg), (dest), (op)); \
3431 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3435 map_to_reg_reg_op (int op)
3444 case OP_COMPARE_IMM:
3446 case OP_ICOMPARE_IMM:
3460 case OP_LOAD_MEMBASE:
3461 return OP_LOAD_MEMINDEX;
3462 case OP_LOADI4_MEMBASE:
3463 return OP_LOADI4_MEMINDEX;
3464 case OP_LOADU4_MEMBASE:
3465 return OP_LOADU4_MEMINDEX;
3466 case OP_LOADU1_MEMBASE:
3467 return OP_LOADU1_MEMINDEX;
3468 case OP_LOADI2_MEMBASE:
3469 return OP_LOADI2_MEMINDEX;
3470 case OP_LOADU2_MEMBASE:
3471 return OP_LOADU2_MEMINDEX;
3472 case OP_LOADI1_MEMBASE:
3473 return OP_LOADI1_MEMINDEX;
3474 case OP_STOREI1_MEMBASE_REG:
3475 return OP_STOREI1_MEMINDEX;
3476 case OP_STOREI2_MEMBASE_REG:
3477 return OP_STOREI2_MEMINDEX;
3478 case OP_STOREI4_MEMBASE_REG:
3479 return OP_STOREI4_MEMINDEX;
3480 case OP_STORE_MEMBASE_REG:
3481 return OP_STORE_MEMINDEX;
3482 case OP_STORER4_MEMBASE_REG:
3483 return OP_STORER4_MEMINDEX;
3484 case OP_STORER8_MEMBASE_REG:
3485 return OP_STORER8_MEMINDEX;
3486 case OP_STORE_MEMBASE_IMM:
3487 return OP_STORE_MEMBASE_REG;
3488 case OP_STOREI1_MEMBASE_IMM:
3489 return OP_STOREI1_MEMBASE_REG;
3490 case OP_STOREI2_MEMBASE_IMM:
3491 return OP_STOREI2_MEMBASE_REG;
3492 case OP_STOREI4_MEMBASE_IMM:
3493 return OP_STOREI4_MEMBASE_REG;
3495 g_assert_not_reached ();
3499 * Remove from the instruction list the instructions that can't be
3500 * represented with very simple instructions with no register
3504 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3506 MonoInst *ins, *temp, *last_ins = NULL;
3507 int rot_amount, imm8, low_imm;
3509 MONO_BB_FOR_EACH_INS (bb, ins) {
3511 switch (ins->opcode) {
3515 case OP_COMPARE_IMM:
3516 case OP_ICOMPARE_IMM:
3530 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3531 ADD_NEW_INS (cfg, temp, OP_ICONST);
3532 temp->inst_c0 = ins->inst_imm;
3533 temp->dreg = mono_alloc_ireg (cfg);
3534 ins->sreg2 = temp->dreg;
3535 ins->opcode = mono_op_imm_to_op (ins->opcode);
3537 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3543 if (ins->inst_imm == 1) {
3544 ins->opcode = OP_MOVE;
3547 if (ins->inst_imm == 0) {
3548 ins->opcode = OP_ICONST;
3552 imm8 = mono_is_power_of_two (ins->inst_imm);
3554 ins->opcode = OP_SHL_IMM;
3555 ins->inst_imm = imm8;
3558 ADD_NEW_INS (cfg, temp, OP_ICONST);
3559 temp->inst_c0 = ins->inst_imm;
3560 temp->dreg = mono_alloc_ireg (cfg);
3561 ins->sreg2 = temp->dreg;
3562 ins->opcode = OP_IMUL;
3568 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3569 /* ARM sets the C flag to 1 if there was _no_ overflow */
3570 ins->next->opcode = OP_COND_EXC_NC;
3573 case OP_IDIV_UN_IMM:
3575 case OP_IREM_UN_IMM:
3576 ADD_NEW_INS (cfg, temp, OP_ICONST);
3577 temp->inst_c0 = ins->inst_imm;
3578 temp->dreg = mono_alloc_ireg (cfg);
3579 ins->sreg2 = temp->dreg;
3580 ins->opcode = mono_op_imm_to_op (ins->opcode);
3582 case OP_LOCALLOC_IMM:
3583 ADD_NEW_INS (cfg, temp, OP_ICONST);
3584 temp->inst_c0 = ins->inst_imm;
3585 temp->dreg = mono_alloc_ireg (cfg);
3586 ins->sreg1 = temp->dreg;
3587 ins->opcode = OP_LOCALLOC;
3589 case OP_LOAD_MEMBASE:
3590 case OP_LOADI4_MEMBASE:
3591 case OP_LOADU4_MEMBASE:
3592 case OP_LOADU1_MEMBASE:
3593 /* we can do two things: load the immed in a register
3594 * and use an indexed load, or see if the immed can be
3595 * represented as an ad_imm + a load with a smaller offset
3596 * that fits. We just do the first for now, optimize later.
3598 if (arm_is_imm12 (ins->inst_offset))
3600 ADD_NEW_INS (cfg, temp, OP_ICONST);
3601 temp->inst_c0 = ins->inst_offset;
3602 temp->dreg = mono_alloc_ireg (cfg);
3603 ins->sreg2 = temp->dreg;
3604 ins->opcode = map_to_reg_reg_op (ins->opcode);
3606 case OP_LOADI2_MEMBASE:
3607 case OP_LOADU2_MEMBASE:
3608 case OP_LOADI1_MEMBASE:
3609 if (arm_is_imm8 (ins->inst_offset))
3611 ADD_NEW_INS (cfg, temp, OP_ICONST);
3612 temp->inst_c0 = ins->inst_offset;
3613 temp->dreg = mono_alloc_ireg (cfg);
3614 ins->sreg2 = temp->dreg;
3615 ins->opcode = map_to_reg_reg_op (ins->opcode);
3617 case OP_LOADR4_MEMBASE:
3618 case OP_LOADR8_MEMBASE:
3619 if (arm_is_fpimm8 (ins->inst_offset))
3621 low_imm = ins->inst_offset & 0x1ff;
3622 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3623 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3624 temp->inst_imm = ins->inst_offset & ~0x1ff;
3625 temp->sreg1 = ins->inst_basereg;
3626 temp->dreg = mono_alloc_ireg (cfg);
3627 ins->inst_basereg = temp->dreg;
3628 ins->inst_offset = low_imm;
3632 ADD_NEW_INS (cfg, temp, OP_ICONST);
3633 temp->inst_c0 = ins->inst_offset;
3634 temp->dreg = mono_alloc_ireg (cfg);
3636 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3637 add_ins->sreg1 = ins->inst_basereg;
3638 add_ins->sreg2 = temp->dreg;
3639 add_ins->dreg = mono_alloc_ireg (cfg);
3641 ins->inst_basereg = add_ins->dreg;
3642 ins->inst_offset = 0;
3645 case OP_STORE_MEMBASE_REG:
3646 case OP_STOREI4_MEMBASE_REG:
3647 case OP_STOREI1_MEMBASE_REG:
3648 if (arm_is_imm12 (ins->inst_offset))
3650 ADD_NEW_INS (cfg, temp, OP_ICONST);
3651 temp->inst_c0 = ins->inst_offset;
3652 temp->dreg = mono_alloc_ireg (cfg);
3653 ins->sreg2 = temp->dreg;
3654 ins->opcode = map_to_reg_reg_op (ins->opcode);
3656 case OP_STOREI2_MEMBASE_REG:
3657 if (arm_is_imm8 (ins->inst_offset))
3659 ADD_NEW_INS (cfg, temp, OP_ICONST);
3660 temp->inst_c0 = ins->inst_offset;
3661 temp->dreg = mono_alloc_ireg (cfg);
3662 ins->sreg2 = temp->dreg;
3663 ins->opcode = map_to_reg_reg_op (ins->opcode);
3665 case OP_STORER4_MEMBASE_REG:
3666 case OP_STORER8_MEMBASE_REG:
3667 if (arm_is_fpimm8 (ins->inst_offset))
3669 low_imm = ins->inst_offset & 0x1ff;
3670 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3671 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3672 temp->inst_imm = ins->inst_offset & ~0x1ff;
3673 temp->sreg1 = ins->inst_destbasereg;
3674 temp->dreg = mono_alloc_ireg (cfg);
3675 ins->inst_destbasereg = temp->dreg;
3676 ins->inst_offset = low_imm;
3680 ADD_NEW_INS (cfg, temp, OP_ICONST);
3681 temp->inst_c0 = ins->inst_offset;
3682 temp->dreg = mono_alloc_ireg (cfg);
3684 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3685 add_ins->sreg1 = ins->inst_destbasereg;
3686 add_ins->sreg2 = temp->dreg;
3687 add_ins->dreg = mono_alloc_ireg (cfg);
3689 ins->inst_destbasereg = add_ins->dreg;
3690 ins->inst_offset = 0;
3693 case OP_STORE_MEMBASE_IMM:
3694 case OP_STOREI1_MEMBASE_IMM:
3695 case OP_STOREI2_MEMBASE_IMM:
3696 case OP_STOREI4_MEMBASE_IMM:
3697 ADD_NEW_INS (cfg, temp, OP_ICONST);
3698 temp->inst_c0 = ins->inst_imm;
3699 temp->dreg = mono_alloc_ireg (cfg);
3700 ins->sreg1 = temp->dreg;
3701 ins->opcode = map_to_reg_reg_op (ins->opcode);
3703 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3706 gboolean swap = FALSE;
3710 /* Optimized away */
3715 /* Some fp compares require swapped operands */
3716 switch (ins->next->opcode) {
3718 ins->next->opcode = OP_FBLT;
3722 ins->next->opcode = OP_FBLT_UN;
3726 ins->next->opcode = OP_FBGE;
3730 ins->next->opcode = OP_FBGE_UN;
3738 ins->sreg1 = ins->sreg2;
3747 bb->last_ins = last_ins;
3748 bb->max_vreg = cfg->next_vreg;
3752 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3756 if (long_ins->opcode == OP_LNEG) {
3758 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3759 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3765 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3767 /* sreg is a float, dreg is an integer reg */
3769 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3771 ARM_TOSIZD (code, vfp_scratch1, sreg);
3773 ARM_TOUIZD (code, vfp_scratch1, sreg);
3774 ARM_FMRS (code, dreg, vfp_scratch1);
3775 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3779 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3780 else if (size == 2) {
3781 ARM_SHL_IMM (code, dreg, dreg, 16);
3782 ARM_SHR_IMM (code, dreg, dreg, 16);
3786 ARM_SHL_IMM (code, dreg, dreg, 24);
3787 ARM_SAR_IMM (code, dreg, dreg, 24);
3788 } else if (size == 2) {
3789 ARM_SHL_IMM (code, dreg, dreg, 16);
3790 ARM_SAR_IMM (code, dreg, dreg, 16);
3797 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3799 /* sreg is a float, dreg is an integer reg */
3801 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3803 ARM_TOSIZS (code, vfp_scratch1, sreg);
3805 ARM_TOUIZS (code, vfp_scratch1, sreg);
3806 ARM_FMRS (code, dreg, vfp_scratch1);
3807 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3811 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3812 else if (size == 2) {
3813 ARM_SHL_IMM (code, dreg, dreg, 16);
3814 ARM_SHR_IMM (code, dreg, dreg, 16);
3818 ARM_SHL_IMM (code, dreg, dreg, 24);
3819 ARM_SAR_IMM (code, dreg, dreg, 24);
3820 } else if (size == 2) {
3821 ARM_SHL_IMM (code, dreg, dreg, 16);
3822 ARM_SAR_IMM (code, dreg, dreg, 16);
3828 #endif /* #ifndef DISABLE_JIT */
3830 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3833 emit_thunk (guint8 *code, gconstpointer target)
3837 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3838 if (thumb_supported)
3839 ARM_BX (code, ARMREG_IP);
3841 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3842 *(guint32*)code = (guint32)target;
3844 mono_arch_flush_icache (p, code - p);
3848 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3850 MonoJitInfo *ji = NULL;
3851 MonoThunkJitInfo *info;
3854 guint8 *orig_target;
3855 guint8 *target_thunk;
3858 domain = mono_domain_get ();
3862 * This can be called multiple times during JITting,
3863 * save the current position in cfg->arch to avoid
3864 * doing a O(n^2) search.
3866 if (!cfg->arch.thunks) {
3867 cfg->arch.thunks = cfg->thunks;
3868 cfg->arch.thunks_size = cfg->thunk_area;
3870 thunks = cfg->arch.thunks;
3871 thunks_size = cfg->arch.thunks_size;
3873 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3874 g_assert_not_reached ();
3877 g_assert (*(guint32*)thunks == 0);
3878 emit_thunk (thunks, target);
3879 arm_patch (code, thunks);
3881 cfg->arch.thunks += THUNK_SIZE;
3882 cfg->arch.thunks_size -= THUNK_SIZE;
3884 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3886 info = mono_jit_info_get_thunk_info (ji);
3889 thunks = (guint8*)ji->code_start + info->thunks_offset;
3890 thunks_size = info->thunks_size;
3892 orig_target = mono_arch_get_call_target (code + 4);
3894 mono_mini_arch_lock ();
3896 target_thunk = NULL;
3897 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3898 /* The call already points to a thunk, because of trampolines etc. */
3899 target_thunk = orig_target;
3901 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3902 if (((guint32*)p) [0] == 0) {
3906 } else if (((guint32*)p) [2] == (guint32)target) {
3907 /* Thunk already points to target */
3914 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
3916 if (!target_thunk) {
3917 mono_mini_arch_unlock ();
3918 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3919 g_assert_not_reached ();
3922 emit_thunk (target_thunk, target);
3923 arm_patch (code, target_thunk);
3924 mono_arch_flush_icache (code, 4);
3926 mono_mini_arch_unlock ();
3931 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3933 guint32 *code32 = (void*)code;
3934 guint32 ins = *code32;
3935 guint32 prim = (ins >> 25) & 7;
3936 guint32 tval = GPOINTER_TO_UINT (target);
3938 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3939 if (prim == 5) { /* 101b */
3940 /* the diff starts 8 bytes from the branch opcode */
3941 gint diff = target - code - 8;
3943 gint tmask = 0xffffffff;
3944 if (tval & 1) { /* entering thumb mode */
3945 diff = target - 1 - code - 8;
3946 g_assert (thumb_supported);
3947 tbits = 0xf << 28; /* bl->blx bit pattern */
3948 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3949 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3953 tmask = ~(1 << 24); /* clear the link bit */
3954 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3959 if (diff <= 33554431) {
3961 ins = (ins & 0xff000000) | diff;
3963 *code32 = ins | tbits;
3967 /* diff between 0 and -33554432 */
3968 if (diff >= -33554432) {
3970 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3972 *code32 = ins | tbits;
3977 handle_thunk (cfg, domain, code, target);
3981 #ifdef USE_JUMP_TABLES
3983 gpointer *jte = mono_jumptable_get_entry (code);
3985 jte [0] = (gpointer) target;
3989 * The alternative call sequences looks like this:
3991 * ldr ip, [pc] // loads the address constant
3992 * b 1f // jumps around the constant
3993 * address constant embedded in the code
3998 * There are two cases for patching:
3999 * a) at the end of method emission: in this case code points to the start
4000 * of the call sequence
4001 * b) during runtime patching of the call site: in this case code points
4002 * to the mov pc, ip instruction
4004 * We have to handle also the thunk jump code sequence:
4008 * address constant // execution never reaches here
4010 if ((ins & 0x0ffffff0) == 0x12fff10) {
4011 /* Branch and exchange: the address is constructed in a reg
4012 * We can patch BX when the code sequence is the following:
4013 * ldr ip, [pc, #0] ; 0x8
4020 guint8 *emit = (guint8*)ccode;
4021 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4023 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4024 ARM_BX (emit, ARMREG_IP);
4026 /*patching from magic trampoline*/
4027 if (ins == ccode [3]) {
4028 g_assert (code32 [-4] == ccode [0]);
4029 g_assert (code32 [-3] == ccode [1]);
4030 g_assert (code32 [-1] == ccode [2]);
4031 code32 [-2] = (guint32)target;
4034 /*patching from JIT*/
4035 if (ins == ccode [0]) {
4036 g_assert (code32 [1] == ccode [1]);
4037 g_assert (code32 [3] == ccode [2]);
4038 g_assert (code32 [4] == ccode [3]);
4039 code32 [2] = (guint32)target;
4042 g_assert_not_reached ();
4043 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
4051 guint8 *emit = (guint8*)ccode;
4052 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4054 ARM_BLX_REG (emit, ARMREG_IP);
4056 g_assert (code32 [-3] == ccode [0]);
4057 g_assert (code32 [-2] == ccode [1]);
4058 g_assert (code32 [0] == ccode [2]);
4060 code32 [-1] = (guint32)target;
4063 guint32 *tmp = ccode;
4064 guint8 *emit = (guint8*)tmp;
4065 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4066 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4067 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
4068 ARM_BX (emit, ARMREG_IP);
4069 if (ins == ccode [2]) {
4070 g_assert_not_reached (); // should be -2 ...
4071 code32 [-1] = (guint32)target;
4074 if (ins == ccode [0]) {
4075 /* handles both thunk jump code and the far call sequence */
4076 code32 [2] = (guint32)target;
4079 g_assert_not_reached ();
4081 // g_print ("patched with 0x%08x\n", ins);
4086 arm_patch (guchar *code, const guchar *target)
4088 arm_patch_general (NULL, NULL, code, target);
4092 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4093 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4094 * to be used with the emit macros.
4095 * Return -1 otherwise.
4098 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4101 for (i = 0; i < 31; i+= 2) {
4102 res = (val << (32 - i)) | (val >> i);
4105 *rot_amount = i? 32 - i: 0;
4112 * Emits in code a sequence of instructions that load the value 'val'
4113 * into the dreg register. Uses at most 4 instructions.
4116 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4118 int imm8, rot_amount;
4120 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4121 /* skip the constant pool */
4127 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4128 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4129 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4130 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4133 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4135 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4139 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4141 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4143 if (val & 0xFF0000) {
4144 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4146 if (val & 0xFF000000) {
4147 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4149 } else if (val & 0xFF00) {
4150 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4151 if (val & 0xFF0000) {
4152 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4154 if (val & 0xFF000000) {
4155 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4157 } else if (val & 0xFF0000) {
4158 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4159 if (val & 0xFF000000) {
4160 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4163 //g_assert_not_reached ();
4169 mono_arm_thumb_supported (void)
4171 return thumb_supported;
4177 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4182 call = (MonoCallInst*)ins;
4183 cinfo = call->call_info;
4185 switch (cinfo->ret.storage) {
4187 MonoInst *loc = cfg->arch.vret_addr_loc;
4190 /* Load the destination address */
4191 g_assert (loc && loc->opcode == OP_REGOFFSET);
4193 if (arm_is_imm12 (loc->inst_offset)) {
4194 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4196 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4197 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4199 for (i = 0; i < cinfo->ret.nregs; ++i) {
4200 if (cinfo->ret.esize == 4)
4201 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4203 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4211 switch (ins->opcode) {
4214 case OP_FCALL_MEMBASE:
4216 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4217 if (sig_ret->type == MONO_TYPE_R4) {
4218 if (IS_HARD_FLOAT) {
4219 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4221 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4222 ARM_CVTS (code, ins->dreg, ins->dreg);
4225 if (IS_HARD_FLOAT) {
4226 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4228 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4235 case OP_RCALL_MEMBASE: {
4240 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4241 g_assert (sig_ret->type == MONO_TYPE_R4);
4242 if (IS_HARD_FLOAT) {
4243 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4245 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4246 ARM_CPYS (code, ins->dreg, ins->dreg);
4258 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4263 guint8 *code = cfg->native_code + cfg->code_len;
4264 MonoInst *last_ins = NULL;
4265 guint last_offset = 0;
4267 int imm8, rot_amount;
4269 /* we don't align basic blocks of loops on arm */
4271 if (cfg->verbose_level > 2)
4272 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4274 cpos = bb->max_offset;
4276 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4277 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4278 //g_assert (!mono_compile_aot);
4281 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4282 /* this is not thread save, but good enough */
4283 /* fixme: howto handle overflows? */
4284 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4287 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4288 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4289 (gpointer)"mono_break");
4290 code = emit_call_seq (cfg, code);
4293 MONO_BB_FOR_EACH_INS (bb, ins) {
4294 offset = code - cfg->native_code;
4296 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4298 if (offset > (cfg->code_size - max_len - 16)) {
4299 cfg->code_size *= 2;
4300 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4301 code = cfg->native_code + offset;
4303 // if (ins->cil_code)
4304 // g_print ("cil code\n");
4305 mono_debug_record_line_number (cfg, ins, offset);
4307 switch (ins->opcode) {
4308 case OP_MEMORY_BARRIER:
4310 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4311 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4315 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4317 case OP_TLS_GET_REG:
4318 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4321 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4323 case OP_TLS_SET_REG:
4324 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4326 case OP_ATOMIC_EXCHANGE_I4:
4327 case OP_ATOMIC_CAS_I4:
4328 case OP_ATOMIC_ADD_I4: {
4332 g_assert (v7_supported);
4335 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4337 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4339 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4343 g_assert (cfg->arch.atomic_tmp_offset != -1);
4344 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4346 switch (ins->opcode) {
4347 case OP_ATOMIC_EXCHANGE_I4:
4349 ARM_DMB (code, ARM_DMB_SY);
4350 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4351 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4352 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4354 ARM_B_COND (code, ARMCOND_NE, 0);
4355 arm_patch (buf [1], buf [0]);
4357 case OP_ATOMIC_CAS_I4:
4358 ARM_DMB (code, ARM_DMB_SY);
4360 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4361 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4363 ARM_B_COND (code, ARMCOND_NE, 0);
4364 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4365 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4367 ARM_B_COND (code, ARMCOND_NE, 0);
4368 arm_patch (buf [2], buf [0]);
4369 arm_patch (buf [1], code);
4371 case OP_ATOMIC_ADD_I4:
4373 ARM_DMB (code, ARM_DMB_SY);
4374 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4375 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4376 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4377 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4379 ARM_B_COND (code, ARMCOND_NE, 0);
4380 arm_patch (buf [1], buf [0]);
4383 g_assert_not_reached ();
4386 ARM_DMB (code, ARM_DMB_SY);
4387 if (tmpreg != ins->dreg)
4388 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4389 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4392 case OP_ATOMIC_LOAD_I1:
4393 case OP_ATOMIC_LOAD_U1:
4394 case OP_ATOMIC_LOAD_I2:
4395 case OP_ATOMIC_LOAD_U2:
4396 case OP_ATOMIC_LOAD_I4:
4397 case OP_ATOMIC_LOAD_U4:
4398 case OP_ATOMIC_LOAD_R4:
4399 case OP_ATOMIC_LOAD_R8: {
4400 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4401 ARM_DMB (code, ARM_DMB_SY);
4403 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4405 switch (ins->opcode) {
4406 case OP_ATOMIC_LOAD_I1:
4407 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4409 case OP_ATOMIC_LOAD_U1:
4410 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4412 case OP_ATOMIC_LOAD_I2:
4413 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4415 case OP_ATOMIC_LOAD_U2:
4416 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4418 case OP_ATOMIC_LOAD_I4:
4419 case OP_ATOMIC_LOAD_U4:
4420 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4422 case OP_ATOMIC_LOAD_R4:
4424 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4425 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4427 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4428 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4429 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4430 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4431 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4434 case OP_ATOMIC_LOAD_R8:
4435 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4436 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4440 ARM_DMB (code, ARM_DMB_SY);
4443 case OP_ATOMIC_STORE_I1:
4444 case OP_ATOMIC_STORE_U1:
4445 case OP_ATOMIC_STORE_I2:
4446 case OP_ATOMIC_STORE_U2:
4447 case OP_ATOMIC_STORE_I4:
4448 case OP_ATOMIC_STORE_U4:
4449 case OP_ATOMIC_STORE_R4:
4450 case OP_ATOMIC_STORE_R8: {
4451 ARM_DMB (code, ARM_DMB_SY);
4453 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4455 switch (ins->opcode) {
4456 case OP_ATOMIC_STORE_I1:
4457 case OP_ATOMIC_STORE_U1:
4458 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4460 case OP_ATOMIC_STORE_I2:
4461 case OP_ATOMIC_STORE_U2:
4462 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4464 case OP_ATOMIC_STORE_I4:
4465 case OP_ATOMIC_STORE_U4:
4466 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4468 case OP_ATOMIC_STORE_R4:
4470 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4471 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4473 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4474 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4475 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4476 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4477 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4480 case OP_ATOMIC_STORE_R8:
4481 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4482 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4486 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4487 ARM_DMB (code, ARM_DMB_SY);
4491 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4492 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4495 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4496 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4498 case OP_STOREI1_MEMBASE_IMM:
4499 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4500 g_assert (arm_is_imm12 (ins->inst_offset));
4501 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4503 case OP_STOREI2_MEMBASE_IMM:
4504 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4505 g_assert (arm_is_imm8 (ins->inst_offset));
4506 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4508 case OP_STORE_MEMBASE_IMM:
4509 case OP_STOREI4_MEMBASE_IMM:
4510 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4511 g_assert (arm_is_imm12 (ins->inst_offset));
4512 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4514 case OP_STOREI1_MEMBASE_REG:
4515 g_assert (arm_is_imm12 (ins->inst_offset));
4516 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4518 case OP_STOREI2_MEMBASE_REG:
4519 g_assert (arm_is_imm8 (ins->inst_offset));
4520 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4522 case OP_STORE_MEMBASE_REG:
4523 case OP_STOREI4_MEMBASE_REG:
4524 /* this case is special, since it happens for spill code after lowering has been called */
4525 if (arm_is_imm12 (ins->inst_offset)) {
4526 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4528 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4529 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4532 case OP_STOREI1_MEMINDEX:
4533 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4535 case OP_STOREI2_MEMINDEX:
4536 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4538 case OP_STORE_MEMINDEX:
4539 case OP_STOREI4_MEMINDEX:
4540 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4543 g_assert_not_reached ();
4545 case OP_LOAD_MEMINDEX:
4546 case OP_LOADI4_MEMINDEX:
4547 case OP_LOADU4_MEMINDEX:
4548 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4550 case OP_LOADI1_MEMINDEX:
4551 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4553 case OP_LOADU1_MEMINDEX:
4554 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4556 case OP_LOADI2_MEMINDEX:
4557 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4559 case OP_LOADU2_MEMINDEX:
4560 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4562 case OP_LOAD_MEMBASE:
4563 case OP_LOADI4_MEMBASE:
4564 case OP_LOADU4_MEMBASE:
4565 /* this case is special, since it happens for spill code after lowering has been called */
4566 if (arm_is_imm12 (ins->inst_offset)) {
4567 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4569 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4570 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4573 case OP_LOADI1_MEMBASE:
4574 g_assert (arm_is_imm8 (ins->inst_offset));
4575 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4577 case OP_LOADU1_MEMBASE:
4578 g_assert (arm_is_imm12 (ins->inst_offset));
4579 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4581 case OP_LOADU2_MEMBASE:
4582 g_assert (arm_is_imm8 (ins->inst_offset));
4583 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4585 case OP_LOADI2_MEMBASE:
4586 g_assert (arm_is_imm8 (ins->inst_offset));
4587 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4589 case OP_ICONV_TO_I1:
4590 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4591 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4593 case OP_ICONV_TO_I2:
4594 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4595 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4597 case OP_ICONV_TO_U1:
4598 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4600 case OP_ICONV_TO_U2:
4601 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4602 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4606 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4608 case OP_COMPARE_IMM:
4609 case OP_ICOMPARE_IMM:
4610 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4611 g_assert (imm8 >= 0);
4612 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4616 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4617 * So instead of emitting a trap, we emit a call a C function and place a
4620 //*(int*)code = 0xef9f0001;
4623 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4624 (gpointer)"mono_break");
4625 code = emit_call_seq (cfg, code);
4627 case OP_RELAXED_NOP:
4632 case OP_DUMMY_STORE:
4633 case OP_DUMMY_ICONST:
4634 case OP_DUMMY_R8CONST:
4635 case OP_NOT_REACHED:
4638 case OP_IL_SEQ_POINT:
4639 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4641 case OP_SEQ_POINT: {
4643 MonoInst *info_var = cfg->arch.seq_point_info_var;
4644 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4645 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
4646 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4647 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4649 int dreg = ARMREG_LR;
4651 if (cfg->soft_breakpoints) {
4652 g_assert (!cfg->compile_aot);
4656 * For AOT, we use one got slot per method, which will point to a
4657 * SeqPointInfo structure, containing all the information required
4658 * by the code below.
4660 if (cfg->compile_aot) {
4661 g_assert (info_var);
4662 g_assert (info_var->opcode == OP_REGOFFSET);
4663 g_assert (arm_is_imm12 (info_var->inst_offset));
4666 if (!cfg->soft_breakpoints) {
4668 * Read from the single stepping trigger page. This will cause a
4669 * SIGSEGV when single stepping is enabled.
4670 * We do this _before_ the breakpoint, so single stepping after
4671 * a breakpoint is hit will step to the next IL offset.
4673 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4676 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4677 if (cfg->soft_breakpoints) {
4678 /* Load the address of the sequence point trigger variable. */
4681 g_assert (var->opcode == OP_REGOFFSET);
4682 g_assert (arm_is_imm12 (var->inst_offset));
4683 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4685 /* Read the value and check whether it is non-zero. */
4686 ARM_LDR_IMM (code, dreg, dreg, 0);
4687 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4689 /* Load the address of the sequence point method. */
4690 var = ss_method_var;
4692 g_assert (var->opcode == OP_REGOFFSET);
4693 g_assert (arm_is_imm12 (var->inst_offset));
4694 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4696 /* Call it conditionally. */
4697 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4699 if (cfg->compile_aot) {
4700 /* Load the trigger page addr from the variable initialized in the prolog */
4701 var = ss_trigger_page_var;
4703 g_assert (var->opcode == OP_REGOFFSET);
4704 g_assert (arm_is_imm12 (var->inst_offset));
4705 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4707 #ifdef USE_JUMP_TABLES
4708 gpointer *jte = mono_jumptable_add_entry ();
4709 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4710 jte [0] = ss_trigger_page;
4712 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4714 *(int*)code = (int)ss_trigger_page;
4718 ARM_LDR_IMM (code, dreg, dreg, 0);
4722 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4724 if (cfg->soft_breakpoints) {
4725 /* Load the address of the breakpoint method into ip. */
4726 var = bp_method_var;
4728 g_assert (var->opcode == OP_REGOFFSET);
4729 g_assert (arm_is_imm12 (var->inst_offset));
4730 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4733 * A placeholder for a possible breakpoint inserted by
4734 * mono_arch_set_breakpoint ().
4737 } else if (cfg->compile_aot) {
4738 guint32 offset = code - cfg->native_code;
4741 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4742 /* Add the offset */
4743 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4744 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4745 if (arm_is_imm12 ((int)val)) {
4746 ARM_LDR_IMM (code, dreg, dreg, val);
4748 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4750 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4752 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4753 g_assert (!(val & 0xFF000000));
4755 ARM_LDR_IMM (code, dreg, dreg, 0);
4757 /* What is faster, a branch or a load ? */
4758 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4759 /* The breakpoint instruction */
4760 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4763 * A placeholder for a possible breakpoint inserted by
4764 * mono_arch_set_breakpoint ().
4766 for (i = 0; i < 4; ++i)
4771 * Add an additional nop so skipping the bp doesn't cause the ip to point
4772 * to another IL offset.
4780 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4783 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4787 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4790 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4791 g_assert (imm8 >= 0);
4792 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4796 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4797 g_assert (imm8 >= 0);
4798 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4802 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4803 g_assert (imm8 >= 0);
4804 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4807 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4808 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4810 case OP_IADD_OVF_UN:
4811 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4812 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4815 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4816 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4818 case OP_ISUB_OVF_UN:
4819 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4820 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4822 case OP_ADD_OVF_CARRY:
4823 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4824 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4826 case OP_ADD_OVF_UN_CARRY:
4827 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4828 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4830 case OP_SUB_OVF_CARRY:
4831 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4832 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4834 case OP_SUB_OVF_UN_CARRY:
4835 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4836 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4840 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4843 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4844 g_assert (imm8 >= 0);
4845 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4848 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4852 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4856 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4857 g_assert (imm8 >= 0);
4858 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4862 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4863 g_assert (imm8 >= 0);
4864 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4866 case OP_ARM_RSBS_IMM:
4867 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4868 g_assert (imm8 >= 0);
4869 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4871 case OP_ARM_RSC_IMM:
4872 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4873 g_assert (imm8 >= 0);
4874 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4877 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4881 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4882 g_assert (imm8 >= 0);
4883 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4886 g_assert (v7s_supported);
4887 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4890 g_assert (v7s_supported);
4891 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4894 g_assert (v7s_supported);
4895 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4896 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4899 g_assert (v7s_supported);
4900 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4901 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4905 g_assert_not_reached ();
4907 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4911 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4912 g_assert (imm8 >= 0);
4913 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4916 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4920 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4921 g_assert (imm8 >= 0);
4922 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4925 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4930 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4931 else if (ins->dreg != ins->sreg1)
4932 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4935 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4940 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4941 else if (ins->dreg != ins->sreg1)
4942 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4945 case OP_ISHR_UN_IMM:
4947 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4948 else if (ins->dreg != ins->sreg1)
4949 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4952 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4955 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4958 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4961 if (ins->dreg == ins->sreg2)
4962 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4964 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4967 g_assert_not_reached ();
4970 /* FIXME: handle ovf/ sreg2 != dreg */
4971 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4972 /* FIXME: MUL doesn't set the C/O flags on ARM */
4974 case OP_IMUL_OVF_UN:
4975 /* FIXME: handle ovf/ sreg2 != dreg */
4976 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4977 /* FIXME: MUL doesn't set the C/O flags on ARM */
4980 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4983 /* Load the GOT offset */
4984 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4985 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4987 *(gpointer*)code = NULL;
4989 /* Load the value from the GOT */
4990 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4992 case OP_OBJC_GET_SELECTOR:
4993 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4994 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4996 *(gpointer*)code = NULL;
4998 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
5000 case OP_ICONV_TO_I4:
5001 case OP_ICONV_TO_U4:
5003 if (ins->dreg != ins->sreg1)
5004 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5007 int saved = ins->sreg2;
5008 if (ins->sreg2 == ARM_LSW_REG) {
5009 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
5012 if (ins->sreg1 != ARM_LSW_REG)
5013 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
5014 if (saved != ARM_MSW_REG)
5015 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
5019 if (IS_VFP && ins->dreg != ins->sreg1)
5020 ARM_CPYD (code, ins->dreg, ins->sreg1);
5023 if (IS_VFP && ins->dreg != ins->sreg1)
5024 ARM_CPYS (code, ins->dreg, ins->sreg1);
5026 case OP_MOVE_F_TO_I4:
5028 ARM_FMRS (code, ins->dreg, ins->sreg1);
5030 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5031 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5032 ARM_FMRS (code, ins->dreg, vfp_scratch1);
5033 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5036 case OP_MOVE_I4_TO_F:
5038 ARM_FMSR (code, ins->dreg, ins->sreg1);
5040 ARM_FMSR (code, ins->dreg, ins->sreg1);
5041 ARM_CVTS (code, ins->dreg, ins->dreg);
5044 case OP_FCONV_TO_R4:
5047 ARM_CVTD (code, ins->dreg, ins->sreg1);
5049 ARM_CVTD (code, ins->dreg, ins->sreg1);
5050 ARM_CVTS (code, ins->dreg, ins->dreg);
5055 MonoCallInst *call = (MonoCallInst*)ins;
5058 * The stack looks like the following:
5059 * <caller argument area>
5062 * <callee argument area>
5063 * Need to copy the arguments from the callee argument area to
5064 * the caller argument area, and pop the frame.
5066 if (call->stack_usage) {
5067 int i, prev_sp_offset = 0;
5069 /* Compute size of saved registers restored below */
5071 prev_sp_offset = 2 * 4;
5073 prev_sp_offset = 1 * 4;
5074 for (i = 0; i < 16; ++i) {
5075 if (cfg->used_int_regs & (1 << i))
5076 prev_sp_offset += 4;
5079 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5081 /* Copy arguments on the stack to our argument area */
5082 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5083 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5084 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5089 * Keep in sync with mono_arch_emit_epilog
5091 g_assert (!cfg->method->save_lmf);
5093 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5095 if (cfg->used_int_regs)
5096 ARM_POP (code, cfg->used_int_regs);
5097 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5099 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5102 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5103 if (cfg->compile_aot) {
5104 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5106 *(gpointer*)code = NULL;
5108 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5110 code = mono_arm_patchable_b (code, ARMCOND_AL);
5111 cfg->thunk_area += THUNK_SIZE;
5116 /* ensure ins->sreg1 is not NULL */
5117 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5120 g_assert (cfg->sig_cookie < 128);
5121 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5122 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5132 call = (MonoCallInst*)ins;
5135 code = emit_float_args (cfg, call, code, &max_len, &offset);
5137 if (ins->flags & MONO_INST_HAS_METHOD)
5138 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5140 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5141 code = emit_call_seq (cfg, code);
5142 ins->flags |= MONO_INST_GC_CALLSITE;
5143 ins->backend.pc_offset = code - cfg->native_code;
5144 code = emit_move_return_value (cfg, ins, code);
5151 case OP_VOIDCALL_REG:
5154 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5156 code = emit_call_reg (code, ins->sreg1);
5157 ins->flags |= MONO_INST_GC_CALLSITE;
5158 ins->backend.pc_offset = code - cfg->native_code;
5159 code = emit_move_return_value (cfg, ins, code);
5161 case OP_FCALL_MEMBASE:
5162 case OP_RCALL_MEMBASE:
5163 case OP_LCALL_MEMBASE:
5164 case OP_VCALL_MEMBASE:
5165 case OP_VCALL2_MEMBASE:
5166 case OP_VOIDCALL_MEMBASE:
5167 case OP_CALL_MEMBASE: {
5168 g_assert (ins->sreg1 != ARMREG_LR);
5169 call = (MonoCallInst*)ins;
5172 code = emit_float_args (cfg, call, code, &max_len, &offset);
5173 if (!arm_is_imm12 (ins->inst_offset))
5174 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5175 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5176 if (!arm_is_imm12 (ins->inst_offset))
5177 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5179 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5180 ins->flags |= MONO_INST_GC_CALLSITE;
5181 ins->backend.pc_offset = code - cfg->native_code;
5182 code = emit_move_return_value (cfg, ins, code);
5185 case OP_GENERIC_CLASS_INIT: {
5186 static int byte_offset = -1;
5187 static guint8 bitmask;
5191 if (byte_offset < 0)
5192 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5194 g_assert (arm_is_imm8 (byte_offset));
5195 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5196 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5197 g_assert (imm8 >= 0);
5198 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5199 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5201 ARM_B_COND (code, ARMCOND_NE, 0);
5203 /* Uninitialized case */
5204 g_assert (ins->sreg1 == ARMREG_R0);
5206 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5207 (gpointer)"mono_generic_class_init");
5208 code = emit_call_seq (cfg, code);
5210 /* Initialized case */
5211 arm_patch (jump, code);
5215 /* round the size to 8 bytes */
5216 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
5217 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
5218 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5219 /* memzero the area: dreg holds the size, sp is the pointer */
5220 if (ins->flags & MONO_INST_INIT) {
5221 guint8 *start_loop, *branch_to_cond;
5222 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5223 branch_to_cond = code;
5226 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5227 arm_patch (branch_to_cond, code);
5228 /* decrement by 4 and set flags */
5229 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5230 ARM_B_COND (code, ARMCOND_GE, 0);
5231 arm_patch (code - 4, start_loop);
5233 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5234 if (cfg->param_area)
5235 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5240 MonoInst *var = cfg->dyn_call_var;
5242 g_assert (var->opcode == OP_REGOFFSET);
5243 g_assert (arm_is_imm12 (var->inst_offset));
5245 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5246 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5248 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5250 /* Save args buffer */
5251 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5253 /* Set stack slots using R0 as scratch reg */
5254 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5255 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5256 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5257 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5260 /* Set argument registers */
5261 for (i = 0; i < PARAM_REGS; ++i)
5262 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5265 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5266 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5269 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5270 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5271 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5275 if (ins->sreg1 != ARMREG_R0)
5276 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5277 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5278 (gpointer)"mono_arch_throw_exception");
5279 code = emit_call_seq (cfg, code);
5283 if (ins->sreg1 != ARMREG_R0)
5284 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5285 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5286 (gpointer)"mono_arch_rethrow_exception");
5287 code = emit_call_seq (cfg, code);
5290 case OP_START_HANDLER: {
5291 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5294 /* Reserve a param area, see filter-stack.exe */
5295 if (cfg->param_area) {
5296 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5297 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5299 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5300 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5304 if (arm_is_imm12 (spvar->inst_offset)) {
5305 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5307 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5308 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5312 case OP_ENDFILTER: {
5313 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5316 /* Free the param area */
5317 if (cfg->param_area) {
5318 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5319 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5321 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5322 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5326 if (ins->sreg1 != ARMREG_R0)
5327 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5328 if (arm_is_imm12 (spvar->inst_offset)) {
5329 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5331 g_assert (ARMREG_IP != spvar->inst_basereg);
5332 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5333 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5335 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5338 case OP_ENDFINALLY: {
5339 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5342 /* Free the param area */
5343 if (cfg->param_area) {
5344 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5345 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5347 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5348 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5352 if (arm_is_imm12 (spvar->inst_offset)) {
5353 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5355 g_assert (ARMREG_IP != spvar->inst_basereg);
5356 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5357 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5359 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5362 case OP_CALL_HANDLER:
5363 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5364 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5365 cfg->thunk_area += THUNK_SIZE;
5366 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5369 if (ins->dreg != ARMREG_R0)
5370 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5374 ins->inst_c0 = code - cfg->native_code;
5377 /*if (ins->inst_target_bb->native_offset) {
5379 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5381 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5382 code = mono_arm_patchable_b (code, ARMCOND_AL);
5386 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5390 * In the normal case we have:
5391 * ldr pc, [pc, ins->sreg1 << 2]
5394 * ldr lr, [pc, ins->sreg1 << 2]
5396 * After follows the data.
5397 * FIXME: add aot support.
5399 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5400 #ifdef USE_JUMP_TABLES
5402 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5403 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5404 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5408 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5409 if (offset + max_len > (cfg->code_size - 16)) {
5410 cfg->code_size += max_len;
5411 cfg->code_size *= 2;
5412 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5413 code = cfg->native_code + offset;
5415 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5417 code += 4 * GPOINTER_TO_INT (ins->klass);
5422 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5423 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5427 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5428 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5432 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5433 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5437 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5438 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5442 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5443 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5446 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5447 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5450 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5451 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5454 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5455 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5458 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5459 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5462 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5463 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5465 case OP_COND_EXC_EQ:
5466 case OP_COND_EXC_NE_UN:
5467 case OP_COND_EXC_LT:
5468 case OP_COND_EXC_LT_UN:
5469 case OP_COND_EXC_GT:
5470 case OP_COND_EXC_GT_UN:
5471 case OP_COND_EXC_GE:
5472 case OP_COND_EXC_GE_UN:
5473 case OP_COND_EXC_LE:
5474 case OP_COND_EXC_LE_UN:
5475 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5477 case OP_COND_EXC_IEQ:
5478 case OP_COND_EXC_INE_UN:
5479 case OP_COND_EXC_ILT:
5480 case OP_COND_EXC_ILT_UN:
5481 case OP_COND_EXC_IGT:
5482 case OP_COND_EXC_IGT_UN:
5483 case OP_COND_EXC_IGE:
5484 case OP_COND_EXC_IGE_UN:
5485 case OP_COND_EXC_ILE:
5486 case OP_COND_EXC_ILE_UN:
5487 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5490 case OP_COND_EXC_IC:
5491 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5493 case OP_COND_EXC_OV:
5494 case OP_COND_EXC_IOV:
5495 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5497 case OP_COND_EXC_NC:
5498 case OP_COND_EXC_INC:
5499 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5501 case OP_COND_EXC_NO:
5502 case OP_COND_EXC_INO:
5503 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5515 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5518 /* floating point opcodes */
5520 if (cfg->compile_aot) {
5521 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5523 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5525 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5528 /* FIXME: we can optimize the imm load by dealing with part of
5529 * the displacement in LDFD (aligning to 512).
5531 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5532 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5536 if (cfg->compile_aot) {
5537 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5539 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5542 ARM_CVTS (code, ins->dreg, ins->dreg);
5544 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5545 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5547 ARM_CVTS (code, ins->dreg, ins->dreg);
5550 case OP_STORER8_MEMBASE_REG:
5551 /* This is generated by the local regalloc pass which runs after the lowering pass */
5552 if (!arm_is_fpimm8 (ins->inst_offset)) {
5553 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5554 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5555 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5557 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5560 case OP_LOADR8_MEMBASE:
5561 /* This is generated by the local regalloc pass which runs after the lowering pass */
5562 if (!arm_is_fpimm8 (ins->inst_offset)) {
5563 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5564 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5565 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5567 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5570 case OP_STORER4_MEMBASE_REG:
5571 g_assert (arm_is_fpimm8 (ins->inst_offset));
5573 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5575 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5576 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5577 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5578 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5581 case OP_LOADR4_MEMBASE:
5583 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5585 g_assert (arm_is_fpimm8 (ins->inst_offset));
5586 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5587 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5588 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5589 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5592 case OP_ICONV_TO_R_UN: {
5593 g_assert_not_reached ();
5596 case OP_ICONV_TO_R4:
5598 ARM_FMSR (code, ins->dreg, ins->sreg1);
5599 ARM_FSITOS (code, ins->dreg, ins->dreg);
5601 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5602 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5603 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5604 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5605 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5608 case OP_ICONV_TO_R8:
5609 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5610 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5611 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5612 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5616 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5617 if (sig_ret->type == MONO_TYPE_R4) {
5619 g_assert (!IS_HARD_FLOAT);
5620 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5622 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5625 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5629 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5631 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5635 case OP_FCONV_TO_I1:
5636 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5638 case OP_FCONV_TO_U1:
5639 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5641 case OP_FCONV_TO_I2:
5642 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5644 case OP_FCONV_TO_U2:
5645 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5647 case OP_FCONV_TO_I4:
5649 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5651 case OP_FCONV_TO_U4:
5653 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5655 case OP_FCONV_TO_I8:
5656 case OP_FCONV_TO_U8:
5657 g_assert_not_reached ();
5658 /* Implemented as helper calls */
5660 case OP_LCONV_TO_R_UN:
5661 g_assert_not_reached ();
5662 /* Implemented as helper calls */
5664 case OP_LCONV_TO_OVF_I4_2: {
5665 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5667 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5670 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5671 high_bit_not_set = code;
5672 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5674 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5675 valid_negative = code;
5676 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5677 invalid_negative = code;
5678 ARM_B_COND (code, ARMCOND_AL, 0);
5680 arm_patch (high_bit_not_set, code);
5682 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5683 valid_positive = code;
5684 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5686 arm_patch (invalid_negative, code);
5687 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5689 arm_patch (valid_negative, code);
5690 arm_patch (valid_positive, code);
5692 if (ins->dreg != ins->sreg1)
5693 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5697 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5700 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5703 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5706 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5709 ARM_NEGD (code, ins->dreg, ins->sreg1);
5713 g_assert_not_reached ();
5717 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5723 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5728 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5731 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5732 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5736 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5739 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5740 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5744 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5747 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5748 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5749 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5753 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5756 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5757 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5761 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5764 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5765 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5766 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5770 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5773 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5774 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5778 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5781 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5782 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5786 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5789 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5790 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5793 /* ARM FPA flags table:
5794 * N Less than ARMCOND_MI
5795 * Z Equal ARMCOND_EQ
5796 * C Greater Than or Equal ARMCOND_CS
5797 * V Unordered ARMCOND_VS
5800 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5803 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5806 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5809 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5810 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5816 g_assert_not_reached ();
5820 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5822 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5823 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5824 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5828 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5829 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5834 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5835 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5837 #ifdef USE_JUMP_TABLES
5839 gpointer *jte = mono_jumptable_add_entries (2);
5840 jte [0] = GUINT_TO_POINTER (0xffffffff);
5841 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5842 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5843 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5846 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5847 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5849 *(guint32*)code = 0xffffffff;
5851 *(guint32*)code = 0x7fefffff;
5854 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5856 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5857 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5859 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5860 ARM_CPYD (code, ins->dreg, ins->sreg1);
5862 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5863 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5868 case OP_RCONV_TO_I1:
5869 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5871 case OP_RCONV_TO_U1:
5872 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5874 case OP_RCONV_TO_I2:
5875 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5877 case OP_RCONV_TO_U2:
5878 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5880 case OP_RCONV_TO_I4:
5881 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5883 case OP_RCONV_TO_U4:
5884 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5886 case OP_RCONV_TO_R4:
5888 if (ins->dreg != ins->sreg1)
5889 ARM_CPYS (code, ins->dreg, ins->sreg1);
5891 case OP_RCONV_TO_R8:
5893 ARM_CVTS (code, ins->dreg, ins->sreg1);
5896 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5899 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5902 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5905 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5908 ARM_NEGS (code, ins->dreg, ins->sreg1);
5912 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5915 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5916 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5920 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5923 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5924 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5928 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5931 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5932 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5933 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5937 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5940 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5941 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5945 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5948 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5949 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5950 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5954 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5957 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5958 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5962 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5965 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5966 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5970 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5973 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5974 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5977 case OP_GC_LIVENESS_DEF:
5978 case OP_GC_LIVENESS_USE:
5979 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5980 ins->backend.pc_offset = code - cfg->native_code;
5982 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5983 ins->backend.pc_offset = code - cfg->native_code;
5984 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5986 case OP_GC_SAFE_POINT: {
5987 #if defined (USE_COOP_GC)
5988 const char *polling_func = NULL;
5991 polling_func = "mono_threads_state_poll";
5992 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5993 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5995 ARM_B_COND (code, ARMCOND_EQ, 0);
5996 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5997 code = emit_call_seq (cfg, code);
5998 arm_patch (buf [0], code);
6004 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6005 g_assert_not_reached ();
6008 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
6009 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
6010 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6011 g_assert_not_reached ();
6017 last_offset = offset;
6020 cfg->code_len = code - cfg->native_code;
6023 #endif /* DISABLE_JIT */
6026 mono_arch_register_lowlevel_calls (void)
6028 /* The signature doesn't matter */
6029 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
6030 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
6032 #ifndef MONO_CROSS_COMPILE
6033 if (mono_arm_have_tls_get ()) {
6034 if (mono_arm_have_fast_tls ()) {
6035 mono_register_jit_icall (mono_fast_get_tls_key, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
6036 mono_register_jit_icall (mono_fast_set_tls_key, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
6038 mono_tramp_info_register (
6039 mono_tramp_info_create (
6041 (guint8*)mono_fast_get_tls_key,
6042 (guint8*)mono_fast_get_tls_key_end - (guint8*)mono_fast_get_tls_key,
6044 mono_arch_get_cie_program ()
6048 mono_tramp_info_register (
6049 mono_tramp_info_create (
6051 (guint8*)mono_fast_set_tls_key,
6052 (guint8*)mono_fast_set_tls_key_end - (guint8*)mono_fast_set_tls_key,
6054 mono_arch_get_cie_program ()
6059 g_warning ("No fast tls on device. Using fallbacks.");
6060 mono_register_jit_icall (mono_fallback_get_tls_key, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
6061 mono_register_jit_icall (mono_fallback_set_tls_key, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
6067 #define patch_lis_ori(ip,val) do {\
6068 guint16 *__lis_ori = (guint16*)(ip); \
6069 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
6070 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
6074 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6076 unsigned char *ip = ji->ip.i + code;
6078 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6082 case MONO_PATCH_INFO_SWITCH: {
6083 #ifdef USE_JUMP_TABLES
6084 gpointer *jt = mono_jumptable_get_entry (ip);
6086 gpointer *jt = (gpointer*)(ip + 8);
6089 /* jt is the inlined jump table, 2 instructions after ip
6090 * In the normal case we store the absolute addresses,
6091 * otherwise the displacements.
6093 for (i = 0; i < ji->data.table->table_size; i++)
6094 jt [i] = code + (int)ji->data.table->table [i];
6097 case MONO_PATCH_INFO_IP:
6098 g_assert_not_reached ();
6099 patch_lis_ori (ip, ip);
6101 case MONO_PATCH_INFO_METHOD_REL:
6102 g_assert_not_reached ();
6103 *((gpointer *)(ip)) = target;
6105 case MONO_PATCH_INFO_METHODCONST:
6106 case MONO_PATCH_INFO_CLASS:
6107 case MONO_PATCH_INFO_IMAGE:
6108 case MONO_PATCH_INFO_FIELD:
6109 case MONO_PATCH_INFO_VTABLE:
6110 case MONO_PATCH_INFO_IID:
6111 case MONO_PATCH_INFO_SFLDA:
6112 case MONO_PATCH_INFO_LDSTR:
6113 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6114 case MONO_PATCH_INFO_LDTOKEN:
6115 g_assert_not_reached ();
6116 /* from OP_AOTCONST : lis + ori */
6117 patch_lis_ori (ip, target);
6119 case MONO_PATCH_INFO_R4:
6120 case MONO_PATCH_INFO_R8:
6121 g_assert_not_reached ();
6122 *((gconstpointer *)(ip + 2)) = target;
6124 case MONO_PATCH_INFO_EXC_NAME:
6125 g_assert_not_reached ();
6126 *((gconstpointer *)(ip + 1)) = target;
6128 case MONO_PATCH_INFO_NONE:
6129 case MONO_PATCH_INFO_BB_OVF:
6130 case MONO_PATCH_INFO_EXC_OVF:
6131 /* everything is dealt with at epilog output time */
6134 arm_patch_general (cfg, domain, ip, target);
6142 * Stack frame layout:
6144 * ------------------- fp
6145 * MonoLMF structure or saved registers
6146 * -------------------
6148 * -------------------
6150 * -------------------
6151 * optional 8 bytes for tracing
6152 * -------------------
6153 * param area size is cfg->param_area
6154 * ------------------- sp
6157 mono_arch_emit_prolog (MonoCompile *cfg)
6159 MonoMethod *method = cfg->method;
6161 MonoMethodSignature *sig;
6163 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6168 int prev_sp_offset, reg_offset;
6170 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6173 sig = mono_method_signature (method);
6174 cfg->code_size = 256 + sig->param_count * 64;
6175 code = cfg->native_code = g_malloc (cfg->code_size);
6177 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6179 alloc_size = cfg->stack_offset;
6185 * The iphone uses R7 as the frame pointer, and it points at the saved
6190 * We can't use r7 as a frame pointer since it points into the middle of
6191 * the frame, so we keep using our own frame pointer.
6192 * FIXME: Optimize this.
6194 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6195 prev_sp_offset += 8; /* r7 and lr */
6196 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6197 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6198 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6201 if (!method->save_lmf) {
6203 /* No need to push LR again */
6204 if (cfg->used_int_regs)
6205 ARM_PUSH (code, cfg->used_int_regs);
6207 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6208 prev_sp_offset += 4;
6210 for (i = 0; i < 16; ++i) {
6211 if (cfg->used_int_regs & (1 << i))
6212 prev_sp_offset += 4;
6214 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6216 for (i = 0; i < 16; ++i) {
6217 if ((cfg->used_int_regs & (1 << i))) {
6218 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6219 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6224 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6225 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6227 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6228 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6231 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6232 ARM_PUSH (code, 0x5ff0);
6233 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6234 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6236 for (i = 0; i < 16; ++i) {
6237 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6238 /* The original r7 is saved at the start */
6239 if (!(iphone_abi && i == ARMREG_R7))
6240 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6244 g_assert (reg_offset == 4 * 10);
6245 pos += sizeof (MonoLMF) - (4 * 10);
6249 orig_alloc_size = alloc_size;
6250 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6251 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6252 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6253 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6256 /* the stack used in the pushed regs */
6257 if (prev_sp_offset & 4)
6259 cfg->stack_usage = alloc_size;
6261 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6262 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6264 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6265 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6267 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6269 if (cfg->frame_reg != ARMREG_SP) {
6270 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6271 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6273 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6274 prev_sp_offset += alloc_size;
6276 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6277 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6279 /* compute max_offset in order to use short forward jumps
6280 * we could skip do it on arm because the immediate displacement
6281 * for jumps is large enough, it may be useful later for constant pools
6284 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6285 MonoInst *ins = bb->code;
6286 bb->max_offset = max_offset;
6288 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6291 MONO_BB_FOR_EACH_INS (bb, ins)
6292 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6295 /* store runtime generic context */
6296 if (cfg->rgctx_var) {
6297 MonoInst *ins = cfg->rgctx_var;
6299 g_assert (ins->opcode == OP_REGOFFSET);
6301 if (arm_is_imm12 (ins->inst_offset)) {
6302 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6304 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6305 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6309 /* load arguments allocated to register from the stack */
6312 cinfo = get_call_info (NULL, sig);
6314 if (cinfo->ret.storage == RegTypeStructByAddr) {
6315 ArgInfo *ainfo = &cinfo->ret;
6316 inst = cfg->vret_addr;
6317 g_assert (arm_is_imm12 (inst->inst_offset));
6318 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6321 if (sig->call_convention == MONO_CALL_VARARG) {
6322 ArgInfo *cookie = &cinfo->sig_cookie;
6324 /* Save the sig cookie address */
6325 g_assert (cookie->storage == RegTypeBase);
6327 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6328 g_assert (arm_is_imm12 (cfg->sig_cookie));
6329 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6330 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6333 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6334 ArgInfo *ainfo = cinfo->args + i;
6335 inst = cfg->args [pos];
6337 if (cfg->verbose_level > 2)
6338 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6340 if (inst->opcode == OP_REGVAR) {
6341 if (ainfo->storage == RegTypeGeneral)
6342 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6343 else if (ainfo->storage == RegTypeFP) {
6344 g_assert_not_reached ();
6345 } else if (ainfo->storage == RegTypeBase) {
6346 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6347 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6349 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6350 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6353 g_assert_not_reached ();
6355 if (cfg->verbose_level > 2)
6356 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6358 switch (ainfo->storage) {
6360 for (part = 0; part < ainfo->nregs; part ++) {
6361 if (ainfo->esize == 4)
6362 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6364 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6367 case RegTypeGeneral:
6368 case RegTypeIRegPair:
6369 case RegTypeGSharedVtInReg:
6370 switch (ainfo->size) {
6372 if (arm_is_imm12 (inst->inst_offset))
6373 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6375 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6376 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6380 if (arm_is_imm8 (inst->inst_offset)) {
6381 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6383 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6384 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6388 if (arm_is_imm12 (inst->inst_offset)) {
6389 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6391 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6392 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6394 if (arm_is_imm12 (inst->inst_offset + 4)) {
6395 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6397 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6398 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6402 if (arm_is_imm12 (inst->inst_offset)) {
6403 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6405 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6406 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6411 case RegTypeBaseGen:
6412 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6413 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6415 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6416 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6418 if (arm_is_imm12 (inst->inst_offset + 4)) {
6419 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6420 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6422 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6423 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6424 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6425 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6429 case RegTypeGSharedVtOnStack:
6430 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6431 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6433 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6434 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6437 switch (ainfo->size) {
6439 if (arm_is_imm8 (inst->inst_offset)) {
6440 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6442 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6443 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6447 if (arm_is_imm8 (inst->inst_offset)) {
6448 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6450 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6451 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6455 if (arm_is_imm12 (inst->inst_offset)) {
6456 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6458 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6459 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6461 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6462 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6464 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6465 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6467 if (arm_is_imm12 (inst->inst_offset + 4)) {
6468 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6470 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6471 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6475 if (arm_is_imm12 (inst->inst_offset)) {
6476 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6478 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6479 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6485 int imm8, rot_amount;
6487 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6488 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6489 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6491 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6493 if (ainfo->size == 8)
6494 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6496 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6499 case RegTypeStructByVal: {
6500 int doffset = inst->inst_offset;
6504 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6505 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6506 if (arm_is_imm12 (doffset)) {
6507 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6509 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6510 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6512 soffset += sizeof (gpointer);
6513 doffset += sizeof (gpointer);
6515 if (ainfo->vtsize) {
6516 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6517 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6518 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6522 case RegTypeStructByAddr:
6523 g_assert_not_reached ();
6524 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6525 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6527 g_assert_not_reached ();
6534 if (method->save_lmf)
6535 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6538 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6540 if (cfg->arch.seq_point_info_var) {
6541 MonoInst *ins = cfg->arch.seq_point_info_var;
6543 /* Initialize the variable from a GOT slot */
6544 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6545 #ifdef USE_JUMP_TABLES
6547 gpointer *jte = mono_jumptable_add_entry ();
6548 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6549 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6551 /** XXX: is it correct? */
6553 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6555 *(gpointer*)code = NULL;
6558 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6560 g_assert (ins->opcode == OP_REGOFFSET);
6562 if (arm_is_imm12 (ins->inst_offset)) {
6563 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6565 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6566 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6570 /* Initialize ss_trigger_page_var */
6571 if (!cfg->soft_breakpoints) {
6572 MonoInst *info_var = cfg->arch.seq_point_info_var;
6573 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6574 int dreg = ARMREG_LR;
6577 g_assert (info_var->opcode == OP_REGOFFSET);
6578 g_assert (arm_is_imm12 (info_var->inst_offset));
6580 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6581 /* Load the trigger page addr */
6582 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6583 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6587 if (cfg->arch.seq_point_read_var) {
6588 MonoInst *read_ins = cfg->arch.seq_point_read_var;
6589 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6590 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6591 #ifdef USE_JUMP_TABLES
6594 g_assert (read_ins->opcode == OP_REGOFFSET);
6595 g_assert (arm_is_imm12 (read_ins->inst_offset));
6596 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6597 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6598 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6599 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6601 #ifdef USE_JUMP_TABLES
6602 jte = mono_jumptable_add_entries (3);
6603 jte [0] = (gpointer)&ss_trigger_var;
6604 jte [1] = single_step_tramp;
6605 jte [2] = breakpoint_tramp;
6606 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6608 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6610 *(volatile int **)code = &ss_trigger_var;
6612 *(gpointer*)code = single_step_tramp;
6614 *(gpointer*)code = breakpoint_tramp;
6618 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6619 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
6620 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6621 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6622 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
6623 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6626 cfg->code_len = code - cfg->native_code;
6627 g_assert (cfg->code_len < cfg->code_size);
6634 mono_arch_emit_epilog (MonoCompile *cfg)
6636 MonoMethod *method = cfg->method;
6637 int pos, i, rot_amount;
6638 int max_epilog_size = 16 + 20*4;
6642 if (cfg->method->save_lmf)
6643 max_epilog_size += 128;
6645 if (mono_jit_trace_calls != NULL)
6646 max_epilog_size += 50;
6648 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6649 max_epilog_size += 50;
6651 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6652 cfg->code_size *= 2;
6653 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6654 cfg->stat_code_reallocs++;
6658 * Keep in sync with OP_JMP
6660 code = cfg->native_code + cfg->code_len;
6662 /* Save the uwind state which is needed by the out-of-line code */
6663 mono_emit_unwind_op_remember_state (cfg, code);
6665 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6666 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6670 /* Load returned vtypes into registers if needed */
6671 cinfo = cfg->arch.cinfo;
6672 switch (cinfo->ret.storage) {
6673 case RegTypeStructByVal: {
6674 MonoInst *ins = cfg->ret;
6676 if (arm_is_imm12 (ins->inst_offset)) {
6677 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6679 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6680 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6685 MonoInst *ins = cfg->ret;
6687 for (i = 0; i < cinfo->ret.nregs; ++i) {
6688 if (cinfo->ret.esize == 4)
6689 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6691 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6699 if (method->save_lmf) {
6700 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6701 /* all but r0-r3, sp and pc */
6702 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6705 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6707 /* This points to r4 inside MonoLMF->iregs */
6708 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6710 regmask = 0x9ff0; /* restore lr to pc */
6711 /* Skip caller saved registers not used by the method */
6712 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6713 regmask &= ~(1 << reg);
6718 /* Restored later */
6719 regmask &= ~(1 << ARMREG_PC);
6720 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6721 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6722 for (i = 0; i < 16; i++) {
6723 if (regmask & (1 << i))
6726 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6728 ARM_POP (code, regmask);
6730 for (i = 0; i < 16; i++) {
6731 if (regmask & (1 << i))
6732 mono_emit_unwind_op_same_value (cfg, code, i);
6734 /* Restore saved r7, restore LR to PC */
6735 /* Skip lr from the lmf */
6736 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6737 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6738 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6739 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6742 int i, nused_int_regs = 0;
6744 for (i = 0; i < 16; i++) {
6745 if (cfg->used_int_regs & (1 << i))
6749 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6750 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6752 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6753 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6756 if (cfg->frame_reg != ARMREG_SP) {
6757 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6761 /* Restore saved gregs */
6762 if (cfg->used_int_regs) {
6763 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6764 ARM_POP (code, cfg->used_int_regs);
6765 for (i = 0; i < 16; i++) {
6766 if (cfg->used_int_regs & (1 << i))
6767 mono_emit_unwind_op_same_value (cfg, code, i);
6770 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6771 /* Restore saved r7, restore LR to PC */
6772 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6774 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6775 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6779 /* Restore the unwind state to be the same as before the epilog */
6780 mono_emit_unwind_op_restore_state (cfg, code);
6782 cfg->code_len = code - cfg->native_code;
6784 g_assert (cfg->code_len < cfg->code_size);
6789 mono_arch_emit_exceptions (MonoCompile *cfg)
6791 MonoJumpInfo *patch_info;
6794 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6795 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6796 int max_epilog_size = 50;
6798 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6799 exc_throw_pos [i] = NULL;
6800 exc_throw_found [i] = 0;
6803 /* count the number of exception infos */
6806 * make sure we have enough space for exceptions
6808 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6809 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6810 i = mini_exception_id_by_name (patch_info->data.target);
6811 if (!exc_throw_found [i]) {
6812 max_epilog_size += 32;
6813 exc_throw_found [i] = TRUE;
6818 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6819 cfg->code_size *= 2;
6820 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6821 cfg->stat_code_reallocs++;
6824 code = cfg->native_code + cfg->code_len;
6826 /* add code to raise exceptions */
6827 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6828 switch (patch_info->type) {
6829 case MONO_PATCH_INFO_EXC: {
6830 MonoClass *exc_class;
6831 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6833 i = mini_exception_id_by_name (patch_info->data.target);
6834 if (exc_throw_pos [i]) {
6835 arm_patch (ip, exc_throw_pos [i]);
6836 patch_info->type = MONO_PATCH_INFO_NONE;
6839 exc_throw_pos [i] = code;
6841 arm_patch (ip, code);
6843 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6844 g_assert (exc_class);
6846 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6847 #ifdef USE_JUMP_TABLES
6849 gpointer *jte = mono_jumptable_add_entries (2);
6850 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6851 patch_info->data.name = "mono_arch_throw_corlib_exception";
6852 patch_info->ip.i = code - cfg->native_code;
6853 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6854 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6855 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6856 ARM_BLX_REG (code, ARMREG_IP);
6857 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6860 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6861 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6862 patch_info->data.name = "mono_arch_throw_corlib_exception";
6863 patch_info->ip.i = code - cfg->native_code;
6865 cfg->thunk_area += THUNK_SIZE;
6866 *(guint32*)(gpointer)code = exc_class->type_token;
6877 cfg->code_len = code - cfg->native_code;
6879 g_assert (cfg->code_len < cfg->code_size);
6883 #endif /* #ifndef DISABLE_JIT */
6886 mono_arch_finish_init (void)
6891 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6896 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6903 mono_arch_print_tree (MonoInst *tree, int arity)
6913 mono_arch_get_patch_offset (guint8 *code)
6920 mono_arch_flush_register_windows (void)
6925 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6927 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6931 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6933 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6937 mono_arch_get_cie_program (void)
6941 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6946 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6947 #define BASE_SIZE (6 * 4)
6948 #define BSEARCH_ENTRY_SIZE (4 * 4)
6949 #define CMP_SIZE (3 * 4)
6950 #define BRANCH_SIZE (1 * 4)
6951 #define CALL_SIZE (2 * 4)
6952 #define WMC_SIZE (8 * 4)
6953 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6955 #ifdef USE_JUMP_TABLES
6957 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6959 g_assert (base [index] == NULL);
6960 base [index] = value;
6963 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6965 if (arm_is_imm12 (jti * 4)) {
6966 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6968 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6969 if ((jti * 4) >> 16)
6970 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6971 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6977 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6979 guint32 delta = DISTANCE (target, code);
6981 g_assert (delta >= 0 && delta <= 0xFFF);
6982 *target = *target | delta;
6988 #ifdef ENABLE_WRONG_METHOD_CHECK
6990 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6992 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6998 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6999 gpointer fail_tramp)
7002 arminstr_t *code, *start;
7003 #ifdef USE_JUMP_TABLES
7006 gboolean large_offsets = FALSE;
7007 guint32 **constant_pool_starts;
7008 arminstr_t *vtable_target = NULL;
7009 int extra_space = 0;
7011 #ifdef ENABLE_WRONG_METHOD_CHECK
7017 #ifdef USE_JUMP_TABLES
7018 for (i = 0; i < count; ++i) {
7019 MonoIMTCheckItem *item = imt_entries [i];
7020 item->chunk_size += 4 * 16;
7021 if (!item->is_equals)
7022 imt_entries [item->check_target_idx]->compare_done = TRUE;
7023 size += item->chunk_size;
7026 constant_pool_starts = g_new0 (guint32*, count);
7028 for (i = 0; i < count; ++i) {
7029 MonoIMTCheckItem *item = imt_entries [i];
7030 if (item->is_equals) {
7031 gboolean fail_case = !item->check_target_idx && fail_tramp;
7033 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
7034 item->chunk_size += 32;
7035 large_offsets = TRUE;
7038 if (item->check_target_idx || fail_case) {
7039 if (!item->compare_done || fail_case)
7040 item->chunk_size += CMP_SIZE;
7041 item->chunk_size += BRANCH_SIZE;
7043 #ifdef ENABLE_WRONG_METHOD_CHECK
7044 item->chunk_size += WMC_SIZE;
7048 item->chunk_size += 16;
7049 large_offsets = TRUE;
7051 item->chunk_size += CALL_SIZE;
7053 item->chunk_size += BSEARCH_ENTRY_SIZE;
7054 imt_entries [item->check_target_idx]->compare_done = TRUE;
7056 size += item->chunk_size;
7060 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
7064 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7066 code = mono_domain_code_reserve (domain, size);
7069 unwind_ops = mono_arch_get_cie_program ();
7072 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
7073 for (i = 0; i < count; ++i) {
7074 MonoIMTCheckItem *item = imt_entries [i];
7075 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
7079 #ifdef USE_JUMP_TABLES
7080 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7081 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 3 * sizeof (mgreg_t));
7082 #define VTABLE_JTI 0
7083 #define IMT_METHOD_OFFSET 0
7084 #define TARGET_CODE_OFFSET 1
7085 #define JUMP_CODE_OFFSET 2
7086 #define RECORDS_PER_ENTRY 3
7087 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
7088 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
7089 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
7091 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
7092 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
7093 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
7094 set_jumptable_element (jte, VTABLE_JTI, vtable);
7096 if (large_offsets) {
7097 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7098 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
7100 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7101 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7103 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7104 vtable_target = code;
7105 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7107 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7109 for (i = 0; i < count; ++i) {
7110 MonoIMTCheckItem *item = imt_entries [i];
7111 #ifdef USE_JUMP_TABLES
7112 guint32 imt_method_jti = 0, target_code_jti = 0;
7114 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7116 gint32 vtable_offset;
7118 item->code_target = (guint8*)code;
7120 if (item->is_equals) {
7121 gboolean fail_case = !item->check_target_idx && fail_tramp;
7123 if (item->check_target_idx || fail_case) {
7124 if (!item->compare_done || fail_case) {
7125 #ifdef USE_JUMP_TABLES
7126 imt_method_jti = IMT_METHOD_JTI (i);
7127 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7130 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7132 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7134 #ifdef USE_JUMP_TABLES
7135 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7136 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7137 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7139 item->jmp_code = (guint8*)code;
7140 ARM_B_COND (code, ARMCOND_NE, 0);
7143 /*Enable the commented code to assert on wrong method*/
7144 #ifdef ENABLE_WRONG_METHOD_CHECK
7145 #ifdef USE_JUMP_TABLES
7146 imt_method_jti = IMT_METHOD_JTI (i);
7147 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7150 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7152 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7154 ARM_B_COND (code, ARMCOND_EQ, 0);
7156 /* Define this if your system is so bad that gdb is failing. */
7157 #ifdef BROKEN_DEV_ENV
7158 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7160 arm_patch (code - 1, mini_dump_bad_imt);
7164 arm_patch (cond, code);
7168 if (item->has_target_code) {
7169 /* Load target address */
7170 #ifdef USE_JUMP_TABLES
7171 target_code_jti = TARGET_CODE_JTI (i);
7172 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7173 /* Restore registers */
7174 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7175 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7177 ARM_BX (code, ARMREG_R1);
7178 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7180 target_code_ins = code;
7181 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7182 /* Save it to the fourth slot */
7183 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7184 /* Restore registers and branch */
7185 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7187 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7190 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7191 if (!arm_is_imm12 (vtable_offset)) {
7193 * We need to branch to a computed address but we don't have
7194 * a free register to store it, since IP must contain the
7195 * vtable address. So we push the two values to the stack, and
7196 * load them both using LDM.
7198 /* Compute target address */
7199 #ifdef USE_JUMP_TABLES
7200 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7201 if (vtable_offset >> 16)
7202 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7203 /* IP had vtable base. */
7204 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7205 /* Restore registers and branch */
7206 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7207 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7208 ARM_BX (code, ARMREG_IP);
7210 vtable_offset_ins = code;
7211 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7212 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7213 /* Save it to the fourth slot */
7214 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7215 /* Restore registers and branch */
7216 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7218 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7221 #ifdef USE_JUMP_TABLES
7222 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7223 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7224 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7225 ARM_BX (code, ARMREG_IP);
7227 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7228 if (large_offsets) {
7229 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7230 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7232 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7233 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7239 #ifdef USE_JUMP_TABLES
7240 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7241 target_code_jti = TARGET_CODE_JTI (i);
7242 /* Load target address */
7243 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7244 /* Restore registers */
7245 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7246 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7248 ARM_BX (code, ARMREG_R1);
7249 set_jumptable_element (jte, target_code_jti, fail_tramp);
7251 arm_patch (item->jmp_code, (guchar*)code);
7253 target_code_ins = code;
7254 /* Load target address */
7255 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7256 /* Save it to the fourth slot */
7257 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7258 /* Restore registers and branch */
7259 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7261 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7263 item->jmp_code = NULL;
7266 #ifdef USE_JUMP_TABLES
7268 set_jumptable_element (jte, imt_method_jti, item->key);
7271 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7273 /*must emit after unconditional branch*/
7274 if (vtable_target) {
7275 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7276 item->chunk_size += 4;
7277 vtable_target = NULL;
7280 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7281 constant_pool_starts [i] = code;
7283 code += extra_space;
7288 #ifdef USE_JUMP_TABLES
7289 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7290 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7291 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7292 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7293 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7295 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7296 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7298 item->jmp_code = (guint8*)code;
7299 ARM_B_COND (code, ARMCOND_HS, 0);
7305 for (i = 0; i < count; ++i) {
7306 MonoIMTCheckItem *item = imt_entries [i];
7307 if (item->jmp_code) {
7308 if (item->check_target_idx)
7309 #ifdef USE_JUMP_TABLES
7310 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7312 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7315 if (i > 0 && item->is_equals) {
7317 #ifdef USE_JUMP_TABLES
7318 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7319 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7321 arminstr_t *space_start = constant_pool_starts [i];
7322 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7323 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7331 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7332 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7337 #ifndef USE_JUMP_TABLES
7338 g_free (constant_pool_starts);
7341 mono_arch_flush_icache ((guint8*)start, size);
7342 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7343 mono_stats.imt_thunks_size += code - start;
7345 g_assert (DISTANCE (start, code) <= size);
7347 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7353 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7355 return ctx->regs [reg];
7359 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7361 ctx->regs [reg] = val;
7365 * mono_arch_get_trampolines:
7367 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7371 mono_arch_get_trampolines (gboolean aot)
7373 return mono_arm_get_exception_trampolines (aot);
7377 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7384 bp = MONO_CONTEXT_GET_BP (ctx);
7385 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7387 old_value = *lr_loc;
7388 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7391 *lr_loc = new_value;
7396 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7398 * mono_arch_set_breakpoint:
7400 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7401 * The location should contain code emitted by OP_SEQ_POINT.
7404 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7407 guint32 native_offset = ip - (guint8*)ji->code_start;
7408 MonoDebugOptions *opt = mini_get_debug_options ();
7410 if (opt->soft_breakpoints) {
7411 g_assert (!ji->from_aot);
7413 ARM_BLX_REG (code, ARMREG_LR);
7414 mono_arch_flush_icache (code - 4, 4);
7415 } else if (ji->from_aot) {
7416 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7418 g_assert (native_offset % 4 == 0);
7419 g_assert (info->bp_addrs [native_offset / 4] == 0);
7420 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7422 int dreg = ARMREG_LR;
7424 /* Read from another trigger page */
7425 #ifdef USE_JUMP_TABLES
7426 gpointer *jte = mono_jumptable_add_entry ();
7427 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7428 jte [0] = bp_trigger_page;
7430 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7432 *(int*)code = (int)bp_trigger_page;
7435 ARM_LDR_IMM (code, dreg, dreg, 0);
7437 mono_arch_flush_icache (code - 16, 16);
7440 /* This is currently implemented by emitting an SWI instruction, which
7441 * qemu/linux seems to convert to a SIGILL.
7443 *(int*)code = (0xef << 24) | 8;
7445 mono_arch_flush_icache (code - 4, 4);
7451 * mono_arch_clear_breakpoint:
7453 * Clear the breakpoint at IP.
7456 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7458 MonoDebugOptions *opt = mini_get_debug_options ();
7462 if (opt->soft_breakpoints) {
7463 g_assert (!ji->from_aot);
7466 mono_arch_flush_icache (code - 4, 4);
7467 } else if (ji->from_aot) {
7468 guint32 native_offset = ip - (guint8*)ji->code_start;
7469 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7471 g_assert (native_offset % 4 == 0);
7472 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7473 info->bp_addrs [native_offset / 4] = 0;
7475 for (i = 0; i < 4; ++i)
7478 mono_arch_flush_icache (ip, code - ip);
7483 * mono_arch_start_single_stepping:
7485 * Start single stepping.
7488 mono_arch_start_single_stepping (void)
7490 if (ss_trigger_page)
7491 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7497 * mono_arch_stop_single_stepping:
7499 * Stop single stepping.
7502 mono_arch_stop_single_stepping (void)
7504 if (ss_trigger_page)
7505 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7511 #define DBG_SIGNAL SIGBUS
7513 #define DBG_SIGNAL SIGSEGV
7517 * mono_arch_is_single_step_event:
7519 * Return whenever the machine state in SIGCTX corresponds to a single
7523 mono_arch_is_single_step_event (void *info, void *sigctx)
7525 siginfo_t *sinfo = info;
7527 if (!ss_trigger_page)
7530 /* Sometimes the address is off by 4 */
7531 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7538 * mono_arch_is_breakpoint_event:
7540 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7543 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7545 siginfo_t *sinfo = info;
7547 if (!ss_trigger_page)
7550 if (sinfo->si_signo == DBG_SIGNAL) {
7551 /* Sometimes the address is off by 4 */
7552 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7562 * mono_arch_skip_breakpoint:
7564 * See mini-amd64.c for docs.
7567 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7569 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7573 * mono_arch_skip_single_step:
7575 * See mini-amd64.c for docs.
7578 mono_arch_skip_single_step (MonoContext *ctx)
7580 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7583 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7586 * mono_arch_get_seq_point_info:
7588 * See mini-amd64.c for docs.
7591 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7596 // FIXME: Add a free function
7598 mono_domain_lock (domain);
7599 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7601 mono_domain_unlock (domain);
7604 ji = mono_jit_info_table_find (domain, (char*)code);
7607 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7609 info->ss_trigger_page = ss_trigger_page;
7610 info->bp_trigger_page = bp_trigger_page;
7612 mono_domain_lock (domain);
7613 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7615 mono_domain_unlock (domain);
7622 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7624 ext->lmf.previous_lmf = prev_lmf;
7625 /* Mark that this is a MonoLMFExt */
7626 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7627 ext->lmf.sp = (gssize)ext;
7631 * mono_arch_set_target:
7633 * Set the target architecture the JIT backend should generate code for, in the form
7634 * of a GNU target triplet. Only used in AOT mode.
7637 mono_arch_set_target (char *mtriple)
7639 /* The GNU target triple format is not very well documented */
7640 if (strstr (mtriple, "armv7")) {
7641 v5_supported = TRUE;
7642 v6_supported = TRUE;
7643 v7_supported = TRUE;
7645 if (strstr (mtriple, "armv6")) {
7646 v5_supported = TRUE;
7647 v6_supported = TRUE;
7649 if (strstr (mtriple, "armv7s")) {
7650 v7s_supported = TRUE;
7652 if (strstr (mtriple, "thumbv7s")) {
7653 v5_supported = TRUE;
7654 v6_supported = TRUE;
7655 v7_supported = TRUE;
7656 v7s_supported = TRUE;
7657 thumb_supported = TRUE;
7658 thumb2_supported = TRUE;
7660 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7661 v5_supported = TRUE;
7662 v6_supported = TRUE;
7663 thumb_supported = TRUE;
7666 if (strstr (mtriple, "gnueabi"))
7667 eabi_supported = TRUE;
7671 mono_arch_opcode_supported (int opcode)
7674 case OP_ATOMIC_ADD_I4:
7675 case OP_ATOMIC_EXCHANGE_I4:
7676 case OP_ATOMIC_CAS_I4:
7677 case OP_ATOMIC_LOAD_I1:
7678 case OP_ATOMIC_LOAD_I2:
7679 case OP_ATOMIC_LOAD_I4:
7680 case OP_ATOMIC_LOAD_U1:
7681 case OP_ATOMIC_LOAD_U2:
7682 case OP_ATOMIC_LOAD_U4:
7683 case OP_ATOMIC_STORE_I1:
7684 case OP_ATOMIC_STORE_I2:
7685 case OP_ATOMIC_STORE_I4:
7686 case OP_ATOMIC_STORE_U1:
7687 case OP_ATOMIC_STORE_U2:
7688 case OP_ATOMIC_STORE_U4:
7689 return v7_supported;
7690 case OP_ATOMIC_LOAD_R4:
7691 case OP_ATOMIC_LOAD_R8:
7692 case OP_ATOMIC_STORE_R4:
7693 case OP_ATOMIC_STORE_R8:
7694 return v7_supported && IS_VFP;
7700 #if defined(ENABLE_GSHAREDVT)
7702 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7704 #endif /* !MONOTOUCH */