mono/mini/mini-arm.c

   1 /*
   2  * mini-arm.c: ARM backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *
   8  * (C) 2003 Ximian, Inc.
   9  */
  10 #include "mini.h"
  11 #include <string.h>
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15
  16 #include "mini-arm.h"
  17 #include "inssel.h"
  18 #include "cpu-arm.h"
  19 #include "trace.h"
  20 #include "mono/arch/arm/arm-fpa-codegen.h"
  21
  22 /*
  23  * TODO:
  24  * floating point support: on ARM it is a mess, there are at least 3
  25  * different setups, each of which binary incompat with the other.
  26  * 1) FPA: old and ugly, but unfortunately what current distros use
  27  *    the double binary format has the two words swapped. 8 double registers.
  28  *    Implemented usually by kernel emulation.
  29  * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
  30  *    ugly swapped double format (I guess a softfloat-vfp exists, too, though).
  31  * 3) VFP: the new and actually sensible and useful FP support. Implemented
  32  *    in HW or kernel-emulated, requires new tools. I think this ios what symbian uses.
  33  *
  34  * The plan is to write the FPA support first. softfloat can be tested in a chroot.
  35  */
  36 int mono_exc_esp_offset = 0;
  37
  38 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
  39 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
  40 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
  41
  42 const char*
  43 mono_arch_regname (int reg) {
  44         static const char * rnames[] = {
  45                 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
  46                 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
  47                 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
  48                 "arm_pc"
  49         };
  50         if (reg >= 0 && reg < 16)
  51                 return rnames [reg];
  52         return "unknown";
  53 }
  54
  55 const char*
  56 mono_arch_fregname (int reg) {
  57         static const char * rnames[] = {
  58                 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
  59                 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
  60                 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
  61                 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
  62                 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
  63                 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
  64                 "arm_f30", "arm_f31"
  65         };
  66         if (reg >= 0 && reg < 32)
  67                 return rnames [reg];
  68         return "unknown";
  69 }
  70
  71 static guint8*
  72 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
  73 {
  74         int imm8, rot_amount;
  75         if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
  76                 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
  77                 return code;
  78         }
  79         g_assert (dreg != sreg);
  80         code = mono_arm_emit_load_imm (code, dreg, imm);
  81         ARM_ADD_REG_REG (code, dreg, dreg, sreg);
  82         return code;
  83 }
  84
  85 static guint8*
  86 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
  87 {
  88         /* we can use r0-r3, since this is called only for incoming args on the stack */
  89         if (size > sizeof (gpointer) * 4) {
  90                 guint8 *start_loop;
  91                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
  92                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
  93                 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
  94                 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
  95                 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
  96                 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
  97                 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
  98                 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
  99                 ARM_B_COND (code, ARMCOND_NE, 0);
 100                 arm_patch (code - 4, start_loop);
 101                 return code;
 102         }
 103         g_assert (arm_is_imm12 (doffset));
 104         g_assert (arm_is_imm12 (doffset + size));
 105         g_assert (arm_is_imm12 (soffset));
 106         g_assert (arm_is_imm12 (soffset + size));
 107         while (size >= 4) {
 108                 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
 109                 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
 110                 doffset += 4;
 111                 soffset += 4;
 112                 size -= 4;
 113         }
 114         g_assert (size == 0);
 115         return code;
 116 }
 117
 118 /*
 119  * mono_arch_get_argument_info:
 120  * @csig:  a method signature
 121  * @param_count: the number of parameters to consider
 122  * @arg_info: an array to store the result infos
 123  *
 124  * Gathers information on parameters such as size, alignment and
 125  * padding. arg_info should be large enought to hold param_count + 1 entries.
 126  *
 127  * Returns the size of the activation frame.
 128  */
 129 int
 130 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 131 {
 132         int k, frame_size = 0;
 133         int size, align, pad;
 134         int offset = 8;
 135
 136         if (MONO_TYPE_ISSTRUCT (csig->ret)) {
 137                 frame_size += sizeof (gpointer);
 138                 offset += 4;
 139         }
 140
 141         arg_info [0].offset = offset;
 142
 143         if (csig->hasthis) {
 144                 frame_size += sizeof (gpointer);
 145                 offset += 4;
 146         }
 147
 148         arg_info [0].size = frame_size;
 149
 150         for (k = 0; k < param_count; k++) {
 151
 152                 if (csig->pinvoke)
 153                         size = mono_type_native_stack_size (csig->params [k], &align);
 154                 else
 155                         size = mono_type_stack_size (csig->params [k], &align);
 156
 157                 /* ignore alignment for now */
 158                 align = 1;
 159
 160                 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 161                 arg_info [k].pad = pad;
 162                 frame_size += size;
 163                 arg_info [k + 1].pad = 0;
 164                 arg_info [k + 1].size = size;
 165                 offset += pad;
 166                 arg_info [k + 1].offset = offset;
 167                 offset += size;
 168         }
 169
 170         align = MONO_ARCH_FRAME_ALIGNMENT;
 171         frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 172         arg_info [k].pad = pad;
 173
 174         return frame_size;
 175 }
 176
 177 /*
 178  * Initialize the cpu to execute managed code.
 179  */
 180 void
 181 mono_arch_cpu_init (void)
 182 {
 183 }
 184
 185 /*
 186  * This function returns the optimizations supported on this cpu.
 187  */
 188 guint32
 189 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 190 {
 191         guint32 opts = 0;
 192
 193         /* no arm-specific optimizations yet */
 194         *exclude_mask = 0;
 195         return opts;
 196 }
 197
 198 static gboolean
 199 is_regsize_var (MonoType *t) {
 200         if (t->byref)
 201                 return TRUE;
 202         t = mono_type_get_underlying_type (t);
 203         switch (t->type) {
 204         case MONO_TYPE_I4:
 205         case MONO_TYPE_U4:
 206         case MONO_TYPE_I:
 207         case MONO_TYPE_U:
 208         case MONO_TYPE_PTR:
 209         case MONO_TYPE_FNPTR:
 210                 return TRUE;
 211         case MONO_TYPE_OBJECT:
 212         case MONO_TYPE_STRING:
 213         case MONO_TYPE_CLASS:
 214         case MONO_TYPE_SZARRAY:
 215         case MONO_TYPE_ARRAY:
 216                 return TRUE;
 217         case MONO_TYPE_VALUETYPE:
 218                 return FALSE;
 219         }
 220         return FALSE;
 221 }
 222
 223 GList *
 224 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 225 {
 226         GList *vars = NULL;
 227         int i;
 228
 229         for (i = 0; i < cfg->num_varinfo; i++) {
 230                 MonoInst *ins = cfg->varinfo [i];
 231                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 232
 233                 /* unused vars */
 234                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 235                         continue;
 236
 237                 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 238                         continue;
 239
 240                 /* we can only allocate 32 bit values */
 241                 if (is_regsize_var (ins->inst_vtype)) {
 242                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 243                         g_assert (i == vmv->idx);
 244                         vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
 245                 }
 246         }
 247
 248         return vars;
 249 }
 250
 251 #define USE_EXTRA_TEMPS 0
 252
 253 GList *
 254 mono_arch_get_global_int_regs (MonoCompile *cfg)
 255 {
 256         GList *regs = NULL;
 257         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
 258         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
 259         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
 260         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
 261         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
 262         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
 263         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
 264
 265         return regs;
 266 }
 267
 268 /*
 269  * mono_arch_regalloc_cost:
 270  *
 271  *  Return the cost, in number of memory references, of the action of
 272  * allocating the variable VMV into a register during global register
 273  * allocation.
 274  */
 275 guint32
 276 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 277 {
 278         /* FIXME: */
 279         return 2;
 280 }
 281
 282 void
 283 mono_arch_flush_icache (guint8 *code, gint size)
 284 {
 285         __asm __volatile ("mov r0, %0\n"
 286                         "mov r1, %1\n"
 287                         "mov r2, %2\n"
 288                         "swi 0x9f0002       @ sys_cacheflush"
 289                         : /* no outputs */
 290                         : "r" (code), "r" (code + size), "r" (0)
 291                         : "r0", "r1", "r3" );
 292
 293 }
 294
 295 #define NOT_IMPLEMENTED(x) \
 296                 g_error ("FIXME: %s is not yet implemented. (trampoline)", x);
 297
 298 enum {
 299         RegTypeGeneral,
 300         RegTypeBase,
 301         RegTypeFP,
 302         RegTypeStructByVal,
 303         RegTypeStructByAddr
 304 };
 305
 306 typedef struct {
 307         gint32  offset;
 308         guint16 vtsize; /* in param area */
 309         guint8  reg;
 310         guint8  regtype : 4; /* 0 general, 1 basereg, 2 floating point register, see RegType* */
 311         guint8  size    : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
 312 } ArgInfo;
 313
 314 typedef struct {
 315         int nargs;
 316         guint32 stack_usage;
 317         guint32 struct_ret;
 318         ArgInfo ret;
 319         ArgInfo sig_cookie;
 320         ArgInfo args [1];
 321 } CallInfo;
 322
 323 #define DEBUG(a)
 324
 325 static void inline
 326 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
 327 {
 328         if (simple) {
 329                 if (*gr > ARMREG_R3) {
 330                         ainfo->offset = *stack_size;
 331                         ainfo->reg = ARMREG_SP; /* in the caller */
 332                         ainfo->regtype = RegTypeBase;
 333                         *stack_size += 4;
 334                 } else {
 335                         ainfo->reg = *gr;
 336                 }
 337         } else {
 338                 if (*gr > ARMREG_R2) {
 339                         *stack_size += 7;
 340                         *stack_size &= ~7;
 341                         ainfo->offset = *stack_size;
 342                         ainfo->reg = ARMREG_SP; /* in the caller */
 343                         ainfo->regtype = RegTypeBase;
 344                         *stack_size += 8;
 345                 } else {
 346                         /*if ((*gr) & 1)
 347                                 (*gr) ++;*/
 348                         ainfo->reg = *gr;
 349                 }
 350                 (*gr) ++;
 351         }
 352         (*gr) ++;
 353 }
 354
 355 static CallInfo*
 356 calculate_sizes (MonoMethodSignature *sig, gboolean is_pinvoke)
 357 {
 358         guint i, gr;
 359         int n = sig->hasthis + sig->param_count;
 360         guint32 simpletype;
 361         guint32 stack_size = 0;
 362         CallInfo *cinfo = g_malloc0 (sizeof (CallInfo) + sizeof (ArgInfo) * n);
 363
 364         gr = ARMREG_R0;
 365
 366         /* FIXME: handle returning a struct */
 367         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 368                 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
 369                 cinfo->struct_ret = ARMREG_R0;
 370         }
 371
 372         n = 0;
 373         if (sig->hasthis) {
 374                 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 375                 n++;
 376         }
 377         DEBUG(printf("params: %d\n", sig->param_count));
 378         for (i = 0; i < sig->param_count; ++i) {
 379                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 380                         /* Prevent implicit arguments and sig_cookie from
 381                            being passed in registers */
 382                         gr = ARMREG_R3 + 1;
 383                         /* Emit the signature cookie just before the implicit arguments */
 384                         add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
 385                 }
 386                 DEBUG(printf("param %d: ", i));
 387                 if (sig->params [i]->byref) {
 388                         DEBUG(printf("byref\n"));
 389                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 390                         n++;
 391                         continue;
 392                 }
 393                 simpletype = mono_type_get_underlying_type (sig->params [i])->type;
 394                 switch (simpletype) {
 395                 case MONO_TYPE_BOOLEAN:
 396                 case MONO_TYPE_I1:
 397                 case MONO_TYPE_U1:
 398                         cinfo->args [n].size = 1;
 399                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 400                         n++;
 401                         break;
 402                 case MONO_TYPE_CHAR:
 403                 case MONO_TYPE_I2:
 404                 case MONO_TYPE_U2:
 405                         cinfo->args [n].size = 2;
 406                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 407                         n++;
 408                         break;
 409                 case MONO_TYPE_I4:
 410                 case MONO_TYPE_U4:
 411                         cinfo->args [n].size = 4;
 412                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 413                         n++;
 414                         break;
 415                 case MONO_TYPE_I:
 416                 case MONO_TYPE_U:
 417                 case MONO_TYPE_PTR:
 418                 case MONO_TYPE_FNPTR:
 419                 case MONO_TYPE_CLASS:
 420                 case MONO_TYPE_OBJECT:
 421                 case MONO_TYPE_STRING:
 422                 case MONO_TYPE_SZARRAY:
 423                 case MONO_TYPE_ARRAY:
 424                 case MONO_TYPE_R4:
 425                         cinfo->args [n].size = sizeof (gpointer);
 426                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 427                         n++;
 428                         break;
 429                 case MONO_TYPE_TYPEDBYREF:
 430                 case MONO_TYPE_VALUETYPE: {
 431                         gint size;
 432                         int align_size;
 433                         int nwords;
 434
 435                         if (simpletype == MONO_TYPE_TYPEDBYREF) {
 436                                 size = sizeof (MonoTypedRef);
 437                         } else {
 438                                 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
 439                                 if (is_pinvoke)
 440                                         size = mono_class_native_size (klass, NULL);
 441                                 else
 442                                         size = mono_class_value_size (klass, NULL);
 443                         }
 444                         DEBUG(printf ("load %d bytes struct\n",
 445                                       mono_class_native_size (sig->params [i]->data.klass, NULL)));
 446                         align_size = size;
 447                         nwords = 0;
 448                         align_size += (sizeof (gpointer) - 1);
 449                         align_size &= ~(sizeof (gpointer) - 1);
 450                         nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
 451                         cinfo->args [n].regtype = RegTypeStructByVal;
 452                         /* FIXME: align gr and stack_size if needed */
 453                         if (gr > ARMREG_R3) {
 454                                 cinfo->args [n].size = 0;
 455                                 cinfo->args [n].vtsize = nwords;
 456                         } else {
 457                                 int rest = ARMREG_R3 - gr + 1;
 458                                 int n_in_regs = rest >= nwords? nwords: rest;
 459                                 cinfo->args [n].size = n_in_regs;
 460                                 cinfo->args [n].vtsize = nwords - n_in_regs;
 461                                 cinfo->args [n].reg = gr;
 462                                 gr += n_in_regs;
 463                         }
 464                         cinfo->args [n].offset = stack_size;
 465                         /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
 466                         stack_size += nwords * sizeof (gpointer);
 467                         n++;
 468                         break;
 469                 }
 470                 case MONO_TYPE_U8:
 471                 case MONO_TYPE_I8:
 472                 case MONO_TYPE_R8:
 473                         cinfo->args [n].size = 8;
 474                         add_general (&gr, &stack_size, cinfo->args + n, FALSE);
 475                         n++;
 476                         break;
 477                 default:
 478                         g_error ("Can't trampoline 0x%x", sig->params [i]->type);
 479                 }
 480         }
 481
 482         {
 483                 simpletype = mono_type_get_underlying_type (sig->ret)->type;
 484                 switch (simpletype) {
 485                 case MONO_TYPE_BOOLEAN:
 486                 case MONO_TYPE_I1:
 487                 case MONO_TYPE_U1:
 488                 case MONO_TYPE_I2:
 489                 case MONO_TYPE_U2:
 490                 case MONO_TYPE_CHAR:
 491                 case MONO_TYPE_I4:
 492                 case MONO_TYPE_U4:
 493                 case MONO_TYPE_I:
 494                 case MONO_TYPE_U:
 495                 case MONO_TYPE_PTR:
 496                 case MONO_TYPE_FNPTR:
 497                 case MONO_TYPE_CLASS:
 498                 case MONO_TYPE_OBJECT:
 499                 case MONO_TYPE_SZARRAY:
 500                 case MONO_TYPE_ARRAY:
 501                 case MONO_TYPE_STRING:
 502                         cinfo->ret.reg = ARMREG_R0;
 503                         break;
 504                 case MONO_TYPE_U8:
 505                 case MONO_TYPE_I8:
 506                         cinfo->ret.reg = ARMREG_R0;
 507                         break;
 508                 case MONO_TYPE_R4:
 509                 case MONO_TYPE_R8:
 510                         cinfo->ret.reg = ARMREG_R0;
 511                         /* FIXME: cinfo->ret.reg = ???;
 512                         cinfo->ret.regtype = RegTypeFP;*/
 513                         break;
 514                 case MONO_TYPE_VALUETYPE:
 515                         break;
 516                 case MONO_TYPE_TYPEDBYREF:
 517                 case MONO_TYPE_VOID:
 518                         break;
 519                 default:
 520                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 521                 }
 522         }
 523
 524         /* align stack size to 8 */
 525         DEBUG (printf ("      stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
 526         stack_size = (stack_size + 7) & ~7;
 527
 528         cinfo->stack_usage = stack_size;
 529         return cinfo;
 530 }
 531
 532
 533 /*
 534  * Set var information according to the calling convention. arm version.
 535  * The locals var stuff should most likely be split in another method.
 536  */
 537 void
 538 mono_arch_allocate_vars (MonoCompile *m)
 539 {
 540         MonoMethodSignature *sig;
 541         MonoMethodHeader *header;
 542         MonoInst *inst;
 543         int i, offset, size, align, curinst;
 544         int frame_reg = ARMREG_FP;
 545
 546         /* FIXME: this will change when we use FP as gcc does */
 547         m->flags |= MONO_CFG_HAS_SPILLUP;
 548
 549         /* allow room for the vararg method args: void* and long/double */
 550         if (mono_jit_trace_calls != NULL && mono_trace_eval (m->method))
 551                 m->param_area = MAX (m->param_area, sizeof (gpointer)*8);
 552
 553         header = mono_method_get_header (m->method);
 554
 555         /*
 556          * We use the frame register also for any method that has
 557          * exception clauses. This way, when the handlers are called,
 558          * the code will reference local variables using the frame reg instead of
 559          * the stack pointer: if we had to restore the stack pointer, we'd
 560          * corrupt the method frames that are already on the stack (since
 561          * filters get called before stack unwinding happens) when the filter
 562          * code would call any method (this also applies to finally etc.).
 563          */
 564         if ((m->flags & MONO_CFG_HAS_ALLOCA) || header->num_clauses)
 565                 frame_reg = ARMREG_FP;
 566         m->frame_reg = frame_reg;
 567         if (frame_reg != ARMREG_SP) {
 568                 m->used_int_regs |= 1 << frame_reg;
 569         }
 570
 571         sig = mono_method_signature (m->method);
 572
 573         offset = 0;
 574         curinst = 0;
 575         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 576                 m->ret->opcode = OP_REGVAR;
 577                 m->ret->inst_c0 = ARMREG_R0;
 578         } else {
 579                 /* FIXME: handle long and FP values */
 580                 switch (mono_type_get_underlying_type (sig->ret)->type) {
 581                 case MONO_TYPE_VOID:
 582                         break;
 583                 default:
 584                         m->ret->opcode = OP_REGVAR;
 585                         m->ret->inst_c0 = ARMREG_R0;
 586                         break;
 587                 }
 588         }
 589         /* local vars are at a positive offset from the stack pointer */
 590         /*
 591          * also note that if the function uses alloca, we use FP
 592          * to point at the local variables.
 593          */
 594         offset = 0; /* linkage area */
 595         /* align the offset to 16 bytes: not sure this is needed here  */
 596         //offset += 8 - 1;
 597         //offset &= ~(8 - 1);
 598
 599         /* add parameter area size for called functions */
 600         offset += m->param_area;
 601         offset += 8 - 1;
 602         offset &= ~(8 - 1);
 603         if (m->flags & MONO_CFG_HAS_FPOUT)
 604                 offset += 8;
 605
 606         /* allow room to save the return value */
 607         if (mono_jit_trace_calls != NULL && mono_trace_eval (m->method))
 608                 offset += 8;
 609
 610         /* the MonoLMF structure is stored just below the stack pointer */
 611
 612         if (sig->call_convention == MONO_CALL_VARARG) {
 613                 m->sig_cookie = 0;
 614         }
 615
 616         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 617                 inst = m->ret;
 618                 offset += sizeof(gpointer) - 1;
 619                 offset &= ~(sizeof(gpointer) - 1);
 620                 inst->inst_offset = offset;
 621                 inst->opcode = OP_REGOFFSET;
 622                 inst->inst_basereg = frame_reg;
 623                 offset += sizeof(gpointer);
 624                 if (sig->call_convention == MONO_CALL_VARARG)
 625                         m->sig_cookie += sizeof (gpointer);
 626         }
 627
 628         curinst = m->locals_start;
 629         for (i = curinst; i < m->num_varinfo; ++i) {
 630                 inst = m->varinfo [i];
 631                 if ((inst->flags & MONO_INST_IS_DEAD) || inst->opcode == OP_REGVAR)
 632                         continue;
 633
 634                 /* inst->unused indicates native sized value types, this is used by the
 635                 * pinvoke wrappers when they call functions returning structure */
 636                 if (inst->unused && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
 637                         size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), &align);
 638                 else
 639                         size = mono_type_size (inst->inst_vtype, &align);
 640
 641                 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
 642                  * since it loads/stores misaligned words, which don't do the right thing.
 643                  */
 644                 if (align < 4 && size >= 4)
 645                         align = 4;
 646                 offset += align - 1;
 647                 offset &= ~(align - 1);
 648                 inst->inst_offset = offset;
 649                 inst->opcode = OP_REGOFFSET;
 650                 inst->inst_basereg = frame_reg;
 651                 offset += size;
 652                 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
 653         }
 654
 655         curinst = 0;
 656         if (sig->hasthis) {
 657                 inst = m->varinfo [curinst];
 658                 if (inst->opcode != OP_REGVAR) {
 659                         inst->opcode = OP_REGOFFSET;
 660                         inst->inst_basereg = frame_reg;
 661                         offset += sizeof (gpointer) - 1;
 662                         offset &= ~(sizeof (gpointer) - 1);
 663                         inst->inst_offset = offset;
 664                         offset += sizeof (gpointer);
 665                         if (sig->call_convention == MONO_CALL_VARARG)
 666                                 m->sig_cookie += sizeof (gpointer);
 667                 }
 668                 curinst++;
 669         }
 670
 671         for (i = 0; i < sig->param_count; ++i) {
 672                 inst = m->varinfo [curinst];
 673                 if (inst->opcode != OP_REGVAR) {
 674                         inst->opcode = OP_REGOFFSET;
 675                         inst->inst_basereg = frame_reg;
 676                         size = mono_type_size (sig->params [i], &align);
 677                         /* FIXME: if a structure is misaligned, our memcpy doesn't work,
 678                          * since it loads/stores misaligned words, which don't do the right thing.
 679                          */
 680                         if (align < 4 && size >= 4)
 681                                 align = 4;
 682                         offset += align - 1;
 683                         offset &= ~(align - 1);
 684                         inst->inst_offset = offset;
 685                         offset += size;
 686                         if ((sig->call_convention == MONO_CALL_VARARG) && (i < sig->sentinelpos))
 687                                 m->sig_cookie += size;
 688                 }
 689                 curinst++;
 690         }
 691
 692         /* align the offset to 8 bytes */
 693         offset += 8 - 1;
 694         offset &= ~(8 - 1);
 695
 696         /* change sign? */
 697         m->stack_offset = offset;
 698
 699 }
 700
 701 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
 702  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
 703  */
 704
 705 /*
 706  * take the arguments and generate the arch-specific
 707  * instructions to properly call the function in call.
 708  * This includes pushing, moving arguments to the right register
 709  * etc.
 710  * Issue: who does the spilling if needed, and when?
 711  */
 712 MonoCallInst*
 713 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
 714         MonoInst *arg, *in;
 715         MonoMethodSignature *sig;
 716         int i, n;
 717         CallInfo *cinfo;
 718         ArgInfo *ainfo;
 719
 720         sig = call->signature;
 721         n = sig->param_count + sig->hasthis;
 722
 723         cinfo = calculate_sizes (sig, sig->pinvoke);
 724         if (cinfo->struct_ret)
 725                 call->used_iregs |= 1 << cinfo->struct_ret;
 726
 727         for (i = 0; i < n; ++i) {
 728                 ainfo = cinfo->args + i;
 729                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 730                         MonoInst *sig_arg;
 731                         cfg->disable_aot = TRUE;
 732
 733                         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
 734                         sig_arg->inst_p0 = call->signature;
 735
 736                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
 737                         arg->inst_imm = cinfo->sig_cookie.offset;
 738                         arg->inst_left = sig_arg;
 739
 740                         /* prepend, so they get reversed */
 741                         arg->next = call->out_args;
 742                         call->out_args = arg;
 743                 }
 744                 if (is_virtual && i == 0) {
 745                         /* the argument will be attached to the call instrucion */
 746                         in = call->args [i];
 747                         call->used_iregs |= 1 << ainfo->reg;
 748                 } else {
 749                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
 750                         in = call->args [i];
 751                         arg->cil_code = in->cil_code;
 752                         arg->inst_left = in;
 753                         arg->inst_right = (MonoInst*)call;
 754                         arg->type = in->type;
 755                         /* prepend, we'll need to reverse them later */
 756                         arg->next = call->out_args;
 757                         call->out_args = arg;
 758                         if (ainfo->regtype == RegTypeGeneral) {
 759                                 arg->unused = ainfo->reg;
 760                                 call->used_iregs |= 1 << ainfo->reg;
 761                                 if (arg->type == STACK_I8)
 762                                         call->used_iregs |= 1 << (ainfo->reg + 1);
 763                                 if (arg->type == STACK_R8) {
 764                                         if (ainfo->size == 4) {
 765                                                 arg->opcode = OP_OUTARG_R4;
 766                                         } else {
 767                                                 call->used_iregs |= 1 << (ainfo->reg + 1);
 768                                         }
 769                                         cfg->flags |= MONO_CFG_HAS_FPOUT;
 770                                 }
 771                         } else if (ainfo->regtype == RegTypeStructByAddr) {
 772                                 /* FIXME: where si the data allocated? */
 773                                 arg->unused = ainfo->reg;
 774                                 call->used_iregs |= 1 << ainfo->reg;
 775                                 g_assert_not_reached ();
 776                         } else if (ainfo->regtype == RegTypeStructByVal) {
 777                                 int cur_reg;
 778                                 /* mark the used regs */
 779                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
 780                                         call->used_iregs |= 1 << (ainfo->reg + cur_reg);
 781                                 }
 782                                 arg->opcode = OP_OUTARG_VT;
 783                                 /* vtsize and offset have just 12 bits of encoding in number of words */
 784                                 g_assert (((ainfo->vtsize | (ainfo->offset / 4)) & 0xfffff000) == 0);
 785                                 arg->unused = ainfo->reg | (ainfo->size << 4) | (ainfo->vtsize << 8) | ((ainfo->offset / 4) << 20);
 786                         } else if (ainfo->regtype == RegTypeBase) {
 787                                 arg->opcode = OP_OUTARG_MEMBASE;
 788                                 arg->unused = (ainfo->offset << 8) | ainfo->size;
 789                         } else if (ainfo->regtype == RegTypeFP) {
 790                                 arg->unused = ainfo->reg;
 791                                 /* FPA args are passed in int regs */
 792                                 call->used_iregs |= 1 << ainfo->reg;
 793                                 if (ainfo->size == 8) {
 794                                         arg->opcode = OP_OUTARG_R8;
 795                                         call->used_iregs |= 1 << (ainfo->reg + 1);
 796                                 } else {
 797                                         arg->opcode = OP_OUTARG_R4;
 798                                 }
 799                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
 800                         } else {
 801                                 g_assert_not_reached ();
 802                         }
 803                 }
 804         }
 805         /*
 806          * Reverse the call->out_args list.
 807          */
 808         {
 809                 MonoInst *prev = NULL, *list = call->out_args, *next;
 810                 while (list) {
 811                         next = list->next;
 812                         list->next = prev;
 813                         prev = list;
 814                         list = next;
 815                 }
 816                 call->out_args = prev;
 817         }
 818         call->stack_usage = cinfo->stack_usage;
 819         cfg->param_area = MAX (cfg->param_area, cinfo->stack_usage);
 820         cfg->flags |= MONO_CFG_HAS_CALLS;
 821         /*
 822          * should set more info in call, such as the stack space
 823          * used by the args that needs to be added back to esp
 824          */
 825
 826         g_free (cinfo);
 827         return call;
 828 }
 829
 830 /*
 831  * Allow tracing to work with this interface (with an optional argument)
 832  */
 833
 834 void*
 835 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
 836 {
 837         guchar *code = p;
 838
 839         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
 840         ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
 841         code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
 842         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
 843         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_R2);
 844         return code;
 845 }
 846
 847 enum {
 848         SAVE_NONE,
 849         SAVE_STRUCT,
 850         SAVE_ONE,
 851         SAVE_TWO,
 852         SAVE_FP
 853 };
 854
 855 void*
 856 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
 857 {
 858         guchar *code = p;
 859         int save_mode = SAVE_NONE;
 860         int offset;
 861         MonoMethod *method = cfg->method;
 862         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
 863         int save_offset = cfg->param_area;
 864         save_offset += 7;
 865         save_offset &= ~7;
 866
 867         offset = code - cfg->native_code;
 868         /* we need about 16 instructions */
 869         if (offset > (cfg->code_size - 16 * 4)) {
 870                 cfg->code_size *= 2;
 871                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
 872                 code = cfg->native_code + offset;
 873         }
 874 handle_enum:
 875         switch (rtype) {
 876         case MONO_TYPE_VOID:
 877                 /* special case string .ctor icall */
 878                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
 879                         save_mode = SAVE_ONE;
 880                 else
 881                         save_mode = SAVE_NONE;
 882                 break;
 883         case MONO_TYPE_I8:
 884         case MONO_TYPE_U8:
 885                 save_mode = SAVE_TWO;
 886                 break;
 887         case MONO_TYPE_R4:
 888         case MONO_TYPE_R8:
 889                 save_mode = SAVE_FP;
 890                 break;
 891         case MONO_TYPE_VALUETYPE:
 892                 save_mode = SAVE_STRUCT;
 893                 break;
 894         default:
 895                 save_mode = SAVE_ONE;
 896                 break;
 897         }
 898
 899         switch (save_mode) {
 900         case SAVE_TWO:
 901                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
 902                 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
 903                 if (enable_arguments) {
 904                         ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
 905                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
 906                 }
 907                 break;
 908         case SAVE_ONE:
 909                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
 910                 if (enable_arguments) {
 911                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
 912                 }
 913                 break;
 914         case SAVE_FP:
 915                 /* FIXME: what reg?  */
 916                 if (enable_arguments) {
 917                         /* FIXME: what reg?  */
 918                 }
 919                 break;
 920         case SAVE_STRUCT:
 921                 if (enable_arguments) {
 922                         /* FIXME: get the actual address  */
 923                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
 924                 }
 925                 break;
 926         case SAVE_NONE:
 927         default:
 928                 break;
 929         }
 930
 931         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
 932         code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
 933         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
 934         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 935
 936         switch (save_mode) {
 937         case SAVE_TWO:
 938                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
 939                 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
 940                 break;
 941         case SAVE_ONE:
 942                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
 943                 break;
 944         case SAVE_FP:
 945                 /* FIXME */
 946                 break;
 947         case SAVE_NONE:
 948         default:
 949                 break;
 950         }
 951
 952         return code;
 953 }
 954
 955 /*
 956  * The immediate field for cond branches is big enough for all reasonable methods
 957  */
 958 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
 959 if (ins->flags & MONO_INST_BRLABEL) { \
 960         if (0 && ins->inst_i0->inst_c0) { \
 961                 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_i0->inst_c0) & 0xffffff);    \
 962         } else { \
 963                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
 964                 ARM_B_COND (code, (condcode), 0);       \
 965         } \
 966 } else { \
 967         if (0 && ins->inst_true_bb->native_offset) { \
 968                 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
 969         } else { \
 970                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
 971                 ARM_B_COND (code, (condcode), 0);       \
 972         } \
 973 }
 974
 975 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
 976
 977 /* emit an exception if condition is fail
 978  *
 979  * We assign the extra code used to throw the implicit exceptions
 980  * to cfg->bb_exit as far as the big branch handling is concerned
 981  */
 982 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name)            \
 983         do {                                                        \
 984                 mono_add_patch_info (cfg, code - cfg->native_code,   \
 985                                     MONO_PATCH_INFO_EXC, exc_name);  \
 986                 ARM_BL_COND (code, (condcode), 0);      \
 987         } while (0);
 988
 989 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
 990
 991 static void
 992 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
 993 {
 994         MonoInst *ins, *last_ins = NULL;
 995         ins = bb->code;
 996
 997         while (ins) {
 998
 999                 switch (ins->opcode) {
1000                 case OP_MUL_IMM:
1001                         /* remove unnecessary multiplication with 1 */
1002                         if (ins->inst_imm == 1) {
1003                                 if (ins->dreg != ins->sreg1) {
1004                                         ins->opcode = OP_MOVE;
1005                                 } else {
1006                                         last_ins->next = ins->next;
1007                                         ins = ins->next;
1008                                         continue;
1009                                 }
1010                         } else {
1011                                 int power2 = mono_is_power_of_two (ins->inst_imm);
1012                                 if (power2 > 0) {
1013                                         ins->opcode = OP_SHL_IMM;
1014                                         ins->inst_imm = power2;
1015                                 }
1016                         }
1017                         break;
1018                 case OP_LOAD_MEMBASE:
1019                 case OP_LOADI4_MEMBASE:
1020                         /*
1021                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1022                          * OP_LOAD_MEMBASE offset(basereg), reg
1023                          */
1024                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1025                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1026                             ins->inst_basereg == last_ins->inst_destbasereg &&
1027                             ins->inst_offset == last_ins->inst_offset) {
1028                                 if (ins->dreg == last_ins->sreg1) {
1029                                         last_ins->next = ins->next;
1030                                         ins = ins->next;
1031                                         continue;
1032                                 } else {
1033                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1034                                         ins->opcode = OP_MOVE;
1035                                         ins->sreg1 = last_ins->sreg1;
1036                                 }
1037
1038                         /*
1039                          * Note: reg1 must be different from the basereg in the second load
1040                          * OP_LOAD_MEMBASE offset(basereg), reg1
1041                          * OP_LOAD_MEMBASE offset(basereg), reg2
1042                          * -->
1043                          * OP_LOAD_MEMBASE offset(basereg), reg1
1044                          * OP_MOVE reg1, reg2
1045                          */
1046                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1047                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1048                               ins->inst_basereg != last_ins->dreg &&
1049                               ins->inst_basereg == last_ins->inst_basereg &&
1050                               ins->inst_offset == last_ins->inst_offset) {
1051
1052                                 if (ins->dreg == last_ins->dreg) {
1053                                         last_ins->next = ins->next;
1054                                         ins = ins->next;
1055                                         continue;
1056                                 } else {
1057                                         ins->opcode = OP_MOVE;
1058                                         ins->sreg1 = last_ins->dreg;
1059                                 }
1060
1061                                 //g_assert_not_reached ();
1062
1063 #if 0
1064                         /*
1065                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1066                          * OP_LOAD_MEMBASE offset(basereg), reg
1067                          * -->
1068                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1069                          * OP_ICONST reg, imm
1070                          */
1071                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1072                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1073                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1074                                    ins->inst_offset == last_ins->inst_offset) {
1075                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1076                                 ins->opcode = OP_ICONST;
1077                                 ins->inst_c0 = last_ins->inst_imm;
1078                                 g_assert_not_reached (); // check this rule
1079 #endif
1080                         }
1081                         break;
1082                 case OP_LOADU1_MEMBASE:
1083                 case OP_LOADI1_MEMBASE:
1084                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1085                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1086                                         ins->inst_offset == last_ins->inst_offset) {
1087                                 if (ins->dreg == last_ins->sreg1) {
1088                                         last_ins->next = ins->next;
1089                                         ins = ins->next;
1090                                         continue;
1091                                 } else {
1092                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1093                                         ins->opcode = OP_MOVE;
1094                                         ins->sreg1 = last_ins->sreg1;
1095                                 }
1096                         }
1097                         break;
1098                 case OP_LOADU2_MEMBASE:
1099                 case OP_LOADI2_MEMBASE:
1100                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1101                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1102                                         ins->inst_offset == last_ins->inst_offset) {
1103                                 if (ins->dreg == last_ins->sreg1) {
1104                                         last_ins->next = ins->next;
1105                                         ins = ins->next;
1106                                         continue;
1107                                 } else {
1108                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1109                                         ins->opcode = OP_MOVE;
1110                                         ins->sreg1 = last_ins->sreg1;
1111                                 }
1112                         }
1113                         break;
1114                 case CEE_CONV_I4:
1115                 case CEE_CONV_U4:
1116                 case OP_MOVE:
1117                 case OP_SETREG:
1118                         ins->opcode = OP_MOVE;
1119                         /*
1120                          * OP_MOVE reg, reg
1121                          */
1122                         if (ins->dreg == ins->sreg1) {
1123                                 if (last_ins)
1124                                         last_ins->next = ins->next;
1125                                 ins = ins->next;
1126                                 continue;
1127                         }
1128                         /*
1129                          * OP_MOVE sreg, dreg
1130                          * OP_MOVE dreg, sreg
1131                          */
1132                         if (last_ins && last_ins->opcode == OP_MOVE &&
1133                             ins->sreg1 == last_ins->dreg &&
1134                             ins->dreg == last_ins->sreg1) {
1135                                 last_ins->next = ins->next;
1136                                 ins = ins->next;
1137                                 continue;
1138                         }
1139                         break;
1140                 }
1141                 last_ins = ins;
1142                 ins = ins->next;
1143         }
1144         bb->last_ins = last_ins;
1145 }
1146
1147 /*
1148  * the branch_cc_table should maintain the order of these
1149  * opcodes.
1150 case CEE_BEQ:
1151 case CEE_BGE:
1152 case CEE_BGT:
1153 case CEE_BLE:
1154 case CEE_BLT:
1155 case CEE_BNE_UN:
1156 case CEE_BGE_UN:
1157 case CEE_BGT_UN:
1158 case CEE_BLE_UN:
1159 case CEE_BLT_UN:
1160  */
1161 static const guchar
1162 branch_cc_table [] = {
1163         ARMCOND_EQ,
1164         ARMCOND_GE,
1165         ARMCOND_GT,
1166         ARMCOND_LE,
1167         ARMCOND_LT,
1168
1169         ARMCOND_NE,
1170         ARMCOND_HS,
1171         ARMCOND_HI,
1172         ARMCOND_LS,
1173         ARMCOND_LO
1174 };
1175
1176
1177 static void
1178 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *to_insert)
1179 {
1180         if (ins == NULL) {
1181                 ins = bb->code;
1182                 bb->code = to_insert;
1183                 to_insert->next = ins;
1184         } else {
1185                 to_insert->next = ins->next;
1186                 ins->next = to_insert;
1187         }
1188 }
1189
1190 #define NEW_INS(cfg,dest,op) do {       \
1191                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1192                 (dest)->opcode = (op);  \
1193                 insert_after_ins (bb, last_ins, (dest)); \
1194         } while (0)
1195
1196 static int
1197 map_to_reg_reg_op (int op)
1198 {
1199         switch (op) {
1200         case OP_ADD_IMM:
1201                 return CEE_ADD;
1202         case OP_SUB_IMM:
1203                 return CEE_SUB;
1204         case OP_AND_IMM:
1205                 return CEE_AND;
1206         case OP_COMPARE_IMM:
1207                 return OP_COMPARE;
1208         case OP_ADDCC_IMM:
1209                 return OP_ADDCC;
1210         case OP_ADC_IMM:
1211                 return OP_ADC;
1212         case OP_SUBCC_IMM:
1213                 return OP_SUBCC;
1214         case OP_SBB_IMM:
1215                 return OP_SBB;
1216         case OP_OR_IMM:
1217                 return CEE_OR;
1218         case OP_XOR_IMM:
1219                 return CEE_XOR;
1220         case OP_LOAD_MEMBASE:
1221                 return OP_LOAD_MEMINDEX;
1222         case OP_LOADI4_MEMBASE:
1223                 return OP_LOADI4_MEMINDEX;
1224         case OP_LOADU4_MEMBASE:
1225                 return OP_LOADU4_MEMINDEX;
1226         case OP_LOADU1_MEMBASE:
1227                 return OP_LOADU1_MEMINDEX;
1228         case OP_LOADI2_MEMBASE:
1229                 return OP_LOADI2_MEMINDEX;
1230         case OP_LOADU2_MEMBASE:
1231                 return OP_LOADU2_MEMINDEX;
1232         case OP_LOADI1_MEMBASE:
1233                 return OP_LOADI1_MEMINDEX;
1234         case OP_STOREI1_MEMBASE_REG:
1235                 return OP_STOREI1_MEMINDEX;
1236         case OP_STOREI2_MEMBASE_REG:
1237                 return OP_STOREI2_MEMINDEX;
1238         case OP_STOREI4_MEMBASE_REG:
1239                 return OP_STOREI4_MEMINDEX;
1240         case OP_STORE_MEMBASE_REG:
1241                 return OP_STORE_MEMINDEX;
1242         case OP_STORER4_MEMBASE_REG:
1243                 return OP_STORER4_MEMINDEX;
1244         case OP_STORER8_MEMBASE_REG:
1245                 return OP_STORER8_MEMINDEX;
1246         case OP_STORE_MEMBASE_IMM:
1247                 return OP_STORE_MEMBASE_REG;
1248         case OP_STOREI1_MEMBASE_IMM:
1249                 return OP_STOREI1_MEMBASE_REG;
1250         case OP_STOREI2_MEMBASE_IMM:
1251                 return OP_STOREI2_MEMBASE_REG;
1252         case OP_STOREI4_MEMBASE_IMM:
1253                 return OP_STOREI4_MEMBASE_REG;
1254         }
1255         g_assert_not_reached ();
1256 }
1257
1258 /*
1259  * Remove from the instruction list the instructions that can't be
1260  * represented with very simple instructions with no register
1261  * requirements.
1262  */
1263 static void
1264 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1265 {
1266         MonoInst *ins, *next, *temp, *last_ins = NULL;
1267         int rot_amount, imm8, low_imm;
1268
1269         /* setup the virtual reg allocator */
1270         if (bb->max_ireg > cfg->rs->next_vireg)
1271                 cfg->rs->next_vireg = bb->max_ireg;
1272
1273         ins = bb->code;
1274         while (ins) {
1275 loop_start:
1276                 switch (ins->opcode) {
1277                 case OP_ADD_IMM:
1278                 case OP_SUB_IMM:
1279                 case OP_AND_IMM:
1280                 case OP_COMPARE_IMM:
1281                 case OP_ADDCC_IMM:
1282                 case OP_ADC_IMM:
1283                 case OP_SUBCC_IMM:
1284                 case OP_SBB_IMM:
1285                 case OP_OR_IMM:
1286                 case OP_XOR_IMM:
1287                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
1288                                 NEW_INS (cfg, temp, OP_ICONST);
1289                                 temp->inst_c0 = ins->inst_imm;
1290                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1291                                 ins->sreg2 = temp->dreg;
1292                                 ins->opcode = map_to_reg_reg_op (ins->opcode);
1293                         }
1294                         break;
1295                 case OP_MUL_IMM:
1296                         if (ins->inst_imm == 1) {
1297                                 ins->opcode = OP_MOVE;
1298                                 break;
1299                         }
1300                         if (ins->inst_imm == 0) {
1301                                 ins->opcode = OP_ICONST;
1302                                 ins->inst_c0 = 0;
1303                                 break;
1304                         }
1305                         imm8 = mono_is_power_of_two (ins->inst_imm);
1306                         if (imm8 > 0) {
1307                                 ins->opcode = OP_SHL_IMM;
1308                                 ins->inst_imm = imm8;
1309                                 break;
1310                         }
1311                         NEW_INS (cfg, temp, OP_ICONST);
1312                         temp->inst_c0 = ins->inst_imm;
1313                         temp->dreg = mono_regstate_next_int (cfg->rs);
1314                         ins->sreg2 = temp->dreg;
1315                         ins->opcode = CEE_MUL;
1316                         break;
1317                 case OP_LOAD_MEMBASE:
1318                 case OP_LOADI4_MEMBASE:
1319                 case OP_LOADU4_MEMBASE:
1320                 case OP_LOADU1_MEMBASE:
1321                         /* we can do two things: load the immed in a register
1322                          * and use an indexed load, or see if the immed can be
1323                          * represented as an ad_imm + a load with a smaller offset
1324                          * that fits. We just do the first for now, optimize later.
1325                          */
1326                         if (arm_is_imm12 (ins->inst_offset))
1327                                 break;
1328                         NEW_INS (cfg, temp, OP_ICONST);
1329                         temp->inst_c0 = ins->inst_offset;
1330                         temp->dreg = mono_regstate_next_int (cfg->rs);
1331                         ins->sreg2 = temp->dreg;
1332                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1333                         break;
1334                 case OP_LOADI2_MEMBASE:
1335                 case OP_LOADU2_MEMBASE:
1336                 case OP_LOADI1_MEMBASE:
1337                         if (arm_is_imm8 (ins->inst_offset))
1338                                 break;
1339                         NEW_INS (cfg, temp, OP_ICONST);
1340                         temp->inst_c0 = ins->inst_offset;
1341                         temp->dreg = mono_regstate_next_int (cfg->rs);
1342                         ins->sreg2 = temp->dreg;
1343                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1344                         break;
1345                 case OP_LOADR4_MEMBASE:
1346                 case OP_LOADR8_MEMBASE:
1347                         if (arm_is_fpimm8 (ins->inst_offset))
1348                                 break;
1349                         low_imm = ins->inst_offset & 0x1ff;
1350                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
1351                                 NEW_INS (cfg, temp, OP_ADD_IMM);
1352                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
1353                                 temp->sreg1 = ins->inst_basereg;
1354                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1355                                 ins->inst_basereg = temp->dreg;
1356                                 ins->inst_offset = low_imm;
1357                                 break;
1358                         }
1359                         /* FPA doesn't have indexed load instructions */
1360                         g_assert_not_reached ();
1361                         break;
1362                 case OP_STORE_MEMBASE_REG:
1363                 case OP_STOREI4_MEMBASE_REG:
1364                 case OP_STOREI1_MEMBASE_REG:
1365                         if (arm_is_imm12 (ins->inst_offset))
1366                                 break;
1367                         NEW_INS (cfg, temp, OP_ICONST);
1368                         temp->inst_c0 = ins->inst_offset;
1369                         temp->dreg = mono_regstate_next_int (cfg->rs);
1370                         ins->sreg2 = temp->dreg;
1371                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1372                         break;
1373                 case OP_STOREI2_MEMBASE_REG:
1374                         if (arm_is_imm8 (ins->inst_offset))
1375                                 break;
1376                         NEW_INS (cfg, temp, OP_ICONST);
1377                         temp->inst_c0 = ins->inst_offset;
1378                         temp->dreg = mono_regstate_next_int (cfg->rs);
1379                         ins->sreg2 = temp->dreg;
1380                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1381                         break;
1382                 case OP_STORER4_MEMBASE_REG:
1383                 case OP_STORER8_MEMBASE_REG:
1384                         if (arm_is_fpimm8 (ins->inst_offset))
1385                                 break;
1386                         low_imm = ins->inst_offset & 0x1ff;
1387                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
1388                                 NEW_INS (cfg, temp, OP_ADD_IMM);
1389                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
1390                                 temp->sreg1 = ins->inst_destbasereg;
1391                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1392                                 ins->inst_destbasereg = temp->dreg;
1393                                 ins->inst_offset = low_imm;
1394                                 break;
1395                         }
1396                         /*g_print ("fail with: %d (%d, %d)\n", ins->inst_offset, ins->inst_offset & ~0x1ff, low_imm);*/
1397                         /* FPA doesn't have indexed store instructions */
1398                         g_assert_not_reached ();
1399                         break;
1400                 case OP_STORE_MEMBASE_IMM:
1401                 case OP_STOREI1_MEMBASE_IMM:
1402                 case OP_STOREI2_MEMBASE_IMM:
1403                 case OP_STOREI4_MEMBASE_IMM:
1404                         NEW_INS (cfg, temp, OP_ICONST);
1405                         temp->inst_c0 = ins->inst_imm;
1406                         temp->dreg = mono_regstate_next_int (cfg->rs);
1407                         ins->sreg1 = temp->dreg;
1408                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1409                         last_ins = temp;
1410                         goto loop_start; /* make it handle the possibly big ins->inst_offset */
1411                 }
1412                 last_ins = ins;
1413                 ins = ins->next;
1414         }
1415         bb->last_ins = last_ins;
1416         bb->max_ireg = cfg->rs->next_vireg;
1417
1418 }
1419
1420 void
1421 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1422 {
1423         if (!bb->code)
1424                 return;
1425         mono_arch_lowering_pass (cfg, bb);
1426         mono_local_regalloc (cfg, bb);
1427 }
1428
1429 static guchar*
1430 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1431 {
1432         /* sreg is a float, dreg is an integer reg  */
1433         ARM_FIXZ (code, dreg, sreg);
1434         if (!is_signed) {
1435                 if (size == 1)
1436                         ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
1437                 else if (size == 2) {
1438                         ARM_SHL_IMM (code, dreg, dreg, 16);
1439                         ARM_SHR_IMM (code, dreg, dreg, 16);
1440                 }
1441         } else {
1442                 if (size == 1) {
1443                         ARM_SHL_IMM (code, dreg, dreg, 24);
1444                         ARM_SAR_IMM (code, dreg, dreg, 24);
1445                 } else if (size == 2) {
1446                         ARM_SHL_IMM (code, dreg, dreg, 16);
1447                         ARM_SAR_IMM (code, dreg, dreg, 16);
1448                 }
1449         }
1450         return code;
1451 }
1452
1453 typedef struct {
1454         guchar *code;
1455         const guchar *target;
1456         int absolute;
1457         int found;
1458 } PatchData;
1459
1460 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
1461
1462 static int
1463 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
1464         PatchData *pdata = (PatchData*)user_data;
1465         guchar *code = data;
1466         guint32 *thunks = data;
1467         guint32 *endthunks = (guint32*)(code + bsize);
1468         int i, count = 0;
1469         int difflow, diffhigh;
1470
1471         /* always ensure a call from pdata->code can reach to the thunks without further thunks */
1472         difflow = (char*)pdata->code - (char*)thunks;
1473         diffhigh = (char*)pdata->code - (char*)endthunks;
1474         if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
1475                 return 0;
1476
1477         /*
1478          * The thunk is composed of 3 words:
1479          * load constant from thunks [2] into ARM_IP
1480          * bx to ARM_IP
1481          * address constant
1482          * Note that the LR register is already setup
1483          */
1484         //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
1485         if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
1486                 while (thunks < endthunks) {
1487                         //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
1488                         if (thunks [2] == (guint32)pdata->target) {
1489                                 arm_patch (pdata->code, (guchar*)thunks);
1490                                 mono_arch_flush_icache (pdata->code, 4);
1491                                 pdata->found = 1;
1492                                 return 1;
1493                         } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
1494                                 /* found a free slot instead: emit thunk */
1495                                 code = (guchar*)thunks;
1496                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
1497                                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
1498                                 thunks [2] = (guint32)pdata->target;
1499                                 mono_arch_flush_icache ((guchar*)thunks, 12);
1500
1501                                 arm_patch (pdata->code, (guchar*)thunks);
1502                                 mono_arch_flush_icache (pdata->code, 4);
1503                                 pdata->found = 1;
1504                                 return 1;
1505                         }
1506                         /* skip 12 bytes, the size of the thunk */
1507                         thunks += 3;
1508                         count++;
1509                 }
1510                 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
1511         }
1512         return 0;
1513 }
1514
1515 static void
1516 handle_thunk (int absolute, guchar *code, const guchar *target) {
1517         MonoDomain *domain = mono_domain_get ();
1518         PatchData pdata;
1519
1520         pdata.code = code;
1521         pdata.target = target;
1522         pdata.absolute = absolute;
1523         pdata.found = 0;
1524
1525         mono_domain_lock (domain);
1526         mono_code_manager_foreach (domain->code_mp, search_thunk_slot, &pdata);
1527
1528         if (!pdata.found) {
1529                 /* this uses the first available slot */
1530                 pdata.found = 2;
1531                 mono_code_manager_foreach (domain->code_mp, search_thunk_slot, &pdata);
1532         }
1533         mono_domain_unlock (domain);
1534
1535         if (pdata.found != 1)
1536                 g_print ("thunk failed for %p from %p\n", target, code);
1537         g_assert (pdata.found == 1);
1538 }
1539
1540 void
1541 arm_patch (guchar *code, const guchar *target)
1542 {
1543         guint32 ins = *(guint32*)code;
1544         guint32 prim = (ins >> 25) & 7;
1545         guint32 ovf;
1546
1547         //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
1548         if (prim == 5) { /* 101b */
1549                 /* the diff starts 8 bytes from the branch opcode */
1550                 gint diff = target - code - 8;
1551                 if (diff >= 0) {
1552                         if (diff <= 33554431) {
1553                                 diff >>= 2;
1554                                 ins = (ins & 0xff000000) | diff;
1555                                 *(guint32*)code = ins;
1556                                 return;
1557                         }
1558                 } else {
1559                         /* diff between 0 and -33554432 */
1560                         if (diff >= -33554432) {
1561                                 diff >>= 2;
1562                                 ins = (ins & 0xff000000) | (diff & ~0xff000000);
1563                                 *(guint32*)code = ins;
1564                                 return;
1565                         }
1566                 }
1567
1568                 handle_thunk (TRUE, code, target);
1569                 return;
1570         }
1571
1572
1573         if ((ins & 0x0ffffff0) == 0x12fff10) {
1574                 /* branch and exchange: the address is constructed in a reg */
1575                 g_assert_not_reached ();
1576         } else {
1577                 g_assert_not_reached ();
1578         }
1579 //      g_print ("patched with 0x%08x\n", ins);
1580 }
1581
1582 /*
1583  * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
1584  * (with the rotation amount in *rot_amount. rot_amount is already adjusted
1585  * to be used with the emit macros.
1586  * Return -1 otherwise.
1587  */
1588 int
1589 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
1590 {
1591         guint32 res, i;
1592         for (i = 0; i < 31; i+= 2) {
1593                 res = (val << (32 - i)) | (val >> i);
1594                 if (res & ~0xff)
1595                         continue;
1596                 *rot_amount = i? 32 - i: 0;
1597                 return res;
1598         }
1599         return -1;
1600 }
1601
1602 /*
1603  * Emits in code a sequence of instructions that load the value 'val'
1604  * into the dreg register. Uses at most 4 instructions.
1605  */
1606 guint8*
1607 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
1608 {
1609         int imm8, rot_amount;
1610 #if 0
1611         ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
1612         /* skip the constant pool */
1613         ARM_B (code, 0);
1614         *(int*)code = val;
1615         code += 4;
1616         return code;
1617 #endif
1618         if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
1619                 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
1620         } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
1621                 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
1622         } else {
1623                 if (val & 0xFF) {
1624                         ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
1625                         if (val & 0xFF00) {
1626                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
1627                         }
1628                         if (val & 0xFF0000) {
1629                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
1630                         }
1631                         if (val & 0xFF000000) {
1632                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
1633                         }
1634                 } else if (val & 0xFF00) {
1635                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
1636                         if (val & 0xFF0000) {
1637                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
1638                         }
1639                         if (val & 0xFF000000) {
1640                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
1641                         }
1642                 } else if (val & 0xFF0000) {
1643                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
1644                         if (val & 0xFF000000) {
1645                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
1646                         }
1647                 }
1648                 //g_assert_not_reached ();
1649         }
1650         return code;
1651 }
1652
1653 void
1654 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
1655 {
1656         MonoInst *ins;
1657         MonoCallInst *call;
1658         guint offset;
1659         guint8 *code = cfg->native_code + cfg->code_len;
1660         MonoInst *last_ins = NULL;
1661         guint last_offset = 0;
1662         int max_len, cpos;
1663         int imm8, rot_amount;
1664
1665         if (cfg->opt & MONO_OPT_PEEPHOLE)
1666                 peephole_pass (cfg, bb);
1667
1668         /* we don't align basic blocks of loops on arm */
1669
1670         if (cfg->verbose_level > 2)
1671                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
1672
1673         cpos = bb->max_offset;
1674
1675         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
1676                 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
1677                 //g_assert (!mono_compile_aot);
1678                 //cpos += 6;
1679                 //if (bb->cil_code)
1680                 //      cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
1681                 /* this is not thread save, but good enough */
1682                 /* fixme: howto handle overflows? */
1683                 //x86_inc_mem (code, &cov->data [bb->dfn].count);
1684         }
1685
1686         ins = bb->code;
1687         while (ins) {
1688                 offset = code - cfg->native_code;
1689
1690                 max_len = ((guint8 *)arm_cpu_desc [ins->opcode])[MONO_INST_LEN];
1691
1692                 if (offset > (cfg->code_size - max_len - 16)) {
1693                         cfg->code_size *= 2;
1694                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
1695                         code = cfg->native_code + offset;
1696                 }
1697         //      if (ins->cil_code)
1698         //              g_print ("cil code\n");
1699                 mono_debug_record_line_number (cfg, ins, offset);
1700
1701                 switch (ins->opcode) {
1702                 case OP_TLS_GET:
1703                         g_assert_not_reached ();
1704                         break;
1705                 /*case OP_BIGMUL:
1706                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
1707                         ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
1708                         break;
1709                 case OP_BIGMUL_UN:
1710                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
1711                         ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
1712                         break;*/
1713                 case OP_STOREI1_MEMBASE_IMM:
1714                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
1715                         g_assert (arm_is_imm12 (ins->inst_offset));
1716                         ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
1717                         break;
1718                 case OP_STOREI2_MEMBASE_IMM:
1719                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
1720                         g_assert (arm_is_imm8 (ins->inst_offset));
1721                         ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
1722                         break;
1723                 case OP_STORE_MEMBASE_IMM:
1724                 case OP_STOREI4_MEMBASE_IMM:
1725                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
1726                         g_assert (arm_is_imm12 (ins->inst_offset));
1727                         ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
1728                         break;
1729                 case OP_STOREI1_MEMBASE_REG:
1730                         g_assert (arm_is_imm12 (ins->inst_offset));
1731                         ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
1732                         break;
1733                 case OP_STOREI2_MEMBASE_REG:
1734                         g_assert (arm_is_imm8 (ins->inst_offset));
1735                         ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
1736                         break;
1737                 case OP_STORE_MEMBASE_REG:
1738                 case OP_STOREI4_MEMBASE_REG:
1739                         /* this case is special, since it happens for spill code after lowering has been called */
1740                         if (arm_is_imm12 (ins->inst_offset)) {
1741                                 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
1742                         } else {
1743                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
1744                                 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
1745                         }
1746                         break;
1747                 case OP_STOREI1_MEMINDEX:
1748                         ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
1749                         break;
1750                 case OP_STOREI2_MEMINDEX:
1751                         /* note: the args are reversed in the macro */
1752                         ARM_STRH_REG_REG (code, ins->inst_destbasereg, ins->sreg1, ins->sreg2);
1753                         break;
1754                 case OP_STORE_MEMINDEX:
1755                 case OP_STOREI4_MEMINDEX:
1756                         ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
1757                         break;
1758                 case CEE_LDIND_I:
1759                 case CEE_LDIND_I4:
1760                 case CEE_LDIND_U4:
1761                         g_assert_not_reached ();
1762                         break;
1763                 case OP_LOADU4_MEM:
1764                         g_assert_not_reached ();
1765                         break;
1766                 case OP_LOAD_MEMINDEX:
1767                 case OP_LOADI4_MEMINDEX:
1768                 case OP_LOADU4_MEMINDEX:
1769                         ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1770                         break;
1771                 case OP_LOADI1_MEMINDEX:
1772                         /* note: the args are reversed in the macro */
1773                         ARM_LDRSB_REG_REG (code, ins->inst_basereg, ins->dreg, ins->sreg2);
1774                         break;
1775                 case OP_LOADU1_MEMINDEX:
1776                         ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1777                         break;
1778                 case OP_LOADI2_MEMINDEX:
1779                         /* note: the args are reversed in the macro */
1780                         ARM_LDRSH_REG_REG (code, ins->inst_basereg, ins->dreg, ins->sreg2);
1781                         break;
1782                 case OP_LOADU2_MEMINDEX:
1783                         /* note: the args are reversed in the macro */
1784                         ARM_LDRH_REG_REG (code, ins->inst_basereg, ins->dreg, ins->sreg2);
1785                         break;
1786                 case OP_LOAD_MEMBASE:
1787                 case OP_LOADI4_MEMBASE:
1788                 case OP_LOADU4_MEMBASE:
1789                         /* this case is special, since it happens for spill code after lowering has been called */
1790                         if (arm_is_imm12 (ins->inst_offset)) {
1791                                 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1792                         } else {
1793                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
1794                                 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
1795                         }
1796                         break;
1797                 case OP_LOADI1_MEMBASE:
1798                         g_assert (arm_is_imm8 (ins->inst_offset));
1799                         ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1800                         break;
1801                 case OP_LOADU1_MEMBASE:
1802                         g_assert (arm_is_imm12 (ins->inst_offset));
1803                         ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1804                         break;
1805                 case OP_LOADU2_MEMBASE:
1806                         g_assert (arm_is_imm8 (ins->inst_offset));
1807                         ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1808                         break;
1809                 case OP_LOADI2_MEMBASE:
1810                         g_assert (arm_is_imm8 (ins->inst_offset));
1811                         ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1812                         break;
1813                 case CEE_CONV_I1:
1814                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
1815                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
1816                         break;
1817                 case CEE_CONV_I2:
1818                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
1819                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
1820                         break;
1821                 case CEE_CONV_U1:
1822                         ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
1823                         break;
1824                 case CEE_CONV_U2:
1825                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
1826                         ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
1827                         break;
1828                 case OP_COMPARE:
1829                         ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
1830                         break;
1831                 case OP_COMPARE_IMM:
1832                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1833                         g_assert (imm8 >= 0);
1834                         ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
1835                         break;
1836                 case OP_X86_TEST_NULL:
1837                         g_assert_not_reached ();
1838                         break;
1839                 case CEE_BREAK:
1840                         *(int*)code = 0xe7f001f0;
1841                         *(int*)code = 0xef9f0001;
1842                         code += 4;
1843                         //ARM_DBRK (code);
1844                         break;
1845                 case OP_ADDCC:
1846                         ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1847                         break;
1848                 case CEE_ADD:
1849                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1850                         break;
1851                 case OP_ADC:
1852                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1853                         break;
1854                 case OP_ADDCC_IMM:
1855                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1856                         g_assert (imm8 >= 0);
1857                         ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1858                         break;
1859                 case OP_ADD_IMM:
1860                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1861                         g_assert (imm8 >= 0);
1862                         ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1863                         break;
1864                 case OP_ADC_IMM:
1865                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1866                         g_assert (imm8 >= 0);
1867                         ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1868                         break;
1869                 case CEE_ADD_OVF:
1870                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1871                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1872                         break;
1873                 case CEE_ADD_OVF_UN:
1874                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1875                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1876                         break;
1877                 case CEE_SUB_OVF:
1878                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1879                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1880                         break;
1881                 case CEE_SUB_OVF_UN:
1882                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1883                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
1884                         break;
1885                 case OP_ADD_OVF_CARRY:
1886                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1887                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1888                         break;
1889                 case OP_ADD_OVF_UN_CARRY:
1890                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1891                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1892                         break;
1893                 case OP_SUB_OVF_CARRY:
1894                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1895                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1896                         break;
1897                 case OP_SUB_OVF_UN_CARRY:
1898                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1899                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
1900                         break;
1901                 case OP_SUBCC:
1902                         ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1903                         break;
1904                 case OP_SUBCC_IMM:
1905                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1906                         g_assert (imm8 >= 0);
1907                         ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1908                         break;
1909                 case CEE_SUB:
1910                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1911                         break;
1912                 case OP_SBB:
1913                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1914                         break;
1915                 case OP_SUB_IMM:
1916                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1917                         g_assert (imm8 >= 0);
1918                         ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1919                         break;
1920                 case OP_SBB_IMM:
1921                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1922                         g_assert (imm8 >= 0);
1923                         ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1924                         break;
1925                 case OP_ARM_RSBS_IMM:
1926                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1927                         g_assert (imm8 >= 0);
1928                         ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1929                         break;
1930                 case OP_ARM_RSC_IMM:
1931                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1932                         g_assert (imm8 >= 0);
1933                         ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1934                         break;
1935                 case CEE_AND:
1936                         ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1937                         break;
1938                 case OP_AND_IMM:
1939                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1940                         g_assert (imm8 >= 0);
1941                         ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1942                         break;
1943                 case CEE_DIV:
1944                 case CEE_DIV_UN:
1945                 case OP_DIV_IMM:
1946                 case CEE_REM:
1947                 case CEE_REM_UN:
1948                 case OP_REM_IMM:
1949                         /* crappy ARM arch doesn't have a DIV instruction */
1950                         g_assert_not_reached ();
1951                 case CEE_OR:
1952                         ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1953                         break;
1954                 case OP_OR_IMM:
1955                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1956                         g_assert (imm8 >= 0);
1957                         ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1958                         break;
1959                 case CEE_XOR:
1960                         ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1961                         break;
1962                 case OP_XOR_IMM:
1963                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1964                         g_assert (imm8 >= 0);
1965                         ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1966                         break;
1967                 case CEE_SHL:
1968                         ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1969                         break;
1970                 case OP_SHL_IMM:
1971                         if (ins->inst_imm)
1972                                 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
1973                         break;
1974                 case CEE_SHR:
1975                         ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1976                         break;
1977                 case OP_SHR_IMM:
1978                         if (ins->inst_imm)
1979                                 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
1980                         break;
1981                 case OP_SHR_UN_IMM:
1982                         if (ins->inst_imm)
1983                                 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
1984                         break;
1985                 case CEE_SHR_UN:
1986                         ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1987                         break;
1988                 case CEE_NOT:
1989                         ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
1990                         break;
1991                 case CEE_NEG:
1992                         ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
1993                         break;
1994                 case CEE_MUL:
1995                         if (ins->dreg == ins->sreg2)
1996                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1997                         else
1998                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
1999                         break;
2000                 case OP_MUL_IMM:
2001                         g_assert_not_reached ();
2002                         break;
2003                 case CEE_MUL_OVF:
2004                         /* FIXME: handle ovf/ sreg2 != dreg */
2005                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
2006                         break;
2007                 case CEE_MUL_OVF_UN:
2008                         /* FIXME: handle ovf/ sreg2 != dreg */
2009                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
2010                         break;
2011                 case OP_ICONST:
2012                 case OP_SETREGIMM:
2013                         code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
2014                         break;
2015                 case OP_AOTCONST:
2016                         g_assert_not_reached ();
2017                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2018                         break;
2019                 case CEE_CONV_I4:
2020                 case CEE_CONV_U4:
2021                 case OP_MOVE:
2022                 case OP_SETREG:
2023                         if (ins->dreg != ins->sreg1)
2024                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
2025                         break;
2026                 case OP_SETLRET: {
2027                         int saved = ins->sreg2;
2028                         if (ins->sreg2 == ARM_LSW_REG) {
2029                                 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
2030                                 saved = ARMREG_LR;
2031                         }
2032                         if (ins->sreg1 != ARM_LSW_REG)
2033                                 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
2034                         if (saved != ARM_MSW_REG)
2035                                 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
2036                         break;
2037                 }
2038                 case OP_SETFREG:
2039                 case OP_FMOVE:
2040                         ARM_MVFD (code, ins->dreg, ins->sreg1);
2041                         break;
2042                 case OP_FCONV_TO_R4:
2043                         ARM_MVFS (code, ins->dreg, ins->sreg1);
2044                         break;
2045                 case CEE_JMP:
2046                         /*
2047                          * Keep in sync with mono_arch_emit_epilog
2048                          */
2049                         g_assert (!cfg->method->save_lmf);
2050                         code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
2051                         ARM_POP_NWB (code, cfg->used_int_regs | ((1 << ARMREG_SP)) | ((1 << ARMREG_LR)));
2052                         mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2053                         ARM_B (code, 0);
2054                         break;
2055                 case OP_CHECK_THIS:
2056                         /* ensure ins->sreg1 is not NULL */
2057                         ARM_LDR_IMM (code, ARMREG_LR, ins->sreg1, 0);
2058                         break;
2059                 case OP_ARGLIST: {
2060 #if ARM_PORT
2061                         if (ppc_is_imm16 (cfg->sig_cookie + cfg->stack_usage)) {
2062                                 ppc_addi (code, ppc_r11, cfg->frame_reg, cfg->sig_cookie + cfg->stack_usage);
2063                         } else {
2064                                 ppc_load (code, ppc_r11, cfg->sig_cookie + cfg->stack_usage);
2065                                 ppc_add (code, ppc_r11, cfg->frame_reg, ppc_r11);
2066                         }
2067                         ppc_stw (code, ppc_r11, 0, ins->sreg1);
2068 #endif
2069                         break;
2070                 }
2071                 case OP_FCALL:
2072                 case OP_LCALL:
2073                 case OP_VCALL:
2074                 case OP_VOIDCALL:
2075                 case CEE_CALL:
2076                         call = (MonoCallInst*)ins;
2077                         if (ins->flags & MONO_INST_HAS_METHOD)
2078                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
2079                         else
2080                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
2081                         if (cfg->method->dynamic) {
2082                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2083                                 ARM_B (code, 0);
2084                                 *(gpointer*)code = NULL;
2085                                 code += 4;
2086                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2087                                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2088                         } else {
2089                                 ARM_BL (code, 0);
2090                         }
2091                         break;
2092                 case OP_FCALL_REG:
2093                 case OP_LCALL_REG:
2094                 case OP_VCALL_REG:
2095                 case OP_VOIDCALL_REG:
2096                 case OP_CALL_REG:
2097                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2098                         ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
2099                         break;
2100                 case OP_FCALL_MEMBASE:
2101                 case OP_LCALL_MEMBASE:
2102                 case OP_VCALL_MEMBASE:
2103                 case OP_VOIDCALL_MEMBASE:
2104                 case OP_CALL_MEMBASE:
2105                         g_assert (arm_is_imm12 (ins->inst_offset));
2106                         g_assert (ins->sreg1 != ARMREG_LR);
2107                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2108                         ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
2109                         break;
2110                 case OP_OUTARG:
2111                         g_assert_not_reached ();
2112                         break;
2113                 case OP_LOCALLOC: {
2114                         /* keep alignment */
2115                         int alloca_waste = cfg->param_area;
2116                         alloca_waste += 7;
2117                         alloca_waste &= ~7;
2118                         /* round the size to 8 bytes */
2119                         ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
2120                         ARM_BIC_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
2121                         ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
2122                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
2123                         /* memzero the area: dreg holds the size, sp is the pointer */
2124                         if (ins->flags & MONO_INST_INIT) {
2125                                 guint8 *start_loop, *branch_to_cond;
2126                                 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
2127                                 branch_to_cond = code;
2128                                 ARM_B (code, 0);
2129                                 start_loop = code;
2130                                 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
2131                                 arm_patch (branch_to_cond, code);
2132                                 /* decrement by 4 and set flags */
2133                                 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, 4);
2134                                 ARM_B_COND (code, ARMCOND_LT, 0);
2135                                 arm_patch (code - 4, start_loop);
2136                         }
2137                         ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
2138                         break;
2139                 }
2140                 case CEE_RET:
2141                         g_assert_not_reached ();
2142                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_LR);
2143                         break;
2144                 case CEE_THROW: {
2145                         if (ins->sreg1 != ARMREG_R0)
2146                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
2147                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2148                                              (gpointer)"mono_arch_throw_exception");
2149                         if (cfg->method->dynamic) {
2150                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2151                                 ARM_B (code, 0);
2152                                 *(gpointer*)code = NULL;
2153                                 code += 4;
2154                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2155                                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2156                         } else {
2157                                 ARM_BL (code, 0);
2158                         }
2159                         break;
2160                 }
2161                 case OP_RETHROW: {
2162                         if (ins->sreg1 != ARMREG_R0)
2163                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
2164                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2165                                              (gpointer)"mono_arch_rethrow_exception");
2166                         if (cfg->method->dynamic) {
2167                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2168                                 ARM_B (code, 0);
2169                                 *(gpointer*)code = NULL;
2170                                 code += 4;
2171                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2172                                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2173                         } else {
2174                                 ARM_BL (code, 0);
2175                         }
2176                         break;
2177                 }
2178                 case OP_START_HANDLER:
2179                         if (arm_is_imm12 (ins->inst_left->inst_offset)) {
2180                                 ARM_STR_IMM (code, ARMREG_LR, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
2181                         } else {
2182                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_left->inst_offset);
2183                                 ARM_STR_REG_REG (code, ARMREG_LR, ins->inst_left->inst_basereg, ARMREG_IP);
2184                         }
2185                         break;
2186                 case OP_ENDFILTER:
2187                         if (ins->sreg1 != ARMREG_R0)
2188                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
2189                         if (arm_is_imm12 (ins->inst_left->inst_offset)) {
2190                                 ARM_LDR_IMM (code, ARMREG_IP, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
2191                         } else {
2192                                 g_assert (ARMREG_IP != ins->inst_left->inst_basereg);
2193                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_left->inst_offset);
2194                                 ARM_LDR_REG_REG (code, ARMREG_IP, ins->inst_left->inst_basereg, ARMREG_IP);
2195                         }
2196                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2197                         break;
2198                 case CEE_ENDFINALLY:
2199                         if (arm_is_imm12 (ins->inst_left->inst_offset)) {
2200                                 ARM_LDR_IMM (code, ARMREG_IP, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
2201                         } else {
2202                                 g_assert (ARMREG_IP != ins->inst_left->inst_basereg);
2203                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_left->inst_offset);
2204                                 ARM_LDR_REG_REG (code, ARMREG_IP, ins->inst_left->inst_basereg, ARMREG_IP);
2205                         }
2206                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2207                         break;
2208                 case OP_CALL_HANDLER:
2209                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2210                         ARM_BL (code, 0);
2211                         break;
2212                 case OP_LABEL:
2213                         ins->inst_c0 = code - cfg->native_code;
2214                         break;
2215                 case CEE_BR:
2216                         if (ins->flags & MONO_INST_BRLABEL) {
2217                                 /*if (ins->inst_i0->inst_c0) {
2218                                         ARM_B (code, 0);
2219                                         //x86_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
2220                                 } else*/ {
2221                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2222                                         ARM_B (code, 0);
2223                                 }
2224                         } else {
2225                                 /*if (ins->inst_target_bb->native_offset) {
2226                                         ARM_B (code, 0);
2227                                         //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2228                                 } else*/ {
2229                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2230                                         ARM_B (code, 0);
2231                                 }
2232                         }
2233                         break;
2234                 case OP_BR_REG:
2235                         ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
2236                         break;
2237                 case CEE_SWITCH:
2238                         /*
2239                          * In the normal case we have:
2240                          *      ldr pc, [pc, ins->sreg1 << 2]
2241                          *      nop
2242                          * If aot, we have:
2243                          *      ldr lr, [pc, ins->sreg1 << 2]
2244                          *      add pc, pc, lr
2245                          * After follows the data.
2246                          * FIXME: add aot support.
2247                          */
2248                         max_len += 4 * GPOINTER_TO_INT (ins->klass);
2249                         if (offset > (cfg->code_size - max_len - 16)) {
2250                                 cfg->code_size += max_len;
2251                                 cfg->code_size *= 2;
2252                                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2253                                 code = cfg->native_code + offset;
2254                         }
2255                         ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
2256                         ARM_NOP (code);
2257                         code += 4 * GPOINTER_TO_INT (ins->klass);
2258                         break;
2259                 case OP_CEQ:
2260                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2261                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
2262                         break;
2263                 case OP_CLT:
2264                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2265                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
2266                         break;
2267                 case OP_CLT_UN:
2268                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2269                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
2270                         break;
2271                 case OP_CGT:
2272                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2273                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
2274                         break;
2275                 case OP_CGT_UN:
2276                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2277                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
2278                         break;
2279                 case OP_COND_EXC_EQ:
2280                 case OP_COND_EXC_NE_UN:
2281                 case OP_COND_EXC_LT:
2282                 case OP_COND_EXC_LT_UN:
2283                 case OP_COND_EXC_GT:
2284                 case OP_COND_EXC_GT_UN:
2285                 case OP_COND_EXC_GE:
2286                 case OP_COND_EXC_GE_UN:
2287                 case OP_COND_EXC_LE:
2288                 case OP_COND_EXC_LE_UN:
2289                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
2290                         break;
2291                 case OP_COND_EXC_C:
2292                 case OP_COND_EXC_OV:
2293                 case OP_COND_EXC_NC:
2294                 case OP_COND_EXC_NO:
2295                         g_assert_not_reached ();
2296                         break;
2297                 case CEE_BEQ:
2298                 case CEE_BNE_UN:
2299                 case CEE_BLT:
2300                 case CEE_BLT_UN:
2301                 case CEE_BGT:
2302                 case CEE_BGT_UN:
2303                 case CEE_BGE:
2304                 case CEE_BGE_UN:
2305                 case CEE_BLE:
2306                 case CEE_BLE_UN:
2307                         EMIT_COND_BRANCH (ins, ins->opcode - CEE_BEQ);
2308                         break;
2309
2310                 /* floating point opcodes */
2311                 case OP_R8CONST:
2312                         /* FIXME: we can optimize the imm load by dealing with part of
2313                          * the displacement in LDFD (aligning to 512).
2314                          */
2315                         code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
2316                         ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
2317                         break;
2318                 case OP_R4CONST:
2319                         code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
2320                         ARM_LDFS (code, ins->dreg, ARMREG_LR, 0);
2321                         break;
2322                 case OP_STORER8_MEMBASE_REG:
2323                         g_assert (arm_is_fpimm8 (ins->inst_offset));
2324                         ARM_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
2325                         break;
2326                 case OP_LOADR8_MEMBASE:
2327                         g_assert (arm_is_fpimm8 (ins->inst_offset));
2328                         ARM_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2329                         break;
2330                 case OP_STORER4_MEMBASE_REG:
2331                         g_assert (arm_is_fpimm8 (ins->inst_offset));
2332                         ARM_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
2333                         break;
2334                 case OP_LOADR4_MEMBASE:
2335                         g_assert (arm_is_fpimm8 (ins->inst_offset));
2336                         ARM_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2337                         break;
2338                 case CEE_CONV_R_UN: {
2339                         int tmpreg;
2340                         tmpreg = ins->dreg == 0? 1: 0;
2341                         ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
2342                         ARM_FLTD (code, ins->dreg, ins->sreg1);
2343                         ARM_B_COND (code, ARMCOND_GE, 8);
2344                         /* save the temp register */
2345                         ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
2346                         ARM_STFD (code, tmpreg, ARMREG_SP, 0);
2347                         ARM_LDFD (code, tmpreg, ARMREG_PC, 4);
2348                         ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
2349                         ARM_LDFD (code, tmpreg, ARMREG_SP, 0);
2350                         ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
2351                         /* skip the constant pool */
2352                         ARM_B (code, 4);
2353                         *(int*)code = 0x41f00000;
2354                         code += 4;
2355                         *(int*)code = 0;
2356                         code += 4;
2357                         /* FIXME: adjust:
2358                          * ldfltd  ftemp, [pc, #8] 0x41f00000 0x00000000
2359                          * adfltd  fdest, fdest, ftemp
2360                          */
2361                         break;
2362                 }
2363                 case CEE_CONV_R4:
2364                         ARM_FLTS (code, ins->dreg, ins->sreg1);
2365                         break;
2366                 case CEE_CONV_R8:
2367                         ARM_FLTD (code, ins->dreg, ins->sreg1);
2368                         break;
2369                 case OP_X86_FP_LOAD_I8:
2370                         g_assert_not_reached ();
2371                         /*x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);*/
2372                         break;
2373                 case OP_X86_FP_LOAD_I4:
2374                         g_assert_not_reached ();
2375                         /*x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);*/
2376                         break;
2377                 case OP_FCONV_TO_I1:
2378                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
2379                         break;
2380                 case OP_FCONV_TO_U1:
2381                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
2382                         break;
2383                 case OP_FCONV_TO_I2:
2384                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
2385                         break;
2386                 case OP_FCONV_TO_U2:
2387                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
2388                         break;
2389                 case OP_FCONV_TO_I4:
2390                 case OP_FCONV_TO_I:
2391                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
2392                         break;
2393                 case OP_FCONV_TO_U4:
2394                 case OP_FCONV_TO_U:
2395                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
2396                         break;
2397                 case OP_FCONV_TO_I8:
2398                 case OP_FCONV_TO_U8:
2399                         g_assert_not_reached ();
2400                         /* Implemented as helper calls */
2401                         break;
2402                 case OP_LCONV_TO_R_UN:
2403                         g_assert_not_reached ();
2404                         /* Implemented as helper calls */
2405                         break;
2406                 case OP_LCONV_TO_OVF_I: {
2407 #if ARM_PORT
2408                         guint32 *negative_branch, *msword_positive_branch, *msword_negative_branch, *ovf_ex_target;
2409                         // Check if its negative
2410                         ppc_cmpi (code, 0, 0, ins->sreg1, 0);
2411                         negative_branch = code;
2412                         ppc_bc (code, PPC_BR_TRUE, PPC_BR_LT, 0);
2413                         // Its positive msword == 0
2414                         ppc_cmpi (code, 0, 0, ins->sreg2, 0);
2415                         msword_positive_branch = code;
2416                         ppc_bc (code, PPC_BR_TRUE, PPC_BR_EQ, 0);
2417
2418                         ovf_ex_target = code;
2419                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_ALWAYS, 0, "OverflowException");
2420                         // Negative
2421                         ppc_patch (negative_branch, code);
2422                         ppc_cmpi (code, 0, 0, ins->sreg2, -1);
2423                         msword_negative_branch = code;
2424                         ppc_bc (code, PPC_BR_FALSE, PPC_BR_EQ, 0);
2425                         ppc_patch (msword_negative_branch, ovf_ex_target);
2426
2427                         ppc_patch (msword_positive_branch, code);
2428                         if (ins->dreg != ins->sreg1)
2429                                 ppc_mr (code, ins->dreg, ins->sreg1);
2430 #endif
2431                         if (ins->dreg != ins->sreg1)
2432                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
2433                         break;
2434                 }
2435                 case OP_FADD:
2436                         ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2437                         break;
2438                 case OP_FSUB:
2439                         ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2440                         break;
2441                 case OP_FMUL:
2442                         ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2443                         break;
2444                 case OP_FDIV:
2445                         ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2446                         break;
2447                 case OP_FNEG:
2448                         ARM_MNFD (code, ins->dreg, ins->sreg1);
2449                         break;
2450                 case OP_FREM:
2451                         /* emulated */
2452                         g_assert_not_reached ();
2453                         break;
2454                 case OP_FCOMPARE:
2455                         /* each fp compare op needs to do its own */
2456                         g_assert_not_reached ();
2457                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2458                         break;
2459                 case OP_FCEQ:
2460                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2461                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2462                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
2463                         break;
2464                 case OP_FCLT:
2465                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2466                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2467                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2468                         break;
2469                 case OP_FCLT_UN:
2470                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2471                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2472                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2473                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
2474                         break;
2475                 case OP_FCGT:
2476                         /* swapped */
2477                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2478                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2479                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2480                         break;
2481                 case OP_FCGT_UN:
2482                         /* swapped */
2483                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2484                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2485                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2486                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
2487                         break;
2488                 /* ARM FPA flags table:
2489                  * N        Less than               ARMCOND_MI
2490                  * Z        Equal                   ARMCOND_EQ
2491                  * C        Greater Than or Equal   ARMCOND_CS
2492                  * V        Unordered               ARMCOND_VS
2493                  */
2494                 case OP_FBEQ:
2495                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2496                         EMIT_COND_BRANCH (ins, CEE_BEQ - CEE_BEQ);
2497                         break;
2498                 case OP_FBNE_UN:
2499                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2500                         EMIT_COND_BRANCH (ins, CEE_BNE_UN - CEE_BEQ);
2501                         break;
2502                 case OP_FBLT:
2503                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2504                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
2505                         break;
2506                 case OP_FBLT_UN:
2507                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2508                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2509                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
2510                         break;
2511                 case OP_FBGT:
2512                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2513                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set, swapped args */
2514                         break;
2515                 case OP_FBGT_UN:
2516                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2517                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2518                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set, swapped args */
2519                         break;
2520                 case OP_FBGE:
2521                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2522                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
2523                         break;
2524                 case OP_FBGE_UN:
2525                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2526                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2527                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
2528                         break;
2529                 case OP_FBLE:
2530                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2531                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS); /* swapped */
2532                         break;
2533                 case OP_FBLE_UN:
2534                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2535                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2536                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS); /* swapped */
2537                         break;
2538                 case CEE_CKFINITE: {
2539                         /*ppc_stfd (code, ins->sreg1, -8, ppc_sp);
2540                         ppc_lwz (code, ppc_r11, -8, ppc_sp);
2541                         ppc_rlwinm (code, ppc_r11, ppc_r11, 0, 1, 31);
2542                         ppc_addis (code, ppc_r11, ppc_r11, -32752);
2543                         ppc_rlwinmd (code, ppc_r11, ppc_r11, 1, 31, 31);
2544                         EMIT_COND_SYSTEM_EXCEPTION (CEE_BEQ - CEE_BEQ, "ArithmeticException");*/
2545                         g_assert_not_reached ();
2546                         break;
2547                 }
2548                 default:
2549                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
2550                         g_assert_not_reached ();
2551                 }
2552
2553                 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
2554                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
2555                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
2556                         g_assert_not_reached ();
2557                 }
2558
2559                 cpos += max_len;
2560
2561                 last_ins = ins;
2562                 last_offset = offset;
2563
2564                 ins = ins->next;
2565         }
2566
2567         cfg->code_len = code - cfg->native_code;
2568 }
2569
2570 void
2571 mono_arch_register_lowlevel_calls (void)
2572 {
2573 }
2574
2575 #define patch_lis_ori(ip,val) do {\
2576                 guint16 *__lis_ori = (guint16*)(ip);    \
2577                 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff;      \
2578                 __lis_ori [3] = ((guint32)(val)) & 0xffff;      \
2579         } while (0)
2580
2581 void
2582 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
2583 {
2584         MonoJumpInfo *patch_info;
2585
2586         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
2587                 unsigned char *ip = patch_info->ip.i + code;
2588                 const unsigned char *target;
2589
2590                 if (patch_info->type == MONO_PATCH_INFO_SWITCH) {
2591                         gpointer *table = (gpointer *)patch_info->data.table->table;
2592                         gpointer *jt = (gpointer*)(ip + 8);
2593                         int i;
2594                         /* jt is the inlined jump table, 2 instructions after ip
2595                          * In the normal case we store the absolute addresses,
2596                          * otherwise the displacements.
2597                          */
2598                         for (i = 0; i < patch_info->data.table->table_size; i++) {
2599                                 jt [i] = code + (int)patch_info->data.table->table [i];
2600                         }
2601                         continue;
2602                 }
2603                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
2604
2605                 switch (patch_info->type) {
2606                 case MONO_PATCH_INFO_IP:
2607                         g_assert_not_reached ();
2608                         patch_lis_ori (ip, ip);
2609                         continue;
2610                 case MONO_PATCH_INFO_METHOD_REL:
2611                         g_assert_not_reached ();
2612                         *((gpointer *)(ip)) = code + patch_info->data.offset;
2613                         continue;
2614                 case MONO_PATCH_INFO_METHODCONST:
2615                 case MONO_PATCH_INFO_CLASS:
2616                 case MONO_PATCH_INFO_IMAGE:
2617                 case MONO_PATCH_INFO_FIELD:
2618                 case MONO_PATCH_INFO_VTABLE:
2619                 case MONO_PATCH_INFO_IID:
2620                 case MONO_PATCH_INFO_SFLDA:
2621                 case MONO_PATCH_INFO_LDSTR:
2622                 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
2623                 case MONO_PATCH_INFO_LDTOKEN:
2624                         g_assert_not_reached ();
2625                         /* from OP_AOTCONST : lis + ori */
2626                         patch_lis_ori (ip, target);
2627                         continue;
2628                 case MONO_PATCH_INFO_R4:
2629                 case MONO_PATCH_INFO_R8:
2630                         g_assert_not_reached ();
2631                         *((gconstpointer *)(ip + 2)) = patch_info->data.target;
2632                         continue;
2633                 case MONO_PATCH_INFO_EXC_NAME:
2634                         g_assert_not_reached ();
2635                         *((gconstpointer *)(ip + 1)) = patch_info->data.name;
2636                         continue;
2637                 case MONO_PATCH_INFO_NONE:
2638                 case MONO_PATCH_INFO_BB_OVF:
2639                 case MONO_PATCH_INFO_EXC_OVF:
2640                         /* everything is dealt with at epilog output time */
2641                         continue;
2642                 default:
2643                         break;
2644                 }
2645                 arm_patch (ip, target);
2646         }
2647 }
2648
2649 /*
2650  * Stack frame layout:
2651  *
2652  *   ------------------- fp
2653  *      MonoLMF structure or saved registers
2654  *   -------------------
2655  *      locals
2656  *   -------------------
2657  *      spilled regs
2658  *   -------------------
2659  *      optional 8 bytes for tracing
2660  *   -------------------
2661  *      param area             size is cfg->param_area
2662  *   ------------------- sp
2663  */
2664 guint8 *
2665 mono_arch_emit_prolog (MonoCompile *cfg)
2666 {
2667         MonoMethod *method = cfg->method;
2668         MonoBasicBlock *bb;
2669         MonoMethodSignature *sig;
2670         MonoInst *inst;
2671         int alloc_size, pos, max_offset, i, rot_amount;
2672         guint8 *code;
2673         CallInfo *cinfo;
2674         int tracing = 0;
2675         int lmf_offset = 0;
2676         int prev_sp_offset;
2677
2678         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
2679                 tracing = 1;
2680
2681         sig = mono_method_signature (method);
2682         cfg->code_size = 256 + sig->param_count * 20;
2683         code = cfg->native_code = g_malloc (cfg->code_size);
2684
2685         ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
2686
2687         alloc_size = cfg->stack_offset;
2688         pos = 0;
2689
2690         if (!method->save_lmf) {
2691                 ARM_PUSH (code, (cfg->used_int_regs | (1 << ARMREG_IP) | (1 << ARMREG_LR)));
2692                 prev_sp_offset = 8; /* ip and lr */
2693                 for (i = 0; i < 16; ++i) {
2694                         if (cfg->used_int_regs & (1 << i))
2695                                 prev_sp_offset += 4;
2696                 }
2697         } else {
2698                 ARM_PUSH (code, 0x5ff0);
2699                 prev_sp_offset = 4 * 10; /* all but r0-r3, sp and pc */
2700                 pos += sizeof (MonoLMF) - prev_sp_offset;
2701                 lmf_offset = pos;
2702         }
2703         alloc_size += pos;
2704         // align to MONO_ARCH_FRAME_ALIGNMENT bytes
2705         if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
2706                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
2707                 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
2708         }
2709
2710         /* the stack used in the pushed regs */
2711         if (prev_sp_offset & 4)
2712                 alloc_size += 4;
2713         cfg->stack_usage = alloc_size;
2714         if (alloc_size) {
2715                 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
2716                         ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
2717                 } else {
2718                         code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
2719                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
2720                 }
2721         }
2722         if (cfg->frame_reg != ARMREG_SP)
2723                 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
2724         //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
2725         prev_sp_offset += alloc_size;
2726
2727         /* compute max_offset in order to use short forward jumps
2728          * we could skip do it on arm because the immediate displacement
2729          * for jumps is large enough, it may be useful later for constant pools
2730          */
2731         max_offset = 0;
2732         for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
2733                 MonoInst *ins = bb->code;
2734                 bb->max_offset = max_offset;
2735
2736                 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
2737                         max_offset += 6;
2738
2739                 while (ins) {
2740                         max_offset += ((guint8 *)arm_cpu_desc [ins->opcode])[MONO_INST_LEN];
2741                         ins = ins->next;
2742                 }
2743         }
2744
2745         /* load arguments allocated to register from the stack */
2746         pos = 0;
2747
2748         cinfo = calculate_sizes (sig, sig->pinvoke);
2749
2750         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
2751                 ArgInfo *ainfo = &cinfo->ret;
2752                 inst = cfg->ret;
2753                 g_assert (arm_is_imm12 (inst->inst_offset));
2754                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2755         }
2756         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2757                 ArgInfo *ainfo = cinfo->args + i;
2758                 inst = cfg->varinfo [pos];
2759
2760                 if (cfg->verbose_level > 2)
2761                         g_print ("Saving argument %d (type: %d)\n", i, ainfo->regtype);
2762                 if (inst->opcode == OP_REGVAR) {
2763                         if (ainfo->regtype == RegTypeGeneral)
2764                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
2765                         else if (ainfo->regtype == RegTypeFP) {
2766                                 g_assert_not_reached ();
2767                         } else if (ainfo->regtype == RegTypeBase) {
2768                                 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
2769                                 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2770                         } else
2771                                 g_assert_not_reached ();
2772
2773                         if (cfg->verbose_level > 2)
2774                                 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
2775                 } else {
2776                         /* the argument should be put on the stack: FIXME handle size != word  */
2777                         if (ainfo->regtype == RegTypeGeneral) {
2778                                 switch (ainfo->size) {
2779                                 case 1:
2780                                         if (arm_is_imm12 (inst->inst_offset))
2781                                                 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2782                                         else {
2783                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
2784                                                 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
2785                                         }
2786                                         break;
2787                                 case 2:
2788                                         g_assert (arm_is_imm8 (inst->inst_offset));
2789                                         ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2790                                         break;
2791                                 case 8:
2792                                         g_assert (arm_is_imm12 (inst->inst_offset));
2793                                         ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2794                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
2795                                         ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
2796                                         break;
2797                                 default:
2798                                         if (arm_is_imm12 (inst->inst_offset)) {
2799                                                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2800                                         } else {
2801                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
2802                                                 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
2803                                         }
2804                                         break;
2805                                 }
2806                         } else if (ainfo->regtype == RegTypeBase) {
2807                                 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
2808                                 switch (ainfo->size) {
2809                                 case 1:
2810                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2811                                         g_assert (arm_is_imm12 (inst->inst_offset));
2812                                         ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2813                                         break;
2814                                 case 2:
2815                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2816                                         g_assert (arm_is_imm8 (inst->inst_offset));
2817                                         ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2818                                         break;
2819                                 case 8:
2820                                         g_assert (arm_is_imm12 (inst->inst_offset));
2821                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2822                                         ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2823                                         g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4));
2824                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
2825                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
2826                                         ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
2827                                         break;
2828                                 default:
2829                                         g_assert (arm_is_imm12 (inst->inst_offset));
2830                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2831                                         ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2832                                         break;
2833                                 }
2834                         } else if (ainfo->regtype == RegTypeFP) {
2835                                 g_assert_not_reached ();
2836                         } else if (ainfo->regtype == RegTypeStructByVal) {
2837                                 int doffset = inst->inst_offset;
2838                                 int soffset = 0;
2839                                 int cur_reg;
2840                                 int size = 0;
2841                                 if (mono_class_from_mono_type (inst->inst_vtype))
2842                                         size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
2843                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
2844                                         g_assert (arm_is_imm12 (doffset));
2845                                         ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
2846                                         soffset += sizeof (gpointer);
2847                                         doffset += sizeof (gpointer);
2848                                 }
2849                                 if (ainfo->vtsize) {
2850                                         /* FIXME: handle overrun! with struct sizes not multiple of 4 */
2851                                         //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
2852                                         code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
2853                                 }
2854                         } else if (ainfo->regtype == RegTypeStructByAddr) {
2855                                 g_assert_not_reached ();
2856                                 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
2857                                 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
2858                         } else
2859                                 g_assert_not_reached ();
2860                 }
2861                 pos++;
2862         }
2863
2864         if (method->save_lmf) {
2865
2866                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2867                              (gpointer)"mono_get_lmf_addr");
2868                 if (cfg->method->dynamic) {
2869                         ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2870                         ARM_B (code, 0);
2871                         *(gpointer*)code = NULL;
2872                         code += 4;
2873                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2874                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2875                 } else {
2876                         ARM_BL (code, 0);
2877                 }
2878                 /* we build the MonoLMF structure on the stack - see mini-arm.h */
2879                 /* lmf_offset is the offset from the previous stack pointer,
2880                  * alloc_size is the total stack space allocated, so the offset
2881                  * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
2882                  * The pointer to the struct is put in r1 (new_lmf).
2883                  * r2 is used as scratch
2884                  * The callee-saved registers are already in the MonoLMF structure
2885                  */
2886                 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, alloc_size - lmf_offset);
2887                 /* r0 is the result from mono_get_lmf_addr () */
2888                 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
2889                 /* new_lmf->previous_lmf = *lmf_addr */
2890                 ARM_LDR_IMM (code, ARMREG_R2, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2891                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2892                 /* *(lmf_addr) = r1 */
2893                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2894                 /* save method info */
2895                 code = mono_arm_emit_load_imm (code, ARMREG_R2, method);
2896                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, method));
2897                 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ebp));
2898                 /* save the current IP */
2899                 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
2900                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, eip));
2901         }
2902
2903         if (tracing)
2904                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
2905
2906         cfg->code_len = code - cfg->native_code;
2907         g_assert (cfg->code_len < cfg->code_size);
2908         g_free (cinfo);
2909
2910         return code;
2911 }
2912
2913 void
2914 mono_arch_emit_epilog (MonoCompile *cfg)
2915 {
2916         MonoJumpInfo *patch_info;
2917         MonoMethod *method = cfg->method;
2918         int pos, i, rot_amount;
2919         int max_epilog_size = 16 + 20*4;
2920         guint8 *code;
2921
2922         if (cfg->method->save_lmf)
2923                 max_epilog_size += 128;
2924
2925         if (mono_jit_trace_calls != NULL)
2926                 max_epilog_size += 50;
2927
2928         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2929                 max_epilog_size += 50;
2930
2931         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
2932                 cfg->code_size *= 2;
2933                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2934                 mono_jit_stats.code_reallocs++;
2935         }
2936
2937         /*
2938          * Keep in sync with CEE_JMP
2939          */
2940         code = cfg->native_code + cfg->code_len;
2941
2942         if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
2943                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
2944         }
2945         pos = 0;
2946
2947         if (method->save_lmf) {
2948                 int lmf_offset;
2949                 /* all but r0-r3, sp and pc */
2950                 pos += sizeof (MonoLMF) - (4 * 10);
2951                 lmf_offset = pos;
2952                 /* r2 contains the pointer to the current LMF */
2953                 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, cfg->stack_usage - lmf_offset);
2954                 /* ip = previous_lmf */
2955                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2956                 /* lr = lmf_addr */
2957                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
2958                 /* *(lmf_addr) = previous_lmf */
2959                 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2960                 /* FIXME: speedup: there is no actual need to restore the registers if
2961                  * we didn't actually change them (idea from Zoltan).
2962                  */
2963                 /* restore iregs */
2964                 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
2965                 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_R2, (sizeof (MonoLMF) - 10 * sizeof (gulong)));
2966                 ARM_POP_NWB (code, 0xaff0); /* restore ip to sp and lr to pc */
2967         } else {
2968                 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
2969                         ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
2970                 } else {
2971                         code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
2972                         ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
2973                 }
2974                 ARM_POP_NWB (code, cfg->used_int_regs | ((1 << ARMREG_SP) | (1 << ARMREG_PC)));
2975         }
2976
2977         cfg->code_len = code - cfg->native_code;
2978
2979         g_assert (cfg->code_len < cfg->code_size);
2980
2981 }
2982
2983 /* remove once throw_exception_by_name is eliminated */
2984 static int
2985 exception_id_by_name (const char *name)
2986 {
2987         if (strcmp (name, "IndexOutOfRangeException") == 0)
2988                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2989         if (strcmp (name, "OverflowException") == 0)
2990                 return MONO_EXC_OVERFLOW;
2991         if (strcmp (name, "ArithmeticException") == 0)
2992                 return MONO_EXC_ARITHMETIC;
2993         if (strcmp (name, "DivideByZeroException") == 0)
2994                 return MONO_EXC_DIVIDE_BY_ZERO;
2995         if (strcmp (name, "InvalidCastException") == 0)
2996                 return MONO_EXC_INVALID_CAST;
2997         if (strcmp (name, "NullReferenceException") == 0)
2998                 return MONO_EXC_NULL_REF;
2999         if (strcmp (name, "ArrayTypeMismatchException") == 0)
3000                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
3001         g_error ("Unknown intrinsic exception %s\n", name);
3002 }
3003
3004 void
3005 mono_arch_emit_exceptions (MonoCompile *cfg)
3006 {
3007         MonoJumpInfo *patch_info;
3008         int nthrows, i;
3009         guint8 *code;
3010         const guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM] = {NULL};
3011         guint8 exc_throw_found [MONO_EXC_INTRINS_NUM] = {0};
3012         guint32 code_size;
3013         int exc_count = 0;
3014         int max_epilog_size = 50;
3015
3016         /* count the number of exception infos */
3017
3018         /*
3019          * make sure we have enough space for exceptions
3020          * 12 is the simulated call to throw_exception_by_name
3021          */
3022         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3023                 if (patch_info->type == MONO_PATCH_INFO_EXC) {
3024                         i = exception_id_by_name (patch_info->data.target);
3025                         if (!exc_throw_found [i]) {
3026                                 max_epilog_size += 12;
3027                                 exc_throw_found [i] = TRUE;
3028                         }
3029                 }
3030         }
3031
3032         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
3033                 cfg->code_size *= 2;
3034                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3035                 mono_jit_stats.code_reallocs++;
3036         }
3037
3038         code = cfg->native_code + cfg->code_len;
3039
3040         /* add code to raise exceptions */
3041         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3042                 switch (patch_info->type) {
3043                 case MONO_PATCH_INFO_EXC: {
3044                         unsigned char *ip = patch_info->ip.i + cfg->native_code;
3045                         const char *ex_name = patch_info->data.target;
3046                         i = exception_id_by_name (patch_info->data.target);
3047                         if (exc_throw_pos [i]) {
3048                                 arm_patch (ip, exc_throw_pos [i]);
3049                                 patch_info->type = MONO_PATCH_INFO_NONE;
3050                                 break;
3051                         } else {
3052                                 exc_throw_pos [i] = code;
3053                         }
3054                         arm_patch (ip, code);
3055                         //*(int*)code = 0xef9f0001;
3056                         code += 4;
3057                         /*mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC_NAME, patch_info->data.target);*/
3058                         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
3059                         /* we got here from a conditional call, so the calling ip is set in lr already */
3060                         patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
3061                         patch_info->data.name = "mono_arch_throw_exception_by_name";
3062                         patch_info->ip.i = code - cfg->native_code;
3063                         ARM_B (code, 0);
3064                         *(gpointer*)code = ex_name;
3065                         code += 4;
3066                         break;
3067                 }
3068                 default:
3069                         /* do nothing */
3070                         break;
3071                 }
3072         }
3073
3074         cfg->code_len = code - cfg->native_code;
3075
3076         g_assert (cfg->code_len < cfg->code_size);
3077
3078 }
3079
3080 void
3081 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
3082 {
3083 }
3084
3085 void
3086 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
3087 {
3088 }
3089
3090 void
3091 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
3092 {
3093
3094         int this_dreg = ARMREG_R0;
3095
3096         if (vt_reg != -1)
3097                 this_dreg = ARMREG_R1;
3098
3099         /* add the this argument */
3100         if (this_reg != -1) {
3101                 MonoInst *this;
3102                 MONO_INST_NEW (cfg, this, OP_SETREG);
3103                 this->type = this_type;
3104                 this->sreg1 = this_reg;
3105                 this->dreg = mono_regstate_next_int (cfg->rs);
3106                 mono_bblock_add_inst (cfg->cbb, this);
3107                 mono_call_inst_add_outarg_reg (inst, this->dreg, this_dreg, FALSE);
3108         }
3109
3110         if (vt_reg != -1) {
3111                 MonoInst *vtarg;
3112                 MONO_INST_NEW (cfg, vtarg, OP_SETREG);
3113                 vtarg->type = STACK_MP;
3114                 vtarg->sreg1 = vt_reg;
3115                 vtarg->dreg = mono_regstate_next_int (cfg->rs);
3116                 mono_bblock_add_inst (cfg->cbb, vtarg);
3117                 mono_call_inst_add_outarg_reg (inst, vtarg->dreg, ARMREG_R0, FALSE);
3118         }
3119 }
3120
3121 MonoInst*
3122 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
3123 {
3124         return NULL;
3125 }
3126
3127 gboolean
3128 mono_arch_print_tree (MonoInst *tree, int arity)
3129 {
3130         return 0;
3131 }
3132
3133 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
3134 {
3135         return NULL;
3136 }
3137
3138 MonoInst*
3139 mono_arch_get_thread_intrinsic (MonoCompile* cfg)
3140 {
3141         return NULL;
3142 }
3143
3144 void
3145 mono_arch_flush_register_windows (void)
3146 {
3147 }
3148
3149 void
3150 mono_arch_fixup_jinfo (MonoCompile *cfg)
3151 {
3152         /* max encoded stack usage is 64KB * 4 */
3153         g_assert ((cfg->stack_usage & ~(0xffff << 2)) == 0);
3154         cfg->jit_info->used_regs |= cfg->stack_usage << 14;
3155 }
3156