2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
24 #include "mini-arm-tls.h"
28 #include "debugger-agent.h"
30 #include "mono/arch/arm/arm-vfp-codegen.h"
32 #if defined(HAVE_KW_THREAD) && defined(__linux__) \
33 || defined(TARGET_ANDROID) \
34 || defined(TARGET_IOS)
38 /* Sanity check: This makes no sense */
39 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
40 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
44 * IS_SOFT_FLOAT: Is full software floating point used?
45 * IS_HARD_FLOAT: Is full hardware floating point used?
46 * IS_VFP: Is hardware floating point with software ABI used?
48 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
49 * IS_VFP may delegate to mono_arch_is_soft_float ().
52 #if defined(ARM_FPU_VFP_HARD)
53 #define IS_SOFT_FLOAT (FALSE)
54 #define IS_HARD_FLOAT (TRUE)
56 #elif defined(ARM_FPU_NONE)
57 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
58 #define IS_HARD_FLOAT (FALSE)
59 #define IS_VFP (!mono_arch_is_soft_float ())
61 #define IS_SOFT_FLOAT (FALSE)
62 #define IS_HARD_FLOAT (FALSE)
66 #define THUNK_SIZE (3 * 4)
68 #ifdef __native_client_codegen__
69 const guint kNaClAlignment = kNaClAlignmentARM;
70 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
71 gint8 nacl_align_byte = -1; /* 0xff */
74 mono_arch_nacl_pad (guint8 *code, int pad)
76 /* Not yet properly implemented. */
77 g_assert_not_reached ();
82 mono_arch_nacl_skip_nops (guint8 *code)
84 /* Not yet properly implemented. */
85 g_assert_not_reached ();
89 #endif /* __native_client_codegen__ */
91 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
94 void sys_icache_invalidate (void *start, size_t len);
97 /* This mutex protects architecture specific caches */
98 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
99 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
100 static mono_mutex_t mini_arch_mutex;
102 static gboolean v5_supported = FALSE;
103 static gboolean v6_supported = FALSE;
104 static gboolean v7_supported = FALSE;
105 static gboolean v7s_supported = FALSE;
106 static gboolean thumb_supported = FALSE;
107 static gboolean thumb2_supported = FALSE;
109 * Whenever to use the ARM EABI
111 static gboolean eabi_supported = FALSE;
114 * Whenever to use the iphone ABI extensions:
115 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
116 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
117 * This is required for debugging/profiling tools to work, but it has some overhead so it should
118 * only be turned on in debug builds.
120 static gboolean iphone_abi = FALSE;
123 * The FPU we are generating code for. This is NOT runtime configurable right now,
124 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
126 static MonoArmFPU arm_fpu;
128 #if defined(ARM_FPU_VFP_HARD)
130 * On armhf, d0-d7 are used for argument passing and d8-d15
131 * must be preserved across calls, which leaves us no room
132 * for scratch registers. So we use d14-d15 but back up their
133 * previous contents to a stack slot before using them - see
134 * mono_arm_emit_vfp_scratch_save/_restore ().
136 static int vfp_scratch1 = ARM_VFP_D14;
137 static int vfp_scratch2 = ARM_VFP_D15;
140 * On armel, d0-d7 do not need to be preserved, so we can
141 * freely make use of them as scratch registers.
143 static int vfp_scratch1 = ARM_VFP_D0;
144 static int vfp_scratch2 = ARM_VFP_D1;
149 static volatile int ss_trigger_var = 0;
151 static gpointer single_step_tramp, breakpoint_tramp;
154 * The code generated for sequence points reads from this location, which is
155 * made read-only when single stepping is enabled.
157 static gpointer ss_trigger_page;
159 /* Enabled breakpoints read from this trigger page */
160 static gpointer bp_trigger_page;
164 * floating point support: on ARM it is a mess, there are at least 3
165 * different setups, each of which binary incompat with the other.
166 * 1) FPA: old and ugly, but unfortunately what current distros use
167 * the double binary format has the two words swapped. 8 double registers.
168 * Implemented usually by kernel emulation.
169 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
170 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
171 * 3) VFP: the new and actually sensible and useful FP support. Implemented
172 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
174 * We do not care about FPA. We will support soft float and VFP.
176 int mono_exc_esp_offset = 0;
178 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
179 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
180 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
182 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
183 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
184 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
186 //#define DEBUG_IMT 0
189 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
193 mono_arch_regname (int reg)
195 static const char * rnames[] = {
196 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
197 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
198 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
201 if (reg >= 0 && reg < 16)
207 mono_arch_fregname (int reg)
209 static const char * rnames[] = {
210 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
211 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
212 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
213 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
214 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
215 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
218 if (reg >= 0 && reg < 32)
226 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
228 int imm8, rot_amount;
229 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
230 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
234 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
235 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
237 code = mono_arm_emit_load_imm (code, dreg, imm);
238 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
243 /* If dreg == sreg, this clobbers IP */
245 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
247 int imm8, rot_amount;
248 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
249 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
253 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
254 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
256 code = mono_arm_emit_load_imm (code, dreg, imm);
257 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
263 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
265 /* we can use r0-r3, since this is called only for incoming args on the stack */
266 if (size > sizeof (gpointer) * 4) {
268 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
269 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
270 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
271 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
272 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
273 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
274 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
275 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
276 ARM_B_COND (code, ARMCOND_NE, 0);
277 arm_patch (code - 4, start_loop);
280 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
281 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
283 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
284 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
290 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
291 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
292 doffset = soffset = 0;
294 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
295 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
301 g_assert (size == 0);
306 emit_call_reg (guint8 *code, int reg)
309 ARM_BLX_REG (code, reg);
311 #ifdef USE_JUMP_TABLES
312 g_assert_not_reached ();
314 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
318 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
324 emit_call_seq (MonoCompile *cfg, guint8 *code)
326 #ifdef USE_JUMP_TABLES
327 code = mono_arm_patchable_bl (code, ARMCOND_AL);
329 if (cfg->method->dynamic) {
330 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
332 *(gpointer*)code = NULL;
334 code = emit_call_reg (code, ARMREG_IP);
338 cfg->thunk_area += THUNK_SIZE;
344 mono_arm_patchable_b (guint8 *code, int cond)
346 #ifdef USE_JUMP_TABLES
349 jte = mono_jumptable_add_entry ();
350 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
351 ARM_BX_COND (code, cond, ARMREG_IP);
353 ARM_B_COND (code, cond, 0);
359 mono_arm_patchable_bl (guint8 *code, int cond)
361 #ifdef USE_JUMP_TABLES
364 jte = mono_jumptable_add_entry ();
365 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
366 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
368 ARM_BL_COND (code, cond, 0);
373 #ifdef USE_JUMP_TABLES
375 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
377 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
378 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
383 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
385 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
386 ARM_LDR_IMM (code, reg, reg, 0);
392 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
395 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
396 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
398 code = emit_call_seq (cfg, code);
399 if (dreg != ARMREG_R0)
400 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
402 g_assert_not_reached ();
408 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
411 if (tls_offset_reg != ARMREG_R0)
412 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
413 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
415 code = emit_call_seq (cfg, code);
416 if (dreg != ARMREG_R0)
417 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
419 g_assert_not_reached ();
425 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
428 if (sreg != ARMREG_R1)
429 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
430 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
431 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
433 code = emit_call_seq (cfg, code);
435 g_assert_not_reached ();
441 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
444 /* Get sreg in R1 and tls_offset_reg in R0 */
445 if (tls_offset_reg == ARMREG_R1) {
446 if (sreg == ARMREG_R0) {
447 /* swap sreg and tls_offset_reg */
448 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
449 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
450 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
452 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
453 if (sreg != ARMREG_R1)
454 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
457 if (sreg != ARMREG_R1)
458 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
459 if (tls_offset_reg != ARMREG_R0)
460 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
462 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
464 code = emit_call_seq (cfg, code);
466 g_assert_not_reached ();
474 * Emit code to push an LMF structure on the LMF stack.
475 * On arm, this is intermixed with the initialization of other fields of the structure.
478 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
480 gboolean get_lmf_fast = FALSE;
483 if (mono_arm_have_tls_get ()) {
485 if (cfg->compile_aot) {
487 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
488 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
490 *(gpointer*)code = NULL;
492 /* Load the value from the GOT */
493 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
494 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
496 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
497 g_assert (lmf_addr_tls_offset != -1);
498 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
503 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
504 (gpointer)"mono_get_lmf_addr");
505 code = emit_call_seq (cfg, code);
507 /* we build the MonoLMF structure on the stack - see mini-arm.h */
508 /* lmf_offset is the offset from the previous stack pointer,
509 * alloc_size is the total stack space allocated, so the offset
510 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
511 * The pointer to the struct is put in r1 (new_lmf).
512 * ip is used as scratch
513 * The callee-saved registers are already in the MonoLMF structure
515 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
516 /* r0 is the result from mono_get_lmf_addr () */
517 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
518 /* new_lmf->previous_lmf = *lmf_addr */
519 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
520 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
521 /* *(lmf_addr) = r1 */
522 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
523 /* Skip method (only needed for trampoline LMF frames) */
524 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
525 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
526 /* save the current IP */
527 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
528 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
530 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
531 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
542 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
546 g_assert (!cfg->r4fp);
548 for (list = inst->float_args; list; list = list->next) {
549 FloatArgData *fad = list->data;
550 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
551 gboolean imm = arm_is_fpimm8 (var->inst_offset);
553 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
559 if (*offset + *max_len > cfg->code_size) {
560 cfg->code_size += *max_len;
561 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
563 code = cfg->native_code + *offset;
567 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
568 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
570 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
572 *offset = code - cfg->native_code;
579 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
583 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
585 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
588 if (!arm_is_fpimm8 (inst->inst_offset)) {
589 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
590 ARM_FSTD (code, reg, ARMREG_LR, 0);
592 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
599 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
603 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
605 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
608 if (!arm_is_fpimm8 (inst->inst_offset)) {
609 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
610 ARM_FLDD (code, reg, ARMREG_LR, 0);
612 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
621 * Emit code to pop an LMF structure from the LMF stack.
624 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
628 if (lmf_offset < 32) {
629 basereg = cfg->frame_reg;
634 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
637 /* ip = previous_lmf */
638 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
640 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
641 /* *(lmf_addr) = previous_lmf */
642 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
647 #endif /* #ifndef DISABLE_JIT */
649 #ifndef MONO_CROSS_COMPILE
651 mono_arm_have_fast_tls (void)
653 if (mini_get_debug_options ()->arm_use_fallback_tls)
655 #if (defined(HAVE_KW_THREAD) && defined(__linux__)) \
656 || defined(TARGET_ANDROID)
657 guint32* kuser_get_tls = (void*)0xffff0fe0;
658 guint32 expected [] = {0xee1d0f70, 0xe12fff1e};
660 /* Expecting mrc + bx lr in the kuser_get_tls kernel helper */
661 return memcmp (kuser_get_tls, expected, 8) == 0;
662 #elif defined(TARGET_IOS)
663 guint32 expected [] = {0x1f70ee1d, 0x0103f021, 0x0020f851, 0xbf004770};
664 /* Discard thumb bit */
665 guint32* pthread_getspecific_addr = (guint32*) ((guint32)pthread_getspecific & 0xfffffffe);
666 return memcmp ((void*)pthread_getspecific_addr, expected, 16) == 0;
674 * mono_arm_have_tls_get:
676 * Returns whether we have tls access implemented on the current
680 mono_arm_have_tls_get (void)
690 * mono_arch_get_argument_info:
691 * @csig: a method signature
692 * @param_count: the number of parameters to consider
693 * @arg_info: an array to store the result infos
695 * Gathers information on parameters such as size, alignment and
696 * padding. arg_info should be large enought to hold param_count + 1 entries.
698 * Returns the size of the activation frame.
701 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
703 int k, frame_size = 0;
704 guint32 size, align, pad;
708 t = mini_get_underlying_type (csig->ret);
709 if (MONO_TYPE_ISSTRUCT (t)) {
710 frame_size += sizeof (gpointer);
714 arg_info [0].offset = offset;
717 frame_size += sizeof (gpointer);
721 arg_info [0].size = frame_size;
723 for (k = 0; k < param_count; k++) {
724 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
726 /* ignore alignment for now */
729 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
730 arg_info [k].pad = pad;
732 arg_info [k + 1].pad = 0;
733 arg_info [k + 1].size = size;
735 arg_info [k + 1].offset = offset;
739 align = MONO_ARCH_FRAME_ALIGNMENT;
740 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
741 arg_info [k].pad = pad;
746 #define MAX_ARCH_DELEGATE_PARAMS 3
749 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
751 guint8 *code, *start;
754 start = code = mono_global_codeman_reserve (12);
756 /* Replace the this argument with the target */
757 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
758 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
759 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
761 g_assert ((code - start) <= 12);
763 mono_arch_flush_icache (start, 12);
767 size = 8 + param_count * 4;
768 start = code = mono_global_codeman_reserve (size);
770 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
771 /* slide down the arguments */
772 for (i = 0; i < param_count; ++i) {
773 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
775 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
777 g_assert ((code - start) <= size);
779 mono_arch_flush_icache (start, size);
782 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
784 *code_size = code - start;
790 * mono_arch_get_delegate_invoke_impls:
792 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
796 mono_arch_get_delegate_invoke_impls (void)
804 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
805 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
807 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
808 code = get_delegate_invoke_impl (FALSE, i, &code_len);
809 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
810 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
818 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
820 guint8 *code, *start;
823 /* FIXME: Support more cases */
824 sig_ret = mini_get_underlying_type (sig->ret);
825 if (MONO_TYPE_ISSTRUCT (sig_ret))
829 static guint8* cached = NULL;
830 mono_mini_arch_lock ();
832 mono_mini_arch_unlock ();
837 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
839 start = get_delegate_invoke_impl (TRUE, 0, NULL);
841 mono_mini_arch_unlock ();
844 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
847 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
849 for (i = 0; i < sig->param_count; ++i)
850 if (!mono_is_regsize_var (sig->params [i]))
853 mono_mini_arch_lock ();
854 code = cache [sig->param_count];
856 mono_mini_arch_unlock ();
861 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
862 start = mono_aot_get_trampoline (name);
865 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
867 cache [sig->param_count] = start;
868 mono_mini_arch_unlock ();
876 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
882 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
884 return (gpointer)regs [ARMREG_R0];
888 * Initialize the cpu to execute managed code.
891 mono_arch_cpu_init (void)
893 i8_align = MONO_ABI_ALIGNOF (gint64);
894 #ifdef MONO_CROSS_COMPILE
895 /* Need to set the alignment of i8 since it can different on the target */
896 #ifdef TARGET_ANDROID
898 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
904 * Initialize architecture specific code.
907 mono_arch_init (void)
909 const char *cpu_arch;
911 mono_mutex_init_recursive (&mini_arch_mutex);
912 if (mini_get_debug_options ()->soft_breakpoints) {
913 single_step_tramp = mini_get_single_step_trampoline ();
914 breakpoint_tramp = mini_get_breakpoint_trampoline ();
916 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
917 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
918 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
921 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
922 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
923 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
924 #if defined(ENABLE_GSHAREDVT)
925 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
928 #if defined(__ARM_EABI__)
929 eabi_supported = TRUE;
932 #if defined(ARM_FPU_VFP_HARD)
933 arm_fpu = MONO_ARM_FPU_VFP_HARD;
935 arm_fpu = MONO_ARM_FPU_VFP;
937 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
939 * If we're compiling with a soft float fallback and it
940 * turns out that no VFP unit is available, we need to
941 * switch to soft float. We don't do this for iOS, since
942 * iOS devices always have a VFP unit.
944 if (!mono_hwcap_arm_has_vfp)
945 arm_fpu = MONO_ARM_FPU_NONE;
948 * This environment variable can be useful in testing
949 * environments to make sure the soft float fallback
950 * works. Most ARM devices have VFP units these days, so
951 * normally soft float code would not be exercised much.
953 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
955 if (soft && !strncmp (soft, "1", 1))
956 arm_fpu = MONO_ARM_FPU_NONE;
960 v5_supported = mono_hwcap_arm_is_v5;
961 v6_supported = mono_hwcap_arm_is_v6;
962 v7_supported = mono_hwcap_arm_is_v7;
963 v7s_supported = mono_hwcap_arm_is_v7s;
965 #if defined(__APPLE__)
966 /* iOS is special-cased here because we don't yet
967 have a way to properly detect CPU features on it. */
968 thumb_supported = TRUE;
971 thumb_supported = mono_hwcap_arm_has_thumb;
972 thumb2_supported = mono_hwcap_arm_has_thumb2;
975 /* Format: armv(5|6|7[s])[-thumb[2]] */
976 cpu_arch = g_getenv ("MONO_CPU_ARCH");
978 /* Do this here so it overrides any detection. */
980 if (strncmp (cpu_arch, "armv", 4) == 0) {
981 v5_supported = cpu_arch [4] >= '5';
982 v6_supported = cpu_arch [4] >= '6';
983 v7_supported = cpu_arch [4] >= '7';
984 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
987 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
988 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
993 * Cleanup architecture specific code.
996 mono_arch_cleanup (void)
1001 * This function returns the optimizations supported on this cpu.
1004 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1006 /* no arm-specific optimizations yet */
1012 * This function test for all SIMD functions supported.
1014 * Returns a bitmask corresponding to all supported versions.
1018 mono_arch_cpu_enumerate_simd_versions (void)
1020 /* SIMD is currently unimplemented */
1028 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1030 if (v7s_supported) {
1044 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1046 mono_arch_is_soft_float (void)
1048 return arm_fpu == MONO_ARM_FPU_NONE;
1053 mono_arm_is_hard_float (void)
1055 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1059 is_regsize_var (MonoType *t)
1063 t = mini_get_underlying_type (t);
1070 case MONO_TYPE_FNPTR:
1072 case MONO_TYPE_OBJECT:
1073 case MONO_TYPE_STRING:
1074 case MONO_TYPE_CLASS:
1075 case MONO_TYPE_SZARRAY:
1076 case MONO_TYPE_ARRAY:
1078 case MONO_TYPE_GENERICINST:
1079 if (!mono_type_generic_inst_is_valuetype (t))
1082 case MONO_TYPE_VALUETYPE:
1089 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1094 for (i = 0; i < cfg->num_varinfo; i++) {
1095 MonoInst *ins = cfg->varinfo [i];
1096 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1099 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1102 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1105 /* we can only allocate 32 bit values */
1106 if (is_regsize_var (ins->inst_vtype)) {
1107 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1108 g_assert (i == vmv->idx);
1109 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1117 mono_arch_get_global_int_regs (MonoCompile *cfg)
1121 mono_arch_compute_omit_fp (cfg);
1124 * FIXME: Interface calls might go through a static rgctx trampoline which
1125 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1128 if (cfg->flags & MONO_CFG_HAS_CALLS)
1129 cfg->uses_rgctx_reg = TRUE;
1131 if (cfg->arch.omit_fp)
1132 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1133 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1134 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1135 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1137 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1138 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1140 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1141 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1142 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1143 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1144 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1145 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1151 * mono_arch_regalloc_cost:
1153 * Return the cost, in number of memory references, of the action of
1154 * allocating the variable VMV into a register during global register
1158 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1164 #endif /* #ifndef DISABLE_JIT */
1166 #ifndef __GNUC_PREREQ
1167 #define __GNUC_PREREQ(maj, min) (0)
1171 mono_arch_flush_icache (guint8 *code, gint size)
1173 #if defined(__native_client__)
1174 // For Native Client we don't have to flush i-cache here,
1175 // as it's being done by dyncode interface.
1178 #ifdef MONO_CROSS_COMPILE
1180 sys_icache_invalidate (code, size);
1181 #elif __GNUC_PREREQ(4, 3)
1182 __builtin___clear_cache (code, code + size);
1183 #elif __GNUC_PREREQ(4, 1)
1184 __clear_cache (code, code + size);
1185 #elif defined(PLATFORM_ANDROID)
1186 const int syscall = 0xf0002;
1194 : "r" (code), "r" (code + size), "r" (syscall)
1195 : "r0", "r1", "r7", "r2"
1198 __asm __volatile ("mov r0, %0\n"
1201 "swi 0x9f0002 @ sys_cacheflush"
1203 : "r" (code), "r" (code + size), "r" (0)
1204 : "r0", "r1", "r3" );
1206 #endif /* !__native_client__ */
1211 /* Passed/returned in an ireg */
1213 /* Passed/returned in a pair of iregs */
1215 /* Passed on the stack */
1217 /* First word in r3, second word on the stack */
1219 /* FP value passed in either an ireg or a vfp reg */
1222 RegTypeStructByAddr,
1223 /* gsharedvt argument passed by addr in greg */
1224 RegTypeGSharedVtInReg,
1225 /* gsharedvt argument passed by addr on stack */
1226 RegTypeGSharedVtOnStack,
1232 guint16 vtsize; /* in param area */
1240 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1245 guint32 stack_usage;
1246 /* The index of the vret arg in the argument list for RegTypeStructByAddr */
1256 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1259 if (*gr > ARMREG_R3) {
1261 ainfo->offset = *stack_size;
1262 ainfo->reg = ARMREG_SP; /* in the caller */
1263 ainfo->storage = RegTypeBase;
1266 ainfo->storage = RegTypeGeneral;
1273 split = i8_align == 4;
1278 if (*gr == ARMREG_R3 && split) {
1279 /* first word in r3 and the second on the stack */
1280 ainfo->offset = *stack_size;
1281 ainfo->reg = ARMREG_SP; /* in the caller */
1282 ainfo->storage = RegTypeBaseGen;
1284 } else if (*gr >= ARMREG_R3) {
1285 if (eabi_supported) {
1286 /* darwin aligns longs to 4 byte only */
1287 if (i8_align == 8) {
1292 ainfo->offset = *stack_size;
1293 ainfo->reg = ARMREG_SP; /* in the caller */
1294 ainfo->storage = RegTypeBase;
1297 if (eabi_supported) {
1298 if (i8_align == 8 && ((*gr) & 1))
1301 ainfo->storage = RegTypeIRegPair;
1310 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1313 * If we're calling a function like this:
1315 * void foo(float a, double b, float c)
1317 * We pass a in s0 and b in d1. That leaves us
1318 * with s1 being unused. The armhf ABI recognizes
1319 * this and requires register assignment to then
1320 * use that for the next single-precision arg,
1321 * i.e. c in this example. So float_spare either
1322 * tells us which reg to use for the next single-
1323 * precision arg, or it's -1, meaning use *fpr.
1325 * Note that even though most of the JIT speaks
1326 * double-precision, fpr represents single-
1327 * precision registers.
1329 * See parts 5.5 and 6.1.2 of the AAPCS for how
1333 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1334 ainfo->storage = RegTypeFP;
1338 * If we're passing a double-precision value
1339 * and *fpr is odd (e.g. it's s1, s3, ...)
1340 * we need to use the next even register. So
1341 * we mark the current *fpr as a spare that
1342 * can be used for the next single-precision
1346 *float_spare = *fpr;
1351 * At this point, we have an even register
1352 * so we assign that and move along.
1356 } else if (*float_spare >= 0) {
1358 * We're passing a single-precision value
1359 * and it looks like a spare single-
1360 * precision register is available. Let's
1364 ainfo->reg = *float_spare;
1368 * If we hit this branch, we're passing a
1369 * single-precision value and we can simply
1370 * use the next available register.
1378 * We've exhausted available floating point
1379 * regs, so pass the rest on the stack.
1387 ainfo->offset = *stack_size;
1388 ainfo->reg = ARMREG_SP;
1389 ainfo->storage = RegTypeBase;
1396 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1400 MonoClassField *field;
1401 MonoType *ftype, *prev_ftype = NULL;
1404 klass = mono_class_from_mono_type (t);
1406 while ((field = mono_class_get_fields (klass, &iter))) {
1407 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1409 ftype = mono_field_get_type (field);
1410 ftype = mini_get_underlying_type (ftype);
1412 if (MONO_TYPE_ISSTRUCT (ftype)) {
1413 int nested_nfields, nested_esize;
1415 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1417 if (nested_esize == 4)
1418 ftype = &mono_defaults.single_class->byval_arg;
1420 ftype = &mono_defaults.double_class->byval_arg;
1421 if (prev_ftype && prev_ftype->type != ftype->type)
1424 nfields += nested_nfields;
1426 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1428 if (prev_ftype && prev_ftype->type != ftype->type)
1434 if (nfields == 0 || nfields > 4)
1436 *out_nfields = nfields;
1437 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1442 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1444 guint i, gr, fpr, pstart;
1446 int n = sig->hasthis + sig->param_count;
1450 guint32 stack_size = 0;
1452 gboolean is_pinvoke = sig->pinvoke;
1453 gboolean vtype_retaddr = FALSE;
1456 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1458 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1465 t = mini_get_underlying_type (sig->ret);
1476 case MONO_TYPE_FNPTR:
1477 case MONO_TYPE_CLASS:
1478 case MONO_TYPE_OBJECT:
1479 case MONO_TYPE_SZARRAY:
1480 case MONO_TYPE_ARRAY:
1481 case MONO_TYPE_STRING:
1482 cinfo->ret.storage = RegTypeGeneral;
1483 cinfo->ret.reg = ARMREG_R0;
1487 cinfo->ret.storage = RegTypeIRegPair;
1488 cinfo->ret.reg = ARMREG_R0;
1492 cinfo->ret.storage = RegTypeFP;
1494 if (t->type == MONO_TYPE_R4)
1495 cinfo->ret.size = 4;
1497 cinfo->ret.size = 8;
1499 if (IS_HARD_FLOAT) {
1500 cinfo->ret.reg = ARM_VFP_F0;
1502 cinfo->ret.reg = ARMREG_R0;
1505 case MONO_TYPE_GENERICINST:
1506 if (!mono_type_generic_inst_is_valuetype (t)) {
1507 cinfo->ret.storage = RegTypeGeneral;
1508 cinfo->ret.reg = ARMREG_R0;
1511 // FIXME: Only for variable types
1512 if (mini_is_gsharedvt_type (t)) {
1513 cinfo->ret.storage = RegTypeStructByAddr;
1517 case MONO_TYPE_VALUETYPE:
1518 case MONO_TYPE_TYPEDBYREF:
1519 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1520 cinfo->ret.storage = RegTypeHFA;
1522 cinfo->ret.nregs = nfields;
1523 cinfo->ret.esize = esize;
1525 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1526 cinfo->ret.storage = RegTypeStructByVal;
1528 cinfo->ret.storage = RegTypeStructByAddr;
1532 case MONO_TYPE_MVAR:
1533 g_assert (mini_is_gsharedvt_type (t));
1534 cinfo->ret.storage = RegTypeStructByAddr;
1536 case MONO_TYPE_VOID:
1539 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1542 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1547 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1548 * the first argument, allowing 'this' to be always passed in the first arg reg.
1549 * Also do this if the first argument is a reference type, since virtual calls
1550 * are sometimes made using calli without sig->hasthis set, like in the delegate
1553 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1555 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1557 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1561 cinfo->ret.reg = gr;
1563 cinfo->vret_arg_index = 1;
1567 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1570 if (vtype_retaddr) {
1571 cinfo->ret.reg = gr;
1576 DEBUG(printf("params: %d\n", sig->param_count));
1577 for (i = pstart; i < sig->param_count; ++i) {
1578 ArgInfo *ainfo = &cinfo->args [n];
1580 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1581 /* Prevent implicit arguments and sig_cookie from
1582 being passed in registers */
1585 /* Emit the signature cookie just before the implicit arguments */
1586 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1588 DEBUG(printf("param %d: ", i));
1589 if (sig->params [i]->byref) {
1590 DEBUG(printf("byref\n"));
1591 add_general (&gr, &stack_size, ainfo, TRUE);
1595 t = mini_get_underlying_type (sig->params [i]);
1599 cinfo->args [n].size = 1;
1600 add_general (&gr, &stack_size, ainfo, TRUE);
1604 cinfo->args [n].size = 2;
1605 add_general (&gr, &stack_size, ainfo, TRUE);
1609 cinfo->args [n].size = 4;
1610 add_general (&gr, &stack_size, ainfo, TRUE);
1615 case MONO_TYPE_FNPTR:
1616 case MONO_TYPE_CLASS:
1617 case MONO_TYPE_OBJECT:
1618 case MONO_TYPE_STRING:
1619 case MONO_TYPE_SZARRAY:
1620 case MONO_TYPE_ARRAY:
1621 cinfo->args [n].size = sizeof (gpointer);
1622 add_general (&gr, &stack_size, ainfo, TRUE);
1624 case MONO_TYPE_GENERICINST:
1625 if (!mono_type_generic_inst_is_valuetype (t)) {
1626 cinfo->args [n].size = sizeof (gpointer);
1627 add_general (&gr, &stack_size, ainfo, TRUE);
1630 if (mini_is_gsharedvt_type (t)) {
1631 /* gsharedvt arguments are passed by ref */
1632 g_assert (mini_is_gsharedvt_type (t));
1633 add_general (&gr, &stack_size, ainfo, TRUE);
1634 switch (ainfo->storage) {
1635 case RegTypeGeneral:
1636 ainfo->storage = RegTypeGSharedVtInReg;
1639 ainfo->storage = RegTypeGSharedVtOnStack;
1642 g_assert_not_reached ();
1647 case MONO_TYPE_TYPEDBYREF:
1648 case MONO_TYPE_VALUETYPE: {
1651 int nwords, nfields, esize;
1654 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1655 if (fpr + nfields < ARM_VFP_F16) {
1656 ainfo->storage = RegTypeHFA;
1658 ainfo->nregs = nfields;
1659 ainfo->esize = esize;
1667 if (t->type == MONO_TYPE_TYPEDBYREF) {
1668 size = sizeof (MonoTypedRef);
1669 align = sizeof (gpointer);
1671 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1673 size = mono_class_native_size (klass, &align);
1675 size = mini_type_stack_size_full (t, &align, FALSE);
1677 DEBUG(printf ("load %d bytes struct\n", size));
1680 align_size += (sizeof (gpointer) - 1);
1681 align_size &= ~(sizeof (gpointer) - 1);
1682 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1683 ainfo->storage = RegTypeStructByVal;
1684 ainfo->struct_size = size;
1685 /* FIXME: align stack_size if needed */
1686 if (eabi_supported) {
1687 if (align >= 8 && (gr & 1))
1690 if (gr > ARMREG_R3) {
1692 ainfo->vtsize = nwords;
1694 int rest = ARMREG_R3 - gr + 1;
1695 int n_in_regs = rest >= nwords? nwords: rest;
1697 ainfo->size = n_in_regs;
1698 ainfo->vtsize = nwords - n_in_regs;
1701 nwords -= n_in_regs;
1703 if (sig->call_convention == MONO_CALL_VARARG)
1704 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1705 stack_size = ALIGN_TO (stack_size, align);
1706 ainfo->offset = stack_size;
1707 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1708 stack_size += nwords * sizeof (gpointer);
1714 add_general (&gr, &stack_size, ainfo, FALSE);
1720 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1722 add_general (&gr, &stack_size, ainfo, TRUE);
1728 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1730 add_general (&gr, &stack_size, ainfo, FALSE);
1733 case MONO_TYPE_MVAR:
1734 /* gsharedvt arguments are passed by ref */
1735 g_assert (mini_is_gsharedvt_type (t));
1736 add_general (&gr, &stack_size, ainfo, TRUE);
1737 switch (ainfo->storage) {
1738 case RegTypeGeneral:
1739 ainfo->storage = RegTypeGSharedVtInReg;
1742 ainfo->storage = RegTypeGSharedVtOnStack;
1745 g_assert_not_reached ();
1749 g_error ("Can't handle 0x%x", sig->params [i]->type);
1754 /* Handle the case where there are no implicit arguments */
1755 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1756 /* Prevent implicit arguments and sig_cookie from
1757 being passed in registers */
1760 /* Emit the signature cookie just before the implicit arguments */
1761 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1764 /* align stack size to 8 */
1765 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1766 stack_size = (stack_size + 7) & ~7;
1768 cinfo->stack_usage = stack_size;
1774 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1776 MonoType *callee_ret;
1780 c1 = get_call_info (NULL, caller_sig);
1781 c2 = get_call_info (NULL, callee_sig);
1784 * Tail calls with more callee stack usage than the caller cannot be supported, since
1785 * the extra stack space would be left on the stack after the tail call.
1787 res = c1->stack_usage >= c2->stack_usage;
1788 callee_ret = mini_get_underlying_type (callee_sig->ret);
1789 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1790 /* An address on the callee's stack is passed as the first argument */
1793 if (c2->stack_usage > 16 * 4)
1805 debug_omit_fp (void)
1808 return mono_debug_count ();
1815 * mono_arch_compute_omit_fp:
1817 * Determine whenever the frame pointer can be eliminated.
1820 mono_arch_compute_omit_fp (MonoCompile *cfg)
1822 MonoMethodSignature *sig;
1823 MonoMethodHeader *header;
1827 if (cfg->arch.omit_fp_computed)
1830 header = cfg->header;
1832 sig = mono_method_signature (cfg->method);
1834 if (!cfg->arch.cinfo)
1835 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1836 cinfo = cfg->arch.cinfo;
1839 * FIXME: Remove some of the restrictions.
1841 cfg->arch.omit_fp = TRUE;
1842 cfg->arch.omit_fp_computed = TRUE;
1844 if (cfg->disable_omit_fp)
1845 cfg->arch.omit_fp = FALSE;
1846 if (!debug_omit_fp ())
1847 cfg->arch.omit_fp = FALSE;
1849 if (cfg->method->save_lmf)
1850 cfg->arch.omit_fp = FALSE;
1852 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1853 cfg->arch.omit_fp = FALSE;
1854 if (header->num_clauses)
1855 cfg->arch.omit_fp = FALSE;
1856 if (cfg->param_area)
1857 cfg->arch.omit_fp = FALSE;
1858 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1859 cfg->arch.omit_fp = FALSE;
1860 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1861 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1862 cfg->arch.omit_fp = FALSE;
1863 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1864 ArgInfo *ainfo = &cinfo->args [i];
1866 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1868 * The stack offset can only be determined when the frame
1871 cfg->arch.omit_fp = FALSE;
1876 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1877 MonoInst *ins = cfg->varinfo [i];
1880 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1885 * Set var information according to the calling convention. arm version.
1886 * The locals var stuff should most likely be split in another method.
1889 mono_arch_allocate_vars (MonoCompile *cfg)
1891 MonoMethodSignature *sig;
1892 MonoMethodHeader *header;
1895 int i, offset, size, align, curinst;
1900 sig = mono_method_signature (cfg->method);
1902 if (!cfg->arch.cinfo)
1903 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1904 cinfo = cfg->arch.cinfo;
1905 sig_ret = mini_get_underlying_type (sig->ret);
1907 mono_arch_compute_omit_fp (cfg);
1909 if (cfg->arch.omit_fp)
1910 cfg->frame_reg = ARMREG_SP;
1912 cfg->frame_reg = ARMREG_FP;
1914 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1916 /* allow room for the vararg method args: void* and long/double */
1917 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1918 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1920 header = cfg->header;
1922 /* See mono_arch_get_global_int_regs () */
1923 if (cfg->flags & MONO_CFG_HAS_CALLS)
1924 cfg->uses_rgctx_reg = TRUE;
1926 if (cfg->frame_reg != ARMREG_SP)
1927 cfg->used_int_regs |= 1 << cfg->frame_reg;
1929 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1930 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1931 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1935 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1936 if (sig_ret->type != MONO_TYPE_VOID) {
1937 cfg->ret->opcode = OP_REGVAR;
1938 cfg->ret->inst_c0 = ARMREG_R0;
1941 /* local vars are at a positive offset from the stack pointer */
1943 * also note that if the function uses alloca, we use FP
1944 * to point at the local variables.
1946 offset = 0; /* linkage area */
1947 /* align the offset to 16 bytes: not sure this is needed here */
1949 //offset &= ~(8 - 1);
1951 /* add parameter area size for called functions */
1952 offset += cfg->param_area;
1955 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1958 /* allow room to save the return value */
1959 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1962 switch (cinfo->ret.storage) {
1963 case RegTypeStructByVal:
1964 cfg->ret->opcode = OP_REGOFFSET;
1965 cfg->ret->inst_basereg = cfg->frame_reg;
1966 offset += sizeof (gpointer) - 1;
1967 offset &= ~(sizeof (gpointer) - 1);
1968 cfg->ret->inst_offset = - offset;
1969 offset += sizeof(gpointer);
1972 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1973 offset = ALIGN_TO (offset, 8);
1974 cfg->ret->opcode = OP_REGOFFSET;
1975 cfg->ret->inst_basereg = cfg->frame_reg;
1976 cfg->ret->inst_offset = offset;
1980 case RegTypeStructByAddr:
1981 ins = cfg->vret_addr;
1982 offset += sizeof(gpointer) - 1;
1983 offset &= ~(sizeof(gpointer) - 1);
1984 ins->inst_offset = offset;
1985 ins->opcode = OP_REGOFFSET;
1986 ins->inst_basereg = cfg->frame_reg;
1987 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1988 printf ("vret_addr =");
1989 mono_print_ins (cfg->vret_addr);
1991 offset += sizeof(gpointer);
1997 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1998 if (cfg->arch.seq_point_info_var) {
2001 ins = cfg->arch.seq_point_info_var;
2005 offset += align - 1;
2006 offset &= ~(align - 1);
2007 ins->opcode = OP_REGOFFSET;
2008 ins->inst_basereg = cfg->frame_reg;
2009 ins->inst_offset = offset;
2012 ins = cfg->arch.ss_trigger_page_var;
2015 offset += align - 1;
2016 offset &= ~(align - 1);
2017 ins->opcode = OP_REGOFFSET;
2018 ins->inst_basereg = cfg->frame_reg;
2019 ins->inst_offset = offset;
2023 if (cfg->arch.seq_point_read_var) {
2026 ins = cfg->arch.seq_point_read_var;
2030 offset += align - 1;
2031 offset &= ~(align - 1);
2032 ins->opcode = OP_REGOFFSET;
2033 ins->inst_basereg = cfg->frame_reg;
2034 ins->inst_offset = offset;
2037 ins = cfg->arch.seq_point_ss_method_var;
2040 offset += align - 1;
2041 offset &= ~(align - 1);
2042 ins->opcode = OP_REGOFFSET;
2043 ins->inst_basereg = cfg->frame_reg;
2044 ins->inst_offset = offset;
2047 ins = cfg->arch.seq_point_bp_method_var;
2050 offset += align - 1;
2051 offset &= ~(align - 1);
2052 ins->opcode = OP_REGOFFSET;
2053 ins->inst_basereg = cfg->frame_reg;
2054 ins->inst_offset = offset;
2058 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
2059 /* Allocate a temporary used by the atomic ops */
2063 /* Allocate a local slot to hold the sig cookie address */
2064 offset += align - 1;
2065 offset &= ~(align - 1);
2066 cfg->arch.atomic_tmp_offset = offset;
2069 cfg->arch.atomic_tmp_offset = -1;
2072 cfg->locals_min_stack_offset = offset;
2074 curinst = cfg->locals_start;
2075 for (i = curinst; i < cfg->num_varinfo; ++i) {
2078 ins = cfg->varinfo [i];
2079 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
2082 t = ins->inst_vtype;
2083 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
2086 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
2087 * pinvoke wrappers when they call functions returning structure */
2088 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2089 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
2093 size = mono_type_size (t, &align);
2095 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2096 * since it loads/stores misaligned words, which don't do the right thing.
2098 if (align < 4 && size >= 4)
2100 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2101 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2102 offset += align - 1;
2103 offset &= ~(align - 1);
2104 ins->opcode = OP_REGOFFSET;
2105 ins->inst_offset = offset;
2106 ins->inst_basereg = cfg->frame_reg;
2108 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2111 cfg->locals_max_stack_offset = offset;
2115 ins = cfg->args [curinst];
2116 if (ins->opcode != OP_REGVAR) {
2117 ins->opcode = OP_REGOFFSET;
2118 ins->inst_basereg = cfg->frame_reg;
2119 offset += sizeof (gpointer) - 1;
2120 offset &= ~(sizeof (gpointer) - 1);
2121 ins->inst_offset = offset;
2122 offset += sizeof (gpointer);
2127 if (sig->call_convention == MONO_CALL_VARARG) {
2131 /* Allocate a local slot to hold the sig cookie address */
2132 offset += align - 1;
2133 offset &= ~(align - 1);
2134 cfg->sig_cookie = offset;
2138 for (i = 0; i < sig->param_count; ++i) {
2139 ainfo = cinfo->args + i;
2141 ins = cfg->args [curinst];
2143 switch (ainfo->storage) {
2145 offset = ALIGN_TO (offset, 8);
2146 ins->opcode = OP_REGOFFSET;
2147 ins->inst_basereg = cfg->frame_reg;
2148 /* These arguments are saved to the stack in the prolog */
2149 ins->inst_offset = offset;
2150 if (cfg->verbose_level >= 2)
2151 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2159 if (ins->opcode != OP_REGVAR) {
2160 ins->opcode = OP_REGOFFSET;
2161 ins->inst_basereg = cfg->frame_reg;
2162 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2164 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2165 * since it loads/stores misaligned words, which don't do the right thing.
2167 if (align < 4 && size >= 4)
2169 /* The code in the prolog () stores words when storing vtypes received in a register */
2170 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2172 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2173 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2174 offset += align - 1;
2175 offset &= ~(align - 1);
2176 ins->inst_offset = offset;
2182 /* align the offset to 8 bytes */
2183 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2184 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2189 cfg->stack_offset = offset;
2193 mono_arch_create_vars (MonoCompile *cfg)
2195 MonoMethodSignature *sig;
2199 sig = mono_method_signature (cfg->method);
2201 if (!cfg->arch.cinfo)
2202 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2203 cinfo = cfg->arch.cinfo;
2205 if (IS_HARD_FLOAT) {
2206 for (i = 0; i < 2; i++) {
2207 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2208 inst->flags |= MONO_INST_VOLATILE;
2210 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2214 if (cinfo->ret.storage == RegTypeStructByVal)
2215 cfg->ret_var_is_local = TRUE;
2217 if (cinfo->ret.storage == RegTypeStructByAddr) {
2218 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2219 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2220 printf ("vret_addr = ");
2221 mono_print_ins (cfg->vret_addr);
2225 if (cfg->gen_sdb_seq_points) {
2226 if (cfg->soft_breakpoints) {
2227 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2228 ins->flags |= MONO_INST_VOLATILE;
2229 cfg->arch.seq_point_read_var = ins;
2231 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2232 ins->flags |= MONO_INST_VOLATILE;
2233 cfg->arch.seq_point_ss_method_var = ins;
2235 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2236 ins->flags |= MONO_INST_VOLATILE;
2237 cfg->arch.seq_point_bp_method_var = ins;
2239 g_assert (!cfg->compile_aot);
2240 } else if (cfg->compile_aot) {
2241 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2242 ins->flags |= MONO_INST_VOLATILE;
2243 cfg->arch.seq_point_info_var = ins;
2245 /* Allocate a separate variable for this to save 1 load per seq point */
2246 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2247 ins->flags |= MONO_INST_VOLATILE;
2248 cfg->arch.ss_trigger_page_var = ins;
2254 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2256 MonoMethodSignature *tmp_sig;
2259 if (call->tail_call)
2262 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2265 * mono_ArgIterator_Setup assumes the signature cookie is
2266 * passed first and all the arguments which were before it are
2267 * passed on the stack after the signature. So compensate by
2268 * passing a different signature.
2270 tmp_sig = mono_metadata_signature_dup (call->signature);
2271 tmp_sig->param_count -= call->signature->sentinelpos;
2272 tmp_sig->sentinelpos = 0;
2273 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2275 sig_reg = mono_alloc_ireg (cfg);
2276 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2278 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2283 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2288 LLVMCallInfo *linfo;
2290 n = sig->param_count + sig->hasthis;
2292 cinfo = get_call_info (cfg->mempool, sig);
2294 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2297 * LLVM always uses the native ABI while we use our own ABI, the
2298 * only difference is the handling of vtypes:
2299 * - we only pass/receive them in registers in some cases, and only
2300 * in 1 or 2 integer registers.
2302 switch (cinfo->ret.storage) {
2303 case RegTypeGeneral:
2306 case RegTypeIRegPair:
2308 case RegTypeStructByAddr:
2309 /* Vtype returned using a hidden argument */
2310 linfo->ret.storage = LLVMArgVtypeRetAddr;
2311 linfo->vret_arg_index = cinfo->vret_arg_index;
2314 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2315 cfg->disable_llvm = TRUE;
2319 for (i = 0; i < n; ++i) {
2320 ainfo = cinfo->args + i;
2322 linfo->args [i].storage = LLVMArgNone;
2324 switch (ainfo->storage) {
2325 case RegTypeGeneral:
2326 case RegTypeIRegPair:
2328 case RegTypeBaseGen:
2329 linfo->args [i].storage = LLVMArgInIReg;
2331 case RegTypeStructByVal:
2332 linfo->args [i].storage = LLVMArgAsIArgs;
2333 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2336 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2337 cfg->disable_llvm = TRUE;
2347 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2350 MonoMethodSignature *sig;
2354 sig = call->signature;
2355 n = sig->param_count + sig->hasthis;
2357 cinfo = get_call_info (cfg->mempool, sig);
2359 switch (cinfo->ret.storage) {
2360 case RegTypeStructByVal:
2361 /* The JIT will transform this into a normal call */
2362 call->vret_in_reg = TRUE;
2366 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2367 * the location pointed to by it after call in emit_move_return_value ().
2369 if (!cfg->arch.vret_addr_loc) {
2370 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2371 /* Prevent it from being register allocated or optimized away */
2372 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2375 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2377 case RegTypeStructByAddr: {
2379 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2380 vtarg->sreg1 = call->vret_var->dreg;
2381 vtarg->dreg = mono_alloc_preg (cfg);
2382 MONO_ADD_INS (cfg->cbb, vtarg);
2384 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2391 for (i = 0; i < n; ++i) {
2392 ArgInfo *ainfo = cinfo->args + i;
2395 if (i >= sig->hasthis)
2396 t = sig->params [i - sig->hasthis];
2398 t = &mono_defaults.int_class->byval_arg;
2399 t = mini_get_underlying_type (t);
2401 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2402 /* Emit the signature cookie just before the implicit arguments */
2403 emit_sig_cookie (cfg, call, cinfo);
2406 in = call->args [i];
2408 switch (ainfo->storage) {
2409 case RegTypeGeneral:
2410 case RegTypeIRegPair:
2411 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2412 MONO_INST_NEW (cfg, ins, OP_MOVE);
2413 ins->dreg = mono_alloc_ireg (cfg);
2414 ins->sreg1 = in->dreg + 1;
2415 MONO_ADD_INS (cfg->cbb, ins);
2416 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2418 MONO_INST_NEW (cfg, ins, OP_MOVE);
2419 ins->dreg = mono_alloc_ireg (cfg);
2420 ins->sreg1 = in->dreg + 2;
2421 MONO_ADD_INS (cfg->cbb, ins);
2422 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2423 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2424 if (ainfo->size == 4) {
2425 if (IS_SOFT_FLOAT) {
2426 /* mono_emit_call_args () have already done the r8->r4 conversion */
2427 /* The converted value is in an int vreg */
2428 MONO_INST_NEW (cfg, ins, OP_MOVE);
2429 ins->dreg = mono_alloc_ireg (cfg);
2430 ins->sreg1 = in->dreg;
2431 MONO_ADD_INS (cfg->cbb, ins);
2432 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2436 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2437 creg = mono_alloc_ireg (cfg);
2438 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2439 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2442 if (IS_SOFT_FLOAT) {
2443 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2444 ins->dreg = mono_alloc_ireg (cfg);
2445 ins->sreg1 = in->dreg;
2446 MONO_ADD_INS (cfg->cbb, ins);
2447 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2449 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2450 ins->dreg = mono_alloc_ireg (cfg);
2451 ins->sreg1 = in->dreg;
2452 MONO_ADD_INS (cfg->cbb, ins);
2453 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2457 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2458 creg = mono_alloc_ireg (cfg);
2459 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2460 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2461 creg = mono_alloc_ireg (cfg);
2462 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2463 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2466 cfg->flags |= MONO_CFG_HAS_FPOUT;
2468 MONO_INST_NEW (cfg, ins, OP_MOVE);
2469 ins->dreg = mono_alloc_ireg (cfg);
2470 ins->sreg1 = in->dreg;
2471 MONO_ADD_INS (cfg->cbb, ins);
2473 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2476 case RegTypeStructByAddr:
2479 /* FIXME: where si the data allocated? */
2480 arg->backend.reg3 = ainfo->reg;
2481 call->used_iregs |= 1 << ainfo->reg;
2482 g_assert_not_reached ();
2485 case RegTypeStructByVal:
2486 case RegTypeGSharedVtInReg:
2487 case RegTypeGSharedVtOnStack:
2489 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2490 ins->opcode = OP_OUTARG_VT;
2491 ins->sreg1 = in->dreg;
2492 ins->klass = in->klass;
2493 ins->inst_p0 = call;
2494 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2495 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2496 mono_call_inst_add_outarg_vt (cfg, call, ins);
2497 MONO_ADD_INS (cfg->cbb, ins);
2500 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2501 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2502 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2503 if (t->type == MONO_TYPE_R8) {
2504 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2507 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2509 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2512 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2515 case RegTypeBaseGen:
2516 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2517 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
2518 MONO_INST_NEW (cfg, ins, OP_MOVE);
2519 ins->dreg = mono_alloc_ireg (cfg);
2520 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
2521 MONO_ADD_INS (cfg->cbb, ins);
2522 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2523 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2526 /* This should work for soft-float as well */
2528 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2529 creg = mono_alloc_ireg (cfg);
2530 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2531 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2532 creg = mono_alloc_ireg (cfg);
2533 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2534 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2535 cfg->flags |= MONO_CFG_HAS_FPOUT;
2537 g_assert_not_reached ();
2541 int fdreg = mono_alloc_freg (cfg);
2543 if (ainfo->size == 8) {
2544 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2545 ins->sreg1 = in->dreg;
2547 MONO_ADD_INS (cfg->cbb, ins);
2549 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2554 * Mono's register allocator doesn't speak single-precision registers that
2555 * overlap double-precision registers (i.e. armhf). So we have to work around
2556 * the register allocator and load the value from memory manually.
2558 * So we create a variable for the float argument and an instruction to store
2559 * the argument into the variable. We then store the list of these arguments
2560 * in cfg->float_args. This list is then used by emit_float_args later to
2561 * pass the arguments in the various call opcodes.
2563 * This is not very nice, and we should really try to fix the allocator.
2566 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2568 /* Make sure the instruction isn't seen as pointless and removed.
2570 float_arg->flags |= MONO_INST_VOLATILE;
2572 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2574 /* We use the dreg to look up the instruction later. The hreg is used to
2575 * emit the instruction that loads the value into the FP reg.
2577 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2578 fad->vreg = float_arg->dreg;
2579 fad->hreg = ainfo->reg;
2581 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2584 call->used_iregs |= 1 << ainfo->reg;
2585 cfg->flags |= MONO_CFG_HAS_FPOUT;
2589 g_assert_not_reached ();
2593 /* Handle the case where there are no implicit arguments */
2594 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2595 emit_sig_cookie (cfg, call, cinfo);
2597 call->call_info = cinfo;
2598 call->stack_usage = cinfo->stack_usage;
2602 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2608 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2609 ins->dreg = mono_alloc_freg (cfg);
2610 ins->sreg1 = arg->dreg;
2611 MONO_ADD_INS (cfg->cbb, ins);
2612 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2615 g_assert_not_reached ();
2621 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2623 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2625 ArgInfo *ainfo = ins->inst_p1;
2626 int ovf_size = ainfo->vtsize;
2627 int doffset = ainfo->offset;
2628 int struct_size = ainfo->struct_size;
2629 int i, soffset, dreg, tmpreg;
2631 switch (ainfo->storage) {
2632 case RegTypeGSharedVtInReg:
2634 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2636 case RegTypeGSharedVtOnStack:
2637 /* Pass by addr on stack */
2638 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2641 for (i = 0; i < ainfo->nregs; ++i) {
2642 if (ainfo->esize == 4)
2643 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2645 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2646 load->dreg = mono_alloc_freg (cfg);
2647 load->inst_basereg = src->dreg;
2648 load->inst_offset = i * ainfo->esize;
2649 MONO_ADD_INS (cfg->cbb, load);
2651 if (ainfo->esize == 4) {
2654 /* See RegTypeFP in mono_arch_emit_call () */
2655 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2656 float_arg->flags |= MONO_INST_VOLATILE;
2657 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2659 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2660 fad->vreg = float_arg->dreg;
2661 fad->hreg = ainfo->reg + i;
2663 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2665 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + i, load);
2671 for (i = 0; i < ainfo->size; ++i) {
2672 dreg = mono_alloc_ireg (cfg);
2673 switch (struct_size) {
2675 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2678 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2681 tmpreg = mono_alloc_ireg (cfg);
2682 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2683 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2684 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2685 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2686 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2687 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2688 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2691 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2694 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2695 soffset += sizeof (gpointer);
2696 struct_size -= sizeof (gpointer);
2698 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2700 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2706 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2708 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2711 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2714 if (COMPILE_LLVM (cfg)) {
2715 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2717 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2718 ins->sreg1 = val->dreg + 1;
2719 ins->sreg2 = val->dreg + 2;
2720 MONO_ADD_INS (cfg->cbb, ins);
2725 case MONO_ARM_FPU_NONE:
2726 if (ret->type == MONO_TYPE_R8) {
2729 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2730 ins->dreg = cfg->ret->dreg;
2731 ins->sreg1 = val->dreg;
2732 MONO_ADD_INS (cfg->cbb, ins);
2735 if (ret->type == MONO_TYPE_R4) {
2736 /* Already converted to an int in method_to_ir () */
2737 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2741 case MONO_ARM_FPU_VFP:
2742 case MONO_ARM_FPU_VFP_HARD:
2743 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2746 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2747 ins->dreg = cfg->ret->dreg;
2748 ins->sreg1 = val->dreg;
2749 MONO_ADD_INS (cfg->cbb, ins);
2754 g_assert_not_reached ();
2758 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2761 #endif /* #ifndef DISABLE_JIT */
2764 mono_arch_is_inst_imm (gint64 imm)
2770 MonoMethodSignature *sig;
2773 MonoType **param_types;
2777 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2781 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2784 switch (cinfo->ret.storage) {
2786 case RegTypeGeneral:
2787 case RegTypeIRegPair:
2788 case RegTypeStructByAddr:
2799 for (i = 0; i < cinfo->nargs; ++i) {
2800 ArgInfo *ainfo = &cinfo->args [i];
2803 switch (ainfo->storage) {
2804 case RegTypeGeneral:
2806 case RegTypeIRegPair:
2809 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2812 case RegTypeStructByVal:
2813 if (ainfo->size == 0)
2814 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2816 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2817 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2825 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2826 for (i = 0; i < sig->param_count; ++i) {
2827 MonoType *t = sig->params [i];
2832 t = mini_get_underlying_type (t);
2855 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2857 ArchDynCallInfo *info;
2861 cinfo = get_call_info (NULL, sig);
2863 if (!dyn_call_supported (cinfo, sig)) {
2868 info = g_new0 (ArchDynCallInfo, 1);
2869 // FIXME: Preprocess the info to speed up start_dyn_call ()
2871 info->cinfo = cinfo;
2872 info->rtype = mini_get_underlying_type (sig->ret);
2873 info->param_types = g_new0 (MonoType*, sig->param_count);
2874 for (i = 0; i < sig->param_count; ++i)
2875 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2877 return (MonoDynCallInfo*)info;
2881 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2883 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2885 g_free (ainfo->cinfo);
2890 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2892 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2893 DynCallArgs *p = (DynCallArgs*)buf;
2894 int arg_index, greg, i, j, pindex;
2895 MonoMethodSignature *sig = dinfo->sig;
2897 g_assert (buf_len >= sizeof (DynCallArgs));
2906 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2907 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2912 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2913 p->regs [greg ++] = (mgreg_t)ret;
2915 for (i = pindex; i < sig->param_count; i++) {
2916 MonoType *t = dinfo->param_types [i];
2917 gpointer *arg = args [arg_index ++];
2918 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2921 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2923 else if (ainfo->storage == RegTypeBase)
2924 slot = PARAM_REGS + (ainfo->offset / 4);
2926 g_assert_not_reached ();
2929 p->regs [slot] = (mgreg_t)*arg;
2934 case MONO_TYPE_STRING:
2935 case MONO_TYPE_CLASS:
2936 case MONO_TYPE_ARRAY:
2937 case MONO_TYPE_SZARRAY:
2938 case MONO_TYPE_OBJECT:
2942 p->regs [slot] = (mgreg_t)*arg;
2945 p->regs [slot] = *(guint8*)arg;
2948 p->regs [slot] = *(gint8*)arg;
2951 p->regs [slot] = *(gint16*)arg;
2954 p->regs [slot] = *(guint16*)arg;
2957 p->regs [slot] = *(gint32*)arg;
2960 p->regs [slot] = *(guint32*)arg;
2964 p->regs [slot ++] = (mgreg_t)arg [0];
2965 p->regs [slot] = (mgreg_t)arg [1];
2968 p->regs [slot] = *(mgreg_t*)arg;
2971 p->regs [slot ++] = (mgreg_t)arg [0];
2972 p->regs [slot] = (mgreg_t)arg [1];
2974 case MONO_TYPE_GENERICINST:
2975 if (MONO_TYPE_IS_REFERENCE (t)) {
2976 p->regs [slot] = (mgreg_t)*arg;
2979 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2980 MonoClass *klass = mono_class_from_mono_type (t);
2981 guint8 *nullable_buf;
2984 size = mono_class_value_size (klass, NULL);
2985 nullable_buf = g_alloca (size);
2986 g_assert (nullable_buf);
2988 /* The argument pointed to by arg is either a boxed vtype or null */
2989 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2991 arg = (gpointer*)nullable_buf;
2997 case MONO_TYPE_VALUETYPE:
2998 g_assert (ainfo->storage == RegTypeStructByVal);
3000 if (ainfo->size == 0)
3001 slot = PARAM_REGS + (ainfo->offset / 4);
3005 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
3006 p->regs [slot ++] = ((mgreg_t*)arg) [j];
3009 g_assert_not_reached ();
3015 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
3017 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
3018 MonoType *ptype = ainfo->rtype;
3019 guint8 *ret = ((DynCallArgs*)buf)->ret;
3020 mgreg_t res = ((DynCallArgs*)buf)->res;
3021 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
3023 switch (ptype->type) {
3024 case MONO_TYPE_VOID:
3025 *(gpointer*)ret = NULL;
3027 case MONO_TYPE_STRING:
3028 case MONO_TYPE_CLASS:
3029 case MONO_TYPE_ARRAY:
3030 case MONO_TYPE_SZARRAY:
3031 case MONO_TYPE_OBJECT:
3035 *(gpointer*)ret = (gpointer)res;
3041 *(guint8*)ret = res;
3044 *(gint16*)ret = res;
3047 *(guint16*)ret = res;
3050 *(gint32*)ret = res;
3053 *(guint32*)ret = res;
3057 /* This handles endianness as well */
3058 ((gint32*)ret) [0] = res;
3059 ((gint32*)ret) [1] = res2;
3061 case MONO_TYPE_GENERICINST:
3062 if (MONO_TYPE_IS_REFERENCE (ptype)) {
3063 *(gpointer*)ret = (gpointer)res;
3068 case MONO_TYPE_VALUETYPE:
3069 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
3074 *(float*)ret = *(float*)&res;
3076 case MONO_TYPE_R8: {
3083 *(double*)ret = *(double*)®s;
3087 g_assert_not_reached ();
3094 * Allow tracing to work with this interface (with an optional argument)
3098 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3102 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3103 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3104 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3105 code = emit_call_reg (code, ARMREG_R2);
3119 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3122 int save_mode = SAVE_NONE;
3124 MonoMethod *method = cfg->method;
3125 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3126 int rtype = ret_type->type;
3127 int save_offset = cfg->param_area;
3131 offset = code - cfg->native_code;
3132 /* we need about 16 instructions */
3133 if (offset > (cfg->code_size - 16 * 4)) {
3134 cfg->code_size *= 2;
3135 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3136 code = cfg->native_code + offset;
3139 case MONO_TYPE_VOID:
3140 /* special case string .ctor icall */
3141 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3142 save_mode = SAVE_ONE;
3144 save_mode = SAVE_NONE;
3148 save_mode = SAVE_TWO;
3152 save_mode = SAVE_ONE_FP;
3154 save_mode = SAVE_ONE;
3158 save_mode = SAVE_TWO_FP;
3160 save_mode = SAVE_TWO;
3162 case MONO_TYPE_GENERICINST:
3163 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3164 save_mode = SAVE_ONE;
3168 case MONO_TYPE_VALUETYPE:
3169 save_mode = SAVE_STRUCT;
3172 save_mode = SAVE_ONE;
3176 switch (save_mode) {
3178 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3179 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3180 if (enable_arguments) {
3181 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3182 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3186 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3187 if (enable_arguments) {
3188 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3192 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3193 if (enable_arguments) {
3194 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3198 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3199 if (enable_arguments) {
3200 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3204 if (enable_arguments) {
3205 /* FIXME: get the actual address */
3206 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3214 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3215 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3216 code = emit_call_reg (code, ARMREG_IP);
3218 switch (save_mode) {
3220 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3221 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3224 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3227 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3230 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3241 * The immediate field for cond branches is big enough for all reasonable methods
3243 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3244 if (0 && ins->inst_true_bb->native_offset) { \
3245 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3247 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3248 ARM_B_COND (code, (condcode), 0); \
3251 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3253 /* emit an exception if condition is fail
3255 * We assign the extra code used to throw the implicit exceptions
3256 * to cfg->bb_exit as far as the big branch handling is concerned
3258 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3260 mono_add_patch_info (cfg, code - cfg->native_code, \
3261 MONO_PATCH_INFO_EXC, exc_name); \
3262 ARM_BL_COND (code, (condcode), 0); \
3265 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3268 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3273 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3277 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3278 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3280 switch (ins->opcode) {
3283 /* Already done by an arch-independent pass */
3285 case OP_LOAD_MEMBASE:
3286 case OP_LOADI4_MEMBASE:
3288 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3289 * OP_LOAD_MEMBASE offset(basereg), reg
3291 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3292 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3293 ins->inst_basereg == last_ins->inst_destbasereg &&
3294 ins->inst_offset == last_ins->inst_offset) {
3295 if (ins->dreg == last_ins->sreg1) {
3296 MONO_DELETE_INS (bb, ins);
3299 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3300 ins->opcode = OP_MOVE;
3301 ins->sreg1 = last_ins->sreg1;
3305 * Note: reg1 must be different from the basereg in the second load
3306 * OP_LOAD_MEMBASE offset(basereg), reg1
3307 * OP_LOAD_MEMBASE offset(basereg), reg2
3309 * OP_LOAD_MEMBASE offset(basereg), reg1
3310 * OP_MOVE reg1, reg2
3312 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3313 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3314 ins->inst_basereg != last_ins->dreg &&
3315 ins->inst_basereg == last_ins->inst_basereg &&
3316 ins->inst_offset == last_ins->inst_offset) {
3318 if (ins->dreg == last_ins->dreg) {
3319 MONO_DELETE_INS (bb, ins);
3322 ins->opcode = OP_MOVE;
3323 ins->sreg1 = last_ins->dreg;
3326 //g_assert_not_reached ();
3330 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3331 * OP_LOAD_MEMBASE offset(basereg), reg
3333 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3334 * OP_ICONST reg, imm
3336 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3337 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3338 ins->inst_basereg == last_ins->inst_destbasereg &&
3339 ins->inst_offset == last_ins->inst_offset) {
3340 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3341 ins->opcode = OP_ICONST;
3342 ins->inst_c0 = last_ins->inst_imm;
3343 g_assert_not_reached (); // check this rule
3347 case OP_LOADU1_MEMBASE:
3348 case OP_LOADI1_MEMBASE:
3349 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3350 ins->inst_basereg == last_ins->inst_destbasereg &&
3351 ins->inst_offset == last_ins->inst_offset) {
3352 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3353 ins->sreg1 = last_ins->sreg1;
3356 case OP_LOADU2_MEMBASE:
3357 case OP_LOADI2_MEMBASE:
3358 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3359 ins->inst_basereg == last_ins->inst_destbasereg &&
3360 ins->inst_offset == last_ins->inst_offset) {
3361 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3362 ins->sreg1 = last_ins->sreg1;
3366 ins->opcode = OP_MOVE;
3370 if (ins->dreg == ins->sreg1) {
3371 MONO_DELETE_INS (bb, ins);
3375 * OP_MOVE sreg, dreg
3376 * OP_MOVE dreg, sreg
3378 if (last_ins && last_ins->opcode == OP_MOVE &&
3379 ins->sreg1 == last_ins->dreg &&
3380 ins->dreg == last_ins->sreg1) {
3381 MONO_DELETE_INS (bb, ins);
3390 * the branch_cc_table should maintain the order of these
3404 branch_cc_table [] = {
3418 #define ADD_NEW_INS(cfg,dest,op) do { \
3419 MONO_INST_NEW ((cfg), (dest), (op)); \
3420 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3424 map_to_reg_reg_op (int op)
3433 case OP_COMPARE_IMM:
3435 case OP_ICOMPARE_IMM:
3449 case OP_LOAD_MEMBASE:
3450 return OP_LOAD_MEMINDEX;
3451 case OP_LOADI4_MEMBASE:
3452 return OP_LOADI4_MEMINDEX;
3453 case OP_LOADU4_MEMBASE:
3454 return OP_LOADU4_MEMINDEX;
3455 case OP_LOADU1_MEMBASE:
3456 return OP_LOADU1_MEMINDEX;
3457 case OP_LOADI2_MEMBASE:
3458 return OP_LOADI2_MEMINDEX;
3459 case OP_LOADU2_MEMBASE:
3460 return OP_LOADU2_MEMINDEX;
3461 case OP_LOADI1_MEMBASE:
3462 return OP_LOADI1_MEMINDEX;
3463 case OP_STOREI1_MEMBASE_REG:
3464 return OP_STOREI1_MEMINDEX;
3465 case OP_STOREI2_MEMBASE_REG:
3466 return OP_STOREI2_MEMINDEX;
3467 case OP_STOREI4_MEMBASE_REG:
3468 return OP_STOREI4_MEMINDEX;
3469 case OP_STORE_MEMBASE_REG:
3470 return OP_STORE_MEMINDEX;
3471 case OP_STORER4_MEMBASE_REG:
3472 return OP_STORER4_MEMINDEX;
3473 case OP_STORER8_MEMBASE_REG:
3474 return OP_STORER8_MEMINDEX;
3475 case OP_STORE_MEMBASE_IMM:
3476 return OP_STORE_MEMBASE_REG;
3477 case OP_STOREI1_MEMBASE_IMM:
3478 return OP_STOREI1_MEMBASE_REG;
3479 case OP_STOREI2_MEMBASE_IMM:
3480 return OP_STOREI2_MEMBASE_REG;
3481 case OP_STOREI4_MEMBASE_IMM:
3482 return OP_STOREI4_MEMBASE_REG;
3484 g_assert_not_reached ();
3488 * Remove from the instruction list the instructions that can't be
3489 * represented with very simple instructions with no register
3493 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3495 MonoInst *ins, *temp, *last_ins = NULL;
3496 int rot_amount, imm8, low_imm;
3498 MONO_BB_FOR_EACH_INS (bb, ins) {
3500 switch (ins->opcode) {
3504 case OP_COMPARE_IMM:
3505 case OP_ICOMPARE_IMM:
3519 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3520 ADD_NEW_INS (cfg, temp, OP_ICONST);
3521 temp->inst_c0 = ins->inst_imm;
3522 temp->dreg = mono_alloc_ireg (cfg);
3523 ins->sreg2 = temp->dreg;
3524 ins->opcode = mono_op_imm_to_op (ins->opcode);
3526 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3532 if (ins->inst_imm == 1) {
3533 ins->opcode = OP_MOVE;
3536 if (ins->inst_imm == 0) {
3537 ins->opcode = OP_ICONST;
3541 imm8 = mono_is_power_of_two (ins->inst_imm);
3543 ins->opcode = OP_SHL_IMM;
3544 ins->inst_imm = imm8;
3547 ADD_NEW_INS (cfg, temp, OP_ICONST);
3548 temp->inst_c0 = ins->inst_imm;
3549 temp->dreg = mono_alloc_ireg (cfg);
3550 ins->sreg2 = temp->dreg;
3551 ins->opcode = OP_IMUL;
3557 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3558 /* ARM sets the C flag to 1 if there was _no_ overflow */
3559 ins->next->opcode = OP_COND_EXC_NC;
3562 case OP_IDIV_UN_IMM:
3564 case OP_IREM_UN_IMM:
3565 ADD_NEW_INS (cfg, temp, OP_ICONST);
3566 temp->inst_c0 = ins->inst_imm;
3567 temp->dreg = mono_alloc_ireg (cfg);
3568 ins->sreg2 = temp->dreg;
3569 ins->opcode = mono_op_imm_to_op (ins->opcode);
3571 case OP_LOCALLOC_IMM:
3572 ADD_NEW_INS (cfg, temp, OP_ICONST);
3573 temp->inst_c0 = ins->inst_imm;
3574 temp->dreg = mono_alloc_ireg (cfg);
3575 ins->sreg1 = temp->dreg;
3576 ins->opcode = OP_LOCALLOC;
3578 case OP_LOAD_MEMBASE:
3579 case OP_LOADI4_MEMBASE:
3580 case OP_LOADU4_MEMBASE:
3581 case OP_LOADU1_MEMBASE:
3582 /* we can do two things: load the immed in a register
3583 * and use an indexed load, or see if the immed can be
3584 * represented as an ad_imm + a load with a smaller offset
3585 * that fits. We just do the first for now, optimize later.
3587 if (arm_is_imm12 (ins->inst_offset))
3589 ADD_NEW_INS (cfg, temp, OP_ICONST);
3590 temp->inst_c0 = ins->inst_offset;
3591 temp->dreg = mono_alloc_ireg (cfg);
3592 ins->sreg2 = temp->dreg;
3593 ins->opcode = map_to_reg_reg_op (ins->opcode);
3595 case OP_LOADI2_MEMBASE:
3596 case OP_LOADU2_MEMBASE:
3597 case OP_LOADI1_MEMBASE:
3598 if (arm_is_imm8 (ins->inst_offset))
3600 ADD_NEW_INS (cfg, temp, OP_ICONST);
3601 temp->inst_c0 = ins->inst_offset;
3602 temp->dreg = mono_alloc_ireg (cfg);
3603 ins->sreg2 = temp->dreg;
3604 ins->opcode = map_to_reg_reg_op (ins->opcode);
3606 case OP_LOADR4_MEMBASE:
3607 case OP_LOADR8_MEMBASE:
3608 if (arm_is_fpimm8 (ins->inst_offset))
3610 low_imm = ins->inst_offset & 0x1ff;
3611 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3612 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3613 temp->inst_imm = ins->inst_offset & ~0x1ff;
3614 temp->sreg1 = ins->inst_basereg;
3615 temp->dreg = mono_alloc_ireg (cfg);
3616 ins->inst_basereg = temp->dreg;
3617 ins->inst_offset = low_imm;
3621 ADD_NEW_INS (cfg, temp, OP_ICONST);
3622 temp->inst_c0 = ins->inst_offset;
3623 temp->dreg = mono_alloc_ireg (cfg);
3625 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3626 add_ins->sreg1 = ins->inst_basereg;
3627 add_ins->sreg2 = temp->dreg;
3628 add_ins->dreg = mono_alloc_ireg (cfg);
3630 ins->inst_basereg = add_ins->dreg;
3631 ins->inst_offset = 0;
3634 case OP_STORE_MEMBASE_REG:
3635 case OP_STOREI4_MEMBASE_REG:
3636 case OP_STOREI1_MEMBASE_REG:
3637 if (arm_is_imm12 (ins->inst_offset))
3639 ADD_NEW_INS (cfg, temp, OP_ICONST);
3640 temp->inst_c0 = ins->inst_offset;
3641 temp->dreg = mono_alloc_ireg (cfg);
3642 ins->sreg2 = temp->dreg;
3643 ins->opcode = map_to_reg_reg_op (ins->opcode);
3645 case OP_STOREI2_MEMBASE_REG:
3646 if (arm_is_imm8 (ins->inst_offset))
3648 ADD_NEW_INS (cfg, temp, OP_ICONST);
3649 temp->inst_c0 = ins->inst_offset;
3650 temp->dreg = mono_alloc_ireg (cfg);
3651 ins->sreg2 = temp->dreg;
3652 ins->opcode = map_to_reg_reg_op (ins->opcode);
3654 case OP_STORER4_MEMBASE_REG:
3655 case OP_STORER8_MEMBASE_REG:
3656 if (arm_is_fpimm8 (ins->inst_offset))
3658 low_imm = ins->inst_offset & 0x1ff;
3659 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3660 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3661 temp->inst_imm = ins->inst_offset & ~0x1ff;
3662 temp->sreg1 = ins->inst_destbasereg;
3663 temp->dreg = mono_alloc_ireg (cfg);
3664 ins->inst_destbasereg = temp->dreg;
3665 ins->inst_offset = low_imm;
3669 ADD_NEW_INS (cfg, temp, OP_ICONST);
3670 temp->inst_c0 = ins->inst_offset;
3671 temp->dreg = mono_alloc_ireg (cfg);
3673 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3674 add_ins->sreg1 = ins->inst_destbasereg;
3675 add_ins->sreg2 = temp->dreg;
3676 add_ins->dreg = mono_alloc_ireg (cfg);
3678 ins->inst_destbasereg = add_ins->dreg;
3679 ins->inst_offset = 0;
3682 case OP_STORE_MEMBASE_IMM:
3683 case OP_STOREI1_MEMBASE_IMM:
3684 case OP_STOREI2_MEMBASE_IMM:
3685 case OP_STOREI4_MEMBASE_IMM:
3686 ADD_NEW_INS (cfg, temp, OP_ICONST);
3687 temp->inst_c0 = ins->inst_imm;
3688 temp->dreg = mono_alloc_ireg (cfg);
3689 ins->sreg1 = temp->dreg;
3690 ins->opcode = map_to_reg_reg_op (ins->opcode);
3692 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3695 gboolean swap = FALSE;
3699 /* Optimized away */
3704 /* Some fp compares require swapped operands */
3705 switch (ins->next->opcode) {
3707 ins->next->opcode = OP_FBLT;
3711 ins->next->opcode = OP_FBLT_UN;
3715 ins->next->opcode = OP_FBGE;
3719 ins->next->opcode = OP_FBGE_UN;
3727 ins->sreg1 = ins->sreg2;
3736 bb->last_ins = last_ins;
3737 bb->max_vreg = cfg->next_vreg;
3741 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3745 if (long_ins->opcode == OP_LNEG) {
3747 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3748 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3754 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3756 /* sreg is a float, dreg is an integer reg */
3758 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3760 ARM_TOSIZD (code, vfp_scratch1, sreg);
3762 ARM_TOUIZD (code, vfp_scratch1, sreg);
3763 ARM_FMRS (code, dreg, vfp_scratch1);
3764 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3768 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3769 else if (size == 2) {
3770 ARM_SHL_IMM (code, dreg, dreg, 16);
3771 ARM_SHR_IMM (code, dreg, dreg, 16);
3775 ARM_SHL_IMM (code, dreg, dreg, 24);
3776 ARM_SAR_IMM (code, dreg, dreg, 24);
3777 } else if (size == 2) {
3778 ARM_SHL_IMM (code, dreg, dreg, 16);
3779 ARM_SAR_IMM (code, dreg, dreg, 16);
3786 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3788 /* sreg is a float, dreg is an integer reg */
3790 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3792 ARM_TOSIZS (code, vfp_scratch1, sreg);
3794 ARM_TOUIZS (code, vfp_scratch1, sreg);
3795 ARM_FMRS (code, dreg, vfp_scratch1);
3796 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3800 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3801 else if (size == 2) {
3802 ARM_SHL_IMM (code, dreg, dreg, 16);
3803 ARM_SHR_IMM (code, dreg, dreg, 16);
3807 ARM_SHL_IMM (code, dreg, dreg, 24);
3808 ARM_SAR_IMM (code, dreg, dreg, 24);
3809 } else if (size == 2) {
3810 ARM_SHL_IMM (code, dreg, dreg, 16);
3811 ARM_SAR_IMM (code, dreg, dreg, 16);
3817 #endif /* #ifndef DISABLE_JIT */
3819 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3822 emit_thunk (guint8 *code, gconstpointer target)
3826 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3827 if (thumb_supported)
3828 ARM_BX (code, ARMREG_IP);
3830 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3831 *(guint32*)code = (guint32)target;
3833 mono_arch_flush_icache (p, code - p);
3837 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3839 MonoJitInfo *ji = NULL;
3840 MonoThunkJitInfo *info;
3843 guint8 *orig_target;
3844 guint8 *target_thunk;
3847 domain = mono_domain_get ();
3851 * This can be called multiple times during JITting,
3852 * save the current position in cfg->arch to avoid
3853 * doing a O(n^2) search.
3855 if (!cfg->arch.thunks) {
3856 cfg->arch.thunks = cfg->thunks;
3857 cfg->arch.thunks_size = cfg->thunk_area;
3859 thunks = cfg->arch.thunks;
3860 thunks_size = cfg->arch.thunks_size;
3862 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3863 g_assert_not_reached ();
3866 g_assert (*(guint32*)thunks == 0);
3867 emit_thunk (thunks, target);
3868 arm_patch (code, thunks);
3870 cfg->arch.thunks += THUNK_SIZE;
3871 cfg->arch.thunks_size -= THUNK_SIZE;
3873 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3875 info = mono_jit_info_get_thunk_info (ji);
3878 thunks = (guint8*)ji->code_start + info->thunks_offset;
3879 thunks_size = info->thunks_size;
3881 orig_target = mono_arch_get_call_target (code + 4);
3883 mono_mini_arch_lock ();
3885 target_thunk = NULL;
3886 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3887 /* The call already points to a thunk, because of trampolines etc. */
3888 target_thunk = orig_target;
3890 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3891 if (((guint32*)p) [0] == 0) {
3899 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
3901 if (!target_thunk) {
3902 mono_mini_arch_unlock ();
3903 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3904 g_assert_not_reached ();
3907 emit_thunk (target_thunk, target);
3908 arm_patch (code, target_thunk);
3909 mono_arch_flush_icache (code, 4);
3911 mono_mini_arch_unlock ();
3916 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3918 guint32 *code32 = (void*)code;
3919 guint32 ins = *code32;
3920 guint32 prim = (ins >> 25) & 7;
3921 guint32 tval = GPOINTER_TO_UINT (target);
3923 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3924 if (prim == 5) { /* 101b */
3925 /* the diff starts 8 bytes from the branch opcode */
3926 gint diff = target - code - 8;
3928 gint tmask = 0xffffffff;
3929 if (tval & 1) { /* entering thumb mode */
3930 diff = target - 1 - code - 8;
3931 g_assert (thumb_supported);
3932 tbits = 0xf << 28; /* bl->blx bit pattern */
3933 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3934 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3938 tmask = ~(1 << 24); /* clear the link bit */
3939 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3944 if (diff <= 33554431) {
3946 ins = (ins & 0xff000000) | diff;
3948 *code32 = ins | tbits;
3952 /* diff between 0 and -33554432 */
3953 if (diff >= -33554432) {
3955 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3957 *code32 = ins | tbits;
3962 handle_thunk (cfg, domain, code, target);
3966 #ifdef USE_JUMP_TABLES
3968 gpointer *jte = mono_jumptable_get_entry (code);
3970 jte [0] = (gpointer) target;
3974 * The alternative call sequences looks like this:
3976 * ldr ip, [pc] // loads the address constant
3977 * b 1f // jumps around the constant
3978 * address constant embedded in the code
3983 * There are two cases for patching:
3984 * a) at the end of method emission: in this case code points to the start
3985 * of the call sequence
3986 * b) during runtime patching of the call site: in this case code points
3987 * to the mov pc, ip instruction
3989 * We have to handle also the thunk jump code sequence:
3993 * address constant // execution never reaches here
3995 if ((ins & 0x0ffffff0) == 0x12fff10) {
3996 /* Branch and exchange: the address is constructed in a reg
3997 * We can patch BX when the code sequence is the following:
3998 * ldr ip, [pc, #0] ; 0x8
4005 guint8 *emit = (guint8*)ccode;
4006 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4008 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4009 ARM_BX (emit, ARMREG_IP);
4011 /*patching from magic trampoline*/
4012 if (ins == ccode [3]) {
4013 g_assert (code32 [-4] == ccode [0]);
4014 g_assert (code32 [-3] == ccode [1]);
4015 g_assert (code32 [-1] == ccode [2]);
4016 code32 [-2] = (guint32)target;
4019 /*patching from JIT*/
4020 if (ins == ccode [0]) {
4021 g_assert (code32 [1] == ccode [1]);
4022 g_assert (code32 [3] == ccode [2]);
4023 g_assert (code32 [4] == ccode [3]);
4024 code32 [2] = (guint32)target;
4027 g_assert_not_reached ();
4028 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
4036 guint8 *emit = (guint8*)ccode;
4037 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4039 ARM_BLX_REG (emit, ARMREG_IP);
4041 g_assert (code32 [-3] == ccode [0]);
4042 g_assert (code32 [-2] == ccode [1]);
4043 g_assert (code32 [0] == ccode [2]);
4045 code32 [-1] = (guint32)target;
4048 guint32 *tmp = ccode;
4049 guint8 *emit = (guint8*)tmp;
4050 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4051 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4052 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
4053 ARM_BX (emit, ARMREG_IP);
4054 if (ins == ccode [2]) {
4055 g_assert_not_reached (); // should be -2 ...
4056 code32 [-1] = (guint32)target;
4059 if (ins == ccode [0]) {
4060 /* handles both thunk jump code and the far call sequence */
4061 code32 [2] = (guint32)target;
4064 g_assert_not_reached ();
4066 // g_print ("patched with 0x%08x\n", ins);
4071 arm_patch (guchar *code, const guchar *target)
4073 arm_patch_general (NULL, NULL, code, target);
4077 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4078 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4079 * to be used with the emit macros.
4080 * Return -1 otherwise.
4083 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4086 for (i = 0; i < 31; i+= 2) {
4087 res = (val << (32 - i)) | (val >> i);
4090 *rot_amount = i? 32 - i: 0;
4097 * Emits in code a sequence of instructions that load the value 'val'
4098 * into the dreg register. Uses at most 4 instructions.
4101 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4103 int imm8, rot_amount;
4105 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4106 /* skip the constant pool */
4112 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4113 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4114 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4115 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4118 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4120 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4124 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4126 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4128 if (val & 0xFF0000) {
4129 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4131 if (val & 0xFF000000) {
4132 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4134 } else if (val & 0xFF00) {
4135 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4136 if (val & 0xFF0000) {
4137 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4139 if (val & 0xFF000000) {
4140 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4142 } else if (val & 0xFF0000) {
4143 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4144 if (val & 0xFF000000) {
4145 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4148 //g_assert_not_reached ();
4154 mono_arm_thumb_supported (void)
4156 return thumb_supported;
4162 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4167 call = (MonoCallInst*)ins;
4168 cinfo = call->call_info;
4170 switch (cinfo->ret.storage) {
4172 MonoInst *loc = cfg->arch.vret_addr_loc;
4175 /* Load the destination address */
4176 g_assert (loc && loc->opcode == OP_REGOFFSET);
4178 if (arm_is_imm12 (loc->inst_offset)) {
4179 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4181 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4182 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4184 for (i = 0; i < cinfo->ret.nregs; ++i) {
4185 if (cinfo->ret.esize == 4)
4186 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4188 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4196 switch (ins->opcode) {
4199 case OP_FCALL_MEMBASE:
4201 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4202 if (sig_ret->type == MONO_TYPE_R4) {
4203 if (IS_HARD_FLOAT) {
4204 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4206 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4207 ARM_CVTS (code, ins->dreg, ins->dreg);
4210 if (IS_HARD_FLOAT) {
4211 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4213 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4220 case OP_RCALL_MEMBASE: {
4225 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4226 g_assert (sig_ret->type == MONO_TYPE_R4);
4227 if (IS_HARD_FLOAT) {
4228 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4230 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4231 ARM_CPYS (code, ins->dreg, ins->dreg);
4243 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4248 guint8 *code = cfg->native_code + cfg->code_len;
4249 MonoInst *last_ins = NULL;
4250 guint last_offset = 0;
4252 int imm8, rot_amount;
4254 /* we don't align basic blocks of loops on arm */
4256 if (cfg->verbose_level > 2)
4257 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4259 cpos = bb->max_offset;
4261 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4262 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4263 //g_assert (!mono_compile_aot);
4266 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4267 /* this is not thread save, but good enough */
4268 /* fixme: howto handle overflows? */
4269 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4272 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4273 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4274 (gpointer)"mono_break");
4275 code = emit_call_seq (cfg, code);
4278 MONO_BB_FOR_EACH_INS (bb, ins) {
4279 offset = code - cfg->native_code;
4281 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4283 if (offset > (cfg->code_size - max_len - 16)) {
4284 cfg->code_size *= 2;
4285 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4286 code = cfg->native_code + offset;
4288 // if (ins->cil_code)
4289 // g_print ("cil code\n");
4290 mono_debug_record_line_number (cfg, ins, offset);
4292 switch (ins->opcode) {
4293 case OP_MEMORY_BARRIER:
4295 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4296 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4300 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4302 case OP_TLS_GET_REG:
4303 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4306 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4308 case OP_TLS_SET_REG:
4309 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4311 case OP_ATOMIC_EXCHANGE_I4:
4312 case OP_ATOMIC_CAS_I4:
4313 case OP_ATOMIC_ADD_I4: {
4317 g_assert (v7_supported);
4320 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4322 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4324 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4328 g_assert (cfg->arch.atomic_tmp_offset != -1);
4329 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4331 switch (ins->opcode) {
4332 case OP_ATOMIC_EXCHANGE_I4:
4334 ARM_DMB (code, ARM_DMB_SY);
4335 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4336 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4337 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4339 ARM_B_COND (code, ARMCOND_NE, 0);
4340 arm_patch (buf [1], buf [0]);
4342 case OP_ATOMIC_CAS_I4:
4343 ARM_DMB (code, ARM_DMB_SY);
4345 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4346 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4348 ARM_B_COND (code, ARMCOND_NE, 0);
4349 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4350 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4352 ARM_B_COND (code, ARMCOND_NE, 0);
4353 arm_patch (buf [2], buf [0]);
4354 arm_patch (buf [1], code);
4356 case OP_ATOMIC_ADD_I4:
4358 ARM_DMB (code, ARM_DMB_SY);
4359 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4360 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4361 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4362 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4364 ARM_B_COND (code, ARMCOND_NE, 0);
4365 arm_patch (buf [1], buf [0]);
4368 g_assert_not_reached ();
4371 ARM_DMB (code, ARM_DMB_SY);
4372 if (tmpreg != ins->dreg)
4373 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4374 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4377 case OP_ATOMIC_LOAD_I1:
4378 case OP_ATOMIC_LOAD_U1:
4379 case OP_ATOMIC_LOAD_I2:
4380 case OP_ATOMIC_LOAD_U2:
4381 case OP_ATOMIC_LOAD_I4:
4382 case OP_ATOMIC_LOAD_U4:
4383 case OP_ATOMIC_LOAD_R4:
4384 case OP_ATOMIC_LOAD_R8: {
4385 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4386 ARM_DMB (code, ARM_DMB_SY);
4388 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4390 switch (ins->opcode) {
4391 case OP_ATOMIC_LOAD_I1:
4392 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4394 case OP_ATOMIC_LOAD_U1:
4395 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4397 case OP_ATOMIC_LOAD_I2:
4398 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4400 case OP_ATOMIC_LOAD_U2:
4401 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4403 case OP_ATOMIC_LOAD_I4:
4404 case OP_ATOMIC_LOAD_U4:
4405 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4407 case OP_ATOMIC_LOAD_R4:
4409 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4410 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4412 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4413 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4414 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4415 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4416 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4419 case OP_ATOMIC_LOAD_R8:
4420 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4421 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4425 ARM_DMB (code, ARM_DMB_SY);
4428 case OP_ATOMIC_STORE_I1:
4429 case OP_ATOMIC_STORE_U1:
4430 case OP_ATOMIC_STORE_I2:
4431 case OP_ATOMIC_STORE_U2:
4432 case OP_ATOMIC_STORE_I4:
4433 case OP_ATOMIC_STORE_U4:
4434 case OP_ATOMIC_STORE_R4:
4435 case OP_ATOMIC_STORE_R8: {
4436 ARM_DMB (code, ARM_DMB_SY);
4438 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4440 switch (ins->opcode) {
4441 case OP_ATOMIC_STORE_I1:
4442 case OP_ATOMIC_STORE_U1:
4443 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4445 case OP_ATOMIC_STORE_I2:
4446 case OP_ATOMIC_STORE_U2:
4447 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4449 case OP_ATOMIC_STORE_I4:
4450 case OP_ATOMIC_STORE_U4:
4451 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4453 case OP_ATOMIC_STORE_R4:
4455 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4456 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4458 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4459 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4460 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4461 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4462 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4465 case OP_ATOMIC_STORE_R8:
4466 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4467 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4471 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4472 ARM_DMB (code, ARM_DMB_SY);
4476 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4477 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4480 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4481 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4483 case OP_STOREI1_MEMBASE_IMM:
4484 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4485 g_assert (arm_is_imm12 (ins->inst_offset));
4486 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4488 case OP_STOREI2_MEMBASE_IMM:
4489 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4490 g_assert (arm_is_imm8 (ins->inst_offset));
4491 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4493 case OP_STORE_MEMBASE_IMM:
4494 case OP_STOREI4_MEMBASE_IMM:
4495 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4496 g_assert (arm_is_imm12 (ins->inst_offset));
4497 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4499 case OP_STOREI1_MEMBASE_REG:
4500 g_assert (arm_is_imm12 (ins->inst_offset));
4501 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4503 case OP_STOREI2_MEMBASE_REG:
4504 g_assert (arm_is_imm8 (ins->inst_offset));
4505 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4507 case OP_STORE_MEMBASE_REG:
4508 case OP_STOREI4_MEMBASE_REG:
4509 /* this case is special, since it happens for spill code after lowering has been called */
4510 if (arm_is_imm12 (ins->inst_offset)) {
4511 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4513 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4514 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4517 case OP_STOREI1_MEMINDEX:
4518 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4520 case OP_STOREI2_MEMINDEX:
4521 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4523 case OP_STORE_MEMINDEX:
4524 case OP_STOREI4_MEMINDEX:
4525 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4528 g_assert_not_reached ();
4530 case OP_LOAD_MEMINDEX:
4531 case OP_LOADI4_MEMINDEX:
4532 case OP_LOADU4_MEMINDEX:
4533 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4535 case OP_LOADI1_MEMINDEX:
4536 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4538 case OP_LOADU1_MEMINDEX:
4539 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4541 case OP_LOADI2_MEMINDEX:
4542 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4544 case OP_LOADU2_MEMINDEX:
4545 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4547 case OP_LOAD_MEMBASE:
4548 case OP_LOADI4_MEMBASE:
4549 case OP_LOADU4_MEMBASE:
4550 /* this case is special, since it happens for spill code after lowering has been called */
4551 if (arm_is_imm12 (ins->inst_offset)) {
4552 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4554 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4555 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4558 case OP_LOADI1_MEMBASE:
4559 g_assert (arm_is_imm8 (ins->inst_offset));
4560 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4562 case OP_LOADU1_MEMBASE:
4563 g_assert (arm_is_imm12 (ins->inst_offset));
4564 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4566 case OP_LOADU2_MEMBASE:
4567 g_assert (arm_is_imm8 (ins->inst_offset));
4568 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4570 case OP_LOADI2_MEMBASE:
4571 g_assert (arm_is_imm8 (ins->inst_offset));
4572 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4574 case OP_ICONV_TO_I1:
4575 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4576 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4578 case OP_ICONV_TO_I2:
4579 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4580 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4582 case OP_ICONV_TO_U1:
4583 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4585 case OP_ICONV_TO_U2:
4586 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4587 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4591 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4593 case OP_COMPARE_IMM:
4594 case OP_ICOMPARE_IMM:
4595 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4596 g_assert (imm8 >= 0);
4597 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4601 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4602 * So instead of emitting a trap, we emit a call a C function and place a
4605 //*(int*)code = 0xef9f0001;
4608 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4609 (gpointer)"mono_break");
4610 code = emit_call_seq (cfg, code);
4612 case OP_RELAXED_NOP:
4617 case OP_DUMMY_STORE:
4618 case OP_DUMMY_ICONST:
4619 case OP_DUMMY_R8CONST:
4620 case OP_NOT_REACHED:
4623 case OP_IL_SEQ_POINT:
4624 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4626 case OP_SEQ_POINT: {
4628 MonoInst *info_var = cfg->arch.seq_point_info_var;
4629 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4630 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
4631 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4632 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4634 int dreg = ARMREG_LR;
4636 if (cfg->soft_breakpoints) {
4637 g_assert (!cfg->compile_aot);
4641 * For AOT, we use one got slot per method, which will point to a
4642 * SeqPointInfo structure, containing all the information required
4643 * by the code below.
4645 if (cfg->compile_aot) {
4646 g_assert (info_var);
4647 g_assert (info_var->opcode == OP_REGOFFSET);
4648 g_assert (arm_is_imm12 (info_var->inst_offset));
4651 if (!cfg->soft_breakpoints) {
4653 * Read from the single stepping trigger page. This will cause a
4654 * SIGSEGV when single stepping is enabled.
4655 * We do this _before_ the breakpoint, so single stepping after
4656 * a breakpoint is hit will step to the next IL offset.
4658 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4661 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4662 if (cfg->soft_breakpoints) {
4663 /* Load the address of the sequence point trigger variable. */
4666 g_assert (var->opcode == OP_REGOFFSET);
4667 g_assert (arm_is_imm12 (var->inst_offset));
4668 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4670 /* Read the value and check whether it is non-zero. */
4671 ARM_LDR_IMM (code, dreg, dreg, 0);
4672 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4674 /* Load the address of the sequence point method. */
4675 var = ss_method_var;
4677 g_assert (var->opcode == OP_REGOFFSET);
4678 g_assert (arm_is_imm12 (var->inst_offset));
4679 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4681 /* Call it conditionally. */
4682 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4684 if (cfg->compile_aot) {
4685 /* Load the trigger page addr from the variable initialized in the prolog */
4686 var = ss_trigger_page_var;
4688 g_assert (var->opcode == OP_REGOFFSET);
4689 g_assert (arm_is_imm12 (var->inst_offset));
4690 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4692 #ifdef USE_JUMP_TABLES
4693 gpointer *jte = mono_jumptable_add_entry ();
4694 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4695 jte [0] = ss_trigger_page;
4697 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4699 *(int*)code = (int)ss_trigger_page;
4703 ARM_LDR_IMM (code, dreg, dreg, 0);
4707 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4709 if (cfg->soft_breakpoints) {
4710 /* Load the address of the breakpoint method into ip. */
4711 var = bp_method_var;
4713 g_assert (var->opcode == OP_REGOFFSET);
4714 g_assert (arm_is_imm12 (var->inst_offset));
4715 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4718 * A placeholder for a possible breakpoint inserted by
4719 * mono_arch_set_breakpoint ().
4722 } else if (cfg->compile_aot) {
4723 guint32 offset = code - cfg->native_code;
4726 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4727 /* Add the offset */
4728 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4729 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4730 if (arm_is_imm12 ((int)val)) {
4731 ARM_LDR_IMM (code, dreg, dreg, val);
4733 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4735 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4737 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4738 g_assert (!(val & 0xFF000000));
4740 ARM_LDR_IMM (code, dreg, dreg, 0);
4742 /* What is faster, a branch or a load ? */
4743 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4744 /* The breakpoint instruction */
4745 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4748 * A placeholder for a possible breakpoint inserted by
4749 * mono_arch_set_breakpoint ().
4751 for (i = 0; i < 4; ++i)
4756 * Add an additional nop so skipping the bp doesn't cause the ip to point
4757 * to another IL offset.
4765 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4768 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4772 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4775 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4776 g_assert (imm8 >= 0);
4777 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4781 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4782 g_assert (imm8 >= 0);
4783 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4787 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4788 g_assert (imm8 >= 0);
4789 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4792 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4793 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4795 case OP_IADD_OVF_UN:
4796 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4797 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4800 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4801 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4803 case OP_ISUB_OVF_UN:
4804 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4805 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4807 case OP_ADD_OVF_CARRY:
4808 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4809 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4811 case OP_ADD_OVF_UN_CARRY:
4812 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4813 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4815 case OP_SUB_OVF_CARRY:
4816 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4817 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4819 case OP_SUB_OVF_UN_CARRY:
4820 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4821 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4825 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4828 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4829 g_assert (imm8 >= 0);
4830 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4833 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4837 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4841 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4842 g_assert (imm8 >= 0);
4843 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4847 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4848 g_assert (imm8 >= 0);
4849 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4851 case OP_ARM_RSBS_IMM:
4852 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4853 g_assert (imm8 >= 0);
4854 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4856 case OP_ARM_RSC_IMM:
4857 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4858 g_assert (imm8 >= 0);
4859 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4862 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4866 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4867 g_assert (imm8 >= 0);
4868 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4871 g_assert (v7s_supported);
4872 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4875 g_assert (v7s_supported);
4876 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4879 g_assert (v7s_supported);
4880 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4881 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4884 g_assert (v7s_supported);
4885 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4886 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4890 g_assert_not_reached ();
4892 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4896 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4897 g_assert (imm8 >= 0);
4898 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4901 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4905 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4906 g_assert (imm8 >= 0);
4907 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4910 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4915 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4916 else if (ins->dreg != ins->sreg1)
4917 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4920 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4925 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4926 else if (ins->dreg != ins->sreg1)
4927 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4930 case OP_ISHR_UN_IMM:
4932 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4933 else if (ins->dreg != ins->sreg1)
4934 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4937 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4940 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4943 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4946 if (ins->dreg == ins->sreg2)
4947 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4949 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4952 g_assert_not_reached ();
4955 /* FIXME: handle ovf/ sreg2 != dreg */
4956 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4957 /* FIXME: MUL doesn't set the C/O flags on ARM */
4959 case OP_IMUL_OVF_UN:
4960 /* FIXME: handle ovf/ sreg2 != dreg */
4961 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4962 /* FIXME: MUL doesn't set the C/O flags on ARM */
4965 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4968 /* Load the GOT offset */
4969 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4970 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4972 *(gpointer*)code = NULL;
4974 /* Load the value from the GOT */
4975 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4977 case OP_OBJC_GET_SELECTOR:
4978 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4979 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4981 *(gpointer*)code = NULL;
4983 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4985 case OP_ICONV_TO_I4:
4986 case OP_ICONV_TO_U4:
4988 if (ins->dreg != ins->sreg1)
4989 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4992 int saved = ins->sreg2;
4993 if (ins->sreg2 == ARM_LSW_REG) {
4994 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4997 if (ins->sreg1 != ARM_LSW_REG)
4998 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4999 if (saved != ARM_MSW_REG)
5000 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
5004 if (IS_VFP && ins->dreg != ins->sreg1)
5005 ARM_CPYD (code, ins->dreg, ins->sreg1);
5008 if (IS_VFP && ins->dreg != ins->sreg1)
5009 ARM_CPYS (code, ins->dreg, ins->sreg1);
5011 case OP_MOVE_F_TO_I4:
5013 ARM_FMRS (code, ins->dreg, ins->sreg1);
5015 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5016 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5017 ARM_FMRS (code, ins->dreg, vfp_scratch1);
5018 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5021 case OP_MOVE_I4_TO_F:
5023 ARM_FMSR (code, ins->dreg, ins->sreg1);
5025 ARM_FMSR (code, ins->dreg, ins->sreg1);
5026 ARM_CVTS (code, ins->dreg, ins->dreg);
5029 case OP_FCONV_TO_R4:
5032 ARM_CVTD (code, ins->dreg, ins->sreg1);
5034 ARM_CVTD (code, ins->dreg, ins->sreg1);
5035 ARM_CVTS (code, ins->dreg, ins->dreg);
5040 MonoCallInst *call = (MonoCallInst*)ins;
5043 * The stack looks like the following:
5044 * <caller argument area>
5047 * <callee argument area>
5048 * Need to copy the arguments from the callee argument area to
5049 * the caller argument area, and pop the frame.
5051 if (call->stack_usage) {
5052 int i, prev_sp_offset = 0;
5054 /* Compute size of saved registers restored below */
5056 prev_sp_offset = 2 * 4;
5058 prev_sp_offset = 1 * 4;
5059 for (i = 0; i < 16; ++i) {
5060 if (cfg->used_int_regs & (1 << i))
5061 prev_sp_offset += 4;
5064 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5066 /* Copy arguments on the stack to our argument area */
5067 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5068 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5069 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5074 * Keep in sync with mono_arch_emit_epilog
5076 g_assert (!cfg->method->save_lmf);
5078 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5080 if (cfg->used_int_regs)
5081 ARM_POP (code, cfg->used_int_regs);
5082 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5084 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5087 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5088 if (cfg->compile_aot) {
5089 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5091 *(gpointer*)code = NULL;
5093 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5095 code = mono_arm_patchable_b (code, ARMCOND_AL);
5096 cfg->thunk_area += THUNK_SIZE;
5101 /* ensure ins->sreg1 is not NULL */
5102 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5105 g_assert (cfg->sig_cookie < 128);
5106 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5107 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5117 call = (MonoCallInst*)ins;
5120 code = emit_float_args (cfg, call, code, &max_len, &offset);
5122 if (ins->flags & MONO_INST_HAS_METHOD)
5123 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5125 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5126 code = emit_call_seq (cfg, code);
5127 ins->flags |= MONO_INST_GC_CALLSITE;
5128 ins->backend.pc_offset = code - cfg->native_code;
5129 code = emit_move_return_value (cfg, ins, code);
5136 case OP_VOIDCALL_REG:
5139 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5141 code = emit_call_reg (code, ins->sreg1);
5142 ins->flags |= MONO_INST_GC_CALLSITE;
5143 ins->backend.pc_offset = code - cfg->native_code;
5144 code = emit_move_return_value (cfg, ins, code);
5146 case OP_FCALL_MEMBASE:
5147 case OP_RCALL_MEMBASE:
5148 case OP_LCALL_MEMBASE:
5149 case OP_VCALL_MEMBASE:
5150 case OP_VCALL2_MEMBASE:
5151 case OP_VOIDCALL_MEMBASE:
5152 case OP_CALL_MEMBASE: {
5153 g_assert (ins->sreg1 != ARMREG_LR);
5154 call = (MonoCallInst*)ins;
5157 code = emit_float_args (cfg, call, code, &max_len, &offset);
5158 if (!arm_is_imm12 (ins->inst_offset))
5159 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5160 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5161 if (!arm_is_imm12 (ins->inst_offset))
5162 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5164 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5165 ins->flags |= MONO_INST_GC_CALLSITE;
5166 ins->backend.pc_offset = code - cfg->native_code;
5167 code = emit_move_return_value (cfg, ins, code);
5170 case OP_GENERIC_CLASS_INIT: {
5171 static int byte_offset = -1;
5172 static guint8 bitmask;
5176 if (byte_offset < 0)
5177 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5179 g_assert (arm_is_imm8 (byte_offset));
5180 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5181 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5182 g_assert (imm8 >= 0);
5183 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5184 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5186 ARM_B_COND (code, ARMCOND_NE, 0);
5188 /* Uninitialized case */
5189 g_assert (ins->sreg1 == ARMREG_R0);
5191 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5192 (gpointer)"mono_generic_class_init");
5193 code = emit_call_seq (cfg, code);
5195 /* Initialized case */
5196 arm_patch (jump, code);
5200 /* round the size to 8 bytes */
5201 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
5202 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
5203 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5204 /* memzero the area: dreg holds the size, sp is the pointer */
5205 if (ins->flags & MONO_INST_INIT) {
5206 guint8 *start_loop, *branch_to_cond;
5207 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5208 branch_to_cond = code;
5211 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5212 arm_patch (branch_to_cond, code);
5213 /* decrement by 4 and set flags */
5214 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5215 ARM_B_COND (code, ARMCOND_GE, 0);
5216 arm_patch (code - 4, start_loop);
5218 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5219 if (cfg->param_area)
5220 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5225 MonoInst *var = cfg->dyn_call_var;
5227 g_assert (var->opcode == OP_REGOFFSET);
5228 g_assert (arm_is_imm12 (var->inst_offset));
5230 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5231 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5233 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5235 /* Save args buffer */
5236 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5238 /* Set stack slots using R0 as scratch reg */
5239 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5240 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5241 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5242 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5245 /* Set argument registers */
5246 for (i = 0; i < PARAM_REGS; ++i)
5247 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5250 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5251 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5254 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5255 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5256 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5260 if (ins->sreg1 != ARMREG_R0)
5261 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5262 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5263 (gpointer)"mono_arch_throw_exception");
5264 code = emit_call_seq (cfg, code);
5268 if (ins->sreg1 != ARMREG_R0)
5269 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5270 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5271 (gpointer)"mono_arch_rethrow_exception");
5272 code = emit_call_seq (cfg, code);
5275 case OP_START_HANDLER: {
5276 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5279 /* Reserve a param area, see filter-stack.exe */
5280 if (cfg->param_area) {
5281 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5282 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5284 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5285 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5289 if (arm_is_imm12 (spvar->inst_offset)) {
5290 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5292 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5293 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5297 case OP_ENDFILTER: {
5298 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5301 /* Free the param area */
5302 if (cfg->param_area) {
5303 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5304 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5306 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5307 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5311 if (ins->sreg1 != ARMREG_R0)
5312 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5313 if (arm_is_imm12 (spvar->inst_offset)) {
5314 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5316 g_assert (ARMREG_IP != spvar->inst_basereg);
5317 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5318 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5320 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5323 case OP_ENDFINALLY: {
5324 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5327 /* Free the param area */
5328 if (cfg->param_area) {
5329 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5330 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5332 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5333 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5337 if (arm_is_imm12 (spvar->inst_offset)) {
5338 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5340 g_assert (ARMREG_IP != spvar->inst_basereg);
5341 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5342 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5344 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5347 case OP_CALL_HANDLER:
5348 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5349 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5350 cfg->thunk_area += THUNK_SIZE;
5351 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5354 if (ins->dreg != ARMREG_R0)
5355 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5359 ins->inst_c0 = code - cfg->native_code;
5362 /*if (ins->inst_target_bb->native_offset) {
5364 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5366 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5367 code = mono_arm_patchable_b (code, ARMCOND_AL);
5371 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5375 * In the normal case we have:
5376 * ldr pc, [pc, ins->sreg1 << 2]
5379 * ldr lr, [pc, ins->sreg1 << 2]
5381 * After follows the data.
5382 * FIXME: add aot support.
5384 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5385 #ifdef USE_JUMP_TABLES
5387 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5388 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5389 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5393 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5394 if (offset + max_len > (cfg->code_size - 16)) {
5395 cfg->code_size += max_len;
5396 cfg->code_size *= 2;
5397 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5398 code = cfg->native_code + offset;
5400 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5402 code += 4 * GPOINTER_TO_INT (ins->klass);
5407 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5408 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5412 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5413 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5417 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5418 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5422 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5423 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5427 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5428 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5431 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5432 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5435 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5436 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5439 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5440 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5443 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5444 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5447 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5448 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5450 case OP_COND_EXC_EQ:
5451 case OP_COND_EXC_NE_UN:
5452 case OP_COND_EXC_LT:
5453 case OP_COND_EXC_LT_UN:
5454 case OP_COND_EXC_GT:
5455 case OP_COND_EXC_GT_UN:
5456 case OP_COND_EXC_GE:
5457 case OP_COND_EXC_GE_UN:
5458 case OP_COND_EXC_LE:
5459 case OP_COND_EXC_LE_UN:
5460 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5462 case OP_COND_EXC_IEQ:
5463 case OP_COND_EXC_INE_UN:
5464 case OP_COND_EXC_ILT:
5465 case OP_COND_EXC_ILT_UN:
5466 case OP_COND_EXC_IGT:
5467 case OP_COND_EXC_IGT_UN:
5468 case OP_COND_EXC_IGE:
5469 case OP_COND_EXC_IGE_UN:
5470 case OP_COND_EXC_ILE:
5471 case OP_COND_EXC_ILE_UN:
5472 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5475 case OP_COND_EXC_IC:
5476 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5478 case OP_COND_EXC_OV:
5479 case OP_COND_EXC_IOV:
5480 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5482 case OP_COND_EXC_NC:
5483 case OP_COND_EXC_INC:
5484 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5486 case OP_COND_EXC_NO:
5487 case OP_COND_EXC_INO:
5488 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5500 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5503 /* floating point opcodes */
5505 if (cfg->compile_aot) {
5506 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5508 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5510 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5513 /* FIXME: we can optimize the imm load by dealing with part of
5514 * the displacement in LDFD (aligning to 512).
5516 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5517 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5521 if (cfg->compile_aot) {
5522 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5524 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5527 ARM_CVTS (code, ins->dreg, ins->dreg);
5529 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5530 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5532 ARM_CVTS (code, ins->dreg, ins->dreg);
5535 case OP_STORER8_MEMBASE_REG:
5536 /* This is generated by the local regalloc pass which runs after the lowering pass */
5537 if (!arm_is_fpimm8 (ins->inst_offset)) {
5538 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5539 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5540 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5542 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5545 case OP_LOADR8_MEMBASE:
5546 /* This is generated by the local regalloc pass which runs after the lowering pass */
5547 if (!arm_is_fpimm8 (ins->inst_offset)) {
5548 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5549 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5550 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5552 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5555 case OP_STORER4_MEMBASE_REG:
5556 g_assert (arm_is_fpimm8 (ins->inst_offset));
5558 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5560 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5561 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5562 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5563 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5566 case OP_LOADR4_MEMBASE:
5568 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5570 g_assert (arm_is_fpimm8 (ins->inst_offset));
5571 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5572 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5573 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5574 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5577 case OP_ICONV_TO_R_UN: {
5578 g_assert_not_reached ();
5581 case OP_ICONV_TO_R4:
5583 ARM_FMSR (code, ins->dreg, ins->sreg1);
5584 ARM_FSITOS (code, ins->dreg, ins->dreg);
5586 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5587 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5588 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5589 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5590 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5593 case OP_ICONV_TO_R8:
5594 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5595 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5596 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5597 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5601 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5602 if (sig_ret->type == MONO_TYPE_R4) {
5604 g_assert (!IS_HARD_FLOAT);
5605 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5607 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5610 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5614 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5616 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5620 case OP_FCONV_TO_I1:
5621 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5623 case OP_FCONV_TO_U1:
5624 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5626 case OP_FCONV_TO_I2:
5627 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5629 case OP_FCONV_TO_U2:
5630 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5632 case OP_FCONV_TO_I4:
5634 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5636 case OP_FCONV_TO_U4:
5638 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5640 case OP_FCONV_TO_I8:
5641 case OP_FCONV_TO_U8:
5642 g_assert_not_reached ();
5643 /* Implemented as helper calls */
5645 case OP_LCONV_TO_R_UN:
5646 g_assert_not_reached ();
5647 /* Implemented as helper calls */
5649 case OP_LCONV_TO_OVF_I4_2: {
5650 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5652 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5655 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5656 high_bit_not_set = code;
5657 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5659 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5660 valid_negative = code;
5661 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5662 invalid_negative = code;
5663 ARM_B_COND (code, ARMCOND_AL, 0);
5665 arm_patch (high_bit_not_set, code);
5667 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5668 valid_positive = code;
5669 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5671 arm_patch (invalid_negative, code);
5672 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5674 arm_patch (valid_negative, code);
5675 arm_patch (valid_positive, code);
5677 if (ins->dreg != ins->sreg1)
5678 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5682 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5685 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5688 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5691 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5694 ARM_NEGD (code, ins->dreg, ins->sreg1);
5698 g_assert_not_reached ();
5702 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5708 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5713 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5716 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5717 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5721 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5724 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5725 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5729 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5732 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5733 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5734 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5738 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5741 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5742 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5746 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5749 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5750 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5751 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5755 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5758 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5759 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5763 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5766 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5767 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5771 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5774 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5775 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5778 /* ARM FPA flags table:
5779 * N Less than ARMCOND_MI
5780 * Z Equal ARMCOND_EQ
5781 * C Greater Than or Equal ARMCOND_CS
5782 * V Unordered ARMCOND_VS
5785 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5788 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5791 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5794 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5795 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5801 g_assert_not_reached ();
5805 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5807 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5808 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5809 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5813 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5814 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5819 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5820 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5822 #ifdef USE_JUMP_TABLES
5824 gpointer *jte = mono_jumptable_add_entries (2);
5825 jte [0] = GUINT_TO_POINTER (0xffffffff);
5826 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5827 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5828 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5831 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5832 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5834 *(guint32*)code = 0xffffffff;
5836 *(guint32*)code = 0x7fefffff;
5839 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5841 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5842 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5844 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5845 ARM_CPYD (code, ins->dreg, ins->sreg1);
5847 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5848 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5853 case OP_RCONV_TO_I1:
5854 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5856 case OP_RCONV_TO_U1:
5857 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5859 case OP_RCONV_TO_I2:
5860 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5862 case OP_RCONV_TO_U2:
5863 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5865 case OP_RCONV_TO_I4:
5866 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5868 case OP_RCONV_TO_U4:
5869 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5871 case OP_RCONV_TO_R4:
5873 if (ins->dreg != ins->sreg1)
5874 ARM_CPYS (code, ins->dreg, ins->sreg1);
5876 case OP_RCONV_TO_R8:
5878 ARM_CVTS (code, ins->dreg, ins->sreg1);
5881 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5884 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5887 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5890 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5893 ARM_NEGS (code, ins->dreg, ins->sreg1);
5897 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5900 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5901 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5905 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5908 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5909 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5913 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5916 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5917 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5918 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5922 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5925 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5926 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5930 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5933 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5934 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5935 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5939 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5942 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5943 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5947 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5950 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5951 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5955 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5958 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5959 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5962 case OP_GC_LIVENESS_DEF:
5963 case OP_GC_LIVENESS_USE:
5964 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5965 ins->backend.pc_offset = code - cfg->native_code;
5967 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5968 ins->backend.pc_offset = code - cfg->native_code;
5969 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5973 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5974 g_assert_not_reached ();
5977 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5978 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5979 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5980 g_assert_not_reached ();
5986 last_offset = offset;
5989 cfg->code_len = code - cfg->native_code;
5992 #endif /* DISABLE_JIT */
5995 mono_arch_register_lowlevel_calls (void)
5997 /* The signature doesn't matter */
5998 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5999 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
6001 #ifndef MONO_CROSS_COMPILE
6002 if (mono_arm_have_tls_get ()) {
6003 if (mono_arm_have_fast_tls ()) {
6004 mono_register_jit_icall (mono_fast_get_tls_key, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
6005 mono_register_jit_icall (mono_fast_set_tls_key, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
6007 g_warning ("No fast tls on device. Using fallbacks.");
6008 mono_register_jit_icall (mono_fallback_get_tls_key, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
6009 mono_register_jit_icall (mono_fallback_set_tls_key, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
6015 #define patch_lis_ori(ip,val) do {\
6016 guint16 *__lis_ori = (guint16*)(ip); \
6017 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
6018 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
6022 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6024 unsigned char *ip = ji->ip.i + code;
6026 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6030 case MONO_PATCH_INFO_SWITCH: {
6031 #ifdef USE_JUMP_TABLES
6032 gpointer *jt = mono_jumptable_get_entry (ip);
6034 gpointer *jt = (gpointer*)(ip + 8);
6037 /* jt is the inlined jump table, 2 instructions after ip
6038 * In the normal case we store the absolute addresses,
6039 * otherwise the displacements.
6041 for (i = 0; i < ji->data.table->table_size; i++)
6042 jt [i] = code + (int)ji->data.table->table [i];
6045 case MONO_PATCH_INFO_IP:
6046 g_assert_not_reached ();
6047 patch_lis_ori (ip, ip);
6049 case MONO_PATCH_INFO_METHOD_REL:
6050 g_assert_not_reached ();
6051 *((gpointer *)(ip)) = target;
6053 case MONO_PATCH_INFO_METHODCONST:
6054 case MONO_PATCH_INFO_CLASS:
6055 case MONO_PATCH_INFO_IMAGE:
6056 case MONO_PATCH_INFO_FIELD:
6057 case MONO_PATCH_INFO_VTABLE:
6058 case MONO_PATCH_INFO_IID:
6059 case MONO_PATCH_INFO_SFLDA:
6060 case MONO_PATCH_INFO_LDSTR:
6061 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6062 case MONO_PATCH_INFO_LDTOKEN:
6063 g_assert_not_reached ();
6064 /* from OP_AOTCONST : lis + ori */
6065 patch_lis_ori (ip, target);
6067 case MONO_PATCH_INFO_R4:
6068 case MONO_PATCH_INFO_R8:
6069 g_assert_not_reached ();
6070 *((gconstpointer *)(ip + 2)) = target;
6072 case MONO_PATCH_INFO_EXC_NAME:
6073 g_assert_not_reached ();
6074 *((gconstpointer *)(ip + 1)) = target;
6076 case MONO_PATCH_INFO_NONE:
6077 case MONO_PATCH_INFO_BB_OVF:
6078 case MONO_PATCH_INFO_EXC_OVF:
6079 /* everything is dealt with at epilog output time */
6082 arm_patch_general (cfg, domain, ip, target);
6090 * Stack frame layout:
6092 * ------------------- fp
6093 * MonoLMF structure or saved registers
6094 * -------------------
6096 * -------------------
6098 * -------------------
6099 * optional 8 bytes for tracing
6100 * -------------------
6101 * param area size is cfg->param_area
6102 * ------------------- sp
6105 mono_arch_emit_prolog (MonoCompile *cfg)
6107 MonoMethod *method = cfg->method;
6109 MonoMethodSignature *sig;
6111 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6116 int prev_sp_offset, reg_offset;
6118 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6121 sig = mono_method_signature (method);
6122 cfg->code_size = 256 + sig->param_count * 64;
6123 code = cfg->native_code = g_malloc (cfg->code_size);
6125 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6127 alloc_size = cfg->stack_offset;
6133 * The iphone uses R7 as the frame pointer, and it points at the saved
6138 * We can't use r7 as a frame pointer since it points into the middle of
6139 * the frame, so we keep using our own frame pointer.
6140 * FIXME: Optimize this.
6142 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6143 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6144 prev_sp_offset += 8; /* r7 and lr */
6145 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6146 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6149 if (!method->save_lmf) {
6151 /* No need to push LR again */
6152 if (cfg->used_int_regs)
6153 ARM_PUSH (code, cfg->used_int_regs);
6155 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6156 prev_sp_offset += 4;
6158 for (i = 0; i < 16; ++i) {
6159 if (cfg->used_int_regs & (1 << i))
6160 prev_sp_offset += 4;
6162 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6164 for (i = 0; i < 16; ++i) {
6165 if ((cfg->used_int_regs & (1 << i))) {
6166 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6167 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6172 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6173 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6175 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6176 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6179 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6180 ARM_PUSH (code, 0x5ff0);
6181 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6182 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6184 for (i = 0; i < 16; ++i) {
6185 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6186 /* The original r7 is saved at the start */
6187 if (!(iphone_abi && i == ARMREG_R7))
6188 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6192 g_assert (reg_offset == 4 * 10);
6193 pos += sizeof (MonoLMF) - (4 * 10);
6197 orig_alloc_size = alloc_size;
6198 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6199 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6200 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6201 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6204 /* the stack used in the pushed regs */
6205 if (prev_sp_offset & 4)
6207 cfg->stack_usage = alloc_size;
6209 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6210 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6212 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6213 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6215 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6217 if (cfg->frame_reg != ARMREG_SP) {
6218 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6219 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6221 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6222 prev_sp_offset += alloc_size;
6224 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6225 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6227 /* compute max_offset in order to use short forward jumps
6228 * we could skip do it on arm because the immediate displacement
6229 * for jumps is large enough, it may be useful later for constant pools
6232 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6233 MonoInst *ins = bb->code;
6234 bb->max_offset = max_offset;
6236 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6239 MONO_BB_FOR_EACH_INS (bb, ins)
6240 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6243 /* store runtime generic context */
6244 if (cfg->rgctx_var) {
6245 MonoInst *ins = cfg->rgctx_var;
6247 g_assert (ins->opcode == OP_REGOFFSET);
6249 if (arm_is_imm12 (ins->inst_offset)) {
6250 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6252 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6253 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6257 /* load arguments allocated to register from the stack */
6260 cinfo = get_call_info (NULL, sig);
6262 if (cinfo->ret.storage == RegTypeStructByAddr) {
6263 ArgInfo *ainfo = &cinfo->ret;
6264 inst = cfg->vret_addr;
6265 g_assert (arm_is_imm12 (inst->inst_offset));
6266 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6269 if (sig->call_convention == MONO_CALL_VARARG) {
6270 ArgInfo *cookie = &cinfo->sig_cookie;
6272 /* Save the sig cookie address */
6273 g_assert (cookie->storage == RegTypeBase);
6275 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6276 g_assert (arm_is_imm12 (cfg->sig_cookie));
6277 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6278 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6281 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6282 ArgInfo *ainfo = cinfo->args + i;
6283 inst = cfg->args [pos];
6285 if (cfg->verbose_level > 2)
6286 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6288 if (inst->opcode == OP_REGVAR) {
6289 if (ainfo->storage == RegTypeGeneral)
6290 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6291 else if (ainfo->storage == RegTypeFP) {
6292 g_assert_not_reached ();
6293 } else if (ainfo->storage == RegTypeBase) {
6294 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6295 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6297 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6298 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6301 g_assert_not_reached ();
6303 if (cfg->verbose_level > 2)
6304 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6306 switch (ainfo->storage) {
6308 for (part = 0; part < ainfo->nregs; part ++) {
6309 if (ainfo->esize == 4)
6310 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6312 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6315 case RegTypeGeneral:
6316 case RegTypeIRegPair:
6317 case RegTypeGSharedVtInReg:
6318 switch (ainfo->size) {
6320 if (arm_is_imm12 (inst->inst_offset))
6321 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6323 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6324 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6328 if (arm_is_imm8 (inst->inst_offset)) {
6329 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6331 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6332 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6336 if (arm_is_imm12 (inst->inst_offset)) {
6337 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6339 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6340 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6342 if (arm_is_imm12 (inst->inst_offset + 4)) {
6343 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6345 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6346 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6350 if (arm_is_imm12 (inst->inst_offset)) {
6351 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6353 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6354 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6359 case RegTypeBaseGen:
6360 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6361 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6363 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6364 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6366 if (arm_is_imm12 (inst->inst_offset + 4)) {
6367 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6368 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6370 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6371 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6372 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6373 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6377 case RegTypeGSharedVtOnStack:
6378 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6379 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6381 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6382 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6385 switch (ainfo->size) {
6387 if (arm_is_imm8 (inst->inst_offset)) {
6388 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6390 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6391 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6395 if (arm_is_imm8 (inst->inst_offset)) {
6396 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6398 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6399 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6403 if (arm_is_imm12 (inst->inst_offset)) {
6404 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6406 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6407 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6409 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6410 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6412 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6413 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6415 if (arm_is_imm12 (inst->inst_offset + 4)) {
6416 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6418 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6419 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6423 if (arm_is_imm12 (inst->inst_offset)) {
6424 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6426 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6427 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6433 int imm8, rot_amount;
6435 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6436 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6437 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6439 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6441 if (ainfo->size == 8)
6442 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6444 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6447 case RegTypeStructByVal: {
6448 int doffset = inst->inst_offset;
6452 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6453 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6454 if (arm_is_imm12 (doffset)) {
6455 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6457 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6458 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6460 soffset += sizeof (gpointer);
6461 doffset += sizeof (gpointer);
6463 if (ainfo->vtsize) {
6464 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6465 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6466 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6470 case RegTypeStructByAddr:
6471 g_assert_not_reached ();
6472 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6473 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6475 g_assert_not_reached ();
6482 if (method->save_lmf)
6483 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6486 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6488 if (cfg->arch.seq_point_info_var) {
6489 MonoInst *ins = cfg->arch.seq_point_info_var;
6491 /* Initialize the variable from a GOT slot */
6492 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6493 #ifdef USE_JUMP_TABLES
6495 gpointer *jte = mono_jumptable_add_entry ();
6496 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6497 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6499 /** XXX: is it correct? */
6501 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6503 *(gpointer*)code = NULL;
6506 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6508 g_assert (ins->opcode == OP_REGOFFSET);
6510 if (arm_is_imm12 (ins->inst_offset)) {
6511 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6513 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6514 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6518 /* Initialize ss_trigger_page_var */
6519 if (!cfg->soft_breakpoints) {
6520 MonoInst *info_var = cfg->arch.seq_point_info_var;
6521 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6522 int dreg = ARMREG_LR;
6525 g_assert (info_var->opcode == OP_REGOFFSET);
6526 g_assert (arm_is_imm12 (info_var->inst_offset));
6528 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6529 /* Load the trigger page addr */
6530 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6531 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6535 if (cfg->arch.seq_point_read_var) {
6536 MonoInst *read_ins = cfg->arch.seq_point_read_var;
6537 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6538 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6539 #ifdef USE_JUMP_TABLES
6542 g_assert (read_ins->opcode == OP_REGOFFSET);
6543 g_assert (arm_is_imm12 (read_ins->inst_offset));
6544 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6545 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6546 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6547 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6549 #ifdef USE_JUMP_TABLES
6550 jte = mono_jumptable_add_entries (3);
6551 jte [0] = (gpointer)&ss_trigger_var;
6552 jte [1] = single_step_tramp;
6553 jte [2] = breakpoint_tramp;
6554 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6556 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6558 *(volatile int **)code = &ss_trigger_var;
6560 *(gpointer*)code = single_step_tramp;
6562 *(gpointer*)code = breakpoint_tramp;
6566 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6567 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
6568 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6569 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6570 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
6571 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6574 cfg->code_len = code - cfg->native_code;
6575 g_assert (cfg->code_len < cfg->code_size);
6582 mono_arch_emit_epilog (MonoCompile *cfg)
6584 MonoMethod *method = cfg->method;
6585 int pos, i, rot_amount;
6586 int max_epilog_size = 16 + 20*4;
6590 if (cfg->method->save_lmf)
6591 max_epilog_size += 128;
6593 if (mono_jit_trace_calls != NULL)
6594 max_epilog_size += 50;
6596 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6597 max_epilog_size += 50;
6599 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6600 cfg->code_size *= 2;
6601 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6602 cfg->stat_code_reallocs++;
6606 * Keep in sync with OP_JMP
6608 code = cfg->native_code + cfg->code_len;
6610 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6611 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6615 /* Load returned vtypes into registers if needed */
6616 cinfo = cfg->arch.cinfo;
6617 switch (cinfo->ret.storage) {
6618 case RegTypeStructByVal: {
6619 MonoInst *ins = cfg->ret;
6621 if (arm_is_imm12 (ins->inst_offset)) {
6622 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6624 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6625 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6630 MonoInst *ins = cfg->ret;
6632 for (i = 0; i < cinfo->ret.nregs; ++i) {
6633 if (cinfo->ret.esize == 4)
6634 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6636 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6644 if (method->save_lmf) {
6645 int lmf_offset, reg, sp_adj, regmask;
6646 /* all but r0-r3, sp and pc */
6647 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6650 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6652 /* This points to r4 inside MonoLMF->iregs */
6653 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6655 regmask = 0x9ff0; /* restore lr to pc */
6656 /* Skip caller saved registers not used by the method */
6657 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6658 regmask &= ~(1 << reg);
6663 /* Restored later */
6664 regmask &= ~(1 << ARMREG_PC);
6665 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6666 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6668 ARM_POP (code, regmask);
6670 /* Restore saved r7, restore LR to PC */
6671 /* Skip lr from the lmf */
6672 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6673 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6676 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6677 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6679 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6680 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6684 /* Restore saved gregs */
6685 if (cfg->used_int_regs)
6686 ARM_POP (code, cfg->used_int_regs);
6687 /* Restore saved r7, restore LR to PC */
6688 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6690 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6694 cfg->code_len = code - cfg->native_code;
6696 g_assert (cfg->code_len < cfg->code_size);
6701 mono_arch_emit_exceptions (MonoCompile *cfg)
6703 MonoJumpInfo *patch_info;
6706 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6707 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6708 int max_epilog_size = 50;
6710 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6711 exc_throw_pos [i] = NULL;
6712 exc_throw_found [i] = 0;
6715 /* count the number of exception infos */
6718 * make sure we have enough space for exceptions
6720 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6721 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6722 i = mini_exception_id_by_name (patch_info->data.target);
6723 if (!exc_throw_found [i]) {
6724 max_epilog_size += 32;
6725 exc_throw_found [i] = TRUE;
6730 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6731 cfg->code_size *= 2;
6732 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6733 cfg->stat_code_reallocs++;
6736 code = cfg->native_code + cfg->code_len;
6738 /* add code to raise exceptions */
6739 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6740 switch (patch_info->type) {
6741 case MONO_PATCH_INFO_EXC: {
6742 MonoClass *exc_class;
6743 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6745 i = mini_exception_id_by_name (patch_info->data.target);
6746 if (exc_throw_pos [i]) {
6747 arm_patch (ip, exc_throw_pos [i]);
6748 patch_info->type = MONO_PATCH_INFO_NONE;
6751 exc_throw_pos [i] = code;
6753 arm_patch (ip, code);
6755 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6756 g_assert (exc_class);
6758 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6759 #ifdef USE_JUMP_TABLES
6761 gpointer *jte = mono_jumptable_add_entries (2);
6762 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6763 patch_info->data.name = "mono_arch_throw_corlib_exception";
6764 patch_info->ip.i = code - cfg->native_code;
6765 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6766 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6767 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6768 ARM_BLX_REG (code, ARMREG_IP);
6769 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6772 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6773 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6774 patch_info->data.name = "mono_arch_throw_corlib_exception";
6775 patch_info->ip.i = code - cfg->native_code;
6777 cfg->thunk_area += THUNK_SIZE;
6778 *(guint32*)(gpointer)code = exc_class->type_token;
6789 cfg->code_len = code - cfg->native_code;
6791 g_assert (cfg->code_len < cfg->code_size);
6795 #endif /* #ifndef DISABLE_JIT */
6798 mono_arch_finish_init (void)
6803 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6808 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6815 mono_arch_print_tree (MonoInst *tree, int arity)
6825 mono_arch_get_patch_offset (guint8 *code)
6832 mono_arch_flush_register_windows (void)
6837 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6839 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6843 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6845 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6848 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6849 #define BASE_SIZE (6 * 4)
6850 #define BSEARCH_ENTRY_SIZE (4 * 4)
6851 #define CMP_SIZE (3 * 4)
6852 #define BRANCH_SIZE (1 * 4)
6853 #define CALL_SIZE (2 * 4)
6854 #define WMC_SIZE (8 * 4)
6855 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6857 #ifdef USE_JUMP_TABLES
6859 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6861 g_assert (base [index] == NULL);
6862 base [index] = value;
6865 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6867 if (arm_is_imm12 (jti * 4)) {
6868 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6870 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6871 if ((jti * 4) >> 16)
6872 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6873 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6879 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6881 guint32 delta = DISTANCE (target, code);
6883 g_assert (delta >= 0 && delta <= 0xFFF);
6884 *target = *target | delta;
6890 #ifdef ENABLE_WRONG_METHOD_CHECK
6892 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6894 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6900 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6901 gpointer fail_tramp)
6904 arminstr_t *code, *start;
6905 #ifdef USE_JUMP_TABLES
6908 gboolean large_offsets = FALSE;
6909 guint32 **constant_pool_starts;
6910 arminstr_t *vtable_target = NULL;
6911 int extra_space = 0;
6913 #ifdef ENABLE_WRONG_METHOD_CHECK
6918 #ifdef USE_JUMP_TABLES
6919 for (i = 0; i < count; ++i) {
6920 MonoIMTCheckItem *item = imt_entries [i];
6921 item->chunk_size += 4 * 16;
6922 if (!item->is_equals)
6923 imt_entries [item->check_target_idx]->compare_done = TRUE;
6924 size += item->chunk_size;
6927 constant_pool_starts = g_new0 (guint32*, count);
6929 for (i = 0; i < count; ++i) {
6930 MonoIMTCheckItem *item = imt_entries [i];
6931 if (item->is_equals) {
6932 gboolean fail_case = !item->check_target_idx && fail_tramp;
6934 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6935 item->chunk_size += 32;
6936 large_offsets = TRUE;
6939 if (item->check_target_idx || fail_case) {
6940 if (!item->compare_done || fail_case)
6941 item->chunk_size += CMP_SIZE;
6942 item->chunk_size += BRANCH_SIZE;
6944 #ifdef ENABLE_WRONG_METHOD_CHECK
6945 item->chunk_size += WMC_SIZE;
6949 item->chunk_size += 16;
6950 large_offsets = TRUE;
6952 item->chunk_size += CALL_SIZE;
6954 item->chunk_size += BSEARCH_ENTRY_SIZE;
6955 imt_entries [item->check_target_idx]->compare_done = TRUE;
6957 size += item->chunk_size;
6961 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6965 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6967 code = mono_domain_code_reserve (domain, size);
6971 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6972 for (i = 0; i < count; ++i) {
6973 MonoIMTCheckItem *item = imt_entries [i];
6974 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6978 #ifdef USE_JUMP_TABLES
6979 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6980 #define VTABLE_JTI 0
6981 #define IMT_METHOD_OFFSET 0
6982 #define TARGET_CODE_OFFSET 1
6983 #define JUMP_CODE_OFFSET 2
6984 #define RECORDS_PER_ENTRY 3
6985 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
6986 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
6987 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
6989 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
6990 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
6991 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
6992 set_jumptable_element (jte, VTABLE_JTI, vtable);
6995 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6997 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6998 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6999 vtable_target = code;
7000 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7002 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7004 for (i = 0; i < count; ++i) {
7005 MonoIMTCheckItem *item = imt_entries [i];
7006 #ifdef USE_JUMP_TABLES
7007 guint32 imt_method_jti = 0, target_code_jti = 0;
7009 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7011 gint32 vtable_offset;
7013 item->code_target = (guint8*)code;
7015 if (item->is_equals) {
7016 gboolean fail_case = !item->check_target_idx && fail_tramp;
7018 if (item->check_target_idx || fail_case) {
7019 if (!item->compare_done || fail_case) {
7020 #ifdef USE_JUMP_TABLES
7021 imt_method_jti = IMT_METHOD_JTI (i);
7022 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7025 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7027 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7029 #ifdef USE_JUMP_TABLES
7030 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7031 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7032 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7034 item->jmp_code = (guint8*)code;
7035 ARM_B_COND (code, ARMCOND_NE, 0);
7038 /*Enable the commented code to assert on wrong method*/
7039 #ifdef ENABLE_WRONG_METHOD_CHECK
7040 #ifdef USE_JUMP_TABLES
7041 imt_method_jti = IMT_METHOD_JTI (i);
7042 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7045 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7047 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7049 ARM_B_COND (code, ARMCOND_EQ, 0);
7051 /* Define this if your system is so bad that gdb is failing. */
7052 #ifdef BROKEN_DEV_ENV
7053 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7055 arm_patch (code - 1, mini_dump_bad_imt);
7059 arm_patch (cond, code);
7063 if (item->has_target_code) {
7064 /* Load target address */
7065 #ifdef USE_JUMP_TABLES
7066 target_code_jti = TARGET_CODE_JTI (i);
7067 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7068 /* Restore registers */
7069 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7071 ARM_BX (code, ARMREG_R1);
7072 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7074 target_code_ins = code;
7075 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7076 /* Save it to the fourth slot */
7077 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7078 /* Restore registers and branch */
7079 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7081 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7084 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7085 if (!arm_is_imm12 (vtable_offset)) {
7087 * We need to branch to a computed address but we don't have
7088 * a free register to store it, since IP must contain the
7089 * vtable address. So we push the two values to the stack, and
7090 * load them both using LDM.
7092 /* Compute target address */
7093 #ifdef USE_JUMP_TABLES
7094 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7095 if (vtable_offset >> 16)
7096 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7097 /* IP had vtable base. */
7098 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7099 /* Restore registers and branch */
7100 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7101 ARM_BX (code, ARMREG_IP);
7103 vtable_offset_ins = code;
7104 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7105 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7106 /* Save it to the fourth slot */
7107 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7108 /* Restore registers and branch */
7109 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7111 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7114 #ifdef USE_JUMP_TABLES
7115 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7116 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7117 ARM_BX (code, ARMREG_IP);
7119 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7121 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7122 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7128 #ifdef USE_JUMP_TABLES
7129 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7130 target_code_jti = TARGET_CODE_JTI (i);
7131 /* Load target address */
7132 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7133 /* Restore registers */
7134 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7136 ARM_BX (code, ARMREG_R1);
7137 set_jumptable_element (jte, target_code_jti, fail_tramp);
7139 arm_patch (item->jmp_code, (guchar*)code);
7141 target_code_ins = code;
7142 /* Load target address */
7143 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7144 /* Save it to the fourth slot */
7145 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7146 /* Restore registers and branch */
7147 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7149 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7151 item->jmp_code = NULL;
7154 #ifdef USE_JUMP_TABLES
7156 set_jumptable_element (jte, imt_method_jti, item->key);
7159 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7161 /*must emit after unconditional branch*/
7162 if (vtable_target) {
7163 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7164 item->chunk_size += 4;
7165 vtable_target = NULL;
7168 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7169 constant_pool_starts [i] = code;
7171 code += extra_space;
7176 #ifdef USE_JUMP_TABLES
7177 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7178 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7179 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7180 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7181 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7183 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7184 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7186 item->jmp_code = (guint8*)code;
7187 ARM_B_COND (code, ARMCOND_HS, 0);
7193 for (i = 0; i < count; ++i) {
7194 MonoIMTCheckItem *item = imt_entries [i];
7195 if (item->jmp_code) {
7196 if (item->check_target_idx)
7197 #ifdef USE_JUMP_TABLES
7198 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7200 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7203 if (i > 0 && item->is_equals) {
7205 #ifdef USE_JUMP_TABLES
7206 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7207 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7209 arminstr_t *space_start = constant_pool_starts [i];
7210 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7211 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7219 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7220 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7225 #ifndef USE_JUMP_TABLES
7226 g_free (constant_pool_starts);
7229 mono_arch_flush_icache ((guint8*)start, size);
7230 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7231 mono_stats.imt_thunks_size += code - start;
7233 g_assert (DISTANCE (start, code) <= size);
7238 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7240 return ctx->regs [reg];
7244 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7246 ctx->regs [reg] = val;
7250 * mono_arch_get_trampolines:
7252 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7256 mono_arch_get_trampolines (gboolean aot)
7258 return mono_arm_get_exception_trampolines (aot);
7262 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7269 bp = MONO_CONTEXT_GET_BP (ctx);
7270 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7272 old_value = *lr_loc;
7273 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7276 *lr_loc = new_value;
7281 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7283 * mono_arch_set_breakpoint:
7285 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7286 * The location should contain code emitted by OP_SEQ_POINT.
7289 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7292 guint32 native_offset = ip - (guint8*)ji->code_start;
7293 MonoDebugOptions *opt = mini_get_debug_options ();
7295 if (opt->soft_breakpoints) {
7296 g_assert (!ji->from_aot);
7298 ARM_BLX_REG (code, ARMREG_LR);
7299 mono_arch_flush_icache (code - 4, 4);
7300 } else if (ji->from_aot) {
7301 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7303 g_assert (native_offset % 4 == 0);
7304 g_assert (info->bp_addrs [native_offset / 4] == 0);
7305 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7307 int dreg = ARMREG_LR;
7309 /* Read from another trigger page */
7310 #ifdef USE_JUMP_TABLES
7311 gpointer *jte = mono_jumptable_add_entry ();
7312 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7313 jte [0] = bp_trigger_page;
7315 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7317 *(int*)code = (int)bp_trigger_page;
7320 ARM_LDR_IMM (code, dreg, dreg, 0);
7322 mono_arch_flush_icache (code - 16, 16);
7325 /* This is currently implemented by emitting an SWI instruction, which
7326 * qemu/linux seems to convert to a SIGILL.
7328 *(int*)code = (0xef << 24) | 8;
7330 mono_arch_flush_icache (code - 4, 4);
7336 * mono_arch_clear_breakpoint:
7338 * Clear the breakpoint at IP.
7341 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7343 MonoDebugOptions *opt = mini_get_debug_options ();
7347 if (opt->soft_breakpoints) {
7348 g_assert (!ji->from_aot);
7351 mono_arch_flush_icache (code - 4, 4);
7352 } else if (ji->from_aot) {
7353 guint32 native_offset = ip - (guint8*)ji->code_start;
7354 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7356 g_assert (native_offset % 4 == 0);
7357 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7358 info->bp_addrs [native_offset / 4] = 0;
7360 for (i = 0; i < 4; ++i)
7363 mono_arch_flush_icache (ip, code - ip);
7368 * mono_arch_start_single_stepping:
7370 * Start single stepping.
7373 mono_arch_start_single_stepping (void)
7375 if (ss_trigger_page)
7376 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7382 * mono_arch_stop_single_stepping:
7384 * Stop single stepping.
7387 mono_arch_stop_single_stepping (void)
7389 if (ss_trigger_page)
7390 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7396 #define DBG_SIGNAL SIGBUS
7398 #define DBG_SIGNAL SIGSEGV
7402 * mono_arch_is_single_step_event:
7404 * Return whenever the machine state in SIGCTX corresponds to a single
7408 mono_arch_is_single_step_event (void *info, void *sigctx)
7410 siginfo_t *sinfo = info;
7412 if (!ss_trigger_page)
7415 /* Sometimes the address is off by 4 */
7416 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7423 * mono_arch_is_breakpoint_event:
7425 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7428 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7430 siginfo_t *sinfo = info;
7432 if (!ss_trigger_page)
7435 if (sinfo->si_signo == DBG_SIGNAL) {
7436 /* Sometimes the address is off by 4 */
7437 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7447 * mono_arch_skip_breakpoint:
7449 * See mini-amd64.c for docs.
7452 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7454 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7458 * mono_arch_skip_single_step:
7460 * See mini-amd64.c for docs.
7463 mono_arch_skip_single_step (MonoContext *ctx)
7465 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7468 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7471 * mono_arch_get_seq_point_info:
7473 * See mini-amd64.c for docs.
7476 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7481 // FIXME: Add a free function
7483 mono_domain_lock (domain);
7484 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7486 mono_domain_unlock (domain);
7489 ji = mono_jit_info_table_find (domain, (char*)code);
7492 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7494 info->ss_trigger_page = ss_trigger_page;
7495 info->bp_trigger_page = bp_trigger_page;
7497 mono_domain_lock (domain);
7498 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7500 mono_domain_unlock (domain);
7507 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7509 ext->lmf.previous_lmf = prev_lmf;
7510 /* Mark that this is a MonoLMFExt */
7511 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7512 ext->lmf.sp = (gssize)ext;
7516 * mono_arch_set_target:
7518 * Set the target architecture the JIT backend should generate code for, in the form
7519 * of a GNU target triplet. Only used in AOT mode.
7522 mono_arch_set_target (char *mtriple)
7524 /* The GNU target triple format is not very well documented */
7525 if (strstr (mtriple, "armv7")) {
7526 v5_supported = TRUE;
7527 v6_supported = TRUE;
7528 v7_supported = TRUE;
7530 if (strstr (mtriple, "armv6")) {
7531 v5_supported = TRUE;
7532 v6_supported = TRUE;
7534 if (strstr (mtriple, "armv7s")) {
7535 v7s_supported = TRUE;
7537 if (strstr (mtriple, "thumbv7s")) {
7538 v5_supported = TRUE;
7539 v6_supported = TRUE;
7540 v7_supported = TRUE;
7541 v7s_supported = TRUE;
7542 thumb_supported = TRUE;
7543 thumb2_supported = TRUE;
7545 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7546 v5_supported = TRUE;
7547 v6_supported = TRUE;
7548 thumb_supported = TRUE;
7551 if (strstr (mtriple, "gnueabi"))
7552 eabi_supported = TRUE;
7556 mono_arch_opcode_supported (int opcode)
7559 case OP_ATOMIC_ADD_I4:
7560 case OP_ATOMIC_EXCHANGE_I4:
7561 case OP_ATOMIC_CAS_I4:
7562 case OP_ATOMIC_LOAD_I1:
7563 case OP_ATOMIC_LOAD_I2:
7564 case OP_ATOMIC_LOAD_I4:
7565 case OP_ATOMIC_LOAD_U1:
7566 case OP_ATOMIC_LOAD_U2:
7567 case OP_ATOMIC_LOAD_U4:
7568 case OP_ATOMIC_STORE_I1:
7569 case OP_ATOMIC_STORE_I2:
7570 case OP_ATOMIC_STORE_I4:
7571 case OP_ATOMIC_STORE_U1:
7572 case OP_ATOMIC_STORE_U2:
7573 case OP_ATOMIC_STORE_U4:
7574 return v7_supported;
7575 case OP_ATOMIC_LOAD_R4:
7576 case OP_ATOMIC_LOAD_R8:
7577 case OP_ATOMIC_STORE_R4:
7578 case OP_ATOMIC_STORE_R8:
7579 return v7_supported && IS_VFP;
7585 #if defined(ENABLE_GSHAREDVT)
7587 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7589 #endif /* !MONOTOUCH */