mono/mini/mini-arm.c

   1 /*
   2  * mini-arm.c: ARM backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *
   8  * (C) 2003 Ximian, Inc.
   9  */
  10 #include "mini.h"
  11 #include <string.h>
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/utils/mono-mmap.h>
  16
  17 #include "mini-arm.h"
  18 #include "cpu-arm.h"
  19 #include "trace.h"
  20 #include "ir-emit.h"
  21 #ifdef ARM_FPU_FPA
  22 #include "mono/arch/arm/arm-fpa-codegen.h"
  23 #elif defined(ARM_FPU_VFP)
  24 #include "mono/arch/arm/arm-vfp-codegen.h"
  25 #endif
  26
  27 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
  28 #define HAVE_AEABI_READ_TP 1
  29 #endif
  30
  31 static gint lmf_tls_offset = -1;
  32 static gint lmf_addr_tls_offset = -1;
  33
  34 /* This mutex protects architecture specific caches */
  35 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  36 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  37 static CRITICAL_SECTION mini_arch_mutex;
  38
  39 static int v5_supported = 0;
  40 static int v6_supported = 0;
  41 static int v7_supported = 0;
  42 static int thumb_supported = 0;
  43 /*
  44  * Whenever to use the ARM EABI
  45  */
  46 static int eabi_supported = 0;
  47
  48 /*
  49  * Whenever we are on arm/darwin aka the iphone.
  50  */
  51 static int darwin = 0;
  52 /*
  53  * Whenever to use the iphone ABI extensions:
  54  * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
  55  * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
  56  * This is required for debugging/profiling tools to work, but it has some overhead so it should
  57  * only be turned on in debug builds.
  58  */
  59 static int iphone_abi = 0;
  60 static int i8_align;
  61
  62 /*
  63  * The code generated for sequence points reads from this location, which is
  64  * made read-only when single stepping is enabled.
  65  */
  66 static gpointer ss_trigger_page;
  67
  68 /* Enabled breakpoints read from this trigger page */
  69 static gpointer bp_trigger_page;
  70
  71 /* Structure used by the sequence points in AOTed code */
  72 typedef struct {
  73         gpointer ss_trigger_page;
  74         gpointer bp_trigger_page;
  75         guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
  76 } SeqPointInfo;
  77
  78 /*
  79  * TODO:
  80  * floating point support: on ARM it is a mess, there are at least 3
  81  * different setups, each of which binary incompat with the other.
  82  * 1) FPA: old and ugly, but unfortunately what current distros use
  83  *    the double binary format has the two words swapped. 8 double registers.
  84  *    Implemented usually by kernel emulation.
  85  * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
  86  *    ugly swapped double format (I guess a softfloat-vfp exists, too, though).
  87  * 3) VFP: the new and actually sensible and useful FP support. Implemented
  88  *    in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
  89  *
  90  * The plan is to write the FPA support first. softfloat can be tested in a chroot.
  91  */
  92 int mono_exc_esp_offset = 0;
  93
  94 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
  95 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
  96 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
  97
  98 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
  99 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
 100 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
 101
 102 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
 103 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) |  (ARMREG_LR << 12) | ARMREG_PC)
 104 #define DEBUG_IMT 0
 105
 106 /* A variant of ARM_LDR_IMM which can handle large offsets */
 107 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
 108         if (arm_is_imm12 ((offset))) { \
 109                 ARM_LDR_IMM (code, (dreg), (basereg), (offset));        \
 110         } else {                                                                                                \
 111                 g_assert ((scratch_reg) != (basereg));                                     \
 112                 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset));  \
 113                 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg));               \
 114         }                                                                                                                                       \
 115         } while (0)
 116
 117 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do {      \
 118         if (arm_is_imm12 ((offset))) { \
 119                 ARM_STR_IMM (code, (dreg), (basereg), (offset));        \
 120         } else {                                                                                                \
 121                 g_assert ((scratch_reg) != (basereg));                                     \
 122                 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset));  \
 123                 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg));               \
 124         }                                                                                                                                       \
 125         } while (0)
 126
 127 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
 128
 129 const char*
 130 mono_arch_regname (int reg)
 131 {
 132         static const char * rnames[] = {
 133                 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
 134                 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
 135                 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
 136                 "arm_pc"
 137         };
 138         if (reg >= 0 && reg < 16)
 139                 return rnames [reg];
 140         return "unknown";
 141 }
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         static const char * rnames[] = {
 147                 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
 148                 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
 149                 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
 150                 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
 151                 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
 152                 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
 153                 "arm_f30", "arm_f31"
 154         };
 155         if (reg >= 0 && reg < 32)
 156                 return rnames [reg];
 157         return "unknown";
 158 }
 159
 160 #ifndef DISABLE_JIT
 161
 162 static guint8*
 163 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
 164 {
 165         int imm8, rot_amount;
 166         if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
 167                 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
 168                 return code;
 169         }
 170         g_assert (dreg != sreg);
 171         code = mono_arm_emit_load_imm (code, dreg, imm);
 172         ARM_ADD_REG_REG (code, dreg, dreg, sreg);
 173         return code;
 174 }
 175
 176 static guint8*
 177 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
 178 {
 179         /* we can use r0-r3, since this is called only for incoming args on the stack */
 180         if (size > sizeof (gpointer) * 4) {
 181                 guint8 *start_loop;
 182                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
 183                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
 184                 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
 185                 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
 186                 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
 187                 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
 188                 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
 189                 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
 190                 ARM_B_COND (code, ARMCOND_NE, 0);
 191                 arm_patch (code - 4, start_loop);
 192                 return code;
 193         }
 194         if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
 195                         arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
 196                 while (size >= 4) {
 197                         ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
 198                         ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
 199                         doffset += 4;
 200                         soffset += 4;
 201                         size -= 4;
 202                 }
 203         } else if (size) {
 204                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
 205                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
 206                 doffset = soffset = 0;
 207                 while (size >= 4) {
 208                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
 209                         ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
 210                         doffset += 4;
 211                         soffset += 4;
 212                         size -= 4;
 213                 }
 214         }
 215         g_assert (size == 0);
 216         return code;
 217 }
 218
 219 static guint8*
 220 emit_call_reg (guint8 *code, int reg)
 221 {
 222         if (v5_supported) {
 223                 ARM_BLX_REG (code, reg);
 224         } else {
 225                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
 226                 if (thumb_supported)
 227                         ARM_BX (code, reg);
 228                 else
 229                         ARM_MOV_REG_REG (code, ARMREG_PC, reg);
 230         }
 231         return code;
 232 }
 233
 234 static guint8*
 235 emit_call_seq (MonoCompile *cfg, guint8 *code)
 236 {
 237         if (cfg->method->dynamic) {
 238                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
 239                 ARM_B (code, 0);
 240                 *(gpointer*)code = NULL;
 241                 code += 4;
 242                 code = emit_call_reg (code, ARMREG_IP);
 243         } else {
 244                 ARM_BL (code, 0);
 245         }
 246         return code;
 247 }
 248
 249 static guint8*
 250 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
 251 {
 252         switch (ins->opcode) {
 253         case OP_FCALL:
 254         case OP_FCALL_REG:
 255         case OP_FCALL_MEMBASE:
 256 #ifdef ARM_FPU_FPA
 257                 if (ins->dreg != ARM_FPA_F0)
 258                         ARM_MVFD (code, ins->dreg, ARM_FPA_F0);
 259 #elif defined(ARM_FPU_VFP)
 260                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
 261                         ARM_FMSR (code, ins->dreg, ARMREG_R0);
 262                         ARM_CVTS (code, ins->dreg, ins->dreg);
 263                 } else {
 264                         ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
 265                 }
 266 #endif
 267                 break;
 268         }
 269
 270         return code;
 271 }
 272
 273 #endif /* #ifndef DISABLE_JIT */
 274
 275 /*
 276  * mono_arch_get_argument_info:
 277  * @csig:  a method signature
 278  * @param_count: the number of parameters to consider
 279  * @arg_info: an array to store the result infos
 280  *
 281  * Gathers information on parameters such as size, alignment and
 282  * padding. arg_info should be large enought to hold param_count + 1 entries.
 283  *
 284  * Returns the size of the activation frame.
 285  */
 286 int
 287 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 288 {
 289         int k, frame_size = 0;
 290         guint32 size, align, pad;
 291         int offset = 8;
 292
 293         if (MONO_TYPE_ISSTRUCT (csig->ret)) {
 294                 frame_size += sizeof (gpointer);
 295                 offset += 4;
 296         }
 297
 298         arg_info [0].offset = offset;
 299
 300         if (csig->hasthis) {
 301                 frame_size += sizeof (gpointer);
 302                 offset += 4;
 303         }
 304
 305         arg_info [0].size = frame_size;
 306
 307         for (k = 0; k < param_count; k++) {
 308                 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
 309
 310                 /* ignore alignment for now */
 311                 align = 1;
 312
 313                 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 314                 arg_info [k].pad = pad;
 315                 frame_size += size;
 316                 arg_info [k + 1].pad = 0;
 317                 arg_info [k + 1].size = size;
 318                 offset += pad;
 319                 arg_info [k + 1].offset = offset;
 320                 offset += size;
 321         }
 322
 323         align = MONO_ARCH_FRAME_ALIGNMENT;
 324         frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 325         arg_info [k].pad = pad;
 326
 327         return frame_size;
 328 }
 329
 330 #define MAX_ARCH_DELEGATE_PARAMS 3
 331
 332 static gpointer
 333 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
 334 {
 335         guint8 *code, *start;
 336
 337         if (has_target) {
 338                 start = code = mono_global_codeman_reserve (12);
 339
 340                 /* Replace the this argument with the target */
 341                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
 342                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
 343                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 344
 345                 g_assert ((code - start) <= 12);
 346
 347                 mono_arch_flush_icache (start, 12);
 348         } else {
 349                 int size, i;
 350
 351                 size = 8 + param_count * 4;
 352                 start = code = mono_global_codeman_reserve (size);
 353
 354                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
 355                 /* slide down the arguments */
 356                 for (i = 0; i < param_count; ++i) {
 357                         ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
 358                 }
 359                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 360
 361                 g_assert ((code - start) <= size);
 362
 363                 mono_arch_flush_icache (start, size);
 364         }
 365
 366         if (code_size)
 367                 *code_size = code - start;
 368
 369         return start;
 370 }
 371
 372 /*
 373  * mono_arch_get_delegate_invoke_impls:
 374  *
 375  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
 376  * trampolines.
 377  */
 378 GSList*
 379 mono_arch_get_delegate_invoke_impls (void)
 380 {
 381         GSList *res = NULL;
 382         guint8 *code;
 383         guint32 code_len;
 384         int i;
 385
 386         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
 387         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
 388
 389         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
 390                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
 391                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
 392         }
 393
 394         return res;
 395 }
 396
 397 gpointer
 398 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
 399 {
 400         guint8 *code, *start;
 401
 402         /* FIXME: Support more cases */
 403         if (MONO_TYPE_ISSTRUCT (sig->ret))
 404                 return NULL;
 405
 406         if (has_target) {
 407                 static guint8* cached = NULL;
 408                 mono_mini_arch_lock ();
 409                 if (cached) {
 410                         mono_mini_arch_unlock ();
 411                         return cached;
 412                 }
 413
 414                 if (mono_aot_only)
 415                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
 416                 else
 417                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
 418                 cached = start;
 419                 mono_mini_arch_unlock ();
 420                 return cached;
 421         } else {
 422                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
 423                 int i;
 424
 425                 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
 426                         return NULL;
 427                 for (i = 0; i < sig->param_count; ++i)
 428                         if (!mono_is_regsize_var (sig->params [i]))
 429                                 return NULL;
 430
 431                 mono_mini_arch_lock ();
 432                 code = cache [sig->param_count];
 433                 if (code) {
 434                         mono_mini_arch_unlock ();
 435                         return code;
 436                 }
 437
 438                 if (mono_aot_only) {
 439                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
 440                         start = mono_aot_get_trampoline (name);
 441                         g_free (name);
 442                 } else {
 443                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
 444                 }
 445                 cache [sig->param_count] = start;
 446                 mono_mini_arch_unlock ();
 447                 return start;
 448         }
 449
 450         return NULL;
 451 }
 452
 453 gpointer
 454 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
 455 {
 456         return (gpointer)regs [ARMREG_R0];
 457 }
 458
 459 /*
 460  * Initialize the cpu to execute managed code.
 461  */
 462 void
 463 mono_arch_cpu_init (void)
 464 {
 465 #if defined(__ARM_EABI__)
 466         eabi_supported = TRUE;
 467 #endif
 468 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
 469                 i8_align = 4;
 470 #else
 471                 i8_align = __alignof__ (gint64);
 472 #endif
 473 }
 474
 475 /*
 476  * Initialize architecture specific code.
 477  */
 478 void
 479 mono_arch_init (void)
 480 {
 481         InitializeCriticalSection (&mini_arch_mutex);
 482
 483         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 484         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 485         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 486
 487         mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
 488         mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
 489         mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
 490 }
 491
 492 /*
 493  * Cleanup architecture specific code.
 494  */
 495 void
 496 mono_arch_cleanup (void)
 497 {
 498 }
 499
 500 /*
 501  * This function returns the optimizations supported on this cpu.
 502  */
 503 guint32
 504 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 505 {
 506         guint32 opts = 0;
 507         const char *cpu_arch = getenv ("MONO_CPU_ARCH");
 508         if (cpu_arch != NULL) {
 509                 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
 510                 if (strncmp (cpu_arch, "armv", 4) == 0) {
 511                         v5_supported = cpu_arch [4] >= '5';
 512                         v6_supported = cpu_arch [4] >= '6';
 513                         v7_supported = cpu_arch [4] >= '7';
 514                 }
 515         } else {
 516 #if __APPLE__
 517         thumb_supported = TRUE;
 518         v5_supported = TRUE;
 519         darwin = TRUE;
 520         iphone_abi = TRUE;
 521 #else
 522         char buf [512];
 523         char *line;
 524         FILE *file = fopen ("/proc/cpuinfo", "r");
 525         if (file) {
 526                 while ((line = fgets (buf, 512, file))) {
 527                         if (strncmp (line, "Processor", 9) == 0) {
 528                                 char *ver = strstr (line, "(v");
 529                                 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
 530                                         v5_supported = TRUE;
 531                                 if (ver && (ver [2] == '6' || ver [2] == '7'))
 532                                         v6_supported = TRUE;
 533                                 if (ver && (ver [2] == '7'))
 534                                         v7_supported = TRUE;
 535                                 continue;
 536                         }
 537                         if (strncmp (line, "Features", 8) == 0) {
 538                                 char *th = strstr (line, "thumb");
 539                                 if (th) {
 540                                         thumb_supported = TRUE;
 541                                         if (v5_supported)
 542                                                 break;
 543                                 }
 544                                 continue;
 545                         }
 546                 }
 547                 fclose (file);
 548                 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
 549         }
 550 #endif
 551         }
 552
 553         /* no arm-specific optimizations yet */
 554         *exclude_mask = 0;
 555         return opts;
 556 }
 557
 558 #ifndef DISABLE_JIT
 559
 560 static gboolean
 561 is_regsize_var (MonoType *t) {
 562         if (t->byref)
 563                 return TRUE;
 564         t = mini_type_get_underlying_type (NULL, t);
 565         switch (t->type) {
 566         case MONO_TYPE_I4:
 567         case MONO_TYPE_U4:
 568         case MONO_TYPE_I:
 569         case MONO_TYPE_U:
 570         case MONO_TYPE_PTR:
 571         case MONO_TYPE_FNPTR:
 572                 return TRUE;
 573         case MONO_TYPE_OBJECT:
 574         case MONO_TYPE_STRING:
 575         case MONO_TYPE_CLASS:
 576         case MONO_TYPE_SZARRAY:
 577         case MONO_TYPE_ARRAY:
 578                 return TRUE;
 579         case MONO_TYPE_GENERICINST:
 580                 if (!mono_type_generic_inst_is_valuetype (t))
 581                         return TRUE;
 582                 return FALSE;
 583         case MONO_TYPE_VALUETYPE:
 584                 return FALSE;
 585         }
 586         return FALSE;
 587 }
 588
 589 GList *
 590 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 591 {
 592         GList *vars = NULL;
 593         int i;
 594
 595         for (i = 0; i < cfg->num_varinfo; i++) {
 596                 MonoInst *ins = cfg->varinfo [i];
 597                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 598
 599                 /* unused vars */
 600                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 601                         continue;
 602
 603                 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 604                         continue;
 605
 606                 /* we can only allocate 32 bit values */
 607                 if (is_regsize_var (ins->inst_vtype)) {
 608                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 609                         g_assert (i == vmv->idx);
 610                         vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
 611                 }
 612         }
 613
 614         return vars;
 615 }
 616
 617 #define USE_EXTRA_TEMPS 0
 618
 619 GList *
 620 mono_arch_get_global_int_regs (MonoCompile *cfg)
 621 {
 622         GList *regs = NULL;
 623
 624         mono_arch_compute_omit_fp (cfg);
 625
 626         /*
 627          * FIXME: Interface calls might go through a static rgctx trampoline which
 628          * sets V5, but it doesn't save it, so we need to save it ourselves, and
 629          * avoid using it.
 630          */
 631         if (cfg->flags & MONO_CFG_HAS_CALLS)
 632                 cfg->uses_rgctx_reg = TRUE;
 633
 634         if (cfg->arch.omit_fp)
 635                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
 636         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
 637         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
 638         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
 639         if (darwin)
 640                 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
 641                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
 642         else
 643                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
 644         if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
 645                 /* V5 is reserved for passing the vtable/rgctx/IMT method */
 646                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
 647         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
 648         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
 649
 650         return regs;
 651 }
 652
 653 /*
 654  * mono_arch_regalloc_cost:
 655  *
 656  *  Return the cost, in number of memory references, of the action of
 657  * allocating the variable VMV into a register during global register
 658  * allocation.
 659  */
 660 guint32
 661 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 662 {
 663         /* FIXME: */
 664         return 2;
 665 }
 666
 667 #endif /* #ifndef DISABLE_JIT */
 668
 669 #ifndef __GNUC_PREREQ
 670 #define __GNUC_PREREQ(maj, min) (0)
 671 #endif
 672
 673 void
 674 mono_arch_flush_icache (guint8 *code, gint size)
 675 {
 676 #if __APPLE__
 677         sys_icache_invalidate (code, size);
 678 #elif __GNUC_PREREQ(4, 1)
 679         __clear_cache (code, code + size);
 680 #elif defined(PLATFORM_ANDROID)
 681         const int syscall = 0xf0002;
 682         __asm __volatile (
 683                 "mov     r0, %0\n"
 684                 "mov     r1, %1\n"
 685                 "mov     r7, %2\n"
 686                 "mov     r2, #0x0\n"
 687                 "svc     0x00000000\n"
 688                 :
 689                 :       "r" (code), "r" (code + size), "r" (syscall)
 690                 :       "r0", "r1", "r7", "r2"
 691                 );
 692 #else
 693         __asm __volatile ("mov r0, %0\n"
 694                         "mov r1, %1\n"
 695                         "mov r2, %2\n"
 696                         "swi 0x9f0002       @ sys_cacheflush"
 697                         : /* no outputs */
 698                         : "r" (code), "r" (code + size), "r" (0)
 699                         : "r0", "r1", "r3" );
 700 #endif
 701 }
 702
 703 typedef enum {
 704         RegTypeNone,
 705         RegTypeGeneral,
 706         RegTypeIRegPair,
 707         RegTypeBase,
 708         RegTypeBaseGen,
 709         RegTypeFP,
 710         RegTypeStructByVal,
 711         RegTypeStructByAddr
 712 } ArgStorage;
 713
 714 typedef struct {
 715         gint32  offset;
 716         guint16 vtsize; /* in param area */
 717         guint8  reg;
 718         ArgStorage  storage;
 719         gint32  struct_size;
 720         guint8  size    : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
 721 } ArgInfo;
 722
 723 typedef struct {
 724         int nargs;
 725         guint32 stack_usage;
 726         gboolean vtype_retaddr;
 727         /* The index of the vret arg in the argument list */
 728         int vret_arg_index;
 729         ArgInfo ret;
 730         ArgInfo sig_cookie;
 731         ArgInfo args [1];
 732 } CallInfo;
 733
 734 #define DEBUG(a)
 735
 736 #ifndef __GNUC__
 737 /*#define __alignof__(a) sizeof(a)*/
 738 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
 739 #endif
 740
 741 #define PARAM_REGS 4
 742
 743 static void inline
 744 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
 745 {
 746         if (simple) {
 747                 if (*gr > ARMREG_R3) {
 748                         ainfo->offset = *stack_size;
 749                         ainfo->reg = ARMREG_SP; /* in the caller */
 750                         ainfo->storage = RegTypeBase;
 751                         *stack_size += 4;
 752                 } else {
 753                         ainfo->storage = RegTypeGeneral;
 754                         ainfo->reg = *gr;
 755                 }
 756         } else {
 757                 gboolean split;
 758
 759                 if (eabi_supported)
 760                         split = i8_align == 4;
 761                 else
 762                         split = TRUE;
 763
 764                 if (*gr == ARMREG_R3 && split) {
 765                         /* first word in r3 and the second on the stack */
 766                         ainfo->offset = *stack_size;
 767                         ainfo->reg = ARMREG_SP; /* in the caller */
 768                         ainfo->storage = RegTypeBaseGen;
 769                         *stack_size += 4;
 770                 } else if (*gr >= ARMREG_R3) {
 771                         if (eabi_supported) {
 772                                 /* darwin aligns longs to 4 byte only */
 773                                 if (i8_align == 8) {
 774                                         *stack_size += 7;
 775                                         *stack_size &= ~7;
 776                                 }
 777                         }
 778                         ainfo->offset = *stack_size;
 779                         ainfo->reg = ARMREG_SP; /* in the caller */
 780                         ainfo->storage = RegTypeBase;
 781                         *stack_size += 8;
 782                 } else {
 783                         if (eabi_supported) {
 784                                 if (i8_align == 8 && ((*gr) & 1))
 785                                         (*gr) ++;
 786                         }
 787                         ainfo->storage = RegTypeIRegPair;
 788                         ainfo->reg = *gr;
 789                 }
 790                 (*gr) ++;
 791         }
 792         (*gr) ++;
 793 }
 794
 795 static CallInfo*
 796 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 797 {
 798         guint i, gr, pstart;
 799         int n = sig->hasthis + sig->param_count;
 800         MonoType *simpletype;
 801         guint32 stack_size = 0;
 802         CallInfo *cinfo;
 803         gboolean is_pinvoke = sig->pinvoke;
 804
 805         if (mp)
 806                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 807         else
 808                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 809
 810         cinfo->nargs = n;
 811         gr = ARMREG_R0;
 812
 813         /* FIXME: handle returning a struct */
 814         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 815                 guint32 align;
 816
 817                 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (sig->ret), &align) <= sizeof (gpointer)) {
 818                         cinfo->ret.storage = RegTypeStructByVal;
 819                 } else {
 820                         cinfo->vtype_retaddr = TRUE;
 821                 }
 822         }
 823
 824         pstart = 0;
 825         n = 0;
 826         /*
 827          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 828          * the first argument, allowing 'this' to be always passed in the first arg reg.
 829          * Also do this if the first argument is a reference type, since virtual calls
 830          * are sometimes made using calli without sig->hasthis set, like in the delegate
 831          * invoke wrappers.
 832          */
 833         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
 834                 if (sig->hasthis) {
 835                         add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
 836                 } else {
 837                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
 838                         pstart = 1;
 839                 }
 840                 n ++;
 841                 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
 842                 cinfo->vret_arg_index = 1;
 843         } else {
 844                 /* this */
 845                 if (sig->hasthis) {
 846                         add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
 847                         n ++;
 848                 }
 849
 850                 if (cinfo->vtype_retaddr)
 851                         add_general (&gr, &stack_size, &cinfo->ret, TRUE);
 852         }
 853
 854         DEBUG(printf("params: %d\n", sig->param_count));
 855         for (i = pstart; i < sig->param_count; ++i) {
 856                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 857                         /* Prevent implicit arguments and sig_cookie from
 858                            being passed in registers */
 859                         gr = ARMREG_R3 + 1;
 860                         /* Emit the signature cookie just before the implicit arguments */
 861                         add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
 862                 }
 863                 DEBUG(printf("param %d: ", i));
 864                 if (sig->params [i]->byref) {
 865                         DEBUG(printf("byref\n"));
 866                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 867                         n++;
 868                         continue;
 869                 }
 870                 simpletype = mini_type_get_underlying_type (NULL, sig->params [i]);
 871                 switch (simpletype->type) {
 872                 case MONO_TYPE_BOOLEAN:
 873                 case MONO_TYPE_I1:
 874                 case MONO_TYPE_U1:
 875                         cinfo->args [n].size = 1;
 876                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 877                         n++;
 878                         break;
 879                 case MONO_TYPE_CHAR:
 880                 case MONO_TYPE_I2:
 881                 case MONO_TYPE_U2:
 882                         cinfo->args [n].size = 2;
 883                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 884                         n++;
 885                         break;
 886                 case MONO_TYPE_I4:
 887                 case MONO_TYPE_U4:
 888                         cinfo->args [n].size = 4;
 889                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 890                         n++;
 891                         break;
 892                 case MONO_TYPE_I:
 893                 case MONO_TYPE_U:
 894                 case MONO_TYPE_PTR:
 895                 case MONO_TYPE_FNPTR:
 896                 case MONO_TYPE_CLASS:
 897                 case MONO_TYPE_OBJECT:
 898                 case MONO_TYPE_STRING:
 899                 case MONO_TYPE_SZARRAY:
 900                 case MONO_TYPE_ARRAY:
 901                 case MONO_TYPE_R4:
 902                         cinfo->args [n].size = sizeof (gpointer);
 903                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 904                         n++;
 905                         break;
 906                 case MONO_TYPE_GENERICINST:
 907                         if (!mono_type_generic_inst_is_valuetype (simpletype)) {
 908                                 cinfo->args [n].size = sizeof (gpointer);
 909                                 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 910                                 n++;
 911                                 break;
 912                         }
 913                         /* Fall through */
 914                 case MONO_TYPE_TYPEDBYREF:
 915                 case MONO_TYPE_VALUETYPE: {
 916                         gint size;
 917                         int align_size;
 918                         int nwords;
 919                         guint32 align;
 920
 921                         if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
 922                                 size = sizeof (MonoTypedRef);
 923                                 align = sizeof (gpointer);
 924                         } else {
 925                                 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
 926                                 if (is_pinvoke)
 927                                         size = mono_class_native_size (klass, &align);
 928                                 else
 929                                         size = mono_class_value_size (klass, &align);
 930                         }
 931                         DEBUG(printf ("load %d bytes struct\n",
 932                                       mono_class_native_size (sig->params [i]->data.klass, NULL)));
 933                         align_size = size;
 934                         nwords = 0;
 935                         align_size += (sizeof (gpointer) - 1);
 936                         align_size &= ~(sizeof (gpointer) - 1);
 937                         nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
 938                         cinfo->args [n].storage = RegTypeStructByVal;
 939                         cinfo->args [n].struct_size = size;
 940                         /* FIXME: align stack_size if needed */
 941                         if (eabi_supported) {
 942                                 if (align >= 8 && (gr & 1))
 943                                         gr ++;
 944                         }
 945                         if (gr > ARMREG_R3) {
 946                                 cinfo->args [n].size = 0;
 947                                 cinfo->args [n].vtsize = nwords;
 948                         } else {
 949                                 int rest = ARMREG_R3 - gr + 1;
 950                                 int n_in_regs = rest >= nwords? nwords: rest;
 951
 952                                 cinfo->args [n].size = n_in_regs;
 953                                 cinfo->args [n].vtsize = nwords - n_in_regs;
 954                                 cinfo->args [n].reg = gr;
 955                                 gr += n_in_regs;
 956                                 nwords -= n_in_regs;
 957                         }
 958                         cinfo->args [n].offset = stack_size;
 959                         /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
 960                         stack_size += nwords * sizeof (gpointer);
 961                         n++;
 962                         break;
 963                 }
 964                 case MONO_TYPE_U8:
 965                 case MONO_TYPE_I8:
 966                 case MONO_TYPE_R8:
 967                         cinfo->args [n].size = 8;
 968                         add_general (&gr, &stack_size, cinfo->args + n, FALSE);
 969                         n++;
 970                         break;
 971                 default:
 972                         g_error ("Can't trampoline 0x%x", sig->params [i]->type);
 973                 }
 974         }
 975
 976         /* Handle the case where there are no implicit arguments */
 977         if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 978                 /* Prevent implicit arguments and sig_cookie from
 979                    being passed in registers */
 980                 gr = ARMREG_R3 + 1;
 981                 /* Emit the signature cookie just before the implicit arguments */
 982                 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
 983         }
 984
 985         {
 986                 simpletype = mini_type_get_underlying_type (NULL, sig->ret);
 987                 switch (simpletype->type) {
 988                 case MONO_TYPE_BOOLEAN:
 989                 case MONO_TYPE_I1:
 990                 case MONO_TYPE_U1:
 991                 case MONO_TYPE_I2:
 992                 case MONO_TYPE_U2:
 993                 case MONO_TYPE_CHAR:
 994                 case MONO_TYPE_I4:
 995                 case MONO_TYPE_U4:
 996                 case MONO_TYPE_I:
 997                 case MONO_TYPE_U:
 998                 case MONO_TYPE_PTR:
 999                 case MONO_TYPE_FNPTR:
1000                 case MONO_TYPE_CLASS:
1001                 case MONO_TYPE_OBJECT:
1002                 case MONO_TYPE_SZARRAY:
1003                 case MONO_TYPE_ARRAY:
1004                 case MONO_TYPE_STRING:
1005                         cinfo->ret.storage = RegTypeGeneral;
1006                         cinfo->ret.reg = ARMREG_R0;
1007                         break;
1008                 case MONO_TYPE_U8:
1009                 case MONO_TYPE_I8:
1010                         cinfo->ret.storage = RegTypeIRegPair;
1011                         cinfo->ret.reg = ARMREG_R0;
1012                         break;
1013                 case MONO_TYPE_R4:
1014                 case MONO_TYPE_R8:
1015                         cinfo->ret.storage = RegTypeFP;
1016                         cinfo->ret.reg = ARMREG_R0;
1017                         /* FIXME: cinfo->ret.reg = ???;
1018                         cinfo->ret.storage = RegTypeFP;*/
1019                         break;
1020                 case MONO_TYPE_GENERICINST:
1021                         if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1022                                 cinfo->ret.storage = RegTypeGeneral;
1023                                 cinfo->ret.reg = ARMREG_R0;
1024                                 break;
1025                         }
1026                         /* Fall through */
1027                 case MONO_TYPE_VALUETYPE:
1028                 case MONO_TYPE_TYPEDBYREF:
1029                         if (cinfo->ret.storage != RegTypeStructByVal)
1030                                 cinfo->ret.storage = RegTypeStructByAddr;
1031                         break;
1032                 case MONO_TYPE_VOID:
1033                         break;
1034                 default:
1035                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
1036                 }
1037         }
1038
1039         /* align stack size to 8 */
1040         DEBUG (printf ("      stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1041         stack_size = (stack_size + 7) & ~7;
1042
1043         cinfo->stack_usage = stack_size;
1044         return cinfo;
1045 }
1046
1047 #ifndef DISABLE_JIT
1048
1049 G_GNUC_UNUSED static void
1050 break_count (void)
1051 {
1052 }
1053
1054 G_GNUC_UNUSED static gboolean
1055 debug_count (void)
1056 {
1057         static int count = 0;
1058         count ++;
1059
1060         if (!getenv ("COUNT"))
1061                 return TRUE;
1062
1063         if (count == atoi (getenv ("COUNT"))) {
1064                 break_count ();
1065         }
1066
1067         if (count > atoi (getenv ("COUNT"))) {
1068                 return FALSE;
1069         }
1070
1071         return TRUE;
1072 }
1073
1074 static gboolean
1075 debug_omit_fp (void)
1076 {
1077 #if 0
1078         return debug_count ();
1079 #else
1080         return TRUE;
1081 #endif
1082 }
1083
1084 /**
1085  * mono_arch_compute_omit_fp:
1086  *
1087  *   Determine whenever the frame pointer can be eliminated.
1088  */
1089 static void
1090 mono_arch_compute_omit_fp (MonoCompile *cfg)
1091 {
1092         MonoMethodSignature *sig;
1093         MonoMethodHeader *header;
1094         int i, locals_size;
1095         CallInfo *cinfo;
1096
1097         if (cfg->arch.omit_fp_computed)
1098                 return;
1099
1100         header = cfg->header;
1101
1102         sig = mono_method_signature (cfg->method);
1103
1104         if (!cfg->arch.cinfo)
1105                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1106         cinfo = cfg->arch.cinfo;
1107
1108         /*
1109          * FIXME: Remove some of the restrictions.
1110          */
1111         cfg->arch.omit_fp = TRUE;
1112         cfg->arch.omit_fp_computed = TRUE;
1113
1114         if (cfg->disable_omit_fp)
1115                 cfg->arch.omit_fp = FALSE;
1116         if (!debug_omit_fp ())
1117                 cfg->arch.omit_fp = FALSE;
1118         /*
1119         if (cfg->method->save_lmf)
1120                 cfg->arch.omit_fp = FALSE;
1121         */
1122         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1123                 cfg->arch.omit_fp = FALSE;
1124         if (header->num_clauses)
1125                 cfg->arch.omit_fp = FALSE;
1126         if (cfg->param_area)
1127                 cfg->arch.omit_fp = FALSE;
1128         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1129                 cfg->arch.omit_fp = FALSE;
1130         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1131                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1132                 cfg->arch.omit_fp = FALSE;
1133         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1134                 ArgInfo *ainfo = &cinfo->args [i];
1135
1136                 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1137                         /*
1138                          * The stack offset can only be determined when the frame
1139                          * size is known.
1140                          */
1141                         cfg->arch.omit_fp = FALSE;
1142                 }
1143         }
1144
1145         locals_size = 0;
1146         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1147                 MonoInst *ins = cfg->varinfo [i];
1148                 int ialign;
1149
1150                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1151         }
1152 }
1153
1154 /*
1155  * Set var information according to the calling convention. arm version.
1156  * The locals var stuff should most likely be split in another method.
1157  */
1158 void
1159 mono_arch_allocate_vars (MonoCompile *cfg)
1160 {
1161         MonoMethodSignature *sig;
1162         MonoMethodHeader *header;
1163         MonoInst *ins;
1164         int i, offset, size, align, curinst;
1165         CallInfo *cinfo;
1166         guint32 ualign;
1167
1168         sig = mono_method_signature (cfg->method);
1169
1170         if (!cfg->arch.cinfo)
1171                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1172         cinfo = cfg->arch.cinfo;
1173
1174         mono_arch_compute_omit_fp (cfg);
1175
1176         if (cfg->arch.omit_fp)
1177                 cfg->frame_reg = ARMREG_SP;
1178         else
1179                 cfg->frame_reg = ARMREG_FP;
1180
1181         cfg->flags |= MONO_CFG_HAS_SPILLUP;
1182
1183         /* allow room for the vararg method args: void* and long/double */
1184         if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1185                 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1186
1187         header = cfg->header;
1188
1189         /* See mono_arch_get_global_int_regs () */
1190         if (cfg->flags & MONO_CFG_HAS_CALLS)
1191                 cfg->uses_rgctx_reg = TRUE;
1192
1193         if (cfg->frame_reg != ARMREG_SP)
1194                 cfg->used_int_regs |= 1 << cfg->frame_reg;
1195
1196         if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1197                 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1198                 cfg->used_int_regs |= (1 << ARMREG_V5);
1199
1200         offset = 0;
1201         curinst = 0;
1202         if (!MONO_TYPE_ISSTRUCT (sig->ret)) {
1203                 switch (mini_type_get_underlying_type (NULL, sig->ret)->type) {
1204                 case MONO_TYPE_VOID:
1205                         break;
1206                 default:
1207                         cfg->ret->opcode = OP_REGVAR;
1208                         cfg->ret->inst_c0 = ARMREG_R0;
1209                         break;
1210                 }
1211         }
1212         /* local vars are at a positive offset from the stack pointer */
1213         /*
1214          * also note that if the function uses alloca, we use FP
1215          * to point at the local variables.
1216          */
1217         offset = 0; /* linkage area */
1218         /* align the offset to 16 bytes: not sure this is needed here  */
1219         //offset += 8 - 1;
1220         //offset &= ~(8 - 1);
1221
1222         /* add parameter area size for called functions */
1223         offset += cfg->param_area;
1224         offset += 8 - 1;
1225         offset &= ~(8 - 1);
1226         if (cfg->flags & MONO_CFG_HAS_FPOUT)
1227                 offset += 8;
1228
1229         /* allow room to save the return value */
1230         if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1231                 offset += 8;
1232
1233         /* the MonoLMF structure is stored just below the stack pointer */
1234         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1235                 if (cinfo->ret.storage == RegTypeStructByVal) {
1236                         cfg->ret->opcode = OP_REGOFFSET;
1237                         cfg->ret->inst_basereg = cfg->frame_reg;
1238                         offset += sizeof (gpointer) - 1;
1239                         offset &= ~(sizeof (gpointer) - 1);
1240                         cfg->ret->inst_offset = - offset;
1241                 } else {
1242                         ins = cfg->vret_addr;
1243                         offset += sizeof(gpointer) - 1;
1244                         offset &= ~(sizeof(gpointer) - 1);
1245                         ins->inst_offset = offset;
1246                         ins->opcode = OP_REGOFFSET;
1247                         ins->inst_basereg = cfg->frame_reg;
1248                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1249                                 printf ("vret_addr =");
1250                                 mono_print_ins (cfg->vret_addr);
1251                         }
1252                 }
1253                 offset += sizeof(gpointer);
1254         }
1255
1256         /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1257         if (cfg->arch.seq_point_info_var) {
1258                 MonoInst *ins;
1259
1260                 ins = cfg->arch.seq_point_info_var;
1261
1262                 size = 4;
1263                 align = 4;
1264                 offset += align - 1;
1265                 offset &= ~(align - 1);
1266                 ins->opcode = OP_REGOFFSET;
1267                 ins->inst_basereg = cfg->frame_reg;
1268                 ins->inst_offset = offset;
1269                 offset += size;
1270
1271                 ins = cfg->arch.ss_trigger_page_var;
1272                 size = 4;
1273                 align = 4;
1274                 offset += align - 1;
1275                 offset &= ~(align - 1);
1276                 ins->opcode = OP_REGOFFSET;
1277                 ins->inst_basereg = cfg->frame_reg;
1278                 ins->inst_offset = offset;
1279                 offset += size;
1280         }
1281
1282         curinst = cfg->locals_start;
1283         for (i = curinst; i < cfg->num_varinfo; ++i) {
1284                 ins = cfg->varinfo [i];
1285                 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1286                         continue;
1287
1288                 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1289                 * pinvoke wrappers when they call functions returning structure */
1290                 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (ins->inst_vtype) && ins->inst_vtype->type != MONO_TYPE_TYPEDBYREF) {
1291                         size = mono_class_native_size (mono_class_from_mono_type (ins->inst_vtype), &ualign);
1292                         align = ualign;
1293                 }
1294                 else
1295                         size = mono_type_size (ins->inst_vtype, &align);
1296
1297                 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1298                  * since it loads/stores misaligned words, which don't do the right thing.
1299                  */
1300                 if (align < 4 && size >= 4)
1301                         align = 4;
1302                 offset += align - 1;
1303                 offset &= ~(align - 1);
1304                 ins->opcode = OP_REGOFFSET;
1305                 ins->inst_offset = offset;
1306                 ins->inst_basereg = cfg->frame_reg;
1307                 offset += size;
1308                 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1309         }
1310
1311         curinst = 0;
1312         if (sig->hasthis) {
1313                 ins = cfg->args [curinst];
1314                 if (ins->opcode != OP_REGVAR) {
1315                         ins->opcode = OP_REGOFFSET;
1316                         ins->inst_basereg = cfg->frame_reg;
1317                         offset += sizeof (gpointer) - 1;
1318                         offset &= ~(sizeof (gpointer) - 1);
1319                         ins->inst_offset = offset;
1320                         offset += sizeof (gpointer);
1321                 }
1322                 curinst++;
1323         }
1324
1325         if (sig->call_convention == MONO_CALL_VARARG) {
1326                 size = 4;
1327                 align = 4;
1328
1329                 /* Allocate a local slot to hold the sig cookie address */
1330                 offset += align - 1;
1331                 offset &= ~(align - 1);
1332                 cfg->sig_cookie = offset;
1333                 offset += size;
1334         }
1335
1336         for (i = 0; i < sig->param_count; ++i) {
1337                 ins = cfg->args [curinst];
1338
1339                 if (ins->opcode != OP_REGVAR) {
1340                         ins->opcode = OP_REGOFFSET;
1341                         ins->inst_basereg = cfg->frame_reg;
1342                         size = mini_type_stack_size_full (NULL, sig->params [i], &ualign, sig->pinvoke);
1343                         align = ualign;
1344                         /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1345                          * since it loads/stores misaligned words, which don't do the right thing.
1346                          */
1347                         if (align < 4 && size >= 4)
1348                                 align = 4;
1349                         /* The code in the prolog () stores words when storing vtypes received in a register */
1350                         if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1351                                 align = 4;
1352                         offset += align - 1;
1353                         offset &= ~(align - 1);
1354                         ins->inst_offset = offset;
1355                         offset += size;
1356                 }
1357                 curinst++;
1358         }
1359
1360         /* align the offset to 8 bytes */
1361         offset += 8 - 1;
1362         offset &= ~(8 - 1);
1363
1364         /* change sign? */
1365         cfg->stack_offset = offset;
1366 }
1367
1368 void
1369 mono_arch_create_vars (MonoCompile *cfg)
1370 {
1371         MonoMethodSignature *sig;
1372         CallInfo *cinfo;
1373
1374         sig = mono_method_signature (cfg->method);
1375
1376         if (!cfg->arch.cinfo)
1377                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1378         cinfo = cfg->arch.cinfo;
1379
1380         if (cinfo->ret.storage == RegTypeStructByVal)
1381                 cfg->ret_var_is_local = TRUE;
1382
1383         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
1384                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1385                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1386                         printf ("vret_addr = ");
1387                         mono_print_ins (cfg->vret_addr);
1388                 }
1389         }
1390
1391         if (cfg->gen_seq_points && cfg->compile_aot) {
1392             MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1393                 ins->flags |= MONO_INST_VOLATILE;
1394                 cfg->arch.seq_point_info_var = ins;
1395
1396                 /* Allocate a separate variable for this to save 1 load per seq point */
1397             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1398                 ins->flags |= MONO_INST_VOLATILE;
1399                 cfg->arch.ss_trigger_page_var = ins;
1400         }
1401 }
1402
1403 static void
1404 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1405 {
1406         MonoMethodSignature *tmp_sig;
1407         MonoInst *sig_arg;
1408
1409         if (call->tail_call)
1410                 NOT_IMPLEMENTED;
1411
1412         /* FIXME: Add support for signature tokens to AOT */
1413         cfg->disable_aot = TRUE;
1414
1415         g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1416
1417         /*
1418          * mono_ArgIterator_Setup assumes the signature cookie is
1419          * passed first and all the arguments which were before it are
1420          * passed on the stack after the signature. So compensate by
1421          * passing a different signature.
1422          */
1423         tmp_sig = mono_metadata_signature_dup (call->signature);
1424         tmp_sig->param_count -= call->signature->sentinelpos;
1425         tmp_sig->sentinelpos = 0;
1426         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1427
1428         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1429         sig_arg->dreg = mono_alloc_ireg (cfg);
1430         sig_arg->inst_p0 = tmp_sig;
1431         MONO_ADD_INS (cfg->cbb, sig_arg);
1432
1433         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_arg->dreg);
1434 }
1435
1436 #ifdef ENABLE_LLVM
1437 LLVMCallInfo*
1438 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1439 {
1440         int i, n;
1441         CallInfo *cinfo;
1442         ArgInfo *ainfo;
1443         LLVMCallInfo *linfo;
1444
1445         n = sig->param_count + sig->hasthis;
1446
1447         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1448
1449         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1450
1451         /*
1452          * LLVM always uses the native ABI while we use our own ABI, the
1453          * only difference is the handling of vtypes:
1454          * - we only pass/receive them in registers in some cases, and only
1455          *   in 1 or 2 integer registers.
1456          */
1457         if (cinfo->vtype_retaddr) {
1458                 /* Vtype returned using a hidden argument */
1459                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1460                 linfo->vret_arg_index = cinfo->vret_arg_index;
1461         } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1462                 cfg->exception_message = g_strdup ("unknown ret conv");
1463                 cfg->disable_llvm = TRUE;
1464                 return linfo;
1465         }
1466
1467         for (i = 0; i < n; ++i) {
1468                 ainfo = cinfo->args + i;
1469
1470                 linfo->args [i].storage = LLVMArgNone;
1471
1472                 switch (ainfo->storage) {
1473                 case RegTypeGeneral:
1474                 case RegTypeIRegPair:
1475                 case RegTypeBase:
1476                         linfo->args [i].storage = LLVMArgInIReg;
1477                         break;
1478                 case RegTypeStructByVal:
1479                         // FIXME: Passing entirely on the stack or split reg/stack
1480                         if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1481                                 linfo->args [i].storage = LLVMArgVtypeInReg;
1482                                 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1483                                 if (ainfo->size == 2)
1484                                         linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1485                                 else
1486                                         linfo->args [i].pair_storage [1] = LLVMArgNone;
1487                         } else {
1488                                 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1489                                 cfg->disable_llvm = TRUE;
1490                         }
1491                         break;
1492                 default:
1493                         cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1494                         cfg->disable_llvm = TRUE;
1495                         break;
1496                 }
1497         }
1498
1499         return linfo;
1500 }
1501 #endif
1502
1503 void
1504 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1505 {
1506         MonoInst *in, *ins;
1507         MonoMethodSignature *sig;
1508         int i, n;
1509         CallInfo *cinfo;
1510
1511         sig = call->signature;
1512         n = sig->param_count + sig->hasthis;
1513
1514         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1515
1516         for (i = 0; i < n; ++i) {
1517                 ArgInfo *ainfo = cinfo->args + i;
1518                 MonoType *t;
1519
1520                 if (i >= sig->hasthis)
1521                         t = sig->params [i - sig->hasthis];
1522                 else
1523                         t = &mono_defaults.int_class->byval_arg;
1524                 t = mini_type_get_underlying_type (NULL, t);
1525
1526                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1527                         /* Emit the signature cookie just before the implicit arguments */
1528                         emit_sig_cookie (cfg, call, cinfo);
1529                 }
1530
1531                 in = call->args [i];
1532
1533                 switch (ainfo->storage) {
1534                 case RegTypeGeneral:
1535                 case RegTypeIRegPair:
1536                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1537                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1538                                 ins->dreg = mono_alloc_ireg (cfg);
1539                                 ins->sreg1 = in->dreg + 1;
1540                                 MONO_ADD_INS (cfg->cbb, ins);
1541                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1542
1543                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1544                                 ins->dreg = mono_alloc_ireg (cfg);
1545                                 ins->sreg1 = in->dreg + 2;
1546                                 MONO_ADD_INS (cfg->cbb, ins);
1547                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1548                         } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1549 #ifndef MONO_ARCH_SOFT_FLOAT
1550                                 int creg;
1551 #endif
1552
1553                                 if (ainfo->size == 4) {
1554 #ifdef MONO_ARCH_SOFT_FLOAT
1555                                         /* mono_emit_call_args () have already done the r8->r4 conversion */
1556                                         /* The converted value is in an int vreg */
1557                                         MONO_INST_NEW (cfg, ins, OP_MOVE);
1558                                         ins->dreg = mono_alloc_ireg (cfg);
1559                                         ins->sreg1 = in->dreg;
1560                                         MONO_ADD_INS (cfg->cbb, ins);
1561                                         mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1562 #else
1563                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1564                                         creg = mono_alloc_ireg (cfg);
1565                                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1566                                         mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1567 #endif
1568                                 } else {
1569 #ifdef MONO_ARCH_SOFT_FLOAT
1570                                         MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1571                                         ins->dreg = mono_alloc_ireg (cfg);
1572                                         ins->sreg1 = in->dreg;
1573                                         MONO_ADD_INS (cfg->cbb, ins);
1574                                         mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1575
1576                                         MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1577                                         ins->dreg = mono_alloc_ireg (cfg);
1578                                         ins->sreg1 = in->dreg;
1579                                         MONO_ADD_INS (cfg->cbb, ins);
1580                                         mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1581 #else
1582                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1583                                         creg = mono_alloc_ireg (cfg);
1584                                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1585                                         mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1586                                         creg = mono_alloc_ireg (cfg);
1587                                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1588                                         mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1589 #endif
1590                                 }
1591                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
1592                         } else {
1593                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1594                                 ins->dreg = mono_alloc_ireg (cfg);
1595                                 ins->sreg1 = in->dreg;
1596                                 MONO_ADD_INS (cfg->cbb, ins);
1597
1598                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1599                         }
1600                         break;
1601                 case RegTypeStructByAddr:
1602                         NOT_IMPLEMENTED;
1603 #if 0
1604                         /* FIXME: where si the data allocated? */
1605                         arg->backend.reg3 = ainfo->reg;
1606                         call->used_iregs |= 1 << ainfo->reg;
1607                         g_assert_not_reached ();
1608 #endif
1609                         break;
1610                 case RegTypeStructByVal:
1611                         MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1612                         ins->opcode = OP_OUTARG_VT;
1613                         ins->sreg1 = in->dreg;
1614                         ins->klass = in->klass;
1615                         ins->inst_p0 = call;
1616                         ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1617                         memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1618                         mono_call_inst_add_outarg_vt (cfg, call, ins);
1619                         MONO_ADD_INS (cfg->cbb, ins);
1620                         break;
1621                 case RegTypeBase:
1622                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1623                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1624                         } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1625                                 if (t->type == MONO_TYPE_R8) {
1626                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1627                                 } else {
1628 #ifdef MONO_ARCH_SOFT_FLOAT
1629                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1630 #else
1631                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1632 #endif
1633                                 }
1634                         } else {
1635                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1636                         }
1637                         break;
1638                 case RegTypeBaseGen:
1639                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1640                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1641                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1642                                 ins->dreg = mono_alloc_ireg (cfg);
1643                                 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1644                                 MONO_ADD_INS (cfg->cbb, ins);
1645                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1646                         } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1647                                 int creg;
1648
1649                                 /* This should work for soft-float as well */
1650
1651                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1652                                 creg = mono_alloc_ireg (cfg);
1653                                 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1654                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1655                                 creg = mono_alloc_ireg (cfg);
1656                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1657                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1658                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
1659                         } else {
1660                                 g_assert_not_reached ();
1661                         }
1662                         break;
1663                 case RegTypeFP: {
1664                         /* FIXME: */
1665                         NOT_IMPLEMENTED;
1666 #if 0
1667                         arg->backend.reg3 = ainfo->reg;
1668                         /* FP args are passed in int regs */
1669                         call->used_iregs |= 1 << ainfo->reg;
1670                         if (ainfo->size == 8) {
1671                                 arg->opcode = OP_OUTARG_R8;
1672                                 call->used_iregs |= 1 << (ainfo->reg + 1);
1673                         } else {
1674                                 arg->opcode = OP_OUTARG_R4;
1675                         }
1676 #endif
1677                         cfg->flags |= MONO_CFG_HAS_FPOUT;
1678                         break;
1679                 }
1680                 default:
1681                         g_assert_not_reached ();
1682                 }
1683         }
1684
1685         /* Handle the case where there are no implicit arguments */
1686         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1687                 emit_sig_cookie (cfg, call, cinfo);
1688
1689         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1690                 MonoInst *vtarg;
1691
1692                 if (cinfo->ret.storage == RegTypeStructByVal) {
1693                         /* The JIT will transform this into a normal call */
1694                         call->vret_in_reg = TRUE;
1695                 } else {
1696                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1697                         vtarg->sreg1 = call->vret_var->dreg;
1698                         vtarg->dreg = mono_alloc_preg (cfg);
1699                         MONO_ADD_INS (cfg->cbb, vtarg);
1700
1701                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1702                 }
1703         }
1704
1705         call->stack_usage = cinfo->stack_usage;
1706
1707         g_free (cinfo);
1708 }
1709
1710 void
1711 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1712 {
1713         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1714         ArgInfo *ainfo = ins->inst_p1;
1715         int ovf_size = ainfo->vtsize;
1716         int doffset = ainfo->offset;
1717         int struct_size = ainfo->struct_size;
1718         int i, soffset, dreg, tmpreg;
1719
1720         soffset = 0;
1721         for (i = 0; i < ainfo->size; ++i) {
1722                 dreg = mono_alloc_ireg (cfg);
1723                 switch (struct_size) {
1724                 case 1:
1725                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1726                         break;
1727                 case 2:
1728                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
1729                         break;
1730                 case 3:
1731                         tmpreg = mono_alloc_ireg (cfg);
1732                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1733                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
1734                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
1735                         MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1736                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
1737                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
1738                         MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1739                         break;
1740                 default:
1741                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1742                         break;
1743                 }
1744                 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
1745                 soffset += sizeof (gpointer);
1746                 struct_size -= sizeof (gpointer);
1747         }
1748         //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
1749         if (ovf_size != 0)
1750                 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
1751 }
1752
1753 void
1754 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1755 {
1756         MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1757
1758         if (!ret->byref) {
1759                 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1760                         MonoInst *ins;
1761
1762                         if (COMPILE_LLVM (cfg)) {
1763                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1764                         } else {
1765                                 MONO_INST_NEW (cfg, ins, OP_SETLRET);
1766                                 ins->sreg1 = val->dreg + 1;
1767                                 ins->sreg2 = val->dreg + 2;
1768                                 MONO_ADD_INS (cfg->cbb, ins);
1769                         }
1770                         return;
1771                 }
1772 #ifdef MONO_ARCH_SOFT_FLOAT
1773                 if (ret->type == MONO_TYPE_R8) {
1774                         MonoInst *ins;
1775
1776                         MONO_INST_NEW (cfg, ins, OP_SETFRET);
1777                         ins->dreg = cfg->ret->dreg;
1778                         ins->sreg1 = val->dreg;
1779                         MONO_ADD_INS (cfg->cbb, ins);
1780                         return;
1781                 }
1782                 if (ret->type == MONO_TYPE_R4) {
1783                         /* Already converted to an int in method_to_ir () */
1784                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1785                         return;
1786                 }
1787 #elif defined(ARM_FPU_VFP)
1788                 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
1789                         MonoInst *ins;
1790
1791                         MONO_INST_NEW (cfg, ins, OP_SETFRET);
1792                         ins->dreg = cfg->ret->dreg;
1793                         ins->sreg1 = val->dreg;
1794                         MONO_ADD_INS (cfg->cbb, ins);
1795                         return;
1796                 }
1797 #else
1798                 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
1799                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1800                         return;
1801                 }
1802 #endif
1803         }
1804
1805         /* FIXME: */
1806         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1807 }
1808
1809 #endif /* #ifndef DISABLE_JIT */
1810
1811 gboolean
1812 mono_arch_is_inst_imm (gint64 imm)
1813 {
1814         return TRUE;
1815 }
1816
1817 #define DYN_CALL_STACK_ARGS 6
1818
1819 typedef struct {
1820         MonoMethodSignature *sig;
1821         CallInfo *cinfo;
1822 } ArchDynCallInfo;
1823
1824 typedef struct {
1825         mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
1826         mgreg_t res, res2;
1827         guint8 *ret;
1828 } DynCallArgs;
1829
1830 static gboolean
1831 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
1832 {
1833         int i;
1834
1835         if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
1836                 return FALSE;
1837
1838         switch (cinfo->ret.storage) {
1839         case RegTypeNone:
1840         case RegTypeGeneral:
1841         case RegTypeIRegPair:
1842         case RegTypeStructByAddr:
1843                 break;
1844         case RegTypeFP:
1845 #ifdef ARM_FPU_FPA
1846                 return FALSE;
1847 #elif defined(ARM_FPU_VFP)
1848                 break;
1849 #else
1850                 return FALSE;
1851 #endif
1852         default:
1853                 return FALSE;
1854         }
1855
1856         for (i = 0; i < cinfo->nargs; ++i) {
1857                 switch (cinfo->args [i].storage) {
1858                 case RegTypeGeneral:
1859                         break;
1860                 case RegTypeIRegPair:
1861                         break;
1862                 case RegTypeBase:
1863                         if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
1864                                 return FALSE;
1865                         break;
1866                 case RegTypeStructByVal:
1867                         if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
1868                                 return FALSE;
1869                         break;
1870                 default:
1871                         return FALSE;
1872                 }
1873         }
1874
1875         // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
1876         for (i = 0; i < sig->param_count; ++i) {
1877                 MonoType *t = sig->params [i];
1878
1879                 if (t->byref)
1880                         continue;
1881
1882                 switch (t->type) {
1883                 case MONO_TYPE_R4:
1884                 case MONO_TYPE_R8:
1885 #ifdef MONO_ARCH_SOFT_FLOAT
1886                         return FALSE;
1887 #else
1888                         break;
1889 #endif
1890                         /*
1891                 case MONO_TYPE_I8:
1892                 case MONO_TYPE_U8:
1893                         return FALSE;
1894                         */
1895                 default:
1896                         break;
1897                 }
1898         }
1899
1900         return TRUE;
1901 }
1902
1903 MonoDynCallInfo*
1904 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
1905 {
1906         ArchDynCallInfo *info;
1907         CallInfo *cinfo;
1908
1909         cinfo = get_call_info (NULL, NULL, sig);
1910
1911         if (!dyn_call_supported (cinfo, sig)) {
1912                 g_free (cinfo);
1913                 return NULL;
1914         }
1915
1916         info = g_new0 (ArchDynCallInfo, 1);
1917         // FIXME: Preprocess the info to speed up start_dyn_call ()
1918         info->sig = sig;
1919         info->cinfo = cinfo;
1920
1921         return (MonoDynCallInfo*)info;
1922 }
1923
1924 void
1925 mono_arch_dyn_call_free (MonoDynCallInfo *info)
1926 {
1927         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1928
1929         g_free (ainfo->cinfo);
1930         g_free (ainfo);
1931 }
1932
1933 void
1934 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
1935 {
1936         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
1937         DynCallArgs *p = (DynCallArgs*)buf;
1938         int arg_index, greg, i, j, pindex;
1939         MonoMethodSignature *sig = dinfo->sig;
1940
1941         g_assert (buf_len >= sizeof (DynCallArgs));
1942
1943         p->res = 0;
1944         p->ret = ret;
1945
1946         arg_index = 0;
1947         greg = 0;
1948         pindex = 0;
1949
1950         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
1951                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
1952                 if (!sig->hasthis)
1953                         pindex = 1;
1954         }
1955
1956         if (dinfo->cinfo->vtype_retaddr)
1957                 p->regs [greg ++] = (mgreg_t)ret;
1958
1959         for (i = pindex; i < sig->param_count; i++) {
1960                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
1961                 gpointer *arg = args [arg_index ++];
1962                 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
1963                 int slot = -1;
1964
1965                 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
1966                         slot = ainfo->reg;
1967                 else if (ainfo->storage == RegTypeBase)
1968                         slot = PARAM_REGS + (ainfo->offset / 4);
1969                 else
1970                         g_assert_not_reached ();
1971
1972                 if (t->byref) {
1973                         p->regs [slot] = (mgreg_t)*arg;
1974                         continue;
1975                 }
1976
1977                 switch (t->type) {
1978                 case MONO_TYPE_STRING:
1979                 case MONO_TYPE_CLASS:
1980                 case MONO_TYPE_ARRAY:
1981                 case MONO_TYPE_SZARRAY:
1982                 case MONO_TYPE_OBJECT:
1983                 case MONO_TYPE_PTR:
1984                 case MONO_TYPE_I:
1985                 case MONO_TYPE_U:
1986                         p->regs [slot] = (mgreg_t)*arg;
1987                         break;
1988                 case MONO_TYPE_BOOLEAN:
1989                 case MONO_TYPE_U1:
1990                         p->regs [slot] = *(guint8*)arg;
1991                         break;
1992                 case MONO_TYPE_I1:
1993                         p->regs [slot] = *(gint8*)arg;
1994                         break;
1995                 case MONO_TYPE_I2:
1996                         p->regs [slot] = *(gint16*)arg;
1997                         break;
1998                 case MONO_TYPE_U2:
1999                 case MONO_TYPE_CHAR:
2000                         p->regs [slot] = *(guint16*)arg;
2001                         break;
2002                 case MONO_TYPE_I4:
2003                         p->regs [slot] = *(gint32*)arg;
2004                         break;
2005                 case MONO_TYPE_U4:
2006                         p->regs [slot] = *(guint32*)arg;
2007                         break;
2008                 case MONO_TYPE_I8:
2009                 case MONO_TYPE_U8:
2010                         p->regs [slot ++] = (mgreg_t)arg [0];
2011                         p->regs [slot] = (mgreg_t)arg [1];
2012                         break;
2013                 case MONO_TYPE_R4:
2014                         p->regs [slot] = *(mgreg_t*)arg;
2015                         break;
2016                 case MONO_TYPE_R8:
2017                         p->regs [slot ++] = (mgreg_t)arg [0];
2018                         p->regs [slot] = (mgreg_t)arg [1];
2019                         break;
2020                 case MONO_TYPE_GENERICINST:
2021                         if (MONO_TYPE_IS_REFERENCE (t)) {
2022                                 p->regs [slot] = (mgreg_t)*arg;
2023                                 break;
2024                         } else {
2025                                 /* Fall though */
2026                         }
2027                 case MONO_TYPE_VALUETYPE:
2028                         g_assert (ainfo->storage == RegTypeStructByVal);
2029
2030                         if (ainfo->size == 0)
2031                                 slot = PARAM_REGS + (ainfo->offset / 4);
2032                         else
2033                                 slot = ainfo->reg;
2034
2035                         for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2036                                 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2037                         break;
2038                 default:
2039                         g_assert_not_reached ();
2040                 }
2041         }
2042 }
2043
2044 void
2045 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2046 {
2047         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2048         MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2049         guint8 *ret = ((DynCallArgs*)buf)->ret;
2050         mgreg_t res = ((DynCallArgs*)buf)->res;
2051         mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2052
2053         switch (mono_type_get_underlying_type (sig->ret)->type) {
2054         case MONO_TYPE_VOID:
2055                 *(gpointer*)ret = NULL;
2056                 break;
2057         case MONO_TYPE_STRING:
2058         case MONO_TYPE_CLASS:
2059         case MONO_TYPE_ARRAY:
2060         case MONO_TYPE_SZARRAY:
2061         case MONO_TYPE_OBJECT:
2062         case MONO_TYPE_I:
2063         case MONO_TYPE_U:
2064         case MONO_TYPE_PTR:
2065                 *(gpointer*)ret = (gpointer)res;
2066                 break;
2067         case MONO_TYPE_I1:
2068                 *(gint8*)ret = res;
2069                 break;
2070         case MONO_TYPE_U1:
2071         case MONO_TYPE_BOOLEAN:
2072                 *(guint8*)ret = res;
2073                 break;
2074         case MONO_TYPE_I2:
2075                 *(gint16*)ret = res;
2076                 break;
2077         case MONO_TYPE_U2:
2078         case MONO_TYPE_CHAR:
2079                 *(guint16*)ret = res;
2080                 break;
2081         case MONO_TYPE_I4:
2082                 *(gint32*)ret = res;
2083                 break;
2084         case MONO_TYPE_U4:
2085                 *(guint32*)ret = res;
2086                 break;
2087         case MONO_TYPE_I8:
2088         case MONO_TYPE_U8:
2089                 /* This handles endianness as well */
2090                 ((gint32*)ret) [0] = res;
2091                 ((gint32*)ret) [1] = res2;
2092                 break;
2093         case MONO_TYPE_GENERICINST:
2094                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2095                         *(gpointer*)ret = (gpointer)res;
2096                         break;
2097                 } else {
2098                         /* Fall though */
2099                 }
2100         case MONO_TYPE_VALUETYPE:
2101                 g_assert (ainfo->cinfo->vtype_retaddr);
2102                 /* Nothing to do */
2103                 break;
2104 #if defined(ARM_FPU_VFP)
2105         case MONO_TYPE_R4:
2106                 *(float*)ret = *(float*)&res;
2107                 break;
2108         case MONO_TYPE_R8: {
2109                 mgreg_t regs [2];
2110
2111                 regs [0] = res;
2112                 regs [1] = res2;
2113
2114                 *(double*)ret = *(double*)&regs;
2115                 break;
2116         }
2117 #endif
2118         default:
2119                 g_assert_not_reached ();
2120         }
2121 }
2122
2123 #ifndef DISABLE_JIT
2124
2125 /*
2126  * Allow tracing to work with this interface (with an optional argument)
2127  */
2128
2129 void*
2130 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2131 {
2132         guchar *code = p;
2133
2134         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2135         ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2136         code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2137         code = emit_call_reg (code, ARMREG_R2);
2138         return code;
2139 }
2140
2141 enum {
2142         SAVE_NONE,
2143         SAVE_STRUCT,
2144         SAVE_ONE,
2145         SAVE_TWO,
2146         SAVE_FP
2147 };
2148
2149 void*
2150 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2151 {
2152         guchar *code = p;
2153         int save_mode = SAVE_NONE;
2154         int offset;
2155         MonoMethod *method = cfg->method;
2156         int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2157         int save_offset = cfg->param_area;
2158         save_offset += 7;
2159         save_offset &= ~7;
2160
2161         offset = code - cfg->native_code;
2162         /* we need about 16 instructions */
2163         if (offset > (cfg->code_size - 16 * 4)) {
2164                 cfg->code_size *= 2;
2165                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2166                 code = cfg->native_code + offset;
2167         }
2168         switch (rtype) {
2169         case MONO_TYPE_VOID:
2170                 /* special case string .ctor icall */
2171                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2172                         save_mode = SAVE_ONE;
2173                 else
2174                         save_mode = SAVE_NONE;
2175                 break;
2176         case MONO_TYPE_I8:
2177         case MONO_TYPE_U8:
2178                 save_mode = SAVE_TWO;
2179                 break;
2180         case MONO_TYPE_R4:
2181         case MONO_TYPE_R8:
2182                 save_mode = SAVE_FP;
2183                 break;
2184         case MONO_TYPE_VALUETYPE:
2185                 save_mode = SAVE_STRUCT;
2186                 break;
2187         default:
2188                 save_mode = SAVE_ONE;
2189                 break;
2190         }
2191
2192         switch (save_mode) {
2193         case SAVE_TWO:
2194                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2195                 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2196                 if (enable_arguments) {
2197                         ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2198                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2199                 }
2200                 break;
2201         case SAVE_ONE:
2202                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2203                 if (enable_arguments) {
2204                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2205                 }
2206                 break;
2207         case SAVE_FP:
2208                 /* FIXME: what reg?  */
2209                 if (enable_arguments) {
2210                         /* FIXME: what reg?  */
2211                 }
2212                 break;
2213         case SAVE_STRUCT:
2214                 if (enable_arguments) {
2215                         /* FIXME: get the actual address  */
2216                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2217                 }
2218                 break;
2219         case SAVE_NONE:
2220         default:
2221                 break;
2222         }
2223
2224         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2225         code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2226         code = emit_call_reg (code, ARMREG_IP);
2227
2228         switch (save_mode) {
2229         case SAVE_TWO:
2230                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2231                 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2232                 break;
2233         case SAVE_ONE:
2234                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2235                 break;
2236         case SAVE_FP:
2237                 /* FIXME */
2238                 break;
2239         case SAVE_NONE:
2240         default:
2241                 break;
2242         }
2243
2244         return code;
2245 }
2246
2247 /*
2248  * The immediate field for cond branches is big enough for all reasonable methods
2249  */
2250 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2251 if (0 && ins->inst_true_bb->native_offset) { \
2252         ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2253 } else { \
2254         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2255         ARM_B_COND (code, (condcode), 0);       \
2256 }
2257
2258 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2259
2260 /* emit an exception if condition is fail
2261  *
2262  * We assign the extra code used to throw the implicit exceptions
2263  * to cfg->bb_exit as far as the big branch handling is concerned
2264  */
2265 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name)            \
2266         do {                                                        \
2267                 mono_add_patch_info (cfg, code - cfg->native_code,   \
2268                                     MONO_PATCH_INFO_EXC, exc_name);  \
2269                 ARM_BL_COND (code, (condcode), 0);      \
2270         } while (0);
2271
2272 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2273
2274 void
2275 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2276 {
2277 }
2278
2279 void
2280 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2281 {
2282         MonoInst *ins, *n, *last_ins = NULL;
2283
2284         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2285                 switch (ins->opcode) {
2286                 case OP_MUL_IMM:
2287                 case OP_IMUL_IMM:
2288                         /* Already done by an arch-independent pass */
2289                         break;
2290                 case OP_LOAD_MEMBASE:
2291                 case OP_LOADI4_MEMBASE:
2292                         /*
2293                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2294                          * OP_LOAD_MEMBASE offset(basereg), reg
2295                          */
2296                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2297                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2298                             ins->inst_basereg == last_ins->inst_destbasereg &&
2299                             ins->inst_offset == last_ins->inst_offset) {
2300                                 if (ins->dreg == last_ins->sreg1) {
2301                                         MONO_DELETE_INS (bb, ins);
2302                                         continue;
2303                                 } else {
2304                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2305                                         ins->opcode = OP_MOVE;
2306                                         ins->sreg1 = last_ins->sreg1;
2307                                 }
2308
2309                         /*
2310                          * Note: reg1 must be different from the basereg in the second load
2311                          * OP_LOAD_MEMBASE offset(basereg), reg1
2312                          * OP_LOAD_MEMBASE offset(basereg), reg2
2313                          * -->
2314                          * OP_LOAD_MEMBASE offset(basereg), reg1
2315                          * OP_MOVE reg1, reg2
2316                          */
2317                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2318                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
2319                               ins->inst_basereg != last_ins->dreg &&
2320                               ins->inst_basereg == last_ins->inst_basereg &&
2321                               ins->inst_offset == last_ins->inst_offset) {
2322
2323                                 if (ins->dreg == last_ins->dreg) {
2324                                         MONO_DELETE_INS (bb, ins);
2325                                         continue;
2326                                 } else {
2327                                         ins->opcode = OP_MOVE;
2328                                         ins->sreg1 = last_ins->dreg;
2329                                 }
2330
2331                                 //g_assert_not_reached ();
2332
2333 #if 0
2334                         /*
2335                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2336                          * OP_LOAD_MEMBASE offset(basereg), reg
2337                          * -->
2338                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2339                          * OP_ICONST reg, imm
2340                          */
2341                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2342                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2343                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2344                                    ins->inst_offset == last_ins->inst_offset) {
2345                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2346                                 ins->opcode = OP_ICONST;
2347                                 ins->inst_c0 = last_ins->inst_imm;
2348                                 g_assert_not_reached (); // check this rule
2349 #endif
2350                         }
2351                         break;
2352                 case OP_LOADU1_MEMBASE:
2353                 case OP_LOADI1_MEMBASE:
2354                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2355                                         ins->inst_basereg == last_ins->inst_destbasereg &&
2356                                         ins->inst_offset == last_ins->inst_offset) {
2357                                 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2358                                 ins->sreg1 = last_ins->sreg1;
2359                         }
2360                         break;
2361                 case OP_LOADU2_MEMBASE:
2362                 case OP_LOADI2_MEMBASE:
2363                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2364                                         ins->inst_basereg == last_ins->inst_destbasereg &&
2365                                         ins->inst_offset == last_ins->inst_offset) {
2366                                 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2367                                 ins->sreg1 = last_ins->sreg1;
2368                         }
2369                         break;
2370                 case OP_MOVE:
2371                         ins->opcode = OP_MOVE;
2372                         /*
2373                          * OP_MOVE reg, reg
2374                          */
2375                         if (ins->dreg == ins->sreg1) {
2376                                 MONO_DELETE_INS (bb, ins);
2377                                 continue;
2378                         }
2379                         /*
2380                          * OP_MOVE sreg, dreg
2381                          * OP_MOVE dreg, sreg
2382                          */
2383                         if (last_ins && last_ins->opcode == OP_MOVE &&
2384                             ins->sreg1 == last_ins->dreg &&
2385                             ins->dreg == last_ins->sreg1) {
2386                                 MONO_DELETE_INS (bb, ins);
2387                                 continue;
2388                         }
2389                         break;
2390                 }
2391                 last_ins = ins;
2392                 ins = ins->next;
2393         }
2394         bb->last_ins = last_ins;
2395 }
2396
2397 /*
2398  * the branch_cc_table should maintain the order of these
2399  * opcodes.
2400 case CEE_BEQ:
2401 case CEE_BGE:
2402 case CEE_BGT:
2403 case CEE_BLE:
2404 case CEE_BLT:
2405 case CEE_BNE_UN:
2406 case CEE_BGE_UN:
2407 case CEE_BGT_UN:
2408 case CEE_BLE_UN:
2409 case CEE_BLT_UN:
2410  */
2411 static const guchar
2412 branch_cc_table [] = {
2413         ARMCOND_EQ,
2414         ARMCOND_GE,
2415         ARMCOND_GT,
2416         ARMCOND_LE,
2417         ARMCOND_LT,
2418
2419         ARMCOND_NE,
2420         ARMCOND_HS,
2421         ARMCOND_HI,
2422         ARMCOND_LS,
2423         ARMCOND_LO
2424 };
2425
2426 #define NEW_INS(cfg,dest,op) do {       \
2427                 MONO_INST_NEW ((cfg), (dest), (op)); \
2428         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2429         } while (0)
2430
2431 static int
2432 map_to_reg_reg_op (int op)
2433 {
2434         switch (op) {
2435         case OP_ADD_IMM:
2436                 return OP_IADD;
2437         case OP_SUB_IMM:
2438                 return OP_ISUB;
2439         case OP_AND_IMM:
2440                 return OP_IAND;
2441         case OP_COMPARE_IMM:
2442                 return OP_COMPARE;
2443         case OP_ICOMPARE_IMM:
2444                 return OP_ICOMPARE;
2445         case OP_ADDCC_IMM:
2446                 return OP_ADDCC;
2447         case OP_ADC_IMM:
2448                 return OP_ADC;
2449         case OP_SUBCC_IMM:
2450                 return OP_SUBCC;
2451         case OP_SBB_IMM:
2452                 return OP_SBB;
2453         case OP_OR_IMM:
2454                 return OP_IOR;
2455         case OP_XOR_IMM:
2456                 return OP_IXOR;
2457         case OP_LOAD_MEMBASE:
2458                 return OP_LOAD_MEMINDEX;
2459         case OP_LOADI4_MEMBASE:
2460                 return OP_LOADI4_MEMINDEX;
2461         case OP_LOADU4_MEMBASE:
2462                 return OP_LOADU4_MEMINDEX;
2463         case OP_LOADU1_MEMBASE:
2464                 return OP_LOADU1_MEMINDEX;
2465         case OP_LOADI2_MEMBASE:
2466                 return OP_LOADI2_MEMINDEX;
2467         case OP_LOADU2_MEMBASE:
2468                 return OP_LOADU2_MEMINDEX;
2469         case OP_LOADI1_MEMBASE:
2470                 return OP_LOADI1_MEMINDEX;
2471         case OP_STOREI1_MEMBASE_REG:
2472                 return OP_STOREI1_MEMINDEX;
2473         case OP_STOREI2_MEMBASE_REG:
2474                 return OP_STOREI2_MEMINDEX;
2475         case OP_STOREI4_MEMBASE_REG:
2476                 return OP_STOREI4_MEMINDEX;
2477         case OP_STORE_MEMBASE_REG:
2478                 return OP_STORE_MEMINDEX;
2479         case OP_STORER4_MEMBASE_REG:
2480                 return OP_STORER4_MEMINDEX;
2481         case OP_STORER8_MEMBASE_REG:
2482                 return OP_STORER8_MEMINDEX;
2483         case OP_STORE_MEMBASE_IMM:
2484                 return OP_STORE_MEMBASE_REG;
2485         case OP_STOREI1_MEMBASE_IMM:
2486                 return OP_STOREI1_MEMBASE_REG;
2487         case OP_STOREI2_MEMBASE_IMM:
2488                 return OP_STOREI2_MEMBASE_REG;
2489         case OP_STOREI4_MEMBASE_IMM:
2490                 return OP_STOREI4_MEMBASE_REG;
2491         }
2492         g_assert_not_reached ();
2493 }
2494
2495 /*
2496  * Remove from the instruction list the instructions that can't be
2497  * represented with very simple instructions with no register
2498  * requirements.
2499  */
2500 void
2501 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2502 {
2503         MonoInst *ins, *temp, *last_ins = NULL;
2504         int rot_amount, imm8, low_imm;
2505
2506         MONO_BB_FOR_EACH_INS (bb, ins) {
2507 loop_start:
2508                 switch (ins->opcode) {
2509                 case OP_ADD_IMM:
2510                 case OP_SUB_IMM:
2511                 case OP_AND_IMM:
2512                 case OP_COMPARE_IMM:
2513                 case OP_ICOMPARE_IMM:
2514                 case OP_ADDCC_IMM:
2515                 case OP_ADC_IMM:
2516                 case OP_SUBCC_IMM:
2517                 case OP_SBB_IMM:
2518                 case OP_OR_IMM:
2519                 case OP_XOR_IMM:
2520                 case OP_IADD_IMM:
2521                 case OP_ISUB_IMM:
2522                 case OP_IAND_IMM:
2523                 case OP_IADC_IMM:
2524                 case OP_ISBB_IMM:
2525                 case OP_IOR_IMM:
2526                 case OP_IXOR_IMM:
2527                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2528                                 NEW_INS (cfg, temp, OP_ICONST);
2529                                 temp->inst_c0 = ins->inst_imm;
2530                                 temp->dreg = mono_alloc_ireg (cfg);
2531                                 ins->sreg2 = temp->dreg;
2532                                 ins->opcode = mono_op_imm_to_op (ins->opcode);
2533                         }
2534                         if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2535                                 goto loop_start;
2536                         else
2537                                 break;
2538                 case OP_MUL_IMM:
2539                 case OP_IMUL_IMM:
2540                         if (ins->inst_imm == 1) {
2541                                 ins->opcode = OP_MOVE;
2542                                 break;
2543                         }
2544                         if (ins->inst_imm == 0) {
2545                                 ins->opcode = OP_ICONST;
2546                                 ins->inst_c0 = 0;
2547                                 break;
2548                         }
2549                         imm8 = mono_is_power_of_two (ins->inst_imm);
2550                         if (imm8 > 0) {
2551                                 ins->opcode = OP_SHL_IMM;
2552                                 ins->inst_imm = imm8;
2553                                 break;
2554                         }
2555                         NEW_INS (cfg, temp, OP_ICONST);
2556                         temp->inst_c0 = ins->inst_imm;
2557                         temp->dreg = mono_alloc_ireg (cfg);
2558                         ins->sreg2 = temp->dreg;
2559                         ins->opcode = OP_IMUL;
2560                         break;
2561                 case OP_SBB:
2562                 case OP_ISBB:
2563                 case OP_SUBCC:
2564                 case OP_ISUBCC:
2565                         if (ins->next  && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2566                                 /* ARM sets the C flag to 1 if there was _no_ overflow */
2567                                 ins->next->opcode = OP_COND_EXC_NC;
2568                         break;
2569                 case OP_LOCALLOC_IMM:
2570                         NEW_INS (cfg, temp, OP_ICONST);
2571                         temp->inst_c0 = ins->inst_imm;
2572                         temp->dreg = mono_alloc_ireg (cfg);
2573                         ins->sreg1 = temp->dreg;
2574                         ins->opcode = OP_LOCALLOC;
2575                         break;
2576                 case OP_LOAD_MEMBASE:
2577                 case OP_LOADI4_MEMBASE:
2578                 case OP_LOADU4_MEMBASE:
2579                 case OP_LOADU1_MEMBASE:
2580                         /* we can do two things: load the immed in a register
2581                          * and use an indexed load, or see if the immed can be
2582                          * represented as an ad_imm + a load with a smaller offset
2583                          * that fits. We just do the first for now, optimize later.
2584                          */
2585                         if (arm_is_imm12 (ins->inst_offset))
2586                                 break;
2587                         NEW_INS (cfg, temp, OP_ICONST);
2588                         temp->inst_c0 = ins->inst_offset;
2589                         temp->dreg = mono_alloc_ireg (cfg);
2590                         ins->sreg2 = temp->dreg;
2591                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2592                         break;
2593                 case OP_LOADI2_MEMBASE:
2594                 case OP_LOADU2_MEMBASE:
2595                 case OP_LOADI1_MEMBASE:
2596                         if (arm_is_imm8 (ins->inst_offset))
2597                                 break;
2598                         NEW_INS (cfg, temp, OP_ICONST);
2599                         temp->inst_c0 = ins->inst_offset;
2600                         temp->dreg = mono_alloc_ireg (cfg);
2601                         ins->sreg2 = temp->dreg;
2602                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2603                         break;
2604                 case OP_LOADR4_MEMBASE:
2605                 case OP_LOADR8_MEMBASE:
2606                         if (arm_is_fpimm8 (ins->inst_offset))
2607                                 break;
2608                         low_imm = ins->inst_offset & 0x1ff;
2609                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2610                                 NEW_INS (cfg, temp, OP_ADD_IMM);
2611                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
2612                                 temp->sreg1 = ins->inst_basereg;
2613                                 temp->dreg = mono_alloc_ireg (cfg);
2614                                 ins->inst_basereg = temp->dreg;
2615                                 ins->inst_offset = low_imm;
2616                                 break;
2617                         }
2618                         /* VFP/FPA doesn't have indexed load instructions */
2619                         g_assert_not_reached ();
2620                         break;
2621                 case OP_STORE_MEMBASE_REG:
2622                 case OP_STOREI4_MEMBASE_REG:
2623                 case OP_STOREI1_MEMBASE_REG:
2624                         if (arm_is_imm12 (ins->inst_offset))
2625                                 break;
2626                         NEW_INS (cfg, temp, OP_ICONST);
2627                         temp->inst_c0 = ins->inst_offset;
2628                         temp->dreg = mono_alloc_ireg (cfg);
2629                         ins->sreg2 = temp->dreg;
2630                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2631                         break;
2632                 case OP_STOREI2_MEMBASE_REG:
2633                         if (arm_is_imm8 (ins->inst_offset))
2634                                 break;
2635                         NEW_INS (cfg, temp, OP_ICONST);
2636                         temp->inst_c0 = ins->inst_offset;
2637                         temp->dreg = mono_alloc_ireg (cfg);
2638                         ins->sreg2 = temp->dreg;
2639                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2640                         break;
2641                 case OP_STORER4_MEMBASE_REG:
2642                 case OP_STORER8_MEMBASE_REG:
2643                         if (arm_is_fpimm8 (ins->inst_offset))
2644                                 break;
2645                         low_imm = ins->inst_offset & 0x1ff;
2646                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2647                                 NEW_INS (cfg, temp, OP_ADD_IMM);
2648                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
2649                                 temp->sreg1 = ins->inst_destbasereg;
2650                                 temp->dreg = mono_alloc_ireg (cfg);
2651                                 ins->inst_destbasereg = temp->dreg;
2652                                 ins->inst_offset = low_imm;
2653                                 break;
2654                         }
2655                         /*g_print ("fail with: %d (%d, %d)\n", ins->inst_offset, ins->inst_offset & ~0x1ff, low_imm);*/
2656                         /* VFP/FPA doesn't have indexed store instructions */
2657                         g_assert_not_reached ();
2658                         break;
2659                 case OP_STORE_MEMBASE_IMM:
2660                 case OP_STOREI1_MEMBASE_IMM:
2661                 case OP_STOREI2_MEMBASE_IMM:
2662                 case OP_STOREI4_MEMBASE_IMM:
2663                         NEW_INS (cfg, temp, OP_ICONST);
2664                         temp->inst_c0 = ins->inst_imm;
2665                         temp->dreg = mono_alloc_ireg (cfg);
2666                         ins->sreg1 = temp->dreg;
2667                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2668                         last_ins = temp;
2669                         goto loop_start; /* make it handle the possibly big ins->inst_offset */
2670                 case OP_FCOMPARE: {
2671                         gboolean swap = FALSE;
2672                         int reg;
2673
2674                         if (!ins->next) {
2675                                 /* Optimized away */
2676                                 NULLIFY_INS (ins);
2677                                 break;
2678                         }
2679
2680                         /* Some fp compares require swapped operands */
2681                         switch (ins->next->opcode) {
2682                         case OP_FBGT:
2683                                 ins->next->opcode = OP_FBLT;
2684                                 swap = TRUE;
2685                                 break;
2686                         case OP_FBGT_UN:
2687                                 ins->next->opcode = OP_FBLT_UN;
2688                                 swap = TRUE;
2689                                 break;
2690                         case OP_FBLE:
2691                                 ins->next->opcode = OP_FBGE;
2692                                 swap = TRUE;
2693                                 break;
2694                         case OP_FBLE_UN:
2695                                 ins->next->opcode = OP_FBGE_UN;
2696                                 swap = TRUE;
2697                                 break;
2698                         default:
2699                                 break;
2700                         }
2701                         if (swap) {
2702                                 reg = ins->sreg1;
2703                                 ins->sreg1 = ins->sreg2;
2704                                 ins->sreg2 = reg;
2705                         }
2706                         break;
2707                 }
2708                 }
2709
2710                 last_ins = ins;
2711         }
2712         bb->last_ins = last_ins;
2713         bb->max_vreg = cfg->next_vreg;
2714 }
2715
2716 void
2717 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2718 {
2719         MonoInst *ins;
2720
2721         if (long_ins->opcode == OP_LNEG) {
2722                 ins = long_ins;
2723                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
2724                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
2725                 NULLIFY_INS (ins);
2726         }
2727 }
2728
2729 static guchar*
2730 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2731 {
2732         /* sreg is a float, dreg is an integer reg  */
2733 #ifdef ARM_FPU_FPA
2734         ARM_FIXZ (code, dreg, sreg);
2735 #elif defined(ARM_FPU_VFP)
2736         if (is_signed)
2737                 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
2738         else
2739                 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
2740         ARM_FMRS (code, dreg, ARM_VFP_F0);
2741 #endif
2742         if (!is_signed) {
2743                 if (size == 1)
2744                         ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
2745                 else if (size == 2) {
2746                         ARM_SHL_IMM (code, dreg, dreg, 16);
2747                         ARM_SHR_IMM (code, dreg, dreg, 16);
2748                 }
2749         } else {
2750                 if (size == 1) {
2751                         ARM_SHL_IMM (code, dreg, dreg, 24);
2752                         ARM_SAR_IMM (code, dreg, dreg, 24);
2753                 } else if (size == 2) {
2754                         ARM_SHL_IMM (code, dreg, dreg, 16);
2755                         ARM_SAR_IMM (code, dreg, dreg, 16);
2756                 }
2757         }
2758         return code;
2759 }
2760
2761 #endif /* #ifndef DISABLE_JIT */
2762
2763 typedef struct {
2764         guchar *code;
2765         const guchar *target;
2766         int absolute;
2767         int found;
2768 } PatchData;
2769
2770 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
2771
2772 static int
2773 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
2774         PatchData *pdata = (PatchData*)user_data;
2775         guchar *code = data;
2776         guint32 *thunks = data;
2777         guint32 *endthunks = (guint32*)(code + bsize);
2778         int count = 0;
2779         int difflow, diffhigh;
2780
2781         /* always ensure a call from pdata->code can reach to the thunks without further thunks */
2782         difflow = (char*)pdata->code - (char*)thunks;
2783         diffhigh = (char*)pdata->code - (char*)endthunks;
2784         if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
2785                 return 0;
2786
2787         /*
2788          * The thunk is composed of 3 words:
2789          * load constant from thunks [2] into ARM_IP
2790          * bx to ARM_IP
2791          * address constant
2792          * Note that the LR register is already setup
2793          */
2794         //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
2795         if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
2796                 while (thunks < endthunks) {
2797                         //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
2798                         if (thunks [2] == (guint32)pdata->target) {
2799                                 arm_patch (pdata->code, (guchar*)thunks);
2800                                 mono_arch_flush_icache (pdata->code, 4);
2801                                 pdata->found = 1;
2802                                 return 1;
2803                         } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
2804                                 /* found a free slot instead: emit thunk */
2805                                 /* ARMREG_IP is fine to use since this can't be an IMT call
2806                                  * which is indirect
2807                                  */
2808                                 code = (guchar*)thunks;
2809                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2810                                 if (thumb_supported)
2811                                         ARM_BX (code, ARMREG_IP);
2812                                 else
2813                                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2814                                 thunks [2] = (guint32)pdata->target;
2815                                 mono_arch_flush_icache ((guchar*)thunks, 12);
2816
2817                                 arm_patch (pdata->code, (guchar*)thunks);
2818                                 mono_arch_flush_icache (pdata->code, 4);
2819                                 pdata->found = 1;
2820                                 return 1;
2821                         }
2822                         /* skip 12 bytes, the size of the thunk */
2823                         thunks += 3;
2824                         count++;
2825                 }
2826                 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
2827         }
2828         return 0;
2829 }
2830
2831 static void
2832 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
2833 {
2834         PatchData pdata;
2835
2836         if (!domain)
2837                 domain = mono_domain_get ();
2838
2839         pdata.code = code;
2840         pdata.target = target;
2841         pdata.absolute = absolute;
2842         pdata.found = 0;
2843
2844         if (dyn_code_mp) {
2845                 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
2846         }
2847
2848         if (pdata.found != 1) {
2849                 mono_domain_lock (domain);
2850                 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
2851
2852                 if (!pdata.found) {
2853                         /* this uses the first available slot */
2854                         pdata.found = 2;
2855                         mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
2856                 }
2857                 mono_domain_unlock (domain);
2858         }
2859
2860         if (pdata.found != 1) {
2861                 GHashTable *hash;
2862                 GHashTableIter iter;
2863                 MonoJitDynamicMethodInfo *ji;
2864
2865                 /*
2866                  * This might be a dynamic method, search its code manager. We can only
2867                  * use the dynamic method containing CODE, since the others might be freed later.
2868                  */
2869                 pdata.found = 0;
2870
2871                 mono_domain_lock (domain);
2872                 hash = domain_jit_info (domain)->dynamic_code_hash;
2873                 if (hash) {
2874                         /* FIXME: Speed this up */
2875                         g_hash_table_iter_init (&iter, hash);
2876                         while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
2877                                 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
2878                                 if (pdata.found == 1)
2879                                         break;
2880                         }
2881                 }
2882                 mono_domain_unlock (domain);
2883         }
2884         if (pdata.found != 1)
2885                 g_print ("thunk failed for %p from %p\n", target, code);
2886         g_assert (pdata.found == 1);
2887 }
2888
2889 static void
2890 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
2891 {
2892         guint32 *code32 = (void*)code;
2893         guint32 ins = *code32;
2894         guint32 prim = (ins >> 25) & 7;
2895         guint32 tval = GPOINTER_TO_UINT (target);
2896
2897         //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
2898         if (prim == 5) { /* 101b */
2899                 /* the diff starts 8 bytes from the branch opcode */
2900                 gint diff = target - code - 8;
2901                 gint tbits;
2902                 gint tmask = 0xffffffff;
2903                 if (tval & 1) { /* entering thumb mode */
2904                         diff = target - 1 - code - 8;
2905                         g_assert (thumb_supported);
2906                         tbits = 0xf << 28; /* bl->blx bit pattern */
2907                         g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
2908                         /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
2909                         if (diff & 2) {
2910                                 tbits |= 1 << 24;
2911                         }
2912                         tmask = ~(1 << 24); /* clear the link bit */
2913                         /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
2914                 } else {
2915                         tbits = 0;
2916                 }
2917                 if (diff >= 0) {
2918                         if (diff <= 33554431) {
2919                                 diff >>= 2;
2920                                 ins = (ins & 0xff000000) | diff;
2921                                 ins &= tmask;
2922                                 *code32 = ins | tbits;
2923                                 return;
2924                         }
2925                 } else {
2926                         /* diff between 0 and -33554432 */
2927                         if (diff >= -33554432) {
2928                                 diff >>= 2;
2929                                 ins = (ins & 0xff000000) | (diff & ~0xff000000);
2930                                 ins &= tmask;
2931                                 *code32 = ins | tbits;
2932                                 return;
2933                         }
2934                 }
2935
2936                 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
2937                 return;
2938         }
2939
2940         /*
2941          * The alternative call sequences looks like this:
2942          *
2943          *      ldr ip, [pc] // loads the address constant
2944          *      b 1f         // jumps around the constant
2945          *      address constant embedded in the code
2946          *   1f:
2947          *      mov lr, pc
2948          *      mov pc, ip
2949          *
2950          * There are two cases for patching:
2951          * a) at the end of method emission: in this case code points to the start
2952          *    of the call sequence
2953          * b) during runtime patching of the call site: in this case code points
2954          *    to the mov pc, ip instruction
2955          *
2956          * We have to handle also the thunk jump code sequence:
2957          *
2958          *      ldr ip, [pc]
2959          *      mov pc, ip
2960          *      address constant // execution never reaches here
2961          */
2962         if ((ins & 0x0ffffff0) == 0x12fff10) {
2963                 /* Branch and exchange: the address is constructed in a reg
2964                  * We can patch BX when the code sequence is the following:
2965                  *  ldr     ip, [pc, #0]    ; 0x8
2966                  *  b       0xc
2967                  *  .word code_ptr
2968                  *  mov     lr, pc
2969                  *  bx      ips
2970                  * */
2971                 guint32 ccode [4];
2972                 guint8 *emit = (guint8*)ccode;
2973                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
2974                 ARM_B (emit, 0);
2975                 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
2976                 ARM_BX (emit, ARMREG_IP);
2977
2978                 /*patching from magic trampoline*/
2979                 if (ins == ccode [3]) {
2980                         g_assert (code32 [-4] == ccode [0]);
2981                         g_assert (code32 [-3] == ccode [1]);
2982                         g_assert (code32 [-1] == ccode [2]);
2983                         code32 [-2] = (guint32)target;
2984                         return;
2985                 }
2986                 /*patching from JIT*/
2987                 if (ins == ccode [0]) {
2988                         g_assert (code32 [1] == ccode [1]);
2989                         g_assert (code32 [3] == ccode [2]);
2990                         g_assert (code32 [4] == ccode [3]);
2991                         code32 [2] = (guint32)target;
2992                         return;
2993                 }
2994                 g_assert_not_reached ();
2995         } else if ((ins & 0x0ffffff0) == 0x12fff30) {
2996                 /*
2997                  * ldr ip, [pc, #0]
2998                  * b 0xc
2999                  * .word code_ptr
3000                  * blx ip
3001                  */
3002                 guint32 ccode [4];
3003                 guint8 *emit = (guint8*)ccode;
3004                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3005                 ARM_B (emit, 0);
3006                 ARM_BLX_REG (emit, ARMREG_IP);
3007
3008                 g_assert (code32 [-3] == ccode [0]);
3009                 g_assert (code32 [-2] == ccode [1]);
3010                 g_assert (code32 [0] == ccode [2]);
3011
3012                 code32 [-1] = (guint32)target;
3013         } else {
3014                 guint32 ccode [4];
3015                 guint32 *tmp = ccode;
3016                 guint8 *emit = (guint8*)tmp;
3017                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3018                 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3019                 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3020                 ARM_BX (emit, ARMREG_IP);
3021                 if (ins == ccode [2]) {
3022                         g_assert_not_reached (); // should be -2 ...
3023                         code32 [-1] = (guint32)target;
3024                         return;
3025                 }
3026                 if (ins == ccode [0]) {
3027                         /* handles both thunk jump code and the far call sequence */
3028                         code32 [2] = (guint32)target;
3029                         return;
3030                 }
3031                 g_assert_not_reached ();
3032         }
3033 //      g_print ("patched with 0x%08x\n", ins);
3034 }
3035
3036 void
3037 arm_patch (guchar *code, const guchar *target)
3038 {
3039         arm_patch_general (NULL, code, target, NULL);
3040 }
3041
3042 /*
3043  * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3044  * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3045  * to be used with the emit macros.
3046  * Return -1 otherwise.
3047  */
3048 int
3049 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3050 {
3051         guint32 res, i;
3052         for (i = 0; i < 31; i+= 2) {
3053                 res = (val << (32 - i)) | (val >> i);
3054                 if (res & ~0xff)
3055                         continue;
3056                 *rot_amount = i? 32 - i: 0;
3057                 return res;
3058         }
3059         return -1;
3060 }
3061
3062 /*
3063  * Emits in code a sequence of instructions that load the value 'val'
3064  * into the dreg register. Uses at most 4 instructions.
3065  */
3066 guint8*
3067 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3068 {
3069         int imm8, rot_amount;
3070 #if 0
3071         ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3072         /* skip the constant pool */
3073         ARM_B (code, 0);
3074         *(int*)code = val;
3075         code += 4;
3076         return code;
3077 #endif
3078         if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3079                 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3080         } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3081                 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3082         } else {
3083                 if (v7_supported) {
3084                         ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3085                         if (val >> 16)
3086                                 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3087                         return code;
3088                 }
3089                 if (val & 0xFF) {
3090                         ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3091                         if (val & 0xFF00) {
3092                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3093                         }
3094                         if (val & 0xFF0000) {
3095                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3096                         }
3097                         if (val & 0xFF000000) {
3098                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3099                         }
3100                 } else if (val & 0xFF00) {
3101                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3102                         if (val & 0xFF0000) {
3103                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3104                         }
3105                         if (val & 0xFF000000) {
3106                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3107                         }
3108                 } else if (val & 0xFF0000) {
3109                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3110                         if (val & 0xFF000000) {
3111                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3112                         }
3113                 }
3114                 //g_assert_not_reached ();
3115         }
3116         return code;
3117 }
3118
3119 gboolean
3120 mono_arm_thumb_supported (void)
3121 {
3122         return thumb_supported;
3123 }
3124
3125 #ifndef DISABLE_JIT
3126
3127 /*
3128  * emit_load_volatile_arguments:
3129  *
3130  *  Load volatile arguments from the stack to the original input registers.
3131  * Required before a tail call.
3132  */
3133 static guint8*
3134 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3135 {
3136         MonoMethod *method = cfg->method;
3137         MonoMethodSignature *sig;
3138         MonoInst *inst;
3139         CallInfo *cinfo;
3140         guint32 i, pos;
3141
3142         /* FIXME: Generate intermediate code instead */
3143
3144         sig = mono_method_signature (method);
3145
3146         /* This is the opposite of the code in emit_prolog */
3147
3148         pos = 0;
3149
3150         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3151
3152         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
3153                 ArgInfo *ainfo = &cinfo->ret;
3154                 inst = cfg->vret_addr;
3155                 g_assert (arm_is_imm12 (inst->inst_offset));
3156                 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3157         }
3158         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3159                 ArgInfo *ainfo = cinfo->args + i;
3160                 inst = cfg->args [pos];
3161
3162                 if (cfg->verbose_level > 2)
3163                         g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3164                 if (inst->opcode == OP_REGVAR) {
3165                         if (ainfo->storage == RegTypeGeneral)
3166                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3167                         else if (ainfo->storage == RegTypeFP) {
3168                                 g_assert_not_reached ();
3169                         } else if (ainfo->storage == RegTypeBase) {
3170                                 // FIXME:
3171                                 NOT_IMPLEMENTED;
3172                                 /*
3173                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3174                                         ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3175                                 } else {
3176                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3177                                         ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3178                                 }
3179                                 */
3180                         } else
3181                                 g_assert_not_reached ();
3182                 } else {
3183                         if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3184                                 switch (ainfo->size) {
3185                                 case 1:
3186                                 case 2:
3187                                         // FIXME:
3188                                         NOT_IMPLEMENTED;
3189                                         break;
3190                                 case 8:
3191                                         g_assert (arm_is_imm12 (inst->inst_offset));
3192                                         ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3193                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
3194                                         ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3195                                         break;
3196                                 default:
3197                                         if (arm_is_imm12 (inst->inst_offset)) {
3198                                                 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3199                                         } else {
3200                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3201                                                 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3202                                         }
3203                                         break;
3204                                 }
3205                         } else if (ainfo->storage == RegTypeBaseGen) {
3206                                 // FIXME:
3207                                 NOT_IMPLEMENTED;
3208                         } else if (ainfo->storage == RegTypeBase) {
3209                                 /* Nothing to do */
3210                         } else if (ainfo->storage == RegTypeFP) {
3211                                 g_assert_not_reached ();
3212                         } else if (ainfo->storage == RegTypeStructByVal) {
3213                                 int doffset = inst->inst_offset;
3214                                 int soffset = 0;
3215                                 int cur_reg;
3216                                 int size = 0;
3217                                 if (mono_class_from_mono_type (inst->inst_vtype))
3218                                         size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3219                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3220                                         if (arm_is_imm12 (doffset)) {
3221                                                 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3222                                         } else {
3223                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3224                                                 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3225                                         }
3226                                         soffset += sizeof (gpointer);
3227                                         doffset += sizeof (gpointer);
3228                                 }
3229                                 if (ainfo->vtsize)
3230                                         // FIXME:
3231                                         NOT_IMPLEMENTED;
3232                         } else if (ainfo->storage == RegTypeStructByAddr) {
3233                         } else {
3234                                 // FIXME:
3235                                 NOT_IMPLEMENTED;
3236                         }
3237                 }
3238                 pos ++;
3239         }
3240
3241         g_free (cinfo);
3242
3243         return code;
3244 }
3245
3246 void
3247 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3248 {
3249         MonoInst *ins;
3250         MonoCallInst *call;
3251         guint offset;
3252         guint8 *code = cfg->native_code + cfg->code_len;
3253         MonoInst *last_ins = NULL;
3254         guint last_offset = 0;
3255         int max_len, cpos;
3256         int imm8, rot_amount;
3257
3258         /* we don't align basic blocks of loops on arm */
3259
3260         if (cfg->verbose_level > 2)
3261                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3262
3263         cpos = bb->max_offset;
3264
3265         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3266                 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3267                 //g_assert (!mono_compile_aot);
3268                 //cpos += 6;
3269                 //if (bb->cil_code)
3270                 //      cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3271                 /* this is not thread save, but good enough */
3272                 /* fixme: howto handle overflows? */
3273                 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3274         }
3275
3276     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3277                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3278                                                          (gpointer)"mono_break");
3279                 code = emit_call_seq (cfg, code);
3280         }
3281
3282         MONO_BB_FOR_EACH_INS (bb, ins) {
3283                 offset = code - cfg->native_code;
3284
3285                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3286
3287                 if (offset > (cfg->code_size - max_len - 16)) {
3288                         cfg->code_size *= 2;
3289                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3290                         code = cfg->native_code + offset;
3291                 }
3292         //      if (ins->cil_code)
3293         //              g_print ("cil code\n");
3294                 mono_debug_record_line_number (cfg, ins, offset);
3295
3296                 switch (ins->opcode) {
3297                 case OP_MEMORY_BARRIER:
3298                         if (v6_supported) {
3299                                 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
3300                                 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
3301                         }
3302                         break;
3303                 case OP_TLS_GET:
3304 #ifdef HAVE_AEABI_READ_TP
3305                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3306                                                                  (gpointer)"__aeabi_read_tp");
3307                         code = emit_call_seq (cfg, code);
3308
3309                         ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3310 #else
3311                         g_assert_not_reached ();
3312 #endif
3313                         break;
3314                 /*case OP_BIGMUL:
3315                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3316                         ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3317                         break;
3318                 case OP_BIGMUL_UN:
3319                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3320                         ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3321                         break;*/
3322                 case OP_STOREI1_MEMBASE_IMM:
3323                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3324                         g_assert (arm_is_imm12 (ins->inst_offset));
3325                         ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3326                         break;
3327                 case OP_STOREI2_MEMBASE_IMM:
3328                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3329                         g_assert (arm_is_imm8 (ins->inst_offset));
3330                         ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3331                         break;
3332                 case OP_STORE_MEMBASE_IMM:
3333                 case OP_STOREI4_MEMBASE_IMM:
3334                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3335                         g_assert (arm_is_imm12 (ins->inst_offset));
3336                         ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3337                         break;
3338                 case OP_STOREI1_MEMBASE_REG:
3339                         g_assert (arm_is_imm12 (ins->inst_offset));
3340                         ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3341                         break;
3342                 case OP_STOREI2_MEMBASE_REG:
3343                         g_assert (arm_is_imm8 (ins->inst_offset));
3344                         ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3345                         break;
3346                 case OP_STORE_MEMBASE_REG:
3347                 case OP_STOREI4_MEMBASE_REG:
3348                         /* this case is special, since it happens for spill code after lowering has been called */
3349                         if (arm_is_imm12 (ins->inst_offset)) {
3350                                 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3351                         } else {
3352                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3353                                 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3354                         }
3355                         break;
3356                 case OP_STOREI1_MEMINDEX:
3357                         ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3358                         break;
3359                 case OP_STOREI2_MEMINDEX:
3360                         ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3361                         break;
3362                 case OP_STORE_MEMINDEX:
3363                 case OP_STOREI4_MEMINDEX:
3364                         ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3365                         break;
3366                 case OP_LOADU4_MEM:
3367                         g_assert_not_reached ();
3368                         break;
3369                 case OP_LOAD_MEMINDEX:
3370                 case OP_LOADI4_MEMINDEX:
3371                 case OP_LOADU4_MEMINDEX:
3372                         ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3373                         break;
3374                 case OP_LOADI1_MEMINDEX:
3375                         ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3376                         break;
3377                 case OP_LOADU1_MEMINDEX:
3378                         ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3379                         break;
3380                 case OP_LOADI2_MEMINDEX:
3381                         ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3382                         break;
3383                 case OP_LOADU2_MEMINDEX:
3384                         ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3385                         break;
3386                 case OP_LOAD_MEMBASE:
3387                 case OP_LOADI4_MEMBASE:
3388                 case OP_LOADU4_MEMBASE:
3389                         /* this case is special, since it happens for spill code after lowering has been called */
3390                         if (arm_is_imm12 (ins->inst_offset)) {
3391                                 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3392                         } else {
3393                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3394                                 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3395                         }
3396                         break;
3397                 case OP_LOADI1_MEMBASE:
3398                         g_assert (arm_is_imm8 (ins->inst_offset));
3399                         ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3400                         break;
3401                 case OP_LOADU1_MEMBASE:
3402                         g_assert (arm_is_imm12 (ins->inst_offset));
3403                         ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3404                         break;
3405                 case OP_LOADU2_MEMBASE:
3406                         g_assert (arm_is_imm8 (ins->inst_offset));
3407                         ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3408                         break;
3409                 case OP_LOADI2_MEMBASE:
3410                         g_assert (arm_is_imm8 (ins->inst_offset));
3411                         ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3412                         break;
3413                 case OP_ICONV_TO_I1:
3414                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3415                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3416                         break;
3417                 case OP_ICONV_TO_I2:
3418                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3419                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3420                         break;
3421                 case OP_ICONV_TO_U1:
3422                         ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3423                         break;
3424                 case OP_ICONV_TO_U2:
3425                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3426                         ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3427                         break;
3428                 case OP_COMPARE:
3429                 case OP_ICOMPARE:
3430                         ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3431                         break;
3432                 case OP_COMPARE_IMM:
3433                 case OP_ICOMPARE_IMM:
3434                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3435                         g_assert (imm8 >= 0);
3436                         ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3437                         break;
3438                 case OP_BREAK:
3439                         /*
3440                          * gdb does not like encountering the hw breakpoint ins in the debugged code.
3441                          * So instead of emitting a trap, we emit a call a C function and place a
3442                          * breakpoint there.
3443                          */
3444                         //*(int*)code = 0xef9f0001;
3445                         //code += 4;
3446                         //ARM_DBRK (code);
3447                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3448                                                                  (gpointer)"mono_break");
3449                         code = emit_call_seq (cfg, code);
3450                         break;
3451                 case OP_RELAXED_NOP:
3452                         ARM_NOP (code);
3453                         break;
3454                 case OP_NOP:
3455                 case OP_DUMMY_USE:
3456                 case OP_DUMMY_STORE:
3457                 case OP_NOT_REACHED:
3458                 case OP_NOT_NULL:
3459                         break;
3460                 case OP_SEQ_POINT: {
3461                         int i;
3462                         MonoInst *info_var = cfg->arch.seq_point_info_var;
3463                         MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3464                         MonoInst *var;
3465                         int dreg = ARMREG_LR;
3466
3467                         /*
3468                          * For AOT, we use one got slot per method, which will point to a
3469                          * SeqPointInfo structure, containing all the information required
3470                          * by the code below.
3471                          */
3472                         if (cfg->compile_aot) {
3473                                 g_assert (info_var);
3474                                 g_assert (info_var->opcode == OP_REGOFFSET);
3475                                 g_assert (arm_is_imm12 (info_var->inst_offset));
3476                         }
3477
3478                         /*
3479                          * Read from the single stepping trigger page. This will cause a
3480                          * SIGSEGV when single stepping is enabled.
3481                          * We do this _before_ the breakpoint, so single stepping after
3482                          * a breakpoint is hit will step to the next IL offset.
3483                          */
3484                         g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3485
3486                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3487                                 if (cfg->compile_aot) {
3488                                         /* Load the trigger page addr from the variable initialized in the prolog */
3489                                         var = ss_trigger_page_var;
3490                                         g_assert (var);
3491                                         g_assert (var->opcode == OP_REGOFFSET);
3492                                         g_assert (arm_is_imm12 (var->inst_offset));
3493                                         ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3494                                 } else {
3495                                         ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3496                                         ARM_B (code, 0);
3497                                         *(int*)code = (int)ss_trigger_page;
3498                                         code += 4;
3499                                 }
3500                                 ARM_LDR_IMM (code, dreg, dreg, 0);
3501                         }
3502
3503                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3504
3505                         if (cfg->compile_aot) {
3506                                 guint32 offset = code - cfg->native_code;
3507                                 guint32 val;
3508
3509                                 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3510                                 /* Add the offset */
3511                                 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3512                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3513                                 /*
3514                                  * Have to emit nops to keep the difference between the offset
3515                                  * stored in seq_points and breakpoint instruction constant,
3516                                  * mono_arch_get_ip_for_breakpoint () depends on this.
3517                                  */
3518                                 if (val & 0xFF00)
3519                                         ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3520                                 else
3521                                         ARM_NOP (code);
3522                                 if (val & 0xFF0000)
3523                                         ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3524                                 else
3525                                         ARM_NOP (code);
3526                                 g_assert (!(val & 0xFF000000));
3527                                 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3528                                 ARM_LDR_IMM (code, dreg, dreg, 0);
3529
3530                                 /* What is faster, a branch or a load ? */
3531                                 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3532                                 /* The breakpoint instruction */
3533                                 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3534                         } else {
3535                                 /*
3536                                  * A placeholder for a possible breakpoint inserted by
3537                                  * mono_arch_set_breakpoint ().
3538                                  */
3539                                 for (i = 0; i < 4; ++i)
3540                                         ARM_NOP (code);
3541                         }
3542                         break;
3543                 }
3544                 case OP_ADDCC:
3545                 case OP_IADDCC:
3546                         ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3547                         break;
3548                 case OP_IADD:
3549                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3550                         break;
3551                 case OP_ADC:
3552                 case OP_IADC:
3553                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3554                         break;
3555                 case OP_ADDCC_IMM:
3556                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3557                         g_assert (imm8 >= 0);
3558                         ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3559                         break;
3560                 case OP_ADD_IMM:
3561                 case OP_IADD_IMM:
3562                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3563                         g_assert (imm8 >= 0);
3564                         ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3565                         break;
3566                 case OP_ADC_IMM:
3567                 case OP_IADC_IMM:
3568                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3569                         g_assert (imm8 >= 0);
3570                         ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3571                         break;
3572                 case OP_IADD_OVF:
3573                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3574                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3575                         break;
3576                 case OP_IADD_OVF_UN:
3577                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3578                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3579                         break;
3580                 case OP_ISUB_OVF:
3581                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3582                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3583                         break;
3584                 case OP_ISUB_OVF_UN:
3585                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3586                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3587                         break;
3588                 case OP_ADD_OVF_CARRY:
3589                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3590                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3591                         break;
3592                 case OP_ADD_OVF_UN_CARRY:
3593                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3594                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3595                         break;
3596                 case OP_SUB_OVF_CARRY:
3597                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3598                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3599                         break;
3600                 case OP_SUB_OVF_UN_CARRY:
3601                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3602                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3603                         break;
3604                 case OP_SUBCC:
3605                 case OP_ISUBCC:
3606                         ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3607                         break;
3608                 case OP_SUBCC_IMM:
3609                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3610                         g_assert (imm8 >= 0);
3611                         ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3612                         break;
3613                 case OP_ISUB:
3614                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3615                         break;
3616                 case OP_SBB:
3617                 case OP_ISBB:
3618                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3619                         break;
3620                 case OP_SUB_IMM:
3621                 case OP_ISUB_IMM:
3622                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3623                         g_assert (imm8 >= 0);
3624                         ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3625                         break;
3626                 case OP_SBB_IMM:
3627                 case OP_ISBB_IMM:
3628                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3629                         g_assert (imm8 >= 0);
3630                         ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3631                         break;
3632                 case OP_ARM_RSBS_IMM:
3633                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3634                         g_assert (imm8 >= 0);
3635                         ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3636                         break;
3637                 case OP_ARM_RSC_IMM:
3638                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3639                         g_assert (imm8 >= 0);
3640                         ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3641                         break;
3642                 case OP_IAND:
3643                         ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3644                         break;
3645                 case OP_AND_IMM:
3646                 case OP_IAND_IMM:
3647                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3648                         g_assert (imm8 >= 0);
3649                         ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3650                         break;
3651                 case OP_IDIV:
3652                 case OP_IDIV_UN:
3653                 case OP_DIV_IMM:
3654                 case OP_IREM:
3655                 case OP_IREM_UN:
3656                 case OP_REM_IMM:
3657                         /* crappy ARM arch doesn't have a DIV instruction */
3658                         g_assert_not_reached ();
3659                 case OP_IOR:
3660                         ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3661                         break;
3662                 case OP_OR_IMM:
3663                 case OP_IOR_IMM:
3664                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3665                         g_assert (imm8 >= 0);
3666                         ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3667                         break;
3668                 case OP_IXOR:
3669                         ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3670                         break;
3671                 case OP_XOR_IMM:
3672                 case OP_IXOR_IMM:
3673                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3674                         g_assert (imm8 >= 0);
3675                         ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3676                         break;
3677                 case OP_ISHL:
3678                         ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3679                         break;
3680                 case OP_SHL_IMM:
3681                 case OP_ISHL_IMM:
3682                         if (ins->inst_imm)
3683                                 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3684                         else if (ins->dreg != ins->sreg1)
3685                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3686                         break;
3687                 case OP_ISHR:
3688                         ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3689                         break;
3690                 case OP_SHR_IMM:
3691                 case OP_ISHR_IMM:
3692                         if (ins->inst_imm)
3693                                 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3694                         else if (ins->dreg != ins->sreg1)
3695                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3696                         break;
3697                 case OP_SHR_UN_IMM:
3698                 case OP_ISHR_UN_IMM:
3699                         if (ins->inst_imm)
3700                                 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3701                         else if (ins->dreg != ins->sreg1)
3702                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3703                         break;
3704                 case OP_ISHR_UN:
3705                         ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3706                         break;
3707                 case OP_INOT:
3708                         ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
3709                         break;
3710                 case OP_INEG:
3711                         ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
3712                         break;
3713                 case OP_IMUL:
3714                         if (ins->dreg == ins->sreg2)
3715                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3716                         else
3717                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
3718                         break;
3719                 case OP_MUL_IMM:
3720                         g_assert_not_reached ();
3721                         break;
3722                 case OP_IMUL_OVF:
3723                         /* FIXME: handle ovf/ sreg2 != dreg */
3724                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3725                         /* FIXME: MUL doesn't set the C/O flags on ARM */
3726                         break;
3727                 case OP_IMUL_OVF_UN:
3728                         /* FIXME: handle ovf/ sreg2 != dreg */
3729                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3730                         /* FIXME: MUL doesn't set the C/O flags on ARM */
3731                         break;
3732                 case OP_ICONST:
3733                         code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
3734                         break;
3735                 case OP_AOTCONST:
3736                         /* Load the GOT offset */
3737                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3738                         ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
3739                         ARM_B (code, 0);
3740                         *(gpointer*)code = NULL;
3741                         code += 4;
3742                         /* Load the value from the GOT */
3743                         ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
3744                         break;
3745                 case OP_ICONV_TO_I4:
3746                 case OP_ICONV_TO_U4:
3747                 case OP_MOVE:
3748                         if (ins->dreg != ins->sreg1)
3749                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3750                         break;
3751                 case OP_SETLRET: {
3752                         int saved = ins->sreg2;
3753                         if (ins->sreg2 == ARM_LSW_REG) {
3754                                 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
3755                                 saved = ARMREG_LR;
3756                         }
3757                         if (ins->sreg1 != ARM_LSW_REG)
3758                                 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
3759                         if (saved != ARM_MSW_REG)
3760                                 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
3761                         break;
3762                 }
3763                 case OP_FMOVE:
3764 #ifdef ARM_FPU_FPA
3765                         ARM_MVFD (code, ins->dreg, ins->sreg1);
3766 #elif defined(ARM_FPU_VFP)
3767                         ARM_CPYD (code, ins->dreg, ins->sreg1);
3768 #endif
3769                         break;
3770                 case OP_FCONV_TO_R4:
3771 #ifdef ARM_FPU_FPA
3772                         ARM_MVFS (code, ins->dreg, ins->sreg1);
3773 #elif defined(ARM_FPU_VFP)
3774                         ARM_CVTD (code, ins->dreg, ins->sreg1);
3775                         ARM_CVTS (code, ins->dreg, ins->dreg);
3776 #endif
3777                         break;
3778                 case OP_JMP:
3779                         /*
3780                          * Keep in sync with mono_arch_emit_epilog
3781                          */
3782                         g_assert (!cfg->method->save_lmf);
3783
3784                         code = emit_load_volatile_arguments (cfg, code);
3785
3786                         code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
3787                         if (iphone_abi) {
3788                                 if (cfg->used_int_regs)
3789                                         ARM_POP (code, cfg->used_int_regs);
3790                                 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
3791                         } else {
3792                                 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
3793                         }
3794                         mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3795                         if (cfg->compile_aot) {
3796                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3797                                 ARM_B (code, 0);
3798                                 *(gpointer*)code = NULL;
3799                                 code += 4;
3800                                 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
3801                         } else {
3802                                 ARM_B (code, 0);
3803                         }
3804                         break;
3805                 case OP_CHECK_THIS:
3806                         /* ensure ins->sreg1 is not NULL */
3807                         ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
3808                         break;
3809                 case OP_ARGLIST: {
3810                         g_assert (cfg->sig_cookie < 128);
3811                         ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
3812                         ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
3813                         break;
3814                 }
3815                 case OP_FCALL:
3816                 case OP_LCALL:
3817                 case OP_VCALL:
3818                 case OP_VCALL2:
3819                 case OP_VOIDCALL:
3820                 case OP_CALL:
3821                         call = (MonoCallInst*)ins;
3822                         if (ins->flags & MONO_INST_HAS_METHOD)
3823                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
3824                         else
3825                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
3826                         code = emit_call_seq (cfg, code);
3827                         code = emit_move_return_value (cfg, ins, code);
3828                         break;
3829                 case OP_FCALL_REG:
3830                 case OP_LCALL_REG:
3831                 case OP_VCALL_REG:
3832                 case OP_VCALL2_REG:
3833                 case OP_VOIDCALL_REG:
3834                 case OP_CALL_REG:
3835                         code = emit_call_reg (code, ins->sreg1);
3836                         code = emit_move_return_value (cfg, ins, code);
3837                         break;
3838                 case OP_FCALL_MEMBASE:
3839                 case OP_LCALL_MEMBASE:
3840                 case OP_VCALL_MEMBASE:
3841                 case OP_VCALL2_MEMBASE:
3842                 case OP_VOIDCALL_MEMBASE:
3843                 case OP_CALL_MEMBASE:
3844                         g_assert (arm_is_imm12 (ins->inst_offset));
3845                         g_assert (ins->sreg1 != ARMREG_LR);
3846                         call = (MonoCallInst*)ins;
3847                         if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE) {
3848                                 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
3849                                 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
3850                                 /*
3851                                  * We can't embed the method in the code stream in PIC code, or
3852                                  * in gshared code.
3853                                  * Instead, we put it in V5 in code emitted by
3854                                  * mono_arch_emit_imt_argument (), and embed NULL here to
3855                                  * signal the IMT thunk that the value is in V5.
3856                                  */
3857                                 if (call->dynamic_imt_arg)
3858                                         *((gpointer*)code) = NULL;
3859                                 else
3860                                         *((gpointer*)code) = (gpointer)call->method;
3861                                 code += 4;
3862                         } else {
3863                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
3864                                 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
3865                         }
3866                         code = emit_move_return_value (cfg, ins, code);
3867                         break;
3868                 case OP_LOCALLOC: {
3869                         /* keep alignment */
3870                         int alloca_waste = cfg->param_area;
3871                         alloca_waste += 7;
3872                         alloca_waste &= ~7;
3873                         /* round the size to 8 bytes */
3874                         ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
3875                         ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
3876                         if (alloca_waste)
3877                                 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
3878                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
3879                         /* memzero the area: dreg holds the size, sp is the pointer */
3880                         if (ins->flags & MONO_INST_INIT) {
3881                                 guint8 *start_loop, *branch_to_cond;
3882                                 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
3883                                 branch_to_cond = code;
3884                                 ARM_B (code, 0);
3885                                 start_loop = code;
3886                                 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
3887                                 arm_patch (branch_to_cond, code);
3888                                 /* decrement by 4 and set flags */
3889                                 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
3890                                 ARM_B_COND (code, ARMCOND_GE, 0);
3891                                 arm_patch (code - 4, start_loop);
3892                         }
3893                         ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
3894                         break;
3895                 }
3896                 case OP_DYN_CALL: {
3897                         int i;
3898                         MonoInst *var = cfg->dyn_call_var;
3899
3900                         g_assert (var->opcode == OP_REGOFFSET);
3901                         g_assert (arm_is_imm12 (var->inst_offset));
3902
3903                         /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
3904                         ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
3905                         /* ip = ftn */
3906                         ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
3907
3908                         /* Save args buffer */
3909                         ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
3910
3911                         /* Set stack slots using R0 as scratch reg */
3912                         /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
3913                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
3914                                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
3915                                 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
3916                         }
3917
3918                         /* Set argument registers */
3919                         for (i = 0; i < PARAM_REGS; ++i)
3920                                 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
3921
3922                         /* Make the call */
3923                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
3924                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3925
3926                         /* Save result */
3927                         ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
3928                         ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
3929                         ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
3930                         break;
3931                 }
3932                 case OP_THROW: {
3933                         if (ins->sreg1 != ARMREG_R0)
3934                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
3935                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3936                                              (gpointer)"mono_arch_throw_exception");
3937                         code = emit_call_seq (cfg, code);
3938                         break;
3939                 }
3940                 case OP_RETHROW: {
3941                         if (ins->sreg1 != ARMREG_R0)
3942                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
3943                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3944                                              (gpointer)"mono_arch_rethrow_exception");
3945                         code = emit_call_seq (cfg, code);
3946                         break;
3947                 }
3948                 case OP_START_HANDLER: {
3949                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3950
3951                         if (arm_is_imm12 (spvar->inst_offset)) {
3952                                 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
3953                         } else {
3954                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
3955                                 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
3956                         }
3957                         break;
3958                 }
3959                 case OP_ENDFILTER: {
3960                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3961
3962                         if (ins->sreg1 != ARMREG_R0)
3963                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
3964                         if (arm_is_imm12 (spvar->inst_offset)) {
3965                                 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
3966                         } else {
3967                                 g_assert (ARMREG_IP != spvar->inst_basereg);
3968                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
3969                                 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
3970                         }
3971                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3972                         break;
3973                 }
3974                 case OP_ENDFINALLY: {
3975                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3976
3977                         if (arm_is_imm12 (spvar->inst_offset)) {
3978                                 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
3979                         } else {
3980                                 g_assert (ARMREG_IP != spvar->inst_basereg);
3981                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
3982                                 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
3983                         }
3984                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3985                         break;
3986                 }
3987                 case OP_CALL_HANDLER:
3988                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3989                         ARM_BL (code, 0);
3990                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3991                         break;
3992                 case OP_LABEL:
3993                         ins->inst_c0 = code - cfg->native_code;
3994                         break;
3995                 case OP_BR:
3996                         /*if (ins->inst_target_bb->native_offset) {
3997                                 ARM_B (code, 0);
3998                                 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3999                         } else*/ {
4000                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4001                                 ARM_B (code, 0);
4002                         }
4003                         break;
4004                 case OP_BR_REG:
4005                         ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
4006                         break;
4007                 case OP_SWITCH:
4008                         /*
4009                          * In the normal case we have:
4010                          *      ldr pc, [pc, ins->sreg1 << 2]
4011                          *      nop
4012                          * If aot, we have:
4013                          *      ldr lr, [pc, ins->sreg1 << 2]
4014                          *      add pc, pc, lr
4015                          * After follows the data.
4016                          * FIXME: add aot support.
4017                          */
4018                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
4019                         max_len += 4 * GPOINTER_TO_INT (ins->klass);
4020                         if (offset + max_len > (cfg->code_size - 16)) {
4021                                 cfg->code_size += max_len;
4022                                 cfg->code_size *= 2;
4023                                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4024                                 code = cfg->native_code + offset;
4025                         }
4026                         ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
4027                         ARM_NOP (code);
4028                         code += 4 * GPOINTER_TO_INT (ins->klass);
4029                         break;
4030                 case OP_CEQ:
4031                 case OP_ICEQ:
4032                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4033                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4034                         break;
4035                 case OP_CLT:
4036                 case OP_ICLT:
4037                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4038                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
4039                         break;
4040                 case OP_CLT_UN:
4041                 case OP_ICLT_UN:
4042                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4043                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
4044                         break;
4045                 case OP_CGT:
4046                 case OP_ICGT:
4047                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4048                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
4049                         break;
4050                 case OP_CGT_UN:
4051                 case OP_ICGT_UN:
4052                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4053                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
4054                         break;
4055                 case OP_COND_EXC_EQ:
4056                 case OP_COND_EXC_NE_UN:
4057                 case OP_COND_EXC_LT:
4058                 case OP_COND_EXC_LT_UN:
4059                 case OP_COND_EXC_GT:
4060                 case OP_COND_EXC_GT_UN:
4061                 case OP_COND_EXC_GE:
4062                 case OP_COND_EXC_GE_UN:
4063                 case OP_COND_EXC_LE:
4064                 case OP_COND_EXC_LE_UN:
4065                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
4066                         break;
4067                 case OP_COND_EXC_IEQ:
4068                 case OP_COND_EXC_INE_UN:
4069                 case OP_COND_EXC_ILT:
4070                 case OP_COND_EXC_ILT_UN:
4071                 case OP_COND_EXC_IGT:
4072                 case OP_COND_EXC_IGT_UN:
4073                 case OP_COND_EXC_IGE:
4074                 case OP_COND_EXC_IGE_UN:
4075                 case OP_COND_EXC_ILE:
4076                 case OP_COND_EXC_ILE_UN:
4077                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4078                         break;
4079                 case OP_COND_EXC_C:
4080                 case OP_COND_EXC_IC:
4081                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4082                         break;
4083                 case OP_COND_EXC_OV:
4084                 case OP_COND_EXC_IOV:
4085                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4086                         break;
4087                 case OP_COND_EXC_NC:
4088                 case OP_COND_EXC_INC:
4089                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4090                         break;
4091                 case OP_COND_EXC_NO:
4092                 case OP_COND_EXC_INO:
4093                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4094                         break;
4095                 case OP_IBEQ:
4096                 case OP_IBNE_UN:
4097                 case OP_IBLT:
4098                 case OP_IBLT_UN:
4099                 case OP_IBGT:
4100                 case OP_IBGT_UN:
4101                 case OP_IBGE:
4102                 case OP_IBGE_UN:
4103                 case OP_IBLE:
4104                 case OP_IBLE_UN:
4105                         EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4106                         break;
4107
4108                 /* floating point opcodes */
4109 #ifdef ARM_FPU_FPA
4110                 case OP_R8CONST:
4111                         if (cfg->compile_aot) {
4112                                 ARM_LDFD (code, ins->dreg, ARMREG_PC, 0);
4113                                 ARM_B (code, 1);
4114                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4115                                 code += 4;
4116                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4117                                 code += 4;
4118                         } else {
4119                                 /* FIXME: we can optimize the imm load by dealing with part of
4120                                  * the displacement in LDFD (aligning to 512).
4121                                  */
4122                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4123                                 ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
4124                         }
4125                         break;
4126                 case OP_R4CONST:
4127                         if (cfg->compile_aot) {
4128                                 ARM_LDFS (code, ins->dreg, ARMREG_PC, 0);
4129                                 ARM_B (code, 0);
4130                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4131                                 code += 4;
4132                         } else {
4133                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4134                                 ARM_LDFS (code, ins->dreg, ARMREG_LR, 0);
4135                         }
4136                         break;
4137                 case OP_STORER8_MEMBASE_REG:
4138                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4139                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4140                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4141                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4142                                 ARM_STFD (code, ins->sreg1, ARMREG_LR, 0);
4143                         } else {
4144                                 ARM_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4145                         }
4146                         break;
4147                 case OP_LOADR8_MEMBASE:
4148                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4149                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4150                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4151                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4152                                 ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
4153                         } else {
4154                                 ARM_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4155                         }
4156                         break;
4157                 case OP_STORER4_MEMBASE_REG:
4158                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4159                         ARM_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4160                         break;
4161                 case OP_LOADR4_MEMBASE:
4162                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4163                         ARM_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4164                         break;
4165                 case OP_ICONV_TO_R_UN: {
4166                         int tmpreg;
4167                         tmpreg = ins->dreg == 0? 1: 0;
4168                         ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4169                         ARM_FLTD (code, ins->dreg, ins->sreg1);
4170                         ARM_B_COND (code, ARMCOND_GE, 8);
4171                         /* save the temp register */
4172                         ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4173                         ARM_STFD (code, tmpreg, ARMREG_SP, 0);
4174                         ARM_LDFD (code, tmpreg, ARMREG_PC, 12);
4175                         ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4176                         ARM_LDFD (code, tmpreg, ARMREG_SP, 0);
4177                         ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4178                         /* skip the constant pool */
4179                         ARM_B (code, 8);
4180                         code += 4;
4181                         *(int*)code = 0x41f00000;
4182                         code += 4;
4183                         *(int*)code = 0;
4184                         code += 4;
4185                         /* FIXME: adjust:
4186                          * ldfltd  ftemp, [pc, #8] 0x41f00000 0x00000000
4187                          * adfltd  fdest, fdest, ftemp
4188                          */
4189                         break;
4190                 }
4191                 case OP_ICONV_TO_R4:
4192                         ARM_FLTS (code, ins->dreg, ins->sreg1);
4193                         break;
4194                 case OP_ICONV_TO_R8:
4195                         ARM_FLTD (code, ins->dreg, ins->sreg1);
4196                         break;
4197
4198 #elif defined(ARM_FPU_VFP)
4199
4200                 case OP_R8CONST:
4201                         if (cfg->compile_aot) {
4202                                 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4203                                 ARM_B (code, 1);
4204                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4205                                 code += 4;
4206                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4207                                 code += 4;
4208                         } else {
4209                                 /* FIXME: we can optimize the imm load by dealing with part of
4210                                  * the displacement in LDFD (aligning to 512).
4211                                  */
4212                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4213                                 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4214                         }
4215                         break;
4216                 case OP_R4CONST:
4217                         if (cfg->compile_aot) {
4218                                 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4219                                 ARM_B (code, 0);
4220                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4221                                 code += 4;
4222                                 ARM_CVTS (code, ins->dreg, ins->dreg);
4223                         } else {
4224                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4225                                 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4226                                 ARM_CVTS (code, ins->dreg, ins->dreg);
4227                         }
4228                         break;
4229                 case OP_STORER8_MEMBASE_REG:
4230                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4231                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4232                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4233                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4234                                 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4235                         } else {
4236                                 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4237                         }
4238                         break;
4239                 case OP_LOADR8_MEMBASE:
4240                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4241                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4242                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4243                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4244                                 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4245                         } else {
4246                                 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4247                         }
4248                         break;
4249                 case OP_STORER4_MEMBASE_REG:
4250                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4251                         ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4252                         ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4253                         break;
4254                 case OP_LOADR4_MEMBASE:
4255                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4256                         ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4257                         ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4258                         break;
4259                 case OP_ICONV_TO_R_UN: {
4260                         g_assert_not_reached ();
4261                         break;
4262                 }
4263                 case OP_ICONV_TO_R4:
4264                         ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4265                         ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4266                         ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4267                         break;
4268                 case OP_ICONV_TO_R8:
4269                         ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4270                         ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4271                         break;
4272
4273                 case OP_SETFRET:
4274                         if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4275                                 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4276                                 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4277                         } else {
4278                                 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4279                         }
4280                         break;
4281
4282 #endif
4283
4284                 case OP_FCONV_TO_I1:
4285                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4286                         break;
4287                 case OP_FCONV_TO_U1:
4288                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4289                         break;
4290                 case OP_FCONV_TO_I2:
4291                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4292                         break;
4293                 case OP_FCONV_TO_U2:
4294                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4295                         break;
4296                 case OP_FCONV_TO_I4:
4297                 case OP_FCONV_TO_I:
4298                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4299                         break;
4300                 case OP_FCONV_TO_U4:
4301                 case OP_FCONV_TO_U:
4302                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4303                         break;
4304                 case OP_FCONV_TO_I8:
4305                 case OP_FCONV_TO_U8:
4306                         g_assert_not_reached ();
4307                         /* Implemented as helper calls */
4308                         break;
4309                 case OP_LCONV_TO_R_UN:
4310                         g_assert_not_reached ();
4311                         /* Implemented as helper calls */
4312                         break;
4313                 case OP_LCONV_TO_OVF_I4_2: {
4314                         guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4315                         /*
4316                          * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4317                          */
4318
4319                         ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4320                         high_bit_not_set = code;
4321                         ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4322
4323                         ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4324                         valid_negative = code;
4325                         ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4326                         invalid_negative = code;
4327                         ARM_B_COND (code, ARMCOND_AL, 0);
4328
4329                         arm_patch (high_bit_not_set, code);
4330
4331                         ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4332                         valid_positive = code;
4333                         ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4334
4335                         arm_patch (invalid_negative, code);
4336                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4337
4338                         arm_patch (valid_negative, code);
4339                         arm_patch (valid_positive, code);
4340
4341                         if (ins->dreg != ins->sreg1)
4342                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4343                         break;
4344                 }
4345 #ifdef ARM_FPU_FPA
4346                 case OP_FADD:
4347                         ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4348                         break;
4349                 case OP_FSUB:
4350                         ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4351                         break;
4352                 case OP_FMUL:
4353                         ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4354                         break;
4355                 case OP_FDIV:
4356                         ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4357                         break;
4358                 case OP_FNEG:
4359                         ARM_MNFD (code, ins->dreg, ins->sreg1);
4360                         break;
4361 #elif defined(ARM_FPU_VFP)
4362                 case OP_FADD:
4363                         ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4364                         break;
4365                 case OP_FSUB:
4366                         ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4367                         break;
4368                 case OP_FMUL:
4369                         ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4370                         break;
4371                 case OP_FDIV:
4372                         ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4373                         break;
4374                 case OP_FNEG:
4375                         ARM_NEGD (code, ins->dreg, ins->sreg1);
4376                         break;
4377 #endif
4378                 case OP_FREM:
4379                         /* emulated */
4380                         g_assert_not_reached ();
4381                         break;
4382                 case OP_FCOMPARE:
4383 #ifdef ARM_FPU_FPA
4384                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4385 #elif defined(ARM_FPU_VFP)
4386                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4387                         ARM_FMSTAT (code);
4388 #endif
4389                         break;
4390                 case OP_FCEQ:
4391 #ifdef ARM_FPU_FPA
4392                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4393 #elif defined(ARM_FPU_VFP)
4394                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4395                         ARM_FMSTAT (code);
4396 #endif
4397                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4398                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4399                         break;
4400                 case OP_FCLT:
4401 #ifdef ARM_FPU_FPA
4402                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4403 #elif defined(ARM_FPU_VFP)
4404                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4405                         ARM_FMSTAT (code);
4406 #endif
4407                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4408                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4409                         break;
4410                 case OP_FCLT_UN:
4411 #ifdef ARM_FPU_FPA
4412                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4413 #elif defined(ARM_FPU_VFP)
4414                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4415                         ARM_FMSTAT (code);
4416 #endif
4417                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4418                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4419                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4420                         break;
4421                 case OP_FCGT:
4422                         /* swapped */
4423 #ifdef ARM_FPU_FPA
4424                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4425 #elif defined(ARM_FPU_VFP)
4426                         ARM_CMPD (code, ins->sreg2, ins->sreg1);
4427                         ARM_FMSTAT (code);
4428 #endif
4429                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4430                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4431                         break;
4432                 case OP_FCGT_UN:
4433                         /* swapped */
4434 #ifdef ARM_FPU_FPA
4435                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4436 #elif defined(ARM_FPU_VFP)
4437                         ARM_CMPD (code, ins->sreg2, ins->sreg1);
4438                         ARM_FMSTAT (code);
4439 #endif
4440                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4441                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4442                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4443                         break;
4444                 /* ARM FPA flags table:
4445                  * N        Less than               ARMCOND_MI
4446                  * Z        Equal                   ARMCOND_EQ
4447                  * C        Greater Than or Equal   ARMCOND_CS
4448                  * V        Unordered               ARMCOND_VS
4449                  */
4450                 case OP_FBEQ:
4451                         EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4452                         break;
4453                 case OP_FBNE_UN:
4454                         EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4455                         break;
4456                 case OP_FBLT:
4457                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4458                         break;
4459                 case OP_FBLT_UN:
4460                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4461                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4462                         break;
4463                 case OP_FBGT:
4464                 case OP_FBGT_UN:
4465                 case OP_FBLE:
4466                 case OP_FBLE_UN:
4467                         g_assert_not_reached ();
4468                         break;
4469                 case OP_FBGE:
4470 #ifdef ARM_FPU_VFP
4471                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4472 #else
4473                         /* FPA requires EQ even thou the docs suggests that just CS is enough */
4474                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4475                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4476 #endif
4477                         break;
4478                 case OP_FBGE_UN:
4479                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4480                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4481                         break;
4482
4483                 case OP_CKFINITE: {
4484 #ifdef ARM_FPU_FPA
4485                         if (ins->dreg != ins->sreg1)
4486                                 ARM_MVFD (code, ins->dreg, ins->sreg1);
4487 #elif defined(ARM_FPU_VFP)
4488                         ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4489                         ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4490                         ARM_B (code, 1);
4491                         *(guint32*)code = 0xffffffff;
4492                         code += 4;
4493                         *(guint32*)code = 0x7fefffff;
4494                         code += 4;
4495                         ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4496                         ARM_FMSTAT (code);
4497                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4498                         ARM_CMPD (code, ins->sreg1, ins->sreg1);
4499                         ARM_FMSTAT (code);
4500                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4501
4502                         ARM_CPYD (code, ins->dreg, ins->sreg1);
4503 #endif
4504                         break;
4505                 }
4506                 default:
4507                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4508                         g_assert_not_reached ();
4509                 }
4510
4511                 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4512                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4513                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4514                         g_assert_not_reached ();
4515                 }
4516
4517                 cpos += max_len;
4518
4519                 last_ins = ins;
4520                 last_offset = offset;
4521         }
4522
4523         cfg->code_len = code - cfg->native_code;
4524 }
4525
4526 #endif /* DISABLE_JIT */
4527
4528 #ifdef HAVE_AEABI_READ_TP
4529 void __aeabi_read_tp (void);
4530 #endif
4531
4532 void
4533 mono_arch_register_lowlevel_calls (void)
4534 {
4535         /* The signature doesn't matter */
4536         mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4537         mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4538
4539 #ifndef MONO_CROSS_COMPILE
4540 #ifdef HAVE_AEABI_READ_TP
4541         mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4542 #endif
4543 #endif
4544 }
4545
4546 #define patch_lis_ori(ip,val) do {\
4547                 guint16 *__lis_ori = (guint16*)(ip);    \
4548                 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff;      \
4549                 __lis_ori [3] = ((guint32)(val)) & 0xffff;      \
4550         } while (0)
4551
4552 void
4553 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4554 {
4555         MonoJumpInfo *patch_info;
4556         gboolean compile_aot = !run_cctors;
4557
4558         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4559                 unsigned char *ip = patch_info->ip.i + code;
4560                 const unsigned char *target;
4561
4562                 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4563                         gpointer *jt = (gpointer*)(ip + 8);
4564                         int i;
4565                         /* jt is the inlined jump table, 2 instructions after ip
4566                          * In the normal case we store the absolute addresses,
4567                          * otherwise the displacements.
4568                          */
4569                         for (i = 0; i < patch_info->data.table->table_size; i++)
4570                                 jt [i] = code + (int)patch_info->data.table->table [i];
4571                         continue;
4572                 }
4573                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4574
4575                 if (compile_aot) {
4576                         switch (patch_info->type) {
4577                         case MONO_PATCH_INFO_BB:
4578                         case MONO_PATCH_INFO_LABEL:
4579                                 break;
4580                         default:
4581                                 /* No need to patch these */
4582                                 continue;
4583                         }
4584                 }
4585
4586                 switch (patch_info->type) {
4587                 case MONO_PATCH_INFO_IP:
4588                         g_assert_not_reached ();
4589                         patch_lis_ori (ip, ip);
4590                         continue;
4591                 case MONO_PATCH_INFO_METHOD_REL:
4592                         g_assert_not_reached ();
4593                         *((gpointer *)(ip)) = code + patch_info->data.offset;
4594                         continue;
4595                 case MONO_PATCH_INFO_METHODCONST:
4596                 case MONO_PATCH_INFO_CLASS:
4597                 case MONO_PATCH_INFO_IMAGE:
4598                 case MONO_PATCH_INFO_FIELD:
4599                 case MONO_PATCH_INFO_VTABLE:
4600                 case MONO_PATCH_INFO_IID:
4601                 case MONO_PATCH_INFO_SFLDA:
4602                 case MONO_PATCH_INFO_LDSTR:
4603                 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4604                 case MONO_PATCH_INFO_LDTOKEN:
4605                         g_assert_not_reached ();
4606                         /* from OP_AOTCONST : lis + ori */
4607                         patch_lis_ori (ip, target);
4608                         continue;
4609                 case MONO_PATCH_INFO_R4:
4610                 case MONO_PATCH_INFO_R8:
4611                         g_assert_not_reached ();
4612                         *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4613                         continue;
4614                 case MONO_PATCH_INFO_EXC_NAME:
4615                         g_assert_not_reached ();
4616                         *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4617                         continue;
4618                 case MONO_PATCH_INFO_NONE:
4619                 case MONO_PATCH_INFO_BB_OVF:
4620                 case MONO_PATCH_INFO_EXC_OVF:
4621                         /* everything is dealt with at epilog output time */
4622                         continue;
4623                 default:
4624                         break;
4625                 }
4626                 arm_patch_general (domain, ip, target, dyn_code_mp);
4627         }
4628 }
4629
4630 #ifndef DISABLE_JIT
4631
4632 /*
4633  * Stack frame layout:
4634  *
4635  *   ------------------- fp
4636  *      MonoLMF structure or saved registers
4637  *   -------------------
4638  *      locals
4639  *   -------------------
4640  *      spilled regs
4641  *   -------------------
4642  *      optional 8 bytes for tracing
4643  *   -------------------
4644  *      param area             size is cfg->param_area
4645  *   ------------------- sp
4646  */
4647 guint8 *
4648 mono_arch_emit_prolog (MonoCompile *cfg)
4649 {
4650         MonoMethod *method = cfg->method;
4651         MonoBasicBlock *bb;
4652         MonoMethodSignature *sig;
4653         MonoInst *inst;
4654         int alloc_size, pos, max_offset, i, rot_amount;
4655         guint8 *code;
4656         CallInfo *cinfo;
4657         int tracing = 0;
4658         int lmf_offset = 0;
4659         int prev_sp_offset, reg_offset;
4660
4661         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4662                 tracing = 1;
4663
4664         sig = mono_method_signature (method);
4665         cfg->code_size = 256 + sig->param_count * 64;
4666         code = cfg->native_code = g_malloc (cfg->code_size);
4667
4668         mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
4669
4670         alloc_size = cfg->stack_offset;
4671         pos = 0;
4672         prev_sp_offset = 0;
4673
4674         if (!method->save_lmf) {
4675                 if (iphone_abi) {
4676                         /*
4677                          * The iphone uses R7 as the frame pointer, and it points at the saved
4678                          * r7+lr:
4679                          *         <lr>
4680                          * r7 ->   <r7>
4681                          *         <rest of frame>
4682                          * We can't use r7 as a frame pointer since it points into the middle of
4683                          * the frame, so we keep using our own frame pointer.
4684                          * FIXME: Optimize this.
4685                          */
4686                         g_assert (darwin);
4687                         ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4688                         ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
4689                         prev_sp_offset += 8; /* r7 and lr */
4690                         mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4691                         mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
4692
4693                         /* No need to push LR again */
4694                         if (cfg->used_int_regs)
4695                                 ARM_PUSH (code, cfg->used_int_regs);
4696                 } else {
4697                         ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
4698                         prev_sp_offset += 4;
4699                 }
4700                 for (i = 0; i < 16; ++i) {
4701                         if (cfg->used_int_regs & (1 << i))
4702                                 prev_sp_offset += 4;
4703                 }
4704                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4705                 reg_offset = 0;
4706                 for (i = 0; i < 16; ++i) {
4707                         if ((cfg->used_int_regs & (1 << i))) {
4708                                 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
4709                                 reg_offset += 4;
4710                         }
4711                 }
4712                 if (iphone_abi) {
4713                         mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
4714                 } else {
4715                         mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
4716                 }
4717         } else {
4718                 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
4719                 ARM_PUSH (code, 0x5ff0);
4720                 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
4721                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4722                 reg_offset = 0;
4723                 for (i = 0; i < 16; ++i) {
4724                         if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
4725                                 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
4726                                 reg_offset += 4;
4727                         }
4728                 }
4729                 pos += sizeof (MonoLMF) - prev_sp_offset;
4730                 lmf_offset = pos;
4731         }
4732         alloc_size += pos;
4733         // align to MONO_ARCH_FRAME_ALIGNMENT bytes
4734         if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
4735                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
4736                 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
4737         }
4738
4739         /* the stack used in the pushed regs */
4740         if (prev_sp_offset & 4)
4741                 alloc_size += 4;
4742         cfg->stack_usage = alloc_size;
4743         if (alloc_size) {
4744                 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
4745                         ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4746                 } else {
4747                         code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
4748                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4749                 }
4750                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
4751         }
4752         if (cfg->frame_reg != ARMREG_SP) {
4753                 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
4754                 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
4755         }
4756         //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
4757         prev_sp_offset += alloc_size;
4758
4759         /* compute max_offset in order to use short forward jumps
4760          * we could skip do it on arm because the immediate displacement
4761          * for jumps is large enough, it may be useful later for constant pools
4762          */
4763         max_offset = 0;
4764         for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4765                 MonoInst *ins = bb->code;
4766                 bb->max_offset = max_offset;
4767
4768                 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4769                         max_offset += 6;
4770
4771                 MONO_BB_FOR_EACH_INS (bb, ins)
4772                         max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4773         }
4774
4775         /* store runtime generic context */
4776         if (cfg->rgctx_var) {
4777                 MonoInst *ins = cfg->rgctx_var;
4778
4779                 g_assert (ins->opcode == OP_REGOFFSET);
4780
4781                 if (arm_is_imm12 (ins->inst_offset)) {
4782                         ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
4783                 } else {
4784                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4785                         ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
4786                 }
4787         }
4788
4789         /* load arguments allocated to register from the stack */
4790         pos = 0;
4791
4792         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
4793
4794         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
4795                 ArgInfo *ainfo = &cinfo->ret;
4796                 inst = cfg->vret_addr;
4797                 g_assert (arm_is_imm12 (inst->inst_offset));
4798                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4799         }
4800
4801         if (sig->call_convention == MONO_CALL_VARARG) {
4802                 ArgInfo *cookie = &cinfo->sig_cookie;
4803
4804                 /* Save the sig cookie address */
4805                 g_assert (cookie->storage == RegTypeBase);
4806
4807                 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
4808                 g_assert (arm_is_imm12 (cfg->sig_cookie));
4809                 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
4810                 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4811         }
4812
4813         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4814                 ArgInfo *ainfo = cinfo->args + i;
4815                 inst = cfg->args [pos];
4816
4817                 if (cfg->verbose_level > 2)
4818                         g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
4819                 if (inst->opcode == OP_REGVAR) {
4820                         if (ainfo->storage == RegTypeGeneral)
4821                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
4822                         else if (ainfo->storage == RegTypeFP) {
4823                                 g_assert_not_reached ();
4824                         } else if (ainfo->storage == RegTypeBase) {
4825                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
4826                                         ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4827                                 } else {
4828                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4829                                         ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
4830                                 }
4831                         } else
4832                                 g_assert_not_reached ();
4833
4834                         if (cfg->verbose_level > 2)
4835                                 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
4836                 } else {
4837                         /* the argument should be put on the stack: FIXME handle size != word  */
4838                         if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
4839                                 switch (ainfo->size) {
4840                                 case 1:
4841                                         if (arm_is_imm12 (inst->inst_offset))
4842                                                 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4843                                         else {
4844                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4845                                                 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4846                                         }
4847                                         break;
4848                                 case 2:
4849                                         if (arm_is_imm8 (inst->inst_offset)) {
4850                                                 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4851                                         } else {
4852                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4853                                                 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4854                                         }
4855                                         break;
4856                                 case 8:
4857                                         g_assert (arm_is_imm12 (inst->inst_offset));
4858                                         ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4859                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
4860                                         ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
4861                                         break;
4862                                 default:
4863                                         if (arm_is_imm12 (inst->inst_offset)) {
4864                                                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4865                                         } else {
4866                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4867                                                 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4868                                         }
4869                                         break;
4870                                 }
4871                         } else if (ainfo->storage == RegTypeBaseGen) {
4872                                 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
4873                                 g_assert (arm_is_imm12 (inst->inst_offset));
4874                                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4875                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
4876                                 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
4877                         } else if (ainfo->storage == RegTypeBase) {
4878                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
4879                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4880                                 } else {
4881                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
4882                                         ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
4883                                 }
4884
4885                                 switch (ainfo->size) {
4886                                 case 1:
4887                                         if (arm_is_imm8 (inst->inst_offset)) {
4888                                                 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4889                                         } else {
4890                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4891                                                 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4892                                         }
4893                                         break;
4894                                 case 2:
4895                                         if (arm_is_imm8 (inst->inst_offset)) {
4896                                                 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4897                                         } else {
4898                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4899                                                 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4900                                         }
4901                                         break;
4902                                 case 8:
4903                                         if (arm_is_imm12 (inst->inst_offset)) {
4904                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4905                                         } else {
4906                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4907                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4908                                         }
4909                                         if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
4910                                                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
4911                                         } else {
4912                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
4913                                                 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
4914                                         }
4915                                         if (arm_is_imm12 (inst->inst_offset + 4)) {
4916                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
4917                                         } else {
4918                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
4919                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4920                                         }
4921                                         break;
4922                                 default:
4923                                         if (arm_is_imm12 (inst->inst_offset)) {
4924                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4925                                         } else {
4926                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4927                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4928                                         }
4929                                         break;
4930                                 }
4931                         } else if (ainfo->storage == RegTypeFP) {
4932                                 g_assert_not_reached ();
4933                         } else if (ainfo->storage == RegTypeStructByVal) {
4934                                 int doffset = inst->inst_offset;
4935                                 int soffset = 0;
4936                                 int cur_reg;
4937                                 int size = 0;
4938                                 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
4939                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
4940                                         if (arm_is_imm12 (doffset)) {
4941                                                 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
4942                                         } else {
4943                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
4944                                                 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
4945                                         }
4946                                         soffset += sizeof (gpointer);
4947                                         doffset += sizeof (gpointer);
4948                                 }
4949                                 if (ainfo->vtsize) {
4950                                         /* FIXME: handle overrun! with struct sizes not multiple of 4 */
4951                                         //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
4952                                         code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
4953                                 }
4954                         } else if (ainfo->storage == RegTypeStructByAddr) {
4955                                 g_assert_not_reached ();
4956                                 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
4957                                 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
4958                         } else
4959                                 g_assert_not_reached ();
4960                 }
4961                 pos++;
4962         }
4963
4964         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4965                 if (cfg->compile_aot)
4966                         /* AOT code is only used in the root domain */
4967                         code = mono_arm_emit_load_imm (code, ARMREG_R0, 0);
4968                 else
4969                         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->domain);
4970                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4971                              (gpointer)"mono_jit_thread_attach");
4972                 code = emit_call_seq (cfg, code);
4973         }
4974
4975         if (method->save_lmf) {
4976                 gboolean get_lmf_fast = FALSE;
4977
4978 #ifdef HAVE_AEABI_READ_TP
4979                 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
4980
4981                 if (lmf_addr_tls_offset != -1) {
4982                         get_lmf_fast = TRUE;
4983
4984                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4985                                                                  (gpointer)"__aeabi_read_tp");
4986                         code = emit_call_seq (cfg, code);
4987
4988                         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
4989                         get_lmf_fast = TRUE;
4990                 }
4991 #endif
4992                 if (!get_lmf_fast) {
4993                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4994                                                                  (gpointer)"mono_get_lmf_addr");
4995                         code = emit_call_seq (cfg, code);
4996                 }
4997                 /* we build the MonoLMF structure on the stack - see mini-arm.h */
4998                 /* lmf_offset is the offset from the previous stack pointer,
4999                  * alloc_size is the total stack space allocated, so the offset
5000                  * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
5001                  * The pointer to the struct is put in r1 (new_lmf).
5002                  * r2 is used as scratch
5003                  * The callee-saved registers are already in the MonoLMF structure
5004                  */
5005                 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, alloc_size - lmf_offset);
5006                 /* r0 is the result from mono_get_lmf_addr () */
5007                 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
5008                 /* new_lmf->previous_lmf = *lmf_addr */
5009                 ARM_LDR_IMM (code, ARMREG_R2, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
5010                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
5011                 /* *(lmf_addr) = r1 */
5012                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
5013                 /* Skip method (only needed for trampoline LMF frames) */
5014                 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, esp));
5015                 /* save the current IP */
5016                 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
5017                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, eip));
5018         }
5019
5020         if (tracing)
5021                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5022
5023         if (cfg->arch.seq_point_info_var) {
5024                 MonoInst *ins = cfg->arch.seq_point_info_var;
5025
5026                 /* Initialize the variable from a GOT slot */
5027                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
5028                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5029                 ARM_B (code, 0);
5030                 *(gpointer*)code = NULL;
5031                 code += 4;
5032                 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
5033
5034                 g_assert (ins->opcode == OP_REGOFFSET);
5035
5036                 if (arm_is_imm12 (ins->inst_offset)) {
5037                         ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5038                 } else {
5039                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5040                         ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5041                 }
5042         }
5043
5044         /* Initialize ss_trigger_page_var */
5045         {
5046                 MonoInst *info_var = cfg->arch.seq_point_info_var;
5047                 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
5048                 int dreg = ARMREG_LR;
5049
5050                 if (info_var) {
5051                         g_assert (info_var->opcode == OP_REGOFFSET);
5052                         g_assert (arm_is_imm12 (info_var->inst_offset));
5053
5054                         ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
5055                         /* Load the trigger page addr */
5056                         ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
5057                         ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
5058                 }
5059         }
5060
5061         cfg->code_len = code - cfg->native_code;
5062         g_assert (cfg->code_len < cfg->code_size);
5063         g_free (cinfo);
5064
5065         return code;
5066 }
5067
5068 void
5069 mono_arch_emit_epilog (MonoCompile *cfg)
5070 {
5071         MonoMethod *method = cfg->method;
5072         int pos, i, rot_amount;
5073         int max_epilog_size = 16 + 20*4;
5074         guint8 *code;
5075         CallInfo *cinfo;
5076
5077         if (cfg->method->save_lmf)
5078                 max_epilog_size += 128;
5079
5080         if (mono_jit_trace_calls != NULL)
5081                 max_epilog_size += 50;
5082
5083         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5084                 max_epilog_size += 50;
5085
5086         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5087                 cfg->code_size *= 2;
5088                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5089                 mono_jit_stats.code_reallocs++;
5090         }
5091
5092         /*
5093          * Keep in sync with OP_JMP
5094          */
5095         code = cfg->native_code + cfg->code_len;
5096
5097         if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5098                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5099         }
5100         pos = 0;
5101
5102         /* Load returned vtypes into registers if needed */
5103         cinfo = cfg->arch.cinfo;
5104         if (cinfo->ret.storage == RegTypeStructByVal) {
5105                 MonoInst *ins = cfg->ret;
5106
5107                 if (arm_is_imm12 (ins->inst_offset)) {
5108                         ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5109                 } else {
5110                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5111                         ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5112                 }
5113         }
5114
5115         if (method->save_lmf) {
5116                 int lmf_offset, reg, sp_adj, regmask;
5117                 /* all but r0-r3, sp and pc */
5118                 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5119                 lmf_offset = pos;
5120                 /* r2 contains the pointer to the current LMF */
5121                 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, cfg->stack_usage - lmf_offset);
5122                 /* ip = previous_lmf */
5123                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
5124                 /* lr = lmf_addr */
5125                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
5126                 /* *(lmf_addr) = previous_lmf */
5127                 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
5128                 /* This points to r4 inside MonoLMF->iregs */
5129                 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5130                 reg = ARMREG_R4;
5131                 regmask = 0x9ff0; /* restore lr to pc */
5132                 /* Skip caller saved registers not used by the method */
5133                 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5134                         regmask &= ~(1 << reg);
5135                         sp_adj += 4;
5136                         reg ++;
5137                 }
5138                 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5139                 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_R2, sp_adj);
5140                 /* restore iregs */
5141                 ARM_POP (code, regmask);
5142         } else {
5143                 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5144                         ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5145                 } else {
5146                         code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5147                         ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5148                 }
5149
5150                 if (iphone_abi) {
5151                         /* Restore saved gregs */
5152                         if (cfg->used_int_regs)
5153                                 ARM_POP (code, cfg->used_int_regs);
5154                         /* Restore saved r7, restore LR to PC */
5155                         ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5156                 } else {
5157                         ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5158                 }
5159         }
5160
5161         cfg->code_len = code - cfg->native_code;
5162
5163         g_assert (cfg->code_len < cfg->code_size);
5164
5165 }
5166
5167 /* remove once throw_exception_by_name is eliminated */
5168 static int
5169 exception_id_by_name (const char *name)
5170 {
5171         if (strcmp (name, "IndexOutOfRangeException") == 0)
5172                 return MONO_EXC_INDEX_OUT_OF_RANGE;
5173         if (strcmp (name, "OverflowException") == 0)
5174                 return MONO_EXC_OVERFLOW;
5175         if (strcmp (name, "ArithmeticException") == 0)
5176                 return MONO_EXC_ARITHMETIC;
5177         if (strcmp (name, "DivideByZeroException") == 0)
5178                 return MONO_EXC_DIVIDE_BY_ZERO;
5179         if (strcmp (name, "InvalidCastException") == 0)
5180                 return MONO_EXC_INVALID_CAST;
5181         if (strcmp (name, "NullReferenceException") == 0)
5182                 return MONO_EXC_NULL_REF;
5183         if (strcmp (name, "ArrayTypeMismatchException") == 0)
5184                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5185         if (strcmp (name, "ArgumentException") == 0)
5186                 return MONO_EXC_ARGUMENT;
5187         g_error ("Unknown intrinsic exception %s\n", name);
5188         return -1;
5189 }
5190
5191 void
5192 mono_arch_emit_exceptions (MonoCompile *cfg)
5193 {
5194         MonoJumpInfo *patch_info;
5195         int i;
5196         guint8 *code;
5197         guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5198         guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5199         int max_epilog_size = 50;
5200
5201         for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5202                 exc_throw_pos [i] = NULL;
5203                 exc_throw_found [i] = 0;
5204         }
5205
5206         /* count the number of exception infos */
5207
5208         /*
5209          * make sure we have enough space for exceptions
5210          */
5211         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5212                 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5213                         i = exception_id_by_name (patch_info->data.target);
5214                         if (!exc_throw_found [i]) {
5215                                 max_epilog_size += 32;
5216                                 exc_throw_found [i] = TRUE;
5217                         }
5218                 }
5219         }
5220
5221         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5222                 cfg->code_size *= 2;
5223                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5224                 mono_jit_stats.code_reallocs++;
5225         }
5226
5227         code = cfg->native_code + cfg->code_len;
5228
5229         /* add code to raise exceptions */
5230         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5231                 switch (patch_info->type) {
5232                 case MONO_PATCH_INFO_EXC: {
5233                         MonoClass *exc_class;
5234                         unsigned char *ip = patch_info->ip.i + cfg->native_code;
5235
5236                         i = exception_id_by_name (patch_info->data.target);
5237                         if (exc_throw_pos [i]) {
5238                                 arm_patch (ip, exc_throw_pos [i]);
5239                                 patch_info->type = MONO_PATCH_INFO_NONE;
5240                                 break;
5241                         } else {
5242                                 exc_throw_pos [i] = code;
5243                         }
5244                         arm_patch (ip, code);
5245
5246                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5247                         g_assert (exc_class);
5248
5249                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5250                         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5251                         patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5252                         patch_info->data.name = "mono_arch_throw_corlib_exception";
5253                         patch_info->ip.i = code - cfg->native_code;
5254                         ARM_BL (code, 0);
5255                         *(guint32*)(gpointer)code = exc_class->type_token;
5256                         code += 4;
5257                         break;
5258                 }
5259                 default:
5260                         /* do nothing */
5261                         break;
5262                 }
5263         }
5264
5265         cfg->code_len = code - cfg->native_code;
5266
5267         g_assert (cfg->code_len < cfg->code_size);
5268
5269 }
5270
5271 #endif /* #ifndef DISABLE_JIT */
5272
5273 static gboolean tls_offset_inited = FALSE;
5274
5275 void
5276 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5277 {
5278         if (!tls_offset_inited) {
5279                 tls_offset_inited = TRUE;
5280
5281                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5282                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5283         }
5284 }
5285
5286 void
5287 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5288 {
5289 }
5290
5291 MonoInst*
5292 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5293 {
5294         /* FIXME: */
5295         return NULL;
5296 }
5297
5298 gboolean
5299 mono_arch_print_tree (MonoInst *tree, int arity)
5300 {
5301         return 0;
5302 }
5303
5304 MonoInst*
5305 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5306 {
5307         return mono_get_domain_intrinsic (cfg);
5308 }
5309
5310 guint32
5311 mono_arch_get_patch_offset (guint8 *code)
5312 {
5313         /* OP_AOTCONST */
5314         return 8;
5315 }
5316
5317 void
5318 mono_arch_flush_register_windows (void)
5319 {
5320 }
5321
5322 #ifdef MONO_ARCH_HAVE_IMT
5323
5324 #ifndef DISABLE_JIT
5325
5326 void
5327 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5328 {
5329         if (cfg->compile_aot) {
5330                 int method_reg = mono_alloc_ireg (cfg);
5331                 MonoInst *ins;
5332
5333                 call->dynamic_imt_arg = TRUE;
5334
5335                 if (imt_arg) {
5336                         mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5337                 } else {
5338                         MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5339                         ins->dreg = method_reg;
5340                         ins->inst_p0 = call->method;
5341                         ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5342                         MONO_ADD_INS (cfg->cbb, ins);
5343
5344                         mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5345                 }
5346         } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5347
5348                 /* Always pass in a register for simplicity */
5349                 call->dynamic_imt_arg = TRUE;
5350
5351                 cfg->uses_rgctx_reg = TRUE;
5352
5353                 if (imt_arg) {
5354                         mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5355                 } else {
5356                         MonoInst *ins;
5357                         int method_reg = mono_alloc_preg (cfg);
5358
5359                         MONO_INST_NEW (cfg, ins, OP_PCONST);
5360                         ins->inst_p0 = call->method;
5361                         ins->dreg = method_reg;
5362                         MONO_ADD_INS (cfg->cbb, ins);
5363
5364                         mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5365                 }
5366         }
5367 }
5368
5369 #endif /* DISABLE_JIT */
5370
5371 MonoMethod*
5372 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5373 {
5374         guint32 *code_ptr = (guint32*)code;
5375         code_ptr -= 2;
5376
5377         if (mono_use_llvm)
5378                 /* Passed in V5 */
5379                 return (MonoMethod*)regs [ARMREG_V5];
5380
5381         /* The IMT value is stored in the code stream right after the LDC instruction. */
5382         if (!IS_LDR_PC (code_ptr [0])) {
5383                 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5384                 g_assert (IS_LDR_PC (code_ptr [0]));
5385         }
5386         if (code_ptr [1] == 0)
5387                 /* This is AOTed code, the IMT method is in V5 */
5388                 return (MonoMethod*)regs [ARMREG_V5];
5389         else
5390                 return (MonoMethod*) code_ptr [1];
5391 }
5392
5393 MonoVTable*
5394 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5395 {
5396         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5397 }
5398
5399 #define ENABLE_WRONG_METHOD_CHECK 0
5400 #define BASE_SIZE (6 * 4)
5401 #define BSEARCH_ENTRY_SIZE (4 * 4)
5402 #define CMP_SIZE (3 * 4)
5403 #define BRANCH_SIZE (1 * 4)
5404 #define CALL_SIZE (2 * 4)
5405 #define WMC_SIZE (5 * 4)
5406 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5407
5408 static arminstr_t *
5409 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5410 {
5411         guint32 delta = DISTANCE (target, code);
5412         delta -= 8;
5413         g_assert (delta >= 0 && delta <= 0xFFF);
5414         *target = *target | delta;
5415         *code = value;
5416         return code + 1;
5417 }
5418
5419 gpointer
5420 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5421         gpointer fail_tramp)
5422 {
5423         int size, i, extra_space = 0;
5424         arminstr_t *code, *start, *vtable_target = NULL;
5425         gboolean large_offsets = FALSE;
5426         guint32 **constant_pool_starts;
5427
5428         size = BASE_SIZE;
5429         constant_pool_starts = g_new0 (guint32*, count);
5430
5431         for (i = 0; i < count; ++i) {
5432                 MonoIMTCheckItem *item = imt_entries [i];
5433                 if (item->is_equals) {
5434                         gboolean fail_case = !item->check_target_idx && fail_tramp;
5435
5436                         if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5437                                 item->chunk_size += 32;
5438                                 large_offsets = TRUE;
5439                         }
5440
5441                         if (item->check_target_idx || fail_case) {
5442                                 if (!item->compare_done || fail_case)
5443                                         item->chunk_size += CMP_SIZE;
5444                                 item->chunk_size += BRANCH_SIZE;
5445                         } else {
5446 #if ENABLE_WRONG_METHOD_CHECK
5447                                 item->chunk_size += WMC_SIZE;
5448 #endif
5449                         }
5450                         if (fail_case) {
5451                                 item->chunk_size += 16;
5452                                 large_offsets = TRUE;
5453                         }
5454                         item->chunk_size += CALL_SIZE;
5455                 } else {
5456                         item->chunk_size += BSEARCH_ENTRY_SIZE;
5457                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5458                 }
5459                 size += item->chunk_size;
5460         }
5461
5462         if (large_offsets)
5463                 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5464
5465         if (fail_tramp)
5466                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5467         else
5468                 code = mono_domain_code_reserve (domain, size);
5469         start = code;
5470
5471 #if DEBUG_IMT
5472         printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5473         for (i = 0; i < count; ++i) {
5474                 MonoIMTCheckItem *item = imt_entries [i];
5475                 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5476         }
5477 #endif
5478
5479         if (large_offsets)
5480                 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5481         else
5482                 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5483         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5484         vtable_target = code;
5485         ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5486
5487         if (mono_use_llvm) {
5488                 /* LLVM always passes the IMT method in R5 */
5489                 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5490         } else {
5491                 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5492                 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5493                 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5494         }
5495
5496         for (i = 0; i < count; ++i) {
5497                 MonoIMTCheckItem *item = imt_entries [i];
5498                 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5499                 gint32 vtable_offset;
5500
5501                 item->code_target = (guint8*)code;
5502
5503                 if (item->is_equals) {
5504                         gboolean fail_case = !item->check_target_idx && fail_tramp;
5505
5506                         if (item->check_target_idx || fail_case) {
5507                                 if (!item->compare_done || fail_case) {
5508                                         imt_method = code;
5509                                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5510                                         ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5511                                 }
5512                                 item->jmp_code = (guint8*)code;
5513                                 ARM_B_COND (code, ARMCOND_NE, 0);
5514                         } else {
5515                                 /*Enable the commented code to assert on wrong method*/
5516 #if ENABLE_WRONG_METHOD_CHECK
5517                                 imt_method = code;
5518                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5519                                 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5520                                 ARM_B_COND (code, ARMCOND_NE, 1);
5521
5522                                 ARM_DBRK (code);
5523 #endif
5524                         }
5525
5526                         if (item->has_target_code) {
5527                                 target_code_ins = code;
5528                                 /* Load target address */
5529                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5530                                 /* Save it to the fourth slot */
5531                                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5532                                 /* Restore registers and branch */
5533                                 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5534
5535                                 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5536                         } else {
5537                                 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5538                                 if (!arm_is_imm12 (vtable_offset)) {
5539                                         /*
5540                                          * We need to branch to a computed address but we don't have
5541                                          * a free register to store it, since IP must contain the
5542                                          * vtable address. So we push the two values to the stack, and
5543                                          * load them both using LDM.
5544                                          */
5545                                         /* Compute target address */
5546                                         vtable_offset_ins = code;
5547                                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5548                                         ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5549                                         /* Save it to the fourth slot */
5550                                         ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5551                                         /* Restore registers and branch */
5552                                         ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5553
5554                                         code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5555                                 } else {
5556                                         ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5557                                         if (large_offsets)
5558                                                 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5559                                         ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5560                                 }
5561                         }
5562
5563                         if (fail_case) {
5564                                 arm_patch (item->jmp_code, (guchar*)code);
5565
5566                                 target_code_ins = code;
5567                                 /* Load target address */
5568                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5569                                 /* Save it to the fourth slot */
5570                                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5571                                 /* Restore registers and branch */
5572                                 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5573
5574                                 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5575                                 item->jmp_code = NULL;
5576                         }
5577
5578                         if (imt_method)
5579                                 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5580
5581                         /*must emit after unconditional branch*/
5582                         if (vtable_target) {
5583                                 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5584                                 item->chunk_size += 4;
5585                                 vtable_target = NULL;
5586                         }
5587
5588                         /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5589                         constant_pool_starts [i] = code;
5590                         if (extra_space) {
5591                                 code += extra_space;
5592                                 extra_space = 0;
5593                         }
5594                 } else {
5595                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5596                         ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5597
5598                         item->jmp_code = (guint8*)code;
5599                         ARM_B_COND (code, ARMCOND_GE, 0);
5600                         ++extra_space;
5601                 }
5602         }
5603
5604         for (i = 0; i < count; ++i) {
5605                 MonoIMTCheckItem *item = imt_entries [i];
5606                 if (item->jmp_code) {
5607                         if (item->check_target_idx)
5608                                 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5609                 }
5610                 if (i > 0 && item->is_equals) {
5611                         int j;
5612                         arminstr_t *space_start = constant_pool_starts [i];
5613                         for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5614                                 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5615                         }
5616                 }
5617         }
5618
5619 #if DEBUG_IMT
5620         {
5621                 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5622                 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5623                 g_free (buff);
5624         }
5625 #endif
5626
5627         g_free (constant_pool_starts);
5628
5629         mono_arch_flush_icache ((guint8*)start, size);
5630         mono_stats.imt_thunks_size += code - start;
5631
5632         g_assert (DISTANCE (start, code) <= size);
5633         return start;
5634 }
5635
5636 #endif
5637
5638 gpointer
5639 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5640 {
5641         if (reg == ARMREG_SP)
5642                 return (gpointer)ctx->esp;
5643         else
5644                 return (gpointer)ctx->regs [reg];
5645 }
5646
5647 /*
5648  * mono_arch_get_trampolines:
5649  *
5650  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
5651  * for AOT.
5652  */
5653 GSList *
5654 mono_arch_get_trampolines (gboolean aot)
5655 {
5656         return mono_arm_get_exception_trampolines (aot);
5657 }
5658
5659 /*
5660  * mono_arch_set_breakpoint:
5661  *
5662  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
5663  * The location should contain code emitted by OP_SEQ_POINT.
5664  */
5665 void
5666 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5667 {
5668         guint8 *code = ip;
5669         guint32 native_offset = ip - (guint8*)ji->code_start;
5670
5671         if (ji->from_aot) {
5672                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5673
5674                 g_assert (native_offset % 4 == 0);
5675                 g_assert (info->bp_addrs [native_offset / 4] == 0);
5676                 info->bp_addrs [native_offset / 4] = bp_trigger_page;
5677         } else {
5678                 int dreg = ARMREG_LR;
5679
5680                 /* Read from another trigger page */
5681                 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
5682                 ARM_B (code, 0);
5683                 *(int*)code = (int)bp_trigger_page;
5684                 code += 4;
5685                 ARM_LDR_IMM (code, dreg, dreg, 0);
5686
5687                 mono_arch_flush_icache (code - 16, 16);
5688
5689 #if 0
5690                 /* This is currently implemented by emitting an SWI instruction, which
5691                  * qemu/linux seems to convert to a SIGILL.
5692                  */
5693                 *(int*)code = (0xef << 24) | 8;
5694                 code += 4;
5695                 mono_arch_flush_icache (code - 4, 4);
5696 #endif
5697         }
5698 }
5699
5700 /*
5701  * mono_arch_clear_breakpoint:
5702  *
5703  *   Clear the breakpoint at IP.
5704  */
5705 void
5706 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5707 {
5708         guint8 *code = ip;
5709         int i;
5710
5711         if (ji->from_aot) {
5712                 guint32 native_offset = ip - (guint8*)ji->code_start;
5713                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5714
5715                 g_assert (native_offset % 4 == 0);
5716                 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
5717                 info->bp_addrs [native_offset / 4] = 0;
5718         } else {
5719                 for (i = 0; i < 4; ++i)
5720                         ARM_NOP (code);
5721
5722                 mono_arch_flush_icache (ip, code - ip);
5723         }
5724 }
5725
5726 /*
5727  * mono_arch_start_single_stepping:
5728  *
5729  *   Start single stepping.
5730  */
5731 void
5732 mono_arch_start_single_stepping (void)
5733 {
5734         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
5735 }
5736
5737 /*
5738  * mono_arch_stop_single_stepping:
5739  *
5740  *   Stop single stepping.
5741  */
5742 void
5743 mono_arch_stop_single_stepping (void)
5744 {
5745         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
5746 }
5747
5748 #if __APPLE__
5749 #define DBG_SIGNAL SIGBUS
5750 #else
5751 #define DBG_SIGNAL SIGSEGV
5752 #endif
5753
5754 /*
5755  * mono_arch_is_single_step_event:
5756  *
5757  *   Return whenever the machine state in SIGCTX corresponds to a single
5758  * step event.
5759  */
5760 gboolean
5761 mono_arch_is_single_step_event (void *info, void *sigctx)
5762 {
5763         siginfo_t *sinfo = info;
5764
5765         /* Sometimes the address is off by 4 */
5766         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
5767                 return TRUE;
5768         else
5769                 return FALSE;
5770 }
5771
5772 /*
5773  * mono_arch_is_breakpoint_event:
5774  *
5775  *   Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
5776  */
5777 gboolean
5778 mono_arch_is_breakpoint_event (void *info, void *sigctx)
5779 {
5780         siginfo_t *sinfo = info;
5781
5782         if (sinfo->si_signo == DBG_SIGNAL) {
5783                 /* Sometimes the address is off by 4 */
5784                 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
5785                         return TRUE;
5786                 else
5787                         return FALSE;
5788         } else {
5789                 return FALSE;
5790         }
5791 }
5792
5793 guint8*
5794 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
5795 {
5796         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
5797
5798         if (ji->from_aot)
5799                 ip -= 6 * 4;
5800         else
5801                 ip -= 12;
5802
5803         return ip;
5804 }
5805
5806 guint8*
5807 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
5808 {
5809         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
5810
5811         ip += 4;
5812
5813         return ip;
5814 }
5815
5816 /*
5817  * mono_arch_skip_breakpoint:
5818  *
5819  *   See mini-amd64.c for docs.
5820  */
5821 void
5822 mono_arch_skip_breakpoint (MonoContext *ctx)
5823 {
5824         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
5825 }
5826
5827 /*
5828  * mono_arch_skip_single_step:
5829  *
5830  *   See mini-amd64.c for docs.
5831  */
5832 void
5833 mono_arch_skip_single_step (MonoContext *ctx)
5834 {
5835         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
5836 }
5837
5838 /*
5839  * mono_arch_get_seq_point_info:
5840  *
5841  *   See mini-amd64.c for docs.
5842  */
5843 gpointer
5844 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
5845 {
5846         SeqPointInfo *info;
5847         MonoJitInfo *ji;
5848
5849         // FIXME: Add a free function
5850
5851         mono_domain_lock (domain);
5852         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
5853                                                                 code);
5854         mono_domain_unlock (domain);
5855
5856         if (!info) {
5857                 ji = mono_jit_info_table_find (domain, (char*)code);
5858                 g_assert (ji);
5859
5860                 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
5861
5862                 info->ss_trigger_page = ss_trigger_page;
5863                 info->bp_trigger_page = bp_trigger_page;
5864
5865                 mono_domain_lock (domain);
5866                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
5867                                                          code, info);
5868                 mono_domain_unlock (domain);
5869         }
5870
5871         return info;
5872 }
5873
5874 /*
5875  * mono_arch_set_target:
5876  *
5877  *   Set the target architecture the JIT backend should generate code for, in the form
5878  * of a GNU target triplet. Only used in AOT mode.
5879  */
5880 void
5881 mono_arch_set_target (char *mtriple)
5882 {
5883         /* The GNU target triple format is not very well documented */
5884         if (strstr (mtriple, "armv7")) {
5885                 v6_supported = TRUE;
5886                 v7_supported = TRUE;
5887         }
5888         if (strstr (mtriple, "armv6")) {
5889                 v6_supported = TRUE;
5890         }
5891         if (strstr (mtriple, "darwin")) {
5892                 v5_supported = TRUE;
5893                 thumb_supported = TRUE;
5894                 darwin = TRUE;
5895                 iphone_abi = TRUE;
5896         }
5897         if (strstr (mtriple, "gnueabi"))
5898                 eabi_supported = TRUE;
5899 }
5900