3 * ARM backend for the Mono code generator
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
11 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
12 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
17 #include <mono/metadata/abi-details.h>
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/profiler-private.h>
20 #include <mono/metadata/debug-helpers.h>
21 #include <mono/utils/mono-mmap.h>
22 #include <mono/utils/mono-hwcap.h>
23 #include <mono/utils/mono-memory-model.h>
24 #include <mono/utils/mono-threads-coop.h>
30 #include "debugger-agent.h"
32 #include "mono/arch/arm/arm-vfp-codegen.h"
34 /* Sanity check: This makes no sense */
35 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
36 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
40 * IS_SOFT_FLOAT: Is full software floating point used?
41 * IS_HARD_FLOAT: Is full hardware floating point used?
42 * IS_VFP: Is hardware floating point with software ABI used?
44 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
45 * IS_VFP may delegate to mono_arch_is_soft_float ().
48 #if defined(ARM_FPU_VFP_HARD)
49 #define IS_SOFT_FLOAT (FALSE)
50 #define IS_HARD_FLOAT (TRUE)
52 #elif defined(ARM_FPU_NONE)
53 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
54 #define IS_HARD_FLOAT (FALSE)
55 #define IS_VFP (!mono_arch_is_soft_float ())
57 #define IS_SOFT_FLOAT (FALSE)
58 #define IS_HARD_FLOAT (FALSE)
62 #define THUNK_SIZE (3 * 4)
64 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
67 void sys_icache_invalidate (void *start, size_t len);
70 /* This mutex protects architecture specific caches */
71 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
72 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
73 static mono_mutex_t mini_arch_mutex;
75 static gboolean v5_supported = FALSE;
76 static gboolean v6_supported = FALSE;
77 static gboolean v7_supported = FALSE;
78 static gboolean v7s_supported = FALSE;
79 static gboolean v7k_supported = FALSE;
80 static gboolean thumb_supported = FALSE;
81 static gboolean thumb2_supported = FALSE;
83 * Whenever to use the ARM EABI
85 static gboolean eabi_supported = FALSE;
88 * Whenever to use the iphone ABI extensions:
89 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
90 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
91 * This is required for debugging/profiling tools to work, but it has some overhead so it should
92 * only be turned on in debug builds.
94 static gboolean iphone_abi = FALSE;
97 * The FPU we are generating code for. This is NOT runtime configurable right now,
98 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
100 static MonoArmFPU arm_fpu;
102 #if defined(ARM_FPU_VFP_HARD)
104 * On armhf, d0-d7 are used for argument passing and d8-d15
105 * must be preserved across calls, which leaves us no room
106 * for scratch registers. So we use d14-d15 but back up their
107 * previous contents to a stack slot before using them - see
108 * mono_arm_emit_vfp_scratch_save/_restore ().
110 static int vfp_scratch1 = ARM_VFP_D14;
111 static int vfp_scratch2 = ARM_VFP_D15;
114 * On armel, d0-d7 do not need to be preserved, so we can
115 * freely make use of them as scratch registers.
117 static int vfp_scratch1 = ARM_VFP_D0;
118 static int vfp_scratch2 = ARM_VFP_D1;
123 static gpointer single_step_tramp, breakpoint_tramp;
124 static gpointer get_tls_tramp;
127 * The code generated for sequence points reads from this location, which is
128 * made read-only when single stepping is enabled.
130 static gpointer ss_trigger_page;
132 /* Enabled breakpoints read from this trigger page */
133 static gpointer bp_trigger_page;
137 * floating point support: on ARM it is a mess, there are at least 3
138 * different setups, each of which binary incompat with the other.
139 * 1) FPA: old and ugly, but unfortunately what current distros use
140 * the double binary format has the two words swapped. 8 double registers.
141 * Implemented usually by kernel emulation.
142 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
143 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
144 * 3) VFP: the new and actually sensible and useful FP support. Implemented
145 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
147 * We do not care about FPA. We will support soft float and VFP.
149 int mono_exc_esp_offset = 0;
151 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
152 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
153 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
155 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
156 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
157 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
159 //#define DEBUG_IMT 0
162 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
166 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data);
169 mono_arch_regname (int reg)
171 static const char * rnames[] = {
172 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
173 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
174 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
177 if (reg >= 0 && reg < 16)
183 mono_arch_fregname (int reg)
185 static const char * rnames[] = {
186 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
187 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
188 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
189 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
190 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
191 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
194 if (reg >= 0 && reg < 32)
202 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
204 int imm8, rot_amount;
205 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
206 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
210 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
211 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
213 code = mono_arm_emit_load_imm (code, dreg, imm);
214 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
219 /* If dreg == sreg, this clobbers IP */
221 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
223 int imm8, rot_amount;
224 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
225 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
229 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
230 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
232 code = mono_arm_emit_load_imm (code, dreg, imm);
233 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
239 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
241 /* we can use r0-r3, since this is called only for incoming args on the stack */
242 if (size > sizeof (gpointer) * 4) {
244 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
245 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
246 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
247 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
248 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
249 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
250 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
251 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
252 ARM_B_COND (code, ARMCOND_NE, 0);
253 arm_patch (code - 4, start_loop);
256 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
257 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
259 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
260 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
266 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
267 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
268 doffset = soffset = 0;
270 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
271 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
277 g_assert (size == 0);
282 emit_call_reg (guint8 *code, int reg)
285 ARM_BLX_REG (code, reg);
287 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
291 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
297 emit_call_seq (MonoCompile *cfg, guint8 *code)
299 if (cfg->method->dynamic) {
300 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
302 *(gpointer*)code = NULL;
304 code = emit_call_reg (code, ARMREG_IP);
308 cfg->thunk_area += THUNK_SIZE;
313 mono_arm_patchable_b (guint8 *code, int cond)
315 ARM_B_COND (code, cond, 0);
320 mono_arm_patchable_bl (guint8 *code, int cond)
322 ARM_BL_COND (code, cond, 0);
326 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(__native_client__)
327 #define HAVE_AEABI_READ_TP 1
330 #ifdef HAVE_AEABI_READ_TP
331 gpointer __aeabi_read_tp (void);
335 mono_arch_have_fast_tls (void)
337 #ifdef HAVE_AEABI_READ_TP
338 static gboolean have_fast_tls = FALSE;
339 static gboolean inited = FALSE;
342 if (mini_get_debug_options ()->use_fallback_tls)
346 return have_fast_tls;
348 tp1 = __aeabi_read_tp ();
349 asm volatile("mrc p15, 0, %0, c13, c0, 3" : "=r" (tp2));
351 have_fast_tls = tp1 && tp1 == tp2;
353 return have_fast_tls;
360 emit_tls_get (guint8 *code, int dreg, int tls_offset)
362 ARM_MRC (code, 15, 0, dreg, 13, 0, 3);
363 ARM_LDR_IMM (code, dreg, dreg, tls_offset);
368 emit_tls_set (guint8 *code, int sreg, int tls_offset)
370 int tp_reg = (sreg != ARMREG_R0) ? ARMREG_R0 : ARMREG_R1;
371 ARM_MRC (code, 15, 0, tp_reg, 13, 0, 3);
372 ARM_STR_IMM (code, sreg, tp_reg, tls_offset);
379 * Emit code to push an LMF structure on the LMF stack.
380 * On arm, this is intermixed with the initialization of other fields of the structure.
383 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
387 if (mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR) != -1) {
388 code = emit_tls_get (code, ARMREG_R0, mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR));
390 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
391 (gpointer)"mono_tls_get_lmf_addr");
392 code = emit_call_seq (cfg, code);
394 /* we build the MonoLMF structure on the stack - see mini-arm.h */
395 /* lmf_offset is the offset from the previous stack pointer,
396 * alloc_size is the total stack space allocated, so the offset
397 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
398 * The pointer to the struct is put in r1 (new_lmf).
399 * ip is used as scratch
400 * The callee-saved registers are already in the MonoLMF structure
402 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
403 /* r0 is the result from mono_get_lmf_addr () */
404 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
405 /* new_lmf->previous_lmf = *lmf_addr */
406 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
407 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
408 /* *(lmf_addr) = r1 */
409 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
410 /* Skip method (only needed for trampoline LMF frames) */
411 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
412 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
413 /* save the current IP */
414 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
415 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
417 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
418 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
429 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
433 for (list = inst->float_args; list; list = list->next) {
434 FloatArgData *fad = list->data;
435 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
436 gboolean imm = arm_is_fpimm8 (var->inst_offset);
438 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
444 if (*offset + *max_len > cfg->code_size) {
445 cfg->code_size += *max_len;
446 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
448 code = cfg->native_code + *offset;
452 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
453 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
455 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
457 *offset = code - cfg->native_code;
464 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
468 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
470 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
473 if (!arm_is_fpimm8 (inst->inst_offset)) {
474 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
475 ARM_FSTD (code, reg, ARMREG_LR, 0);
477 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
484 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
488 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
490 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
493 if (!arm_is_fpimm8 (inst->inst_offset)) {
494 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
495 ARM_FLDD (code, reg, ARMREG_LR, 0);
497 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
506 * Emit code to pop an LMF structure from the LMF stack.
509 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
513 if (lmf_offset < 32) {
514 basereg = cfg->frame_reg;
519 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
522 /* ip = previous_lmf */
523 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
525 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
526 /* *(lmf_addr) = previous_lmf */
527 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
532 #endif /* #ifndef DISABLE_JIT */
535 * mono_arch_get_argument_info:
536 * @csig: a method signature
537 * @param_count: the number of parameters to consider
538 * @arg_info: an array to store the result infos
540 * Gathers information on parameters such as size, alignment and
541 * padding. arg_info should be large enought to hold param_count + 1 entries.
543 * Returns the size of the activation frame.
546 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
548 int k, frame_size = 0;
549 guint32 size, align, pad;
553 t = mini_get_underlying_type (csig->ret);
554 if (MONO_TYPE_ISSTRUCT (t)) {
555 frame_size += sizeof (gpointer);
559 arg_info [0].offset = offset;
562 frame_size += sizeof (gpointer);
566 arg_info [0].size = frame_size;
568 for (k = 0; k < param_count; k++) {
569 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
571 /* ignore alignment for now */
574 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
575 arg_info [k].pad = pad;
577 arg_info [k + 1].pad = 0;
578 arg_info [k + 1].size = size;
580 arg_info [k + 1].offset = offset;
584 align = MONO_ARCH_FRAME_ALIGNMENT;
585 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
586 arg_info [k].pad = pad;
591 #define MAX_ARCH_DELEGATE_PARAMS 3
594 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
596 guint8 *code, *start;
597 GSList *unwind_ops = mono_arch_get_cie_program ();
600 start = code = mono_global_codeman_reserve (12);
602 /* Replace the this argument with the target */
603 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
604 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
605 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
607 g_assert ((code - start) <= 12);
609 mono_arch_flush_icache (start, 12);
613 size = 8 + param_count * 4;
614 start = code = mono_global_codeman_reserve (size);
616 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
617 /* slide down the arguments */
618 for (i = 0; i < param_count; ++i) {
619 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
621 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
623 g_assert ((code - start) <= size);
625 mono_arch_flush_icache (start, size);
629 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
631 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
632 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
636 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
642 * mono_arch_get_delegate_invoke_impls:
644 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
648 mono_arch_get_delegate_invoke_impls (void)
654 get_delegate_invoke_impl (&info, TRUE, 0);
655 res = g_slist_prepend (res, info);
657 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
658 get_delegate_invoke_impl (&info, FALSE, i);
659 res = g_slist_prepend (res, info);
666 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
668 guint8 *code, *start;
671 /* FIXME: Support more cases */
672 sig_ret = mini_get_underlying_type (sig->ret);
673 if (MONO_TYPE_ISSTRUCT (sig_ret))
677 static guint8* cached = NULL;
678 mono_mini_arch_lock ();
680 mono_mini_arch_unlock ();
685 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
688 start = get_delegate_invoke_impl (&info, TRUE, 0);
689 mono_tramp_info_register (info, NULL);
692 mono_mini_arch_unlock ();
695 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
698 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
700 for (i = 0; i < sig->param_count; ++i)
701 if (!mono_is_regsize_var (sig->params [i]))
704 mono_mini_arch_lock ();
705 code = cache [sig->param_count];
707 mono_mini_arch_unlock ();
712 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
713 start = mono_aot_get_trampoline (name);
717 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
718 mono_tramp_info_register (info, NULL);
720 cache [sig->param_count] = start;
721 mono_mini_arch_unlock ();
729 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
735 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
737 return (gpointer)regs [ARMREG_R0];
741 * Initialize the cpu to execute managed code.
744 mono_arch_cpu_init (void)
746 i8_align = MONO_ABI_ALIGNOF (gint64);
747 #ifdef MONO_CROSS_COMPILE
748 /* Need to set the alignment of i8 since it can different on the target */
749 #ifdef TARGET_ANDROID
751 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
757 * Initialize architecture specific code.
760 mono_arch_init (void)
762 const char *cpu_arch;
764 #ifdef TARGET_WATCHOS
765 mini_get_debug_options ()->soft_breakpoints = TRUE;
768 mono_os_mutex_init_recursive (&mini_arch_mutex);
769 if (mini_get_debug_options ()->soft_breakpoints) {
771 breakpoint_tramp = mini_get_breakpoint_trampoline ();
773 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
774 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
775 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
778 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
779 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
780 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
781 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
782 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
784 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
785 mono_aot_register_jit_icall ("mono_arm_handler_block_trampoline_helper", mono_arm_handler_block_trampoline_helper);
786 #if defined(__ARM_EABI__)
787 eabi_supported = TRUE;
790 #if defined(ARM_FPU_VFP_HARD)
791 arm_fpu = MONO_ARM_FPU_VFP_HARD;
793 arm_fpu = MONO_ARM_FPU_VFP;
795 #if defined(ARM_FPU_NONE) && !defined(TARGET_IOS)
797 * If we're compiling with a soft float fallback and it
798 * turns out that no VFP unit is available, we need to
799 * switch to soft float. We don't do this for iOS, since
800 * iOS devices always have a VFP unit.
802 if (!mono_hwcap_arm_has_vfp)
803 arm_fpu = MONO_ARM_FPU_NONE;
806 * This environment variable can be useful in testing
807 * environments to make sure the soft float fallback
808 * works. Most ARM devices have VFP units these days, so
809 * normally soft float code would not be exercised much.
811 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
813 if (soft && !strncmp (soft, "1", 1))
814 arm_fpu = MONO_ARM_FPU_NONE;
819 v5_supported = mono_hwcap_arm_is_v5;
820 v6_supported = mono_hwcap_arm_is_v6;
821 v7_supported = mono_hwcap_arm_is_v7;
824 * On weird devices, the hwcap code may fail to detect
825 * the ARM version. In that case, we can at least safely
826 * assume the version the runtime was compiled for.
838 #if defined(TARGET_IOS)
839 /* iOS is special-cased here because we don't yet
840 have a way to properly detect CPU features on it. */
841 thumb_supported = TRUE;
844 thumb_supported = mono_hwcap_arm_has_thumb;
845 thumb2_supported = mono_hwcap_arm_has_thumb2;
848 /* Format: armv(5|6|7[s])[-thumb[2]] */
849 cpu_arch = g_getenv ("MONO_CPU_ARCH");
851 /* Do this here so it overrides any detection. */
853 if (strncmp (cpu_arch, "armv", 4) == 0) {
854 v5_supported = cpu_arch [4] >= '5';
855 v6_supported = cpu_arch [4] >= '6';
856 v7_supported = cpu_arch [4] >= '7';
857 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
858 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
861 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
862 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
868 * Cleanup architecture specific code.
871 mono_arch_cleanup (void)
876 * This function returns the optimizations supported on this cpu.
879 mono_arch_cpu_optimizations (guint32 *exclude_mask)
881 /* no arm-specific optimizations yet */
887 * This function test for all SIMD functions supported.
889 * Returns a bitmask corresponding to all supported versions.
893 mono_arch_cpu_enumerate_simd_versions (void)
895 /* SIMD is currently unimplemented */
900 mono_arm_is_hard_float (void)
902 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
908 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
910 if (v7s_supported || v7k_supported) {
924 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
926 mono_arch_is_soft_float (void)
928 return arm_fpu == MONO_ARM_FPU_NONE;
933 is_regsize_var (MonoType *t)
937 t = mini_get_underlying_type (t);
944 case MONO_TYPE_FNPTR:
946 case MONO_TYPE_OBJECT:
948 case MONO_TYPE_GENERICINST:
949 if (!mono_type_generic_inst_is_valuetype (t))
952 case MONO_TYPE_VALUETYPE:
959 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
964 for (i = 0; i < cfg->num_varinfo; i++) {
965 MonoInst *ins = cfg->varinfo [i];
966 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
969 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
972 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
975 /* we can only allocate 32 bit values */
976 if (is_regsize_var (ins->inst_vtype)) {
977 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
978 g_assert (i == vmv->idx);
979 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
987 mono_arch_get_global_int_regs (MonoCompile *cfg)
991 mono_arch_compute_omit_fp (cfg);
994 * FIXME: Interface calls might go through a static rgctx trampoline which
995 * sets V5, but it doesn't save it, so we need to save it ourselves, and
998 if (cfg->flags & MONO_CFG_HAS_CALLS)
999 cfg->uses_rgctx_reg = TRUE;
1001 if (cfg->arch.omit_fp)
1002 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1003 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1004 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1005 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1007 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1008 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1010 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1011 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1012 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1013 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1014 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1015 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1021 * mono_arch_regalloc_cost:
1023 * Return the cost, in number of memory references, of the action of
1024 * allocating the variable VMV into a register during global register
1028 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1034 #endif /* #ifndef DISABLE_JIT */
1037 mono_arch_flush_icache (guint8 *code, gint size)
1039 #if defined(MONO_CROSS_COMPILE)
1041 sys_icache_invalidate (code, size);
1043 __builtin___clear_cache (code, code + size);
1050 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1053 if (*gr > ARMREG_R3) {
1055 ainfo->offset = *stack_size;
1056 ainfo->reg = ARMREG_SP; /* in the caller */
1057 ainfo->storage = RegTypeBase;
1060 ainfo->storage = RegTypeGeneral;
1067 split = i8_align == 4;
1072 if (*gr == ARMREG_R3 && split) {
1073 /* first word in r3 and the second on the stack */
1074 ainfo->offset = *stack_size;
1075 ainfo->reg = ARMREG_SP; /* in the caller */
1076 ainfo->storage = RegTypeBaseGen;
1078 } else if (*gr >= ARMREG_R3) {
1079 if (eabi_supported) {
1080 /* darwin aligns longs to 4 byte only */
1081 if (i8_align == 8) {
1086 ainfo->offset = *stack_size;
1087 ainfo->reg = ARMREG_SP; /* in the caller */
1088 ainfo->storage = RegTypeBase;
1091 if (eabi_supported) {
1092 if (i8_align == 8 && ((*gr) & 1))
1095 ainfo->storage = RegTypeIRegPair;
1104 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1107 * If we're calling a function like this:
1109 * void foo(float a, double b, float c)
1111 * We pass a in s0 and b in d1. That leaves us
1112 * with s1 being unused. The armhf ABI recognizes
1113 * this and requires register assignment to then
1114 * use that for the next single-precision arg,
1115 * i.e. c in this example. So float_spare either
1116 * tells us which reg to use for the next single-
1117 * precision arg, or it's -1, meaning use *fpr.
1119 * Note that even though most of the JIT speaks
1120 * double-precision, fpr represents single-
1121 * precision registers.
1123 * See parts 5.5 and 6.1.2 of the AAPCS for how
1127 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1128 ainfo->storage = RegTypeFP;
1132 * If we're passing a double-precision value
1133 * and *fpr is odd (e.g. it's s1, s3, ...)
1134 * we need to use the next even register. So
1135 * we mark the current *fpr as a spare that
1136 * can be used for the next single-precision
1140 *float_spare = *fpr;
1145 * At this point, we have an even register
1146 * so we assign that and move along.
1150 } else if (*float_spare >= 0) {
1152 * We're passing a single-precision value
1153 * and it looks like a spare single-
1154 * precision register is available. Let's
1158 ainfo->reg = *float_spare;
1162 * If we hit this branch, we're passing a
1163 * single-precision value and we can simply
1164 * use the next available register.
1172 * We've exhausted available floating point
1173 * regs, so pass the rest on the stack.
1181 ainfo->offset = *stack_size;
1182 ainfo->reg = ARMREG_SP;
1183 ainfo->storage = RegTypeBase;
1190 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1194 MonoClassField *field;
1195 MonoType *ftype, *prev_ftype = NULL;
1198 klass = mono_class_from_mono_type (t);
1200 while ((field = mono_class_get_fields (klass, &iter))) {
1201 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1203 ftype = mono_field_get_type (field);
1204 ftype = mini_get_underlying_type (ftype);
1206 if (MONO_TYPE_ISSTRUCT (ftype)) {
1207 int nested_nfields, nested_esize;
1209 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1211 if (nested_esize == 4)
1212 ftype = &mono_defaults.single_class->byval_arg;
1214 ftype = &mono_defaults.double_class->byval_arg;
1215 if (prev_ftype && prev_ftype->type != ftype->type)
1218 nfields += nested_nfields;
1220 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1222 if (prev_ftype && prev_ftype->type != ftype->type)
1228 if (nfields == 0 || nfields > 4)
1230 *out_nfields = nfields;
1231 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1236 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1238 guint i, gr, fpr, pstart;
1240 int n = sig->hasthis + sig->param_count;
1244 guint32 stack_size = 0;
1246 gboolean is_pinvoke = sig->pinvoke;
1247 gboolean vtype_retaddr = FALSE;
1250 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1252 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1259 t = mini_get_underlying_type (sig->ret);
1270 case MONO_TYPE_FNPTR:
1271 case MONO_TYPE_OBJECT:
1272 cinfo->ret.storage = RegTypeGeneral;
1273 cinfo->ret.reg = ARMREG_R0;
1277 cinfo->ret.storage = RegTypeIRegPair;
1278 cinfo->ret.reg = ARMREG_R0;
1282 cinfo->ret.storage = RegTypeFP;
1284 if (t->type == MONO_TYPE_R4)
1285 cinfo->ret.size = 4;
1287 cinfo->ret.size = 8;
1289 if (IS_HARD_FLOAT) {
1290 cinfo->ret.reg = ARM_VFP_F0;
1292 cinfo->ret.reg = ARMREG_R0;
1295 case MONO_TYPE_GENERICINST:
1296 if (!mono_type_generic_inst_is_valuetype (t)) {
1297 cinfo->ret.storage = RegTypeGeneral;
1298 cinfo->ret.reg = ARMREG_R0;
1301 if (mini_is_gsharedvt_variable_type (t)) {
1302 cinfo->ret.storage = RegTypeStructByAddr;
1306 case MONO_TYPE_VALUETYPE:
1307 case MONO_TYPE_TYPEDBYREF:
1308 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1309 cinfo->ret.storage = RegTypeHFA;
1311 cinfo->ret.nregs = nfields;
1312 cinfo->ret.esize = esize;
1315 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1318 #ifdef TARGET_WATCHOS
1323 if (native_size <= max_size) {
1324 cinfo->ret.storage = RegTypeStructByVal;
1325 cinfo->ret.struct_size = native_size;
1326 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1328 cinfo->ret.storage = RegTypeStructByAddr;
1331 cinfo->ret.storage = RegTypeStructByAddr;
1336 case MONO_TYPE_MVAR:
1337 g_assert (mini_is_gsharedvt_type (t));
1338 cinfo->ret.storage = RegTypeStructByAddr;
1340 case MONO_TYPE_VOID:
1343 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1346 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1351 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1352 * the first argument, allowing 'this' to be always passed in the first arg reg.
1353 * Also do this if the first argument is a reference type, since virtual calls
1354 * are sometimes made using calli without sig->hasthis set, like in the delegate
1357 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1359 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1361 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1365 cinfo->ret.reg = gr;
1367 cinfo->vret_arg_index = 1;
1371 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1374 if (vtype_retaddr) {
1375 cinfo->ret.reg = gr;
1380 DEBUG(g_print("params: %d\n", sig->param_count));
1381 for (i = pstart; i < sig->param_count; ++i) {
1382 ArgInfo *ainfo = &cinfo->args [n];
1384 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1385 /* Prevent implicit arguments and sig_cookie from
1386 being passed in registers */
1389 /* Emit the signature cookie just before the implicit arguments */
1390 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1392 DEBUG(g_print("param %d: ", i));
1393 if (sig->params [i]->byref) {
1394 DEBUG(g_print("byref\n"));
1395 add_general (&gr, &stack_size, ainfo, TRUE);
1399 t = mini_get_underlying_type (sig->params [i]);
1403 cinfo->args [n].size = 1;
1404 add_general (&gr, &stack_size, ainfo, TRUE);
1408 cinfo->args [n].size = 2;
1409 add_general (&gr, &stack_size, ainfo, TRUE);
1413 cinfo->args [n].size = 4;
1414 add_general (&gr, &stack_size, ainfo, TRUE);
1419 case MONO_TYPE_FNPTR:
1420 case MONO_TYPE_OBJECT:
1421 cinfo->args [n].size = sizeof (gpointer);
1422 add_general (&gr, &stack_size, ainfo, TRUE);
1424 case MONO_TYPE_GENERICINST:
1425 if (!mono_type_generic_inst_is_valuetype (t)) {
1426 cinfo->args [n].size = sizeof (gpointer);
1427 add_general (&gr, &stack_size, ainfo, TRUE);
1430 if (mini_is_gsharedvt_variable_type (t)) {
1431 /* gsharedvt arguments are passed by ref */
1432 g_assert (mini_is_gsharedvt_type (t));
1433 add_general (&gr, &stack_size, ainfo, TRUE);
1434 switch (ainfo->storage) {
1435 case RegTypeGeneral:
1436 ainfo->storage = RegTypeGSharedVtInReg;
1439 ainfo->storage = RegTypeGSharedVtOnStack;
1442 g_assert_not_reached ();
1447 case MONO_TYPE_TYPEDBYREF:
1448 case MONO_TYPE_VALUETYPE: {
1451 int nwords, nfields, esize;
1454 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1455 if (fpr + nfields < ARM_VFP_F16) {
1456 ainfo->storage = RegTypeHFA;
1458 ainfo->nregs = nfields;
1459 ainfo->esize = esize;
1470 if (t->type == MONO_TYPE_TYPEDBYREF) {
1471 size = sizeof (MonoTypedRef);
1472 align = sizeof (gpointer);
1474 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1476 size = mono_class_native_size (klass, &align);
1478 size = mini_type_stack_size_full (t, &align, FALSE);
1480 DEBUG(g_print ("load %d bytes struct\n", size));
1482 #ifdef TARGET_WATCHOS
1483 /* Watchos pass large structures by ref */
1484 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1485 if (sig->pinvoke && size > 16) {
1486 add_general (&gr, &stack_size, ainfo, TRUE);
1487 switch (ainfo->storage) {
1488 case RegTypeGeneral:
1489 ainfo->storage = RegTypeStructByAddr;
1492 ainfo->storage = RegTypeStructByAddrOnStack;
1495 g_assert_not_reached ();
1504 align_size += (sizeof (gpointer) - 1);
1505 align_size &= ~(sizeof (gpointer) - 1);
1506 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1507 ainfo->storage = RegTypeStructByVal;
1508 ainfo->struct_size = size;
1509 ainfo->align = align;
1510 /* FIXME: align stack_size if needed */
1511 if (eabi_supported) {
1512 if (align >= 8 && (gr & 1))
1515 if (gr > ARMREG_R3) {
1517 ainfo->vtsize = nwords;
1519 int rest = ARMREG_R3 - gr + 1;
1520 int n_in_regs = rest >= nwords? nwords: rest;
1522 ainfo->size = n_in_regs;
1523 ainfo->vtsize = nwords - n_in_regs;
1526 nwords -= n_in_regs;
1528 if (sig->call_convention == MONO_CALL_VARARG)
1529 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1530 stack_size = ALIGN_TO (stack_size, align);
1531 ainfo->offset = stack_size;
1532 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1533 stack_size += nwords * sizeof (gpointer);
1539 add_general (&gr, &stack_size, ainfo, FALSE);
1545 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1547 add_general (&gr, &stack_size, ainfo, TRUE);
1553 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1555 add_general (&gr, &stack_size, ainfo, FALSE);
1558 case MONO_TYPE_MVAR:
1559 /* gsharedvt arguments are passed by ref */
1560 g_assert (mini_is_gsharedvt_type (t));
1561 add_general (&gr, &stack_size, ainfo, TRUE);
1562 switch (ainfo->storage) {
1563 case RegTypeGeneral:
1564 ainfo->storage = RegTypeGSharedVtInReg;
1567 ainfo->storage = RegTypeGSharedVtOnStack;
1570 g_assert_not_reached ();
1574 g_error ("Can't handle 0x%x", sig->params [i]->type);
1579 /* Handle the case where there are no implicit arguments */
1580 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1581 /* Prevent implicit arguments and sig_cookie from
1582 being passed in registers */
1585 /* Emit the signature cookie just before the implicit arguments */
1586 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1589 /* align stack size to 8 */
1590 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1591 stack_size = (stack_size + 7) & ~7;
1593 cinfo->stack_usage = stack_size;
1599 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1601 MonoType *callee_ret;
1605 c1 = get_call_info (NULL, caller_sig);
1606 c2 = get_call_info (NULL, callee_sig);
1609 * Tail calls with more callee stack usage than the caller cannot be supported, since
1610 * the extra stack space would be left on the stack after the tail call.
1612 res = c1->stack_usage >= c2->stack_usage;
1613 callee_ret = mini_get_underlying_type (callee_sig->ret);
1614 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1615 /* An address on the callee's stack is passed as the first argument */
1618 if (c2->stack_usage > 16 * 4)
1630 debug_omit_fp (void)
1633 return mono_debug_count ();
1640 * mono_arch_compute_omit_fp:
1641 * Determine whether the frame pointer can be eliminated.
1644 mono_arch_compute_omit_fp (MonoCompile *cfg)
1646 MonoMethodSignature *sig;
1647 MonoMethodHeader *header;
1651 if (cfg->arch.omit_fp_computed)
1654 header = cfg->header;
1656 sig = mono_method_signature (cfg->method);
1658 if (!cfg->arch.cinfo)
1659 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1660 cinfo = cfg->arch.cinfo;
1663 * FIXME: Remove some of the restrictions.
1665 cfg->arch.omit_fp = TRUE;
1666 cfg->arch.omit_fp_computed = TRUE;
1668 if (cfg->disable_omit_fp)
1669 cfg->arch.omit_fp = FALSE;
1670 if (!debug_omit_fp ())
1671 cfg->arch.omit_fp = FALSE;
1673 if (cfg->method->save_lmf)
1674 cfg->arch.omit_fp = FALSE;
1676 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1677 cfg->arch.omit_fp = FALSE;
1678 if (header->num_clauses)
1679 cfg->arch.omit_fp = FALSE;
1680 if (cfg->param_area)
1681 cfg->arch.omit_fp = FALSE;
1682 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1683 cfg->arch.omit_fp = FALSE;
1684 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1685 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1686 cfg->arch.omit_fp = FALSE;
1687 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1688 ArgInfo *ainfo = &cinfo->args [i];
1690 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1692 * The stack offset can only be determined when the frame
1695 cfg->arch.omit_fp = FALSE;
1700 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1701 MonoInst *ins = cfg->varinfo [i];
1704 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1709 * Set var information according to the calling convention. arm version.
1710 * The locals var stuff should most likely be split in another method.
1713 mono_arch_allocate_vars (MonoCompile *cfg)
1715 MonoMethodSignature *sig;
1716 MonoMethodHeader *header;
1719 int i, offset, size, align, curinst;
1724 sig = mono_method_signature (cfg->method);
1726 if (!cfg->arch.cinfo)
1727 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1728 cinfo = cfg->arch.cinfo;
1729 sig_ret = mini_get_underlying_type (sig->ret);
1731 mono_arch_compute_omit_fp (cfg);
1733 if (cfg->arch.omit_fp)
1734 cfg->frame_reg = ARMREG_SP;
1736 cfg->frame_reg = ARMREG_FP;
1738 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1740 /* allow room for the vararg method args: void* and long/double */
1741 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1742 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1744 header = cfg->header;
1746 /* See mono_arch_get_global_int_regs () */
1747 if (cfg->flags & MONO_CFG_HAS_CALLS)
1748 cfg->uses_rgctx_reg = TRUE;
1750 if (cfg->frame_reg != ARMREG_SP)
1751 cfg->used_int_regs |= 1 << cfg->frame_reg;
1753 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1754 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1755 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1759 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1760 if (sig_ret->type != MONO_TYPE_VOID) {
1761 cfg->ret->opcode = OP_REGVAR;
1762 cfg->ret->inst_c0 = ARMREG_R0;
1765 /* local vars are at a positive offset from the stack pointer */
1767 * also note that if the function uses alloca, we use FP
1768 * to point at the local variables.
1770 offset = 0; /* linkage area */
1771 /* align the offset to 16 bytes: not sure this is needed here */
1773 //offset &= ~(8 - 1);
1775 /* add parameter area size for called functions */
1776 offset += cfg->param_area;
1779 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1782 /* allow room to save the return value */
1783 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1786 switch (cinfo->ret.storage) {
1787 case RegTypeStructByVal:
1789 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1790 offset = ALIGN_TO (offset, 8);
1791 cfg->ret->opcode = OP_REGOFFSET;
1792 cfg->ret->inst_basereg = cfg->frame_reg;
1793 cfg->ret->inst_offset = offset;
1794 if (cinfo->ret.storage == RegTypeStructByVal)
1795 offset += cinfo->ret.nregs * sizeof (gpointer);
1799 case RegTypeStructByAddr:
1800 ins = cfg->vret_addr;
1801 offset += sizeof(gpointer) - 1;
1802 offset &= ~(sizeof(gpointer) - 1);
1803 ins->inst_offset = offset;
1804 ins->opcode = OP_REGOFFSET;
1805 ins->inst_basereg = cfg->frame_reg;
1806 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1807 g_print ("vret_addr =");
1808 mono_print_ins (cfg->vret_addr);
1810 offset += sizeof(gpointer);
1816 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1817 if (cfg->arch.seq_point_info_var) {
1820 ins = cfg->arch.seq_point_info_var;
1824 offset += align - 1;
1825 offset &= ~(align - 1);
1826 ins->opcode = OP_REGOFFSET;
1827 ins->inst_basereg = cfg->frame_reg;
1828 ins->inst_offset = offset;
1831 if (cfg->arch.ss_trigger_page_var) {
1834 ins = cfg->arch.ss_trigger_page_var;
1837 offset += align - 1;
1838 offset &= ~(align - 1);
1839 ins->opcode = OP_REGOFFSET;
1840 ins->inst_basereg = cfg->frame_reg;
1841 ins->inst_offset = offset;
1845 if (cfg->arch.seq_point_ss_method_var) {
1848 ins = cfg->arch.seq_point_ss_method_var;
1851 offset += align - 1;
1852 offset &= ~(align - 1);
1853 ins->opcode = OP_REGOFFSET;
1854 ins->inst_basereg = cfg->frame_reg;
1855 ins->inst_offset = offset;
1858 if (cfg->arch.seq_point_bp_method_var) {
1861 ins = cfg->arch.seq_point_bp_method_var;
1864 offset += align - 1;
1865 offset &= ~(align - 1);
1866 ins->opcode = OP_REGOFFSET;
1867 ins->inst_basereg = cfg->frame_reg;
1868 ins->inst_offset = offset;
1872 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1873 /* Allocate a temporary used by the atomic ops */
1877 /* Allocate a local slot to hold the sig cookie address */
1878 offset += align - 1;
1879 offset &= ~(align - 1);
1880 cfg->arch.atomic_tmp_offset = offset;
1883 cfg->arch.atomic_tmp_offset = -1;
1886 cfg->locals_min_stack_offset = offset;
1888 curinst = cfg->locals_start;
1889 for (i = curinst; i < cfg->num_varinfo; ++i) {
1892 ins = cfg->varinfo [i];
1893 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1896 t = ins->inst_vtype;
1897 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1900 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1901 * pinvoke wrappers when they call functions returning structure */
1902 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1903 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1907 size = mono_type_size (t, &align);
1909 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1910 * since it loads/stores misaligned words, which don't do the right thing.
1912 if (align < 4 && size >= 4)
1914 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1915 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1916 offset += align - 1;
1917 offset &= ~(align - 1);
1918 ins->opcode = OP_REGOFFSET;
1919 ins->inst_offset = offset;
1920 ins->inst_basereg = cfg->frame_reg;
1922 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1925 cfg->locals_max_stack_offset = offset;
1929 ins = cfg->args [curinst];
1930 if (ins->opcode != OP_REGVAR) {
1931 ins->opcode = OP_REGOFFSET;
1932 ins->inst_basereg = cfg->frame_reg;
1933 offset += sizeof (gpointer) - 1;
1934 offset &= ~(sizeof (gpointer) - 1);
1935 ins->inst_offset = offset;
1936 offset += sizeof (gpointer);
1941 if (sig->call_convention == MONO_CALL_VARARG) {
1945 /* Allocate a local slot to hold the sig cookie address */
1946 offset += align - 1;
1947 offset &= ~(align - 1);
1948 cfg->sig_cookie = offset;
1952 for (i = 0; i < sig->param_count; ++i) {
1953 ainfo = cinfo->args + i;
1955 ins = cfg->args [curinst];
1957 switch (ainfo->storage) {
1959 offset = ALIGN_TO (offset, 8);
1960 ins->opcode = OP_REGOFFSET;
1961 ins->inst_basereg = cfg->frame_reg;
1962 /* These arguments are saved to the stack in the prolog */
1963 ins->inst_offset = offset;
1964 if (cfg->verbose_level >= 2)
1965 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
1973 if (ins->opcode != OP_REGVAR) {
1974 ins->opcode = OP_REGOFFSET;
1975 ins->inst_basereg = cfg->frame_reg;
1976 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
1978 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1979 * since it loads/stores misaligned words, which don't do the right thing.
1981 if (align < 4 && size >= 4)
1983 /* The code in the prolog () stores words when storing vtypes received in a register */
1984 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1986 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1987 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1988 offset += align - 1;
1989 offset &= ~(align - 1);
1990 ins->inst_offset = offset;
1996 /* align the offset to 8 bytes */
1997 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
1998 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2003 cfg->stack_offset = offset;
2007 mono_arch_create_vars (MonoCompile *cfg)
2009 MonoMethodSignature *sig;
2013 sig = mono_method_signature (cfg->method);
2015 if (!cfg->arch.cinfo)
2016 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2017 cinfo = cfg->arch.cinfo;
2019 if (IS_HARD_FLOAT) {
2020 for (i = 0; i < 2; i++) {
2021 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2022 inst->flags |= MONO_INST_VOLATILE;
2024 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2028 if (cinfo->ret.storage == RegTypeStructByVal)
2029 cfg->ret_var_is_local = TRUE;
2031 if (cinfo->ret.storage == RegTypeStructByAddr) {
2032 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2033 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2034 g_print ("vret_addr = ");
2035 mono_print_ins (cfg->vret_addr);
2039 if (cfg->gen_sdb_seq_points) {
2040 if (cfg->compile_aot) {
2041 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2042 ins->flags |= MONO_INST_VOLATILE;
2043 cfg->arch.seq_point_info_var = ins;
2045 if (!cfg->soft_breakpoints) {
2046 /* Allocate a separate variable for this to save 1 load per seq point */
2047 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2048 ins->flags |= MONO_INST_VOLATILE;
2049 cfg->arch.ss_trigger_page_var = ins;
2052 if (cfg->soft_breakpoints) {
2055 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2056 ins->flags |= MONO_INST_VOLATILE;
2057 cfg->arch.seq_point_ss_method_var = ins;
2059 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2060 ins->flags |= MONO_INST_VOLATILE;
2061 cfg->arch.seq_point_bp_method_var = ins;
2067 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2069 MonoMethodSignature *tmp_sig;
2072 if (call->tail_call)
2075 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2078 * mono_ArgIterator_Setup assumes the signature cookie is
2079 * passed first and all the arguments which were before it are
2080 * passed on the stack after the signature. So compensate by
2081 * passing a different signature.
2083 tmp_sig = mono_metadata_signature_dup (call->signature);
2084 tmp_sig->param_count -= call->signature->sentinelpos;
2085 tmp_sig->sentinelpos = 0;
2086 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2088 sig_reg = mono_alloc_ireg (cfg);
2089 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2091 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2096 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2101 LLVMCallInfo *linfo;
2103 n = sig->param_count + sig->hasthis;
2105 cinfo = get_call_info (cfg->mempool, sig);
2107 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2110 * LLVM always uses the native ABI while we use our own ABI, the
2111 * only difference is the handling of vtypes:
2112 * - we only pass/receive them in registers in some cases, and only
2113 * in 1 or 2 integer registers.
2115 switch (cinfo->ret.storage) {
2116 case RegTypeGeneral:
2119 case RegTypeIRegPair:
2121 case RegTypeStructByAddr:
2122 /* Vtype returned using a hidden argument */
2123 linfo->ret.storage = LLVMArgVtypeRetAddr;
2124 linfo->vret_arg_index = cinfo->vret_arg_index;
2127 case RegTypeStructByVal:
2128 /* LLVM models this by returning an int array */
2129 linfo->ret.storage = LLVMArgAsIArgs;
2130 linfo->ret.nslots = cinfo->ret.nregs;
2134 linfo->ret.storage = LLVMArgFpStruct;
2135 linfo->ret.nslots = cinfo->ret.nregs;
2136 linfo->ret.esize = cinfo->ret.esize;
2139 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2140 cfg->disable_llvm = TRUE;
2144 for (i = 0; i < n; ++i) {
2145 LLVMArgInfo *lainfo = &linfo->args [i];
2146 ainfo = cinfo->args + i;
2148 lainfo->storage = LLVMArgNone;
2150 switch (ainfo->storage) {
2151 case RegTypeGeneral:
2152 case RegTypeIRegPair:
2154 case RegTypeBaseGen:
2156 lainfo->storage = LLVMArgNormal;
2158 case RegTypeStructByVal:
2159 lainfo->storage = LLVMArgAsIArgs;
2160 if (eabi_supported && ainfo->align == 8) {
2161 /* LLVM models this by passing an int64 array */
2162 lainfo->nslots = ALIGN_TO (ainfo->struct_size, 8) / 8;
2165 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2169 case RegTypeStructByAddr:
2170 case RegTypeStructByAddrOnStack:
2171 lainfo->storage = LLVMArgVtypeByRef;
2176 lainfo->storage = LLVMArgAsFpArgs;
2177 lainfo->nslots = ainfo->nregs;
2178 lainfo->esize = ainfo->esize;
2179 for (j = 0; j < ainfo->nregs; ++j)
2180 lainfo->pair_storage [j] = LLVMArgInFPReg;
2184 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2185 cfg->disable_llvm = TRUE;
2195 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2198 MonoMethodSignature *sig;
2202 sig = call->signature;
2203 n = sig->param_count + sig->hasthis;
2205 cinfo = get_call_info (cfg->mempool, sig);
2207 switch (cinfo->ret.storage) {
2208 case RegTypeStructByVal:
2210 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2211 /* The JIT will transform this into a normal call */
2212 call->vret_in_reg = TRUE;
2215 if (call->inst.opcode == OP_TAILCALL)
2218 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2219 * the location pointed to by it after call in emit_move_return_value ().
2221 if (!cfg->arch.vret_addr_loc) {
2222 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2223 /* Prevent it from being register allocated or optimized away */
2224 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2227 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2229 case RegTypeStructByAddr: {
2231 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2232 vtarg->sreg1 = call->vret_var->dreg;
2233 vtarg->dreg = mono_alloc_preg (cfg);
2234 MONO_ADD_INS (cfg->cbb, vtarg);
2236 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2243 for (i = 0; i < n; ++i) {
2244 ArgInfo *ainfo = cinfo->args + i;
2247 if (i >= sig->hasthis)
2248 t = sig->params [i - sig->hasthis];
2250 t = &mono_defaults.int_class->byval_arg;
2251 t = mini_get_underlying_type (t);
2253 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2254 /* Emit the signature cookie just before the implicit arguments */
2255 emit_sig_cookie (cfg, call, cinfo);
2258 in = call->args [i];
2260 switch (ainfo->storage) {
2261 case RegTypeGeneral:
2262 case RegTypeIRegPair:
2263 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2264 MONO_INST_NEW (cfg, ins, OP_MOVE);
2265 ins->dreg = mono_alloc_ireg (cfg);
2266 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2267 MONO_ADD_INS (cfg->cbb, ins);
2268 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2270 MONO_INST_NEW (cfg, ins, OP_MOVE);
2271 ins->dreg = mono_alloc_ireg (cfg);
2272 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2273 MONO_ADD_INS (cfg->cbb, ins);
2274 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2275 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2276 if (ainfo->size == 4) {
2277 if (IS_SOFT_FLOAT) {
2278 /* mono_emit_call_args () have already done the r8->r4 conversion */
2279 /* The converted value is in an int vreg */
2280 MONO_INST_NEW (cfg, ins, OP_MOVE);
2281 ins->dreg = mono_alloc_ireg (cfg);
2282 ins->sreg1 = in->dreg;
2283 MONO_ADD_INS (cfg->cbb, ins);
2284 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2288 cfg->param_area = MAX (cfg->param_area, 8);
2289 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2290 creg = mono_alloc_ireg (cfg);
2291 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2292 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2295 if (IS_SOFT_FLOAT) {
2296 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2297 ins->dreg = mono_alloc_ireg (cfg);
2298 ins->sreg1 = in->dreg;
2299 MONO_ADD_INS (cfg->cbb, ins);
2300 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2302 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2303 ins->dreg = mono_alloc_ireg (cfg);
2304 ins->sreg1 = in->dreg;
2305 MONO_ADD_INS (cfg->cbb, ins);
2306 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2310 cfg->param_area = MAX (cfg->param_area, 8);
2311 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2312 creg = mono_alloc_ireg (cfg);
2313 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2314 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2315 creg = mono_alloc_ireg (cfg);
2316 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2317 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2320 cfg->flags |= MONO_CFG_HAS_FPOUT;
2322 MONO_INST_NEW (cfg, ins, OP_MOVE);
2323 ins->dreg = mono_alloc_ireg (cfg);
2324 ins->sreg1 = in->dreg;
2325 MONO_ADD_INS (cfg->cbb, ins);
2327 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2330 case RegTypeStructByVal:
2331 case RegTypeGSharedVtInReg:
2332 case RegTypeGSharedVtOnStack:
2334 case RegTypeStructByAddr:
2335 case RegTypeStructByAddrOnStack:
2336 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2337 ins->opcode = OP_OUTARG_VT;
2338 ins->sreg1 = in->dreg;
2339 ins->klass = in->klass;
2340 ins->inst_p0 = call;
2341 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2342 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2343 mono_call_inst_add_outarg_vt (cfg, call, ins);
2344 MONO_ADD_INS (cfg->cbb, ins);
2347 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2348 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2349 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2350 if (t->type == MONO_TYPE_R8) {
2351 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2354 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2356 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2359 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2362 case RegTypeBaseGen:
2363 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2364 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2365 MONO_INST_NEW (cfg, ins, OP_MOVE);
2366 ins->dreg = mono_alloc_ireg (cfg);
2367 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2368 MONO_ADD_INS (cfg->cbb, ins);
2369 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2370 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2373 /* This should work for soft-float as well */
2375 cfg->param_area = MAX (cfg->param_area, 8);
2376 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2377 creg = mono_alloc_ireg (cfg);
2378 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2379 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2380 creg = mono_alloc_ireg (cfg);
2381 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2382 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2383 cfg->flags |= MONO_CFG_HAS_FPOUT;
2385 g_assert_not_reached ();
2389 int fdreg = mono_alloc_freg (cfg);
2391 if (ainfo->size == 8) {
2392 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2393 ins->sreg1 = in->dreg;
2395 MONO_ADD_INS (cfg->cbb, ins);
2397 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2402 * Mono's register allocator doesn't speak single-precision registers that
2403 * overlap double-precision registers (i.e. armhf). So we have to work around
2404 * the register allocator and load the value from memory manually.
2406 * So we create a variable for the float argument and an instruction to store
2407 * the argument into the variable. We then store the list of these arguments
2408 * in call->float_args. This list is then used by emit_float_args later to
2409 * pass the arguments in the various call opcodes.
2411 * This is not very nice, and we should really try to fix the allocator.
2414 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2416 /* Make sure the instruction isn't seen as pointless and removed.
2418 float_arg->flags |= MONO_INST_VOLATILE;
2420 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2422 /* We use the dreg to look up the instruction later. The hreg is used to
2423 * emit the instruction that loads the value into the FP reg.
2425 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2426 fad->vreg = float_arg->dreg;
2427 fad->hreg = ainfo->reg;
2429 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2432 call->used_iregs |= 1 << ainfo->reg;
2433 cfg->flags |= MONO_CFG_HAS_FPOUT;
2437 g_assert_not_reached ();
2441 /* Handle the case where there are no implicit arguments */
2442 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2443 emit_sig_cookie (cfg, call, cinfo);
2445 call->call_info = cinfo;
2446 call->stack_usage = cinfo->stack_usage;
2450 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2456 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2457 ins->dreg = mono_alloc_freg (cfg);
2458 ins->sreg1 = arg->dreg;
2459 MONO_ADD_INS (cfg->cbb, ins);
2460 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2463 g_assert_not_reached ();
2469 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2471 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2473 ArgInfo *ainfo = ins->inst_p1;
2474 int ovf_size = ainfo->vtsize;
2475 int doffset = ainfo->offset;
2476 int struct_size = ainfo->struct_size;
2477 int i, soffset, dreg, tmpreg;
2479 switch (ainfo->storage) {
2480 case RegTypeGSharedVtInReg:
2481 case RegTypeStructByAddr:
2483 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2485 case RegTypeGSharedVtOnStack:
2486 case RegTypeStructByAddrOnStack:
2487 /* Pass by addr on stack */
2488 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2491 for (i = 0; i < ainfo->nregs; ++i) {
2492 if (ainfo->esize == 4)
2493 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2495 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2496 load->dreg = mono_alloc_freg (cfg);
2497 load->inst_basereg = src->dreg;
2498 load->inst_offset = i * ainfo->esize;
2499 MONO_ADD_INS (cfg->cbb, load);
2501 if (ainfo->esize == 4) {
2504 /* See RegTypeFP in mono_arch_emit_call () */
2505 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2506 float_arg->flags |= MONO_INST_VOLATILE;
2507 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2509 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2510 fad->vreg = float_arg->dreg;
2511 fad->hreg = ainfo->reg + i;
2513 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2515 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2521 for (i = 0; i < ainfo->size; ++i) {
2522 dreg = mono_alloc_ireg (cfg);
2523 switch (struct_size) {
2525 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2528 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2531 tmpreg = mono_alloc_ireg (cfg);
2532 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2533 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2534 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2535 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2536 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2537 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2538 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2541 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2544 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2545 soffset += sizeof (gpointer);
2546 struct_size -= sizeof (gpointer);
2548 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2550 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2556 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2558 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2561 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2564 if (COMPILE_LLVM (cfg)) {
2565 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2567 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2568 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2569 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2570 MONO_ADD_INS (cfg->cbb, ins);
2575 case MONO_ARM_FPU_NONE:
2576 if (ret->type == MONO_TYPE_R8) {
2579 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2580 ins->dreg = cfg->ret->dreg;
2581 ins->sreg1 = val->dreg;
2582 MONO_ADD_INS (cfg->cbb, ins);
2585 if (ret->type == MONO_TYPE_R4) {
2586 /* Already converted to an int in method_to_ir () */
2587 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2591 case MONO_ARM_FPU_VFP:
2592 case MONO_ARM_FPU_VFP_HARD:
2593 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2596 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2597 ins->dreg = cfg->ret->dreg;
2598 ins->sreg1 = val->dreg;
2599 MONO_ADD_INS (cfg->cbb, ins);
2604 g_assert_not_reached ();
2608 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2611 #endif /* #ifndef DISABLE_JIT */
2614 mono_arch_is_inst_imm (gint64 imm)
2620 MonoMethodSignature *sig;
2623 MonoType **param_types;
2627 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2631 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2634 switch (cinfo->ret.storage) {
2636 case RegTypeGeneral:
2637 case RegTypeIRegPair:
2638 case RegTypeStructByAddr:
2649 for (i = 0; i < cinfo->nargs; ++i) {
2650 ArgInfo *ainfo = &cinfo->args [i];
2653 switch (ainfo->storage) {
2654 case RegTypeGeneral:
2655 case RegTypeIRegPair:
2656 case RegTypeBaseGen:
2660 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2663 case RegTypeStructByVal:
2664 if (ainfo->size == 0)
2665 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2667 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2668 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2676 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2677 for (i = 0; i < sig->param_count; ++i) {
2678 MonoType *t = sig->params [i];
2683 t = mini_get_underlying_type (t);
2706 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2708 ArchDynCallInfo *info;
2712 cinfo = get_call_info (NULL, sig);
2714 if (!dyn_call_supported (cinfo, sig)) {
2719 info = g_new0 (ArchDynCallInfo, 1);
2720 // FIXME: Preprocess the info to speed up start_dyn_call ()
2722 info->cinfo = cinfo;
2723 info->rtype = mini_get_underlying_type (sig->ret);
2724 info->param_types = g_new0 (MonoType*, sig->param_count);
2725 for (i = 0; i < sig->param_count; ++i)
2726 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2728 return (MonoDynCallInfo*)info;
2732 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2734 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2736 g_free (ainfo->cinfo);
2741 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2743 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2744 DynCallArgs *p = (DynCallArgs*)buf;
2745 int arg_index, greg, i, j, pindex;
2746 MonoMethodSignature *sig = dinfo->sig;
2748 g_assert (buf_len >= sizeof (DynCallArgs));
2758 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2759 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2764 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2765 p->regs [greg ++] = (mgreg_t)ret;
2767 for (i = pindex; i < sig->param_count; i++) {
2768 MonoType *t = dinfo->param_types [i];
2769 gpointer *arg = args [arg_index ++];
2770 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2773 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2775 } else if (ainfo->storage == RegTypeFP) {
2776 } else if (ainfo->storage == RegTypeBase) {
2777 slot = PARAM_REGS + (ainfo->offset / 4);
2778 } else if (ainfo->storage == RegTypeBaseGen) {
2779 /* slot + 1 is the first stack slot, so the code below will work */
2782 g_assert_not_reached ();
2786 p->regs [slot] = (mgreg_t)*arg;
2791 case MONO_TYPE_OBJECT:
2795 p->regs [slot] = (mgreg_t)*arg;
2798 p->regs [slot] = *(guint8*)arg;
2801 p->regs [slot] = *(gint8*)arg;
2804 p->regs [slot] = *(gint16*)arg;
2807 p->regs [slot] = *(guint16*)arg;
2810 p->regs [slot] = *(gint32*)arg;
2813 p->regs [slot] = *(guint32*)arg;
2817 p->regs [slot ++] = (mgreg_t)arg [0];
2818 p->regs [slot] = (mgreg_t)arg [1];
2821 if (ainfo->storage == RegTypeFP) {
2822 float f = *(float*)arg;
2823 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2826 p->regs [slot] = *(mgreg_t*)arg;
2830 if (ainfo->storage == RegTypeFP) {
2831 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2834 p->regs [slot ++] = (mgreg_t)arg [0];
2835 p->regs [slot] = (mgreg_t)arg [1];
2838 case MONO_TYPE_GENERICINST:
2839 if (MONO_TYPE_IS_REFERENCE (t)) {
2840 p->regs [slot] = (mgreg_t)*arg;
2843 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2844 MonoClass *klass = mono_class_from_mono_type (t);
2845 guint8 *nullable_buf;
2848 size = mono_class_value_size (klass, NULL);
2849 nullable_buf = g_alloca (size);
2850 g_assert (nullable_buf);
2852 /* The argument pointed to by arg is either a boxed vtype or null */
2853 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2855 arg = (gpointer*)nullable_buf;
2861 case MONO_TYPE_VALUETYPE:
2862 g_assert (ainfo->storage == RegTypeStructByVal);
2864 if (ainfo->size == 0)
2865 slot = PARAM_REGS + (ainfo->offset / 4);
2869 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2870 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2873 g_assert_not_reached ();
2879 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2881 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2882 DynCallArgs *p = (DynCallArgs*)buf;
2883 MonoType *ptype = ainfo->rtype;
2884 guint8 *ret = p->ret;
2885 mgreg_t res = p->res;
2886 mgreg_t res2 = p->res2;
2888 switch (ptype->type) {
2889 case MONO_TYPE_VOID:
2890 *(gpointer*)ret = NULL;
2892 case MONO_TYPE_OBJECT:
2896 *(gpointer*)ret = (gpointer)res;
2902 *(guint8*)ret = res;
2905 *(gint16*)ret = res;
2908 *(guint16*)ret = res;
2911 *(gint32*)ret = res;
2914 *(guint32*)ret = res;
2918 /* This handles endianness as well */
2919 ((gint32*)ret) [0] = res;
2920 ((gint32*)ret) [1] = res2;
2922 case MONO_TYPE_GENERICINST:
2923 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2924 *(gpointer*)ret = (gpointer)res;
2929 case MONO_TYPE_VALUETYPE:
2930 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2936 *(float*)ret = *(float*)&p->fpregs [0];
2938 *(float*)ret = *(float*)&res;
2940 case MONO_TYPE_R8: {
2944 if (IS_HARD_FLOAT) {
2945 *(double*)ret = p->fpregs [0];
2950 *(double*)ret = *(double*)®s;
2955 g_assert_not_reached ();
2962 * Allow tracing to work with this interface (with an optional argument)
2966 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2970 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2971 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2972 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2973 code = emit_call_reg (code, ARMREG_R2);
2987 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2990 int save_mode = SAVE_NONE;
2992 MonoMethod *method = cfg->method;
2993 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
2994 int rtype = ret_type->type;
2995 int save_offset = cfg->param_area;
2999 offset = code - cfg->native_code;
3000 /* we need about 16 instructions */
3001 if (offset > (cfg->code_size - 16 * 4)) {
3002 cfg->code_size *= 2;
3003 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3004 code = cfg->native_code + offset;
3007 case MONO_TYPE_VOID:
3008 /* special case string .ctor icall */
3009 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3010 save_mode = SAVE_ONE;
3012 save_mode = SAVE_NONE;
3016 save_mode = SAVE_TWO;
3020 save_mode = SAVE_ONE_FP;
3022 save_mode = SAVE_ONE;
3026 save_mode = SAVE_TWO_FP;
3028 save_mode = SAVE_TWO;
3030 case MONO_TYPE_GENERICINST:
3031 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3032 save_mode = SAVE_ONE;
3036 case MONO_TYPE_VALUETYPE:
3037 save_mode = SAVE_STRUCT;
3040 save_mode = SAVE_ONE;
3044 switch (save_mode) {
3046 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3047 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3048 if (enable_arguments) {
3049 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3050 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3054 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3055 if (enable_arguments) {
3056 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3060 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3061 if (enable_arguments) {
3062 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3066 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3067 if (enable_arguments) {
3068 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3072 if (enable_arguments) {
3073 /* FIXME: get the actual address */
3074 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3082 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3083 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3084 code = emit_call_reg (code, ARMREG_IP);
3086 switch (save_mode) {
3088 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3089 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3092 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3095 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3098 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3109 * The immediate field for cond branches is big enough for all reasonable methods
3111 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3112 if (0 && ins->inst_true_bb->native_offset) { \
3113 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3115 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3116 ARM_B_COND (code, (condcode), 0); \
3119 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3121 /* emit an exception if condition is fail
3123 * We assign the extra code used to throw the implicit exceptions
3124 * to cfg->bb_exit as far as the big branch handling is concerned
3126 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3128 mono_add_patch_info (cfg, code - cfg->native_code, \
3129 MONO_PATCH_INFO_EXC, exc_name); \
3130 ARM_BL_COND (code, (condcode), 0); \
3133 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3136 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3141 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3145 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3146 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3148 switch (ins->opcode) {
3151 /* Already done by an arch-independent pass */
3153 case OP_LOAD_MEMBASE:
3154 case OP_LOADI4_MEMBASE:
3156 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3157 * OP_LOAD_MEMBASE offset(basereg), reg
3159 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3160 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3161 ins->inst_basereg == last_ins->inst_destbasereg &&
3162 ins->inst_offset == last_ins->inst_offset) {
3163 if (ins->dreg == last_ins->sreg1) {
3164 MONO_DELETE_INS (bb, ins);
3167 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3168 ins->opcode = OP_MOVE;
3169 ins->sreg1 = last_ins->sreg1;
3173 * Note: reg1 must be different from the basereg in the second load
3174 * OP_LOAD_MEMBASE offset(basereg), reg1
3175 * OP_LOAD_MEMBASE offset(basereg), reg2
3177 * OP_LOAD_MEMBASE offset(basereg), reg1
3178 * OP_MOVE reg1, reg2
3180 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3181 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3182 ins->inst_basereg != last_ins->dreg &&
3183 ins->inst_basereg == last_ins->inst_basereg &&
3184 ins->inst_offset == last_ins->inst_offset) {
3186 if (ins->dreg == last_ins->dreg) {
3187 MONO_DELETE_INS (bb, ins);
3190 ins->opcode = OP_MOVE;
3191 ins->sreg1 = last_ins->dreg;
3194 //g_assert_not_reached ();
3198 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3199 * OP_LOAD_MEMBASE offset(basereg), reg
3201 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3202 * OP_ICONST reg, imm
3204 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3205 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3206 ins->inst_basereg == last_ins->inst_destbasereg &&
3207 ins->inst_offset == last_ins->inst_offset) {
3208 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3209 ins->opcode = OP_ICONST;
3210 ins->inst_c0 = last_ins->inst_imm;
3211 g_assert_not_reached (); // check this rule
3215 case OP_LOADU1_MEMBASE:
3216 case OP_LOADI1_MEMBASE:
3217 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3218 ins->inst_basereg == last_ins->inst_destbasereg &&
3219 ins->inst_offset == last_ins->inst_offset) {
3220 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3221 ins->sreg1 = last_ins->sreg1;
3224 case OP_LOADU2_MEMBASE:
3225 case OP_LOADI2_MEMBASE:
3226 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3227 ins->inst_basereg == last_ins->inst_destbasereg &&
3228 ins->inst_offset == last_ins->inst_offset) {
3229 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3230 ins->sreg1 = last_ins->sreg1;
3234 ins->opcode = OP_MOVE;
3238 if (ins->dreg == ins->sreg1) {
3239 MONO_DELETE_INS (bb, ins);
3243 * OP_MOVE sreg, dreg
3244 * OP_MOVE dreg, sreg
3246 if (last_ins && last_ins->opcode == OP_MOVE &&
3247 ins->sreg1 == last_ins->dreg &&
3248 ins->dreg == last_ins->sreg1) {
3249 MONO_DELETE_INS (bb, ins);
3258 * the branch_cc_table should maintain the order of these
3272 branch_cc_table [] = {
3286 #define ADD_NEW_INS(cfg,dest,op) do { \
3287 MONO_INST_NEW ((cfg), (dest), (op)); \
3288 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3292 map_to_reg_reg_op (int op)
3301 case OP_COMPARE_IMM:
3303 case OP_ICOMPARE_IMM:
3317 case OP_LOAD_MEMBASE:
3318 return OP_LOAD_MEMINDEX;
3319 case OP_LOADI4_MEMBASE:
3320 return OP_LOADI4_MEMINDEX;
3321 case OP_LOADU4_MEMBASE:
3322 return OP_LOADU4_MEMINDEX;
3323 case OP_LOADU1_MEMBASE:
3324 return OP_LOADU1_MEMINDEX;
3325 case OP_LOADI2_MEMBASE:
3326 return OP_LOADI2_MEMINDEX;
3327 case OP_LOADU2_MEMBASE:
3328 return OP_LOADU2_MEMINDEX;
3329 case OP_LOADI1_MEMBASE:
3330 return OP_LOADI1_MEMINDEX;
3331 case OP_STOREI1_MEMBASE_REG:
3332 return OP_STOREI1_MEMINDEX;
3333 case OP_STOREI2_MEMBASE_REG:
3334 return OP_STOREI2_MEMINDEX;
3335 case OP_STOREI4_MEMBASE_REG:
3336 return OP_STOREI4_MEMINDEX;
3337 case OP_STORE_MEMBASE_REG:
3338 return OP_STORE_MEMINDEX;
3339 case OP_STORER4_MEMBASE_REG:
3340 return OP_STORER4_MEMINDEX;
3341 case OP_STORER8_MEMBASE_REG:
3342 return OP_STORER8_MEMINDEX;
3343 case OP_STORE_MEMBASE_IMM:
3344 return OP_STORE_MEMBASE_REG;
3345 case OP_STOREI1_MEMBASE_IMM:
3346 return OP_STOREI1_MEMBASE_REG;
3347 case OP_STOREI2_MEMBASE_IMM:
3348 return OP_STOREI2_MEMBASE_REG;
3349 case OP_STOREI4_MEMBASE_IMM:
3350 return OP_STOREI4_MEMBASE_REG;
3352 g_assert_not_reached ();
3356 * Remove from the instruction list the instructions that can't be
3357 * represented with very simple instructions with no register
3361 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3363 MonoInst *ins, *temp, *last_ins = NULL;
3364 int rot_amount, imm8, low_imm;
3366 MONO_BB_FOR_EACH_INS (bb, ins) {
3368 switch (ins->opcode) {
3372 case OP_COMPARE_IMM:
3373 case OP_ICOMPARE_IMM:
3387 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3388 int opcode2 = mono_op_imm_to_op (ins->opcode);
3389 ADD_NEW_INS (cfg, temp, OP_ICONST);
3390 temp->inst_c0 = ins->inst_imm;
3391 temp->dreg = mono_alloc_ireg (cfg);
3392 ins->sreg2 = temp->dreg;
3394 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3395 ins->opcode = opcode2;
3397 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3403 if (ins->inst_imm == 1) {
3404 ins->opcode = OP_MOVE;
3407 if (ins->inst_imm == 0) {
3408 ins->opcode = OP_ICONST;
3412 imm8 = mono_is_power_of_two (ins->inst_imm);
3414 ins->opcode = OP_SHL_IMM;
3415 ins->inst_imm = imm8;
3418 ADD_NEW_INS (cfg, temp, OP_ICONST);
3419 temp->inst_c0 = ins->inst_imm;
3420 temp->dreg = mono_alloc_ireg (cfg);
3421 ins->sreg2 = temp->dreg;
3422 ins->opcode = OP_IMUL;
3428 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3429 /* ARM sets the C flag to 1 if there was _no_ overflow */
3430 ins->next->opcode = OP_COND_EXC_NC;
3433 case OP_IDIV_UN_IMM:
3435 case OP_IREM_UN_IMM: {
3436 int opcode2 = mono_op_imm_to_op (ins->opcode);
3437 ADD_NEW_INS (cfg, temp, OP_ICONST);
3438 temp->inst_c0 = ins->inst_imm;
3439 temp->dreg = mono_alloc_ireg (cfg);
3440 ins->sreg2 = temp->dreg;
3442 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3443 ins->opcode = opcode2;
3446 case OP_LOCALLOC_IMM:
3447 ADD_NEW_INS (cfg, temp, OP_ICONST);
3448 temp->inst_c0 = ins->inst_imm;
3449 temp->dreg = mono_alloc_ireg (cfg);
3450 ins->sreg1 = temp->dreg;
3451 ins->opcode = OP_LOCALLOC;
3453 case OP_LOAD_MEMBASE:
3454 case OP_LOADI4_MEMBASE:
3455 case OP_LOADU4_MEMBASE:
3456 case OP_LOADU1_MEMBASE:
3457 /* we can do two things: load the immed in a register
3458 * and use an indexed load, or see if the immed can be
3459 * represented as an ad_imm + a load with a smaller offset
3460 * that fits. We just do the first for now, optimize later.
3462 if (arm_is_imm12 (ins->inst_offset))
3464 ADD_NEW_INS (cfg, temp, OP_ICONST);
3465 temp->inst_c0 = ins->inst_offset;
3466 temp->dreg = mono_alloc_ireg (cfg);
3467 ins->sreg2 = temp->dreg;
3468 ins->opcode = map_to_reg_reg_op (ins->opcode);
3470 case OP_LOADI2_MEMBASE:
3471 case OP_LOADU2_MEMBASE:
3472 case OP_LOADI1_MEMBASE:
3473 if (arm_is_imm8 (ins->inst_offset))
3475 ADD_NEW_INS (cfg, temp, OP_ICONST);
3476 temp->inst_c0 = ins->inst_offset;
3477 temp->dreg = mono_alloc_ireg (cfg);
3478 ins->sreg2 = temp->dreg;
3479 ins->opcode = map_to_reg_reg_op (ins->opcode);
3481 case OP_LOADR4_MEMBASE:
3482 case OP_LOADR8_MEMBASE:
3483 if (arm_is_fpimm8 (ins->inst_offset))
3485 low_imm = ins->inst_offset & 0x1ff;
3486 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3487 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3488 temp->inst_imm = ins->inst_offset & ~0x1ff;
3489 temp->sreg1 = ins->inst_basereg;
3490 temp->dreg = mono_alloc_ireg (cfg);
3491 ins->inst_basereg = temp->dreg;
3492 ins->inst_offset = low_imm;
3496 ADD_NEW_INS (cfg, temp, OP_ICONST);
3497 temp->inst_c0 = ins->inst_offset;
3498 temp->dreg = mono_alloc_ireg (cfg);
3500 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3501 add_ins->sreg1 = ins->inst_basereg;
3502 add_ins->sreg2 = temp->dreg;
3503 add_ins->dreg = mono_alloc_ireg (cfg);
3505 ins->inst_basereg = add_ins->dreg;
3506 ins->inst_offset = 0;
3509 case OP_STORE_MEMBASE_REG:
3510 case OP_STOREI4_MEMBASE_REG:
3511 case OP_STOREI1_MEMBASE_REG:
3512 if (arm_is_imm12 (ins->inst_offset))
3514 ADD_NEW_INS (cfg, temp, OP_ICONST);
3515 temp->inst_c0 = ins->inst_offset;
3516 temp->dreg = mono_alloc_ireg (cfg);
3517 ins->sreg2 = temp->dreg;
3518 ins->opcode = map_to_reg_reg_op (ins->opcode);
3520 case OP_STOREI2_MEMBASE_REG:
3521 if (arm_is_imm8 (ins->inst_offset))
3523 ADD_NEW_INS (cfg, temp, OP_ICONST);
3524 temp->inst_c0 = ins->inst_offset;
3525 temp->dreg = mono_alloc_ireg (cfg);
3526 ins->sreg2 = temp->dreg;
3527 ins->opcode = map_to_reg_reg_op (ins->opcode);
3529 case OP_STORER4_MEMBASE_REG:
3530 case OP_STORER8_MEMBASE_REG:
3531 if (arm_is_fpimm8 (ins->inst_offset))
3533 low_imm = ins->inst_offset & 0x1ff;
3534 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3535 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3536 temp->inst_imm = ins->inst_offset & ~0x1ff;
3537 temp->sreg1 = ins->inst_destbasereg;
3538 temp->dreg = mono_alloc_ireg (cfg);
3539 ins->inst_destbasereg = temp->dreg;
3540 ins->inst_offset = low_imm;
3544 ADD_NEW_INS (cfg, temp, OP_ICONST);
3545 temp->inst_c0 = ins->inst_offset;
3546 temp->dreg = mono_alloc_ireg (cfg);
3548 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3549 add_ins->sreg1 = ins->inst_destbasereg;
3550 add_ins->sreg2 = temp->dreg;
3551 add_ins->dreg = mono_alloc_ireg (cfg);
3553 ins->inst_destbasereg = add_ins->dreg;
3554 ins->inst_offset = 0;
3557 case OP_STORE_MEMBASE_IMM:
3558 case OP_STOREI1_MEMBASE_IMM:
3559 case OP_STOREI2_MEMBASE_IMM:
3560 case OP_STOREI4_MEMBASE_IMM:
3561 ADD_NEW_INS (cfg, temp, OP_ICONST);
3562 temp->inst_c0 = ins->inst_imm;
3563 temp->dreg = mono_alloc_ireg (cfg);
3564 ins->sreg1 = temp->dreg;
3565 ins->opcode = map_to_reg_reg_op (ins->opcode);
3567 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3570 gboolean swap = FALSE;
3574 /* Optimized away */
3579 /* Some fp compares require swapped operands */
3580 switch (ins->next->opcode) {
3582 ins->next->opcode = OP_FBLT;
3586 ins->next->opcode = OP_FBLT_UN;
3590 ins->next->opcode = OP_FBGE;
3594 ins->next->opcode = OP_FBGE_UN;
3602 ins->sreg1 = ins->sreg2;
3611 bb->last_ins = last_ins;
3612 bb->max_vreg = cfg->next_vreg;
3616 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3620 if (long_ins->opcode == OP_LNEG) {
3622 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3623 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3629 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3631 /* sreg is a float, dreg is an integer reg */
3633 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3635 ARM_TOSIZD (code, vfp_scratch1, sreg);
3637 ARM_TOUIZD (code, vfp_scratch1, sreg);
3638 ARM_FMRS (code, dreg, vfp_scratch1);
3639 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3643 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3644 else if (size == 2) {
3645 ARM_SHL_IMM (code, dreg, dreg, 16);
3646 ARM_SHR_IMM (code, dreg, dreg, 16);
3650 ARM_SHL_IMM (code, dreg, dreg, 24);
3651 ARM_SAR_IMM (code, dreg, dreg, 24);
3652 } else if (size == 2) {
3653 ARM_SHL_IMM (code, dreg, dreg, 16);
3654 ARM_SAR_IMM (code, dreg, dreg, 16);
3661 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3663 /* sreg is a float, dreg is an integer reg */
3665 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3667 ARM_TOSIZS (code, vfp_scratch1, sreg);
3669 ARM_TOUIZS (code, vfp_scratch1, sreg);
3670 ARM_FMRS (code, dreg, vfp_scratch1);
3671 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3675 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3676 else if (size == 2) {
3677 ARM_SHL_IMM (code, dreg, dreg, 16);
3678 ARM_SHR_IMM (code, dreg, dreg, 16);
3682 ARM_SHL_IMM (code, dreg, dreg, 24);
3683 ARM_SAR_IMM (code, dreg, dreg, 24);
3684 } else if (size == 2) {
3685 ARM_SHL_IMM (code, dreg, dreg, 16);
3686 ARM_SAR_IMM (code, dreg, dreg, 16);
3692 #endif /* #ifndef DISABLE_JIT */
3694 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3697 emit_thunk (guint8 *code, gconstpointer target)
3701 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3702 if (thumb_supported)
3703 ARM_BX (code, ARMREG_IP);
3705 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3706 *(guint32*)code = (guint32)target;
3708 mono_arch_flush_icache (p, code - p);
3712 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3714 MonoJitInfo *ji = NULL;
3715 MonoThunkJitInfo *info;
3718 guint8 *orig_target;
3719 guint8 *target_thunk;
3722 domain = mono_domain_get ();
3726 * This can be called multiple times during JITting,
3727 * save the current position in cfg->arch to avoid
3728 * doing a O(n^2) search.
3730 if (!cfg->arch.thunks) {
3731 cfg->arch.thunks = cfg->thunks;
3732 cfg->arch.thunks_size = cfg->thunk_area;
3734 thunks = cfg->arch.thunks;
3735 thunks_size = cfg->arch.thunks_size;
3737 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3738 g_assert_not_reached ();
3741 g_assert (*(guint32*)thunks == 0);
3742 emit_thunk (thunks, target);
3743 arm_patch (code, thunks);
3745 cfg->arch.thunks += THUNK_SIZE;
3746 cfg->arch.thunks_size -= THUNK_SIZE;
3748 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3750 info = mono_jit_info_get_thunk_info (ji);
3753 thunks = (guint8*)ji->code_start + info->thunks_offset;
3754 thunks_size = info->thunks_size;
3756 orig_target = mono_arch_get_call_target (code + 4);
3758 mono_mini_arch_lock ();
3760 target_thunk = NULL;
3761 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3762 /* The call already points to a thunk, because of trampolines etc. */
3763 target_thunk = orig_target;
3765 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3766 if (((guint32*)p) [0] == 0) {
3770 } else if (((guint32*)p) [2] == (guint32)target) {
3771 /* Thunk already points to target */
3778 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3780 if (!target_thunk) {
3781 mono_mini_arch_unlock ();
3782 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3783 g_assert_not_reached ();
3786 emit_thunk (target_thunk, target);
3787 arm_patch (code, target_thunk);
3788 mono_arch_flush_icache (code, 4);
3790 mono_mini_arch_unlock ();
3795 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3797 guint32 *code32 = (void*)code;
3798 guint32 ins = *code32;
3799 guint32 prim = (ins >> 25) & 7;
3800 guint32 tval = GPOINTER_TO_UINT (target);
3802 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3803 if (prim == 5) { /* 101b */
3804 /* the diff starts 8 bytes from the branch opcode */
3805 gint diff = target - code - 8;
3807 gint tmask = 0xffffffff;
3808 if (tval & 1) { /* entering thumb mode */
3809 diff = target - 1 - code - 8;
3810 g_assert (thumb_supported);
3811 tbits = 0xf << 28; /* bl->blx bit pattern */
3812 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3813 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3817 tmask = ~(1 << 24); /* clear the link bit */
3818 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3823 if (diff <= 33554431) {
3825 ins = (ins & 0xff000000) | diff;
3827 *code32 = ins | tbits;
3831 /* diff between 0 and -33554432 */
3832 if (diff >= -33554432) {
3834 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3836 *code32 = ins | tbits;
3841 handle_thunk (cfg, domain, code, target);
3846 * The alternative call sequences looks like this:
3848 * ldr ip, [pc] // loads the address constant
3849 * b 1f // jumps around the constant
3850 * address constant embedded in the code
3855 * There are two cases for patching:
3856 * a) at the end of method emission: in this case code points to the start
3857 * of the call sequence
3858 * b) during runtime patching of the call site: in this case code points
3859 * to the mov pc, ip instruction
3861 * We have to handle also the thunk jump code sequence:
3865 * address constant // execution never reaches here
3867 if ((ins & 0x0ffffff0) == 0x12fff10) {
3868 /* Branch and exchange: the address is constructed in a reg
3869 * We can patch BX when the code sequence is the following:
3870 * ldr ip, [pc, #0] ; 0x8
3877 guint8 *emit = (guint8*)ccode;
3878 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3880 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3881 ARM_BX (emit, ARMREG_IP);
3883 /*patching from magic trampoline*/
3884 if (ins == ccode [3]) {
3885 g_assert (code32 [-4] == ccode [0]);
3886 g_assert (code32 [-3] == ccode [1]);
3887 g_assert (code32 [-1] == ccode [2]);
3888 code32 [-2] = (guint32)target;
3891 /*patching from JIT*/
3892 if (ins == ccode [0]) {
3893 g_assert (code32 [1] == ccode [1]);
3894 g_assert (code32 [3] == ccode [2]);
3895 g_assert (code32 [4] == ccode [3]);
3896 code32 [2] = (guint32)target;
3899 g_assert_not_reached ();
3900 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3908 guint8 *emit = (guint8*)ccode;
3909 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3911 ARM_BLX_REG (emit, ARMREG_IP);
3913 g_assert (code32 [-3] == ccode [0]);
3914 g_assert (code32 [-2] == ccode [1]);
3915 g_assert (code32 [0] == ccode [2]);
3917 code32 [-1] = (guint32)target;
3920 guint32 *tmp = ccode;
3921 guint8 *emit = (guint8*)tmp;
3922 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3923 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3924 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3925 ARM_BX (emit, ARMREG_IP);
3926 if (ins == ccode [2]) {
3927 g_assert_not_reached (); // should be -2 ...
3928 code32 [-1] = (guint32)target;
3931 if (ins == ccode [0]) {
3932 /* handles both thunk jump code and the far call sequence */
3933 code32 [2] = (guint32)target;
3936 g_assert_not_reached ();
3938 // g_print ("patched with 0x%08x\n", ins);
3942 arm_patch (guchar *code, const guchar *target)
3944 arm_patch_general (NULL, NULL, code, target);
3948 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3949 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3950 * to be used with the emit macros.
3951 * Return -1 otherwise.
3954 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3957 for (i = 0; i < 31; i+= 2) {
3958 res = (val << (32 - i)) | (val >> i);
3961 *rot_amount = i? 32 - i: 0;
3968 * Emits in code a sequence of instructions that load the value 'val'
3969 * into the dreg register. Uses at most 4 instructions.
3972 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3974 int imm8, rot_amount;
3976 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3977 /* skip the constant pool */
3983 if (mini_get_debug_options()->single_imm_size && v7_supported) {
3984 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3985 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3989 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3990 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3991 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3992 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3995 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3997 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4001 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4003 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4005 if (val & 0xFF0000) {
4006 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4008 if (val & 0xFF000000) {
4009 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4011 } else if (val & 0xFF00) {
4012 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4013 if (val & 0xFF0000) {
4014 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4016 if (val & 0xFF000000) {
4017 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4019 } else if (val & 0xFF0000) {
4020 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4021 if (val & 0xFF000000) {
4022 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4025 //g_assert_not_reached ();
4031 mono_arm_thumb_supported (void)
4033 return thumb_supported;
4039 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4044 call = (MonoCallInst*)ins;
4045 cinfo = call->call_info;
4047 switch (cinfo->ret.storage) {
4048 case RegTypeStructByVal:
4050 MonoInst *loc = cfg->arch.vret_addr_loc;
4053 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4054 /* The JIT treats this as a normal call */
4058 /* Load the destination address */
4059 g_assert (loc && loc->opcode == OP_REGOFFSET);
4061 if (arm_is_imm12 (loc->inst_offset)) {
4062 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4064 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4065 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4068 if (cinfo->ret.storage == RegTypeStructByVal) {
4069 int rsize = cinfo->ret.struct_size;
4071 for (i = 0; i < cinfo->ret.nregs; ++i) {
4072 g_assert (rsize >= 0);
4077 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4080 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4083 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4089 for (i = 0; i < cinfo->ret.nregs; ++i) {
4090 if (cinfo->ret.esize == 4)
4091 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4093 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4102 switch (ins->opcode) {
4105 case OP_FCALL_MEMBASE:
4107 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4108 if (sig_ret->type == MONO_TYPE_R4) {
4109 if (IS_HARD_FLOAT) {
4110 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4112 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4113 ARM_CVTS (code, ins->dreg, ins->dreg);
4116 if (IS_HARD_FLOAT) {
4117 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4119 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4126 case OP_RCALL_MEMBASE: {
4131 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4132 g_assert (sig_ret->type == MONO_TYPE_R4);
4133 if (IS_HARD_FLOAT) {
4134 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4136 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4137 ARM_CPYS (code, ins->dreg, ins->dreg);
4149 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4154 guint8 *code = cfg->native_code + cfg->code_len;
4155 MonoInst *last_ins = NULL;
4156 guint last_offset = 0;
4158 int imm8, rot_amount;
4160 /* we don't align basic blocks of loops on arm */
4162 if (cfg->verbose_level > 2)
4163 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4165 cpos = bb->max_offset;
4167 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4168 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4169 //g_assert (!mono_compile_aot);
4172 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4173 /* this is not thread save, but good enough */
4174 /* fixme: howto handle overflows? */
4175 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4178 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4179 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4180 (gpointer)"mono_break");
4181 code = emit_call_seq (cfg, code);
4184 MONO_BB_FOR_EACH_INS (bb, ins) {
4185 offset = code - cfg->native_code;
4187 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4189 if (offset > (cfg->code_size - max_len - 16)) {
4190 cfg->code_size *= 2;
4191 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4192 code = cfg->native_code + offset;
4194 // if (ins->cil_code)
4195 // g_print ("cil code\n");
4196 mono_debug_record_line_number (cfg, ins, offset);
4198 switch (ins->opcode) {
4199 case OP_MEMORY_BARRIER:
4201 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4202 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4206 code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4209 code = emit_tls_set (code, ins->sreg1, ins->inst_offset);
4211 case OP_ATOMIC_EXCHANGE_I4:
4212 case OP_ATOMIC_CAS_I4:
4213 case OP_ATOMIC_ADD_I4: {
4217 g_assert (v7_supported);
4220 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4222 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4224 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4228 g_assert (cfg->arch.atomic_tmp_offset != -1);
4229 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4231 switch (ins->opcode) {
4232 case OP_ATOMIC_EXCHANGE_I4:
4234 ARM_DMB (code, ARM_DMB_SY);
4235 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4236 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4237 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4239 ARM_B_COND (code, ARMCOND_NE, 0);
4240 arm_patch (buf [1], buf [0]);
4242 case OP_ATOMIC_CAS_I4:
4243 ARM_DMB (code, ARM_DMB_SY);
4245 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4246 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4248 ARM_B_COND (code, ARMCOND_NE, 0);
4249 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4250 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4252 ARM_B_COND (code, ARMCOND_NE, 0);
4253 arm_patch (buf [2], buf [0]);
4254 arm_patch (buf [1], code);
4256 case OP_ATOMIC_ADD_I4:
4258 ARM_DMB (code, ARM_DMB_SY);
4259 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4260 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4261 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4262 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4264 ARM_B_COND (code, ARMCOND_NE, 0);
4265 arm_patch (buf [1], buf [0]);
4268 g_assert_not_reached ();
4271 ARM_DMB (code, ARM_DMB_SY);
4272 if (tmpreg != ins->dreg)
4273 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4274 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4277 case OP_ATOMIC_LOAD_I1:
4278 case OP_ATOMIC_LOAD_U1:
4279 case OP_ATOMIC_LOAD_I2:
4280 case OP_ATOMIC_LOAD_U2:
4281 case OP_ATOMIC_LOAD_I4:
4282 case OP_ATOMIC_LOAD_U4:
4283 case OP_ATOMIC_LOAD_R4:
4284 case OP_ATOMIC_LOAD_R8: {
4285 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4286 ARM_DMB (code, ARM_DMB_SY);
4288 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4290 switch (ins->opcode) {
4291 case OP_ATOMIC_LOAD_I1:
4292 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4294 case OP_ATOMIC_LOAD_U1:
4295 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4297 case OP_ATOMIC_LOAD_I2:
4298 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4300 case OP_ATOMIC_LOAD_U2:
4301 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4303 case OP_ATOMIC_LOAD_I4:
4304 case OP_ATOMIC_LOAD_U4:
4305 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4307 case OP_ATOMIC_LOAD_R4:
4309 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4310 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4312 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4313 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4314 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4315 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4316 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4319 case OP_ATOMIC_LOAD_R8:
4320 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4321 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4325 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4326 ARM_DMB (code, ARM_DMB_SY);
4329 case OP_ATOMIC_STORE_I1:
4330 case OP_ATOMIC_STORE_U1:
4331 case OP_ATOMIC_STORE_I2:
4332 case OP_ATOMIC_STORE_U2:
4333 case OP_ATOMIC_STORE_I4:
4334 case OP_ATOMIC_STORE_U4:
4335 case OP_ATOMIC_STORE_R4:
4336 case OP_ATOMIC_STORE_R8: {
4337 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4338 ARM_DMB (code, ARM_DMB_SY);
4340 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4342 switch (ins->opcode) {
4343 case OP_ATOMIC_STORE_I1:
4344 case OP_ATOMIC_STORE_U1:
4345 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4347 case OP_ATOMIC_STORE_I2:
4348 case OP_ATOMIC_STORE_U2:
4349 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4351 case OP_ATOMIC_STORE_I4:
4352 case OP_ATOMIC_STORE_U4:
4353 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4355 case OP_ATOMIC_STORE_R4:
4357 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4358 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4360 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4361 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4362 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4363 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4364 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4367 case OP_ATOMIC_STORE_R8:
4368 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4369 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4373 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4374 ARM_DMB (code, ARM_DMB_SY);
4378 ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4381 ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4383 case OP_STOREI1_MEMBASE_IMM:
4384 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4385 g_assert (arm_is_imm12 (ins->inst_offset));
4386 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4388 case OP_STOREI2_MEMBASE_IMM:
4389 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4390 g_assert (arm_is_imm8 (ins->inst_offset));
4391 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4393 case OP_STORE_MEMBASE_IMM:
4394 case OP_STOREI4_MEMBASE_IMM:
4395 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4396 g_assert (arm_is_imm12 (ins->inst_offset));
4397 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4399 case OP_STOREI1_MEMBASE_REG:
4400 g_assert (arm_is_imm12 (ins->inst_offset));
4401 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4403 case OP_STOREI2_MEMBASE_REG:
4404 g_assert (arm_is_imm8 (ins->inst_offset));
4405 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4407 case OP_STORE_MEMBASE_REG:
4408 case OP_STOREI4_MEMBASE_REG:
4409 /* this case is special, since it happens for spill code after lowering has been called */
4410 if (arm_is_imm12 (ins->inst_offset)) {
4411 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4413 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4414 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4417 case OP_STOREI1_MEMINDEX:
4418 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4420 case OP_STOREI2_MEMINDEX:
4421 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4423 case OP_STORE_MEMINDEX:
4424 case OP_STOREI4_MEMINDEX:
4425 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4428 g_assert_not_reached ();
4430 case OP_LOAD_MEMINDEX:
4431 case OP_LOADI4_MEMINDEX:
4432 case OP_LOADU4_MEMINDEX:
4433 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4435 case OP_LOADI1_MEMINDEX:
4436 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4438 case OP_LOADU1_MEMINDEX:
4439 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4441 case OP_LOADI2_MEMINDEX:
4442 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4444 case OP_LOADU2_MEMINDEX:
4445 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4447 case OP_LOAD_MEMBASE:
4448 case OP_LOADI4_MEMBASE:
4449 case OP_LOADU4_MEMBASE:
4450 /* this case is special, since it happens for spill code after lowering has been called */
4451 if (arm_is_imm12 (ins->inst_offset)) {
4452 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4454 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4455 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4458 case OP_LOADI1_MEMBASE:
4459 g_assert (arm_is_imm8 (ins->inst_offset));
4460 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4462 case OP_LOADU1_MEMBASE:
4463 g_assert (arm_is_imm12 (ins->inst_offset));
4464 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4466 case OP_LOADU2_MEMBASE:
4467 g_assert (arm_is_imm8 (ins->inst_offset));
4468 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4470 case OP_LOADI2_MEMBASE:
4471 g_assert (arm_is_imm8 (ins->inst_offset));
4472 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4474 case OP_ICONV_TO_I1:
4475 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4476 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4478 case OP_ICONV_TO_I2:
4479 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4480 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4482 case OP_ICONV_TO_U1:
4483 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4485 case OP_ICONV_TO_U2:
4486 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4487 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4491 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4493 case OP_COMPARE_IMM:
4494 case OP_ICOMPARE_IMM:
4495 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4496 g_assert (imm8 >= 0);
4497 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4501 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4502 * So instead of emitting a trap, we emit a call a C function and place a
4505 //*(int*)code = 0xef9f0001;
4508 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4509 (gpointer)"mono_break");
4510 code = emit_call_seq (cfg, code);
4512 case OP_RELAXED_NOP:
4517 case OP_DUMMY_STORE:
4518 case OP_DUMMY_ICONST:
4519 case OP_DUMMY_R8CONST:
4520 case OP_NOT_REACHED:
4523 case OP_IL_SEQ_POINT:
4524 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4526 case OP_SEQ_POINT: {
4528 MonoInst *info_var = cfg->arch.seq_point_info_var;
4529 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4530 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4531 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4533 int dreg = ARMREG_LR;
4536 if (cfg->soft_breakpoints) {
4537 g_assert (!cfg->compile_aot);
4542 * For AOT, we use one got slot per method, which will point to a
4543 * SeqPointInfo structure, containing all the information required
4544 * by the code below.
4546 if (cfg->compile_aot) {
4547 g_assert (info_var);
4548 g_assert (info_var->opcode == OP_REGOFFSET);
4549 g_assert (arm_is_imm12 (info_var->inst_offset));
4552 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4554 * Read from the single stepping trigger page. This will cause a
4555 * SIGSEGV when single stepping is enabled.
4556 * We do this _before_ the breakpoint, so single stepping after
4557 * a breakpoint is hit will step to the next IL offset.
4559 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4562 /* Single step check */
4563 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4564 if (cfg->soft_breakpoints) {
4565 /* Load the address of the sequence point method variable. */
4566 var = ss_method_var;
4568 g_assert (var->opcode == OP_REGOFFSET);
4569 g_assert (arm_is_imm12 (var->inst_offset));
4570 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4572 /* Read the value and check whether it is non-zero. */
4573 ARM_LDR_IMM (code, dreg, dreg, 0);
4574 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4575 /* Call it conditionally. */
4576 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4578 if (cfg->compile_aot) {
4579 /* Load the trigger page addr from the variable initialized in the prolog */
4580 var = ss_trigger_page_var;
4582 g_assert (var->opcode == OP_REGOFFSET);
4583 g_assert (arm_is_imm12 (var->inst_offset));
4584 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4586 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4588 *(int*)code = (int)ss_trigger_page;
4591 ARM_LDR_IMM (code, dreg, dreg, 0);
4595 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4597 /* Breakpoint check */
4598 if (cfg->compile_aot) {
4599 guint32 offset = code - cfg->native_code;
4602 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4603 /* Add the offset */
4604 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4605 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4606 if (arm_is_imm12 ((int)val)) {
4607 ARM_LDR_IMM (code, dreg, dreg, val);
4609 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4611 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4613 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4614 g_assert (!(val & 0xFF000000));
4616 ARM_LDR_IMM (code, dreg, dreg, 0);
4618 /* What is faster, a branch or a load ? */
4619 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4620 /* The breakpoint instruction */
4621 if (cfg->soft_breakpoints)
4622 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4624 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4625 } else if (cfg->soft_breakpoints) {
4626 /* Load the address of the breakpoint method into ip. */
4627 var = bp_method_var;
4629 g_assert (var->opcode == OP_REGOFFSET);
4630 g_assert (arm_is_imm12 (var->inst_offset));
4631 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4634 * A placeholder for a possible breakpoint inserted by
4635 * mono_arch_set_breakpoint ().
4640 * A placeholder for a possible breakpoint inserted by
4641 * mono_arch_set_breakpoint ().
4643 for (i = 0; i < 4; ++i)
4648 * Add an additional nop so skipping the bp doesn't cause the ip to point
4649 * to another IL offset.
4657 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4660 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4664 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4667 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4668 g_assert (imm8 >= 0);
4669 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4673 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4674 g_assert (imm8 >= 0);
4675 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4679 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4680 g_assert (imm8 >= 0);
4681 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4684 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4685 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4687 case OP_IADD_OVF_UN:
4688 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4689 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4692 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4693 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4695 case OP_ISUB_OVF_UN:
4696 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4697 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4699 case OP_ADD_OVF_CARRY:
4700 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4701 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4703 case OP_ADD_OVF_UN_CARRY:
4704 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4705 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4707 case OP_SUB_OVF_CARRY:
4708 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4709 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4711 case OP_SUB_OVF_UN_CARRY:
4712 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4713 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4717 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4720 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4721 g_assert (imm8 >= 0);
4722 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4725 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4729 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4733 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4734 g_assert (imm8 >= 0);
4735 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4739 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4740 g_assert (imm8 >= 0);
4741 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4743 case OP_ARM_RSBS_IMM:
4744 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4745 g_assert (imm8 >= 0);
4746 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4748 case OP_ARM_RSC_IMM:
4749 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4750 g_assert (imm8 >= 0);
4751 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4754 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4758 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4759 g_assert (imm8 >= 0);
4760 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4763 g_assert (v7s_supported || v7k_supported);
4764 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4767 g_assert (v7s_supported || v7k_supported);
4768 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4771 g_assert (v7s_supported || v7k_supported);
4772 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4773 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4776 g_assert (v7s_supported || v7k_supported);
4777 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4778 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4782 g_assert_not_reached ();
4784 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4788 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4789 g_assert (imm8 >= 0);
4790 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4793 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4797 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4798 g_assert (imm8 >= 0);
4799 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4802 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4807 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4808 else if (ins->dreg != ins->sreg1)
4809 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4812 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4817 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4818 else if (ins->dreg != ins->sreg1)
4819 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4822 case OP_ISHR_UN_IMM:
4824 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4825 else if (ins->dreg != ins->sreg1)
4826 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4829 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4832 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4835 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4838 if (ins->dreg == ins->sreg2)
4839 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4841 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4844 g_assert_not_reached ();
4847 /* FIXME: handle ovf/ sreg2 != dreg */
4848 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4849 /* FIXME: MUL doesn't set the C/O flags on ARM */
4851 case OP_IMUL_OVF_UN:
4852 /* FIXME: handle ovf/ sreg2 != dreg */
4853 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4854 /* FIXME: MUL doesn't set the C/O flags on ARM */
4857 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4860 /* Load the GOT offset */
4861 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4862 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4864 *(gpointer*)code = NULL;
4866 /* Load the value from the GOT */
4867 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4869 case OP_OBJC_GET_SELECTOR:
4870 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4871 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4873 *(gpointer*)code = NULL;
4875 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4877 case OP_ICONV_TO_I4:
4878 case OP_ICONV_TO_U4:
4880 if (ins->dreg != ins->sreg1)
4881 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4884 int saved = ins->sreg2;
4885 if (ins->sreg2 == ARM_LSW_REG) {
4886 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4889 if (ins->sreg1 != ARM_LSW_REG)
4890 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4891 if (saved != ARM_MSW_REG)
4892 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4896 if (IS_VFP && ins->dreg != ins->sreg1)
4897 ARM_CPYD (code, ins->dreg, ins->sreg1);
4900 if (IS_VFP && ins->dreg != ins->sreg1)
4901 ARM_CPYS (code, ins->dreg, ins->sreg1);
4903 case OP_MOVE_F_TO_I4:
4905 ARM_FMRS (code, ins->dreg, ins->sreg1);
4907 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4908 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4909 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4910 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4913 case OP_MOVE_I4_TO_F:
4915 ARM_FMSR (code, ins->dreg, ins->sreg1);
4917 ARM_FMSR (code, ins->dreg, ins->sreg1);
4918 ARM_CVTS (code, ins->dreg, ins->dreg);
4921 case OP_FCONV_TO_R4:
4924 ARM_CVTD (code, ins->dreg, ins->sreg1);
4926 ARM_CVTD (code, ins->dreg, ins->sreg1);
4927 ARM_CVTS (code, ins->dreg, ins->dreg);
4932 MonoCallInst *call = (MonoCallInst*)ins;
4935 * The stack looks like the following:
4936 * <caller argument area>
4939 * <callee argument area>
4940 * Need to copy the arguments from the callee argument area to
4941 * the caller argument area, and pop the frame.
4943 if (call->stack_usage) {
4944 int i, prev_sp_offset = 0;
4946 /* Compute size of saved registers restored below */
4948 prev_sp_offset = 2 * 4;
4950 prev_sp_offset = 1 * 4;
4951 for (i = 0; i < 16; ++i) {
4952 if (cfg->used_int_regs & (1 << i))
4953 prev_sp_offset += 4;
4956 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4958 /* Copy arguments on the stack to our argument area */
4959 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4960 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4961 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4966 * Keep in sync with mono_arch_emit_epilog
4968 g_assert (!cfg->method->save_lmf);
4970 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4972 if (cfg->used_int_regs)
4973 ARM_POP (code, cfg->used_int_regs);
4974 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4976 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4979 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4980 if (cfg->compile_aot) {
4981 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4983 *(gpointer*)code = NULL;
4985 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4987 code = mono_arm_patchable_b (code, ARMCOND_AL);
4988 cfg->thunk_area += THUNK_SIZE;
4993 /* ensure ins->sreg1 is not NULL */
4994 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4997 g_assert (cfg->sig_cookie < 128);
4998 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4999 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5009 call = (MonoCallInst*)ins;
5012 code = emit_float_args (cfg, call, code, &max_len, &offset);
5014 if (ins->flags & MONO_INST_HAS_METHOD)
5015 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5017 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5018 code = emit_call_seq (cfg, code);
5019 ins->flags |= MONO_INST_GC_CALLSITE;
5020 ins->backend.pc_offset = code - cfg->native_code;
5021 code = emit_move_return_value (cfg, ins, code);
5028 case OP_VOIDCALL_REG:
5031 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5033 code = emit_call_reg (code, ins->sreg1);
5034 ins->flags |= MONO_INST_GC_CALLSITE;
5035 ins->backend.pc_offset = code - cfg->native_code;
5036 code = emit_move_return_value (cfg, ins, code);
5038 case OP_FCALL_MEMBASE:
5039 case OP_RCALL_MEMBASE:
5040 case OP_LCALL_MEMBASE:
5041 case OP_VCALL_MEMBASE:
5042 case OP_VCALL2_MEMBASE:
5043 case OP_VOIDCALL_MEMBASE:
5044 case OP_CALL_MEMBASE: {
5045 g_assert (ins->sreg1 != ARMREG_LR);
5046 call = (MonoCallInst*)ins;
5049 code = emit_float_args (cfg, call, code, &max_len, &offset);
5050 if (!arm_is_imm12 (ins->inst_offset)) {
5051 /* sreg1 might be IP */
5052 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5053 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5054 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5055 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5056 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5058 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5059 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5061 ins->flags |= MONO_INST_GC_CALLSITE;
5062 ins->backend.pc_offset = code - cfg->native_code;
5063 code = emit_move_return_value (cfg, ins, code);
5066 case OP_GENERIC_CLASS_INIT: {
5070 byte_offset = MONO_STRUCT_OFFSET (MonoVTable, initialized);
5072 g_assert (arm_is_imm8 (byte_offset));
5073 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5074 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5076 ARM_B_COND (code, ARMCOND_NE, 0);
5078 /* Uninitialized case */
5079 g_assert (ins->sreg1 == ARMREG_R0);
5081 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5082 (gpointer)"mono_generic_class_init");
5083 code = emit_call_seq (cfg, code);
5085 /* Initialized case */
5086 arm_patch (jump, code);
5090 /* round the size to 8 bytes */
5091 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5092 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5093 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5094 /* memzero the area: dreg holds the size, sp is the pointer */
5095 if (ins->flags & MONO_INST_INIT) {
5096 guint8 *start_loop, *branch_to_cond;
5097 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5098 branch_to_cond = code;
5101 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5102 arm_patch (branch_to_cond, code);
5103 /* decrement by 4 and set flags */
5104 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5105 ARM_B_COND (code, ARMCOND_GE, 0);
5106 arm_patch (code - 4, start_loop);
5108 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5109 if (cfg->param_area)
5110 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5115 MonoInst *var = cfg->dyn_call_var;
5118 g_assert (var->opcode == OP_REGOFFSET);
5119 g_assert (arm_is_imm12 (var->inst_offset));
5121 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5122 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5124 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5126 /* Save args buffer */
5127 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5129 /* Set stack slots using R0 as scratch reg */
5130 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5131 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5132 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5133 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5136 /* Set fp argument registers */
5137 if (IS_HARD_FLOAT) {
5138 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5139 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5141 ARM_B_COND (code, ARMCOND_EQ, 0);
5142 for (i = 0; i < FP_PARAM_REGS; ++i) {
5143 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5144 g_assert (arm_is_fpimm8 (offset));
5145 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5147 arm_patch (buf [0], code);
5150 /* Set argument registers */
5151 for (i = 0; i < PARAM_REGS; ++i)
5152 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5155 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5156 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5159 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5160 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5161 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5163 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5167 if (ins->sreg1 != ARMREG_R0)
5168 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5169 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5170 (gpointer)"mono_arch_throw_exception");
5171 code = emit_call_seq (cfg, code);
5175 if (ins->sreg1 != ARMREG_R0)
5176 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5177 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5178 (gpointer)"mono_arch_rethrow_exception");
5179 code = emit_call_seq (cfg, code);
5182 case OP_START_HANDLER: {
5183 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5184 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5187 /* Reserve a param area, see filter-stack.exe */
5189 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5190 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5192 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5193 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5197 if (arm_is_imm12 (spvar->inst_offset)) {
5198 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5200 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5201 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5205 case OP_ENDFILTER: {
5206 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5207 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5210 /* Free the param area */
5212 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5213 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5215 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5216 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5220 if (ins->sreg1 != ARMREG_R0)
5221 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5222 if (arm_is_imm12 (spvar->inst_offset)) {
5223 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5225 g_assert (ARMREG_IP != spvar->inst_basereg);
5226 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5227 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5229 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5232 case OP_ENDFINALLY: {
5233 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5234 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5237 /* Free the param area */
5239 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5240 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5242 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5243 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5247 if (arm_is_imm12 (spvar->inst_offset)) {
5248 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5250 g_assert (ARMREG_IP != spvar->inst_basereg);
5251 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5252 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5254 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5257 case OP_CALL_HANDLER:
5258 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5259 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5260 cfg->thunk_area += THUNK_SIZE;
5261 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5264 if (ins->dreg != ARMREG_R0)
5265 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5269 ins->inst_c0 = code - cfg->native_code;
5272 /*if (ins->inst_target_bb->native_offset) {
5274 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5276 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5277 code = mono_arm_patchable_b (code, ARMCOND_AL);
5281 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5285 * In the normal case we have:
5286 * ldr pc, [pc, ins->sreg1 << 2]
5289 * ldr lr, [pc, ins->sreg1 << 2]
5291 * After follows the data.
5292 * FIXME: add aot support.
5294 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5295 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5296 if (offset + max_len > (cfg->code_size - 16)) {
5297 cfg->code_size += max_len;
5298 cfg->code_size *= 2;
5299 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5300 code = cfg->native_code + offset;
5302 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5304 code += 4 * GPOINTER_TO_INT (ins->klass);
5308 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5309 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5313 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5314 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5318 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5319 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5323 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5324 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5328 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5329 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5332 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5333 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5336 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5337 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5340 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5341 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5344 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5345 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5348 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5349 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5351 case OP_COND_EXC_EQ:
5352 case OP_COND_EXC_NE_UN:
5353 case OP_COND_EXC_LT:
5354 case OP_COND_EXC_LT_UN:
5355 case OP_COND_EXC_GT:
5356 case OP_COND_EXC_GT_UN:
5357 case OP_COND_EXC_GE:
5358 case OP_COND_EXC_GE_UN:
5359 case OP_COND_EXC_LE:
5360 case OP_COND_EXC_LE_UN:
5361 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5363 case OP_COND_EXC_IEQ:
5364 case OP_COND_EXC_INE_UN:
5365 case OP_COND_EXC_ILT:
5366 case OP_COND_EXC_ILT_UN:
5367 case OP_COND_EXC_IGT:
5368 case OP_COND_EXC_IGT_UN:
5369 case OP_COND_EXC_IGE:
5370 case OP_COND_EXC_IGE_UN:
5371 case OP_COND_EXC_ILE:
5372 case OP_COND_EXC_ILE_UN:
5373 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5376 case OP_COND_EXC_IC:
5377 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5379 case OP_COND_EXC_OV:
5380 case OP_COND_EXC_IOV:
5381 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5383 case OP_COND_EXC_NC:
5384 case OP_COND_EXC_INC:
5385 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5387 case OP_COND_EXC_NO:
5388 case OP_COND_EXC_INO:
5389 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5401 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5404 /* floating point opcodes */
5406 if (cfg->compile_aot) {
5407 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5409 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5411 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5414 /* FIXME: we can optimize the imm load by dealing with part of
5415 * the displacement in LDFD (aligning to 512).
5417 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5418 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5422 if (cfg->compile_aot) {
5423 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5425 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5428 ARM_CVTS (code, ins->dreg, ins->dreg);
5430 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5431 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5433 ARM_CVTS (code, ins->dreg, ins->dreg);
5436 case OP_STORER8_MEMBASE_REG:
5437 /* This is generated by the local regalloc pass which runs after the lowering pass */
5438 if (!arm_is_fpimm8 (ins->inst_offset)) {
5439 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5440 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5441 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5443 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5446 case OP_LOADR8_MEMBASE:
5447 /* This is generated by the local regalloc pass which runs after the lowering pass */
5448 if (!arm_is_fpimm8 (ins->inst_offset)) {
5449 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5450 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5451 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5453 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5456 case OP_STORER4_MEMBASE_REG:
5457 g_assert (arm_is_fpimm8 (ins->inst_offset));
5459 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5461 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5462 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5463 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5464 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5467 case OP_LOADR4_MEMBASE:
5469 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5471 g_assert (arm_is_fpimm8 (ins->inst_offset));
5472 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5473 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5474 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5475 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5478 case OP_ICONV_TO_R_UN: {
5479 g_assert_not_reached ();
5482 case OP_ICONV_TO_R4:
5484 ARM_FMSR (code, ins->dreg, ins->sreg1);
5485 ARM_FSITOS (code, ins->dreg, ins->dreg);
5487 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5488 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5489 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5490 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5491 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5494 case OP_ICONV_TO_R8:
5495 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5496 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5497 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5498 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5502 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5503 if (sig_ret->type == MONO_TYPE_R4) {
5505 if (IS_HARD_FLOAT) {
5506 if (ins->sreg1 != ARM_VFP_D0)
5507 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5509 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5512 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5515 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5519 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5521 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5525 case OP_FCONV_TO_I1:
5526 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5528 case OP_FCONV_TO_U1:
5529 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5531 case OP_FCONV_TO_I2:
5532 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5534 case OP_FCONV_TO_U2:
5535 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5537 case OP_FCONV_TO_I4:
5539 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5541 case OP_FCONV_TO_U4:
5543 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5545 case OP_FCONV_TO_I8:
5546 case OP_FCONV_TO_U8:
5547 g_assert_not_reached ();
5548 /* Implemented as helper calls */
5550 case OP_LCONV_TO_R_UN:
5551 g_assert_not_reached ();
5552 /* Implemented as helper calls */
5554 case OP_LCONV_TO_OVF_I4_2: {
5555 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5557 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5560 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5561 high_bit_not_set = code;
5562 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5564 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5565 valid_negative = code;
5566 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5567 invalid_negative = code;
5568 ARM_B_COND (code, ARMCOND_AL, 0);
5570 arm_patch (high_bit_not_set, code);
5572 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5573 valid_positive = code;
5574 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5576 arm_patch (invalid_negative, code);
5577 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5579 arm_patch (valid_negative, code);
5580 arm_patch (valid_positive, code);
5582 if (ins->dreg != ins->sreg1)
5583 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5587 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5590 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5593 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5596 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5599 ARM_NEGD (code, ins->dreg, ins->sreg1);
5603 g_assert_not_reached ();
5607 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5613 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5618 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5621 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5622 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5626 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5629 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5630 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5634 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5637 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5638 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5639 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5643 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5646 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5647 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5651 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5654 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5655 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5656 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5660 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5663 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5664 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5668 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5671 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5672 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5676 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5679 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5680 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5683 /* ARM FPA flags table:
5684 * N Less than ARMCOND_MI
5685 * Z Equal ARMCOND_EQ
5686 * C Greater Than or Equal ARMCOND_CS
5687 * V Unordered ARMCOND_VS
5690 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5693 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5696 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5699 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5700 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5706 g_assert_not_reached ();
5710 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5712 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5713 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5714 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5718 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5719 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5724 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5725 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5727 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5728 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5730 *(guint32*)code = 0xffffffff;
5732 *(guint32*)code = 0x7fefffff;
5734 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5736 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5737 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5739 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5740 ARM_CPYD (code, ins->dreg, ins->sreg1);
5742 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5743 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5748 case OP_RCONV_TO_I1:
5749 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5751 case OP_RCONV_TO_U1:
5752 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5754 case OP_RCONV_TO_I2:
5755 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5757 case OP_RCONV_TO_U2:
5758 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5760 case OP_RCONV_TO_I4:
5761 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5763 case OP_RCONV_TO_U4:
5764 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5766 case OP_RCONV_TO_R4:
5768 if (ins->dreg != ins->sreg1)
5769 ARM_CPYS (code, ins->dreg, ins->sreg1);
5771 case OP_RCONV_TO_R8:
5773 ARM_CVTS (code, ins->dreg, ins->sreg1);
5776 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5779 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5782 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5785 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5788 ARM_NEGS (code, ins->dreg, ins->sreg1);
5792 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5795 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5796 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5800 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5803 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5804 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5808 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5811 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5812 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5813 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5817 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5820 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5821 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5825 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5828 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5829 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5830 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5834 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5837 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5838 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5842 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5845 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5846 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5850 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5853 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5854 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5857 case OP_GC_LIVENESS_DEF:
5858 case OP_GC_LIVENESS_USE:
5859 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5860 ins->backend.pc_offset = code - cfg->native_code;
5862 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5863 ins->backend.pc_offset = code - cfg->native_code;
5864 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5866 case OP_GC_SAFE_POINT: {
5869 g_assert (mono_threads_is_coop_enabled ());
5871 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5872 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5874 ARM_B_COND (code, ARMCOND_EQ, 0);
5875 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5876 code = emit_call_seq (cfg, code);
5877 arm_patch (buf [0], code);
5882 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5883 g_assert_not_reached ();
5886 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5887 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5888 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5889 g_assert_not_reached ();
5895 last_offset = offset;
5898 cfg->code_len = code - cfg->native_code;
5901 #endif /* DISABLE_JIT */
5904 mono_arch_register_lowlevel_calls (void)
5906 /* The signature doesn't matter */
5907 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5908 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5909 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5912 #define patch_lis_ori(ip,val) do {\
5913 guint16 *__lis_ori = (guint16*)(ip); \
5914 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5915 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5919 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5921 unsigned char *ip = ji->ip.i + code;
5923 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5927 case MONO_PATCH_INFO_SWITCH: {
5928 gpointer *jt = (gpointer*)(ip + 8);
5930 /* jt is the inlined jump table, 2 instructions after ip
5931 * In the normal case we store the absolute addresses,
5932 * otherwise the displacements.
5934 for (i = 0; i < ji->data.table->table_size; i++)
5935 jt [i] = code + (int)ji->data.table->table [i];
5938 case MONO_PATCH_INFO_IP:
5939 g_assert_not_reached ();
5940 patch_lis_ori (ip, ip);
5942 case MONO_PATCH_INFO_METHOD_REL:
5943 g_assert_not_reached ();
5944 *((gpointer *)(ip)) = target;
5946 case MONO_PATCH_INFO_METHODCONST:
5947 case MONO_PATCH_INFO_CLASS:
5948 case MONO_PATCH_INFO_IMAGE:
5949 case MONO_PATCH_INFO_FIELD:
5950 case MONO_PATCH_INFO_VTABLE:
5951 case MONO_PATCH_INFO_IID:
5952 case MONO_PATCH_INFO_SFLDA:
5953 case MONO_PATCH_INFO_LDSTR:
5954 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5955 case MONO_PATCH_INFO_LDTOKEN:
5956 g_assert_not_reached ();
5957 /* from OP_AOTCONST : lis + ori */
5958 patch_lis_ori (ip, target);
5960 case MONO_PATCH_INFO_R4:
5961 case MONO_PATCH_INFO_R8:
5962 g_assert_not_reached ();
5963 *((gconstpointer *)(ip + 2)) = target;
5965 case MONO_PATCH_INFO_EXC_NAME:
5966 g_assert_not_reached ();
5967 *((gconstpointer *)(ip + 1)) = target;
5969 case MONO_PATCH_INFO_NONE:
5970 case MONO_PATCH_INFO_BB_OVF:
5971 case MONO_PATCH_INFO_EXC_OVF:
5972 /* everything is dealt with at epilog output time */
5975 arm_patch_general (cfg, domain, ip, target);
5981 mono_arm_unaligned_stack (MonoMethod *method)
5983 g_assert_not_reached ();
5989 * Stack frame layout:
5991 * ------------------- fp
5992 * MonoLMF structure or saved registers
5993 * -------------------
5995 * -------------------
5997 * -------------------
5998 * optional 8 bytes for tracing
5999 * -------------------
6000 * param area size is cfg->param_area
6001 * ------------------- sp
6004 mono_arch_emit_prolog (MonoCompile *cfg)
6006 MonoMethod *method = cfg->method;
6008 MonoMethodSignature *sig;
6010 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6015 int prev_sp_offset, reg_offset;
6017 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6020 sig = mono_method_signature (method);
6021 cfg->code_size = 256 + sig->param_count * 64;
6022 code = cfg->native_code = g_malloc (cfg->code_size);
6024 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6026 alloc_size = cfg->stack_offset;
6032 * The iphone uses R7 as the frame pointer, and it points at the saved
6037 * We can't use r7 as a frame pointer since it points into the middle of
6038 * the frame, so we keep using our own frame pointer.
6039 * FIXME: Optimize this.
6041 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6042 prev_sp_offset += 8; /* r7 and lr */
6043 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6044 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6045 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6048 if (!method->save_lmf) {
6050 /* No need to push LR again */
6051 if (cfg->used_int_regs)
6052 ARM_PUSH (code, cfg->used_int_regs);
6054 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6055 prev_sp_offset += 4;
6057 for (i = 0; i < 16; ++i) {
6058 if (cfg->used_int_regs & (1 << i))
6059 prev_sp_offset += 4;
6061 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6063 for (i = 0; i < 16; ++i) {
6064 if ((cfg->used_int_regs & (1 << i))) {
6065 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6066 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6070 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6071 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6073 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6074 ARM_PUSH (code, 0x5ff0);
6075 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6076 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6078 for (i = 0; i < 16; ++i) {
6079 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6080 /* The original r7 is saved at the start */
6081 if (!(iphone_abi && i == ARMREG_R7))
6082 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6086 g_assert (reg_offset == 4 * 10);
6087 pos += sizeof (MonoLMF) - (4 * 10);
6091 orig_alloc_size = alloc_size;
6092 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6093 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6094 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6095 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6098 /* the stack used in the pushed regs */
6099 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6100 cfg->stack_usage = alloc_size;
6102 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6103 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6105 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6106 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6108 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6110 if (cfg->frame_reg != ARMREG_SP) {
6111 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6112 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6114 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6115 prev_sp_offset += alloc_size;
6117 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6118 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6120 /* compute max_offset in order to use short forward jumps
6121 * we could skip do it on arm because the immediate displacement
6122 * for jumps is large enough, it may be useful later for constant pools
6125 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6126 MonoInst *ins = bb->code;
6127 bb->max_offset = max_offset;
6129 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6132 MONO_BB_FOR_EACH_INS (bb, ins)
6133 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6136 /* stack alignment check */
6140 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6141 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6142 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6143 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6145 ARM_B_COND (code, ARMCOND_EQ, 0);
6146 if (cfg->compile_aot)
6147 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6149 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6150 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6151 code = emit_call_seq (cfg, code);
6152 arm_patch (buf [0], code);
6156 /* store runtime generic context */
6157 if (cfg->rgctx_var) {
6158 MonoInst *ins = cfg->rgctx_var;
6160 g_assert (ins->opcode == OP_REGOFFSET);
6162 if (arm_is_imm12 (ins->inst_offset)) {
6163 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6165 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6166 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6170 /* load arguments allocated to register from the stack */
6173 cinfo = get_call_info (NULL, sig);
6175 if (cinfo->ret.storage == RegTypeStructByAddr) {
6176 ArgInfo *ainfo = &cinfo->ret;
6177 inst = cfg->vret_addr;
6178 g_assert (arm_is_imm12 (inst->inst_offset));
6179 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6182 if (sig->call_convention == MONO_CALL_VARARG) {
6183 ArgInfo *cookie = &cinfo->sig_cookie;
6185 /* Save the sig cookie address */
6186 g_assert (cookie->storage == RegTypeBase);
6188 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6189 g_assert (arm_is_imm12 (cfg->sig_cookie));
6190 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6191 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6194 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6195 ArgInfo *ainfo = cinfo->args + i;
6196 inst = cfg->args [pos];
6198 if (cfg->verbose_level > 2)
6199 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6201 if (inst->opcode == OP_REGVAR) {
6202 if (ainfo->storage == RegTypeGeneral)
6203 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6204 else if (ainfo->storage == RegTypeFP) {
6205 g_assert_not_reached ();
6206 } else if (ainfo->storage == RegTypeBase) {
6207 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6208 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6210 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6211 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6214 g_assert_not_reached ();
6216 if (cfg->verbose_level > 2)
6217 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6219 switch (ainfo->storage) {
6221 for (part = 0; part < ainfo->nregs; part ++) {
6222 if (ainfo->esize == 4)
6223 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6225 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6228 case RegTypeGeneral:
6229 case RegTypeIRegPair:
6230 case RegTypeGSharedVtInReg:
6231 case RegTypeStructByAddr:
6232 switch (ainfo->size) {
6234 if (arm_is_imm12 (inst->inst_offset))
6235 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6237 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6238 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6242 if (arm_is_imm8 (inst->inst_offset)) {
6243 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6245 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6246 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6250 if (arm_is_imm12 (inst->inst_offset)) {
6251 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6253 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6254 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6256 if (arm_is_imm12 (inst->inst_offset + 4)) {
6257 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6259 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6260 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6264 if (arm_is_imm12 (inst->inst_offset)) {
6265 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6267 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6268 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6273 case RegTypeBaseGen:
6274 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6275 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6277 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6278 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6280 if (arm_is_imm12 (inst->inst_offset + 4)) {
6281 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6282 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6284 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6285 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6286 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6287 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6291 case RegTypeGSharedVtOnStack:
6292 case RegTypeStructByAddrOnStack:
6293 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6294 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6296 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6297 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6300 switch (ainfo->size) {
6302 if (arm_is_imm8 (inst->inst_offset)) {
6303 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6305 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6306 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6310 if (arm_is_imm8 (inst->inst_offset)) {
6311 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6313 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6314 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6318 if (arm_is_imm12 (inst->inst_offset)) {
6319 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6321 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6322 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6324 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6325 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6327 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6328 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6330 if (arm_is_imm12 (inst->inst_offset + 4)) {
6331 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6333 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6334 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6338 if (arm_is_imm12 (inst->inst_offset)) {
6339 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6341 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6342 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6348 int imm8, rot_amount;
6350 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6351 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6352 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6354 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6356 if (ainfo->size == 8)
6357 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6359 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6362 case RegTypeStructByVal: {
6363 int doffset = inst->inst_offset;
6367 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6368 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6369 if (arm_is_imm12 (doffset)) {
6370 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6372 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6373 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6375 soffset += sizeof (gpointer);
6376 doffset += sizeof (gpointer);
6378 if (ainfo->vtsize) {
6379 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6380 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6381 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6386 g_assert_not_reached ();
6393 if (method->save_lmf)
6394 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6397 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6399 if (cfg->arch.seq_point_info_var) {
6400 MonoInst *ins = cfg->arch.seq_point_info_var;
6402 /* Initialize the variable from a GOT slot */
6403 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6404 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6406 *(gpointer*)code = NULL;
6408 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6410 g_assert (ins->opcode == OP_REGOFFSET);
6412 if (arm_is_imm12 (ins->inst_offset)) {
6413 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6415 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6416 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6420 /* Initialize ss_trigger_page_var */
6421 if (!cfg->soft_breakpoints) {
6422 MonoInst *info_var = cfg->arch.seq_point_info_var;
6423 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6424 int dreg = ARMREG_LR;
6427 g_assert (info_var->opcode == OP_REGOFFSET);
6428 g_assert (arm_is_imm12 (info_var->inst_offset));
6430 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6431 /* Load the trigger page addr */
6432 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6433 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6437 if (cfg->arch.seq_point_ss_method_var) {
6438 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6439 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6441 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6442 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6444 if (cfg->compile_aot) {
6445 MonoInst *info_var = cfg->arch.seq_point_info_var;
6446 int dreg = ARMREG_LR;
6448 g_assert (info_var->opcode == OP_REGOFFSET);
6449 g_assert (arm_is_imm12 (info_var->inst_offset));
6451 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6452 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
6453 ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6455 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6456 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6458 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6460 *(gpointer*)code = &single_step_tramp;
6462 *(gpointer*)code = breakpoint_tramp;
6465 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6466 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6467 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6468 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6472 cfg->code_len = code - cfg->native_code;
6473 g_assert (cfg->code_len < cfg->code_size);
6480 mono_arch_emit_epilog (MonoCompile *cfg)
6482 MonoMethod *method = cfg->method;
6483 int pos, i, rot_amount;
6484 int max_epilog_size = 16 + 20*4;
6488 if (cfg->method->save_lmf)
6489 max_epilog_size += 128;
6491 if (mono_jit_trace_calls != NULL)
6492 max_epilog_size += 50;
6494 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6495 max_epilog_size += 50;
6497 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6498 cfg->code_size *= 2;
6499 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6500 cfg->stat_code_reallocs++;
6504 * Keep in sync with OP_JMP
6506 code = cfg->native_code + cfg->code_len;
6508 /* Save the uwind state which is needed by the out-of-line code */
6509 mono_emit_unwind_op_remember_state (cfg, code);
6511 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6512 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6516 /* Load returned vtypes into registers if needed */
6517 cinfo = cfg->arch.cinfo;
6518 switch (cinfo->ret.storage) {
6519 case RegTypeStructByVal: {
6520 MonoInst *ins = cfg->ret;
6522 if (cinfo->ret.nregs == 1) {
6523 if (arm_is_imm12 (ins->inst_offset)) {
6524 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6526 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6527 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6530 for (i = 0; i < cinfo->ret.nregs; ++i) {
6531 int offset = ins->inst_offset + (i * 4);
6532 if (arm_is_imm12 (offset)) {
6533 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6535 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6536 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6543 MonoInst *ins = cfg->ret;
6545 for (i = 0; i < cinfo->ret.nregs; ++i) {
6546 if (cinfo->ret.esize == 4)
6547 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6549 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6557 if (method->save_lmf) {
6558 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6559 /* all but r0-r3, sp and pc */
6560 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6563 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6565 /* This points to r4 inside MonoLMF->iregs */
6566 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6568 regmask = 0x9ff0; /* restore lr to pc */
6569 /* Skip caller saved registers not used by the method */
6570 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6571 regmask &= ~(1 << reg);
6576 /* Restored later */
6577 regmask &= ~(1 << ARMREG_PC);
6578 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6579 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6580 for (i = 0; i < 16; i++) {
6581 if (regmask & (1 << i))
6584 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6586 ARM_POP (code, regmask);
6588 for (i = 0; i < 16; i++) {
6589 if (regmask & (1 << i))
6590 mono_emit_unwind_op_same_value (cfg, code, i);
6592 /* Restore saved r7, restore LR to PC */
6593 /* Skip lr from the lmf */
6594 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6595 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6596 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6597 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6600 int i, nused_int_regs = 0;
6602 for (i = 0; i < 16; i++) {
6603 if (cfg->used_int_regs & (1 << i))
6607 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6608 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6610 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6611 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6614 if (cfg->frame_reg != ARMREG_SP) {
6615 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6619 /* Restore saved gregs */
6620 if (cfg->used_int_regs) {
6621 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6622 ARM_POP (code, cfg->used_int_regs);
6623 for (i = 0; i < 16; i++) {
6624 if (cfg->used_int_regs & (1 << i))
6625 mono_emit_unwind_op_same_value (cfg, code, i);
6628 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6629 /* Restore saved r7, restore LR to PC */
6630 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6632 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6633 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6637 /* Restore the unwind state to be the same as before the epilog */
6638 mono_emit_unwind_op_restore_state (cfg, code);
6640 cfg->code_len = code - cfg->native_code;
6642 g_assert (cfg->code_len < cfg->code_size);
6647 mono_arch_emit_exceptions (MonoCompile *cfg)
6649 MonoJumpInfo *patch_info;
6652 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6653 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6654 int max_epilog_size = 50;
6656 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6657 exc_throw_pos [i] = NULL;
6658 exc_throw_found [i] = 0;
6661 /* count the number of exception infos */
6664 * make sure we have enough space for exceptions
6666 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6667 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6668 i = mini_exception_id_by_name (patch_info->data.target);
6669 if (!exc_throw_found [i]) {
6670 max_epilog_size += 32;
6671 exc_throw_found [i] = TRUE;
6676 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6677 cfg->code_size *= 2;
6678 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6679 cfg->stat_code_reallocs++;
6682 code = cfg->native_code + cfg->code_len;
6684 /* add code to raise exceptions */
6685 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6686 switch (patch_info->type) {
6687 case MONO_PATCH_INFO_EXC: {
6688 MonoClass *exc_class;
6689 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6691 i = mini_exception_id_by_name (patch_info->data.target);
6692 if (exc_throw_pos [i]) {
6693 arm_patch (ip, exc_throw_pos [i]);
6694 patch_info->type = MONO_PATCH_INFO_NONE;
6697 exc_throw_pos [i] = code;
6699 arm_patch (ip, code);
6701 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6703 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6704 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6705 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6706 patch_info->data.name = "mono_arch_throw_corlib_exception";
6707 patch_info->ip.i = code - cfg->native_code;
6709 cfg->thunk_area += THUNK_SIZE;
6710 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6720 cfg->code_len = code - cfg->native_code;
6722 g_assert (cfg->code_len < cfg->code_size);
6726 #endif /* #ifndef DISABLE_JIT */
6729 mono_arch_finish_init (void)
6734 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6739 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6746 mono_arch_print_tree (MonoInst *tree, int arity)
6756 mono_arch_get_patch_offset (guint8 *code)
6763 mono_arch_flush_register_windows (void)
6768 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6770 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6774 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6776 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6780 mono_arch_get_cie_program (void)
6784 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6789 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6790 #define BASE_SIZE (6 * 4)
6791 #define BSEARCH_ENTRY_SIZE (4 * 4)
6792 #define CMP_SIZE (3 * 4)
6793 #define BRANCH_SIZE (1 * 4)
6794 #define CALL_SIZE (2 * 4)
6795 #define WMC_SIZE (8 * 4)
6796 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6799 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6801 guint32 delta = DISTANCE (target, code);
6803 g_assert (delta >= 0 && delta <= 0xFFF);
6804 *target = *target | delta;
6809 #ifdef ENABLE_WRONG_METHOD_CHECK
6811 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6813 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6819 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6820 gpointer fail_tramp)
6823 arminstr_t *code, *start;
6824 gboolean large_offsets = FALSE;
6825 guint32 **constant_pool_starts;
6826 arminstr_t *vtable_target = NULL;
6827 int extra_space = 0;
6828 #ifdef ENABLE_WRONG_METHOD_CHECK
6834 constant_pool_starts = g_new0 (guint32*, count);
6836 for (i = 0; i < count; ++i) {
6837 MonoIMTCheckItem *item = imt_entries [i];
6838 if (item->is_equals) {
6839 gboolean fail_case = !item->check_target_idx && fail_tramp;
6841 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6842 item->chunk_size += 32;
6843 large_offsets = TRUE;
6846 if (item->check_target_idx || fail_case) {
6847 if (!item->compare_done || fail_case)
6848 item->chunk_size += CMP_SIZE;
6849 item->chunk_size += BRANCH_SIZE;
6851 #ifdef ENABLE_WRONG_METHOD_CHECK
6852 item->chunk_size += WMC_SIZE;
6856 item->chunk_size += 16;
6857 large_offsets = TRUE;
6859 item->chunk_size += CALL_SIZE;
6861 item->chunk_size += BSEARCH_ENTRY_SIZE;
6862 imt_entries [item->check_target_idx]->compare_done = TRUE;
6864 size += item->chunk_size;
6868 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6871 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
6873 code = mono_domain_code_reserve (domain, size);
6876 unwind_ops = mono_arch_get_cie_program ();
6879 g_print ("Building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6880 for (i = 0; i < count; ++i) {
6881 MonoIMTCheckItem *item = imt_entries [i];
6882 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6886 if (large_offsets) {
6887 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6888 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6890 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6891 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6893 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6894 vtable_target = code;
6895 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6896 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6898 for (i = 0; i < count; ++i) {
6899 MonoIMTCheckItem *item = imt_entries [i];
6900 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6901 gint32 vtable_offset;
6903 item->code_target = (guint8*)code;
6905 if (item->is_equals) {
6906 gboolean fail_case = !item->check_target_idx && fail_tramp;
6908 if (item->check_target_idx || fail_case) {
6909 if (!item->compare_done || fail_case) {
6911 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6912 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6914 item->jmp_code = (guint8*)code;
6915 ARM_B_COND (code, ARMCOND_NE, 0);
6917 /*Enable the commented code to assert on wrong method*/
6918 #ifdef ENABLE_WRONG_METHOD_CHECK
6920 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6921 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6923 ARM_B_COND (code, ARMCOND_EQ, 0);
6925 /* Define this if your system is so bad that gdb is failing. */
6926 #ifdef BROKEN_DEV_ENV
6927 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6929 arm_patch (code - 1, mini_dump_bad_imt);
6933 arm_patch (cond, code);
6937 if (item->has_target_code) {
6938 /* Load target address */
6939 target_code_ins = code;
6940 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6941 /* Save it to the fourth slot */
6942 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6943 /* Restore registers and branch */
6944 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6946 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
6948 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
6949 if (!arm_is_imm12 (vtable_offset)) {
6951 * We need to branch to a computed address but we don't have
6952 * a free register to store it, since IP must contain the
6953 * vtable address. So we push the two values to the stack, and
6954 * load them both using LDM.
6956 /* Compute target address */
6957 vtable_offset_ins = code;
6958 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6959 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
6960 /* Save it to the fourth slot */
6961 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6962 /* Restore registers and branch */
6963 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6965 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
6967 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
6968 if (large_offsets) {
6969 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6970 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
6972 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
6973 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
6978 arm_patch (item->jmp_code, (guchar*)code);
6980 target_code_ins = code;
6981 /* Load target address */
6982 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6983 /* Save it to the fourth slot */
6984 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6985 /* Restore registers and branch */
6986 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6988 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
6989 item->jmp_code = NULL;
6993 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
6995 /*must emit after unconditional branch*/
6996 if (vtable_target) {
6997 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
6998 item->chunk_size += 4;
6999 vtable_target = NULL;
7002 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7003 constant_pool_starts [i] = code;
7005 code += extra_space;
7009 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7010 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7012 item->jmp_code = (guint8*)code;
7013 ARM_B_COND (code, ARMCOND_HS, 0);
7018 for (i = 0; i < count; ++i) {
7019 MonoIMTCheckItem *item = imt_entries [i];
7020 if (item->jmp_code) {
7021 if (item->check_target_idx)
7022 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7024 if (i > 0 && item->is_equals) {
7026 arminstr_t *space_start = constant_pool_starts [i];
7027 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7028 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7035 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7036 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7041 g_free (constant_pool_starts);
7043 mono_arch_flush_icache ((guint8*)start, size);
7044 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7045 mono_stats.imt_trampolines_size += code - start;
7047 g_assert (DISTANCE (start, code) <= size);
7049 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7055 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7057 return ctx->regs [reg];
7061 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7063 ctx->regs [reg] = val;
7067 * mono_arch_get_trampolines:
7069 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7073 mono_arch_get_trampolines (gboolean aot)
7075 return mono_arm_get_exception_trampolines (aot);
7079 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7086 bp = MONO_CONTEXT_GET_BP (ctx);
7087 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7089 old_value = *lr_loc;
7090 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7093 *lr_loc = new_value;
7098 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7100 * mono_arch_set_breakpoint:
7102 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7103 * The location should contain code emitted by OP_SEQ_POINT.
7106 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7109 guint32 native_offset = ip - (guint8*)ji->code_start;
7110 MonoDebugOptions *opt = mini_get_debug_options ();
7113 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7115 if (!breakpoint_tramp)
7116 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7118 g_assert (native_offset % 4 == 0);
7119 g_assert (info->bp_addrs [native_offset / 4] == 0);
7120 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7121 } else if (opt->soft_breakpoints) {
7123 ARM_BLX_REG (code, ARMREG_LR);
7124 mono_arch_flush_icache (code - 4, 4);
7126 int dreg = ARMREG_LR;
7128 /* Read from another trigger page */
7129 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7131 *(int*)code = (int)bp_trigger_page;
7133 ARM_LDR_IMM (code, dreg, dreg, 0);
7135 mono_arch_flush_icache (code - 16, 16);
7138 /* This is currently implemented by emitting an SWI instruction, which
7139 * qemu/linux seems to convert to a SIGILL.
7141 *(int*)code = (0xef << 24) | 8;
7143 mono_arch_flush_icache (code - 4, 4);
7149 * mono_arch_clear_breakpoint:
7151 * Clear the breakpoint at IP.
7154 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7156 MonoDebugOptions *opt = mini_get_debug_options ();
7161 guint32 native_offset = ip - (guint8*)ji->code_start;
7162 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7164 if (!breakpoint_tramp)
7165 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7167 g_assert (native_offset % 4 == 0);
7168 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7169 info->bp_addrs [native_offset / 4] = 0;
7170 } else if (opt->soft_breakpoints) {
7173 mono_arch_flush_icache (code - 4, 4);
7175 for (i = 0; i < 4; ++i)
7178 mono_arch_flush_icache (ip, code - ip);
7183 * mono_arch_start_single_stepping:
7185 * Start single stepping.
7188 mono_arch_start_single_stepping (void)
7190 if (ss_trigger_page)
7191 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7193 single_step_tramp = mini_get_single_step_trampoline ();
7197 * mono_arch_stop_single_stepping:
7199 * Stop single stepping.
7202 mono_arch_stop_single_stepping (void)
7204 if (ss_trigger_page)
7205 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7207 single_step_tramp = NULL;
7211 #define DBG_SIGNAL SIGBUS
7213 #define DBG_SIGNAL SIGSEGV
7217 * mono_arch_is_single_step_event:
7219 * Return whenever the machine state in SIGCTX corresponds to a single
7223 mono_arch_is_single_step_event (void *info, void *sigctx)
7225 siginfo_t *sinfo = info;
7227 if (!ss_trigger_page)
7230 /* Sometimes the address is off by 4 */
7231 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7238 * mono_arch_is_breakpoint_event:
7240 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7243 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7245 siginfo_t *sinfo = info;
7247 if (!ss_trigger_page)
7250 if (sinfo->si_signo == DBG_SIGNAL) {
7251 /* Sometimes the address is off by 4 */
7252 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7262 * mono_arch_skip_breakpoint:
7264 * See mini-amd64.c for docs.
7267 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7269 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7273 * mono_arch_skip_single_step:
7275 * See mini-amd64.c for docs.
7278 mono_arch_skip_single_step (MonoContext *ctx)
7280 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7283 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7286 * mono_arch_get_seq_point_info:
7288 * See mini-amd64.c for docs.
7291 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7296 // FIXME: Add a free function
7298 mono_domain_lock (domain);
7299 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7301 mono_domain_unlock (domain);
7304 ji = mono_jit_info_table_find (domain, (char*)code);
7307 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7309 info->ss_trigger_page = ss_trigger_page;
7310 info->bp_trigger_page = bp_trigger_page;
7311 info->ss_tramp_addr = &single_step_tramp;
7313 mono_domain_lock (domain);
7314 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7316 mono_domain_unlock (domain);
7323 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7325 ext->lmf.previous_lmf = prev_lmf;
7326 /* Mark that this is a MonoLMFExt */
7327 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7328 ext->lmf.sp = (gssize)ext;
7332 * mono_arch_set_target:
7334 * Set the target architecture the JIT backend should generate code for, in the form
7335 * of a GNU target triplet. Only used in AOT mode.
7338 mono_arch_set_target (char *mtriple)
7340 /* The GNU target triple format is not very well documented */
7341 if (strstr (mtriple, "armv7")) {
7342 v5_supported = TRUE;
7343 v6_supported = TRUE;
7344 v7_supported = TRUE;
7346 if (strstr (mtriple, "armv6")) {
7347 v5_supported = TRUE;
7348 v6_supported = TRUE;
7350 if (strstr (mtriple, "armv7s")) {
7351 v7s_supported = TRUE;
7353 if (strstr (mtriple, "armv7k")) {
7354 v7k_supported = TRUE;
7356 if (strstr (mtriple, "thumbv7s")) {
7357 v5_supported = TRUE;
7358 v6_supported = TRUE;
7359 v7_supported = TRUE;
7360 v7s_supported = TRUE;
7361 thumb_supported = TRUE;
7362 thumb2_supported = TRUE;
7364 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7365 v5_supported = TRUE;
7366 v6_supported = TRUE;
7367 thumb_supported = TRUE;
7370 if (strstr (mtriple, "gnueabi"))
7371 eabi_supported = TRUE;
7375 mono_arch_opcode_supported (int opcode)
7378 case OP_ATOMIC_ADD_I4:
7379 case OP_ATOMIC_EXCHANGE_I4:
7380 case OP_ATOMIC_CAS_I4:
7381 case OP_ATOMIC_LOAD_I1:
7382 case OP_ATOMIC_LOAD_I2:
7383 case OP_ATOMIC_LOAD_I4:
7384 case OP_ATOMIC_LOAD_U1:
7385 case OP_ATOMIC_LOAD_U2:
7386 case OP_ATOMIC_LOAD_U4:
7387 case OP_ATOMIC_STORE_I1:
7388 case OP_ATOMIC_STORE_I2:
7389 case OP_ATOMIC_STORE_I4:
7390 case OP_ATOMIC_STORE_U1:
7391 case OP_ATOMIC_STORE_U2:
7392 case OP_ATOMIC_STORE_U4:
7393 return v7_supported;
7394 case OP_ATOMIC_LOAD_R4:
7395 case OP_ATOMIC_LOAD_R8:
7396 case OP_ATOMIC_STORE_R4:
7397 case OP_ATOMIC_STORE_R8:
7398 return v7_supported && IS_VFP;
7405 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7407 return get_call_info (mp, sig);
7411 mono_arch_get_get_tls_tramp (void)
7417 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data)
7420 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
7421 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7423 *(gpointer*)code = NULL;
7425 /* Load the value from the GOT */
7426 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);
7431 mono_arm_emit_aotconst (gpointer ji_list, guint8 *code, guint8 *buf, int dreg, int patch_type, gconstpointer data)
7433 MonoJumpInfo **ji = (MonoJumpInfo**)ji_list;
7435 *ji = mono_patch_info_list_prepend (*ji, code - buf, patch_type, data);
7436 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7438 *(gpointer*)code = NULL;
7440 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);