3 * ARM backend for the Mono code generator
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
11 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
12 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
17 #include <mono/metadata/abi-details.h>
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/profiler-private.h>
20 #include <mono/metadata/debug-helpers.h>
21 #include <mono/utils/mono-mmap.h>
22 #include <mono/utils/mono-hwcap.h>
23 #include <mono/utils/mono-memory-model.h>
24 #include <mono/utils/mono-threads-coop.h>
30 #include "debugger-agent.h"
32 #include "mono/arch/arm/arm-vfp-codegen.h"
34 /* Sanity check: This makes no sense */
35 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
36 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
40 * IS_SOFT_FLOAT: Is full software floating point used?
41 * IS_HARD_FLOAT: Is full hardware floating point used?
42 * IS_VFP: Is hardware floating point with software ABI used?
44 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
45 * IS_VFP may delegate to mono_arch_is_soft_float ().
48 #if defined(ARM_FPU_VFP_HARD)
49 #define IS_SOFT_FLOAT (FALSE)
50 #define IS_HARD_FLOAT (TRUE)
52 #elif defined(ARM_FPU_NONE)
53 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
54 #define IS_HARD_FLOAT (FALSE)
55 #define IS_VFP (!mono_arch_is_soft_float ())
57 #define IS_SOFT_FLOAT (FALSE)
58 #define IS_HARD_FLOAT (FALSE)
62 #define THUNK_SIZE (3 * 4)
64 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
67 void sys_icache_invalidate (void *start, size_t len);
70 /* This mutex protects architecture specific caches */
71 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
72 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
73 static mono_mutex_t mini_arch_mutex;
75 static gboolean v5_supported = FALSE;
76 static gboolean v6_supported = FALSE;
77 static gboolean v7_supported = FALSE;
78 static gboolean v7s_supported = FALSE;
79 static gboolean v7k_supported = FALSE;
80 static gboolean thumb_supported = FALSE;
81 static gboolean thumb2_supported = FALSE;
83 * Whenever to use the ARM EABI
85 static gboolean eabi_supported = FALSE;
88 * Whenever to use the iphone ABI extensions:
89 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
90 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
91 * This is required for debugging/profiling tools to work, but it has some overhead so it should
92 * only be turned on in debug builds.
94 static gboolean iphone_abi = FALSE;
97 * The FPU we are generating code for. This is NOT runtime configurable right now,
98 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
100 static MonoArmFPU arm_fpu;
102 #if defined(ARM_FPU_VFP_HARD)
104 * On armhf, d0-d7 are used for argument passing and d8-d15
105 * must be preserved across calls, which leaves us no room
106 * for scratch registers. So we use d14-d15 but back up their
107 * previous contents to a stack slot before using them - see
108 * mono_arm_emit_vfp_scratch_save/_restore ().
110 static int vfp_scratch1 = ARM_VFP_D14;
111 static int vfp_scratch2 = ARM_VFP_D15;
114 * On armel, d0-d7 do not need to be preserved, so we can
115 * freely make use of them as scratch registers.
117 static int vfp_scratch1 = ARM_VFP_D0;
118 static int vfp_scratch2 = ARM_VFP_D1;
123 static gpointer single_step_tramp, breakpoint_tramp;
126 * The code generated for sequence points reads from this location, which is
127 * made read-only when single stepping is enabled.
129 static gpointer ss_trigger_page;
131 /* Enabled breakpoints read from this trigger page */
132 static gpointer bp_trigger_page;
136 * floating point support: on ARM it is a mess, there are at least 3
137 * different setups, each of which binary incompat with the other.
138 * 1) FPA: old and ugly, but unfortunately what current distros use
139 * the double binary format has the two words swapped. 8 double registers.
140 * Implemented usually by kernel emulation.
141 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
142 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
143 * 3) VFP: the new and actually sensible and useful FP support. Implemented
144 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
146 * We do not care about FPA. We will support soft float and VFP.
148 int mono_exc_esp_offset = 0;
150 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
151 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
152 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
154 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
155 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
156 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
158 //#define DEBUG_IMT 0
161 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
165 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data);
168 mono_arch_regname (int reg)
170 static const char * rnames[] = {
171 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
172 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
173 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
176 if (reg >= 0 && reg < 16)
182 mono_arch_fregname (int reg)
184 static const char * rnames[] = {
185 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
186 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
187 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
188 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
189 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
190 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
193 if (reg >= 0 && reg < 32)
201 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
203 int imm8, rot_amount;
204 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
205 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
209 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
210 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
212 code = mono_arm_emit_load_imm (code, dreg, imm);
213 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
219 emit_ldr_imm (guint8 *code, int dreg, int sreg, int imm)
221 if (!arm_is_imm12 (imm)) {
222 g_assert (dreg != sreg);
223 code = emit_big_add (code, dreg, sreg, imm);
224 ARM_LDR_IMM (code, dreg, dreg, 0);
226 ARM_LDR_IMM (code, dreg, sreg, imm);
231 /* If dreg == sreg, this clobbers IP */
233 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
235 int imm8, rot_amount;
236 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
237 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
241 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
242 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
244 code = mono_arm_emit_load_imm (code, dreg, imm);
245 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
251 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
253 /* we can use r0-r3, since this is called only for incoming args on the stack */
254 if (size > sizeof (gpointer) * 4) {
256 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
257 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
258 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
259 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
260 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
261 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
262 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
263 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
264 ARM_B_COND (code, ARMCOND_NE, 0);
265 arm_patch (code - 4, start_loop);
268 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
269 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
271 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
272 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
278 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
279 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
280 doffset = soffset = 0;
282 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
283 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
289 g_assert (size == 0);
294 emit_call_reg (guint8 *code, int reg)
297 ARM_BLX_REG (code, reg);
299 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
303 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
309 emit_call_seq (MonoCompile *cfg, guint8 *code)
311 if (cfg->method->dynamic) {
312 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
314 *(gpointer*)code = NULL;
316 code = emit_call_reg (code, ARMREG_IP);
320 cfg->thunk_area += THUNK_SIZE;
325 mono_arm_patchable_b (guint8 *code, int cond)
327 ARM_B_COND (code, cond, 0);
332 mono_arm_patchable_bl (guint8 *code, int cond)
334 ARM_BL_COND (code, cond, 0);
338 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(MONO_CROSS_COMPILE)
339 #define HAVE_AEABI_READ_TP 1
342 #ifdef HAVE_AEABI_READ_TP
343 gpointer __aeabi_read_tp (void);
347 mono_arch_have_fast_tls (void)
349 #ifdef HAVE_AEABI_READ_TP
350 static gboolean have_fast_tls = FALSE;
351 static gboolean inited = FALSE;
353 if (mini_get_debug_options ()->use_fallback_tls)
357 return have_fast_tls;
362 tp1 = __aeabi_read_tp ();
363 asm volatile("mrc p15, 0, %0, c13, c0, 3" : "=r" (tp2));
365 have_fast_tls = tp1 && tp1 == tp2;
368 return have_fast_tls;
375 emit_tls_get (guint8 *code, int dreg, int tls_offset)
377 g_assert (v7_supported);
378 ARM_MRC (code, 15, 0, dreg, 13, 0, 3);
379 ARM_LDR_IMM (code, dreg, dreg, tls_offset);
384 emit_tls_set (guint8 *code, int sreg, int tls_offset)
386 int tp_reg = (sreg != ARMREG_R0) ? ARMREG_R0 : ARMREG_R1;
387 g_assert (v7_supported);
388 ARM_MRC (code, 15, 0, tp_reg, 13, 0, 3);
389 ARM_STR_IMM (code, sreg, tp_reg, tls_offset);
396 * Emit code to push an LMF structure on the LMF stack.
397 * On arm, this is intermixed with the initialization of other fields of the structure.
400 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
404 if (mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR) != -1) {
405 code = emit_tls_get (code, ARMREG_R0, mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR));
407 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
408 (gpointer)"mono_tls_get_lmf_addr");
409 code = emit_call_seq (cfg, code);
411 /* we build the MonoLMF structure on the stack - see mini-arm.h */
412 /* lmf_offset is the offset from the previous stack pointer,
413 * alloc_size is the total stack space allocated, so the offset
414 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
415 * The pointer to the struct is put in r1 (new_lmf).
416 * ip is used as scratch
417 * The callee-saved registers are already in the MonoLMF structure
419 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
420 /* r0 is the result from mono_get_lmf_addr () */
421 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
422 /* new_lmf->previous_lmf = *lmf_addr */
423 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
424 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
425 /* *(lmf_addr) = r1 */
426 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
427 /* Skip method (only needed for trampoline LMF frames) */
428 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
429 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
430 /* save the current IP */
431 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
432 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
434 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
435 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
446 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
450 for (list = inst->float_args; list; list = list->next) {
451 FloatArgData *fad = list->data;
452 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
453 gboolean imm = arm_is_fpimm8 (var->inst_offset);
455 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
461 if (*offset + *max_len > cfg->code_size) {
462 cfg->code_size += *max_len;
463 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
465 code = cfg->native_code + *offset;
469 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
470 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
472 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
474 *offset = code - cfg->native_code;
481 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
485 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
487 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
490 if (!arm_is_fpimm8 (inst->inst_offset)) {
491 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
492 ARM_FSTD (code, reg, ARMREG_LR, 0);
494 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
501 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
505 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
507 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
510 if (!arm_is_fpimm8 (inst->inst_offset)) {
511 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
512 ARM_FLDD (code, reg, ARMREG_LR, 0);
514 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
523 * Emit code to pop an LMF structure from the LMF stack.
526 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
530 if (lmf_offset < 32) {
531 basereg = cfg->frame_reg;
536 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
539 /* ip = previous_lmf */
540 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
542 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
543 /* *(lmf_addr) = previous_lmf */
544 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
549 #endif /* #ifndef DISABLE_JIT */
552 * mono_arch_get_argument_info:
553 * @csig: a method signature
554 * @param_count: the number of parameters to consider
555 * @arg_info: an array to store the result infos
557 * Gathers information on parameters such as size, alignment and
558 * padding. arg_info should be large enought to hold param_count + 1 entries.
560 * Returns the size of the activation frame.
563 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
565 int k, frame_size = 0;
566 guint32 size, align, pad;
570 t = mini_get_underlying_type (csig->ret);
571 if (MONO_TYPE_ISSTRUCT (t)) {
572 frame_size += sizeof (gpointer);
576 arg_info [0].offset = offset;
579 frame_size += sizeof (gpointer);
583 arg_info [0].size = frame_size;
585 for (k = 0; k < param_count; k++) {
586 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
588 /* ignore alignment for now */
591 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
592 arg_info [k].pad = pad;
594 arg_info [k + 1].pad = 0;
595 arg_info [k + 1].size = size;
597 arg_info [k + 1].offset = offset;
601 align = MONO_ARCH_FRAME_ALIGNMENT;
602 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
603 arg_info [k].pad = pad;
608 #define MAX_ARCH_DELEGATE_PARAMS 3
611 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
613 guint8 *code, *start;
614 GSList *unwind_ops = mono_arch_get_cie_program ();
617 start = code = mono_global_codeman_reserve (12);
619 /* Replace the this argument with the target */
620 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
621 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
622 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
624 g_assert ((code - start) <= 12);
626 mono_arch_flush_icache (start, 12);
630 size = 8 + param_count * 4;
631 start = code = mono_global_codeman_reserve (size);
633 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
634 /* slide down the arguments */
635 for (i = 0; i < param_count; ++i) {
636 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
638 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
640 g_assert ((code - start) <= size);
642 mono_arch_flush_icache (start, size);
646 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
648 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
649 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
653 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
659 * mono_arch_get_delegate_invoke_impls:
661 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
665 mono_arch_get_delegate_invoke_impls (void)
671 get_delegate_invoke_impl (&info, TRUE, 0);
672 res = g_slist_prepend (res, info);
674 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
675 get_delegate_invoke_impl (&info, FALSE, i);
676 res = g_slist_prepend (res, info);
683 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
685 guint8 *code, *start;
688 /* FIXME: Support more cases */
689 sig_ret = mini_get_underlying_type (sig->ret);
690 if (MONO_TYPE_ISSTRUCT (sig_ret))
694 static guint8* cached = NULL;
695 mono_mini_arch_lock ();
697 mono_mini_arch_unlock ();
702 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
705 start = get_delegate_invoke_impl (&info, TRUE, 0);
706 mono_tramp_info_register (info, NULL);
709 mono_mini_arch_unlock ();
712 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
715 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
717 for (i = 0; i < sig->param_count; ++i)
718 if (!mono_is_regsize_var (sig->params [i]))
721 mono_mini_arch_lock ();
722 code = cache [sig->param_count];
724 mono_mini_arch_unlock ();
729 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
730 start = mono_aot_get_trampoline (name);
734 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
735 mono_tramp_info_register (info, NULL);
737 cache [sig->param_count] = start;
738 mono_mini_arch_unlock ();
746 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
752 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
754 return (gpointer)regs [ARMREG_R0];
758 * Initialize the cpu to execute managed code.
761 mono_arch_cpu_init (void)
763 i8_align = MONO_ABI_ALIGNOF (gint64);
764 #ifdef MONO_CROSS_COMPILE
765 /* Need to set the alignment of i8 since it can different on the target */
766 #ifdef TARGET_ANDROID
768 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
774 * Initialize architecture specific code.
777 mono_arch_init (void)
781 #ifdef TARGET_WATCHOS
782 mini_get_debug_options ()->soft_breakpoints = TRUE;
785 mono_os_mutex_init_recursive (&mini_arch_mutex);
786 if (mini_get_debug_options ()->soft_breakpoints) {
788 breakpoint_tramp = mini_get_breakpoint_trampoline ();
790 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
791 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
792 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
795 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
796 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
797 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
798 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
799 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
801 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
802 mono_aot_register_jit_icall ("mono_arm_handler_block_trampoline_helper", mono_arm_handler_block_trampoline_helper);
803 #if defined(__ARM_EABI__)
804 eabi_supported = TRUE;
807 #if defined(ARM_FPU_VFP_HARD)
808 arm_fpu = MONO_ARM_FPU_VFP_HARD;
810 arm_fpu = MONO_ARM_FPU_VFP;
812 #if defined(ARM_FPU_NONE) && !defined(TARGET_IOS)
814 * If we're compiling with a soft float fallback and it
815 * turns out that no VFP unit is available, we need to
816 * switch to soft float. We don't do this for iOS, since
817 * iOS devices always have a VFP unit.
819 if (!mono_hwcap_arm_has_vfp)
820 arm_fpu = MONO_ARM_FPU_NONE;
823 * This environment variable can be useful in testing
824 * environments to make sure the soft float fallback
825 * works. Most ARM devices have VFP units these days, so
826 * normally soft float code would not be exercised much.
828 char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
830 if (soft && !strncmp (soft, "1", 1))
831 arm_fpu = MONO_ARM_FPU_NONE;
836 v5_supported = mono_hwcap_arm_is_v5;
837 v6_supported = mono_hwcap_arm_is_v6;
838 v7_supported = mono_hwcap_arm_is_v7;
841 * On weird devices, the hwcap code may fail to detect
842 * the ARM version. In that case, we can at least safely
843 * assume the version the runtime was compiled for.
855 #if defined(TARGET_IOS)
856 /* iOS is special-cased here because we don't yet
857 have a way to properly detect CPU features on it. */
858 thumb_supported = TRUE;
861 thumb_supported = mono_hwcap_arm_has_thumb;
862 thumb2_supported = mono_hwcap_arm_has_thumb2;
865 /* Format: armv(5|6|7[s])[-thumb[2]] */
866 cpu_arch = g_getenv ("MONO_CPU_ARCH");
868 /* Do this here so it overrides any detection. */
870 if (strncmp (cpu_arch, "armv", 4) == 0) {
871 v5_supported = cpu_arch [4] >= '5';
872 v6_supported = cpu_arch [4] >= '6';
873 v7_supported = cpu_arch [4] >= '7';
874 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
875 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
878 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
879 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
885 * Cleanup architecture specific code.
888 mono_arch_cleanup (void)
893 * This function returns the optimizations supported on this cpu.
896 mono_arch_cpu_optimizations (guint32 *exclude_mask)
898 /* no arm-specific optimizations yet */
904 * This function test for all SIMD functions supported.
906 * Returns a bitmask corresponding to all supported versions.
910 mono_arch_cpu_enumerate_simd_versions (void)
912 /* SIMD is currently unimplemented */
917 mono_arm_is_hard_float (void)
919 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
925 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
927 if (v7s_supported || v7k_supported) {
941 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
943 mono_arch_is_soft_float (void)
945 return arm_fpu == MONO_ARM_FPU_NONE;
950 is_regsize_var (MonoType *t)
954 t = mini_get_underlying_type (t);
961 case MONO_TYPE_FNPTR:
963 case MONO_TYPE_OBJECT:
965 case MONO_TYPE_GENERICINST:
966 if (!mono_type_generic_inst_is_valuetype (t))
969 case MONO_TYPE_VALUETYPE:
976 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
981 for (i = 0; i < cfg->num_varinfo; i++) {
982 MonoInst *ins = cfg->varinfo [i];
983 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
986 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
989 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
992 /* we can only allocate 32 bit values */
993 if (is_regsize_var (ins->inst_vtype)) {
994 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
995 g_assert (i == vmv->idx);
996 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1004 mono_arch_get_global_int_regs (MonoCompile *cfg)
1008 mono_arch_compute_omit_fp (cfg);
1011 * FIXME: Interface calls might go through a static rgctx trampoline which
1012 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1015 if (cfg->flags & MONO_CFG_HAS_CALLS)
1016 cfg->uses_rgctx_reg = TRUE;
1018 if (cfg->arch.omit_fp)
1019 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1020 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1021 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1022 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1024 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1025 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1027 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1028 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1029 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1030 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1031 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1032 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1038 * mono_arch_regalloc_cost:
1040 * Return the cost, in number of memory references, of the action of
1041 * allocating the variable VMV into a register during global register
1045 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1051 #endif /* #ifndef DISABLE_JIT */
1054 mono_arch_flush_icache (guint8 *code, gint size)
1056 #if defined(MONO_CROSS_COMPILE)
1058 sys_icache_invalidate (code, size);
1060 __builtin___clear_cache (code, code + size);
1067 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1070 if (*gr > ARMREG_R3) {
1072 ainfo->offset = *stack_size;
1073 ainfo->reg = ARMREG_SP; /* in the caller */
1074 ainfo->storage = RegTypeBase;
1077 ainfo->storage = RegTypeGeneral;
1084 split = i8_align == 4;
1089 if (*gr == ARMREG_R3 && split) {
1090 /* first word in r3 and the second on the stack */
1091 ainfo->offset = *stack_size;
1092 ainfo->reg = ARMREG_SP; /* in the caller */
1093 ainfo->storage = RegTypeBaseGen;
1095 } else if (*gr >= ARMREG_R3) {
1096 if (eabi_supported) {
1097 /* darwin aligns longs to 4 byte only */
1098 if (i8_align == 8) {
1103 ainfo->offset = *stack_size;
1104 ainfo->reg = ARMREG_SP; /* in the caller */
1105 ainfo->storage = RegTypeBase;
1108 if (eabi_supported) {
1109 if (i8_align == 8 && ((*gr) & 1))
1112 ainfo->storage = RegTypeIRegPair;
1121 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1124 * If we're calling a function like this:
1126 * void foo(float a, double b, float c)
1128 * We pass a in s0 and b in d1. That leaves us
1129 * with s1 being unused. The armhf ABI recognizes
1130 * this and requires register assignment to then
1131 * use that for the next single-precision arg,
1132 * i.e. c in this example. So float_spare either
1133 * tells us which reg to use for the next single-
1134 * precision arg, or it's -1, meaning use *fpr.
1136 * Note that even though most of the JIT speaks
1137 * double-precision, fpr represents single-
1138 * precision registers.
1140 * See parts 5.5 and 6.1.2 of the AAPCS for how
1144 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1145 ainfo->storage = RegTypeFP;
1149 * If we're passing a double-precision value
1150 * and *fpr is odd (e.g. it's s1, s3, ...)
1151 * we need to use the next even register. So
1152 * we mark the current *fpr as a spare that
1153 * can be used for the next single-precision
1157 *float_spare = *fpr;
1162 * At this point, we have an even register
1163 * so we assign that and move along.
1167 } else if (*float_spare >= 0) {
1169 * We're passing a single-precision value
1170 * and it looks like a spare single-
1171 * precision register is available. Let's
1175 ainfo->reg = *float_spare;
1179 * If we hit this branch, we're passing a
1180 * single-precision value and we can simply
1181 * use the next available register.
1189 * We've exhausted available floating point
1190 * regs, so pass the rest on the stack.
1198 ainfo->offset = *stack_size;
1199 ainfo->reg = ARMREG_SP;
1200 ainfo->storage = RegTypeBase;
1207 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1211 MonoClassField *field;
1212 MonoType *ftype, *prev_ftype = NULL;
1215 klass = mono_class_from_mono_type (t);
1217 while ((field = mono_class_get_fields (klass, &iter))) {
1218 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1220 ftype = mono_field_get_type (field);
1221 ftype = mini_get_underlying_type (ftype);
1223 if (MONO_TYPE_ISSTRUCT (ftype)) {
1224 int nested_nfields, nested_esize;
1226 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1228 if (nested_esize == 4)
1229 ftype = &mono_defaults.single_class->byval_arg;
1231 ftype = &mono_defaults.double_class->byval_arg;
1232 if (prev_ftype && prev_ftype->type != ftype->type)
1235 nfields += nested_nfields;
1237 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1239 if (prev_ftype && prev_ftype->type != ftype->type)
1245 if (nfields == 0 || nfields > 4)
1247 *out_nfields = nfields;
1248 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1253 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1255 guint i, gr, fpr, pstart;
1257 int n = sig->hasthis + sig->param_count;
1261 guint32 stack_size = 0;
1263 gboolean is_pinvoke = sig->pinvoke;
1264 gboolean vtype_retaddr = FALSE;
1267 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1269 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1276 t = mini_get_underlying_type (sig->ret);
1287 case MONO_TYPE_FNPTR:
1288 case MONO_TYPE_OBJECT:
1289 cinfo->ret.storage = RegTypeGeneral;
1290 cinfo->ret.reg = ARMREG_R0;
1294 cinfo->ret.storage = RegTypeIRegPair;
1295 cinfo->ret.reg = ARMREG_R0;
1299 cinfo->ret.storage = RegTypeFP;
1301 if (t->type == MONO_TYPE_R4)
1302 cinfo->ret.size = 4;
1304 cinfo->ret.size = 8;
1306 if (IS_HARD_FLOAT) {
1307 cinfo->ret.reg = ARM_VFP_F0;
1309 cinfo->ret.reg = ARMREG_R0;
1312 case MONO_TYPE_GENERICINST:
1313 if (!mono_type_generic_inst_is_valuetype (t)) {
1314 cinfo->ret.storage = RegTypeGeneral;
1315 cinfo->ret.reg = ARMREG_R0;
1318 if (mini_is_gsharedvt_variable_type (t)) {
1319 cinfo->ret.storage = RegTypeStructByAddr;
1323 case MONO_TYPE_VALUETYPE:
1324 case MONO_TYPE_TYPEDBYREF:
1325 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1326 cinfo->ret.storage = RegTypeHFA;
1328 cinfo->ret.nregs = nfields;
1329 cinfo->ret.esize = esize;
1332 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1335 #ifdef TARGET_WATCHOS
1340 if (native_size <= max_size) {
1341 cinfo->ret.storage = RegTypeStructByVal;
1342 cinfo->ret.struct_size = native_size;
1343 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1345 cinfo->ret.storage = RegTypeStructByAddr;
1348 cinfo->ret.storage = RegTypeStructByAddr;
1353 case MONO_TYPE_MVAR:
1354 g_assert (mini_is_gsharedvt_type (t));
1355 cinfo->ret.storage = RegTypeStructByAddr;
1357 case MONO_TYPE_VOID:
1360 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1363 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1368 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1369 * the first argument, allowing 'this' to be always passed in the first arg reg.
1370 * Also do this if the first argument is a reference type, since virtual calls
1371 * are sometimes made using calli without sig->hasthis set, like in the delegate
1374 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1376 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1378 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1382 cinfo->ret.reg = gr;
1384 cinfo->vret_arg_index = 1;
1388 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1391 if (vtype_retaddr) {
1392 cinfo->ret.reg = gr;
1397 DEBUG(g_print("params: %d\n", sig->param_count));
1398 for (i = pstart; i < sig->param_count; ++i) {
1399 ArgInfo *ainfo = &cinfo->args [n];
1401 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1402 /* Prevent implicit arguments and sig_cookie from
1403 being passed in registers */
1406 /* Emit the signature cookie just before the implicit arguments */
1407 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1409 DEBUG(g_print("param %d: ", i));
1410 if (sig->params [i]->byref) {
1411 DEBUG(g_print("byref\n"));
1412 add_general (&gr, &stack_size, ainfo, TRUE);
1416 t = mini_get_underlying_type (sig->params [i]);
1420 cinfo->args [n].size = 1;
1421 add_general (&gr, &stack_size, ainfo, TRUE);
1425 cinfo->args [n].size = 2;
1426 add_general (&gr, &stack_size, ainfo, TRUE);
1430 cinfo->args [n].size = 4;
1431 add_general (&gr, &stack_size, ainfo, TRUE);
1436 case MONO_TYPE_FNPTR:
1437 case MONO_TYPE_OBJECT:
1438 cinfo->args [n].size = sizeof (gpointer);
1439 add_general (&gr, &stack_size, ainfo, TRUE);
1441 case MONO_TYPE_GENERICINST:
1442 if (!mono_type_generic_inst_is_valuetype (t)) {
1443 cinfo->args [n].size = sizeof (gpointer);
1444 add_general (&gr, &stack_size, ainfo, TRUE);
1447 if (mini_is_gsharedvt_variable_type (t)) {
1448 /* gsharedvt arguments are passed by ref */
1449 g_assert (mini_is_gsharedvt_type (t));
1450 add_general (&gr, &stack_size, ainfo, TRUE);
1451 switch (ainfo->storage) {
1452 case RegTypeGeneral:
1453 ainfo->storage = RegTypeGSharedVtInReg;
1456 ainfo->storage = RegTypeGSharedVtOnStack;
1459 g_assert_not_reached ();
1464 case MONO_TYPE_TYPEDBYREF:
1465 case MONO_TYPE_VALUETYPE: {
1468 int nwords, nfields, esize;
1471 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1472 if (fpr + nfields < ARM_VFP_F16) {
1473 ainfo->storage = RegTypeHFA;
1475 ainfo->nregs = nfields;
1476 ainfo->esize = esize;
1487 if (t->type == MONO_TYPE_TYPEDBYREF) {
1488 size = sizeof (MonoTypedRef);
1489 align = sizeof (gpointer);
1491 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1493 size = mono_class_native_size (klass, &align);
1495 size = mini_type_stack_size_full (t, &align, FALSE);
1497 DEBUG(g_print ("load %d bytes struct\n", size));
1499 #ifdef TARGET_WATCHOS
1500 /* Watchos pass large structures by ref */
1501 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1502 if (sig->pinvoke && size > 16) {
1503 add_general (&gr, &stack_size, ainfo, TRUE);
1504 switch (ainfo->storage) {
1505 case RegTypeGeneral:
1506 ainfo->storage = RegTypeStructByAddr;
1509 ainfo->storage = RegTypeStructByAddrOnStack;
1512 g_assert_not_reached ();
1521 align_size += (sizeof (gpointer) - 1);
1522 align_size &= ~(sizeof (gpointer) - 1);
1523 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1524 ainfo->storage = RegTypeStructByVal;
1525 ainfo->struct_size = size;
1526 ainfo->align = align;
1527 /* FIXME: align stack_size if needed */
1528 if (eabi_supported) {
1529 if (align >= 8 && (gr & 1))
1532 if (gr > ARMREG_R3) {
1534 ainfo->vtsize = nwords;
1536 int rest = ARMREG_R3 - gr + 1;
1537 int n_in_regs = rest >= nwords? nwords: rest;
1539 ainfo->size = n_in_regs;
1540 ainfo->vtsize = nwords - n_in_regs;
1543 nwords -= n_in_regs;
1545 if (sig->call_convention == MONO_CALL_VARARG)
1546 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1547 stack_size = ALIGN_TO (stack_size, align);
1548 ainfo->offset = stack_size;
1549 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1550 stack_size += nwords * sizeof (gpointer);
1556 add_general (&gr, &stack_size, ainfo, FALSE);
1562 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1564 add_general (&gr, &stack_size, ainfo, TRUE);
1570 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1572 add_general (&gr, &stack_size, ainfo, FALSE);
1575 case MONO_TYPE_MVAR:
1576 /* gsharedvt arguments are passed by ref */
1577 g_assert (mini_is_gsharedvt_type (t));
1578 add_general (&gr, &stack_size, ainfo, TRUE);
1579 switch (ainfo->storage) {
1580 case RegTypeGeneral:
1581 ainfo->storage = RegTypeGSharedVtInReg;
1584 ainfo->storage = RegTypeGSharedVtOnStack;
1587 g_assert_not_reached ();
1591 g_error ("Can't handle 0x%x", sig->params [i]->type);
1596 /* Handle the case where there are no implicit arguments */
1597 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1598 /* Prevent implicit arguments and sig_cookie from
1599 being passed in registers */
1602 /* Emit the signature cookie just before the implicit arguments */
1603 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1606 /* align stack size to 8 */
1607 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1608 stack_size = (stack_size + 7) & ~7;
1610 cinfo->stack_usage = stack_size;
1616 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1618 MonoType *callee_ret;
1622 c1 = get_call_info (NULL, caller_sig);
1623 c2 = get_call_info (NULL, callee_sig);
1626 * Tail calls with more callee stack usage than the caller cannot be supported, since
1627 * the extra stack space would be left on the stack after the tail call.
1629 res = c1->stack_usage >= c2->stack_usage;
1630 callee_ret = mini_get_underlying_type (callee_sig->ret);
1631 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1632 /* An address on the callee's stack is passed as the first argument */
1635 if (c2->stack_usage > 16 * 4)
1647 debug_omit_fp (void)
1650 return mono_debug_count ();
1657 * mono_arch_compute_omit_fp:
1658 * Determine whether the frame pointer can be eliminated.
1661 mono_arch_compute_omit_fp (MonoCompile *cfg)
1663 MonoMethodSignature *sig;
1664 MonoMethodHeader *header;
1668 if (cfg->arch.omit_fp_computed)
1671 header = cfg->header;
1673 sig = mono_method_signature (cfg->method);
1675 if (!cfg->arch.cinfo)
1676 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1677 cinfo = cfg->arch.cinfo;
1680 * FIXME: Remove some of the restrictions.
1682 cfg->arch.omit_fp = TRUE;
1683 cfg->arch.omit_fp_computed = TRUE;
1685 if (cfg->disable_omit_fp)
1686 cfg->arch.omit_fp = FALSE;
1687 if (!debug_omit_fp ())
1688 cfg->arch.omit_fp = FALSE;
1690 if (cfg->method->save_lmf)
1691 cfg->arch.omit_fp = FALSE;
1693 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1694 cfg->arch.omit_fp = FALSE;
1695 if (header->num_clauses)
1696 cfg->arch.omit_fp = FALSE;
1697 if (cfg->param_area)
1698 cfg->arch.omit_fp = FALSE;
1699 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1700 cfg->arch.omit_fp = FALSE;
1701 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)))
1702 cfg->arch.omit_fp = FALSE;
1703 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1704 ArgInfo *ainfo = &cinfo->args [i];
1706 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1708 * The stack offset can only be determined when the frame
1711 cfg->arch.omit_fp = FALSE;
1716 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1717 MonoInst *ins = cfg->varinfo [i];
1720 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1725 * Set var information according to the calling convention. arm version.
1726 * The locals var stuff should most likely be split in another method.
1729 mono_arch_allocate_vars (MonoCompile *cfg)
1731 MonoMethodSignature *sig;
1732 MonoMethodHeader *header;
1735 int i, offset, size, align, curinst;
1740 sig = mono_method_signature (cfg->method);
1742 if (!cfg->arch.cinfo)
1743 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1744 cinfo = cfg->arch.cinfo;
1745 sig_ret = mini_get_underlying_type (sig->ret);
1747 mono_arch_compute_omit_fp (cfg);
1749 if (cfg->arch.omit_fp)
1750 cfg->frame_reg = ARMREG_SP;
1752 cfg->frame_reg = ARMREG_FP;
1754 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1756 /* allow room for the vararg method args: void* and long/double */
1757 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1758 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1760 header = cfg->header;
1762 /* See mono_arch_get_global_int_regs () */
1763 if (cfg->flags & MONO_CFG_HAS_CALLS)
1764 cfg->uses_rgctx_reg = TRUE;
1766 if (cfg->frame_reg != ARMREG_SP)
1767 cfg->used_int_regs |= 1 << cfg->frame_reg;
1769 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1770 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1771 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1775 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1776 if (sig_ret->type != MONO_TYPE_VOID) {
1777 cfg->ret->opcode = OP_REGVAR;
1778 cfg->ret->inst_c0 = ARMREG_R0;
1781 /* local vars are at a positive offset from the stack pointer */
1783 * also note that if the function uses alloca, we use FP
1784 * to point at the local variables.
1786 offset = 0; /* linkage area */
1787 /* align the offset to 16 bytes: not sure this is needed here */
1789 //offset &= ~(8 - 1);
1791 /* add parameter area size for called functions */
1792 offset += cfg->param_area;
1795 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1798 /* allow room to save the return value */
1799 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1802 switch (cinfo->ret.storage) {
1803 case RegTypeStructByVal:
1805 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1806 offset = ALIGN_TO (offset, 8);
1807 cfg->ret->opcode = OP_REGOFFSET;
1808 cfg->ret->inst_basereg = cfg->frame_reg;
1809 cfg->ret->inst_offset = offset;
1810 if (cinfo->ret.storage == RegTypeStructByVal)
1811 offset += cinfo->ret.nregs * sizeof (gpointer);
1815 case RegTypeStructByAddr:
1816 ins = cfg->vret_addr;
1817 offset += sizeof(gpointer) - 1;
1818 offset &= ~(sizeof(gpointer) - 1);
1819 ins->inst_offset = offset;
1820 ins->opcode = OP_REGOFFSET;
1821 ins->inst_basereg = cfg->frame_reg;
1822 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1823 g_print ("vret_addr =");
1824 mono_print_ins (cfg->vret_addr);
1826 offset += sizeof(gpointer);
1832 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1833 if (cfg->arch.seq_point_info_var) {
1836 ins = cfg->arch.seq_point_info_var;
1840 offset += align - 1;
1841 offset &= ~(align - 1);
1842 ins->opcode = OP_REGOFFSET;
1843 ins->inst_basereg = cfg->frame_reg;
1844 ins->inst_offset = offset;
1847 if (cfg->arch.ss_trigger_page_var) {
1850 ins = cfg->arch.ss_trigger_page_var;
1853 offset += align - 1;
1854 offset &= ~(align - 1);
1855 ins->opcode = OP_REGOFFSET;
1856 ins->inst_basereg = cfg->frame_reg;
1857 ins->inst_offset = offset;
1861 if (cfg->arch.seq_point_ss_method_var) {
1864 ins = cfg->arch.seq_point_ss_method_var;
1867 offset += align - 1;
1868 offset &= ~(align - 1);
1869 ins->opcode = OP_REGOFFSET;
1870 ins->inst_basereg = cfg->frame_reg;
1871 ins->inst_offset = offset;
1874 if (cfg->arch.seq_point_bp_method_var) {
1877 ins = cfg->arch.seq_point_bp_method_var;
1880 offset += align - 1;
1881 offset &= ~(align - 1);
1882 ins->opcode = OP_REGOFFSET;
1883 ins->inst_basereg = cfg->frame_reg;
1884 ins->inst_offset = offset;
1888 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1889 /* Allocate a temporary used by the atomic ops */
1893 /* Allocate a local slot to hold the sig cookie address */
1894 offset += align - 1;
1895 offset &= ~(align - 1);
1896 cfg->arch.atomic_tmp_offset = offset;
1899 cfg->arch.atomic_tmp_offset = -1;
1902 cfg->locals_min_stack_offset = offset;
1904 curinst = cfg->locals_start;
1905 for (i = curinst; i < cfg->num_varinfo; ++i) {
1908 ins = cfg->varinfo [i];
1909 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1912 t = ins->inst_vtype;
1913 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1916 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1917 * pinvoke wrappers when they call functions returning structure */
1918 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1919 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1923 size = mono_type_size (t, &align);
1925 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1926 * since it loads/stores misaligned words, which don't do the right thing.
1928 if (align < 4 && size >= 4)
1930 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1931 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1932 offset += align - 1;
1933 offset &= ~(align - 1);
1934 ins->opcode = OP_REGOFFSET;
1935 ins->inst_offset = offset;
1936 ins->inst_basereg = cfg->frame_reg;
1938 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1941 cfg->locals_max_stack_offset = offset;
1945 ins = cfg->args [curinst];
1946 if (ins->opcode != OP_REGVAR) {
1947 ins->opcode = OP_REGOFFSET;
1948 ins->inst_basereg = cfg->frame_reg;
1949 offset += sizeof (gpointer) - 1;
1950 offset &= ~(sizeof (gpointer) - 1);
1951 ins->inst_offset = offset;
1952 offset += sizeof (gpointer);
1957 if (sig->call_convention == MONO_CALL_VARARG) {
1961 /* Allocate a local slot to hold the sig cookie address */
1962 offset += align - 1;
1963 offset &= ~(align - 1);
1964 cfg->sig_cookie = offset;
1968 for (i = 0; i < sig->param_count; ++i) {
1969 ainfo = cinfo->args + i;
1971 ins = cfg->args [curinst];
1973 switch (ainfo->storage) {
1975 offset = ALIGN_TO (offset, 8);
1976 ins->opcode = OP_REGOFFSET;
1977 ins->inst_basereg = cfg->frame_reg;
1978 /* These arguments are saved to the stack in the prolog */
1979 ins->inst_offset = offset;
1980 if (cfg->verbose_level >= 2)
1981 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
1989 if (ins->opcode != OP_REGVAR) {
1990 ins->opcode = OP_REGOFFSET;
1991 ins->inst_basereg = cfg->frame_reg;
1992 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
1994 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1995 * since it loads/stores misaligned words, which don't do the right thing.
1997 if (align < 4 && size >= 4)
1999 /* The code in the prolog () stores words when storing vtypes received in a register */
2000 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2002 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2003 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2004 offset += align - 1;
2005 offset &= ~(align - 1);
2006 ins->inst_offset = offset;
2012 /* align the offset to 8 bytes */
2013 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2014 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2019 cfg->stack_offset = offset;
2023 mono_arch_create_vars (MonoCompile *cfg)
2025 MonoMethodSignature *sig;
2029 sig = mono_method_signature (cfg->method);
2031 if (!cfg->arch.cinfo)
2032 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2033 cinfo = cfg->arch.cinfo;
2035 if (IS_HARD_FLOAT) {
2036 for (i = 0; i < 2; i++) {
2037 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2038 inst->flags |= MONO_INST_VOLATILE;
2040 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2044 if (cinfo->ret.storage == RegTypeStructByVal)
2045 cfg->ret_var_is_local = TRUE;
2047 if (cinfo->ret.storage == RegTypeStructByAddr) {
2048 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2049 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2050 g_print ("vret_addr = ");
2051 mono_print_ins (cfg->vret_addr);
2055 if (cfg->gen_sdb_seq_points) {
2056 if (cfg->compile_aot) {
2057 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2058 ins->flags |= MONO_INST_VOLATILE;
2059 cfg->arch.seq_point_info_var = ins;
2061 if (!cfg->soft_breakpoints) {
2062 /* Allocate a separate variable for this to save 1 load per seq point */
2063 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2064 ins->flags |= MONO_INST_VOLATILE;
2065 cfg->arch.ss_trigger_page_var = ins;
2068 if (cfg->soft_breakpoints) {
2071 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2072 ins->flags |= MONO_INST_VOLATILE;
2073 cfg->arch.seq_point_ss_method_var = ins;
2075 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2076 ins->flags |= MONO_INST_VOLATILE;
2077 cfg->arch.seq_point_bp_method_var = ins;
2083 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2085 MonoMethodSignature *tmp_sig;
2088 if (call->tail_call)
2091 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2094 * mono_ArgIterator_Setup assumes the signature cookie is
2095 * passed first and all the arguments which were before it are
2096 * passed on the stack after the signature. So compensate by
2097 * passing a different signature.
2099 tmp_sig = mono_metadata_signature_dup (call->signature);
2100 tmp_sig->param_count -= call->signature->sentinelpos;
2101 tmp_sig->sentinelpos = 0;
2102 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2104 sig_reg = mono_alloc_ireg (cfg);
2105 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2107 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2112 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2117 LLVMCallInfo *linfo;
2119 n = sig->param_count + sig->hasthis;
2121 cinfo = get_call_info (cfg->mempool, sig);
2123 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2126 * LLVM always uses the native ABI while we use our own ABI, the
2127 * only difference is the handling of vtypes:
2128 * - we only pass/receive them in registers in some cases, and only
2129 * in 1 or 2 integer registers.
2131 switch (cinfo->ret.storage) {
2132 case RegTypeGeneral:
2135 case RegTypeIRegPair:
2137 case RegTypeStructByAddr:
2138 /* Vtype returned using a hidden argument */
2139 linfo->ret.storage = LLVMArgVtypeRetAddr;
2140 linfo->vret_arg_index = cinfo->vret_arg_index;
2143 case RegTypeStructByVal:
2144 /* LLVM models this by returning an int array */
2145 linfo->ret.storage = LLVMArgAsIArgs;
2146 linfo->ret.nslots = cinfo->ret.nregs;
2150 linfo->ret.storage = LLVMArgFpStruct;
2151 linfo->ret.nslots = cinfo->ret.nregs;
2152 linfo->ret.esize = cinfo->ret.esize;
2155 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2156 cfg->disable_llvm = TRUE;
2160 for (i = 0; i < n; ++i) {
2161 LLVMArgInfo *lainfo = &linfo->args [i];
2162 ainfo = cinfo->args + i;
2164 lainfo->storage = LLVMArgNone;
2166 switch (ainfo->storage) {
2167 case RegTypeGeneral:
2168 case RegTypeIRegPair:
2170 case RegTypeBaseGen:
2172 lainfo->storage = LLVMArgNormal;
2174 case RegTypeStructByVal:
2175 lainfo->storage = LLVMArgAsIArgs;
2176 if (eabi_supported && ainfo->align == 8) {
2177 /* LLVM models this by passing an int64 array */
2178 lainfo->nslots = ALIGN_TO (ainfo->struct_size, 8) / 8;
2181 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2185 case RegTypeStructByAddr:
2186 case RegTypeStructByAddrOnStack:
2187 lainfo->storage = LLVMArgVtypeByRef;
2192 lainfo->storage = LLVMArgAsFpArgs;
2193 lainfo->nslots = ainfo->nregs;
2194 lainfo->esize = ainfo->esize;
2195 for (j = 0; j < ainfo->nregs; ++j)
2196 lainfo->pair_storage [j] = LLVMArgInFPReg;
2200 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2201 cfg->disable_llvm = TRUE;
2211 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2214 MonoMethodSignature *sig;
2218 sig = call->signature;
2219 n = sig->param_count + sig->hasthis;
2221 cinfo = get_call_info (cfg->mempool, sig);
2223 switch (cinfo->ret.storage) {
2224 case RegTypeStructByVal:
2226 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2227 /* The JIT will transform this into a normal call */
2228 call->vret_in_reg = TRUE;
2231 if (call->inst.opcode == OP_TAILCALL)
2234 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2235 * the location pointed to by it after call in emit_move_return_value ().
2237 if (!cfg->arch.vret_addr_loc) {
2238 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2239 /* Prevent it from being register allocated or optimized away */
2240 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2243 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2245 case RegTypeStructByAddr: {
2247 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2248 vtarg->sreg1 = call->vret_var->dreg;
2249 vtarg->dreg = mono_alloc_preg (cfg);
2250 MONO_ADD_INS (cfg->cbb, vtarg);
2252 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2259 for (i = 0; i < n; ++i) {
2260 ArgInfo *ainfo = cinfo->args + i;
2263 if (i >= sig->hasthis)
2264 t = sig->params [i - sig->hasthis];
2266 t = &mono_defaults.int_class->byval_arg;
2267 t = mini_get_underlying_type (t);
2269 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2270 /* Emit the signature cookie just before the implicit arguments */
2271 emit_sig_cookie (cfg, call, cinfo);
2274 in = call->args [i];
2276 switch (ainfo->storage) {
2277 case RegTypeGeneral:
2278 case RegTypeIRegPair:
2279 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2280 MONO_INST_NEW (cfg, ins, OP_MOVE);
2281 ins->dreg = mono_alloc_ireg (cfg);
2282 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2283 MONO_ADD_INS (cfg->cbb, ins);
2284 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2286 MONO_INST_NEW (cfg, ins, OP_MOVE);
2287 ins->dreg = mono_alloc_ireg (cfg);
2288 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2289 MONO_ADD_INS (cfg->cbb, ins);
2290 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2291 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2292 if (ainfo->size == 4) {
2293 if (IS_SOFT_FLOAT) {
2294 /* mono_emit_call_args () have already done the r8->r4 conversion */
2295 /* The converted value is in an int vreg */
2296 MONO_INST_NEW (cfg, ins, OP_MOVE);
2297 ins->dreg = mono_alloc_ireg (cfg);
2298 ins->sreg1 = in->dreg;
2299 MONO_ADD_INS (cfg->cbb, ins);
2300 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2304 cfg->param_area = MAX (cfg->param_area, 8);
2305 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2306 creg = mono_alloc_ireg (cfg);
2307 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2308 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2311 if (IS_SOFT_FLOAT) {
2312 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2313 ins->dreg = mono_alloc_ireg (cfg);
2314 ins->sreg1 = in->dreg;
2315 MONO_ADD_INS (cfg->cbb, ins);
2316 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2318 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2319 ins->dreg = mono_alloc_ireg (cfg);
2320 ins->sreg1 = in->dreg;
2321 MONO_ADD_INS (cfg->cbb, ins);
2322 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2326 cfg->param_area = MAX (cfg->param_area, 8);
2327 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2328 creg = mono_alloc_ireg (cfg);
2329 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2330 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2331 creg = mono_alloc_ireg (cfg);
2332 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2333 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2336 cfg->flags |= MONO_CFG_HAS_FPOUT;
2338 MONO_INST_NEW (cfg, ins, OP_MOVE);
2339 ins->dreg = mono_alloc_ireg (cfg);
2340 ins->sreg1 = in->dreg;
2341 MONO_ADD_INS (cfg->cbb, ins);
2343 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2346 case RegTypeStructByVal:
2347 case RegTypeGSharedVtInReg:
2348 case RegTypeGSharedVtOnStack:
2350 case RegTypeStructByAddr:
2351 case RegTypeStructByAddrOnStack:
2352 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2353 ins->opcode = OP_OUTARG_VT;
2354 ins->sreg1 = in->dreg;
2355 ins->klass = in->klass;
2356 ins->inst_p0 = call;
2357 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2358 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2359 mono_call_inst_add_outarg_vt (cfg, call, ins);
2360 MONO_ADD_INS (cfg->cbb, ins);
2363 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2364 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2365 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2366 if (t->type == MONO_TYPE_R8) {
2367 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2370 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2372 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2375 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2378 case RegTypeBaseGen:
2379 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2380 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2381 MONO_INST_NEW (cfg, ins, OP_MOVE);
2382 ins->dreg = mono_alloc_ireg (cfg);
2383 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2384 MONO_ADD_INS (cfg->cbb, ins);
2385 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2386 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2389 /* This should work for soft-float as well */
2391 cfg->param_area = MAX (cfg->param_area, 8);
2392 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2393 creg = mono_alloc_ireg (cfg);
2394 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2395 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2396 creg = mono_alloc_ireg (cfg);
2397 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2398 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2399 cfg->flags |= MONO_CFG_HAS_FPOUT;
2401 g_assert_not_reached ();
2405 int fdreg = mono_alloc_freg (cfg);
2407 if (ainfo->size == 8) {
2408 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2409 ins->sreg1 = in->dreg;
2411 MONO_ADD_INS (cfg->cbb, ins);
2413 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2418 * Mono's register allocator doesn't speak single-precision registers that
2419 * overlap double-precision registers (i.e. armhf). So we have to work around
2420 * the register allocator and load the value from memory manually.
2422 * So we create a variable for the float argument and an instruction to store
2423 * the argument into the variable. We then store the list of these arguments
2424 * in call->float_args. This list is then used by emit_float_args later to
2425 * pass the arguments in the various call opcodes.
2427 * This is not very nice, and we should really try to fix the allocator.
2430 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2432 /* Make sure the instruction isn't seen as pointless and removed.
2434 float_arg->flags |= MONO_INST_VOLATILE;
2436 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2438 /* We use the dreg to look up the instruction later. The hreg is used to
2439 * emit the instruction that loads the value into the FP reg.
2441 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2442 fad->vreg = float_arg->dreg;
2443 fad->hreg = ainfo->reg;
2445 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2448 call->used_iregs |= 1 << ainfo->reg;
2449 cfg->flags |= MONO_CFG_HAS_FPOUT;
2453 g_assert_not_reached ();
2457 /* Handle the case where there are no implicit arguments */
2458 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2459 emit_sig_cookie (cfg, call, cinfo);
2461 call->call_info = cinfo;
2462 call->stack_usage = cinfo->stack_usage;
2466 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2472 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2473 ins->dreg = mono_alloc_freg (cfg);
2474 ins->sreg1 = arg->dreg;
2475 MONO_ADD_INS (cfg->cbb, ins);
2476 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2479 g_assert_not_reached ();
2485 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2487 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2489 ArgInfo *ainfo = ins->inst_p1;
2490 int ovf_size = ainfo->vtsize;
2491 int doffset = ainfo->offset;
2492 int struct_size = ainfo->struct_size;
2493 int i, soffset, dreg, tmpreg;
2495 switch (ainfo->storage) {
2496 case RegTypeGSharedVtInReg:
2497 case RegTypeStructByAddr:
2499 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2501 case RegTypeGSharedVtOnStack:
2502 case RegTypeStructByAddrOnStack:
2503 /* Pass by addr on stack */
2504 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2507 for (i = 0; i < ainfo->nregs; ++i) {
2508 if (ainfo->esize == 4)
2509 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2511 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2512 load->dreg = mono_alloc_freg (cfg);
2513 load->inst_basereg = src->dreg;
2514 load->inst_offset = i * ainfo->esize;
2515 MONO_ADD_INS (cfg->cbb, load);
2517 if (ainfo->esize == 4) {
2520 /* See RegTypeFP in mono_arch_emit_call () */
2521 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2522 float_arg->flags |= MONO_INST_VOLATILE;
2523 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2525 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2526 fad->vreg = float_arg->dreg;
2527 fad->hreg = ainfo->reg + i;
2529 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2531 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2537 for (i = 0; i < ainfo->size; ++i) {
2538 dreg = mono_alloc_ireg (cfg);
2539 switch (struct_size) {
2541 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2544 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2547 tmpreg = mono_alloc_ireg (cfg);
2548 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2549 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2550 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2551 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2552 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2553 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2554 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2557 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2560 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2561 soffset += sizeof (gpointer);
2562 struct_size -= sizeof (gpointer);
2564 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2566 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2572 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2574 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2577 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2580 if (COMPILE_LLVM (cfg)) {
2581 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2583 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2584 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2585 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2586 MONO_ADD_INS (cfg->cbb, ins);
2591 case MONO_ARM_FPU_NONE:
2592 if (ret->type == MONO_TYPE_R8) {
2595 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2596 ins->dreg = cfg->ret->dreg;
2597 ins->sreg1 = val->dreg;
2598 MONO_ADD_INS (cfg->cbb, ins);
2601 if (ret->type == MONO_TYPE_R4) {
2602 /* Already converted to an int in method_to_ir () */
2603 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2607 case MONO_ARM_FPU_VFP:
2608 case MONO_ARM_FPU_VFP_HARD:
2609 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2612 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2613 ins->dreg = cfg->ret->dreg;
2614 ins->sreg1 = val->dreg;
2615 MONO_ADD_INS (cfg->cbb, ins);
2620 g_assert_not_reached ();
2624 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2627 #endif /* #ifndef DISABLE_JIT */
2630 mono_arch_is_inst_imm (gint64 imm)
2636 MonoMethodSignature *sig;
2639 MonoType **param_types;
2643 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2647 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2650 switch (cinfo->ret.storage) {
2652 case RegTypeGeneral:
2653 case RegTypeIRegPair:
2654 case RegTypeStructByAddr:
2665 for (i = 0; i < cinfo->nargs; ++i) {
2666 ArgInfo *ainfo = &cinfo->args [i];
2669 switch (ainfo->storage) {
2670 case RegTypeGeneral:
2671 case RegTypeIRegPair:
2672 case RegTypeBaseGen:
2676 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2679 case RegTypeStructByVal:
2680 if (ainfo->size == 0)
2681 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2683 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2684 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2692 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2693 for (i = 0; i < sig->param_count; ++i) {
2694 MonoType *t = sig->params [i];
2699 t = mini_get_underlying_type (t);
2722 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2724 ArchDynCallInfo *info;
2728 cinfo = get_call_info (NULL, sig);
2730 if (!dyn_call_supported (cinfo, sig)) {
2735 info = g_new0 (ArchDynCallInfo, 1);
2736 // FIXME: Preprocess the info to speed up start_dyn_call ()
2738 info->cinfo = cinfo;
2739 info->rtype = mini_get_underlying_type (sig->ret);
2740 info->param_types = g_new0 (MonoType*, sig->param_count);
2741 for (i = 0; i < sig->param_count; ++i)
2742 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2744 return (MonoDynCallInfo*)info;
2748 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2750 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2752 g_free (ainfo->cinfo);
2757 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2759 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2760 DynCallArgs *p = (DynCallArgs*)buf;
2761 int arg_index, greg, i, j, pindex;
2762 MonoMethodSignature *sig = dinfo->sig;
2764 g_assert (buf_len >= sizeof (DynCallArgs));
2774 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2775 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2780 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2781 p->regs [greg ++] = (mgreg_t)ret;
2783 for (i = pindex; i < sig->param_count; i++) {
2784 MonoType *t = dinfo->param_types [i];
2785 gpointer *arg = args [arg_index ++];
2786 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2789 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2791 } else if (ainfo->storage == RegTypeFP) {
2792 } else if (ainfo->storage == RegTypeBase) {
2793 slot = PARAM_REGS + (ainfo->offset / 4);
2794 } else if (ainfo->storage == RegTypeBaseGen) {
2795 /* slot + 1 is the first stack slot, so the code below will work */
2798 g_assert_not_reached ();
2802 p->regs [slot] = (mgreg_t)*arg;
2807 case MONO_TYPE_OBJECT:
2811 p->regs [slot] = (mgreg_t)*arg;
2814 p->regs [slot] = *(guint8*)arg;
2817 p->regs [slot] = *(gint8*)arg;
2820 p->regs [slot] = *(gint16*)arg;
2823 p->regs [slot] = *(guint16*)arg;
2826 p->regs [slot] = *(gint32*)arg;
2829 p->regs [slot] = *(guint32*)arg;
2833 p->regs [slot ++] = (mgreg_t)arg [0];
2834 p->regs [slot] = (mgreg_t)arg [1];
2837 if (ainfo->storage == RegTypeFP) {
2838 float f = *(float*)arg;
2839 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2842 p->regs [slot] = *(mgreg_t*)arg;
2846 if (ainfo->storage == RegTypeFP) {
2847 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2850 p->regs [slot ++] = (mgreg_t)arg [0];
2851 p->regs [slot] = (mgreg_t)arg [1];
2854 case MONO_TYPE_GENERICINST:
2855 if (MONO_TYPE_IS_REFERENCE (t)) {
2856 p->regs [slot] = (mgreg_t)*arg;
2859 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2860 MonoClass *klass = mono_class_from_mono_type (t);
2861 guint8 *nullable_buf;
2864 size = mono_class_value_size (klass, NULL);
2865 nullable_buf = g_alloca (size);
2866 g_assert (nullable_buf);
2868 /* The argument pointed to by arg is either a boxed vtype or null */
2869 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2871 arg = (gpointer*)nullable_buf;
2877 case MONO_TYPE_VALUETYPE:
2878 g_assert (ainfo->storage == RegTypeStructByVal);
2880 if (ainfo->size == 0)
2881 slot = PARAM_REGS + (ainfo->offset / 4);
2885 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2886 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2889 g_assert_not_reached ();
2895 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2897 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2898 DynCallArgs *p = (DynCallArgs*)buf;
2899 MonoType *ptype = ainfo->rtype;
2900 guint8 *ret = p->ret;
2901 mgreg_t res = p->res;
2902 mgreg_t res2 = p->res2;
2904 switch (ptype->type) {
2905 case MONO_TYPE_VOID:
2906 *(gpointer*)ret = NULL;
2908 case MONO_TYPE_OBJECT:
2912 *(gpointer*)ret = (gpointer)res;
2918 *(guint8*)ret = res;
2921 *(gint16*)ret = res;
2924 *(guint16*)ret = res;
2927 *(gint32*)ret = res;
2930 *(guint32*)ret = res;
2934 /* This handles endianness as well */
2935 ((gint32*)ret) [0] = res;
2936 ((gint32*)ret) [1] = res2;
2938 case MONO_TYPE_GENERICINST:
2939 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2940 *(gpointer*)ret = (gpointer)res;
2945 case MONO_TYPE_VALUETYPE:
2946 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2952 *(float*)ret = *(float*)&p->fpregs [0];
2954 *(float*)ret = *(float*)&res;
2956 case MONO_TYPE_R8: {
2960 if (IS_HARD_FLOAT) {
2961 *(double*)ret = p->fpregs [0];
2966 *(double*)ret = *(double*)®s;
2971 g_assert_not_reached ();
2978 * Allow tracing to work with this interface (with an optional argument)
2982 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2986 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2987 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2988 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2989 code = emit_call_reg (code, ARMREG_R2);
3003 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3006 int save_mode = SAVE_NONE;
3008 MonoMethod *method = cfg->method;
3009 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3010 int rtype = ret_type->type;
3011 int save_offset = cfg->param_area;
3015 offset = code - cfg->native_code;
3016 /* we need about 16 instructions */
3017 if (offset > (cfg->code_size - 16 * 4)) {
3018 cfg->code_size *= 2;
3019 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3020 code = cfg->native_code + offset;
3023 case MONO_TYPE_VOID:
3024 /* special case string .ctor icall */
3025 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3026 save_mode = SAVE_ONE;
3028 save_mode = SAVE_NONE;
3032 save_mode = SAVE_TWO;
3036 save_mode = SAVE_ONE_FP;
3038 save_mode = SAVE_ONE;
3042 save_mode = SAVE_TWO_FP;
3044 save_mode = SAVE_TWO;
3046 case MONO_TYPE_GENERICINST:
3047 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3048 save_mode = SAVE_ONE;
3052 case MONO_TYPE_VALUETYPE:
3053 save_mode = SAVE_STRUCT;
3056 save_mode = SAVE_ONE;
3060 switch (save_mode) {
3062 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3063 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3064 if (enable_arguments) {
3065 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3066 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3070 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3071 if (enable_arguments) {
3072 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3076 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3077 if (enable_arguments) {
3078 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3082 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3083 if (enable_arguments) {
3084 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3088 if (enable_arguments) {
3089 /* FIXME: get the actual address */
3090 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3098 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3099 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3100 code = emit_call_reg (code, ARMREG_IP);
3102 switch (save_mode) {
3104 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3105 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3108 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3111 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3114 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3125 * The immediate field for cond branches is big enough for all reasonable methods
3127 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3128 if (0 && ins->inst_true_bb->native_offset) { \
3129 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3131 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3132 ARM_B_COND (code, (condcode), 0); \
3135 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3137 /* emit an exception if condition is fail
3139 * We assign the extra code used to throw the implicit exceptions
3140 * to cfg->bb_exit as far as the big branch handling is concerned
3142 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3144 mono_add_patch_info (cfg, code - cfg->native_code, \
3145 MONO_PATCH_INFO_EXC, exc_name); \
3146 ARM_BL_COND (code, (condcode), 0); \
3149 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3152 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3157 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3161 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3162 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3164 switch (ins->opcode) {
3167 /* Already done by an arch-independent pass */
3169 case OP_LOAD_MEMBASE:
3170 case OP_LOADI4_MEMBASE:
3172 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3173 * OP_LOAD_MEMBASE offset(basereg), reg
3175 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3176 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3177 ins->inst_basereg == last_ins->inst_destbasereg &&
3178 ins->inst_offset == last_ins->inst_offset) {
3179 if (ins->dreg == last_ins->sreg1) {
3180 MONO_DELETE_INS (bb, ins);
3183 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3184 ins->opcode = OP_MOVE;
3185 ins->sreg1 = last_ins->sreg1;
3189 * Note: reg1 must be different from the basereg in the second load
3190 * OP_LOAD_MEMBASE offset(basereg), reg1
3191 * OP_LOAD_MEMBASE offset(basereg), reg2
3193 * OP_LOAD_MEMBASE offset(basereg), reg1
3194 * OP_MOVE reg1, reg2
3196 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3197 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3198 ins->inst_basereg != last_ins->dreg &&
3199 ins->inst_basereg == last_ins->inst_basereg &&
3200 ins->inst_offset == last_ins->inst_offset) {
3202 if (ins->dreg == last_ins->dreg) {
3203 MONO_DELETE_INS (bb, ins);
3206 ins->opcode = OP_MOVE;
3207 ins->sreg1 = last_ins->dreg;
3210 //g_assert_not_reached ();
3214 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3215 * OP_LOAD_MEMBASE offset(basereg), reg
3217 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3218 * OP_ICONST reg, imm
3220 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3221 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3222 ins->inst_basereg == last_ins->inst_destbasereg &&
3223 ins->inst_offset == last_ins->inst_offset) {
3224 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3225 ins->opcode = OP_ICONST;
3226 ins->inst_c0 = last_ins->inst_imm;
3227 g_assert_not_reached (); // check this rule
3231 case OP_LOADU1_MEMBASE:
3232 case OP_LOADI1_MEMBASE:
3233 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3234 ins->inst_basereg == last_ins->inst_destbasereg &&
3235 ins->inst_offset == last_ins->inst_offset) {
3236 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3237 ins->sreg1 = last_ins->sreg1;
3240 case OP_LOADU2_MEMBASE:
3241 case OP_LOADI2_MEMBASE:
3242 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3243 ins->inst_basereg == last_ins->inst_destbasereg &&
3244 ins->inst_offset == last_ins->inst_offset) {
3245 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3246 ins->sreg1 = last_ins->sreg1;
3250 ins->opcode = OP_MOVE;
3254 if (ins->dreg == ins->sreg1) {
3255 MONO_DELETE_INS (bb, ins);
3259 * OP_MOVE sreg, dreg
3260 * OP_MOVE dreg, sreg
3262 if (last_ins && last_ins->opcode == OP_MOVE &&
3263 ins->sreg1 == last_ins->dreg &&
3264 ins->dreg == last_ins->sreg1) {
3265 MONO_DELETE_INS (bb, ins);
3274 * the branch_cc_table should maintain the order of these
3288 branch_cc_table [] = {
3302 #define ADD_NEW_INS(cfg,dest,op) do { \
3303 MONO_INST_NEW ((cfg), (dest), (op)); \
3304 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3308 map_to_reg_reg_op (int op)
3317 case OP_COMPARE_IMM:
3319 case OP_ICOMPARE_IMM:
3333 case OP_LOAD_MEMBASE:
3334 return OP_LOAD_MEMINDEX;
3335 case OP_LOADI4_MEMBASE:
3336 return OP_LOADI4_MEMINDEX;
3337 case OP_LOADU4_MEMBASE:
3338 return OP_LOADU4_MEMINDEX;
3339 case OP_LOADU1_MEMBASE:
3340 return OP_LOADU1_MEMINDEX;
3341 case OP_LOADI2_MEMBASE:
3342 return OP_LOADI2_MEMINDEX;
3343 case OP_LOADU2_MEMBASE:
3344 return OP_LOADU2_MEMINDEX;
3345 case OP_LOADI1_MEMBASE:
3346 return OP_LOADI1_MEMINDEX;
3347 case OP_STOREI1_MEMBASE_REG:
3348 return OP_STOREI1_MEMINDEX;
3349 case OP_STOREI2_MEMBASE_REG:
3350 return OP_STOREI2_MEMINDEX;
3351 case OP_STOREI4_MEMBASE_REG:
3352 return OP_STOREI4_MEMINDEX;
3353 case OP_STORE_MEMBASE_REG:
3354 return OP_STORE_MEMINDEX;
3355 case OP_STORER4_MEMBASE_REG:
3356 return OP_STORER4_MEMINDEX;
3357 case OP_STORER8_MEMBASE_REG:
3358 return OP_STORER8_MEMINDEX;
3359 case OP_STORE_MEMBASE_IMM:
3360 return OP_STORE_MEMBASE_REG;
3361 case OP_STOREI1_MEMBASE_IMM:
3362 return OP_STOREI1_MEMBASE_REG;
3363 case OP_STOREI2_MEMBASE_IMM:
3364 return OP_STOREI2_MEMBASE_REG;
3365 case OP_STOREI4_MEMBASE_IMM:
3366 return OP_STOREI4_MEMBASE_REG;
3368 g_assert_not_reached ();
3372 * Remove from the instruction list the instructions that can't be
3373 * represented with very simple instructions with no register
3377 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3379 MonoInst *ins, *temp, *last_ins = NULL;
3380 int rot_amount, imm8, low_imm;
3382 MONO_BB_FOR_EACH_INS (bb, ins) {
3384 switch (ins->opcode) {
3388 case OP_COMPARE_IMM:
3389 case OP_ICOMPARE_IMM:
3403 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3404 int opcode2 = mono_op_imm_to_op (ins->opcode);
3405 ADD_NEW_INS (cfg, temp, OP_ICONST);
3406 temp->inst_c0 = ins->inst_imm;
3407 temp->dreg = mono_alloc_ireg (cfg);
3408 ins->sreg2 = temp->dreg;
3410 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3411 ins->opcode = opcode2;
3413 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3419 if (ins->inst_imm == 1) {
3420 ins->opcode = OP_MOVE;
3423 if (ins->inst_imm == 0) {
3424 ins->opcode = OP_ICONST;
3428 imm8 = mono_is_power_of_two (ins->inst_imm);
3430 ins->opcode = OP_SHL_IMM;
3431 ins->inst_imm = imm8;
3434 ADD_NEW_INS (cfg, temp, OP_ICONST);
3435 temp->inst_c0 = ins->inst_imm;
3436 temp->dreg = mono_alloc_ireg (cfg);
3437 ins->sreg2 = temp->dreg;
3438 ins->opcode = OP_IMUL;
3444 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3445 /* ARM sets the C flag to 1 if there was _no_ overflow */
3446 ins->next->opcode = OP_COND_EXC_NC;
3449 case OP_IDIV_UN_IMM:
3451 case OP_IREM_UN_IMM: {
3452 int opcode2 = mono_op_imm_to_op (ins->opcode);
3453 ADD_NEW_INS (cfg, temp, OP_ICONST);
3454 temp->inst_c0 = ins->inst_imm;
3455 temp->dreg = mono_alloc_ireg (cfg);
3456 ins->sreg2 = temp->dreg;
3458 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3459 ins->opcode = opcode2;
3462 case OP_LOCALLOC_IMM:
3463 ADD_NEW_INS (cfg, temp, OP_ICONST);
3464 temp->inst_c0 = ins->inst_imm;
3465 temp->dreg = mono_alloc_ireg (cfg);
3466 ins->sreg1 = temp->dreg;
3467 ins->opcode = OP_LOCALLOC;
3469 case OP_LOAD_MEMBASE:
3470 case OP_LOADI4_MEMBASE:
3471 case OP_LOADU4_MEMBASE:
3472 case OP_LOADU1_MEMBASE:
3473 /* we can do two things: load the immed in a register
3474 * and use an indexed load, or see if the immed can be
3475 * represented as an ad_imm + a load with a smaller offset
3476 * that fits. We just do the first for now, optimize later.
3478 if (arm_is_imm12 (ins->inst_offset))
3480 ADD_NEW_INS (cfg, temp, OP_ICONST);
3481 temp->inst_c0 = ins->inst_offset;
3482 temp->dreg = mono_alloc_ireg (cfg);
3483 ins->sreg2 = temp->dreg;
3484 ins->opcode = map_to_reg_reg_op (ins->opcode);
3486 case OP_LOADI2_MEMBASE:
3487 case OP_LOADU2_MEMBASE:
3488 case OP_LOADI1_MEMBASE:
3489 if (arm_is_imm8 (ins->inst_offset))
3491 ADD_NEW_INS (cfg, temp, OP_ICONST);
3492 temp->inst_c0 = ins->inst_offset;
3493 temp->dreg = mono_alloc_ireg (cfg);
3494 ins->sreg2 = temp->dreg;
3495 ins->opcode = map_to_reg_reg_op (ins->opcode);
3497 case OP_LOADR4_MEMBASE:
3498 case OP_LOADR8_MEMBASE:
3499 if (arm_is_fpimm8 (ins->inst_offset))
3501 low_imm = ins->inst_offset & 0x1ff;
3502 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3503 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3504 temp->inst_imm = ins->inst_offset & ~0x1ff;
3505 temp->sreg1 = ins->inst_basereg;
3506 temp->dreg = mono_alloc_ireg (cfg);
3507 ins->inst_basereg = temp->dreg;
3508 ins->inst_offset = low_imm;
3512 ADD_NEW_INS (cfg, temp, OP_ICONST);
3513 temp->inst_c0 = ins->inst_offset;
3514 temp->dreg = mono_alloc_ireg (cfg);
3516 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3517 add_ins->sreg1 = ins->inst_basereg;
3518 add_ins->sreg2 = temp->dreg;
3519 add_ins->dreg = mono_alloc_ireg (cfg);
3521 ins->inst_basereg = add_ins->dreg;
3522 ins->inst_offset = 0;
3525 case OP_STORE_MEMBASE_REG:
3526 case OP_STOREI4_MEMBASE_REG:
3527 case OP_STOREI1_MEMBASE_REG:
3528 if (arm_is_imm12 (ins->inst_offset))
3530 ADD_NEW_INS (cfg, temp, OP_ICONST);
3531 temp->inst_c0 = ins->inst_offset;
3532 temp->dreg = mono_alloc_ireg (cfg);
3533 ins->sreg2 = temp->dreg;
3534 ins->opcode = map_to_reg_reg_op (ins->opcode);
3536 case OP_STOREI2_MEMBASE_REG:
3537 if (arm_is_imm8 (ins->inst_offset))
3539 ADD_NEW_INS (cfg, temp, OP_ICONST);
3540 temp->inst_c0 = ins->inst_offset;
3541 temp->dreg = mono_alloc_ireg (cfg);
3542 ins->sreg2 = temp->dreg;
3543 ins->opcode = map_to_reg_reg_op (ins->opcode);
3545 case OP_STORER4_MEMBASE_REG:
3546 case OP_STORER8_MEMBASE_REG:
3547 if (arm_is_fpimm8 (ins->inst_offset))
3549 low_imm = ins->inst_offset & 0x1ff;
3550 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3551 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3552 temp->inst_imm = ins->inst_offset & ~0x1ff;
3553 temp->sreg1 = ins->inst_destbasereg;
3554 temp->dreg = mono_alloc_ireg (cfg);
3555 ins->inst_destbasereg = temp->dreg;
3556 ins->inst_offset = low_imm;
3560 ADD_NEW_INS (cfg, temp, OP_ICONST);
3561 temp->inst_c0 = ins->inst_offset;
3562 temp->dreg = mono_alloc_ireg (cfg);
3564 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3565 add_ins->sreg1 = ins->inst_destbasereg;
3566 add_ins->sreg2 = temp->dreg;
3567 add_ins->dreg = mono_alloc_ireg (cfg);
3569 ins->inst_destbasereg = add_ins->dreg;
3570 ins->inst_offset = 0;
3573 case OP_STORE_MEMBASE_IMM:
3574 case OP_STOREI1_MEMBASE_IMM:
3575 case OP_STOREI2_MEMBASE_IMM:
3576 case OP_STOREI4_MEMBASE_IMM:
3577 ADD_NEW_INS (cfg, temp, OP_ICONST);
3578 temp->inst_c0 = ins->inst_imm;
3579 temp->dreg = mono_alloc_ireg (cfg);
3580 ins->sreg1 = temp->dreg;
3581 ins->opcode = map_to_reg_reg_op (ins->opcode);
3583 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3586 gboolean swap = FALSE;
3590 /* Optimized away */
3595 /* Some fp compares require swapped operands */
3596 switch (ins->next->opcode) {
3598 ins->next->opcode = OP_FBLT;
3602 ins->next->opcode = OP_FBLT_UN;
3606 ins->next->opcode = OP_FBGE;
3610 ins->next->opcode = OP_FBGE_UN;
3618 ins->sreg1 = ins->sreg2;
3627 bb->last_ins = last_ins;
3628 bb->max_vreg = cfg->next_vreg;
3632 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3636 if (long_ins->opcode == OP_LNEG) {
3638 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3639 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3645 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3647 /* sreg is a float, dreg is an integer reg */
3649 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3651 ARM_TOSIZD (code, vfp_scratch1, sreg);
3653 ARM_TOUIZD (code, vfp_scratch1, sreg);
3654 ARM_FMRS (code, dreg, vfp_scratch1);
3655 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3659 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3660 else if (size == 2) {
3661 ARM_SHL_IMM (code, dreg, dreg, 16);
3662 ARM_SHR_IMM (code, dreg, dreg, 16);
3666 ARM_SHL_IMM (code, dreg, dreg, 24);
3667 ARM_SAR_IMM (code, dreg, dreg, 24);
3668 } else if (size == 2) {
3669 ARM_SHL_IMM (code, dreg, dreg, 16);
3670 ARM_SAR_IMM (code, dreg, dreg, 16);
3677 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3679 /* sreg is a float, dreg is an integer reg */
3681 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3683 ARM_TOSIZS (code, vfp_scratch1, sreg);
3685 ARM_TOUIZS (code, vfp_scratch1, sreg);
3686 ARM_FMRS (code, dreg, vfp_scratch1);
3687 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3691 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3692 else if (size == 2) {
3693 ARM_SHL_IMM (code, dreg, dreg, 16);
3694 ARM_SHR_IMM (code, dreg, dreg, 16);
3698 ARM_SHL_IMM (code, dreg, dreg, 24);
3699 ARM_SAR_IMM (code, dreg, dreg, 24);
3700 } else if (size == 2) {
3701 ARM_SHL_IMM (code, dreg, dreg, 16);
3702 ARM_SAR_IMM (code, dreg, dreg, 16);
3708 #endif /* #ifndef DISABLE_JIT */
3710 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3713 emit_thunk (guint8 *code, gconstpointer target)
3717 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3718 if (thumb_supported)
3719 ARM_BX (code, ARMREG_IP);
3721 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3722 *(guint32*)code = (guint32)target;
3724 mono_arch_flush_icache (p, code - p);
3728 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3730 MonoJitInfo *ji = NULL;
3731 MonoThunkJitInfo *info;
3734 guint8 *orig_target;
3735 guint8 *target_thunk;
3738 domain = mono_domain_get ();
3742 * This can be called multiple times during JITting,
3743 * save the current position in cfg->arch to avoid
3744 * doing a O(n^2) search.
3746 if (!cfg->arch.thunks) {
3747 cfg->arch.thunks = cfg->thunks;
3748 cfg->arch.thunks_size = cfg->thunk_area;
3750 thunks = cfg->arch.thunks;
3751 thunks_size = cfg->arch.thunks_size;
3753 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3754 g_assert_not_reached ();
3757 g_assert (*(guint32*)thunks == 0);
3758 emit_thunk (thunks, target);
3759 arm_patch (code, thunks);
3761 cfg->arch.thunks += THUNK_SIZE;
3762 cfg->arch.thunks_size -= THUNK_SIZE;
3764 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3766 info = mono_jit_info_get_thunk_info (ji);
3769 thunks = (guint8*)ji->code_start + info->thunks_offset;
3770 thunks_size = info->thunks_size;
3772 orig_target = mono_arch_get_call_target (code + 4);
3774 mono_mini_arch_lock ();
3776 target_thunk = NULL;
3777 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3778 /* The call already points to a thunk, because of trampolines etc. */
3779 target_thunk = orig_target;
3781 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3782 if (((guint32*)p) [0] == 0) {
3786 } else if (((guint32*)p) [2] == (guint32)target) {
3787 /* Thunk already points to target */
3794 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3796 if (!target_thunk) {
3797 mono_mini_arch_unlock ();
3798 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3799 g_assert_not_reached ();
3802 emit_thunk (target_thunk, target);
3803 arm_patch (code, target_thunk);
3804 mono_arch_flush_icache (code, 4);
3806 mono_mini_arch_unlock ();
3811 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3813 guint32 *code32 = (void*)code;
3814 guint32 ins = *code32;
3815 guint32 prim = (ins >> 25) & 7;
3816 guint32 tval = GPOINTER_TO_UINT (target);
3818 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3819 if (prim == 5) { /* 101b */
3820 /* the diff starts 8 bytes from the branch opcode */
3821 gint diff = target - code - 8;
3823 gint tmask = 0xffffffff;
3824 if (tval & 1) { /* entering thumb mode */
3825 diff = target - 1 - code - 8;
3826 g_assert (thumb_supported);
3827 tbits = 0xf << 28; /* bl->blx bit pattern */
3828 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3829 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3833 tmask = ~(1 << 24); /* clear the link bit */
3834 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3839 if (diff <= 33554431) {
3841 ins = (ins & 0xff000000) | diff;
3843 *code32 = ins | tbits;
3847 /* diff between 0 and -33554432 */
3848 if (diff >= -33554432) {
3850 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3852 *code32 = ins | tbits;
3857 handle_thunk (cfg, domain, code, target);
3862 * The alternative call sequences looks like this:
3864 * ldr ip, [pc] // loads the address constant
3865 * b 1f // jumps around the constant
3866 * address constant embedded in the code
3871 * There are two cases for patching:
3872 * a) at the end of method emission: in this case code points to the start
3873 * of the call sequence
3874 * b) during runtime patching of the call site: in this case code points
3875 * to the mov pc, ip instruction
3877 * We have to handle also the thunk jump code sequence:
3881 * address constant // execution never reaches here
3883 if ((ins & 0x0ffffff0) == 0x12fff10) {
3884 /* Branch and exchange: the address is constructed in a reg
3885 * We can patch BX when the code sequence is the following:
3886 * ldr ip, [pc, #0] ; 0x8
3893 guint8 *emit = (guint8*)ccode;
3894 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3896 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3897 ARM_BX (emit, ARMREG_IP);
3899 /*patching from magic trampoline*/
3900 if (ins == ccode [3]) {
3901 g_assert (code32 [-4] == ccode [0]);
3902 g_assert (code32 [-3] == ccode [1]);
3903 g_assert (code32 [-1] == ccode [2]);
3904 code32 [-2] = (guint32)target;
3907 /*patching from JIT*/
3908 if (ins == ccode [0]) {
3909 g_assert (code32 [1] == ccode [1]);
3910 g_assert (code32 [3] == ccode [2]);
3911 g_assert (code32 [4] == ccode [3]);
3912 code32 [2] = (guint32)target;
3915 g_assert_not_reached ();
3916 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3924 guint8 *emit = (guint8*)ccode;
3925 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3927 ARM_BLX_REG (emit, ARMREG_IP);
3929 g_assert (code32 [-3] == ccode [0]);
3930 g_assert (code32 [-2] == ccode [1]);
3931 g_assert (code32 [0] == ccode [2]);
3933 code32 [-1] = (guint32)target;
3936 guint32 *tmp = ccode;
3937 guint8 *emit = (guint8*)tmp;
3938 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3939 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3940 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3941 ARM_BX (emit, ARMREG_IP);
3942 if (ins == ccode [2]) {
3943 g_assert_not_reached (); // should be -2 ...
3944 code32 [-1] = (guint32)target;
3947 if (ins == ccode [0]) {
3948 /* handles both thunk jump code and the far call sequence */
3949 code32 [2] = (guint32)target;
3952 g_assert_not_reached ();
3954 // g_print ("patched with 0x%08x\n", ins);
3958 arm_patch (guchar *code, const guchar *target)
3960 arm_patch_general (NULL, NULL, code, target);
3964 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3965 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3966 * to be used with the emit macros.
3967 * Return -1 otherwise.
3970 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3973 for (i = 0; i < 31; i+= 2) {
3974 res = (val << (32 - i)) | (val >> i);
3977 *rot_amount = i? 32 - i: 0;
3984 * Emits in code a sequence of instructions that load the value 'val'
3985 * into the dreg register. Uses at most 4 instructions.
3988 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3990 int imm8, rot_amount;
3992 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3993 /* skip the constant pool */
3999 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4000 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4001 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4005 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4006 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4007 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4008 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4011 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4013 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4017 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4019 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4021 if (val & 0xFF0000) {
4022 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4024 if (val & 0xFF000000) {
4025 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4027 } else if (val & 0xFF00) {
4028 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4029 if (val & 0xFF0000) {
4030 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4032 if (val & 0xFF000000) {
4033 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4035 } else if (val & 0xFF0000) {
4036 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4037 if (val & 0xFF000000) {
4038 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4041 //g_assert_not_reached ();
4047 mono_arm_thumb_supported (void)
4049 return thumb_supported;
4053 mono_arm_eabi_supported (void)
4055 return eabi_supported;
4059 mono_arm_i8_align (void)
4067 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4072 call = (MonoCallInst*)ins;
4073 cinfo = call->call_info;
4075 switch (cinfo->ret.storage) {
4076 case RegTypeStructByVal:
4078 MonoInst *loc = cfg->arch.vret_addr_loc;
4081 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4082 /* The JIT treats this as a normal call */
4086 /* Load the destination address */
4087 g_assert (loc && loc->opcode == OP_REGOFFSET);
4089 if (arm_is_imm12 (loc->inst_offset)) {
4090 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4092 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4093 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4096 if (cinfo->ret.storage == RegTypeStructByVal) {
4097 int rsize = cinfo->ret.struct_size;
4099 for (i = 0; i < cinfo->ret.nregs; ++i) {
4100 g_assert (rsize >= 0);
4105 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4108 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4111 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4117 for (i = 0; i < cinfo->ret.nregs; ++i) {
4118 if (cinfo->ret.esize == 4)
4119 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4121 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4130 switch (ins->opcode) {
4133 case OP_FCALL_MEMBASE:
4135 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4136 if (sig_ret->type == MONO_TYPE_R4) {
4137 if (IS_HARD_FLOAT) {
4138 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4140 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4141 ARM_CVTS (code, ins->dreg, ins->dreg);
4144 if (IS_HARD_FLOAT) {
4145 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4147 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4154 case OP_RCALL_MEMBASE: {
4159 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4160 g_assert (sig_ret->type == MONO_TYPE_R4);
4161 if (IS_HARD_FLOAT) {
4162 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4164 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4165 ARM_CPYS (code, ins->dreg, ins->dreg);
4177 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4182 guint8 *code = cfg->native_code + cfg->code_len;
4183 MonoInst *last_ins = NULL;
4184 guint last_offset = 0;
4186 int imm8, rot_amount;
4188 /* we don't align basic blocks of loops on arm */
4190 if (cfg->verbose_level > 2)
4191 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4193 cpos = bb->max_offset;
4195 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4196 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4197 (gpointer)"mono_break");
4198 code = emit_call_seq (cfg, code);
4201 MONO_BB_FOR_EACH_INS (bb, ins) {
4202 offset = code - cfg->native_code;
4204 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4206 if (offset > (cfg->code_size - max_len - 16)) {
4207 cfg->code_size *= 2;
4208 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4209 code = cfg->native_code + offset;
4211 // if (ins->cil_code)
4212 // g_print ("cil code\n");
4213 mono_debug_record_line_number (cfg, ins, offset);
4215 switch (ins->opcode) {
4216 case OP_MEMORY_BARRIER:
4218 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4219 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4223 code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4226 code = emit_tls_set (code, ins->sreg1, ins->inst_offset);
4228 case OP_ATOMIC_EXCHANGE_I4:
4229 case OP_ATOMIC_CAS_I4:
4230 case OP_ATOMIC_ADD_I4: {
4234 g_assert (v7_supported);
4237 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4239 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4241 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4245 g_assert (cfg->arch.atomic_tmp_offset != -1);
4246 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4248 switch (ins->opcode) {
4249 case OP_ATOMIC_EXCHANGE_I4:
4251 ARM_DMB (code, ARM_DMB_SY);
4252 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4253 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4254 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4256 ARM_B_COND (code, ARMCOND_NE, 0);
4257 arm_patch (buf [1], buf [0]);
4259 case OP_ATOMIC_CAS_I4:
4260 ARM_DMB (code, ARM_DMB_SY);
4262 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4263 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4265 ARM_B_COND (code, ARMCOND_NE, 0);
4266 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4267 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4269 ARM_B_COND (code, ARMCOND_NE, 0);
4270 arm_patch (buf [2], buf [0]);
4271 arm_patch (buf [1], code);
4273 case OP_ATOMIC_ADD_I4:
4275 ARM_DMB (code, ARM_DMB_SY);
4276 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4277 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4278 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4279 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4281 ARM_B_COND (code, ARMCOND_NE, 0);
4282 arm_patch (buf [1], buf [0]);
4285 g_assert_not_reached ();
4288 ARM_DMB (code, ARM_DMB_SY);
4289 if (tmpreg != ins->dreg)
4290 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4291 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4294 case OP_ATOMIC_LOAD_I1:
4295 case OP_ATOMIC_LOAD_U1:
4296 case OP_ATOMIC_LOAD_I2:
4297 case OP_ATOMIC_LOAD_U2:
4298 case OP_ATOMIC_LOAD_I4:
4299 case OP_ATOMIC_LOAD_U4:
4300 case OP_ATOMIC_LOAD_R4:
4301 case OP_ATOMIC_LOAD_R8: {
4302 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4303 ARM_DMB (code, ARM_DMB_SY);
4305 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4307 switch (ins->opcode) {
4308 case OP_ATOMIC_LOAD_I1:
4309 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4311 case OP_ATOMIC_LOAD_U1:
4312 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4314 case OP_ATOMIC_LOAD_I2:
4315 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4317 case OP_ATOMIC_LOAD_U2:
4318 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4320 case OP_ATOMIC_LOAD_I4:
4321 case OP_ATOMIC_LOAD_U4:
4322 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4324 case OP_ATOMIC_LOAD_R4:
4326 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4327 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4329 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4330 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4331 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4332 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4333 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4336 case OP_ATOMIC_LOAD_R8:
4337 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4338 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4342 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4343 ARM_DMB (code, ARM_DMB_SY);
4346 case OP_ATOMIC_STORE_I1:
4347 case OP_ATOMIC_STORE_U1:
4348 case OP_ATOMIC_STORE_I2:
4349 case OP_ATOMIC_STORE_U2:
4350 case OP_ATOMIC_STORE_I4:
4351 case OP_ATOMIC_STORE_U4:
4352 case OP_ATOMIC_STORE_R4:
4353 case OP_ATOMIC_STORE_R8: {
4354 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4355 ARM_DMB (code, ARM_DMB_SY);
4357 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4359 switch (ins->opcode) {
4360 case OP_ATOMIC_STORE_I1:
4361 case OP_ATOMIC_STORE_U1:
4362 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4364 case OP_ATOMIC_STORE_I2:
4365 case OP_ATOMIC_STORE_U2:
4366 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4368 case OP_ATOMIC_STORE_I4:
4369 case OP_ATOMIC_STORE_U4:
4370 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4372 case OP_ATOMIC_STORE_R4:
4374 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4375 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4377 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4378 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4379 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4380 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4381 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4384 case OP_ATOMIC_STORE_R8:
4385 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4386 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4390 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4391 ARM_DMB (code, ARM_DMB_SY);
4395 ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4398 ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4400 case OP_STOREI1_MEMBASE_IMM:
4401 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4402 g_assert (arm_is_imm12 (ins->inst_offset));
4403 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4405 case OP_STOREI2_MEMBASE_IMM:
4406 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4407 g_assert (arm_is_imm8 (ins->inst_offset));
4408 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4410 case OP_STORE_MEMBASE_IMM:
4411 case OP_STOREI4_MEMBASE_IMM:
4412 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4413 g_assert (arm_is_imm12 (ins->inst_offset));
4414 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4416 case OP_STOREI1_MEMBASE_REG:
4417 g_assert (arm_is_imm12 (ins->inst_offset));
4418 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4420 case OP_STOREI2_MEMBASE_REG:
4421 g_assert (arm_is_imm8 (ins->inst_offset));
4422 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4424 case OP_STORE_MEMBASE_REG:
4425 case OP_STOREI4_MEMBASE_REG:
4426 /* this case is special, since it happens for spill code after lowering has been called */
4427 if (arm_is_imm12 (ins->inst_offset)) {
4428 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4430 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4431 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4434 case OP_STOREI1_MEMINDEX:
4435 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4437 case OP_STOREI2_MEMINDEX:
4438 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4440 case OP_STORE_MEMINDEX:
4441 case OP_STOREI4_MEMINDEX:
4442 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4445 g_assert_not_reached ();
4447 case OP_LOAD_MEMINDEX:
4448 case OP_LOADI4_MEMINDEX:
4449 case OP_LOADU4_MEMINDEX:
4450 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4452 case OP_LOADI1_MEMINDEX:
4453 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4455 case OP_LOADU1_MEMINDEX:
4456 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4458 case OP_LOADI2_MEMINDEX:
4459 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4461 case OP_LOADU2_MEMINDEX:
4462 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4464 case OP_LOAD_MEMBASE:
4465 case OP_LOADI4_MEMBASE:
4466 case OP_LOADU4_MEMBASE:
4467 /* this case is special, since it happens for spill code after lowering has been called */
4468 if (arm_is_imm12 (ins->inst_offset)) {
4469 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4471 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4472 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4475 case OP_LOADI1_MEMBASE:
4476 g_assert (arm_is_imm8 (ins->inst_offset));
4477 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4479 case OP_LOADU1_MEMBASE:
4480 g_assert (arm_is_imm12 (ins->inst_offset));
4481 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4483 case OP_LOADU2_MEMBASE:
4484 g_assert (arm_is_imm8 (ins->inst_offset));
4485 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4487 case OP_LOADI2_MEMBASE:
4488 g_assert (arm_is_imm8 (ins->inst_offset));
4489 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4491 case OP_ICONV_TO_I1:
4492 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4493 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4495 case OP_ICONV_TO_I2:
4496 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4497 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4499 case OP_ICONV_TO_U1:
4500 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4502 case OP_ICONV_TO_U2:
4503 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4504 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4508 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4510 case OP_COMPARE_IMM:
4511 case OP_ICOMPARE_IMM:
4512 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4513 g_assert (imm8 >= 0);
4514 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4518 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4519 * So instead of emitting a trap, we emit a call a C function and place a
4522 //*(int*)code = 0xef9f0001;
4525 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4526 (gpointer)"mono_break");
4527 code = emit_call_seq (cfg, code);
4529 case OP_RELAXED_NOP:
4534 case OP_DUMMY_STORE:
4535 case OP_DUMMY_ICONST:
4536 case OP_DUMMY_R8CONST:
4537 case OP_NOT_REACHED:
4540 case OP_IL_SEQ_POINT:
4541 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4543 case OP_SEQ_POINT: {
4545 MonoInst *info_var = cfg->arch.seq_point_info_var;
4546 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4547 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4548 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4550 int dreg = ARMREG_LR;
4553 if (cfg->soft_breakpoints) {
4554 g_assert (!cfg->compile_aot);
4559 * For AOT, we use one got slot per method, which will point to a
4560 * SeqPointInfo structure, containing all the information required
4561 * by the code below.
4563 if (cfg->compile_aot) {
4564 g_assert (info_var);
4565 g_assert (info_var->opcode == OP_REGOFFSET);
4568 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4570 * Read from the single stepping trigger page. This will cause a
4571 * SIGSEGV when single stepping is enabled.
4572 * We do this _before_ the breakpoint, so single stepping after
4573 * a breakpoint is hit will step to the next IL offset.
4575 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4578 /* Single step check */
4579 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4580 if (cfg->soft_breakpoints) {
4581 /* Load the address of the sequence point method variable. */
4582 var = ss_method_var;
4584 g_assert (var->opcode == OP_REGOFFSET);
4585 code = emit_ldr_imm (code, dreg, var->inst_basereg, var->inst_offset);
4586 /* Read the value and check whether it is non-zero. */
4587 ARM_LDR_IMM (code, dreg, dreg, 0);
4588 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4589 /* Call it conditionally. */
4590 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4592 if (cfg->compile_aot) {
4593 /* Load the trigger page addr from the variable initialized in the prolog */
4594 var = ss_trigger_page_var;
4596 g_assert (var->opcode == OP_REGOFFSET);
4597 code = emit_ldr_imm (code, dreg, var->inst_basereg, var->inst_offset);
4599 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4601 *(int*)code = (int)ss_trigger_page;
4604 ARM_LDR_IMM (code, dreg, dreg, 0);
4608 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4610 /* Breakpoint check */
4611 if (cfg->compile_aot) {
4612 guint32 offset = code - cfg->native_code;
4616 code = emit_ldr_imm (code, dreg, var->inst_basereg, var->inst_offset);
4617 /* Add the offset */
4618 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4619 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4620 if (arm_is_imm12 ((int)val)) {
4621 ARM_LDR_IMM (code, dreg, dreg, val);
4623 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4625 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4627 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4628 g_assert (!(val & 0xFF000000));
4630 ARM_LDR_IMM (code, dreg, dreg, 0);
4632 /* What is faster, a branch or a load ? */
4633 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4634 /* The breakpoint instruction */
4635 if (cfg->soft_breakpoints)
4636 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4638 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4639 } else if (cfg->soft_breakpoints) {
4640 /* Load the address of the breakpoint method into ip. */
4641 var = bp_method_var;
4643 g_assert (var->opcode == OP_REGOFFSET);
4644 g_assert (arm_is_imm12 (var->inst_offset));
4645 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4648 * A placeholder for a possible breakpoint inserted by
4649 * mono_arch_set_breakpoint ().
4654 * A placeholder for a possible breakpoint inserted by
4655 * mono_arch_set_breakpoint ().
4657 for (i = 0; i < 4; ++i)
4662 * Add an additional nop so skipping the bp doesn't cause the ip to point
4663 * to another IL offset.
4671 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4674 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4678 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4681 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4682 g_assert (imm8 >= 0);
4683 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4687 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4688 g_assert (imm8 >= 0);
4689 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4693 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4694 g_assert (imm8 >= 0);
4695 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4698 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4699 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4701 case OP_IADD_OVF_UN:
4702 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4703 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4706 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4707 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4709 case OP_ISUB_OVF_UN:
4710 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4711 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4713 case OP_ADD_OVF_CARRY:
4714 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4715 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4717 case OP_ADD_OVF_UN_CARRY:
4718 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4719 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4721 case OP_SUB_OVF_CARRY:
4722 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4723 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4725 case OP_SUB_OVF_UN_CARRY:
4726 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4727 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4731 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4734 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4735 g_assert (imm8 >= 0);
4736 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4739 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4743 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4747 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4748 g_assert (imm8 >= 0);
4749 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4753 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4754 g_assert (imm8 >= 0);
4755 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4757 case OP_ARM_RSBS_IMM:
4758 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4759 g_assert (imm8 >= 0);
4760 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4762 case OP_ARM_RSC_IMM:
4763 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4764 g_assert (imm8 >= 0);
4765 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4768 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4772 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4773 g_assert (imm8 >= 0);
4774 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4777 g_assert (v7s_supported || v7k_supported);
4778 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4781 g_assert (v7s_supported || v7k_supported);
4782 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4785 g_assert (v7s_supported || v7k_supported);
4786 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4787 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4790 g_assert (v7s_supported || v7k_supported);
4791 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4792 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4796 g_assert_not_reached ();
4798 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4802 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4803 g_assert (imm8 >= 0);
4804 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4807 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4811 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4812 g_assert (imm8 >= 0);
4813 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4816 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4821 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4822 else if (ins->dreg != ins->sreg1)
4823 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4826 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4831 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4832 else if (ins->dreg != ins->sreg1)
4833 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4836 case OP_ISHR_UN_IMM:
4838 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4839 else if (ins->dreg != ins->sreg1)
4840 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4843 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4846 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4849 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4852 if (ins->dreg == ins->sreg2)
4853 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4855 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4858 g_assert_not_reached ();
4861 /* FIXME: handle ovf/ sreg2 != dreg */
4862 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4863 /* FIXME: MUL doesn't set the C/O flags on ARM */
4865 case OP_IMUL_OVF_UN:
4866 /* FIXME: handle ovf/ sreg2 != dreg */
4867 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4868 /* FIXME: MUL doesn't set the C/O flags on ARM */
4871 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4874 /* Load the GOT offset */
4875 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4876 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4878 *(gpointer*)code = NULL;
4880 /* Load the value from the GOT */
4881 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4883 case OP_OBJC_GET_SELECTOR:
4884 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4885 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4887 *(gpointer*)code = NULL;
4889 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4891 case OP_ICONV_TO_I4:
4892 case OP_ICONV_TO_U4:
4894 if (ins->dreg != ins->sreg1)
4895 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4898 int saved = ins->sreg2;
4899 if (ins->sreg2 == ARM_LSW_REG) {
4900 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4903 if (ins->sreg1 != ARM_LSW_REG)
4904 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4905 if (saved != ARM_MSW_REG)
4906 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4910 if (IS_VFP && ins->dreg != ins->sreg1)
4911 ARM_CPYD (code, ins->dreg, ins->sreg1);
4914 if (IS_VFP && ins->dreg != ins->sreg1)
4915 ARM_CPYS (code, ins->dreg, ins->sreg1);
4917 case OP_MOVE_F_TO_I4:
4919 ARM_FMRS (code, ins->dreg, ins->sreg1);
4921 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4922 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4923 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4924 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4927 case OP_MOVE_I4_TO_F:
4929 ARM_FMSR (code, ins->dreg, ins->sreg1);
4931 ARM_FMSR (code, ins->dreg, ins->sreg1);
4932 ARM_CVTS (code, ins->dreg, ins->dreg);
4935 case OP_FCONV_TO_R4:
4938 ARM_CVTD (code, ins->dreg, ins->sreg1);
4940 ARM_CVTD (code, ins->dreg, ins->sreg1);
4941 ARM_CVTS (code, ins->dreg, ins->dreg);
4946 MonoCallInst *call = (MonoCallInst*)ins;
4949 * The stack looks like the following:
4950 * <caller argument area>
4953 * <callee argument area>
4954 * Need to copy the arguments from the callee argument area to
4955 * the caller argument area, and pop the frame.
4957 if (call->stack_usage) {
4958 int i, prev_sp_offset = 0;
4960 /* Compute size of saved registers restored below */
4962 prev_sp_offset = 2 * 4;
4964 prev_sp_offset = 1 * 4;
4965 for (i = 0; i < 16; ++i) {
4966 if (cfg->used_int_regs & (1 << i))
4967 prev_sp_offset += 4;
4970 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4972 /* Copy arguments on the stack to our argument area */
4973 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4974 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4975 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4980 * Keep in sync with mono_arch_emit_epilog
4982 g_assert (!cfg->method->save_lmf);
4984 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4986 if (cfg->used_int_regs)
4987 ARM_POP (code, cfg->used_int_regs);
4988 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4990 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4993 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4994 if (cfg->compile_aot) {
4995 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4997 *(gpointer*)code = NULL;
4999 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5001 code = mono_arm_patchable_b (code, ARMCOND_AL);
5002 cfg->thunk_area += THUNK_SIZE;
5007 /* ensure ins->sreg1 is not NULL */
5008 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5011 g_assert (cfg->sig_cookie < 128);
5012 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5013 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5023 call = (MonoCallInst*)ins;
5026 code = emit_float_args (cfg, call, code, &max_len, &offset);
5028 if (ins->flags & MONO_INST_HAS_METHOD)
5029 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5031 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5032 code = emit_call_seq (cfg, code);
5033 ins->flags |= MONO_INST_GC_CALLSITE;
5034 ins->backend.pc_offset = code - cfg->native_code;
5035 code = emit_move_return_value (cfg, ins, code);
5042 case OP_VOIDCALL_REG:
5045 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5047 code = emit_call_reg (code, ins->sreg1);
5048 ins->flags |= MONO_INST_GC_CALLSITE;
5049 ins->backend.pc_offset = code - cfg->native_code;
5050 code = emit_move_return_value (cfg, ins, code);
5052 case OP_FCALL_MEMBASE:
5053 case OP_RCALL_MEMBASE:
5054 case OP_LCALL_MEMBASE:
5055 case OP_VCALL_MEMBASE:
5056 case OP_VCALL2_MEMBASE:
5057 case OP_VOIDCALL_MEMBASE:
5058 case OP_CALL_MEMBASE: {
5059 g_assert (ins->sreg1 != ARMREG_LR);
5060 call = (MonoCallInst*)ins;
5063 code = emit_float_args (cfg, call, code, &max_len, &offset);
5064 if (!arm_is_imm12 (ins->inst_offset)) {
5065 /* sreg1 might be IP */
5066 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5067 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5068 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5069 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5070 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5072 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5073 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5075 ins->flags |= MONO_INST_GC_CALLSITE;
5076 ins->backend.pc_offset = code - cfg->native_code;
5077 code = emit_move_return_value (cfg, ins, code);
5080 case OP_GENERIC_CLASS_INIT: {
5084 byte_offset = MONO_STRUCT_OFFSET (MonoVTable, initialized);
5086 g_assert (arm_is_imm8 (byte_offset));
5087 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5088 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5090 ARM_B_COND (code, ARMCOND_NE, 0);
5092 /* Uninitialized case */
5093 g_assert (ins->sreg1 == ARMREG_R0);
5095 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5096 (gpointer)"mono_generic_class_init");
5097 code = emit_call_seq (cfg, code);
5099 /* Initialized case */
5100 arm_patch (jump, code);
5104 /* round the size to 8 bytes */
5105 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5106 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5107 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5108 /* memzero the area: dreg holds the size, sp is the pointer */
5109 if (ins->flags & MONO_INST_INIT) {
5110 guint8 *start_loop, *branch_to_cond;
5111 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5112 branch_to_cond = code;
5115 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5116 arm_patch (branch_to_cond, code);
5117 /* decrement by 4 and set flags */
5118 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5119 ARM_B_COND (code, ARMCOND_GE, 0);
5120 arm_patch (code - 4, start_loop);
5122 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5123 if (cfg->param_area)
5124 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5129 MonoInst *var = cfg->dyn_call_var;
5132 g_assert (var->opcode == OP_REGOFFSET);
5133 g_assert (arm_is_imm12 (var->inst_offset));
5135 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5136 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5138 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5140 /* Save args buffer */
5141 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5143 /* Set stack slots using R0 as scratch reg */
5144 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5145 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5146 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5147 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5150 /* Set fp argument registers */
5151 if (IS_HARD_FLOAT) {
5152 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5153 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5155 ARM_B_COND (code, ARMCOND_EQ, 0);
5156 for (i = 0; i < FP_PARAM_REGS; ++i) {
5157 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5158 g_assert (arm_is_fpimm8 (offset));
5159 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5161 arm_patch (buf [0], code);
5164 /* Set argument registers */
5165 for (i = 0; i < PARAM_REGS; ++i)
5166 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5169 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5170 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5173 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5174 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5175 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5177 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5181 if (ins->sreg1 != ARMREG_R0)
5182 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5183 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5184 (gpointer)"mono_arch_throw_exception");
5185 code = emit_call_seq (cfg, code);
5189 if (ins->sreg1 != ARMREG_R0)
5190 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5191 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5192 (gpointer)"mono_arch_rethrow_exception");
5193 code = emit_call_seq (cfg, code);
5196 case OP_START_HANDLER: {
5197 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5198 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5201 /* Reserve a param area, see filter-stack.exe */
5203 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5204 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5206 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5207 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5211 if (arm_is_imm12 (spvar->inst_offset)) {
5212 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5214 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5215 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5219 case OP_ENDFILTER: {
5220 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5221 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5224 /* Free the param area */
5226 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5227 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5229 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5230 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5234 if (ins->sreg1 != ARMREG_R0)
5235 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5236 if (arm_is_imm12 (spvar->inst_offset)) {
5237 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5239 g_assert (ARMREG_IP != spvar->inst_basereg);
5240 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5241 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5243 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5246 case OP_ENDFINALLY: {
5247 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5248 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5251 /* Free the param area */
5253 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5254 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5256 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5257 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5261 if (arm_is_imm12 (spvar->inst_offset)) {
5262 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5264 g_assert (ARMREG_IP != spvar->inst_basereg);
5265 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5266 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5268 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5271 case OP_CALL_HANDLER:
5272 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5273 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5274 cfg->thunk_area += THUNK_SIZE;
5275 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5278 if (ins->dreg != ARMREG_R0)
5279 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5283 ins->inst_c0 = code - cfg->native_code;
5286 /*if (ins->inst_target_bb->native_offset) {
5288 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5290 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5291 code = mono_arm_patchable_b (code, ARMCOND_AL);
5295 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5299 * In the normal case we have:
5300 * ldr pc, [pc, ins->sreg1 << 2]
5303 * ldr lr, [pc, ins->sreg1 << 2]
5305 * After follows the data.
5306 * FIXME: add aot support.
5308 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5309 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5310 if (offset + max_len > (cfg->code_size - 16)) {
5311 cfg->code_size += max_len;
5312 cfg->code_size *= 2;
5313 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5314 code = cfg->native_code + offset;
5316 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5318 code += 4 * GPOINTER_TO_INT (ins->klass);
5322 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5323 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5327 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5328 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5332 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5333 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5337 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5338 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5342 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5343 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5346 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5347 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5350 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5351 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5354 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5355 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5358 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5359 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5362 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5363 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5365 case OP_COND_EXC_EQ:
5366 case OP_COND_EXC_NE_UN:
5367 case OP_COND_EXC_LT:
5368 case OP_COND_EXC_LT_UN:
5369 case OP_COND_EXC_GT:
5370 case OP_COND_EXC_GT_UN:
5371 case OP_COND_EXC_GE:
5372 case OP_COND_EXC_GE_UN:
5373 case OP_COND_EXC_LE:
5374 case OP_COND_EXC_LE_UN:
5375 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5377 case OP_COND_EXC_IEQ:
5378 case OP_COND_EXC_INE_UN:
5379 case OP_COND_EXC_ILT:
5380 case OP_COND_EXC_ILT_UN:
5381 case OP_COND_EXC_IGT:
5382 case OP_COND_EXC_IGT_UN:
5383 case OP_COND_EXC_IGE:
5384 case OP_COND_EXC_IGE_UN:
5385 case OP_COND_EXC_ILE:
5386 case OP_COND_EXC_ILE_UN:
5387 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5390 case OP_COND_EXC_IC:
5391 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5393 case OP_COND_EXC_OV:
5394 case OP_COND_EXC_IOV:
5395 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5397 case OP_COND_EXC_NC:
5398 case OP_COND_EXC_INC:
5399 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5401 case OP_COND_EXC_NO:
5402 case OP_COND_EXC_INO:
5403 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5415 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5418 /* floating point opcodes */
5420 if (cfg->compile_aot) {
5421 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5423 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5425 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5428 /* FIXME: we can optimize the imm load by dealing with part of
5429 * the displacement in LDFD (aligning to 512).
5431 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5432 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5436 if (cfg->compile_aot) {
5437 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5439 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5442 ARM_CVTS (code, ins->dreg, ins->dreg);
5444 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5445 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5447 ARM_CVTS (code, ins->dreg, ins->dreg);
5450 case OP_STORER8_MEMBASE_REG:
5451 /* This is generated by the local regalloc pass which runs after the lowering pass */
5452 if (!arm_is_fpimm8 (ins->inst_offset)) {
5453 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5454 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5455 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5457 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5460 case OP_LOADR8_MEMBASE:
5461 /* This is generated by the local regalloc pass which runs after the lowering pass */
5462 if (!arm_is_fpimm8 (ins->inst_offset)) {
5463 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5464 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5465 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5467 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5470 case OP_STORER4_MEMBASE_REG:
5471 g_assert (arm_is_fpimm8 (ins->inst_offset));
5473 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5475 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5476 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5477 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5478 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5481 case OP_LOADR4_MEMBASE:
5483 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5485 g_assert (arm_is_fpimm8 (ins->inst_offset));
5486 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5487 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5488 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5489 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5492 case OP_ICONV_TO_R_UN: {
5493 g_assert_not_reached ();
5496 case OP_ICONV_TO_R4:
5498 ARM_FMSR (code, ins->dreg, ins->sreg1);
5499 ARM_FSITOS (code, ins->dreg, ins->dreg);
5501 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5502 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5503 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5504 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5505 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5508 case OP_ICONV_TO_R8:
5509 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5510 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5511 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5512 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5516 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5517 if (sig_ret->type == MONO_TYPE_R4) {
5519 if (IS_HARD_FLOAT) {
5520 if (ins->sreg1 != ARM_VFP_D0)
5521 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5523 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5526 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5529 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5533 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5535 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5539 case OP_FCONV_TO_I1:
5540 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5542 case OP_FCONV_TO_U1:
5543 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5545 case OP_FCONV_TO_I2:
5546 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5548 case OP_FCONV_TO_U2:
5549 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5551 case OP_FCONV_TO_I4:
5553 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5555 case OP_FCONV_TO_U4:
5557 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5559 case OP_FCONV_TO_I8:
5560 case OP_FCONV_TO_U8:
5561 g_assert_not_reached ();
5562 /* Implemented as helper calls */
5564 case OP_LCONV_TO_R_UN:
5565 g_assert_not_reached ();
5566 /* Implemented as helper calls */
5568 case OP_LCONV_TO_OVF_I4_2: {
5569 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5571 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5574 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5575 high_bit_not_set = code;
5576 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5578 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5579 valid_negative = code;
5580 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5581 invalid_negative = code;
5582 ARM_B_COND (code, ARMCOND_AL, 0);
5584 arm_patch (high_bit_not_set, code);
5586 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5587 valid_positive = code;
5588 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5590 arm_patch (invalid_negative, code);
5591 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5593 arm_patch (valid_negative, code);
5594 arm_patch (valid_positive, code);
5596 if (ins->dreg != ins->sreg1)
5597 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5601 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5604 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5607 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5610 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5613 ARM_NEGD (code, ins->dreg, ins->sreg1);
5617 g_assert_not_reached ();
5621 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5627 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5632 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5635 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5636 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5640 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5643 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5644 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5648 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5651 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5652 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5653 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5657 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5660 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5661 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5665 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5668 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5669 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5670 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5674 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5677 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5678 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5682 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5685 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5686 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5690 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5693 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5694 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5697 /* ARM FPA flags table:
5698 * N Less than ARMCOND_MI
5699 * Z Equal ARMCOND_EQ
5700 * C Greater Than or Equal ARMCOND_CS
5701 * V Unordered ARMCOND_VS
5704 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5707 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5710 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5713 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5714 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5720 g_assert_not_reached ();
5724 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5726 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5727 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5728 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5732 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5733 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5738 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5739 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5741 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5742 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5744 *(guint32*)code = 0xffffffff;
5746 *(guint32*)code = 0x7fefffff;
5748 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5750 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5751 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5753 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5754 ARM_CPYD (code, ins->dreg, ins->sreg1);
5756 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5757 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5762 case OP_RCONV_TO_I1:
5763 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5765 case OP_RCONV_TO_U1:
5766 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5768 case OP_RCONV_TO_I2:
5769 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5771 case OP_RCONV_TO_U2:
5772 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5774 case OP_RCONV_TO_I4:
5775 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5777 case OP_RCONV_TO_U4:
5778 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5780 case OP_RCONV_TO_R4:
5782 if (ins->dreg != ins->sreg1)
5783 ARM_CPYS (code, ins->dreg, ins->sreg1);
5785 case OP_RCONV_TO_R8:
5787 ARM_CVTS (code, ins->dreg, ins->sreg1);
5790 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5793 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5796 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5799 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5802 ARM_NEGS (code, ins->dreg, ins->sreg1);
5806 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5809 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5810 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5814 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5817 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5818 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5822 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5825 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5826 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5827 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5831 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5834 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5835 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5839 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5842 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5843 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5844 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5848 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5851 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5852 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5856 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5859 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5860 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5864 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5867 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5868 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5871 case OP_GC_LIVENESS_DEF:
5872 case OP_GC_LIVENESS_USE:
5873 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5874 ins->backend.pc_offset = code - cfg->native_code;
5876 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5877 ins->backend.pc_offset = code - cfg->native_code;
5878 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5880 case OP_GC_SAFE_POINT: {
5883 g_assert (mono_threads_is_coop_enabled ());
5885 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5886 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5888 ARM_B_COND (code, ARMCOND_EQ, 0);
5889 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5890 code = emit_call_seq (cfg, code);
5891 arm_patch (buf [0], code);
5896 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5897 g_assert_not_reached ();
5900 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5901 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5902 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5903 g_assert_not_reached ();
5909 last_offset = offset;
5912 cfg->code_len = code - cfg->native_code;
5915 #endif /* DISABLE_JIT */
5918 mono_arch_register_lowlevel_calls (void)
5920 /* The signature doesn't matter */
5921 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5922 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5923 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5926 #define patch_lis_ori(ip,val) do {\
5927 guint16 *__lis_ori = (guint16*)(ip); \
5928 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5929 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5933 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5935 unsigned char *ip = ji->ip.i + code;
5937 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5941 case MONO_PATCH_INFO_SWITCH: {
5942 gpointer *jt = (gpointer*)(ip + 8);
5944 /* jt is the inlined jump table, 2 instructions after ip
5945 * In the normal case we store the absolute addresses,
5946 * otherwise the displacements.
5948 for (i = 0; i < ji->data.table->table_size; i++)
5949 jt [i] = code + (int)ji->data.table->table [i];
5952 case MONO_PATCH_INFO_IP:
5953 g_assert_not_reached ();
5954 patch_lis_ori (ip, ip);
5956 case MONO_PATCH_INFO_METHOD_REL:
5957 g_assert_not_reached ();
5958 *((gpointer *)(ip)) = target;
5960 case MONO_PATCH_INFO_METHODCONST:
5961 case MONO_PATCH_INFO_CLASS:
5962 case MONO_PATCH_INFO_IMAGE:
5963 case MONO_PATCH_INFO_FIELD:
5964 case MONO_PATCH_INFO_VTABLE:
5965 case MONO_PATCH_INFO_IID:
5966 case MONO_PATCH_INFO_SFLDA:
5967 case MONO_PATCH_INFO_LDSTR:
5968 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5969 case MONO_PATCH_INFO_LDTOKEN:
5970 g_assert_not_reached ();
5971 /* from OP_AOTCONST : lis + ori */
5972 patch_lis_ori (ip, target);
5974 case MONO_PATCH_INFO_R4:
5975 case MONO_PATCH_INFO_R8:
5976 g_assert_not_reached ();
5977 *((gconstpointer *)(ip + 2)) = target;
5979 case MONO_PATCH_INFO_EXC_NAME:
5980 g_assert_not_reached ();
5981 *((gconstpointer *)(ip + 1)) = target;
5983 case MONO_PATCH_INFO_NONE:
5984 case MONO_PATCH_INFO_BB_OVF:
5985 case MONO_PATCH_INFO_EXC_OVF:
5986 /* everything is dealt with at epilog output time */
5989 arm_patch_general (cfg, domain, ip, target);
5995 mono_arm_unaligned_stack (MonoMethod *method)
5997 g_assert_not_reached ();
6003 * Stack frame layout:
6005 * ------------------- fp
6006 * MonoLMF structure or saved registers
6007 * -------------------
6009 * -------------------
6011 * -------------------
6012 * optional 8 bytes for tracing
6013 * -------------------
6014 * param area size is cfg->param_area
6015 * ------------------- sp
6018 mono_arch_emit_prolog (MonoCompile *cfg)
6020 MonoMethod *method = cfg->method;
6022 MonoMethodSignature *sig;
6024 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6029 int prev_sp_offset, reg_offset;
6031 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6034 sig = mono_method_signature (method);
6035 cfg->code_size = 256 + sig->param_count * 64;
6036 code = cfg->native_code = g_malloc (cfg->code_size);
6038 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6040 alloc_size = cfg->stack_offset;
6046 * The iphone uses R7 as the frame pointer, and it points at the saved
6051 * We can't use r7 as a frame pointer since it points into the middle of
6052 * the frame, so we keep using our own frame pointer.
6053 * FIXME: Optimize this.
6055 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6056 prev_sp_offset += 8; /* r7 and lr */
6057 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6058 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6059 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6062 if (!method->save_lmf) {
6064 /* No need to push LR again */
6065 if (cfg->used_int_regs)
6066 ARM_PUSH (code, cfg->used_int_regs);
6068 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6069 prev_sp_offset += 4;
6071 for (i = 0; i < 16; ++i) {
6072 if (cfg->used_int_regs & (1 << i))
6073 prev_sp_offset += 4;
6075 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6077 for (i = 0; i < 16; ++i) {
6078 if ((cfg->used_int_regs & (1 << i))) {
6079 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6080 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6084 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6085 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6087 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6088 ARM_PUSH (code, 0x5ff0);
6089 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6090 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6092 for (i = 0; i < 16; ++i) {
6093 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6094 /* The original r7 is saved at the start */
6095 if (!(iphone_abi && i == ARMREG_R7))
6096 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6100 g_assert (reg_offset == 4 * 10);
6101 pos += sizeof (MonoLMF) - (4 * 10);
6105 orig_alloc_size = alloc_size;
6106 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6107 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6108 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6109 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6112 /* the stack used in the pushed regs */
6113 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6114 cfg->stack_usage = alloc_size;
6116 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6117 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6119 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6120 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6122 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6124 if (cfg->frame_reg != ARMREG_SP) {
6125 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6126 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6128 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6129 prev_sp_offset += alloc_size;
6131 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6132 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6134 /* compute max_offset in order to use short forward jumps
6135 * we could skip do it on arm because the immediate displacement
6136 * for jumps is large enough, it may be useful later for constant pools
6139 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6140 MonoInst *ins = bb->code;
6141 bb->max_offset = max_offset;
6143 MONO_BB_FOR_EACH_INS (bb, ins)
6144 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6147 /* stack alignment check */
6151 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6152 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6153 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6154 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6156 ARM_B_COND (code, ARMCOND_EQ, 0);
6157 if (cfg->compile_aot)
6158 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6160 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6161 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6162 code = emit_call_seq (cfg, code);
6163 arm_patch (buf [0], code);
6167 /* store runtime generic context */
6168 if (cfg->rgctx_var) {
6169 MonoInst *ins = cfg->rgctx_var;
6171 g_assert (ins->opcode == OP_REGOFFSET);
6173 if (arm_is_imm12 (ins->inst_offset)) {
6174 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6176 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6177 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6181 /* load arguments allocated to register from the stack */
6184 cinfo = get_call_info (NULL, sig);
6186 if (cinfo->ret.storage == RegTypeStructByAddr) {
6187 ArgInfo *ainfo = &cinfo->ret;
6188 inst = cfg->vret_addr;
6189 g_assert (arm_is_imm12 (inst->inst_offset));
6190 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6193 if (sig->call_convention == MONO_CALL_VARARG) {
6194 ArgInfo *cookie = &cinfo->sig_cookie;
6196 /* Save the sig cookie address */
6197 g_assert (cookie->storage == RegTypeBase);
6199 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6200 g_assert (arm_is_imm12 (cfg->sig_cookie));
6201 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6202 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6205 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6206 ArgInfo *ainfo = cinfo->args + i;
6207 inst = cfg->args [pos];
6209 if (cfg->verbose_level > 2)
6210 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6212 if (inst->opcode == OP_REGVAR) {
6213 if (ainfo->storage == RegTypeGeneral)
6214 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6215 else if (ainfo->storage == RegTypeFP) {
6216 g_assert_not_reached ();
6217 } else if (ainfo->storage == RegTypeBase) {
6218 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6219 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6221 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6222 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6225 g_assert_not_reached ();
6227 if (cfg->verbose_level > 2)
6228 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6230 switch (ainfo->storage) {
6232 for (part = 0; part < ainfo->nregs; part ++) {
6233 if (ainfo->esize == 4)
6234 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6236 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6239 case RegTypeGeneral:
6240 case RegTypeIRegPair:
6241 case RegTypeGSharedVtInReg:
6242 case RegTypeStructByAddr:
6243 switch (ainfo->size) {
6245 if (arm_is_imm12 (inst->inst_offset))
6246 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6248 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6249 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6253 if (arm_is_imm8 (inst->inst_offset)) {
6254 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6256 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6257 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6261 if (arm_is_imm12 (inst->inst_offset)) {
6262 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6264 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6265 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6267 if (arm_is_imm12 (inst->inst_offset + 4)) {
6268 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6270 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6271 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6275 if (arm_is_imm12 (inst->inst_offset)) {
6276 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6278 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6279 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6284 case RegTypeBaseGen:
6285 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6286 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6288 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6289 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6291 if (arm_is_imm12 (inst->inst_offset + 4)) {
6292 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6293 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6295 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6296 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6297 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6298 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6302 case RegTypeGSharedVtOnStack:
6303 case RegTypeStructByAddrOnStack:
6304 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6305 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6307 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6308 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6311 switch (ainfo->size) {
6313 if (arm_is_imm8 (inst->inst_offset)) {
6314 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6316 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6317 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6321 if (arm_is_imm8 (inst->inst_offset)) {
6322 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6324 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6325 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6329 if (arm_is_imm12 (inst->inst_offset)) {
6330 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6332 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6333 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6335 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6336 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6338 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6339 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6341 if (arm_is_imm12 (inst->inst_offset + 4)) {
6342 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6344 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6345 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6349 if (arm_is_imm12 (inst->inst_offset)) {
6350 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6352 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6353 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6359 int imm8, rot_amount;
6361 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6362 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6363 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6365 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6367 if (ainfo->size == 8)
6368 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6370 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6373 case RegTypeStructByVal: {
6374 int doffset = inst->inst_offset;
6378 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6379 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6380 if (arm_is_imm12 (doffset)) {
6381 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6383 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6384 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6386 soffset += sizeof (gpointer);
6387 doffset += sizeof (gpointer);
6389 if (ainfo->vtsize) {
6390 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6391 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6392 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6397 g_assert_not_reached ();
6404 if (method->save_lmf)
6405 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6408 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6410 if (cfg->arch.seq_point_info_var) {
6411 MonoInst *ins = cfg->arch.seq_point_info_var;
6413 /* Initialize the variable from a GOT slot */
6414 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6415 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6417 *(gpointer*)code = NULL;
6419 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6421 g_assert (ins->opcode == OP_REGOFFSET);
6423 if (arm_is_imm12 (ins->inst_offset)) {
6424 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6426 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6427 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6431 /* Initialize ss_trigger_page_var */
6432 if (!cfg->soft_breakpoints) {
6433 MonoInst *info_var = cfg->arch.seq_point_info_var;
6434 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6435 int dreg = ARMREG_LR;
6438 g_assert (info_var->opcode == OP_REGOFFSET);
6440 code = emit_ldr_imm (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6441 /* Load the trigger page addr */
6442 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6443 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6447 if (cfg->arch.seq_point_ss_method_var) {
6448 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6449 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6451 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6452 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6454 if (cfg->compile_aot) {
6455 MonoInst *info_var = cfg->arch.seq_point_info_var;
6456 int dreg = ARMREG_LR;
6458 g_assert (info_var->opcode == OP_REGOFFSET);
6459 g_assert (arm_is_imm12 (info_var->inst_offset));
6461 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6462 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
6463 ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6465 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6466 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6468 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6470 *(gpointer*)code = &single_step_tramp;
6472 *(gpointer*)code = breakpoint_tramp;
6475 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6476 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6477 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6478 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6482 cfg->code_len = code - cfg->native_code;
6483 g_assert (cfg->code_len < cfg->code_size);
6490 mono_arch_emit_epilog (MonoCompile *cfg)
6492 MonoMethod *method = cfg->method;
6493 int pos, i, rot_amount;
6494 int max_epilog_size = 16 + 20*4;
6498 if (cfg->method->save_lmf)
6499 max_epilog_size += 128;
6501 if (mono_jit_trace_calls != NULL)
6502 max_epilog_size += 50;
6504 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6505 cfg->code_size *= 2;
6506 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6507 cfg->stat_code_reallocs++;
6511 * Keep in sync with OP_JMP
6513 code = cfg->native_code + cfg->code_len;
6515 /* Save the uwind state which is needed by the out-of-line code */
6516 mono_emit_unwind_op_remember_state (cfg, code);
6518 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6519 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6523 /* Load returned vtypes into registers if needed */
6524 cinfo = cfg->arch.cinfo;
6525 switch (cinfo->ret.storage) {
6526 case RegTypeStructByVal: {
6527 MonoInst *ins = cfg->ret;
6529 if (cinfo->ret.nregs == 1) {
6530 if (arm_is_imm12 (ins->inst_offset)) {
6531 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6533 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6534 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6537 for (i = 0; i < cinfo->ret.nregs; ++i) {
6538 int offset = ins->inst_offset + (i * 4);
6539 if (arm_is_imm12 (offset)) {
6540 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6542 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6543 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6550 MonoInst *ins = cfg->ret;
6552 for (i = 0; i < cinfo->ret.nregs; ++i) {
6553 if (cinfo->ret.esize == 4)
6554 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6556 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6564 if (method->save_lmf) {
6565 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6566 /* all but r0-r3, sp and pc */
6567 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6570 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6572 /* This points to r4 inside MonoLMF->iregs */
6573 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6575 regmask = 0x9ff0; /* restore lr to pc */
6576 /* Skip caller saved registers not used by the method */
6577 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6578 regmask &= ~(1 << reg);
6583 /* Restored later */
6584 regmask &= ~(1 << ARMREG_PC);
6585 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6586 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6587 for (i = 0; i < 16; i++) {
6588 if (regmask & (1 << i))
6591 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6593 ARM_POP (code, regmask);
6595 for (i = 0; i < 16; i++) {
6596 if (regmask & (1 << i))
6597 mono_emit_unwind_op_same_value (cfg, code, i);
6599 /* Restore saved r7, restore LR to PC */
6600 /* Skip lr from the lmf */
6601 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6602 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6603 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6604 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6607 int i, nused_int_regs = 0;
6609 for (i = 0; i < 16; i++) {
6610 if (cfg->used_int_regs & (1 << i))
6614 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6615 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6617 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6618 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6621 if (cfg->frame_reg != ARMREG_SP) {
6622 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6626 /* Restore saved gregs */
6627 if (cfg->used_int_regs) {
6628 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6629 ARM_POP (code, cfg->used_int_regs);
6630 for (i = 0; i < 16; i++) {
6631 if (cfg->used_int_regs & (1 << i))
6632 mono_emit_unwind_op_same_value (cfg, code, i);
6635 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6636 /* Restore saved r7, restore LR to PC */
6637 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6639 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6640 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6644 /* Restore the unwind state to be the same as before the epilog */
6645 mono_emit_unwind_op_restore_state (cfg, code);
6647 cfg->code_len = code - cfg->native_code;
6649 g_assert (cfg->code_len < cfg->code_size);
6654 mono_arch_emit_exceptions (MonoCompile *cfg)
6656 MonoJumpInfo *patch_info;
6659 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6660 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6661 int max_epilog_size = 50;
6663 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6664 exc_throw_pos [i] = NULL;
6665 exc_throw_found [i] = 0;
6668 /* count the number of exception infos */
6671 * make sure we have enough space for exceptions
6673 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6674 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6675 i = mini_exception_id_by_name (patch_info->data.target);
6676 if (!exc_throw_found [i]) {
6677 max_epilog_size += 32;
6678 exc_throw_found [i] = TRUE;
6683 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6684 cfg->code_size *= 2;
6685 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6686 cfg->stat_code_reallocs++;
6689 code = cfg->native_code + cfg->code_len;
6691 /* add code to raise exceptions */
6692 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6693 switch (patch_info->type) {
6694 case MONO_PATCH_INFO_EXC: {
6695 MonoClass *exc_class;
6696 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6698 i = mini_exception_id_by_name (patch_info->data.target);
6699 if (exc_throw_pos [i]) {
6700 arm_patch (ip, exc_throw_pos [i]);
6701 patch_info->type = MONO_PATCH_INFO_NONE;
6704 exc_throw_pos [i] = code;
6706 arm_patch (ip, code);
6708 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6710 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6711 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6712 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6713 patch_info->data.name = "mono_arch_throw_corlib_exception";
6714 patch_info->ip.i = code - cfg->native_code;
6716 cfg->thunk_area += THUNK_SIZE;
6717 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6727 cfg->code_len = code - cfg->native_code;
6729 g_assert (cfg->code_len < cfg->code_size);
6733 #endif /* #ifndef DISABLE_JIT */
6736 mono_arch_finish_init (void)
6741 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6746 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6753 mono_arch_print_tree (MonoInst *tree, int arity)
6763 mono_arch_get_patch_offset (guint8 *code)
6770 mono_arch_flush_register_windows (void)
6775 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6777 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6781 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6783 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6787 mono_arch_get_cie_program (void)
6791 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6796 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6797 #define BASE_SIZE (6 * 4)
6798 #define BSEARCH_ENTRY_SIZE (4 * 4)
6799 #define CMP_SIZE (3 * 4)
6800 #define BRANCH_SIZE (1 * 4)
6801 #define CALL_SIZE (2 * 4)
6802 #define WMC_SIZE (8 * 4)
6803 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6806 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6808 guint32 delta = DISTANCE (target, code);
6810 g_assert (delta >= 0 && delta <= 0xFFF);
6811 *target = *target | delta;
6816 #ifdef ENABLE_WRONG_METHOD_CHECK
6818 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6820 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6826 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6827 gpointer fail_tramp)
6830 arminstr_t *code, *start;
6831 gboolean large_offsets = FALSE;
6832 guint32 **constant_pool_starts;
6833 arminstr_t *vtable_target = NULL;
6834 int extra_space = 0;
6835 #ifdef ENABLE_WRONG_METHOD_CHECK
6841 constant_pool_starts = g_new0 (guint32*, count);
6843 for (i = 0; i < count; ++i) {
6844 MonoIMTCheckItem *item = imt_entries [i];
6845 if (item->is_equals) {
6846 gboolean fail_case = !item->check_target_idx && fail_tramp;
6848 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6849 item->chunk_size += 32;
6850 large_offsets = TRUE;
6853 if (item->check_target_idx || fail_case) {
6854 if (!item->compare_done || fail_case)
6855 item->chunk_size += CMP_SIZE;
6856 item->chunk_size += BRANCH_SIZE;
6858 #ifdef ENABLE_WRONG_METHOD_CHECK
6859 item->chunk_size += WMC_SIZE;
6863 item->chunk_size += 16;
6864 large_offsets = TRUE;
6866 item->chunk_size += CALL_SIZE;
6868 item->chunk_size += BSEARCH_ENTRY_SIZE;
6869 imt_entries [item->check_target_idx]->compare_done = TRUE;
6871 size += item->chunk_size;
6875 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6878 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
6880 code = mono_domain_code_reserve (domain, size);
6883 unwind_ops = mono_arch_get_cie_program ();
6886 g_print ("Building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6887 for (i = 0; i < count; ++i) {
6888 MonoIMTCheckItem *item = imt_entries [i];
6889 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6893 if (large_offsets) {
6894 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6895 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6897 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6898 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6900 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6901 vtable_target = code;
6902 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6903 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6905 for (i = 0; i < count; ++i) {
6906 MonoIMTCheckItem *item = imt_entries [i];
6907 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6908 gint32 vtable_offset;
6910 item->code_target = (guint8*)code;
6912 if (item->is_equals) {
6913 gboolean fail_case = !item->check_target_idx && fail_tramp;
6915 if (item->check_target_idx || fail_case) {
6916 if (!item->compare_done || fail_case) {
6918 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6919 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6921 item->jmp_code = (guint8*)code;
6922 ARM_B_COND (code, ARMCOND_NE, 0);
6924 /*Enable the commented code to assert on wrong method*/
6925 #ifdef ENABLE_WRONG_METHOD_CHECK
6927 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6928 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6930 ARM_B_COND (code, ARMCOND_EQ, 0);
6932 /* Define this if your system is so bad that gdb is failing. */
6933 #ifdef BROKEN_DEV_ENV
6934 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6936 arm_patch (code - 1, mini_dump_bad_imt);
6940 arm_patch (cond, code);
6944 if (item->has_target_code) {
6945 /* Load target address */
6946 target_code_ins = code;
6947 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6948 /* Save it to the fourth slot */
6949 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6950 /* Restore registers and branch */
6951 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6953 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
6955 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
6956 if (!arm_is_imm12 (vtable_offset)) {
6958 * We need to branch to a computed address but we don't have
6959 * a free register to store it, since IP must contain the
6960 * vtable address. So we push the two values to the stack, and
6961 * load them both using LDM.
6963 /* Compute target address */
6964 vtable_offset_ins = code;
6965 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6966 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
6967 /* Save it to the fourth slot */
6968 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6969 /* Restore registers and branch */
6970 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6972 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
6974 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
6975 if (large_offsets) {
6976 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6977 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
6979 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
6980 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
6985 arm_patch (item->jmp_code, (guchar*)code);
6987 target_code_ins = code;
6988 /* Load target address */
6989 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6990 /* Save it to the fourth slot */
6991 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6992 /* Restore registers and branch */
6993 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6995 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
6996 item->jmp_code = NULL;
7000 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7002 /*must emit after unconditional branch*/
7003 if (vtable_target) {
7004 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7005 item->chunk_size += 4;
7006 vtable_target = NULL;
7009 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7010 constant_pool_starts [i] = code;
7012 code += extra_space;
7016 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7017 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7019 item->jmp_code = (guint8*)code;
7020 ARM_B_COND (code, ARMCOND_HS, 0);
7025 for (i = 0; i < count; ++i) {
7026 MonoIMTCheckItem *item = imt_entries [i];
7027 if (item->jmp_code) {
7028 if (item->check_target_idx)
7029 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7031 if (i > 0 && item->is_equals) {
7033 arminstr_t *space_start = constant_pool_starts [i];
7034 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7035 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7042 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7043 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7048 g_free (constant_pool_starts);
7050 mono_arch_flush_icache ((guint8*)start, size);
7051 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
7052 mono_stats.imt_trampolines_size += code - start;
7054 g_assert (DISTANCE (start, code) <= size);
7056 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7062 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7064 return ctx->regs [reg];
7068 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7070 ctx->regs [reg] = val;
7074 * mono_arch_get_trampolines:
7076 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7080 mono_arch_get_trampolines (gboolean aot)
7082 return mono_arm_get_exception_trampolines (aot);
7086 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7093 bp = MONO_CONTEXT_GET_BP (ctx);
7094 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7096 old_value = *lr_loc;
7097 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7100 *lr_loc = new_value;
7105 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7107 * mono_arch_set_breakpoint:
7109 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7110 * The location should contain code emitted by OP_SEQ_POINT.
7113 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7116 guint32 native_offset = ip - (guint8*)ji->code_start;
7117 MonoDebugOptions *opt = mini_get_debug_options ();
7120 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7122 if (!breakpoint_tramp)
7123 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7125 g_assert (native_offset % 4 == 0);
7126 g_assert (info->bp_addrs [native_offset / 4] == 0);
7127 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7128 } else if (opt->soft_breakpoints) {
7130 ARM_BLX_REG (code, ARMREG_LR);
7131 mono_arch_flush_icache (code - 4, 4);
7133 int dreg = ARMREG_LR;
7135 /* Read from another trigger page */
7136 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7138 *(int*)code = (int)bp_trigger_page;
7140 ARM_LDR_IMM (code, dreg, dreg, 0);
7142 mono_arch_flush_icache (code - 16, 16);
7145 /* This is currently implemented by emitting an SWI instruction, which
7146 * qemu/linux seems to convert to a SIGILL.
7148 *(int*)code = (0xef << 24) | 8;
7150 mono_arch_flush_icache (code - 4, 4);
7156 * mono_arch_clear_breakpoint:
7158 * Clear the breakpoint at IP.
7161 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7163 MonoDebugOptions *opt = mini_get_debug_options ();
7168 guint32 native_offset = ip - (guint8*)ji->code_start;
7169 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7171 if (!breakpoint_tramp)
7172 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7174 g_assert (native_offset % 4 == 0);
7175 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7176 info->bp_addrs [native_offset / 4] = 0;
7177 } else if (opt->soft_breakpoints) {
7180 mono_arch_flush_icache (code - 4, 4);
7182 for (i = 0; i < 4; ++i)
7185 mono_arch_flush_icache (ip, code - ip);
7190 * mono_arch_start_single_stepping:
7192 * Start single stepping.
7195 mono_arch_start_single_stepping (void)
7197 if (ss_trigger_page)
7198 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7200 single_step_tramp = mini_get_single_step_trampoline ();
7204 * mono_arch_stop_single_stepping:
7206 * Stop single stepping.
7209 mono_arch_stop_single_stepping (void)
7211 if (ss_trigger_page)
7212 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7214 single_step_tramp = NULL;
7218 #define DBG_SIGNAL SIGBUS
7220 #define DBG_SIGNAL SIGSEGV
7224 * mono_arch_is_single_step_event:
7226 * Return whenever the machine state in SIGCTX corresponds to a single
7230 mono_arch_is_single_step_event (void *info, void *sigctx)
7232 siginfo_t *sinfo = info;
7234 if (!ss_trigger_page)
7237 /* Sometimes the address is off by 4 */
7238 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7245 * mono_arch_is_breakpoint_event:
7247 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7250 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7252 siginfo_t *sinfo = info;
7254 if (!ss_trigger_page)
7257 if (sinfo->si_signo == DBG_SIGNAL) {
7258 /* Sometimes the address is off by 4 */
7259 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7269 * mono_arch_skip_breakpoint:
7271 * See mini-amd64.c for docs.
7274 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7276 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7280 * mono_arch_skip_single_step:
7282 * See mini-amd64.c for docs.
7285 mono_arch_skip_single_step (MonoContext *ctx)
7287 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7290 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7293 * mono_arch_get_seq_point_info:
7295 * See mini-amd64.c for docs.
7298 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7303 // FIXME: Add a free function
7305 mono_domain_lock (domain);
7306 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7308 mono_domain_unlock (domain);
7311 ji = mono_jit_info_table_find (domain, (char*)code);
7314 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7316 info->ss_trigger_page = ss_trigger_page;
7317 info->bp_trigger_page = bp_trigger_page;
7318 info->ss_tramp_addr = &single_step_tramp;
7320 mono_domain_lock (domain);
7321 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7323 mono_domain_unlock (domain);
7330 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7332 ext->lmf.previous_lmf = prev_lmf;
7333 /* Mark that this is a MonoLMFExt */
7334 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7335 ext->lmf.sp = (gssize)ext;
7339 * mono_arch_set_target:
7341 * Set the target architecture the JIT backend should generate code for, in the form
7342 * of a GNU target triplet. Only used in AOT mode.
7345 mono_arch_set_target (char *mtriple)
7347 /* The GNU target triple format is not very well documented */
7348 if (strstr (mtriple, "armv7")) {
7349 v5_supported = TRUE;
7350 v6_supported = TRUE;
7351 v7_supported = TRUE;
7353 if (strstr (mtriple, "armv6")) {
7354 v5_supported = TRUE;
7355 v6_supported = TRUE;
7357 if (strstr (mtriple, "armv7s")) {
7358 v7s_supported = TRUE;
7360 if (strstr (mtriple, "armv7k")) {
7361 v7k_supported = TRUE;
7363 if (strstr (mtriple, "thumbv7s")) {
7364 v5_supported = TRUE;
7365 v6_supported = TRUE;
7366 v7_supported = TRUE;
7367 v7s_supported = TRUE;
7368 thumb_supported = TRUE;
7369 thumb2_supported = TRUE;
7371 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7372 v5_supported = TRUE;
7373 v6_supported = TRUE;
7374 thumb_supported = TRUE;
7377 if (strstr (mtriple, "gnueabi"))
7378 eabi_supported = TRUE;
7382 mono_arch_opcode_supported (int opcode)
7385 case OP_ATOMIC_ADD_I4:
7386 case OP_ATOMIC_EXCHANGE_I4:
7387 case OP_ATOMIC_CAS_I4:
7388 case OP_ATOMIC_LOAD_I1:
7389 case OP_ATOMIC_LOAD_I2:
7390 case OP_ATOMIC_LOAD_I4:
7391 case OP_ATOMIC_LOAD_U1:
7392 case OP_ATOMIC_LOAD_U2:
7393 case OP_ATOMIC_LOAD_U4:
7394 case OP_ATOMIC_STORE_I1:
7395 case OP_ATOMIC_STORE_I2:
7396 case OP_ATOMIC_STORE_I4:
7397 case OP_ATOMIC_STORE_U1:
7398 case OP_ATOMIC_STORE_U2:
7399 case OP_ATOMIC_STORE_U4:
7400 return v7_supported;
7401 case OP_ATOMIC_LOAD_R4:
7402 case OP_ATOMIC_LOAD_R8:
7403 case OP_ATOMIC_STORE_R4:
7404 case OP_ATOMIC_STORE_R8:
7405 return v7_supported && IS_VFP;
7412 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7414 return get_call_info (mp, sig);
7418 mono_arch_get_get_tls_tramp (void)
7424 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data)
7427 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
7428 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7430 *(gpointer*)code = NULL;
7432 /* Load the value from the GOT */
7433 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);
7438 mono_arm_emit_aotconst (gpointer ji_list, guint8 *code, guint8 *buf, int dreg, int patch_type, gconstpointer data)
7440 MonoJumpInfo **ji = (MonoJumpInfo**)ji_list;
7442 *ji = mono_patch_info_list_prepend (*ji, code - buf, patch_type, data);
7443 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7445 *(gpointer*)code = NULL;
7447 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);