2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/appdomain.h>
16 #include <mono/metadata/debug-helpers.h>
17 #include <mono/utils/mono-mmap.h>
23 #include "debugger-agent.h"
25 #include "mono/arch/arm/arm-fpa-codegen.h"
26 #include "mono/arch/arm/arm-vfp-codegen.h"
28 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
29 #define HAVE_AEABI_READ_TP 1
32 #ifdef ARM_FPU_VFP_HARD
48 #ifdef MONO_ARCH_SOFT_FLOAT
49 #define IS_SOFT_FLOAT 1
51 #define IS_SOFT_FLOAT 0
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
56 static gint lmf_tls_offset = -1;
57 static gint lmf_addr_tls_offset = -1;
59 /* This mutex protects architecture specific caches */
60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
62 static CRITICAL_SECTION mini_arch_mutex;
64 static int v5_supported = 0;
65 static int v6_supported = 0;
66 static int v7_supported = 0;
67 static int thumb_supported = 0;
69 * Whenever to use the ARM EABI
71 static int eabi_supported = 0;
74 * Whenever we are on arm/darwin aka the iphone.
76 static int darwin = 0;
78 * Whenever to use the iphone ABI extensions:
79 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
80 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
81 * This is required for debugging/profiling tools to work, but it has some overhead so it should
82 * only be turned on in debug builds.
84 static int iphone_abi = 0;
87 * The FPU we are generating code for. This is NOT runtime configurable right now,
88 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
90 static MonoArmFPU arm_fpu;
94 static volatile int ss_trigger_var = 0;
96 static gpointer single_step_func_wrapper;
97 static gpointer breakpoint_func_wrapper;
100 * The code generated for sequence points reads from this location, which is
101 * made read-only when single stepping is enabled.
103 static gpointer ss_trigger_page;
105 /* Enabled breakpoints read from this trigger page */
106 static gpointer bp_trigger_page;
108 /* Structure used by the sequence points in AOTed code */
110 gpointer ss_trigger_page;
111 gpointer bp_trigger_page;
112 guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
117 * floating point support: on ARM it is a mess, there are at least 3
118 * different setups, each of which binary incompat with the other.
119 * 1) FPA: old and ugly, but unfortunately what current distros use
120 * the double binary format has the two words swapped. 8 double registers.
121 * Implemented usually by kernel emulation.
122 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
123 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
124 * 3) VFP: the new and actually sensible and useful FP support. Implemented
125 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
127 * The plan is to write the FPA support first. softfloat can be tested in a chroot.
129 int mono_exc_esp_offset = 0;
131 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
132 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
133 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
135 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
136 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
137 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
139 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
140 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) | (ARMREG_LR << 12) | ARMREG_PC)
143 /* A variant of ARM_LDR_IMM which can handle large offsets */
144 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
145 if (arm_is_imm12 ((offset))) { \
146 ARM_LDR_IMM (code, (dreg), (basereg), (offset)); \
148 g_assert ((scratch_reg) != (basereg)); \
149 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
150 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
154 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
155 if (arm_is_imm12 ((offset))) { \
156 ARM_STR_IMM (code, (dreg), (basereg), (offset)); \
158 g_assert ((scratch_reg) != (basereg)); \
159 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
160 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
164 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
167 mono_arch_regname (int reg)
169 static const char * rnames[] = {
170 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
171 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
172 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
175 if (reg >= 0 && reg < 16)
181 mono_arch_fregname (int reg)
183 static const char * rnames[] = {
184 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
185 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
186 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
187 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
188 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
189 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
192 if (reg >= 0 && reg < 32)
200 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
202 int imm8, rot_amount;
203 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
204 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
207 g_assert (dreg != sreg);
208 code = mono_arm_emit_load_imm (code, dreg, imm);
209 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
214 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
216 /* we can use r0-r3, since this is called only for incoming args on the stack */
217 if (size > sizeof (gpointer) * 4) {
219 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
220 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
221 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
222 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
223 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
224 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
225 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
226 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
227 ARM_B_COND (code, ARMCOND_NE, 0);
228 arm_patch (code - 4, start_loop);
231 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
232 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
234 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
235 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
241 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
242 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
243 doffset = soffset = 0;
245 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
246 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
252 g_assert (size == 0);
257 emit_call_reg (guint8 *code, int reg)
260 ARM_BLX_REG (code, reg);
262 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
266 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
272 emit_call_seq (MonoCompile *cfg, guint8 *code)
274 if (cfg->method->dynamic) {
275 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
277 *(gpointer*)code = NULL;
279 code = emit_call_reg (code, ARMREG_IP);
287 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
289 switch (ins->opcode) {
292 case OP_FCALL_MEMBASE:
294 if (ins->dreg != ARM_FPA_F0)
295 ARM_FPA_MVFD (code, ins->dreg, ARM_FPA_F0);
297 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
298 ARM_FMSR (code, ins->dreg, ARMREG_R0);
299 ARM_CVTS (code, ins->dreg, ins->dreg);
301 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
313 * Emit code to push an LMF structure on the LMF stack.
314 * On arm, this is intermixed with the initialization of other fields of the structure.
317 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
319 gboolean get_lmf_fast = FALSE;
322 #ifdef HAVE_AEABI_READ_TP
323 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
325 if (lmf_addr_tls_offset != -1) {
328 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
329 (gpointer)"__aeabi_read_tp");
330 code = emit_call_seq (cfg, code);
332 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
337 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
338 (gpointer)"mono_get_lmf_addr");
339 code = emit_call_seq (cfg, code);
341 /* we build the MonoLMF structure on the stack - see mini-arm.h */
342 /* lmf_offset is the offset from the previous stack pointer,
343 * alloc_size is the total stack space allocated, so the offset
344 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
345 * The pointer to the struct is put in r1 (new_lmf).
346 * ip is used as scratch
347 * The callee-saved registers are already in the MonoLMF structure
349 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
350 /* r0 is the result from mono_get_lmf_addr () */
351 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
352 /* new_lmf->previous_lmf = *lmf_addr */
353 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
354 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
355 /* *(lmf_addr) = r1 */
356 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
357 /* Skip method (only needed for trampoline LMF frames) */
358 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, sp));
359 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, fp));
360 /* save the current IP */
361 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
362 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ip));
364 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
365 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
373 * Emit code to pop an LMF structure from the LMF stack.
376 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
380 if (lmf_offset < 32) {
381 basereg = cfg->frame_reg;
386 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
389 /* ip = previous_lmf */
390 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
392 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
393 /* *(lmf_addr) = previous_lmf */
394 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
399 #endif /* #ifndef DISABLE_JIT */
402 * mono_arch_get_argument_info:
403 * @csig: a method signature
404 * @param_count: the number of parameters to consider
405 * @arg_info: an array to store the result infos
407 * Gathers information on parameters such as size, alignment and
408 * padding. arg_info should be large enought to hold param_count + 1 entries.
410 * Returns the size of the activation frame.
413 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
415 int k, frame_size = 0;
416 guint32 size, align, pad;
419 if (MONO_TYPE_ISSTRUCT (csig->ret)) {
420 frame_size += sizeof (gpointer);
424 arg_info [0].offset = offset;
427 frame_size += sizeof (gpointer);
431 arg_info [0].size = frame_size;
433 for (k = 0; k < param_count; k++) {
434 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
436 /* ignore alignment for now */
439 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
440 arg_info [k].pad = pad;
442 arg_info [k + 1].pad = 0;
443 arg_info [k + 1].size = size;
445 arg_info [k + 1].offset = offset;
449 align = MONO_ARCH_FRAME_ALIGNMENT;
450 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
451 arg_info [k].pad = pad;
456 #define MAX_ARCH_DELEGATE_PARAMS 3
459 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
461 guint8 *code, *start;
464 start = code = mono_global_codeman_reserve (12);
466 /* Replace the this argument with the target */
467 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
468 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
469 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
471 g_assert ((code - start) <= 12);
473 mono_arch_flush_icache (start, 12);
477 size = 8 + param_count * 4;
478 start = code = mono_global_codeman_reserve (size);
480 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
481 /* slide down the arguments */
482 for (i = 0; i < param_count; ++i) {
483 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
485 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
487 g_assert ((code - start) <= size);
489 mono_arch_flush_icache (start, size);
493 *code_size = code - start;
499 * mono_arch_get_delegate_invoke_impls:
501 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
505 mono_arch_get_delegate_invoke_impls (void)
512 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
513 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
515 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
516 code = get_delegate_invoke_impl (FALSE, i, &code_len);
517 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
524 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
526 guint8 *code, *start;
528 /* FIXME: Support more cases */
529 if (MONO_TYPE_ISSTRUCT (sig->ret))
533 static guint8* cached = NULL;
534 mono_mini_arch_lock ();
536 mono_mini_arch_unlock ();
541 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
543 start = get_delegate_invoke_impl (TRUE, 0, NULL);
545 mono_mini_arch_unlock ();
548 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
551 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
553 for (i = 0; i < sig->param_count; ++i)
554 if (!mono_is_regsize_var (sig->params [i]))
557 mono_mini_arch_lock ();
558 code = cache [sig->param_count];
560 mono_mini_arch_unlock ();
565 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
566 start = mono_aot_get_trampoline (name);
569 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
571 cache [sig->param_count] = start;
572 mono_mini_arch_unlock ();
580 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
582 return (gpointer)regs [ARMREG_R0];
586 * Initialize the cpu to execute managed code.
589 mono_arch_cpu_init (void)
591 #if defined(__ARM_EABI__)
592 eabi_supported = TRUE;
594 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
597 i8_align = __alignof__ (gint64);
602 create_function_wrapper (gpointer function)
604 guint8 *start, *code;
606 start = code = mono_global_codeman_reserve (96);
609 * Construct the MonoContext structure on the stack.
612 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, sizeof (MonoContext));
614 /* save ip, lr and pc into their correspodings ctx.regs slots. */
615 ARM_STR_IMM (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + sizeof (mgreg_t) * ARMREG_IP);
616 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
617 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
619 /* save r0..r10 and fp */
620 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs));
621 ARM_STM (code, ARMREG_IP, 0x0fff);
623 /* now we can update fp. */
624 ARM_MOV_REG_REG (code, ARMREG_FP, ARMREG_SP);
626 /* make ctx.esp hold the actual value of sp at the beginning of this method. */
627 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_FP, sizeof (MonoContext));
628 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, 4 * ARMREG_SP);
629 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_SP);
631 /* make ctx.eip hold the address of the call. */
632 ARM_SUB_REG_IMM8 (code, ARMREG_LR, ARMREG_LR, 4);
633 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, pc));
635 /* r0 now points to the MonoContext */
636 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_FP);
639 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
641 *(gpointer*)code = function;
643 ARM_BLX_REG (code, ARMREG_IP);
645 /* we're back; save ctx.eip and ctx.esp into the corresponding regs slots. */
646 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, pc));
647 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
648 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
650 /* make ip point to the regs array, then restore everything, including pc. */
651 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs));
652 ARM_LDM (code, ARMREG_IP, 0xffff);
654 mono_arch_flush_icache (start, code - start);
660 * Initialize architecture specific code.
663 mono_arch_init (void)
665 InitializeCriticalSection (&mini_arch_mutex);
667 if (mini_get_debug_options ()->soft_breakpoints) {
668 single_step_func_wrapper = create_function_wrapper (debugger_agent_single_step_from_context);
669 breakpoint_func_wrapper = create_function_wrapper (debugger_agent_breakpoint_from_context);
671 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
672 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
673 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
676 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
677 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
678 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
681 arm_fpu = MONO_ARM_FPU_FPA;
682 #elif defined(ARM_FPU_VFP_HARD)
683 arm_fpu = MONO_ARM_FPU_VFP_HARD;
684 #elif defined(ARM_FPU_VFP)
685 arm_fpu = MONO_ARM_FPU_VFP;
687 arm_fpu = MONO_ARM_FPU_NONE;
692 * Cleanup architecture specific code.
695 mono_arch_cleanup (void)
700 * This function returns the optimizations supported on this cpu.
703 mono_arch_cpu_optimizations (guint32 *exclude_mask)
706 const char *cpu_arch = getenv ("MONO_CPU_ARCH");
707 if (cpu_arch != NULL) {
708 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
709 if (strncmp (cpu_arch, "armv", 4) == 0) {
710 v5_supported = cpu_arch [4] >= '5';
711 v6_supported = cpu_arch [4] >= '6';
712 v7_supported = cpu_arch [4] >= '7';
716 thumb_supported = TRUE;
723 FILE *file = fopen ("/proc/cpuinfo", "r");
725 while ((line = fgets (buf, 512, file))) {
726 if (strncmp (line, "Processor", 9) == 0) {
727 char *ver = strstr (line, "(v");
728 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
730 if (ver && (ver [2] == '6' || ver [2] == '7'))
732 if (ver && (ver [2] == '7'))
736 if (strncmp (line, "Features", 8) == 0) {
737 char *th = strstr (line, "thumb");
739 thumb_supported = TRUE;
747 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
752 /* no arm-specific optimizations yet */
758 * This function test for all SIMD functions supported.
760 * Returns a bitmask corresponding to all supported versions.
764 mono_arch_cpu_enumerate_simd_versions (void)
766 /* SIMD is currently unimplemented */
774 is_regsize_var (MonoType *t) {
777 t = mini_type_get_underlying_type (NULL, t);
784 case MONO_TYPE_FNPTR:
786 case MONO_TYPE_OBJECT:
787 case MONO_TYPE_STRING:
788 case MONO_TYPE_CLASS:
789 case MONO_TYPE_SZARRAY:
790 case MONO_TYPE_ARRAY:
792 case MONO_TYPE_GENERICINST:
793 if (!mono_type_generic_inst_is_valuetype (t))
796 case MONO_TYPE_VALUETYPE:
803 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
808 for (i = 0; i < cfg->num_varinfo; i++) {
809 MonoInst *ins = cfg->varinfo [i];
810 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
813 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
816 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
819 /* we can only allocate 32 bit values */
820 if (is_regsize_var (ins->inst_vtype)) {
821 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
822 g_assert (i == vmv->idx);
823 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
830 #define USE_EXTRA_TEMPS 0
833 mono_arch_get_global_int_regs (MonoCompile *cfg)
837 mono_arch_compute_omit_fp (cfg);
840 * FIXME: Interface calls might go through a static rgctx trampoline which
841 * sets V5, but it doesn't save it, so we need to save it ourselves, and
844 if (cfg->flags & MONO_CFG_HAS_CALLS)
845 cfg->uses_rgctx_reg = TRUE;
847 if (cfg->arch.omit_fp)
848 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
849 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
850 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
851 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
853 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
854 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
856 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
857 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
858 /* V5 is reserved for passing the vtable/rgctx/IMT method */
859 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
860 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
861 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
867 * mono_arch_regalloc_cost:
869 * Return the cost, in number of memory references, of the action of
870 * allocating the variable VMV into a register during global register
874 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
880 #endif /* #ifndef DISABLE_JIT */
882 #ifndef __GNUC_PREREQ
883 #define __GNUC_PREREQ(maj, min) (0)
887 mono_arch_flush_icache (guint8 *code, gint size)
889 #ifdef MONO_CROSS_COMPILE
891 sys_icache_invalidate (code, size);
892 #elif __GNUC_PREREQ(4, 1)
893 __clear_cache (code, code + size);
894 #elif defined(PLATFORM_ANDROID)
895 const int syscall = 0xf0002;
903 : "r" (code), "r" (code + size), "r" (syscall)
904 : "r0", "r1", "r7", "r2"
907 __asm __volatile ("mov r0, %0\n"
910 "swi 0x9f0002 @ sys_cacheflush"
912 : "r" (code), "r" (code + size), "r" (0)
913 : "r0", "r1", "r3" );
930 guint16 vtsize; /* in param area */
934 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
940 gboolean vtype_retaddr;
941 /* The index of the vret arg in the argument list */
951 /*#define __alignof__(a) sizeof(a)*/
952 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
958 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
961 if (*gr > ARMREG_R3) {
962 ainfo->offset = *stack_size;
963 ainfo->reg = ARMREG_SP; /* in the caller */
964 ainfo->storage = RegTypeBase;
967 ainfo->storage = RegTypeGeneral;
974 split = i8_align == 4;
978 if (*gr == ARMREG_R3 && split) {
979 /* first word in r3 and the second on the stack */
980 ainfo->offset = *stack_size;
981 ainfo->reg = ARMREG_SP; /* in the caller */
982 ainfo->storage = RegTypeBaseGen;
984 } else if (*gr >= ARMREG_R3) {
985 if (eabi_supported) {
986 /* darwin aligns longs to 4 byte only */
992 ainfo->offset = *stack_size;
993 ainfo->reg = ARMREG_SP; /* in the caller */
994 ainfo->storage = RegTypeBase;
997 if (eabi_supported) {
998 if (i8_align == 8 && ((*gr) & 1))
1001 ainfo->storage = RegTypeIRegPair;
1010 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
1012 guint i, gr, pstart;
1013 int n = sig->hasthis + sig->param_count;
1014 MonoType *simpletype;
1015 guint32 stack_size = 0;
1017 gboolean is_pinvoke = sig->pinvoke;
1020 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1022 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1027 /* FIXME: handle returning a struct */
1028 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1031 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (sig->ret), &align) <= sizeof (gpointer)) {
1032 cinfo->ret.storage = RegTypeStructByVal;
1034 cinfo->vtype_retaddr = TRUE;
1041 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1042 * the first argument, allowing 'this' to be always passed in the first arg reg.
1043 * Also do this if the first argument is a reference type, since virtual calls
1044 * are sometimes made using calli without sig->hasthis set, like in the delegate
1047 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1049 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1051 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1055 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1056 cinfo->vret_arg_index = 1;
1060 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1064 if (cinfo->vtype_retaddr)
1065 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1068 DEBUG(printf("params: %d\n", sig->param_count));
1069 for (i = pstart; i < sig->param_count; ++i) {
1070 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1071 /* Prevent implicit arguments and sig_cookie from
1072 being passed in registers */
1074 /* Emit the signature cookie just before the implicit arguments */
1075 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1077 DEBUG(printf("param %d: ", i));
1078 if (sig->params [i]->byref) {
1079 DEBUG(printf("byref\n"));
1080 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1084 simpletype = mini_type_get_underlying_type (NULL, sig->params [i]);
1085 switch (simpletype->type) {
1086 case MONO_TYPE_BOOLEAN:
1089 cinfo->args [n].size = 1;
1090 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1093 case MONO_TYPE_CHAR:
1096 cinfo->args [n].size = 2;
1097 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1102 cinfo->args [n].size = 4;
1103 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1109 case MONO_TYPE_FNPTR:
1110 case MONO_TYPE_CLASS:
1111 case MONO_TYPE_OBJECT:
1112 case MONO_TYPE_STRING:
1113 case MONO_TYPE_SZARRAY:
1114 case MONO_TYPE_ARRAY:
1116 cinfo->args [n].size = sizeof (gpointer);
1117 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1120 case MONO_TYPE_GENERICINST:
1121 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1122 cinfo->args [n].size = sizeof (gpointer);
1123 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1128 case MONO_TYPE_TYPEDBYREF:
1129 case MONO_TYPE_VALUETYPE: {
1135 if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1136 size = sizeof (MonoTypedRef);
1137 align = sizeof (gpointer);
1139 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1141 size = mono_class_native_size (klass, &align);
1143 size = mono_class_value_size (klass, &align);
1145 DEBUG(printf ("load %d bytes struct\n",
1146 mono_class_native_size (sig->params [i]->data.klass, NULL)));
1149 align_size += (sizeof (gpointer) - 1);
1150 align_size &= ~(sizeof (gpointer) - 1);
1151 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1152 cinfo->args [n].storage = RegTypeStructByVal;
1153 cinfo->args [n].struct_size = size;
1154 /* FIXME: align stack_size if needed */
1155 if (eabi_supported) {
1156 if (align >= 8 && (gr & 1))
1159 if (gr > ARMREG_R3) {
1160 cinfo->args [n].size = 0;
1161 cinfo->args [n].vtsize = nwords;
1163 int rest = ARMREG_R3 - gr + 1;
1164 int n_in_regs = rest >= nwords? nwords: rest;
1166 cinfo->args [n].size = n_in_regs;
1167 cinfo->args [n].vtsize = nwords - n_in_regs;
1168 cinfo->args [n].reg = gr;
1170 nwords -= n_in_regs;
1172 cinfo->args [n].offset = stack_size;
1173 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1174 stack_size += nwords * sizeof (gpointer);
1181 cinfo->args [n].size = 8;
1182 add_general (&gr, &stack_size, cinfo->args + n, FALSE);
1186 g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1190 /* Handle the case where there are no implicit arguments */
1191 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1192 /* Prevent implicit arguments and sig_cookie from
1193 being passed in registers */
1195 /* Emit the signature cookie just before the implicit arguments */
1196 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1200 simpletype = mini_type_get_underlying_type (NULL, sig->ret);
1201 switch (simpletype->type) {
1202 case MONO_TYPE_BOOLEAN:
1207 case MONO_TYPE_CHAR:
1213 case MONO_TYPE_FNPTR:
1214 case MONO_TYPE_CLASS:
1215 case MONO_TYPE_OBJECT:
1216 case MONO_TYPE_SZARRAY:
1217 case MONO_TYPE_ARRAY:
1218 case MONO_TYPE_STRING:
1219 cinfo->ret.storage = RegTypeGeneral;
1220 cinfo->ret.reg = ARMREG_R0;
1224 cinfo->ret.storage = RegTypeIRegPair;
1225 cinfo->ret.reg = ARMREG_R0;
1229 cinfo->ret.storage = RegTypeFP;
1230 cinfo->ret.reg = ARMREG_R0;
1231 /* FIXME: cinfo->ret.reg = ???;
1232 cinfo->ret.storage = RegTypeFP;*/
1234 case MONO_TYPE_GENERICINST:
1235 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1236 cinfo->ret.storage = RegTypeGeneral;
1237 cinfo->ret.reg = ARMREG_R0;
1241 case MONO_TYPE_VALUETYPE:
1242 case MONO_TYPE_TYPEDBYREF:
1243 if (cinfo->ret.storage != RegTypeStructByVal)
1244 cinfo->ret.storage = RegTypeStructByAddr;
1246 case MONO_TYPE_VOID:
1249 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1253 /* align stack size to 8 */
1254 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1255 stack_size = (stack_size + 7) & ~7;
1257 cinfo->stack_usage = stack_size;
1264 debug_omit_fp (void)
1267 return mono_debug_count ();
1274 * mono_arch_compute_omit_fp:
1276 * Determine whenever the frame pointer can be eliminated.
1279 mono_arch_compute_omit_fp (MonoCompile *cfg)
1281 MonoMethodSignature *sig;
1282 MonoMethodHeader *header;
1286 if (cfg->arch.omit_fp_computed)
1289 header = cfg->header;
1291 sig = mono_method_signature (cfg->method);
1293 if (!cfg->arch.cinfo)
1294 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1295 cinfo = cfg->arch.cinfo;
1298 * FIXME: Remove some of the restrictions.
1300 cfg->arch.omit_fp = TRUE;
1301 cfg->arch.omit_fp_computed = TRUE;
1303 if (cfg->disable_omit_fp)
1304 cfg->arch.omit_fp = FALSE;
1305 if (!debug_omit_fp ())
1306 cfg->arch.omit_fp = FALSE;
1308 if (cfg->method->save_lmf)
1309 cfg->arch.omit_fp = FALSE;
1311 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1312 cfg->arch.omit_fp = FALSE;
1313 if (header->num_clauses)
1314 cfg->arch.omit_fp = FALSE;
1315 if (cfg->param_area)
1316 cfg->arch.omit_fp = FALSE;
1317 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1318 cfg->arch.omit_fp = FALSE;
1319 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1320 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1321 cfg->arch.omit_fp = FALSE;
1322 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1323 ArgInfo *ainfo = &cinfo->args [i];
1325 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1327 * The stack offset can only be determined when the frame
1330 cfg->arch.omit_fp = FALSE;
1335 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1336 MonoInst *ins = cfg->varinfo [i];
1339 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1344 * Set var information according to the calling convention. arm version.
1345 * The locals var stuff should most likely be split in another method.
1348 mono_arch_allocate_vars (MonoCompile *cfg)
1350 MonoMethodSignature *sig;
1351 MonoMethodHeader *header;
1353 int i, offset, size, align, curinst;
1357 sig = mono_method_signature (cfg->method);
1359 if (!cfg->arch.cinfo)
1360 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1361 cinfo = cfg->arch.cinfo;
1363 mono_arch_compute_omit_fp (cfg);
1365 if (cfg->arch.omit_fp)
1366 cfg->frame_reg = ARMREG_SP;
1368 cfg->frame_reg = ARMREG_FP;
1370 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1372 /* allow room for the vararg method args: void* and long/double */
1373 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1374 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1376 header = cfg->header;
1378 /* See mono_arch_get_global_int_regs () */
1379 if (cfg->flags & MONO_CFG_HAS_CALLS)
1380 cfg->uses_rgctx_reg = TRUE;
1382 if (cfg->frame_reg != ARMREG_SP)
1383 cfg->used_int_regs |= 1 << cfg->frame_reg;
1385 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1386 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1387 cfg->used_int_regs |= (1 << ARMREG_V5);
1391 if (!MONO_TYPE_ISSTRUCT (sig->ret)) {
1392 switch (mini_type_get_underlying_type (NULL, sig->ret)->type) {
1393 case MONO_TYPE_VOID:
1396 cfg->ret->opcode = OP_REGVAR;
1397 cfg->ret->inst_c0 = ARMREG_R0;
1401 /* local vars are at a positive offset from the stack pointer */
1403 * also note that if the function uses alloca, we use FP
1404 * to point at the local variables.
1406 offset = 0; /* linkage area */
1407 /* align the offset to 16 bytes: not sure this is needed here */
1409 //offset &= ~(8 - 1);
1411 /* add parameter area size for called functions */
1412 offset += cfg->param_area;
1415 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1418 /* allow room to save the return value */
1419 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1422 /* the MonoLMF structure is stored just below the stack pointer */
1423 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1424 if (cinfo->ret.storage == RegTypeStructByVal) {
1425 cfg->ret->opcode = OP_REGOFFSET;
1426 cfg->ret->inst_basereg = cfg->frame_reg;
1427 offset += sizeof (gpointer) - 1;
1428 offset &= ~(sizeof (gpointer) - 1);
1429 cfg->ret->inst_offset = - offset;
1431 ins = cfg->vret_addr;
1432 offset += sizeof(gpointer) - 1;
1433 offset &= ~(sizeof(gpointer) - 1);
1434 ins->inst_offset = offset;
1435 ins->opcode = OP_REGOFFSET;
1436 ins->inst_basereg = cfg->frame_reg;
1437 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1438 printf ("vret_addr =");
1439 mono_print_ins (cfg->vret_addr);
1442 offset += sizeof(gpointer);
1445 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1446 if (cfg->arch.seq_point_info_var) {
1449 ins = cfg->arch.seq_point_info_var;
1453 offset += align - 1;
1454 offset &= ~(align - 1);
1455 ins->opcode = OP_REGOFFSET;
1456 ins->inst_basereg = cfg->frame_reg;
1457 ins->inst_offset = offset;
1460 ins = cfg->arch.ss_trigger_page_var;
1463 offset += align - 1;
1464 offset &= ~(align - 1);
1465 ins->opcode = OP_REGOFFSET;
1466 ins->inst_basereg = cfg->frame_reg;
1467 ins->inst_offset = offset;
1471 if (cfg->arch.seq_point_read_var) {
1474 ins = cfg->arch.seq_point_read_var;
1478 offset += align - 1;
1479 offset &= ~(align - 1);
1480 ins->opcode = OP_REGOFFSET;
1481 ins->inst_basereg = cfg->frame_reg;
1482 ins->inst_offset = offset;
1485 ins = cfg->arch.seq_point_ss_method_var;
1488 offset += align - 1;
1489 offset &= ~(align - 1);
1490 ins->opcode = OP_REGOFFSET;
1491 ins->inst_basereg = cfg->frame_reg;
1492 ins->inst_offset = offset;
1495 ins = cfg->arch.seq_point_bp_method_var;
1498 offset += align - 1;
1499 offset &= ~(align - 1);
1500 ins->opcode = OP_REGOFFSET;
1501 ins->inst_basereg = cfg->frame_reg;
1502 ins->inst_offset = offset;
1506 cfg->locals_min_stack_offset = offset;
1508 curinst = cfg->locals_start;
1509 for (i = curinst; i < cfg->num_varinfo; ++i) {
1510 ins = cfg->varinfo [i];
1511 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1514 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1515 * pinvoke wrappers when they call functions returning structure */
1516 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (ins->inst_vtype) && ins->inst_vtype->type != MONO_TYPE_TYPEDBYREF) {
1517 size = mono_class_native_size (mono_class_from_mono_type (ins->inst_vtype), &ualign);
1521 size = mono_type_size (ins->inst_vtype, &align);
1523 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1524 * since it loads/stores misaligned words, which don't do the right thing.
1526 if (align < 4 && size >= 4)
1528 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1529 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1530 offset += align - 1;
1531 offset &= ~(align - 1);
1532 ins->opcode = OP_REGOFFSET;
1533 ins->inst_offset = offset;
1534 ins->inst_basereg = cfg->frame_reg;
1536 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1539 cfg->locals_max_stack_offset = offset;
1543 ins = cfg->args [curinst];
1544 if (ins->opcode != OP_REGVAR) {
1545 ins->opcode = OP_REGOFFSET;
1546 ins->inst_basereg = cfg->frame_reg;
1547 offset += sizeof (gpointer) - 1;
1548 offset &= ~(sizeof (gpointer) - 1);
1549 ins->inst_offset = offset;
1550 offset += sizeof (gpointer);
1555 if (sig->call_convention == MONO_CALL_VARARG) {
1559 /* Allocate a local slot to hold the sig cookie address */
1560 offset += align - 1;
1561 offset &= ~(align - 1);
1562 cfg->sig_cookie = offset;
1566 for (i = 0; i < sig->param_count; ++i) {
1567 ins = cfg->args [curinst];
1569 if (ins->opcode != OP_REGVAR) {
1570 ins->opcode = OP_REGOFFSET;
1571 ins->inst_basereg = cfg->frame_reg;
1572 size = mini_type_stack_size_full (NULL, sig->params [i], &ualign, sig->pinvoke);
1574 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1575 * since it loads/stores misaligned words, which don't do the right thing.
1577 if (align < 4 && size >= 4)
1579 /* The code in the prolog () stores words when storing vtypes received in a register */
1580 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1582 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1583 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1584 offset += align - 1;
1585 offset &= ~(align - 1);
1586 ins->inst_offset = offset;
1592 /* align the offset to 8 bytes */
1593 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
1594 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1599 cfg->stack_offset = offset;
1603 mono_arch_create_vars (MonoCompile *cfg)
1605 MonoMethodSignature *sig;
1608 sig = mono_method_signature (cfg->method);
1610 if (!cfg->arch.cinfo)
1611 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1612 cinfo = cfg->arch.cinfo;
1614 if (cinfo->ret.storage == RegTypeStructByVal)
1615 cfg->ret_var_is_local = TRUE;
1617 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
1618 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1619 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1620 printf ("vret_addr = ");
1621 mono_print_ins (cfg->vret_addr);
1625 if (cfg->gen_seq_points) {
1626 if (cfg->soft_breakpoints) {
1627 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1628 ins->flags |= MONO_INST_VOLATILE;
1629 cfg->arch.seq_point_read_var = ins;
1631 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1632 ins->flags |= MONO_INST_VOLATILE;
1633 cfg->arch.seq_point_ss_method_var = ins;
1635 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1636 ins->flags |= MONO_INST_VOLATILE;
1637 cfg->arch.seq_point_bp_method_var = ins;
1639 g_assert (!cfg->compile_aot);
1640 } else if (cfg->compile_aot) {
1641 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1642 ins->flags |= MONO_INST_VOLATILE;
1643 cfg->arch.seq_point_info_var = ins;
1645 /* Allocate a separate variable for this to save 1 load per seq point */
1646 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1647 ins->flags |= MONO_INST_VOLATILE;
1648 cfg->arch.ss_trigger_page_var = ins;
1654 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1656 MonoMethodSignature *tmp_sig;
1659 if (call->tail_call)
1662 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1665 * mono_ArgIterator_Setup assumes the signature cookie is
1666 * passed first and all the arguments which were before it are
1667 * passed on the stack after the signature. So compensate by
1668 * passing a different signature.
1670 tmp_sig = mono_metadata_signature_dup (call->signature);
1671 tmp_sig->param_count -= call->signature->sentinelpos;
1672 tmp_sig->sentinelpos = 0;
1673 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1675 sig_reg = mono_alloc_ireg (cfg);
1676 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1678 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
1683 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1688 LLVMCallInfo *linfo;
1690 n = sig->param_count + sig->hasthis;
1692 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1694 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1697 * LLVM always uses the native ABI while we use our own ABI, the
1698 * only difference is the handling of vtypes:
1699 * - we only pass/receive them in registers in some cases, and only
1700 * in 1 or 2 integer registers.
1702 if (cinfo->vtype_retaddr) {
1703 /* Vtype returned using a hidden argument */
1704 linfo->ret.storage = LLVMArgVtypeRetAddr;
1705 linfo->vret_arg_index = cinfo->vret_arg_index;
1706 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1707 cfg->exception_message = g_strdup ("unknown ret conv");
1708 cfg->disable_llvm = TRUE;
1712 for (i = 0; i < n; ++i) {
1713 ainfo = cinfo->args + i;
1715 linfo->args [i].storage = LLVMArgNone;
1717 switch (ainfo->storage) {
1718 case RegTypeGeneral:
1719 case RegTypeIRegPair:
1721 linfo->args [i].storage = LLVMArgInIReg;
1723 case RegTypeStructByVal:
1724 // FIXME: Passing entirely on the stack or split reg/stack
1725 if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1726 linfo->args [i].storage = LLVMArgVtypeInReg;
1727 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1728 if (ainfo->size == 2)
1729 linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1731 linfo->args [i].pair_storage [1] = LLVMArgNone;
1733 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1734 cfg->disable_llvm = TRUE;
1738 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1739 cfg->disable_llvm = TRUE;
1749 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1752 MonoMethodSignature *sig;
1756 sig = call->signature;
1757 n = sig->param_count + sig->hasthis;
1759 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1761 for (i = 0; i < n; ++i) {
1762 ArgInfo *ainfo = cinfo->args + i;
1765 if (i >= sig->hasthis)
1766 t = sig->params [i - sig->hasthis];
1768 t = &mono_defaults.int_class->byval_arg;
1769 t = mini_type_get_underlying_type (NULL, t);
1771 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1772 /* Emit the signature cookie just before the implicit arguments */
1773 emit_sig_cookie (cfg, call, cinfo);
1776 in = call->args [i];
1778 switch (ainfo->storage) {
1779 case RegTypeGeneral:
1780 case RegTypeIRegPair:
1781 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1782 MONO_INST_NEW (cfg, ins, OP_MOVE);
1783 ins->dreg = mono_alloc_ireg (cfg);
1784 ins->sreg1 = in->dreg + 1;
1785 MONO_ADD_INS (cfg->cbb, ins);
1786 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1788 MONO_INST_NEW (cfg, ins, OP_MOVE);
1789 ins->dreg = mono_alloc_ireg (cfg);
1790 ins->sreg1 = in->dreg + 2;
1791 MONO_ADD_INS (cfg->cbb, ins);
1792 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1793 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1794 if (ainfo->size == 4) {
1795 if (IS_SOFT_FLOAT) {
1796 /* mono_emit_call_args () have already done the r8->r4 conversion */
1797 /* The converted value is in an int vreg */
1798 MONO_INST_NEW (cfg, ins, OP_MOVE);
1799 ins->dreg = mono_alloc_ireg (cfg);
1800 ins->sreg1 = in->dreg;
1801 MONO_ADD_INS (cfg->cbb, ins);
1802 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1806 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1807 creg = mono_alloc_ireg (cfg);
1808 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1809 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1812 if (IS_SOFT_FLOAT) {
1813 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1814 ins->dreg = mono_alloc_ireg (cfg);
1815 ins->sreg1 = in->dreg;
1816 MONO_ADD_INS (cfg->cbb, ins);
1817 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1819 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1820 ins->dreg = mono_alloc_ireg (cfg);
1821 ins->sreg1 = in->dreg;
1822 MONO_ADD_INS (cfg->cbb, ins);
1823 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1827 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1828 creg = mono_alloc_ireg (cfg);
1829 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1830 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1831 creg = mono_alloc_ireg (cfg);
1832 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1833 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1836 cfg->flags |= MONO_CFG_HAS_FPOUT;
1838 MONO_INST_NEW (cfg, ins, OP_MOVE);
1839 ins->dreg = mono_alloc_ireg (cfg);
1840 ins->sreg1 = in->dreg;
1841 MONO_ADD_INS (cfg->cbb, ins);
1843 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1846 case RegTypeStructByAddr:
1849 /* FIXME: where si the data allocated? */
1850 arg->backend.reg3 = ainfo->reg;
1851 call->used_iregs |= 1 << ainfo->reg;
1852 g_assert_not_reached ();
1855 case RegTypeStructByVal:
1856 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1857 ins->opcode = OP_OUTARG_VT;
1858 ins->sreg1 = in->dreg;
1859 ins->klass = in->klass;
1860 ins->inst_p0 = call;
1861 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1862 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1863 mono_call_inst_add_outarg_vt (cfg, call, ins);
1864 MONO_ADD_INS (cfg->cbb, ins);
1867 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1868 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1869 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1870 if (t->type == MONO_TYPE_R8) {
1871 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1874 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1876 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1879 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1882 case RegTypeBaseGen:
1883 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1884 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1885 MONO_INST_NEW (cfg, ins, OP_MOVE);
1886 ins->dreg = mono_alloc_ireg (cfg);
1887 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1888 MONO_ADD_INS (cfg->cbb, ins);
1889 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1890 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1893 /* This should work for soft-float as well */
1895 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1896 creg = mono_alloc_ireg (cfg);
1897 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1898 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1899 creg = mono_alloc_ireg (cfg);
1900 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1901 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1902 cfg->flags |= MONO_CFG_HAS_FPOUT;
1904 g_assert_not_reached ();
1911 arg->backend.reg3 = ainfo->reg;
1912 /* FP args are passed in int regs */
1913 call->used_iregs |= 1 << ainfo->reg;
1914 if (ainfo->size == 8) {
1915 arg->opcode = OP_OUTARG_R8;
1916 call->used_iregs |= 1 << (ainfo->reg + 1);
1918 arg->opcode = OP_OUTARG_R4;
1921 cfg->flags |= MONO_CFG_HAS_FPOUT;
1925 g_assert_not_reached ();
1929 /* Handle the case where there are no implicit arguments */
1930 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1931 emit_sig_cookie (cfg, call, cinfo);
1933 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1936 if (cinfo->ret.storage == RegTypeStructByVal) {
1937 /* The JIT will transform this into a normal call */
1938 call->vret_in_reg = TRUE;
1940 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1941 vtarg->sreg1 = call->vret_var->dreg;
1942 vtarg->dreg = mono_alloc_preg (cfg);
1943 MONO_ADD_INS (cfg->cbb, vtarg);
1945 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1949 call->stack_usage = cinfo->stack_usage;
1955 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1957 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1958 ArgInfo *ainfo = ins->inst_p1;
1959 int ovf_size = ainfo->vtsize;
1960 int doffset = ainfo->offset;
1961 int struct_size = ainfo->struct_size;
1962 int i, soffset, dreg, tmpreg;
1965 for (i = 0; i < ainfo->size; ++i) {
1966 dreg = mono_alloc_ireg (cfg);
1967 switch (struct_size) {
1969 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1972 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
1975 tmpreg = mono_alloc_ireg (cfg);
1976 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1977 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
1978 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
1979 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1980 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
1981 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
1982 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1985 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1988 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
1989 soffset += sizeof (gpointer);
1990 struct_size -= sizeof (gpointer);
1992 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
1994 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
1998 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2000 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2003 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2006 if (COMPILE_LLVM (cfg)) {
2007 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2009 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2010 ins->sreg1 = val->dreg + 1;
2011 ins->sreg2 = val->dreg + 2;
2012 MONO_ADD_INS (cfg->cbb, ins);
2017 case MONO_ARM_FPU_NONE:
2018 if (ret->type == MONO_TYPE_R8) {
2021 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2022 ins->dreg = cfg->ret->dreg;
2023 ins->sreg1 = val->dreg;
2024 MONO_ADD_INS (cfg->cbb, ins);
2027 if (ret->type == MONO_TYPE_R4) {
2028 /* Already converted to an int in method_to_ir () */
2029 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2033 case MONO_ARM_FPU_VFP:
2034 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2037 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2038 ins->dreg = cfg->ret->dreg;
2039 ins->sreg1 = val->dreg;
2040 MONO_ADD_INS (cfg->cbb, ins);
2044 case MONO_ARM_FPU_FPA:
2045 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
2046 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2051 g_assert_not_reached ();
2055 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2058 #endif /* #ifndef DISABLE_JIT */
2061 mono_arch_is_inst_imm (gint64 imm)
2066 #define DYN_CALL_STACK_ARGS 6
2069 MonoMethodSignature *sig;
2074 mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
2080 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2084 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2087 switch (cinfo->ret.storage) {
2089 case RegTypeGeneral:
2090 case RegTypeIRegPair:
2091 case RegTypeStructByAddr:
2104 for (i = 0; i < cinfo->nargs; ++i) {
2105 switch (cinfo->args [i].storage) {
2106 case RegTypeGeneral:
2108 case RegTypeIRegPair:
2111 if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2114 case RegTypeStructByVal:
2115 if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2123 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2124 for (i = 0; i < sig->param_count; ++i) {
2125 MonoType *t = sig->params [i];
2151 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2153 ArchDynCallInfo *info;
2156 cinfo = get_call_info (NULL, NULL, sig);
2158 if (!dyn_call_supported (cinfo, sig)) {
2163 info = g_new0 (ArchDynCallInfo, 1);
2164 // FIXME: Preprocess the info to speed up start_dyn_call ()
2166 info->cinfo = cinfo;
2168 return (MonoDynCallInfo*)info;
2172 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2174 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2176 g_free (ainfo->cinfo);
2181 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2183 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2184 DynCallArgs *p = (DynCallArgs*)buf;
2185 int arg_index, greg, i, j, pindex;
2186 MonoMethodSignature *sig = dinfo->sig;
2188 g_assert (buf_len >= sizeof (DynCallArgs));
2197 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2198 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2203 if (dinfo->cinfo->vtype_retaddr)
2204 p->regs [greg ++] = (mgreg_t)ret;
2206 for (i = pindex; i < sig->param_count; i++) {
2207 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2208 gpointer *arg = args [arg_index ++];
2209 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2212 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2214 else if (ainfo->storage == RegTypeBase)
2215 slot = PARAM_REGS + (ainfo->offset / 4);
2217 g_assert_not_reached ();
2220 p->regs [slot] = (mgreg_t)*arg;
2225 case MONO_TYPE_STRING:
2226 case MONO_TYPE_CLASS:
2227 case MONO_TYPE_ARRAY:
2228 case MONO_TYPE_SZARRAY:
2229 case MONO_TYPE_OBJECT:
2233 p->regs [slot] = (mgreg_t)*arg;
2235 case MONO_TYPE_BOOLEAN:
2237 p->regs [slot] = *(guint8*)arg;
2240 p->regs [slot] = *(gint8*)arg;
2243 p->regs [slot] = *(gint16*)arg;
2246 case MONO_TYPE_CHAR:
2247 p->regs [slot] = *(guint16*)arg;
2250 p->regs [slot] = *(gint32*)arg;
2253 p->regs [slot] = *(guint32*)arg;
2257 p->regs [slot ++] = (mgreg_t)arg [0];
2258 p->regs [slot] = (mgreg_t)arg [1];
2261 p->regs [slot] = *(mgreg_t*)arg;
2264 p->regs [slot ++] = (mgreg_t)arg [0];
2265 p->regs [slot] = (mgreg_t)arg [1];
2267 case MONO_TYPE_GENERICINST:
2268 if (MONO_TYPE_IS_REFERENCE (t)) {
2269 p->regs [slot] = (mgreg_t)*arg;
2274 case MONO_TYPE_VALUETYPE:
2275 g_assert (ainfo->storage == RegTypeStructByVal);
2277 if (ainfo->size == 0)
2278 slot = PARAM_REGS + (ainfo->offset / 4);
2282 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2283 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2286 g_assert_not_reached ();
2292 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2294 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2295 MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2296 guint8 *ret = ((DynCallArgs*)buf)->ret;
2297 mgreg_t res = ((DynCallArgs*)buf)->res;
2298 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2300 switch (mono_type_get_underlying_type (sig->ret)->type) {
2301 case MONO_TYPE_VOID:
2302 *(gpointer*)ret = NULL;
2304 case MONO_TYPE_STRING:
2305 case MONO_TYPE_CLASS:
2306 case MONO_TYPE_ARRAY:
2307 case MONO_TYPE_SZARRAY:
2308 case MONO_TYPE_OBJECT:
2312 *(gpointer*)ret = (gpointer)res;
2318 case MONO_TYPE_BOOLEAN:
2319 *(guint8*)ret = res;
2322 *(gint16*)ret = res;
2325 case MONO_TYPE_CHAR:
2326 *(guint16*)ret = res;
2329 *(gint32*)ret = res;
2332 *(guint32*)ret = res;
2336 /* This handles endianness as well */
2337 ((gint32*)ret) [0] = res;
2338 ((gint32*)ret) [1] = res2;
2340 case MONO_TYPE_GENERICINST:
2341 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2342 *(gpointer*)ret = (gpointer)res;
2347 case MONO_TYPE_VALUETYPE:
2348 g_assert (ainfo->cinfo->vtype_retaddr);
2353 *(float*)ret = *(float*)&res;
2355 case MONO_TYPE_R8: {
2362 *(double*)ret = *(double*)®s;
2366 g_assert_not_reached ();
2373 * Allow tracing to work with this interface (with an optional argument)
2377 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2381 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2382 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2383 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2384 code = emit_call_reg (code, ARMREG_R2);
2397 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2400 int save_mode = SAVE_NONE;
2402 MonoMethod *method = cfg->method;
2403 int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2404 int save_offset = cfg->param_area;
2408 offset = code - cfg->native_code;
2409 /* we need about 16 instructions */
2410 if (offset > (cfg->code_size - 16 * 4)) {
2411 cfg->code_size *= 2;
2412 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2413 code = cfg->native_code + offset;
2416 case MONO_TYPE_VOID:
2417 /* special case string .ctor icall */
2418 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2419 save_mode = SAVE_ONE;
2421 save_mode = SAVE_NONE;
2425 save_mode = SAVE_TWO;
2429 save_mode = SAVE_FP;
2431 case MONO_TYPE_VALUETYPE:
2432 save_mode = SAVE_STRUCT;
2435 save_mode = SAVE_ONE;
2439 switch (save_mode) {
2441 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2442 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2443 if (enable_arguments) {
2444 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2445 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2449 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2450 if (enable_arguments) {
2451 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2455 /* FIXME: what reg? */
2456 if (enable_arguments) {
2457 /* FIXME: what reg? */
2461 if (enable_arguments) {
2462 /* FIXME: get the actual address */
2463 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2471 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2472 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2473 code = emit_call_reg (code, ARMREG_IP);
2475 switch (save_mode) {
2477 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2478 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2481 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2495 * The immediate field for cond branches is big enough for all reasonable methods
2497 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2498 if (0 && ins->inst_true_bb->native_offset) { \
2499 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2501 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2502 ARM_B_COND (code, (condcode), 0); \
2505 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2507 /* emit an exception if condition is fail
2509 * We assign the extra code used to throw the implicit exceptions
2510 * to cfg->bb_exit as far as the big branch handling is concerned
2512 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
2514 mono_add_patch_info (cfg, code - cfg->native_code, \
2515 MONO_PATCH_INFO_EXC, exc_name); \
2516 ARM_BL_COND (code, (condcode), 0); \
2519 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2522 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2527 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2529 MonoInst *ins, *n, *last_ins = NULL;
2531 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2532 switch (ins->opcode) {
2535 /* Already done by an arch-independent pass */
2537 case OP_LOAD_MEMBASE:
2538 case OP_LOADI4_MEMBASE:
2540 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2541 * OP_LOAD_MEMBASE offset(basereg), reg
2543 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2544 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2545 ins->inst_basereg == last_ins->inst_destbasereg &&
2546 ins->inst_offset == last_ins->inst_offset) {
2547 if (ins->dreg == last_ins->sreg1) {
2548 MONO_DELETE_INS (bb, ins);
2551 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2552 ins->opcode = OP_MOVE;
2553 ins->sreg1 = last_ins->sreg1;
2557 * Note: reg1 must be different from the basereg in the second load
2558 * OP_LOAD_MEMBASE offset(basereg), reg1
2559 * OP_LOAD_MEMBASE offset(basereg), reg2
2561 * OP_LOAD_MEMBASE offset(basereg), reg1
2562 * OP_MOVE reg1, reg2
2564 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2565 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2566 ins->inst_basereg != last_ins->dreg &&
2567 ins->inst_basereg == last_ins->inst_basereg &&
2568 ins->inst_offset == last_ins->inst_offset) {
2570 if (ins->dreg == last_ins->dreg) {
2571 MONO_DELETE_INS (bb, ins);
2574 ins->opcode = OP_MOVE;
2575 ins->sreg1 = last_ins->dreg;
2578 //g_assert_not_reached ();
2582 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2583 * OP_LOAD_MEMBASE offset(basereg), reg
2585 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2586 * OP_ICONST reg, imm
2588 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2589 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2590 ins->inst_basereg == last_ins->inst_destbasereg &&
2591 ins->inst_offset == last_ins->inst_offset) {
2592 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2593 ins->opcode = OP_ICONST;
2594 ins->inst_c0 = last_ins->inst_imm;
2595 g_assert_not_reached (); // check this rule
2599 case OP_LOADU1_MEMBASE:
2600 case OP_LOADI1_MEMBASE:
2601 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2602 ins->inst_basereg == last_ins->inst_destbasereg &&
2603 ins->inst_offset == last_ins->inst_offset) {
2604 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2605 ins->sreg1 = last_ins->sreg1;
2608 case OP_LOADU2_MEMBASE:
2609 case OP_LOADI2_MEMBASE:
2610 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2611 ins->inst_basereg == last_ins->inst_destbasereg &&
2612 ins->inst_offset == last_ins->inst_offset) {
2613 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2614 ins->sreg1 = last_ins->sreg1;
2618 ins->opcode = OP_MOVE;
2622 if (ins->dreg == ins->sreg1) {
2623 MONO_DELETE_INS (bb, ins);
2627 * OP_MOVE sreg, dreg
2628 * OP_MOVE dreg, sreg
2630 if (last_ins && last_ins->opcode == OP_MOVE &&
2631 ins->sreg1 == last_ins->dreg &&
2632 ins->dreg == last_ins->sreg1) {
2633 MONO_DELETE_INS (bb, ins);
2641 bb->last_ins = last_ins;
2645 * the branch_cc_table should maintain the order of these
2659 branch_cc_table [] = {
2673 #define ADD_NEW_INS(cfg,dest,op) do { \
2674 MONO_INST_NEW ((cfg), (dest), (op)); \
2675 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2679 map_to_reg_reg_op (int op)
2688 case OP_COMPARE_IMM:
2690 case OP_ICOMPARE_IMM:
2704 case OP_LOAD_MEMBASE:
2705 return OP_LOAD_MEMINDEX;
2706 case OP_LOADI4_MEMBASE:
2707 return OP_LOADI4_MEMINDEX;
2708 case OP_LOADU4_MEMBASE:
2709 return OP_LOADU4_MEMINDEX;
2710 case OP_LOADU1_MEMBASE:
2711 return OP_LOADU1_MEMINDEX;
2712 case OP_LOADI2_MEMBASE:
2713 return OP_LOADI2_MEMINDEX;
2714 case OP_LOADU2_MEMBASE:
2715 return OP_LOADU2_MEMINDEX;
2716 case OP_LOADI1_MEMBASE:
2717 return OP_LOADI1_MEMINDEX;
2718 case OP_STOREI1_MEMBASE_REG:
2719 return OP_STOREI1_MEMINDEX;
2720 case OP_STOREI2_MEMBASE_REG:
2721 return OP_STOREI2_MEMINDEX;
2722 case OP_STOREI4_MEMBASE_REG:
2723 return OP_STOREI4_MEMINDEX;
2724 case OP_STORE_MEMBASE_REG:
2725 return OP_STORE_MEMINDEX;
2726 case OP_STORER4_MEMBASE_REG:
2727 return OP_STORER4_MEMINDEX;
2728 case OP_STORER8_MEMBASE_REG:
2729 return OP_STORER8_MEMINDEX;
2730 case OP_STORE_MEMBASE_IMM:
2731 return OP_STORE_MEMBASE_REG;
2732 case OP_STOREI1_MEMBASE_IMM:
2733 return OP_STOREI1_MEMBASE_REG;
2734 case OP_STOREI2_MEMBASE_IMM:
2735 return OP_STOREI2_MEMBASE_REG;
2736 case OP_STOREI4_MEMBASE_IMM:
2737 return OP_STOREI4_MEMBASE_REG;
2739 g_assert_not_reached ();
2743 * Remove from the instruction list the instructions that can't be
2744 * represented with very simple instructions with no register
2748 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2750 MonoInst *ins, *temp, *last_ins = NULL;
2751 int rot_amount, imm8, low_imm;
2753 MONO_BB_FOR_EACH_INS (bb, ins) {
2755 switch (ins->opcode) {
2759 case OP_COMPARE_IMM:
2760 case OP_ICOMPARE_IMM:
2774 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2775 ADD_NEW_INS (cfg, temp, OP_ICONST);
2776 temp->inst_c0 = ins->inst_imm;
2777 temp->dreg = mono_alloc_ireg (cfg);
2778 ins->sreg2 = temp->dreg;
2779 ins->opcode = mono_op_imm_to_op (ins->opcode);
2781 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2787 if (ins->inst_imm == 1) {
2788 ins->opcode = OP_MOVE;
2791 if (ins->inst_imm == 0) {
2792 ins->opcode = OP_ICONST;
2796 imm8 = mono_is_power_of_two (ins->inst_imm);
2798 ins->opcode = OP_SHL_IMM;
2799 ins->inst_imm = imm8;
2802 ADD_NEW_INS (cfg, temp, OP_ICONST);
2803 temp->inst_c0 = ins->inst_imm;
2804 temp->dreg = mono_alloc_ireg (cfg);
2805 ins->sreg2 = temp->dreg;
2806 ins->opcode = OP_IMUL;
2812 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2813 /* ARM sets the C flag to 1 if there was _no_ overflow */
2814 ins->next->opcode = OP_COND_EXC_NC;
2816 case OP_LOCALLOC_IMM:
2817 ADD_NEW_INS (cfg, temp, OP_ICONST);
2818 temp->inst_c0 = ins->inst_imm;
2819 temp->dreg = mono_alloc_ireg (cfg);
2820 ins->sreg1 = temp->dreg;
2821 ins->opcode = OP_LOCALLOC;
2823 case OP_LOAD_MEMBASE:
2824 case OP_LOADI4_MEMBASE:
2825 case OP_LOADU4_MEMBASE:
2826 case OP_LOADU1_MEMBASE:
2827 /* we can do two things: load the immed in a register
2828 * and use an indexed load, or see if the immed can be
2829 * represented as an ad_imm + a load with a smaller offset
2830 * that fits. We just do the first for now, optimize later.
2832 if (arm_is_imm12 (ins->inst_offset))
2834 ADD_NEW_INS (cfg, temp, OP_ICONST);
2835 temp->inst_c0 = ins->inst_offset;
2836 temp->dreg = mono_alloc_ireg (cfg);
2837 ins->sreg2 = temp->dreg;
2838 ins->opcode = map_to_reg_reg_op (ins->opcode);
2840 case OP_LOADI2_MEMBASE:
2841 case OP_LOADU2_MEMBASE:
2842 case OP_LOADI1_MEMBASE:
2843 if (arm_is_imm8 (ins->inst_offset))
2845 ADD_NEW_INS (cfg, temp, OP_ICONST);
2846 temp->inst_c0 = ins->inst_offset;
2847 temp->dreg = mono_alloc_ireg (cfg);
2848 ins->sreg2 = temp->dreg;
2849 ins->opcode = map_to_reg_reg_op (ins->opcode);
2851 case OP_LOADR4_MEMBASE:
2852 case OP_LOADR8_MEMBASE:
2853 if (arm_is_fpimm8 (ins->inst_offset))
2855 low_imm = ins->inst_offset & 0x1ff;
2856 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2857 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2858 temp->inst_imm = ins->inst_offset & ~0x1ff;
2859 temp->sreg1 = ins->inst_basereg;
2860 temp->dreg = mono_alloc_ireg (cfg);
2861 ins->inst_basereg = temp->dreg;
2862 ins->inst_offset = low_imm;
2866 ADD_NEW_INS (cfg, temp, OP_ICONST);
2867 temp->inst_c0 = ins->inst_offset;
2868 temp->dreg = mono_alloc_ireg (cfg);
2870 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2871 add_ins->sreg1 = ins->inst_basereg;
2872 add_ins->sreg2 = temp->dreg;
2873 add_ins->dreg = mono_alloc_ireg (cfg);
2875 ins->inst_basereg = add_ins->dreg;
2876 ins->inst_offset = 0;
2879 case OP_STORE_MEMBASE_REG:
2880 case OP_STOREI4_MEMBASE_REG:
2881 case OP_STOREI1_MEMBASE_REG:
2882 if (arm_is_imm12 (ins->inst_offset))
2884 ADD_NEW_INS (cfg, temp, OP_ICONST);
2885 temp->inst_c0 = ins->inst_offset;
2886 temp->dreg = mono_alloc_ireg (cfg);
2887 ins->sreg2 = temp->dreg;
2888 ins->opcode = map_to_reg_reg_op (ins->opcode);
2890 case OP_STOREI2_MEMBASE_REG:
2891 if (arm_is_imm8 (ins->inst_offset))
2893 ADD_NEW_INS (cfg, temp, OP_ICONST);
2894 temp->inst_c0 = ins->inst_offset;
2895 temp->dreg = mono_alloc_ireg (cfg);
2896 ins->sreg2 = temp->dreg;
2897 ins->opcode = map_to_reg_reg_op (ins->opcode);
2899 case OP_STORER4_MEMBASE_REG:
2900 case OP_STORER8_MEMBASE_REG:
2901 if (arm_is_fpimm8 (ins->inst_offset))
2903 low_imm = ins->inst_offset & 0x1ff;
2904 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2905 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2906 temp->inst_imm = ins->inst_offset & ~0x1ff;
2907 temp->sreg1 = ins->inst_destbasereg;
2908 temp->dreg = mono_alloc_ireg (cfg);
2909 ins->inst_destbasereg = temp->dreg;
2910 ins->inst_offset = low_imm;
2914 ADD_NEW_INS (cfg, temp, OP_ICONST);
2915 temp->inst_c0 = ins->inst_offset;
2916 temp->dreg = mono_alloc_ireg (cfg);
2918 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2919 add_ins->sreg1 = ins->inst_destbasereg;
2920 add_ins->sreg2 = temp->dreg;
2921 add_ins->dreg = mono_alloc_ireg (cfg);
2923 ins->inst_destbasereg = add_ins->dreg;
2924 ins->inst_offset = 0;
2927 case OP_STORE_MEMBASE_IMM:
2928 case OP_STOREI1_MEMBASE_IMM:
2929 case OP_STOREI2_MEMBASE_IMM:
2930 case OP_STOREI4_MEMBASE_IMM:
2931 ADD_NEW_INS (cfg, temp, OP_ICONST);
2932 temp->inst_c0 = ins->inst_imm;
2933 temp->dreg = mono_alloc_ireg (cfg);
2934 ins->sreg1 = temp->dreg;
2935 ins->opcode = map_to_reg_reg_op (ins->opcode);
2937 goto loop_start; /* make it handle the possibly big ins->inst_offset */
2939 gboolean swap = FALSE;
2943 /* Optimized away */
2948 /* Some fp compares require swapped operands */
2949 switch (ins->next->opcode) {
2951 ins->next->opcode = OP_FBLT;
2955 ins->next->opcode = OP_FBLT_UN;
2959 ins->next->opcode = OP_FBGE;
2963 ins->next->opcode = OP_FBGE_UN;
2971 ins->sreg1 = ins->sreg2;
2980 bb->last_ins = last_ins;
2981 bb->max_vreg = cfg->next_vreg;
2985 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2989 if (long_ins->opcode == OP_LNEG) {
2991 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
2992 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
2998 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3000 /* sreg is a float, dreg is an integer reg */
3002 ARM_FPA_FIXZ (code, dreg, sreg);
3005 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
3007 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
3008 ARM_FMRS (code, dreg, ARM_VFP_F0);
3012 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3013 else if (size == 2) {
3014 ARM_SHL_IMM (code, dreg, dreg, 16);
3015 ARM_SHR_IMM (code, dreg, dreg, 16);
3019 ARM_SHL_IMM (code, dreg, dreg, 24);
3020 ARM_SAR_IMM (code, dreg, dreg, 24);
3021 } else if (size == 2) {
3022 ARM_SHL_IMM (code, dreg, dreg, 16);
3023 ARM_SAR_IMM (code, dreg, dreg, 16);
3029 #endif /* #ifndef DISABLE_JIT */
3033 const guchar *target;
3038 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3041 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
3042 PatchData *pdata = (PatchData*)user_data;
3043 guchar *code = data;
3044 guint32 *thunks = data;
3045 guint32 *endthunks = (guint32*)(code + bsize);
3047 int difflow, diffhigh;
3049 /* always ensure a call from pdata->code can reach to the thunks without further thunks */
3050 difflow = (char*)pdata->code - (char*)thunks;
3051 diffhigh = (char*)pdata->code - (char*)endthunks;
3052 if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
3056 * The thunk is composed of 3 words:
3057 * load constant from thunks [2] into ARM_IP
3060 * Note that the LR register is already setup
3062 //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
3063 if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
3064 while (thunks < endthunks) {
3065 //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
3066 if (thunks [2] == (guint32)pdata->target) {
3067 arm_patch (pdata->code, (guchar*)thunks);
3068 mono_arch_flush_icache (pdata->code, 4);
3071 } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
3072 /* found a free slot instead: emit thunk */
3073 /* ARMREG_IP is fine to use since this can't be an IMT call
3076 code = (guchar*)thunks;
3077 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3078 if (thumb_supported)
3079 ARM_BX (code, ARMREG_IP);
3081 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3082 thunks [2] = (guint32)pdata->target;
3083 mono_arch_flush_icache ((guchar*)thunks, 12);
3085 arm_patch (pdata->code, (guchar*)thunks);
3086 mono_arch_flush_icache (pdata->code, 4);
3090 /* skip 12 bytes, the size of the thunk */
3094 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
3100 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3105 domain = mono_domain_get ();
3108 pdata.target = target;
3109 pdata.absolute = absolute;
3113 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
3116 if (pdata.found != 1) {
3117 mono_domain_lock (domain);
3118 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3121 /* this uses the first available slot */
3123 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3125 mono_domain_unlock (domain);
3128 if (pdata.found != 1) {
3130 GHashTableIter iter;
3131 MonoJitDynamicMethodInfo *ji;
3134 * This might be a dynamic method, search its code manager. We can only
3135 * use the dynamic method containing CODE, since the others might be freed later.
3139 mono_domain_lock (domain);
3140 hash = domain_jit_info (domain)->dynamic_code_hash;
3142 /* FIXME: Speed this up */
3143 g_hash_table_iter_init (&iter, hash);
3144 while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
3145 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
3146 if (pdata.found == 1)
3150 mono_domain_unlock (domain);
3152 if (pdata.found != 1)
3153 g_print ("thunk failed for %p from %p\n", target, code);
3154 g_assert (pdata.found == 1);
3158 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3160 guint32 *code32 = (void*)code;
3161 guint32 ins = *code32;
3162 guint32 prim = (ins >> 25) & 7;
3163 guint32 tval = GPOINTER_TO_UINT (target);
3165 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3166 if (prim == 5) { /* 101b */
3167 /* the diff starts 8 bytes from the branch opcode */
3168 gint diff = target - code - 8;
3170 gint tmask = 0xffffffff;
3171 if (tval & 1) { /* entering thumb mode */
3172 diff = target - 1 - code - 8;
3173 g_assert (thumb_supported);
3174 tbits = 0xf << 28; /* bl->blx bit pattern */
3175 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3176 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3180 tmask = ~(1 << 24); /* clear the link bit */
3181 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3186 if (diff <= 33554431) {
3188 ins = (ins & 0xff000000) | diff;
3190 *code32 = ins | tbits;
3194 /* diff between 0 and -33554432 */
3195 if (diff >= -33554432) {
3197 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3199 *code32 = ins | tbits;
3204 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3209 * The alternative call sequences looks like this:
3211 * ldr ip, [pc] // loads the address constant
3212 * b 1f // jumps around the constant
3213 * address constant embedded in the code
3218 * There are two cases for patching:
3219 * a) at the end of method emission: in this case code points to the start
3220 * of the call sequence
3221 * b) during runtime patching of the call site: in this case code points
3222 * to the mov pc, ip instruction
3224 * We have to handle also the thunk jump code sequence:
3228 * address constant // execution never reaches here
3230 if ((ins & 0x0ffffff0) == 0x12fff10) {
3231 /* Branch and exchange: the address is constructed in a reg
3232 * We can patch BX when the code sequence is the following:
3233 * ldr ip, [pc, #0] ; 0x8
3240 guint8 *emit = (guint8*)ccode;
3241 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3243 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3244 ARM_BX (emit, ARMREG_IP);
3246 /*patching from magic trampoline*/
3247 if (ins == ccode [3]) {
3248 g_assert (code32 [-4] == ccode [0]);
3249 g_assert (code32 [-3] == ccode [1]);
3250 g_assert (code32 [-1] == ccode [2]);
3251 code32 [-2] = (guint32)target;
3254 /*patching from JIT*/
3255 if (ins == ccode [0]) {
3256 g_assert (code32 [1] == ccode [1]);
3257 g_assert (code32 [3] == ccode [2]);
3258 g_assert (code32 [4] == ccode [3]);
3259 code32 [2] = (guint32)target;
3262 g_assert_not_reached ();
3263 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3271 guint8 *emit = (guint8*)ccode;
3272 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3274 ARM_BLX_REG (emit, ARMREG_IP);
3276 g_assert (code32 [-3] == ccode [0]);
3277 g_assert (code32 [-2] == ccode [1]);
3278 g_assert (code32 [0] == ccode [2]);
3280 code32 [-1] = (guint32)target;
3283 guint32 *tmp = ccode;
3284 guint8 *emit = (guint8*)tmp;
3285 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3286 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3287 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3288 ARM_BX (emit, ARMREG_IP);
3289 if (ins == ccode [2]) {
3290 g_assert_not_reached (); // should be -2 ...
3291 code32 [-1] = (guint32)target;
3294 if (ins == ccode [0]) {
3295 /* handles both thunk jump code and the far call sequence */
3296 code32 [2] = (guint32)target;
3299 g_assert_not_reached ();
3301 // g_print ("patched with 0x%08x\n", ins);
3305 arm_patch (guchar *code, const guchar *target)
3307 arm_patch_general (NULL, code, target, NULL);
3311 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3312 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3313 * to be used with the emit macros.
3314 * Return -1 otherwise.
3317 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3320 for (i = 0; i < 31; i+= 2) {
3321 res = (val << (32 - i)) | (val >> i);
3324 *rot_amount = i? 32 - i: 0;
3331 * Emits in code a sequence of instructions that load the value 'val'
3332 * into the dreg register. Uses at most 4 instructions.
3335 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3337 int imm8, rot_amount;
3339 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3340 /* skip the constant pool */
3346 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3347 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3348 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3349 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3352 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3354 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3358 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3360 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3362 if (val & 0xFF0000) {
3363 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3365 if (val & 0xFF000000) {
3366 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3368 } else if (val & 0xFF00) {
3369 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3370 if (val & 0xFF0000) {
3371 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3373 if (val & 0xFF000000) {
3374 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3376 } else if (val & 0xFF0000) {
3377 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3378 if (val & 0xFF000000) {
3379 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3382 //g_assert_not_reached ();
3388 mono_arm_thumb_supported (void)
3390 return thumb_supported;
3396 * emit_load_volatile_arguments:
3398 * Load volatile arguments from the stack to the original input registers.
3399 * Required before a tail call.
3402 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3404 MonoMethod *method = cfg->method;
3405 MonoMethodSignature *sig;
3410 /* FIXME: Generate intermediate code instead */
3412 sig = mono_method_signature (method);
3414 /* This is the opposite of the code in emit_prolog */
3418 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3420 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
3421 ArgInfo *ainfo = &cinfo->ret;
3422 inst = cfg->vret_addr;
3423 g_assert (arm_is_imm12 (inst->inst_offset));
3424 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3426 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3427 ArgInfo *ainfo = cinfo->args + i;
3428 inst = cfg->args [pos];
3430 if (cfg->verbose_level > 2)
3431 g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3432 if (inst->opcode == OP_REGVAR) {
3433 if (ainfo->storage == RegTypeGeneral)
3434 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3435 else if (ainfo->storage == RegTypeFP) {
3436 g_assert_not_reached ();
3437 } else if (ainfo->storage == RegTypeBase) {
3441 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3442 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3444 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3445 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3449 g_assert_not_reached ();
3451 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3452 switch (ainfo->size) {
3459 g_assert (arm_is_imm12 (inst->inst_offset));
3460 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3461 g_assert (arm_is_imm12 (inst->inst_offset + 4));
3462 ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3465 if (arm_is_imm12 (inst->inst_offset)) {
3466 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3468 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3469 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3473 } else if (ainfo->storage == RegTypeBaseGen) {
3476 } else if (ainfo->storage == RegTypeBase) {
3478 } else if (ainfo->storage == RegTypeFP) {
3479 g_assert_not_reached ();
3480 } else if (ainfo->storage == RegTypeStructByVal) {
3481 int doffset = inst->inst_offset;
3485 if (mono_class_from_mono_type (inst->inst_vtype))
3486 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3487 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3488 if (arm_is_imm12 (doffset)) {
3489 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3491 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3492 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3494 soffset += sizeof (gpointer);
3495 doffset += sizeof (gpointer);
3500 } else if (ainfo->storage == RegTypeStructByAddr) {
3515 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3520 guint8 *code = cfg->native_code + cfg->code_len;
3521 MonoInst *last_ins = NULL;
3522 guint last_offset = 0;
3524 int imm8, rot_amount;
3526 /* we don't align basic blocks of loops on arm */
3528 if (cfg->verbose_level > 2)
3529 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3531 cpos = bb->max_offset;
3533 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3534 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3535 //g_assert (!mono_compile_aot);
3538 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3539 /* this is not thread save, but good enough */
3540 /* fixme: howto handle overflows? */
3541 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3544 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3545 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3546 (gpointer)"mono_break");
3547 code = emit_call_seq (cfg, code);
3550 MONO_BB_FOR_EACH_INS (bb, ins) {
3551 offset = code - cfg->native_code;
3553 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3555 if (offset > (cfg->code_size - max_len - 16)) {
3556 cfg->code_size *= 2;
3557 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3558 code = cfg->native_code + offset;
3560 // if (ins->cil_code)
3561 // g_print ("cil code\n");
3562 mono_debug_record_line_number (cfg, ins, offset);
3564 switch (ins->opcode) {
3565 case OP_MEMORY_BARRIER:
3567 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
3568 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
3572 #ifdef HAVE_AEABI_READ_TP
3573 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3574 (gpointer)"__aeabi_read_tp");
3575 code = emit_call_seq (cfg, code);
3577 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3579 g_assert_not_reached ();
3583 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3584 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3587 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3588 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3590 case OP_STOREI1_MEMBASE_IMM:
3591 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3592 g_assert (arm_is_imm12 (ins->inst_offset));
3593 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3595 case OP_STOREI2_MEMBASE_IMM:
3596 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3597 g_assert (arm_is_imm8 (ins->inst_offset));
3598 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3600 case OP_STORE_MEMBASE_IMM:
3601 case OP_STOREI4_MEMBASE_IMM:
3602 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3603 g_assert (arm_is_imm12 (ins->inst_offset));
3604 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3606 case OP_STOREI1_MEMBASE_REG:
3607 g_assert (arm_is_imm12 (ins->inst_offset));
3608 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3610 case OP_STOREI2_MEMBASE_REG:
3611 g_assert (arm_is_imm8 (ins->inst_offset));
3612 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3614 case OP_STORE_MEMBASE_REG:
3615 case OP_STOREI4_MEMBASE_REG:
3616 /* this case is special, since it happens for spill code after lowering has been called */
3617 if (arm_is_imm12 (ins->inst_offset)) {
3618 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3620 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3621 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3624 case OP_STOREI1_MEMINDEX:
3625 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3627 case OP_STOREI2_MEMINDEX:
3628 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3630 case OP_STORE_MEMINDEX:
3631 case OP_STOREI4_MEMINDEX:
3632 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3635 g_assert_not_reached ();
3637 case OP_LOAD_MEMINDEX:
3638 case OP_LOADI4_MEMINDEX:
3639 case OP_LOADU4_MEMINDEX:
3640 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3642 case OP_LOADI1_MEMINDEX:
3643 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3645 case OP_LOADU1_MEMINDEX:
3646 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3648 case OP_LOADI2_MEMINDEX:
3649 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3651 case OP_LOADU2_MEMINDEX:
3652 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3654 case OP_LOAD_MEMBASE:
3655 case OP_LOADI4_MEMBASE:
3656 case OP_LOADU4_MEMBASE:
3657 /* this case is special, since it happens for spill code after lowering has been called */
3658 if (arm_is_imm12 (ins->inst_offset)) {
3659 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3661 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3662 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3665 case OP_LOADI1_MEMBASE:
3666 g_assert (arm_is_imm8 (ins->inst_offset));
3667 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3669 case OP_LOADU1_MEMBASE:
3670 g_assert (arm_is_imm12 (ins->inst_offset));
3671 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3673 case OP_LOADU2_MEMBASE:
3674 g_assert (arm_is_imm8 (ins->inst_offset));
3675 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3677 case OP_LOADI2_MEMBASE:
3678 g_assert (arm_is_imm8 (ins->inst_offset));
3679 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3681 case OP_ICONV_TO_I1:
3682 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3683 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3685 case OP_ICONV_TO_I2:
3686 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3687 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3689 case OP_ICONV_TO_U1:
3690 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3692 case OP_ICONV_TO_U2:
3693 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3694 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3698 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3700 case OP_COMPARE_IMM:
3701 case OP_ICOMPARE_IMM:
3702 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3703 g_assert (imm8 >= 0);
3704 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3708 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3709 * So instead of emitting a trap, we emit a call a C function and place a
3712 //*(int*)code = 0xef9f0001;
3715 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3716 (gpointer)"mono_break");
3717 code = emit_call_seq (cfg, code);
3719 case OP_RELAXED_NOP:
3724 case OP_DUMMY_STORE:
3725 case OP_NOT_REACHED:
3728 case OP_SEQ_POINT: {
3730 MonoInst *info_var = cfg->arch.seq_point_info_var;
3731 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3732 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
3733 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
3734 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
3736 int dreg = ARMREG_LR;
3738 if (cfg->soft_breakpoints) {
3739 g_assert (!cfg->compile_aot);
3743 * For AOT, we use one got slot per method, which will point to a
3744 * SeqPointInfo structure, containing all the information required
3745 * by the code below.
3747 if (cfg->compile_aot) {
3748 g_assert (info_var);
3749 g_assert (info_var->opcode == OP_REGOFFSET);
3750 g_assert (arm_is_imm12 (info_var->inst_offset));
3753 if (!cfg->soft_breakpoints) {
3755 * Read from the single stepping trigger page. This will cause a
3756 * SIGSEGV when single stepping is enabled.
3757 * We do this _before_ the breakpoint, so single stepping after
3758 * a breakpoint is hit will step to the next IL offset.
3760 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3763 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3764 if (cfg->soft_breakpoints) {
3765 /* Load the address of the sequence point trigger variable. */
3768 g_assert (var->opcode == OP_REGOFFSET);
3769 g_assert (arm_is_imm12 (var->inst_offset));
3770 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3772 /* Read the value and check whether it is non-zero. */
3773 ARM_LDR_IMM (code, dreg, dreg, 0);
3774 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3776 /* Load the address of the sequence point method. */
3777 var = ss_method_var;
3779 g_assert (var->opcode == OP_REGOFFSET);
3780 g_assert (arm_is_imm12 (var->inst_offset));
3781 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3783 /* Call it conditionally. */
3784 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
3786 if (cfg->compile_aot) {
3787 /* Load the trigger page addr from the variable initialized in the prolog */
3788 var = ss_trigger_page_var;
3790 g_assert (var->opcode == OP_REGOFFSET);
3791 g_assert (arm_is_imm12 (var->inst_offset));
3792 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3794 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3796 *(int*)code = (int)ss_trigger_page;
3799 ARM_LDR_IMM (code, dreg, dreg, 0);
3803 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3805 if (cfg->soft_breakpoints) {
3806 /* Load the address of the breakpoint method into ip. */
3807 var = bp_method_var;
3809 g_assert (var->opcode == OP_REGOFFSET);
3810 g_assert (arm_is_imm12 (var->inst_offset));
3811 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3814 * A placeholder for a possible breakpoint inserted by
3815 * mono_arch_set_breakpoint ().
3818 } else if (cfg->compile_aot) {
3819 guint32 offset = code - cfg->native_code;
3822 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3823 /* Add the offset */
3824 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3825 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3827 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3829 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3830 g_assert (!(val & 0xFF000000));
3831 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3832 ARM_LDR_IMM (code, dreg, dreg, 0);
3834 /* What is faster, a branch or a load ? */
3835 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3836 /* The breakpoint instruction */
3837 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3840 * A placeholder for a possible breakpoint inserted by
3841 * mono_arch_set_breakpoint ().
3843 for (i = 0; i < 4; ++i)
3850 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3853 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3857 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3860 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3861 g_assert (imm8 >= 0);
3862 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3866 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3867 g_assert (imm8 >= 0);
3868 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3872 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3873 g_assert (imm8 >= 0);
3874 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3877 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3878 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3880 case OP_IADD_OVF_UN:
3881 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3882 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3885 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3886 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3888 case OP_ISUB_OVF_UN:
3889 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3890 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3892 case OP_ADD_OVF_CARRY:
3893 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3894 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3896 case OP_ADD_OVF_UN_CARRY:
3897 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3898 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3900 case OP_SUB_OVF_CARRY:
3901 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3902 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3904 case OP_SUB_OVF_UN_CARRY:
3905 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3906 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3910 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3913 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3914 g_assert (imm8 >= 0);
3915 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3918 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3922 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3926 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3927 g_assert (imm8 >= 0);
3928 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3932 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3933 g_assert (imm8 >= 0);
3934 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3936 case OP_ARM_RSBS_IMM:
3937 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3938 g_assert (imm8 >= 0);
3939 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3941 case OP_ARM_RSC_IMM:
3942 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3943 g_assert (imm8 >= 0);
3944 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3947 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3951 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3952 g_assert (imm8 >= 0);
3953 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3961 /* crappy ARM arch doesn't have a DIV instruction */
3962 g_assert_not_reached ();
3964 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3968 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3969 g_assert (imm8 >= 0);
3970 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3973 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3977 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3978 g_assert (imm8 >= 0);
3979 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3982 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3987 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3988 else if (ins->dreg != ins->sreg1)
3989 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3992 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3997 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3998 else if (ins->dreg != ins->sreg1)
3999 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4002 case OP_ISHR_UN_IMM:
4004 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4005 else if (ins->dreg != ins->sreg1)
4006 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4009 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4012 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4015 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4018 if (ins->dreg == ins->sreg2)
4019 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4021 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4024 g_assert_not_reached ();
4027 /* FIXME: handle ovf/ sreg2 != dreg */
4028 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4029 /* FIXME: MUL doesn't set the C/O flags on ARM */
4031 case OP_IMUL_OVF_UN:
4032 /* FIXME: handle ovf/ sreg2 != dreg */
4033 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4034 /* FIXME: MUL doesn't set the C/O flags on ARM */
4037 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4040 /* Load the GOT offset */
4041 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4042 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4044 *(gpointer*)code = NULL;
4046 /* Load the value from the GOT */
4047 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4049 case OP_ICONV_TO_I4:
4050 case OP_ICONV_TO_U4:
4052 if (ins->dreg != ins->sreg1)
4053 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4056 int saved = ins->sreg2;
4057 if (ins->sreg2 == ARM_LSW_REG) {
4058 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4061 if (ins->sreg1 != ARM_LSW_REG)
4062 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4063 if (saved != ARM_MSW_REG)
4064 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4069 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4071 ARM_CPYD (code, ins->dreg, ins->sreg1);
4073 case OP_FCONV_TO_R4:
4075 ARM_FPA_MVFS (code, ins->dreg, ins->sreg1);
4077 ARM_CVTD (code, ins->dreg, ins->sreg1);
4078 ARM_CVTS (code, ins->dreg, ins->dreg);
4083 * Keep in sync with mono_arch_emit_epilog
4085 g_assert (!cfg->method->save_lmf);
4087 code = emit_load_volatile_arguments (cfg, code);
4089 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4091 if (cfg->used_int_regs)
4092 ARM_POP (code, cfg->used_int_regs);
4093 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4095 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4097 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4098 if (cfg->compile_aot) {
4099 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4101 *(gpointer*)code = NULL;
4103 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4109 /* ensure ins->sreg1 is not NULL */
4110 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4113 g_assert (cfg->sig_cookie < 128);
4114 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4115 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4124 call = (MonoCallInst*)ins;
4125 if (ins->flags & MONO_INST_HAS_METHOD)
4126 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4128 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4129 code = emit_call_seq (cfg, code);
4130 ins->flags |= MONO_INST_GC_CALLSITE;
4131 ins->backend.pc_offset = code - cfg->native_code;
4132 code = emit_move_return_value (cfg, ins, code);
4138 case OP_VOIDCALL_REG:
4140 code = emit_call_reg (code, ins->sreg1);
4141 ins->flags |= MONO_INST_GC_CALLSITE;
4142 ins->backend.pc_offset = code - cfg->native_code;
4143 code = emit_move_return_value (cfg, ins, code);
4145 case OP_FCALL_MEMBASE:
4146 case OP_LCALL_MEMBASE:
4147 case OP_VCALL_MEMBASE:
4148 case OP_VCALL2_MEMBASE:
4149 case OP_VOIDCALL_MEMBASE:
4150 case OP_CALL_MEMBASE:
4151 g_assert (arm_is_imm12 (ins->inst_offset));
4152 g_assert (ins->sreg1 != ARMREG_LR);
4153 call = (MonoCallInst*)ins;
4154 if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE) {
4155 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
4156 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4158 * We can't embed the method in the code stream in PIC code, or
4160 * Instead, we put it in V5 in code emitted by
4161 * mono_arch_emit_imt_argument (), and embed NULL here to
4162 * signal the IMT thunk that the value is in V5.
4164 if (call->dynamic_imt_arg)
4165 *((gpointer*)code) = NULL;
4167 *((gpointer*)code) = (gpointer)call->method;
4170 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4171 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4173 ins->flags |= MONO_INST_GC_CALLSITE;
4174 ins->backend.pc_offset = code - cfg->native_code;
4175 code = emit_move_return_value (cfg, ins, code);
4178 /* keep alignment */
4179 int alloca_waste = cfg->param_area;
4182 /* round the size to 8 bytes */
4183 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
4184 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
4186 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
4187 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
4188 /* memzero the area: dreg holds the size, sp is the pointer */
4189 if (ins->flags & MONO_INST_INIT) {
4190 guint8 *start_loop, *branch_to_cond;
4191 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
4192 branch_to_cond = code;
4195 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
4196 arm_patch (branch_to_cond, code);
4197 /* decrement by 4 and set flags */
4198 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
4199 ARM_B_COND (code, ARMCOND_GE, 0);
4200 arm_patch (code - 4, start_loop);
4202 ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
4207 MonoInst *var = cfg->dyn_call_var;
4209 g_assert (var->opcode == OP_REGOFFSET);
4210 g_assert (arm_is_imm12 (var->inst_offset));
4212 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
4213 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
4215 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
4217 /* Save args buffer */
4218 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4220 /* Set stack slots using R0 as scratch reg */
4221 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
4222 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4223 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
4224 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4227 /* Set argument registers */
4228 for (i = 0; i < PARAM_REGS; ++i)
4229 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
4232 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4233 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4236 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
4237 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
4238 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
4242 if (ins->sreg1 != ARMREG_R0)
4243 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4244 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4245 (gpointer)"mono_arch_throw_exception");
4246 code = emit_call_seq (cfg, code);
4250 if (ins->sreg1 != ARMREG_R0)
4251 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4252 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4253 (gpointer)"mono_arch_rethrow_exception");
4254 code = emit_call_seq (cfg, code);
4257 case OP_START_HANDLER: {
4258 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4261 /* Reserve a param area, see filter-stack.exe */
4262 if (cfg->param_area) {
4263 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4264 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4266 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4267 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4271 if (arm_is_imm12 (spvar->inst_offset)) {
4272 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4274 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4275 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
4279 case OP_ENDFILTER: {
4280 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4283 /* Free the param area */
4284 if (cfg->param_area) {
4285 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4286 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4288 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4289 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4293 if (ins->sreg1 != ARMREG_R0)
4294 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4295 if (arm_is_imm12 (spvar->inst_offset)) {
4296 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4298 g_assert (ARMREG_IP != spvar->inst_basereg);
4299 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4300 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4302 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4305 case OP_ENDFINALLY: {
4306 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4309 /* Free the param area */
4310 if (cfg->param_area) {
4311 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4312 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4314 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4315 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4319 if (arm_is_imm12 (spvar->inst_offset)) {
4320 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4322 g_assert (ARMREG_IP != spvar->inst_basereg);
4323 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4324 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4326 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4329 case OP_CALL_HANDLER:
4330 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4332 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4335 ins->inst_c0 = code - cfg->native_code;
4338 /*if (ins->inst_target_bb->native_offset) {
4340 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4342 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4347 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
4351 * In the normal case we have:
4352 * ldr pc, [pc, ins->sreg1 << 2]
4355 * ldr lr, [pc, ins->sreg1 << 2]
4357 * After follows the data.
4358 * FIXME: add aot support.
4360 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
4361 max_len += 4 * GPOINTER_TO_INT (ins->klass);
4362 if (offset + max_len > (cfg->code_size - 16)) {
4363 cfg->code_size += max_len;
4364 cfg->code_size *= 2;
4365 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4366 code = cfg->native_code + offset;
4368 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
4370 code += 4 * GPOINTER_TO_INT (ins->klass);
4374 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4375 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4379 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4380 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
4384 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4385 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
4389 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4390 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
4394 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4395 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
4397 case OP_COND_EXC_EQ:
4398 case OP_COND_EXC_NE_UN:
4399 case OP_COND_EXC_LT:
4400 case OP_COND_EXC_LT_UN:
4401 case OP_COND_EXC_GT:
4402 case OP_COND_EXC_GT_UN:
4403 case OP_COND_EXC_GE:
4404 case OP_COND_EXC_GE_UN:
4405 case OP_COND_EXC_LE:
4406 case OP_COND_EXC_LE_UN:
4407 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
4409 case OP_COND_EXC_IEQ:
4410 case OP_COND_EXC_INE_UN:
4411 case OP_COND_EXC_ILT:
4412 case OP_COND_EXC_ILT_UN:
4413 case OP_COND_EXC_IGT:
4414 case OP_COND_EXC_IGT_UN:
4415 case OP_COND_EXC_IGE:
4416 case OP_COND_EXC_IGE_UN:
4417 case OP_COND_EXC_ILE:
4418 case OP_COND_EXC_ILE_UN:
4419 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4422 case OP_COND_EXC_IC:
4423 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4425 case OP_COND_EXC_OV:
4426 case OP_COND_EXC_IOV:
4427 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4429 case OP_COND_EXC_NC:
4430 case OP_COND_EXC_INC:
4431 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4433 case OP_COND_EXC_NO:
4434 case OP_COND_EXC_INO:
4435 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4447 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4450 /* floating point opcodes */
4453 if (cfg->compile_aot) {
4454 ARM_FPA_LDFD (code, ins->dreg, ARMREG_PC, 0);
4456 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4458 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4461 /* FIXME: we can optimize the imm load by dealing with part of
4462 * the displacement in LDFD (aligning to 512).
4464 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4465 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4469 if (cfg->compile_aot) {
4470 ARM_FPA_LDFS (code, ins->dreg, ARMREG_PC, 0);
4472 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4475 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4476 ARM_FPA_LDFS (code, ins->dreg, ARMREG_LR, 0);
4479 case OP_STORER8_MEMBASE_REG:
4480 /* This is generated by the local regalloc pass which runs after the lowering pass */
4481 if (!arm_is_fpimm8 (ins->inst_offset)) {
4482 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4483 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4484 ARM_FPA_STFD (code, ins->sreg1, ARMREG_LR, 0);
4486 ARM_FPA_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4489 case OP_LOADR8_MEMBASE:
4490 /* This is generated by the local regalloc pass which runs after the lowering pass */
4491 if (!arm_is_fpimm8 (ins->inst_offset)) {
4492 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4493 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4494 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4496 ARM_FPA_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4499 case OP_STORER4_MEMBASE_REG:
4500 g_assert (arm_is_fpimm8 (ins->inst_offset));
4501 ARM_FPA_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4503 case OP_LOADR4_MEMBASE:
4504 g_assert (arm_is_fpimm8 (ins->inst_offset));
4505 ARM_FPA_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4507 case OP_ICONV_TO_R_UN: {
4509 tmpreg = ins->dreg == 0? 1: 0;
4510 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4511 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4512 ARM_B_COND (code, ARMCOND_GE, 8);
4513 /* save the temp register */
4514 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4515 ARM_FPA_STFD (code, tmpreg, ARMREG_SP, 0);
4516 ARM_FPA_LDFD (code, tmpreg, ARMREG_PC, 12);
4517 ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4518 ARM_FPA_LDFD (code, tmpreg, ARMREG_SP, 0);
4519 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4520 /* skip the constant pool */
4523 *(int*)code = 0x41f00000;
4528 * ldfltd ftemp, [pc, #8] 0x41f00000 0x00000000
4529 * adfltd fdest, fdest, ftemp
4533 case OP_ICONV_TO_R4:
4534 ARM_FPA_FLTS (code, ins->dreg, ins->sreg1);
4536 case OP_ICONV_TO_R8:
4537 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4540 #elif defined(ARM_FPU_VFP)
4543 if (cfg->compile_aot) {
4544 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4546 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4548 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4551 /* FIXME: we can optimize the imm load by dealing with part of
4552 * the displacement in LDFD (aligning to 512).
4554 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4555 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4559 if (cfg->compile_aot) {
4560 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4562 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4564 ARM_CVTS (code, ins->dreg, ins->dreg);
4566 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4567 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4568 ARM_CVTS (code, ins->dreg, ins->dreg);
4571 case OP_STORER8_MEMBASE_REG:
4572 /* This is generated by the local regalloc pass which runs after the lowering pass */
4573 if (!arm_is_fpimm8 (ins->inst_offset)) {
4574 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4575 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4576 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4578 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4581 case OP_LOADR8_MEMBASE:
4582 /* This is generated by the local regalloc pass which runs after the lowering pass */
4583 if (!arm_is_fpimm8 (ins->inst_offset)) {
4584 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4585 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4586 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4588 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4591 case OP_STORER4_MEMBASE_REG:
4592 g_assert (arm_is_fpimm8 (ins->inst_offset));
4593 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4594 ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4596 case OP_LOADR4_MEMBASE:
4597 g_assert (arm_is_fpimm8 (ins->inst_offset));
4598 ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4599 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4601 case OP_ICONV_TO_R_UN: {
4602 g_assert_not_reached ();
4605 case OP_ICONV_TO_R4:
4606 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4607 ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4608 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4610 case OP_ICONV_TO_R8:
4611 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4612 ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4616 if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4617 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4618 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4620 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4626 case OP_FCONV_TO_I1:
4627 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4629 case OP_FCONV_TO_U1:
4630 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4632 case OP_FCONV_TO_I2:
4633 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4635 case OP_FCONV_TO_U2:
4636 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4638 case OP_FCONV_TO_I4:
4640 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4642 case OP_FCONV_TO_U4:
4644 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4646 case OP_FCONV_TO_I8:
4647 case OP_FCONV_TO_U8:
4648 g_assert_not_reached ();
4649 /* Implemented as helper calls */
4651 case OP_LCONV_TO_R_UN:
4652 g_assert_not_reached ();
4653 /* Implemented as helper calls */
4655 case OP_LCONV_TO_OVF_I4_2: {
4656 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4658 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4661 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4662 high_bit_not_set = code;
4663 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4665 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4666 valid_negative = code;
4667 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4668 invalid_negative = code;
4669 ARM_B_COND (code, ARMCOND_AL, 0);
4671 arm_patch (high_bit_not_set, code);
4673 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4674 valid_positive = code;
4675 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4677 arm_patch (invalid_negative, code);
4678 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4680 arm_patch (valid_negative, code);
4681 arm_patch (valid_positive, code);
4683 if (ins->dreg != ins->sreg1)
4684 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4689 ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4692 ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4695 ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4698 ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4701 ARM_FPA_MNFD (code, ins->dreg, ins->sreg1);
4703 #elif defined(ARM_FPU_VFP)
4705 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4708 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4711 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4714 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4717 ARM_NEGD (code, ins->dreg, ins->sreg1);
4722 g_assert_not_reached ();
4726 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4727 } else if (IS_VFP) {
4728 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4734 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4735 } else if (IS_VFP) {
4736 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4739 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4740 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4744 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4746 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4749 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4750 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4754 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4755 } else if (IS_VFP) {
4756 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4759 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4760 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4761 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4766 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4767 } else if (IS_VFP) {
4768 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4771 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4772 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4777 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4778 } else if (IS_VFP) {
4779 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4782 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4783 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4784 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4786 /* ARM FPA flags table:
4787 * N Less than ARMCOND_MI
4788 * Z Equal ARMCOND_EQ
4789 * C Greater Than or Equal ARMCOND_CS
4790 * V Unordered ARMCOND_VS
4793 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4796 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4799 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4802 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4803 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4809 g_assert_not_reached ();
4813 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4815 /* FPA requires EQ even thou the docs suggests that just CS is enough */
4816 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4817 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4821 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4822 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4827 if (ins->dreg != ins->sreg1)
4828 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4829 } else if (IS_VFP) {
4830 ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4831 ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4833 *(guint32*)code = 0xffffffff;
4835 *(guint32*)code = 0x7fefffff;
4837 ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4839 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4840 ARM_CMPD (code, ins->sreg1, ins->sreg1);
4842 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4843 ARM_CPYD (code, ins->dreg, ins->sreg1);
4848 case OP_GC_LIVENESS_DEF:
4849 case OP_GC_LIVENESS_USE:
4850 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4851 ins->backend.pc_offset = code - cfg->native_code;
4853 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4854 ins->backend.pc_offset = code - cfg->native_code;
4855 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4859 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4860 g_assert_not_reached ();
4863 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4864 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4865 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4866 g_assert_not_reached ();
4872 last_offset = offset;
4875 cfg->code_len = code - cfg->native_code;
4878 #endif /* DISABLE_JIT */
4880 #ifdef HAVE_AEABI_READ_TP
4881 void __aeabi_read_tp (void);
4885 mono_arch_register_lowlevel_calls (void)
4887 /* The signature doesn't matter */
4888 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4889 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4891 #ifndef MONO_CROSS_COMPILE
4892 #ifdef HAVE_AEABI_READ_TP
4893 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4898 #define patch_lis_ori(ip,val) do {\
4899 guint16 *__lis_ori = (guint16*)(ip); \
4900 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
4901 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
4905 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4907 MonoJumpInfo *patch_info;
4908 gboolean compile_aot = !run_cctors;
4910 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4911 unsigned char *ip = patch_info->ip.i + code;
4912 const unsigned char *target;
4914 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4915 gpointer *jt = (gpointer*)(ip + 8);
4917 /* jt is the inlined jump table, 2 instructions after ip
4918 * In the normal case we store the absolute addresses,
4919 * otherwise the displacements.
4921 for (i = 0; i < patch_info->data.table->table_size; i++)
4922 jt [i] = code + (int)patch_info->data.table->table [i];
4925 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4928 switch (patch_info->type) {
4929 case MONO_PATCH_INFO_BB:
4930 case MONO_PATCH_INFO_LABEL:
4933 /* No need to patch these */
4938 switch (patch_info->type) {
4939 case MONO_PATCH_INFO_IP:
4940 g_assert_not_reached ();
4941 patch_lis_ori (ip, ip);
4943 case MONO_PATCH_INFO_METHOD_REL:
4944 g_assert_not_reached ();
4945 *((gpointer *)(ip)) = code + patch_info->data.offset;
4947 case MONO_PATCH_INFO_METHODCONST:
4948 case MONO_PATCH_INFO_CLASS:
4949 case MONO_PATCH_INFO_IMAGE:
4950 case MONO_PATCH_INFO_FIELD:
4951 case MONO_PATCH_INFO_VTABLE:
4952 case MONO_PATCH_INFO_IID:
4953 case MONO_PATCH_INFO_SFLDA:
4954 case MONO_PATCH_INFO_LDSTR:
4955 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4956 case MONO_PATCH_INFO_LDTOKEN:
4957 g_assert_not_reached ();
4958 /* from OP_AOTCONST : lis + ori */
4959 patch_lis_ori (ip, target);
4961 case MONO_PATCH_INFO_R4:
4962 case MONO_PATCH_INFO_R8:
4963 g_assert_not_reached ();
4964 *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4966 case MONO_PATCH_INFO_EXC_NAME:
4967 g_assert_not_reached ();
4968 *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4970 case MONO_PATCH_INFO_NONE:
4971 case MONO_PATCH_INFO_BB_OVF:
4972 case MONO_PATCH_INFO_EXC_OVF:
4973 /* everything is dealt with at epilog output time */
4978 arm_patch_general (domain, ip, target, dyn_code_mp);
4985 * Stack frame layout:
4987 * ------------------- fp
4988 * MonoLMF structure or saved registers
4989 * -------------------
4991 * -------------------
4993 * -------------------
4994 * optional 8 bytes for tracing
4995 * -------------------
4996 * param area size is cfg->param_area
4997 * ------------------- sp
5000 mono_arch_emit_prolog (MonoCompile *cfg)
5002 MonoMethod *method = cfg->method;
5004 MonoMethodSignature *sig;
5006 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount;
5011 int prev_sp_offset, reg_offset;
5013 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5016 sig = mono_method_signature (method);
5017 cfg->code_size = 256 + sig->param_count * 64;
5018 code = cfg->native_code = g_malloc (cfg->code_size);
5020 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
5022 alloc_size = cfg->stack_offset;
5026 if (!method->save_lmf) {
5029 * The iphone uses R7 as the frame pointer, and it points at the saved
5034 * We can't use r7 as a frame pointer since it points into the middle of
5035 * the frame, so we keep using our own frame pointer.
5036 * FIXME: Optimize this.
5039 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5040 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
5041 prev_sp_offset += 8; /* r7 and lr */
5042 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5043 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
5045 /* No need to push LR again */
5046 if (cfg->used_int_regs)
5047 ARM_PUSH (code, cfg->used_int_regs);
5049 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
5050 prev_sp_offset += 4;
5052 for (i = 0; i < 16; ++i) {
5053 if (cfg->used_int_regs & (1 << i))
5054 prev_sp_offset += 4;
5056 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5058 for (i = 0; i < 16; ++i) {
5059 if ((cfg->used_int_regs & (1 << i))) {
5060 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5061 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
5066 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5067 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5069 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5070 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5073 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
5074 ARM_PUSH (code, 0x5ff0);
5075 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
5076 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5078 for (i = 0; i < 16; ++i) {
5079 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
5080 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5084 pos += sizeof (MonoLMF) - prev_sp_offset;
5088 orig_alloc_size = alloc_size;
5089 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
5090 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
5091 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
5092 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
5095 /* the stack used in the pushed regs */
5096 if (prev_sp_offset & 4)
5098 cfg->stack_usage = alloc_size;
5100 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
5101 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5103 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
5104 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5106 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
5108 if (cfg->frame_reg != ARMREG_SP) {
5109 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
5110 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
5112 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
5113 prev_sp_offset += alloc_size;
5115 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
5116 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
5118 /* compute max_offset in order to use short forward jumps
5119 * we could skip do it on arm because the immediate displacement
5120 * for jumps is large enough, it may be useful later for constant pools
5123 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5124 MonoInst *ins = bb->code;
5125 bb->max_offset = max_offset;
5127 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5130 MONO_BB_FOR_EACH_INS (bb, ins)
5131 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5134 /* store runtime generic context */
5135 if (cfg->rgctx_var) {
5136 MonoInst *ins = cfg->rgctx_var;
5138 g_assert (ins->opcode == OP_REGOFFSET);
5140 if (arm_is_imm12 (ins->inst_offset)) {
5141 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
5143 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5144 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
5148 /* load arguments allocated to register from the stack */
5151 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
5153 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
5154 ArgInfo *ainfo = &cinfo->ret;
5155 inst = cfg->vret_addr;
5156 g_assert (arm_is_imm12 (inst->inst_offset));
5157 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5160 if (sig->call_convention == MONO_CALL_VARARG) {
5161 ArgInfo *cookie = &cinfo->sig_cookie;
5163 /* Save the sig cookie address */
5164 g_assert (cookie->storage == RegTypeBase);
5166 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
5167 g_assert (arm_is_imm12 (cfg->sig_cookie));
5168 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
5169 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5172 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5173 ArgInfo *ainfo = cinfo->args + i;
5174 inst = cfg->args [pos];
5176 if (cfg->verbose_level > 2)
5177 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
5178 if (inst->opcode == OP_REGVAR) {
5179 if (ainfo->storage == RegTypeGeneral)
5180 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
5181 else if (ainfo->storage == RegTypeFP) {
5182 g_assert_not_reached ();
5183 } else if (ainfo->storage == RegTypeBase) {
5184 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5185 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5187 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5188 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
5191 g_assert_not_reached ();
5193 if (cfg->verbose_level > 2)
5194 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5196 /* the argument should be put on the stack: FIXME handle size != word */
5197 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
5198 switch (ainfo->size) {
5200 if (arm_is_imm12 (inst->inst_offset))
5201 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5203 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5204 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5208 if (arm_is_imm8 (inst->inst_offset)) {
5209 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5211 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5212 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5216 if (arm_is_imm12 (inst->inst_offset)) {
5217 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5219 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5220 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5222 if (arm_is_imm12 (inst->inst_offset + 4)) {
5223 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
5225 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5226 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
5230 if (arm_is_imm12 (inst->inst_offset)) {
5231 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5233 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5234 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5238 } else if (ainfo->storage == RegTypeBaseGen) {
5239 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
5240 g_assert (arm_is_imm12 (inst->inst_offset));
5241 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5242 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5243 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
5244 } else if (ainfo->storage == RegTypeBase) {
5245 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5246 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5248 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
5249 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5252 switch (ainfo->size) {
5254 if (arm_is_imm8 (inst->inst_offset)) {
5255 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5257 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5258 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5262 if (arm_is_imm8 (inst->inst_offset)) {
5263 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5265 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5266 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5270 if (arm_is_imm12 (inst->inst_offset)) {
5271 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5273 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5274 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5276 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
5277 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
5279 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
5280 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5282 if (arm_is_imm12 (inst->inst_offset + 4)) {
5283 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5285 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5286 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5290 if (arm_is_imm12 (inst->inst_offset)) {
5291 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5293 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5294 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5298 } else if (ainfo->storage == RegTypeFP) {
5299 g_assert_not_reached ();
5300 } else if (ainfo->storage == RegTypeStructByVal) {
5301 int doffset = inst->inst_offset;
5305 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
5306 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
5307 if (arm_is_imm12 (doffset)) {
5308 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
5310 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
5311 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
5313 soffset += sizeof (gpointer);
5314 doffset += sizeof (gpointer);
5316 if (ainfo->vtsize) {
5317 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5318 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
5319 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
5321 } else if (ainfo->storage == RegTypeStructByAddr) {
5322 g_assert_not_reached ();
5323 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5324 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
5326 g_assert_not_reached ();
5331 if (method->save_lmf)
5332 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
5335 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5337 if (cfg->arch.seq_point_info_var) {
5338 MonoInst *ins = cfg->arch.seq_point_info_var;
5340 /* Initialize the variable from a GOT slot */
5341 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
5342 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5344 *(gpointer*)code = NULL;
5346 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
5348 g_assert (ins->opcode == OP_REGOFFSET);
5350 if (arm_is_imm12 (ins->inst_offset)) {
5351 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5353 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5354 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5358 /* Initialize ss_trigger_page_var */
5359 if (!cfg->soft_breakpoints) {
5360 MonoInst *info_var = cfg->arch.seq_point_info_var;
5361 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
5362 int dreg = ARMREG_LR;
5365 g_assert (info_var->opcode == OP_REGOFFSET);
5366 g_assert (arm_is_imm12 (info_var->inst_offset));
5368 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
5369 /* Load the trigger page addr */
5370 ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
5371 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
5375 if (cfg->arch.seq_point_read_var) {
5376 MonoInst *read_ins = cfg->arch.seq_point_read_var;
5377 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
5378 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
5380 g_assert (read_ins->opcode == OP_REGOFFSET);
5381 g_assert (arm_is_imm12 (read_ins->inst_offset));
5382 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
5383 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
5384 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
5385 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
5387 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5389 *(volatile int **)code = &ss_trigger_var;
5391 *(gpointer*)code = single_step_func_wrapper;
5393 *(gpointer*)code = breakpoint_func_wrapper;
5396 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
5397 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
5398 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
5399 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
5400 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
5401 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
5404 cfg->code_len = code - cfg->native_code;
5405 g_assert (cfg->code_len < cfg->code_size);
5412 mono_arch_emit_epilog (MonoCompile *cfg)
5414 MonoMethod *method = cfg->method;
5415 int pos, i, rot_amount;
5416 int max_epilog_size = 16 + 20*4;
5420 if (cfg->method->save_lmf)
5421 max_epilog_size += 128;
5423 if (mono_jit_trace_calls != NULL)
5424 max_epilog_size += 50;
5426 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5427 max_epilog_size += 50;
5429 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5430 cfg->code_size *= 2;
5431 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5432 cfg->stat_code_reallocs++;
5436 * Keep in sync with OP_JMP
5438 code = cfg->native_code + cfg->code_len;
5440 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5441 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5445 /* Load returned vtypes into registers if needed */
5446 cinfo = cfg->arch.cinfo;
5447 if (cinfo->ret.storage == RegTypeStructByVal) {
5448 MonoInst *ins = cfg->ret;
5450 if (arm_is_imm12 (ins->inst_offset)) {
5451 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5453 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5454 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5458 if (method->save_lmf) {
5459 int lmf_offset, reg, sp_adj, regmask;
5460 /* all but r0-r3, sp and pc */
5461 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5464 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
5466 /* This points to r4 inside MonoLMF->iregs */
5467 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5469 regmask = 0x9ff0; /* restore lr to pc */
5470 /* Skip caller saved registers not used by the method */
5471 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5472 regmask &= ~(1 << reg);
5476 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5477 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
5479 ARM_POP (code, regmask);
5481 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5482 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5484 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5485 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5489 /* Restore saved gregs */
5490 if (cfg->used_int_regs)
5491 ARM_POP (code, cfg->used_int_regs);
5492 /* Restore saved r7, restore LR to PC */
5493 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5495 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5499 cfg->code_len = code - cfg->native_code;
5501 g_assert (cfg->code_len < cfg->code_size);
5505 /* remove once throw_exception_by_name is eliminated */
5507 exception_id_by_name (const char *name)
5509 if (strcmp (name, "IndexOutOfRangeException") == 0)
5510 return MONO_EXC_INDEX_OUT_OF_RANGE;
5511 if (strcmp (name, "OverflowException") == 0)
5512 return MONO_EXC_OVERFLOW;
5513 if (strcmp (name, "ArithmeticException") == 0)
5514 return MONO_EXC_ARITHMETIC;
5515 if (strcmp (name, "DivideByZeroException") == 0)
5516 return MONO_EXC_DIVIDE_BY_ZERO;
5517 if (strcmp (name, "InvalidCastException") == 0)
5518 return MONO_EXC_INVALID_CAST;
5519 if (strcmp (name, "NullReferenceException") == 0)
5520 return MONO_EXC_NULL_REF;
5521 if (strcmp (name, "ArrayTypeMismatchException") == 0)
5522 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5523 if (strcmp (name, "ArgumentException") == 0)
5524 return MONO_EXC_ARGUMENT;
5525 g_error ("Unknown intrinsic exception %s\n", name);
5530 mono_arch_emit_exceptions (MonoCompile *cfg)
5532 MonoJumpInfo *patch_info;
5535 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5536 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5537 int max_epilog_size = 50;
5539 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5540 exc_throw_pos [i] = NULL;
5541 exc_throw_found [i] = 0;
5544 /* count the number of exception infos */
5547 * make sure we have enough space for exceptions
5549 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5550 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5551 i = exception_id_by_name (patch_info->data.target);
5552 if (!exc_throw_found [i]) {
5553 max_epilog_size += 32;
5554 exc_throw_found [i] = TRUE;
5559 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5560 cfg->code_size *= 2;
5561 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5562 cfg->stat_code_reallocs++;
5565 code = cfg->native_code + cfg->code_len;
5567 /* add code to raise exceptions */
5568 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5569 switch (patch_info->type) {
5570 case MONO_PATCH_INFO_EXC: {
5571 MonoClass *exc_class;
5572 unsigned char *ip = patch_info->ip.i + cfg->native_code;
5574 i = exception_id_by_name (patch_info->data.target);
5575 if (exc_throw_pos [i]) {
5576 arm_patch (ip, exc_throw_pos [i]);
5577 patch_info->type = MONO_PATCH_INFO_NONE;
5580 exc_throw_pos [i] = code;
5582 arm_patch (ip, code);
5584 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5585 g_assert (exc_class);
5587 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5588 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5589 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5590 patch_info->data.name = "mono_arch_throw_corlib_exception";
5591 patch_info->ip.i = code - cfg->native_code;
5593 *(guint32*)(gpointer)code = exc_class->type_token;
5603 cfg->code_len = code - cfg->native_code;
5605 g_assert (cfg->code_len < cfg->code_size);
5609 #endif /* #ifndef DISABLE_JIT */
5612 mono_arch_finish_init (void)
5614 lmf_tls_offset = mono_get_lmf_tls_offset ();
5615 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5619 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5624 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5631 mono_arch_print_tree (MonoInst *tree, int arity)
5637 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5639 return mono_get_domain_intrinsic (cfg);
5643 mono_arch_get_patch_offset (guint8 *code)
5650 mono_arch_flush_register_windows (void)
5654 #ifdef MONO_ARCH_HAVE_IMT
5659 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5661 if (cfg->compile_aot) {
5662 int method_reg = mono_alloc_ireg (cfg);
5665 call->dynamic_imt_arg = TRUE;
5668 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5670 MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5671 ins->dreg = method_reg;
5672 ins->inst_p0 = call->method;
5673 ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5674 MONO_ADD_INS (cfg->cbb, ins);
5676 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5678 } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5680 /* Always pass in a register for simplicity */
5681 call->dynamic_imt_arg = TRUE;
5683 cfg->uses_rgctx_reg = TRUE;
5686 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5689 int method_reg = mono_alloc_preg (cfg);
5691 MONO_INST_NEW (cfg, ins, OP_PCONST);
5692 ins->inst_p0 = call->method;
5693 ins->dreg = method_reg;
5694 MONO_ADD_INS (cfg->cbb, ins);
5696 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5701 #endif /* DISABLE_JIT */
5704 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5706 guint32 *code_ptr = (guint32*)code;
5711 return (MonoMethod*)regs [ARMREG_V5];
5713 /* The IMT value is stored in the code stream right after the LDC instruction. */
5714 if (!IS_LDR_PC (code_ptr [0])) {
5715 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5716 g_assert (IS_LDR_PC (code_ptr [0]));
5718 if (code_ptr [1] == 0)
5719 /* This is AOTed code, the IMT method is in V5 */
5720 return (MonoMethod*)regs [ARMREG_V5];
5722 return (MonoMethod*) code_ptr [1];
5726 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5728 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5731 #define ENABLE_WRONG_METHOD_CHECK 0
5732 #define BASE_SIZE (6 * 4)
5733 #define BSEARCH_ENTRY_SIZE (4 * 4)
5734 #define CMP_SIZE (3 * 4)
5735 #define BRANCH_SIZE (1 * 4)
5736 #define CALL_SIZE (2 * 4)
5737 #define WMC_SIZE (5 * 4)
5738 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5741 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5743 guint32 delta = DISTANCE (target, code);
5745 g_assert (delta >= 0 && delta <= 0xFFF);
5746 *target = *target | delta;
5752 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5753 gpointer fail_tramp)
5755 int size, i, extra_space = 0;
5756 arminstr_t *code, *start, *vtable_target = NULL;
5757 gboolean large_offsets = FALSE;
5758 guint32 **constant_pool_starts;
5761 constant_pool_starts = g_new0 (guint32*, count);
5763 for (i = 0; i < count; ++i) {
5764 MonoIMTCheckItem *item = imt_entries [i];
5765 if (item->is_equals) {
5766 gboolean fail_case = !item->check_target_idx && fail_tramp;
5768 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5769 item->chunk_size += 32;
5770 large_offsets = TRUE;
5773 if (item->check_target_idx || fail_case) {
5774 if (!item->compare_done || fail_case)
5775 item->chunk_size += CMP_SIZE;
5776 item->chunk_size += BRANCH_SIZE;
5778 #if ENABLE_WRONG_METHOD_CHECK
5779 item->chunk_size += WMC_SIZE;
5783 item->chunk_size += 16;
5784 large_offsets = TRUE;
5786 item->chunk_size += CALL_SIZE;
5788 item->chunk_size += BSEARCH_ENTRY_SIZE;
5789 imt_entries [item->check_target_idx]->compare_done = TRUE;
5791 size += item->chunk_size;
5795 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5798 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5800 code = mono_domain_code_reserve (domain, size);
5804 printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5805 for (i = 0; i < count; ++i) {
5806 MonoIMTCheckItem *item = imt_entries [i];
5807 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5812 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5814 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5815 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5816 vtable_target = code;
5817 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5819 if (mono_use_llvm) {
5820 /* LLVM always passes the IMT method in R5 */
5821 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5823 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5824 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5825 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5828 for (i = 0; i < count; ++i) {
5829 MonoIMTCheckItem *item = imt_entries [i];
5830 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5831 gint32 vtable_offset;
5833 item->code_target = (guint8*)code;
5835 if (item->is_equals) {
5836 gboolean fail_case = !item->check_target_idx && fail_tramp;
5838 if (item->check_target_idx || fail_case) {
5839 if (!item->compare_done || fail_case) {
5841 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5842 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5844 item->jmp_code = (guint8*)code;
5845 ARM_B_COND (code, ARMCOND_NE, 0);
5847 /*Enable the commented code to assert on wrong method*/
5848 #if ENABLE_WRONG_METHOD_CHECK
5850 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5851 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5852 ARM_B_COND (code, ARMCOND_NE, 1);
5858 if (item->has_target_code) {
5859 target_code_ins = code;
5860 /* Load target address */
5861 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5862 /* Save it to the fourth slot */
5863 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5864 /* Restore registers and branch */
5865 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5867 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5869 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5870 if (!arm_is_imm12 (vtable_offset)) {
5872 * We need to branch to a computed address but we don't have
5873 * a free register to store it, since IP must contain the
5874 * vtable address. So we push the two values to the stack, and
5875 * load them both using LDM.
5877 /* Compute target address */
5878 vtable_offset_ins = code;
5879 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5880 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5881 /* Save it to the fourth slot */
5882 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5883 /* Restore registers and branch */
5884 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5886 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5888 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5890 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5891 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5896 arm_patch (item->jmp_code, (guchar*)code);
5898 target_code_ins = code;
5899 /* Load target address */
5900 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5901 /* Save it to the fourth slot */
5902 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5903 /* Restore registers and branch */
5904 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5906 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5907 item->jmp_code = NULL;
5911 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5913 /*must emit after unconditional branch*/
5914 if (vtable_target) {
5915 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5916 item->chunk_size += 4;
5917 vtable_target = NULL;
5920 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5921 constant_pool_starts [i] = code;
5923 code += extra_space;
5927 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5928 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5930 item->jmp_code = (guint8*)code;
5931 ARM_B_COND (code, ARMCOND_GE, 0);
5936 for (i = 0; i < count; ++i) {
5937 MonoIMTCheckItem *item = imt_entries [i];
5938 if (item->jmp_code) {
5939 if (item->check_target_idx)
5940 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5942 if (i > 0 && item->is_equals) {
5944 arminstr_t *space_start = constant_pool_starts [i];
5945 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5946 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5953 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5954 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5959 g_free (constant_pool_starts);
5961 mono_arch_flush_icache ((guint8*)start, size);
5962 mono_stats.imt_thunks_size += code - start;
5964 g_assert (DISTANCE (start, code) <= size);
5971 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5973 return ctx->regs [reg];
5977 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
5979 ctx->regs [reg] = val;
5983 * mono_arch_get_trampolines:
5985 * Return a list of MonoTrampInfo structures describing arch specific trampolines
5989 mono_arch_get_trampolines (gboolean aot)
5991 return mono_arm_get_exception_trampolines (aot);
5995 * mono_arch_set_breakpoint:
5997 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
5998 * The location should contain code emitted by OP_SEQ_POINT.
6001 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6004 guint32 native_offset = ip - (guint8*)ji->code_start;
6005 MonoDebugOptions *opt = mini_get_debug_options ();
6007 if (opt->soft_breakpoints) {
6008 g_assert (!ji->from_aot);
6010 ARM_BLX_REG (code, ARMREG_LR);
6011 mono_arch_flush_icache (code - 4, 4);
6012 } else if (ji->from_aot) {
6013 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6015 g_assert (native_offset % 4 == 0);
6016 g_assert (info->bp_addrs [native_offset / 4] == 0);
6017 info->bp_addrs [native_offset / 4] = bp_trigger_page;
6019 int dreg = ARMREG_LR;
6021 /* Read from another trigger page */
6022 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
6024 *(int*)code = (int)bp_trigger_page;
6026 ARM_LDR_IMM (code, dreg, dreg, 0);
6028 mono_arch_flush_icache (code - 16, 16);
6031 /* This is currently implemented by emitting an SWI instruction, which
6032 * qemu/linux seems to convert to a SIGILL.
6034 *(int*)code = (0xef << 24) | 8;
6036 mono_arch_flush_icache (code - 4, 4);
6042 * mono_arch_clear_breakpoint:
6044 * Clear the breakpoint at IP.
6047 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6049 MonoDebugOptions *opt = mini_get_debug_options ();
6053 if (opt->soft_breakpoints) {
6054 g_assert (!ji->from_aot);
6057 mono_arch_flush_icache (code - 4, 4);
6058 } else if (ji->from_aot) {
6059 guint32 native_offset = ip - (guint8*)ji->code_start;
6060 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6062 g_assert (native_offset % 4 == 0);
6063 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
6064 info->bp_addrs [native_offset / 4] = 0;
6066 for (i = 0; i < 4; ++i)
6069 mono_arch_flush_icache (ip, code - ip);
6074 * mono_arch_start_single_stepping:
6076 * Start single stepping.
6079 mono_arch_start_single_stepping (void)
6081 if (ss_trigger_page)
6082 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6088 * mono_arch_stop_single_stepping:
6090 * Stop single stepping.
6093 mono_arch_stop_single_stepping (void)
6095 if (ss_trigger_page)
6096 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6102 #define DBG_SIGNAL SIGBUS
6104 #define DBG_SIGNAL SIGSEGV
6108 * mono_arch_is_single_step_event:
6110 * Return whenever the machine state in SIGCTX corresponds to a single
6114 mono_arch_is_single_step_event (void *info, void *sigctx)
6116 siginfo_t *sinfo = info;
6118 if (!ss_trigger_page)
6121 /* Sometimes the address is off by 4 */
6122 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
6129 * mono_arch_is_breakpoint_event:
6131 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
6134 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6136 siginfo_t *sinfo = info;
6138 if (!ss_trigger_page)
6141 if (sinfo->si_signo == DBG_SIGNAL) {
6142 /* Sometimes the address is off by 4 */
6143 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
6153 * mono_arch_skip_breakpoint:
6155 * See mini-amd64.c for docs.
6158 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6160 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6164 * mono_arch_skip_single_step:
6166 * See mini-amd64.c for docs.
6169 mono_arch_skip_single_step (MonoContext *ctx)
6171 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6175 * mono_arch_get_seq_point_info:
6177 * See mini-amd64.c for docs.
6180 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6185 // FIXME: Add a free function
6187 mono_domain_lock (domain);
6188 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
6190 mono_domain_unlock (domain);
6193 ji = mono_jit_info_table_find (domain, (char*)code);
6196 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
6198 info->ss_trigger_page = ss_trigger_page;
6199 info->bp_trigger_page = bp_trigger_page;
6201 mono_domain_lock (domain);
6202 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
6204 mono_domain_unlock (domain);
6211 * mono_arch_set_target:
6213 * Set the target architecture the JIT backend should generate code for, in the form
6214 * of a GNU target triplet. Only used in AOT mode.
6217 mono_arch_set_target (char *mtriple)
6219 /* The GNU target triple format is not very well documented */
6220 if (strstr (mtriple, "armv7")) {
6221 v6_supported = TRUE;
6222 v7_supported = TRUE;
6224 if (strstr (mtriple, "armv6")) {
6225 v6_supported = TRUE;
6227 if (strstr (mtriple, "darwin")) {
6228 v5_supported = TRUE;
6229 thumb_supported = TRUE;
6233 if (strstr (mtriple, "gnueabi"))
6234 eabi_supported = TRUE;