2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/appdomain.h>
16 #include <mono/metadata/debug-helpers.h>
17 #include <mono/utils/mono-mmap.h>
23 #include "debugger-agent.h"
25 #include "mono/arch/arm/arm-fpa-codegen.h"
26 #include "mono/arch/arm/arm-vfp-codegen.h"
28 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
29 #define HAVE_AEABI_READ_TP 1
32 #ifdef ARM_FPU_VFP_HARD
48 #ifdef MONO_ARCH_SOFT_FLOAT
49 #define IS_SOFT_FLOAT 1
51 #define IS_SOFT_FLOAT 0
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
57 void sys_icache_invalidate (void *start, size_t len);
60 static gint lmf_tls_offset = -1;
61 static gint lmf_addr_tls_offset = -1;
63 /* This mutex protects architecture specific caches */
64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
66 static CRITICAL_SECTION mini_arch_mutex;
68 static int v5_supported = 0;
69 static int v6_supported = 0;
70 static int v7_supported = 0;
71 static int thumb_supported = 0;
73 * Whenever to use the ARM EABI
75 static int eabi_supported = 0;
78 * Whenever we are on arm/darwin aka the iphone.
80 static int darwin = 0;
82 * Whenever to use the iphone ABI extensions:
83 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
84 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
85 * This is required for debugging/profiling tools to work, but it has some overhead so it should
86 * only be turned on in debug builds.
88 static int iphone_abi = 0;
91 * The FPU we are generating code for. This is NOT runtime configurable right now,
92 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
94 static MonoArmFPU arm_fpu;
98 static volatile int ss_trigger_var = 0;
100 static gpointer single_step_func_wrapper;
101 static gpointer breakpoint_func_wrapper;
104 * The code generated for sequence points reads from this location, which is
105 * made read-only when single stepping is enabled.
107 static gpointer ss_trigger_page;
109 /* Enabled breakpoints read from this trigger page */
110 static gpointer bp_trigger_page;
112 /* Structure used by the sequence points in AOTed code */
114 gpointer ss_trigger_page;
115 gpointer bp_trigger_page;
116 guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
121 * floating point support: on ARM it is a mess, there are at least 3
122 * different setups, each of which binary incompat with the other.
123 * 1) FPA: old and ugly, but unfortunately what current distros use
124 * the double binary format has the two words swapped. 8 double registers.
125 * Implemented usually by kernel emulation.
126 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
127 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
128 * 3) VFP: the new and actually sensible and useful FP support. Implemented
129 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
131 * The plan is to write the FPA support first. softfloat can be tested in a chroot.
133 int mono_exc_esp_offset = 0;
135 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
136 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
137 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
139 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
140 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
141 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
143 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
144 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) | (ARMREG_LR << 12) | ARMREG_PC)
147 /* A variant of ARM_LDR_IMM which can handle large offsets */
148 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
149 if (arm_is_imm12 ((offset))) { \
150 ARM_LDR_IMM (code, (dreg), (basereg), (offset)); \
152 g_assert ((scratch_reg) != (basereg)); \
153 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
154 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
158 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
159 if (arm_is_imm12 ((offset))) { \
160 ARM_STR_IMM (code, (dreg), (basereg), (offset)); \
162 g_assert ((scratch_reg) != (basereg)); \
163 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
164 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
168 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
171 mono_arch_regname (int reg)
173 static const char * rnames[] = {
174 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
175 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
176 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
179 if (reg >= 0 && reg < 16)
185 mono_arch_fregname (int reg)
187 static const char * rnames[] = {
188 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
189 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
190 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
191 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
192 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
193 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
196 if (reg >= 0 && reg < 32)
204 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
206 int imm8, rot_amount;
207 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
208 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
211 g_assert (dreg != sreg);
212 code = mono_arm_emit_load_imm (code, dreg, imm);
213 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
218 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
220 /* we can use r0-r3, since this is called only for incoming args on the stack */
221 if (size > sizeof (gpointer) * 4) {
223 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
224 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
225 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
226 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
227 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
228 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
229 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
230 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
231 ARM_B_COND (code, ARMCOND_NE, 0);
232 arm_patch (code - 4, start_loop);
235 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
236 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
238 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
239 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
245 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
246 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
247 doffset = soffset = 0;
249 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
250 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
256 g_assert (size == 0);
261 emit_call_reg (guint8 *code, int reg)
264 ARM_BLX_REG (code, reg);
266 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
270 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
276 emit_call_seq (MonoCompile *cfg, guint8 *code)
278 if (cfg->method->dynamic) {
279 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
281 *(gpointer*)code = NULL;
283 code = emit_call_reg (code, ARMREG_IP);
291 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
293 switch (ins->opcode) {
296 case OP_FCALL_MEMBASE:
298 if (ins->dreg != ARM_FPA_F0)
299 ARM_FPA_MVFD (code, ins->dreg, ARM_FPA_F0);
301 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
302 ARM_FMSR (code, ins->dreg, ARMREG_R0);
303 ARM_CVTS (code, ins->dreg, ins->dreg);
305 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
317 * Emit code to push an LMF structure on the LMF stack.
318 * On arm, this is intermixed with the initialization of other fields of the structure.
321 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
323 gboolean get_lmf_fast = FALSE;
326 #ifdef HAVE_AEABI_READ_TP
327 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
329 if (lmf_addr_tls_offset != -1) {
332 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
333 (gpointer)"__aeabi_read_tp");
334 code = emit_call_seq (cfg, code);
336 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
341 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
342 (gpointer)"mono_get_lmf_addr");
343 code = emit_call_seq (cfg, code);
345 /* we build the MonoLMF structure on the stack - see mini-arm.h */
346 /* lmf_offset is the offset from the previous stack pointer,
347 * alloc_size is the total stack space allocated, so the offset
348 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
349 * The pointer to the struct is put in r1 (new_lmf).
350 * ip is used as scratch
351 * The callee-saved registers are already in the MonoLMF structure
353 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
354 /* r0 is the result from mono_get_lmf_addr () */
355 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
356 /* new_lmf->previous_lmf = *lmf_addr */
357 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
358 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
359 /* *(lmf_addr) = r1 */
360 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
361 /* Skip method (only needed for trampoline LMF frames) */
362 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, sp));
363 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, fp));
364 /* save the current IP */
365 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
366 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ip));
368 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
369 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
377 * Emit code to pop an LMF structure from the LMF stack.
380 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
384 if (lmf_offset < 32) {
385 basereg = cfg->frame_reg;
390 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
393 /* ip = previous_lmf */
394 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
396 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
397 /* *(lmf_addr) = previous_lmf */
398 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
403 #endif /* #ifndef DISABLE_JIT */
406 * mono_arch_get_argument_info:
407 * @csig: a method signature
408 * @param_count: the number of parameters to consider
409 * @arg_info: an array to store the result infos
411 * Gathers information on parameters such as size, alignment and
412 * padding. arg_info should be large enought to hold param_count + 1 entries.
414 * Returns the size of the activation frame.
417 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
419 int k, frame_size = 0;
420 guint32 size, align, pad;
423 if (MONO_TYPE_ISSTRUCT (csig->ret)) {
424 frame_size += sizeof (gpointer);
428 arg_info [0].offset = offset;
431 frame_size += sizeof (gpointer);
435 arg_info [0].size = frame_size;
437 for (k = 0; k < param_count; k++) {
438 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
440 /* ignore alignment for now */
443 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
444 arg_info [k].pad = pad;
446 arg_info [k + 1].pad = 0;
447 arg_info [k + 1].size = size;
449 arg_info [k + 1].offset = offset;
453 align = MONO_ARCH_FRAME_ALIGNMENT;
454 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
455 arg_info [k].pad = pad;
460 #define MAX_ARCH_DELEGATE_PARAMS 3
463 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
465 guint8 *code, *start;
468 start = code = mono_global_codeman_reserve (12);
470 /* Replace the this argument with the target */
471 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
472 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
473 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
475 g_assert ((code - start) <= 12);
477 mono_arch_flush_icache (start, 12);
481 size = 8 + param_count * 4;
482 start = code = mono_global_codeman_reserve (size);
484 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
485 /* slide down the arguments */
486 for (i = 0; i < param_count; ++i) {
487 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
489 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
491 g_assert ((code - start) <= size);
493 mono_arch_flush_icache (start, size);
497 *code_size = code - start;
503 * mono_arch_get_delegate_invoke_impls:
505 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
509 mono_arch_get_delegate_invoke_impls (void)
516 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
517 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
519 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
520 code = get_delegate_invoke_impl (FALSE, i, &code_len);
521 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
528 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
530 guint8 *code, *start;
532 /* FIXME: Support more cases */
533 if (MONO_TYPE_ISSTRUCT (sig->ret))
537 static guint8* cached = NULL;
538 mono_mini_arch_lock ();
540 mono_mini_arch_unlock ();
545 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
547 start = get_delegate_invoke_impl (TRUE, 0, NULL);
549 mono_mini_arch_unlock ();
552 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
555 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
557 for (i = 0; i < sig->param_count; ++i)
558 if (!mono_is_regsize_var (sig->params [i]))
561 mono_mini_arch_lock ();
562 code = cache [sig->param_count];
564 mono_mini_arch_unlock ();
569 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
570 start = mono_aot_get_trampoline (name);
573 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
575 cache [sig->param_count] = start;
576 mono_mini_arch_unlock ();
584 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
586 return (gpointer)regs [ARMREG_R0];
590 * Initialize the cpu to execute managed code.
593 mono_arch_cpu_init (void)
595 #if defined(__ARM_EABI__)
596 eabi_supported = TRUE;
598 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
601 i8_align = __alignof__ (gint64);
606 create_function_wrapper (gpointer function)
608 guint8 *start, *code;
610 start = code = mono_global_codeman_reserve (96);
613 * Construct the MonoContext structure on the stack.
616 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, sizeof (MonoContext));
618 /* save ip, lr and pc into their correspodings ctx.regs slots. */
619 ARM_STR_IMM (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + sizeof (mgreg_t) * ARMREG_IP);
620 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
621 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
623 /* save r0..r10 and fp */
624 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs));
625 ARM_STM (code, ARMREG_IP, 0x0fff);
627 /* now we can update fp. */
628 ARM_MOV_REG_REG (code, ARMREG_FP, ARMREG_SP);
630 /* make ctx.esp hold the actual value of sp at the beginning of this method. */
631 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_FP, sizeof (MonoContext));
632 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, 4 * ARMREG_SP);
633 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_SP);
635 /* make ctx.eip hold the address of the call. */
636 ARM_SUB_REG_IMM8 (code, ARMREG_LR, ARMREG_LR, 4);
637 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, pc));
639 /* r0 now points to the MonoContext */
640 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_FP);
643 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
645 *(gpointer*)code = function;
647 ARM_BLX_REG (code, ARMREG_IP);
649 /* we're back; save ctx.eip and ctx.esp into the corresponding regs slots. */
650 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, pc));
651 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
652 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
654 /* make ip point to the regs array, then restore everything, including pc. */
655 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs));
656 ARM_LDM (code, ARMREG_IP, 0xffff);
658 mono_arch_flush_icache (start, code - start);
664 * Initialize architecture specific code.
667 mono_arch_init (void)
669 InitializeCriticalSection (&mini_arch_mutex);
671 if (mini_get_debug_options ()->soft_breakpoints) {
672 single_step_func_wrapper = create_function_wrapper (debugger_agent_single_step_from_context);
673 breakpoint_func_wrapper = create_function_wrapper (debugger_agent_breakpoint_from_context);
675 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
676 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
677 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
680 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
681 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
682 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
685 arm_fpu = MONO_ARM_FPU_FPA;
686 #elif defined(ARM_FPU_VFP_HARD)
687 arm_fpu = MONO_ARM_FPU_VFP_HARD;
688 #elif defined(ARM_FPU_VFP)
689 arm_fpu = MONO_ARM_FPU_VFP;
691 arm_fpu = MONO_ARM_FPU_NONE;
696 * Cleanup architecture specific code.
699 mono_arch_cleanup (void)
704 * This function returns the optimizations supported on this cpu.
707 mono_arch_cpu_optimizations (guint32 *exclude_mask)
710 const char *cpu_arch = getenv ("MONO_CPU_ARCH");
711 if (cpu_arch != NULL) {
712 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
713 if (strncmp (cpu_arch, "armv", 4) == 0) {
714 v5_supported = cpu_arch [4] >= '5';
715 v6_supported = cpu_arch [4] >= '6';
716 v7_supported = cpu_arch [4] >= '7';
720 thumb_supported = TRUE;
727 FILE *file = fopen ("/proc/cpuinfo", "r");
729 while ((line = fgets (buf, 512, file))) {
730 if (strncmp (line, "Processor", 9) == 0) {
731 char *ver = strstr (line, "(v");
732 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
734 if (ver && (ver [2] == '6' || ver [2] == '7'))
736 if (ver && (ver [2] == '7'))
740 if (strncmp (line, "Features", 8) == 0) {
741 char *th = strstr (line, "thumb");
743 thumb_supported = TRUE;
751 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
756 /* no arm-specific optimizations yet */
762 * This function test for all SIMD functions supported.
764 * Returns a bitmask corresponding to all supported versions.
768 mono_arch_cpu_enumerate_simd_versions (void)
770 /* SIMD is currently unimplemented */
778 is_regsize_var (MonoType *t) {
781 t = mini_type_get_underlying_type (NULL, t);
788 case MONO_TYPE_FNPTR:
790 case MONO_TYPE_OBJECT:
791 case MONO_TYPE_STRING:
792 case MONO_TYPE_CLASS:
793 case MONO_TYPE_SZARRAY:
794 case MONO_TYPE_ARRAY:
796 case MONO_TYPE_GENERICINST:
797 if (!mono_type_generic_inst_is_valuetype (t))
800 case MONO_TYPE_VALUETYPE:
807 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
812 for (i = 0; i < cfg->num_varinfo; i++) {
813 MonoInst *ins = cfg->varinfo [i];
814 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
817 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
820 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
823 /* we can only allocate 32 bit values */
824 if (is_regsize_var (ins->inst_vtype)) {
825 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
826 g_assert (i == vmv->idx);
827 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
834 #define USE_EXTRA_TEMPS 0
837 mono_arch_get_global_int_regs (MonoCompile *cfg)
841 mono_arch_compute_omit_fp (cfg);
844 * FIXME: Interface calls might go through a static rgctx trampoline which
845 * sets V5, but it doesn't save it, so we need to save it ourselves, and
848 if (cfg->flags & MONO_CFG_HAS_CALLS)
849 cfg->uses_rgctx_reg = TRUE;
851 if (cfg->arch.omit_fp)
852 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
853 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
854 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
855 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
857 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
858 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
860 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
861 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
862 /* V5 is reserved for passing the vtable/rgctx/IMT method */
863 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
864 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
865 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
871 * mono_arch_regalloc_cost:
873 * Return the cost, in number of memory references, of the action of
874 * allocating the variable VMV into a register during global register
878 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
884 #endif /* #ifndef DISABLE_JIT */
886 #ifndef __GNUC_PREREQ
887 #define __GNUC_PREREQ(maj, min) (0)
891 mono_arch_flush_icache (guint8 *code, gint size)
893 #ifdef MONO_CROSS_COMPILE
895 sys_icache_invalidate (code, size);
896 #elif __GNUC_PREREQ(4, 1)
897 __clear_cache (code, code + size);
898 #elif defined(PLATFORM_ANDROID)
899 const int syscall = 0xf0002;
907 : "r" (code), "r" (code + size), "r" (syscall)
908 : "r0", "r1", "r7", "r2"
911 __asm __volatile ("mov r0, %0\n"
914 "swi 0x9f0002 @ sys_cacheflush"
916 : "r" (code), "r" (code + size), "r" (0)
917 : "r0", "r1", "r3" );
934 guint16 vtsize; /* in param area */
938 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
944 gboolean vtype_retaddr;
945 /* The index of the vret arg in the argument list */
955 /*#define __alignof__(a) sizeof(a)*/
956 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
962 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
965 if (*gr > ARMREG_R3) {
966 ainfo->offset = *stack_size;
967 ainfo->reg = ARMREG_SP; /* in the caller */
968 ainfo->storage = RegTypeBase;
971 ainfo->storage = RegTypeGeneral;
978 split = i8_align == 4;
982 if (*gr == ARMREG_R3 && split) {
983 /* first word in r3 and the second on the stack */
984 ainfo->offset = *stack_size;
985 ainfo->reg = ARMREG_SP; /* in the caller */
986 ainfo->storage = RegTypeBaseGen;
988 } else if (*gr >= ARMREG_R3) {
989 if (eabi_supported) {
990 /* darwin aligns longs to 4 byte only */
996 ainfo->offset = *stack_size;
997 ainfo->reg = ARMREG_SP; /* in the caller */
998 ainfo->storage = RegTypeBase;
1001 if (eabi_supported) {
1002 if (i8_align == 8 && ((*gr) & 1))
1005 ainfo->storage = RegTypeIRegPair;
1014 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
1016 guint i, gr, pstart;
1017 int n = sig->hasthis + sig->param_count;
1018 MonoType *simpletype;
1019 guint32 stack_size = 0;
1021 gboolean is_pinvoke = sig->pinvoke;
1024 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1026 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1031 /* FIXME: handle returning a struct */
1032 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1035 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (sig->ret), &align) <= sizeof (gpointer)) {
1036 cinfo->ret.storage = RegTypeStructByVal;
1038 cinfo->vtype_retaddr = TRUE;
1045 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1046 * the first argument, allowing 'this' to be always passed in the first arg reg.
1047 * Also do this if the first argument is a reference type, since virtual calls
1048 * are sometimes made using calli without sig->hasthis set, like in the delegate
1051 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1053 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1055 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1059 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1060 cinfo->vret_arg_index = 1;
1064 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1068 if (cinfo->vtype_retaddr)
1069 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1072 DEBUG(printf("params: %d\n", sig->param_count));
1073 for (i = pstart; i < sig->param_count; ++i) {
1074 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1075 /* Prevent implicit arguments and sig_cookie from
1076 being passed in registers */
1078 /* Emit the signature cookie just before the implicit arguments */
1079 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1081 DEBUG(printf("param %d: ", i));
1082 if (sig->params [i]->byref) {
1083 DEBUG(printf("byref\n"));
1084 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1088 simpletype = mini_type_get_underlying_type (NULL, sig->params [i]);
1089 switch (simpletype->type) {
1090 case MONO_TYPE_BOOLEAN:
1093 cinfo->args [n].size = 1;
1094 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1097 case MONO_TYPE_CHAR:
1100 cinfo->args [n].size = 2;
1101 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1106 cinfo->args [n].size = 4;
1107 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1113 case MONO_TYPE_FNPTR:
1114 case MONO_TYPE_CLASS:
1115 case MONO_TYPE_OBJECT:
1116 case MONO_TYPE_STRING:
1117 case MONO_TYPE_SZARRAY:
1118 case MONO_TYPE_ARRAY:
1120 cinfo->args [n].size = sizeof (gpointer);
1121 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1124 case MONO_TYPE_GENERICINST:
1125 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1126 cinfo->args [n].size = sizeof (gpointer);
1127 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1132 case MONO_TYPE_TYPEDBYREF:
1133 case MONO_TYPE_VALUETYPE: {
1139 if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1140 size = sizeof (MonoTypedRef);
1141 align = sizeof (gpointer);
1143 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1145 size = mono_class_native_size (klass, &align);
1147 size = mono_class_value_size (klass, &align);
1149 DEBUG(printf ("load %d bytes struct\n",
1150 mono_class_native_size (sig->params [i]->data.klass, NULL)));
1153 align_size += (sizeof (gpointer) - 1);
1154 align_size &= ~(sizeof (gpointer) - 1);
1155 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1156 cinfo->args [n].storage = RegTypeStructByVal;
1157 cinfo->args [n].struct_size = size;
1158 /* FIXME: align stack_size if needed */
1159 if (eabi_supported) {
1160 if (align >= 8 && (gr & 1))
1163 if (gr > ARMREG_R3) {
1164 cinfo->args [n].size = 0;
1165 cinfo->args [n].vtsize = nwords;
1167 int rest = ARMREG_R3 - gr + 1;
1168 int n_in_regs = rest >= nwords? nwords: rest;
1170 cinfo->args [n].size = n_in_regs;
1171 cinfo->args [n].vtsize = nwords - n_in_regs;
1172 cinfo->args [n].reg = gr;
1174 nwords -= n_in_regs;
1176 cinfo->args [n].offset = stack_size;
1177 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1178 stack_size += nwords * sizeof (gpointer);
1185 cinfo->args [n].size = 8;
1186 add_general (&gr, &stack_size, cinfo->args + n, FALSE);
1190 g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1194 /* Handle the case where there are no implicit arguments */
1195 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1196 /* Prevent implicit arguments and sig_cookie from
1197 being passed in registers */
1199 /* Emit the signature cookie just before the implicit arguments */
1200 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1204 simpletype = mini_type_get_underlying_type (NULL, sig->ret);
1205 switch (simpletype->type) {
1206 case MONO_TYPE_BOOLEAN:
1211 case MONO_TYPE_CHAR:
1217 case MONO_TYPE_FNPTR:
1218 case MONO_TYPE_CLASS:
1219 case MONO_TYPE_OBJECT:
1220 case MONO_TYPE_SZARRAY:
1221 case MONO_TYPE_ARRAY:
1222 case MONO_TYPE_STRING:
1223 cinfo->ret.storage = RegTypeGeneral;
1224 cinfo->ret.reg = ARMREG_R0;
1228 cinfo->ret.storage = RegTypeIRegPair;
1229 cinfo->ret.reg = ARMREG_R0;
1233 cinfo->ret.storage = RegTypeFP;
1234 cinfo->ret.reg = ARMREG_R0;
1235 /* FIXME: cinfo->ret.reg = ???;
1236 cinfo->ret.storage = RegTypeFP;*/
1238 case MONO_TYPE_GENERICINST:
1239 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1240 cinfo->ret.storage = RegTypeGeneral;
1241 cinfo->ret.reg = ARMREG_R0;
1245 case MONO_TYPE_VALUETYPE:
1246 case MONO_TYPE_TYPEDBYREF:
1247 if (cinfo->ret.storage != RegTypeStructByVal)
1248 cinfo->ret.storage = RegTypeStructByAddr;
1250 case MONO_TYPE_VOID:
1253 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1257 /* align stack size to 8 */
1258 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1259 stack_size = (stack_size + 7) & ~7;
1261 cinfo->stack_usage = stack_size;
1268 debug_omit_fp (void)
1271 return mono_debug_count ();
1278 * mono_arch_compute_omit_fp:
1280 * Determine whenever the frame pointer can be eliminated.
1283 mono_arch_compute_omit_fp (MonoCompile *cfg)
1285 MonoMethodSignature *sig;
1286 MonoMethodHeader *header;
1290 if (cfg->arch.omit_fp_computed)
1293 header = cfg->header;
1295 sig = mono_method_signature (cfg->method);
1297 if (!cfg->arch.cinfo)
1298 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1299 cinfo = cfg->arch.cinfo;
1302 * FIXME: Remove some of the restrictions.
1304 cfg->arch.omit_fp = TRUE;
1305 cfg->arch.omit_fp_computed = TRUE;
1307 if (cfg->disable_omit_fp)
1308 cfg->arch.omit_fp = FALSE;
1309 if (!debug_omit_fp ())
1310 cfg->arch.omit_fp = FALSE;
1312 if (cfg->method->save_lmf)
1313 cfg->arch.omit_fp = FALSE;
1315 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1316 cfg->arch.omit_fp = FALSE;
1317 if (header->num_clauses)
1318 cfg->arch.omit_fp = FALSE;
1319 if (cfg->param_area)
1320 cfg->arch.omit_fp = FALSE;
1321 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1322 cfg->arch.omit_fp = FALSE;
1323 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1324 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1325 cfg->arch.omit_fp = FALSE;
1326 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1327 ArgInfo *ainfo = &cinfo->args [i];
1329 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1331 * The stack offset can only be determined when the frame
1334 cfg->arch.omit_fp = FALSE;
1339 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1340 MonoInst *ins = cfg->varinfo [i];
1343 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1348 * Set var information according to the calling convention. arm version.
1349 * The locals var stuff should most likely be split in another method.
1352 mono_arch_allocate_vars (MonoCompile *cfg)
1354 MonoMethodSignature *sig;
1355 MonoMethodHeader *header;
1357 int i, offset, size, align, curinst;
1361 sig = mono_method_signature (cfg->method);
1363 if (!cfg->arch.cinfo)
1364 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1365 cinfo = cfg->arch.cinfo;
1367 mono_arch_compute_omit_fp (cfg);
1369 if (cfg->arch.omit_fp)
1370 cfg->frame_reg = ARMREG_SP;
1372 cfg->frame_reg = ARMREG_FP;
1374 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1376 /* allow room for the vararg method args: void* and long/double */
1377 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1378 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1380 header = cfg->header;
1382 /* See mono_arch_get_global_int_regs () */
1383 if (cfg->flags & MONO_CFG_HAS_CALLS)
1384 cfg->uses_rgctx_reg = TRUE;
1386 if (cfg->frame_reg != ARMREG_SP)
1387 cfg->used_int_regs |= 1 << cfg->frame_reg;
1389 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1390 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1391 cfg->used_int_regs |= (1 << ARMREG_V5);
1395 if (!MONO_TYPE_ISSTRUCT (sig->ret)) {
1396 switch (mini_type_get_underlying_type (NULL, sig->ret)->type) {
1397 case MONO_TYPE_VOID:
1400 cfg->ret->opcode = OP_REGVAR;
1401 cfg->ret->inst_c0 = ARMREG_R0;
1405 /* local vars are at a positive offset from the stack pointer */
1407 * also note that if the function uses alloca, we use FP
1408 * to point at the local variables.
1410 offset = 0; /* linkage area */
1411 /* align the offset to 16 bytes: not sure this is needed here */
1413 //offset &= ~(8 - 1);
1415 /* add parameter area size for called functions */
1416 offset += cfg->param_area;
1419 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1422 /* allow room to save the return value */
1423 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1426 /* the MonoLMF structure is stored just below the stack pointer */
1427 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1428 if (cinfo->ret.storage == RegTypeStructByVal) {
1429 cfg->ret->opcode = OP_REGOFFSET;
1430 cfg->ret->inst_basereg = cfg->frame_reg;
1431 offset += sizeof (gpointer) - 1;
1432 offset &= ~(sizeof (gpointer) - 1);
1433 cfg->ret->inst_offset = - offset;
1435 ins = cfg->vret_addr;
1436 offset += sizeof(gpointer) - 1;
1437 offset &= ~(sizeof(gpointer) - 1);
1438 ins->inst_offset = offset;
1439 ins->opcode = OP_REGOFFSET;
1440 ins->inst_basereg = cfg->frame_reg;
1441 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1442 printf ("vret_addr =");
1443 mono_print_ins (cfg->vret_addr);
1446 offset += sizeof(gpointer);
1449 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1450 if (cfg->arch.seq_point_info_var) {
1453 ins = cfg->arch.seq_point_info_var;
1457 offset += align - 1;
1458 offset &= ~(align - 1);
1459 ins->opcode = OP_REGOFFSET;
1460 ins->inst_basereg = cfg->frame_reg;
1461 ins->inst_offset = offset;
1464 ins = cfg->arch.ss_trigger_page_var;
1467 offset += align - 1;
1468 offset &= ~(align - 1);
1469 ins->opcode = OP_REGOFFSET;
1470 ins->inst_basereg = cfg->frame_reg;
1471 ins->inst_offset = offset;
1475 if (cfg->arch.seq_point_read_var) {
1478 ins = cfg->arch.seq_point_read_var;
1482 offset += align - 1;
1483 offset &= ~(align - 1);
1484 ins->opcode = OP_REGOFFSET;
1485 ins->inst_basereg = cfg->frame_reg;
1486 ins->inst_offset = offset;
1489 ins = cfg->arch.seq_point_ss_method_var;
1492 offset += align - 1;
1493 offset &= ~(align - 1);
1494 ins->opcode = OP_REGOFFSET;
1495 ins->inst_basereg = cfg->frame_reg;
1496 ins->inst_offset = offset;
1499 ins = cfg->arch.seq_point_bp_method_var;
1502 offset += align - 1;
1503 offset &= ~(align - 1);
1504 ins->opcode = OP_REGOFFSET;
1505 ins->inst_basereg = cfg->frame_reg;
1506 ins->inst_offset = offset;
1510 cfg->locals_min_stack_offset = offset;
1512 curinst = cfg->locals_start;
1513 for (i = curinst; i < cfg->num_varinfo; ++i) {
1514 ins = cfg->varinfo [i];
1515 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1518 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1519 * pinvoke wrappers when they call functions returning structure */
1520 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (ins->inst_vtype) && ins->inst_vtype->type != MONO_TYPE_TYPEDBYREF) {
1521 size = mono_class_native_size (mono_class_from_mono_type (ins->inst_vtype), &ualign);
1525 size = mono_type_size (ins->inst_vtype, &align);
1527 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1528 * since it loads/stores misaligned words, which don't do the right thing.
1530 if (align < 4 && size >= 4)
1532 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1533 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1534 offset += align - 1;
1535 offset &= ~(align - 1);
1536 ins->opcode = OP_REGOFFSET;
1537 ins->inst_offset = offset;
1538 ins->inst_basereg = cfg->frame_reg;
1540 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1543 cfg->locals_max_stack_offset = offset;
1547 ins = cfg->args [curinst];
1548 if (ins->opcode != OP_REGVAR) {
1549 ins->opcode = OP_REGOFFSET;
1550 ins->inst_basereg = cfg->frame_reg;
1551 offset += sizeof (gpointer) - 1;
1552 offset &= ~(sizeof (gpointer) - 1);
1553 ins->inst_offset = offset;
1554 offset += sizeof (gpointer);
1559 if (sig->call_convention == MONO_CALL_VARARG) {
1563 /* Allocate a local slot to hold the sig cookie address */
1564 offset += align - 1;
1565 offset &= ~(align - 1);
1566 cfg->sig_cookie = offset;
1570 for (i = 0; i < sig->param_count; ++i) {
1571 ins = cfg->args [curinst];
1573 if (ins->opcode != OP_REGVAR) {
1574 ins->opcode = OP_REGOFFSET;
1575 ins->inst_basereg = cfg->frame_reg;
1576 size = mini_type_stack_size_full (NULL, sig->params [i], &ualign, sig->pinvoke);
1578 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1579 * since it loads/stores misaligned words, which don't do the right thing.
1581 if (align < 4 && size >= 4)
1583 /* The code in the prolog () stores words when storing vtypes received in a register */
1584 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1586 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1587 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1588 offset += align - 1;
1589 offset &= ~(align - 1);
1590 ins->inst_offset = offset;
1596 /* align the offset to 8 bytes */
1597 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
1598 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1603 cfg->stack_offset = offset;
1607 mono_arch_create_vars (MonoCompile *cfg)
1609 MonoMethodSignature *sig;
1612 sig = mono_method_signature (cfg->method);
1614 if (!cfg->arch.cinfo)
1615 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1616 cinfo = cfg->arch.cinfo;
1618 if (cinfo->ret.storage == RegTypeStructByVal)
1619 cfg->ret_var_is_local = TRUE;
1621 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
1622 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1623 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1624 printf ("vret_addr = ");
1625 mono_print_ins (cfg->vret_addr);
1629 if (cfg->gen_seq_points) {
1630 if (cfg->soft_breakpoints) {
1631 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1632 ins->flags |= MONO_INST_VOLATILE;
1633 cfg->arch.seq_point_read_var = ins;
1635 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1636 ins->flags |= MONO_INST_VOLATILE;
1637 cfg->arch.seq_point_ss_method_var = ins;
1639 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1640 ins->flags |= MONO_INST_VOLATILE;
1641 cfg->arch.seq_point_bp_method_var = ins;
1643 g_assert (!cfg->compile_aot);
1644 } else if (cfg->compile_aot) {
1645 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1646 ins->flags |= MONO_INST_VOLATILE;
1647 cfg->arch.seq_point_info_var = ins;
1649 /* Allocate a separate variable for this to save 1 load per seq point */
1650 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1651 ins->flags |= MONO_INST_VOLATILE;
1652 cfg->arch.ss_trigger_page_var = ins;
1658 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1660 MonoMethodSignature *tmp_sig;
1663 if (call->tail_call)
1666 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1669 * mono_ArgIterator_Setup assumes the signature cookie is
1670 * passed first and all the arguments which were before it are
1671 * passed on the stack after the signature. So compensate by
1672 * passing a different signature.
1674 tmp_sig = mono_metadata_signature_dup (call->signature);
1675 tmp_sig->param_count -= call->signature->sentinelpos;
1676 tmp_sig->sentinelpos = 0;
1677 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1679 sig_reg = mono_alloc_ireg (cfg);
1680 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1682 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
1687 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1692 LLVMCallInfo *linfo;
1694 n = sig->param_count + sig->hasthis;
1696 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1698 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1701 * LLVM always uses the native ABI while we use our own ABI, the
1702 * only difference is the handling of vtypes:
1703 * - we only pass/receive them in registers in some cases, and only
1704 * in 1 or 2 integer registers.
1706 if (cinfo->vtype_retaddr) {
1707 /* Vtype returned using a hidden argument */
1708 linfo->ret.storage = LLVMArgVtypeRetAddr;
1709 linfo->vret_arg_index = cinfo->vret_arg_index;
1710 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1711 cfg->exception_message = g_strdup ("unknown ret conv");
1712 cfg->disable_llvm = TRUE;
1716 for (i = 0; i < n; ++i) {
1717 ainfo = cinfo->args + i;
1719 linfo->args [i].storage = LLVMArgNone;
1721 switch (ainfo->storage) {
1722 case RegTypeGeneral:
1723 case RegTypeIRegPair:
1725 linfo->args [i].storage = LLVMArgInIReg;
1727 case RegTypeStructByVal:
1728 // FIXME: Passing entirely on the stack or split reg/stack
1729 if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1730 linfo->args [i].storage = LLVMArgVtypeInReg;
1731 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1732 if (ainfo->size == 2)
1733 linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1735 linfo->args [i].pair_storage [1] = LLVMArgNone;
1737 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1738 cfg->disable_llvm = TRUE;
1742 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1743 cfg->disable_llvm = TRUE;
1753 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1756 MonoMethodSignature *sig;
1760 sig = call->signature;
1761 n = sig->param_count + sig->hasthis;
1763 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1765 for (i = 0; i < n; ++i) {
1766 ArgInfo *ainfo = cinfo->args + i;
1769 if (i >= sig->hasthis)
1770 t = sig->params [i - sig->hasthis];
1772 t = &mono_defaults.int_class->byval_arg;
1773 t = mini_type_get_underlying_type (NULL, t);
1775 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1776 /* Emit the signature cookie just before the implicit arguments */
1777 emit_sig_cookie (cfg, call, cinfo);
1780 in = call->args [i];
1782 switch (ainfo->storage) {
1783 case RegTypeGeneral:
1784 case RegTypeIRegPair:
1785 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1786 MONO_INST_NEW (cfg, ins, OP_MOVE);
1787 ins->dreg = mono_alloc_ireg (cfg);
1788 ins->sreg1 = in->dreg + 1;
1789 MONO_ADD_INS (cfg->cbb, ins);
1790 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1792 MONO_INST_NEW (cfg, ins, OP_MOVE);
1793 ins->dreg = mono_alloc_ireg (cfg);
1794 ins->sreg1 = in->dreg + 2;
1795 MONO_ADD_INS (cfg->cbb, ins);
1796 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1797 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1798 if (ainfo->size == 4) {
1799 if (IS_SOFT_FLOAT) {
1800 /* mono_emit_call_args () have already done the r8->r4 conversion */
1801 /* The converted value is in an int vreg */
1802 MONO_INST_NEW (cfg, ins, OP_MOVE);
1803 ins->dreg = mono_alloc_ireg (cfg);
1804 ins->sreg1 = in->dreg;
1805 MONO_ADD_INS (cfg->cbb, ins);
1806 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1810 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1811 creg = mono_alloc_ireg (cfg);
1812 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1813 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1816 if (IS_SOFT_FLOAT) {
1817 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1818 ins->dreg = mono_alloc_ireg (cfg);
1819 ins->sreg1 = in->dreg;
1820 MONO_ADD_INS (cfg->cbb, ins);
1821 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1823 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1824 ins->dreg = mono_alloc_ireg (cfg);
1825 ins->sreg1 = in->dreg;
1826 MONO_ADD_INS (cfg->cbb, ins);
1827 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1831 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1832 creg = mono_alloc_ireg (cfg);
1833 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1834 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1835 creg = mono_alloc_ireg (cfg);
1836 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1837 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1840 cfg->flags |= MONO_CFG_HAS_FPOUT;
1842 MONO_INST_NEW (cfg, ins, OP_MOVE);
1843 ins->dreg = mono_alloc_ireg (cfg);
1844 ins->sreg1 = in->dreg;
1845 MONO_ADD_INS (cfg->cbb, ins);
1847 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1850 case RegTypeStructByAddr:
1853 /* FIXME: where si the data allocated? */
1854 arg->backend.reg3 = ainfo->reg;
1855 call->used_iregs |= 1 << ainfo->reg;
1856 g_assert_not_reached ();
1859 case RegTypeStructByVal:
1860 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1861 ins->opcode = OP_OUTARG_VT;
1862 ins->sreg1 = in->dreg;
1863 ins->klass = in->klass;
1864 ins->inst_p0 = call;
1865 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1866 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1867 mono_call_inst_add_outarg_vt (cfg, call, ins);
1868 MONO_ADD_INS (cfg->cbb, ins);
1871 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1872 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1873 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1874 if (t->type == MONO_TYPE_R8) {
1875 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1878 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1880 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1883 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1886 case RegTypeBaseGen:
1887 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1888 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1889 MONO_INST_NEW (cfg, ins, OP_MOVE);
1890 ins->dreg = mono_alloc_ireg (cfg);
1891 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1892 MONO_ADD_INS (cfg->cbb, ins);
1893 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1894 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1897 /* This should work for soft-float as well */
1899 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1900 creg = mono_alloc_ireg (cfg);
1901 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1902 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1903 creg = mono_alloc_ireg (cfg);
1904 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1905 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1906 cfg->flags |= MONO_CFG_HAS_FPOUT;
1908 g_assert_not_reached ();
1915 arg->backend.reg3 = ainfo->reg;
1916 /* FP args are passed in int regs */
1917 call->used_iregs |= 1 << ainfo->reg;
1918 if (ainfo->size == 8) {
1919 arg->opcode = OP_OUTARG_R8;
1920 call->used_iregs |= 1 << (ainfo->reg + 1);
1922 arg->opcode = OP_OUTARG_R4;
1925 cfg->flags |= MONO_CFG_HAS_FPOUT;
1929 g_assert_not_reached ();
1933 /* Handle the case where there are no implicit arguments */
1934 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1935 emit_sig_cookie (cfg, call, cinfo);
1937 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1940 if (cinfo->ret.storage == RegTypeStructByVal) {
1941 /* The JIT will transform this into a normal call */
1942 call->vret_in_reg = TRUE;
1944 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1945 vtarg->sreg1 = call->vret_var->dreg;
1946 vtarg->dreg = mono_alloc_preg (cfg);
1947 MONO_ADD_INS (cfg->cbb, vtarg);
1949 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1953 call->stack_usage = cinfo->stack_usage;
1959 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1961 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1962 ArgInfo *ainfo = ins->inst_p1;
1963 int ovf_size = ainfo->vtsize;
1964 int doffset = ainfo->offset;
1965 int struct_size = ainfo->struct_size;
1966 int i, soffset, dreg, tmpreg;
1969 for (i = 0; i < ainfo->size; ++i) {
1970 dreg = mono_alloc_ireg (cfg);
1971 switch (struct_size) {
1973 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1976 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
1979 tmpreg = mono_alloc_ireg (cfg);
1980 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1981 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
1982 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
1983 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1984 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
1985 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
1986 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1989 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1992 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
1993 soffset += sizeof (gpointer);
1994 struct_size -= sizeof (gpointer);
1996 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
1998 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2002 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2004 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2007 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2010 if (COMPILE_LLVM (cfg)) {
2011 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2013 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2014 ins->sreg1 = val->dreg + 1;
2015 ins->sreg2 = val->dreg + 2;
2016 MONO_ADD_INS (cfg->cbb, ins);
2021 case MONO_ARM_FPU_NONE:
2022 if (ret->type == MONO_TYPE_R8) {
2025 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2026 ins->dreg = cfg->ret->dreg;
2027 ins->sreg1 = val->dreg;
2028 MONO_ADD_INS (cfg->cbb, ins);
2031 if (ret->type == MONO_TYPE_R4) {
2032 /* Already converted to an int in method_to_ir () */
2033 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2037 case MONO_ARM_FPU_VFP:
2038 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2041 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2042 ins->dreg = cfg->ret->dreg;
2043 ins->sreg1 = val->dreg;
2044 MONO_ADD_INS (cfg->cbb, ins);
2048 case MONO_ARM_FPU_FPA:
2049 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
2050 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2055 g_assert_not_reached ();
2059 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2062 #endif /* #ifndef DISABLE_JIT */
2065 mono_arch_is_inst_imm (gint64 imm)
2070 #define DYN_CALL_STACK_ARGS 6
2073 MonoMethodSignature *sig;
2078 mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
2084 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2088 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2091 switch (cinfo->ret.storage) {
2093 case RegTypeGeneral:
2094 case RegTypeIRegPair:
2095 case RegTypeStructByAddr:
2108 for (i = 0; i < cinfo->nargs; ++i) {
2109 switch (cinfo->args [i].storage) {
2110 case RegTypeGeneral:
2112 case RegTypeIRegPair:
2115 if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2118 case RegTypeStructByVal:
2119 if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2127 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2128 for (i = 0; i < sig->param_count; ++i) {
2129 MonoType *t = sig->params [i];
2155 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2157 ArchDynCallInfo *info;
2160 cinfo = get_call_info (NULL, NULL, sig);
2162 if (!dyn_call_supported (cinfo, sig)) {
2167 info = g_new0 (ArchDynCallInfo, 1);
2168 // FIXME: Preprocess the info to speed up start_dyn_call ()
2170 info->cinfo = cinfo;
2172 return (MonoDynCallInfo*)info;
2176 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2178 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2180 g_free (ainfo->cinfo);
2185 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2187 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2188 DynCallArgs *p = (DynCallArgs*)buf;
2189 int arg_index, greg, i, j, pindex;
2190 MonoMethodSignature *sig = dinfo->sig;
2192 g_assert (buf_len >= sizeof (DynCallArgs));
2201 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2202 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2207 if (dinfo->cinfo->vtype_retaddr)
2208 p->regs [greg ++] = (mgreg_t)ret;
2210 for (i = pindex; i < sig->param_count; i++) {
2211 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2212 gpointer *arg = args [arg_index ++];
2213 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2216 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2218 else if (ainfo->storage == RegTypeBase)
2219 slot = PARAM_REGS + (ainfo->offset / 4);
2221 g_assert_not_reached ();
2224 p->regs [slot] = (mgreg_t)*arg;
2229 case MONO_TYPE_STRING:
2230 case MONO_TYPE_CLASS:
2231 case MONO_TYPE_ARRAY:
2232 case MONO_TYPE_SZARRAY:
2233 case MONO_TYPE_OBJECT:
2237 p->regs [slot] = (mgreg_t)*arg;
2239 case MONO_TYPE_BOOLEAN:
2241 p->regs [slot] = *(guint8*)arg;
2244 p->regs [slot] = *(gint8*)arg;
2247 p->regs [slot] = *(gint16*)arg;
2250 case MONO_TYPE_CHAR:
2251 p->regs [slot] = *(guint16*)arg;
2254 p->regs [slot] = *(gint32*)arg;
2257 p->regs [slot] = *(guint32*)arg;
2261 p->regs [slot ++] = (mgreg_t)arg [0];
2262 p->regs [slot] = (mgreg_t)arg [1];
2265 p->regs [slot] = *(mgreg_t*)arg;
2268 p->regs [slot ++] = (mgreg_t)arg [0];
2269 p->regs [slot] = (mgreg_t)arg [1];
2271 case MONO_TYPE_GENERICINST:
2272 if (MONO_TYPE_IS_REFERENCE (t)) {
2273 p->regs [slot] = (mgreg_t)*arg;
2278 case MONO_TYPE_VALUETYPE:
2279 g_assert (ainfo->storage == RegTypeStructByVal);
2281 if (ainfo->size == 0)
2282 slot = PARAM_REGS + (ainfo->offset / 4);
2286 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2287 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2290 g_assert_not_reached ();
2296 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2298 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2299 MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2300 guint8 *ret = ((DynCallArgs*)buf)->ret;
2301 mgreg_t res = ((DynCallArgs*)buf)->res;
2302 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2304 switch (mono_type_get_underlying_type (sig->ret)->type) {
2305 case MONO_TYPE_VOID:
2306 *(gpointer*)ret = NULL;
2308 case MONO_TYPE_STRING:
2309 case MONO_TYPE_CLASS:
2310 case MONO_TYPE_ARRAY:
2311 case MONO_TYPE_SZARRAY:
2312 case MONO_TYPE_OBJECT:
2316 *(gpointer*)ret = (gpointer)res;
2322 case MONO_TYPE_BOOLEAN:
2323 *(guint8*)ret = res;
2326 *(gint16*)ret = res;
2329 case MONO_TYPE_CHAR:
2330 *(guint16*)ret = res;
2333 *(gint32*)ret = res;
2336 *(guint32*)ret = res;
2340 /* This handles endianness as well */
2341 ((gint32*)ret) [0] = res;
2342 ((gint32*)ret) [1] = res2;
2344 case MONO_TYPE_GENERICINST:
2345 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2346 *(gpointer*)ret = (gpointer)res;
2351 case MONO_TYPE_VALUETYPE:
2352 g_assert (ainfo->cinfo->vtype_retaddr);
2357 *(float*)ret = *(float*)&res;
2359 case MONO_TYPE_R8: {
2366 *(double*)ret = *(double*)®s;
2370 g_assert_not_reached ();
2377 * Allow tracing to work with this interface (with an optional argument)
2381 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2385 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2386 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2387 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2388 code = emit_call_reg (code, ARMREG_R2);
2401 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2404 int save_mode = SAVE_NONE;
2406 MonoMethod *method = cfg->method;
2407 int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2408 int save_offset = cfg->param_area;
2412 offset = code - cfg->native_code;
2413 /* we need about 16 instructions */
2414 if (offset > (cfg->code_size - 16 * 4)) {
2415 cfg->code_size *= 2;
2416 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2417 code = cfg->native_code + offset;
2420 case MONO_TYPE_VOID:
2421 /* special case string .ctor icall */
2422 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2423 save_mode = SAVE_ONE;
2425 save_mode = SAVE_NONE;
2429 save_mode = SAVE_TWO;
2433 save_mode = SAVE_FP;
2435 case MONO_TYPE_VALUETYPE:
2436 save_mode = SAVE_STRUCT;
2439 save_mode = SAVE_ONE;
2443 switch (save_mode) {
2445 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2446 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2447 if (enable_arguments) {
2448 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2449 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2453 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2454 if (enable_arguments) {
2455 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2459 /* FIXME: what reg? */
2460 if (enable_arguments) {
2461 /* FIXME: what reg? */
2465 if (enable_arguments) {
2466 /* FIXME: get the actual address */
2467 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2475 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2476 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2477 code = emit_call_reg (code, ARMREG_IP);
2479 switch (save_mode) {
2481 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2482 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2485 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2499 * The immediate field for cond branches is big enough for all reasonable methods
2501 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2502 if (0 && ins->inst_true_bb->native_offset) { \
2503 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2505 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2506 ARM_B_COND (code, (condcode), 0); \
2509 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2511 /* emit an exception if condition is fail
2513 * We assign the extra code used to throw the implicit exceptions
2514 * to cfg->bb_exit as far as the big branch handling is concerned
2516 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
2518 mono_add_patch_info (cfg, code - cfg->native_code, \
2519 MONO_PATCH_INFO_EXC, exc_name); \
2520 ARM_BL_COND (code, (condcode), 0); \
2523 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2526 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2531 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2533 MonoInst *ins, *n, *last_ins = NULL;
2535 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2536 switch (ins->opcode) {
2539 /* Already done by an arch-independent pass */
2541 case OP_LOAD_MEMBASE:
2542 case OP_LOADI4_MEMBASE:
2544 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2545 * OP_LOAD_MEMBASE offset(basereg), reg
2547 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2548 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2549 ins->inst_basereg == last_ins->inst_destbasereg &&
2550 ins->inst_offset == last_ins->inst_offset) {
2551 if (ins->dreg == last_ins->sreg1) {
2552 MONO_DELETE_INS (bb, ins);
2555 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2556 ins->opcode = OP_MOVE;
2557 ins->sreg1 = last_ins->sreg1;
2561 * Note: reg1 must be different from the basereg in the second load
2562 * OP_LOAD_MEMBASE offset(basereg), reg1
2563 * OP_LOAD_MEMBASE offset(basereg), reg2
2565 * OP_LOAD_MEMBASE offset(basereg), reg1
2566 * OP_MOVE reg1, reg2
2568 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2569 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2570 ins->inst_basereg != last_ins->dreg &&
2571 ins->inst_basereg == last_ins->inst_basereg &&
2572 ins->inst_offset == last_ins->inst_offset) {
2574 if (ins->dreg == last_ins->dreg) {
2575 MONO_DELETE_INS (bb, ins);
2578 ins->opcode = OP_MOVE;
2579 ins->sreg1 = last_ins->dreg;
2582 //g_assert_not_reached ();
2586 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2587 * OP_LOAD_MEMBASE offset(basereg), reg
2589 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2590 * OP_ICONST reg, imm
2592 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2593 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2594 ins->inst_basereg == last_ins->inst_destbasereg &&
2595 ins->inst_offset == last_ins->inst_offset) {
2596 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2597 ins->opcode = OP_ICONST;
2598 ins->inst_c0 = last_ins->inst_imm;
2599 g_assert_not_reached (); // check this rule
2603 case OP_LOADU1_MEMBASE:
2604 case OP_LOADI1_MEMBASE:
2605 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2606 ins->inst_basereg == last_ins->inst_destbasereg &&
2607 ins->inst_offset == last_ins->inst_offset) {
2608 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2609 ins->sreg1 = last_ins->sreg1;
2612 case OP_LOADU2_MEMBASE:
2613 case OP_LOADI2_MEMBASE:
2614 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2615 ins->inst_basereg == last_ins->inst_destbasereg &&
2616 ins->inst_offset == last_ins->inst_offset) {
2617 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2618 ins->sreg1 = last_ins->sreg1;
2622 ins->opcode = OP_MOVE;
2626 if (ins->dreg == ins->sreg1) {
2627 MONO_DELETE_INS (bb, ins);
2631 * OP_MOVE sreg, dreg
2632 * OP_MOVE dreg, sreg
2634 if (last_ins && last_ins->opcode == OP_MOVE &&
2635 ins->sreg1 == last_ins->dreg &&
2636 ins->dreg == last_ins->sreg1) {
2637 MONO_DELETE_INS (bb, ins);
2645 bb->last_ins = last_ins;
2649 * the branch_cc_table should maintain the order of these
2663 branch_cc_table [] = {
2677 #define ADD_NEW_INS(cfg,dest,op) do { \
2678 MONO_INST_NEW ((cfg), (dest), (op)); \
2679 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2683 map_to_reg_reg_op (int op)
2692 case OP_COMPARE_IMM:
2694 case OP_ICOMPARE_IMM:
2708 case OP_LOAD_MEMBASE:
2709 return OP_LOAD_MEMINDEX;
2710 case OP_LOADI4_MEMBASE:
2711 return OP_LOADI4_MEMINDEX;
2712 case OP_LOADU4_MEMBASE:
2713 return OP_LOADU4_MEMINDEX;
2714 case OP_LOADU1_MEMBASE:
2715 return OP_LOADU1_MEMINDEX;
2716 case OP_LOADI2_MEMBASE:
2717 return OP_LOADI2_MEMINDEX;
2718 case OP_LOADU2_MEMBASE:
2719 return OP_LOADU2_MEMINDEX;
2720 case OP_LOADI1_MEMBASE:
2721 return OP_LOADI1_MEMINDEX;
2722 case OP_STOREI1_MEMBASE_REG:
2723 return OP_STOREI1_MEMINDEX;
2724 case OP_STOREI2_MEMBASE_REG:
2725 return OP_STOREI2_MEMINDEX;
2726 case OP_STOREI4_MEMBASE_REG:
2727 return OP_STOREI4_MEMINDEX;
2728 case OP_STORE_MEMBASE_REG:
2729 return OP_STORE_MEMINDEX;
2730 case OP_STORER4_MEMBASE_REG:
2731 return OP_STORER4_MEMINDEX;
2732 case OP_STORER8_MEMBASE_REG:
2733 return OP_STORER8_MEMINDEX;
2734 case OP_STORE_MEMBASE_IMM:
2735 return OP_STORE_MEMBASE_REG;
2736 case OP_STOREI1_MEMBASE_IMM:
2737 return OP_STOREI1_MEMBASE_REG;
2738 case OP_STOREI2_MEMBASE_IMM:
2739 return OP_STOREI2_MEMBASE_REG;
2740 case OP_STOREI4_MEMBASE_IMM:
2741 return OP_STOREI4_MEMBASE_REG;
2743 g_assert_not_reached ();
2747 * Remove from the instruction list the instructions that can't be
2748 * represented with very simple instructions with no register
2752 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2754 MonoInst *ins, *temp, *last_ins = NULL;
2755 int rot_amount, imm8, low_imm;
2757 MONO_BB_FOR_EACH_INS (bb, ins) {
2759 switch (ins->opcode) {
2763 case OP_COMPARE_IMM:
2764 case OP_ICOMPARE_IMM:
2778 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2779 ADD_NEW_INS (cfg, temp, OP_ICONST);
2780 temp->inst_c0 = ins->inst_imm;
2781 temp->dreg = mono_alloc_ireg (cfg);
2782 ins->sreg2 = temp->dreg;
2783 ins->opcode = mono_op_imm_to_op (ins->opcode);
2785 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2791 if (ins->inst_imm == 1) {
2792 ins->opcode = OP_MOVE;
2795 if (ins->inst_imm == 0) {
2796 ins->opcode = OP_ICONST;
2800 imm8 = mono_is_power_of_two (ins->inst_imm);
2802 ins->opcode = OP_SHL_IMM;
2803 ins->inst_imm = imm8;
2806 ADD_NEW_INS (cfg, temp, OP_ICONST);
2807 temp->inst_c0 = ins->inst_imm;
2808 temp->dreg = mono_alloc_ireg (cfg);
2809 ins->sreg2 = temp->dreg;
2810 ins->opcode = OP_IMUL;
2816 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2817 /* ARM sets the C flag to 1 if there was _no_ overflow */
2818 ins->next->opcode = OP_COND_EXC_NC;
2820 case OP_LOCALLOC_IMM:
2821 ADD_NEW_INS (cfg, temp, OP_ICONST);
2822 temp->inst_c0 = ins->inst_imm;
2823 temp->dreg = mono_alloc_ireg (cfg);
2824 ins->sreg1 = temp->dreg;
2825 ins->opcode = OP_LOCALLOC;
2827 case OP_LOAD_MEMBASE:
2828 case OP_LOADI4_MEMBASE:
2829 case OP_LOADU4_MEMBASE:
2830 case OP_LOADU1_MEMBASE:
2831 /* we can do two things: load the immed in a register
2832 * and use an indexed load, or see if the immed can be
2833 * represented as an ad_imm + a load with a smaller offset
2834 * that fits. We just do the first for now, optimize later.
2836 if (arm_is_imm12 (ins->inst_offset))
2838 ADD_NEW_INS (cfg, temp, OP_ICONST);
2839 temp->inst_c0 = ins->inst_offset;
2840 temp->dreg = mono_alloc_ireg (cfg);
2841 ins->sreg2 = temp->dreg;
2842 ins->opcode = map_to_reg_reg_op (ins->opcode);
2844 case OP_LOADI2_MEMBASE:
2845 case OP_LOADU2_MEMBASE:
2846 case OP_LOADI1_MEMBASE:
2847 if (arm_is_imm8 (ins->inst_offset))
2849 ADD_NEW_INS (cfg, temp, OP_ICONST);
2850 temp->inst_c0 = ins->inst_offset;
2851 temp->dreg = mono_alloc_ireg (cfg);
2852 ins->sreg2 = temp->dreg;
2853 ins->opcode = map_to_reg_reg_op (ins->opcode);
2855 case OP_LOADR4_MEMBASE:
2856 case OP_LOADR8_MEMBASE:
2857 if (arm_is_fpimm8 (ins->inst_offset))
2859 low_imm = ins->inst_offset & 0x1ff;
2860 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2861 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2862 temp->inst_imm = ins->inst_offset & ~0x1ff;
2863 temp->sreg1 = ins->inst_basereg;
2864 temp->dreg = mono_alloc_ireg (cfg);
2865 ins->inst_basereg = temp->dreg;
2866 ins->inst_offset = low_imm;
2870 ADD_NEW_INS (cfg, temp, OP_ICONST);
2871 temp->inst_c0 = ins->inst_offset;
2872 temp->dreg = mono_alloc_ireg (cfg);
2874 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2875 add_ins->sreg1 = ins->inst_basereg;
2876 add_ins->sreg2 = temp->dreg;
2877 add_ins->dreg = mono_alloc_ireg (cfg);
2879 ins->inst_basereg = add_ins->dreg;
2880 ins->inst_offset = 0;
2883 case OP_STORE_MEMBASE_REG:
2884 case OP_STOREI4_MEMBASE_REG:
2885 case OP_STOREI1_MEMBASE_REG:
2886 if (arm_is_imm12 (ins->inst_offset))
2888 ADD_NEW_INS (cfg, temp, OP_ICONST);
2889 temp->inst_c0 = ins->inst_offset;
2890 temp->dreg = mono_alloc_ireg (cfg);
2891 ins->sreg2 = temp->dreg;
2892 ins->opcode = map_to_reg_reg_op (ins->opcode);
2894 case OP_STOREI2_MEMBASE_REG:
2895 if (arm_is_imm8 (ins->inst_offset))
2897 ADD_NEW_INS (cfg, temp, OP_ICONST);
2898 temp->inst_c0 = ins->inst_offset;
2899 temp->dreg = mono_alloc_ireg (cfg);
2900 ins->sreg2 = temp->dreg;
2901 ins->opcode = map_to_reg_reg_op (ins->opcode);
2903 case OP_STORER4_MEMBASE_REG:
2904 case OP_STORER8_MEMBASE_REG:
2905 if (arm_is_fpimm8 (ins->inst_offset))
2907 low_imm = ins->inst_offset & 0x1ff;
2908 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2909 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2910 temp->inst_imm = ins->inst_offset & ~0x1ff;
2911 temp->sreg1 = ins->inst_destbasereg;
2912 temp->dreg = mono_alloc_ireg (cfg);
2913 ins->inst_destbasereg = temp->dreg;
2914 ins->inst_offset = low_imm;
2918 ADD_NEW_INS (cfg, temp, OP_ICONST);
2919 temp->inst_c0 = ins->inst_offset;
2920 temp->dreg = mono_alloc_ireg (cfg);
2922 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2923 add_ins->sreg1 = ins->inst_destbasereg;
2924 add_ins->sreg2 = temp->dreg;
2925 add_ins->dreg = mono_alloc_ireg (cfg);
2927 ins->inst_destbasereg = add_ins->dreg;
2928 ins->inst_offset = 0;
2931 case OP_STORE_MEMBASE_IMM:
2932 case OP_STOREI1_MEMBASE_IMM:
2933 case OP_STOREI2_MEMBASE_IMM:
2934 case OP_STOREI4_MEMBASE_IMM:
2935 ADD_NEW_INS (cfg, temp, OP_ICONST);
2936 temp->inst_c0 = ins->inst_imm;
2937 temp->dreg = mono_alloc_ireg (cfg);
2938 ins->sreg1 = temp->dreg;
2939 ins->opcode = map_to_reg_reg_op (ins->opcode);
2941 goto loop_start; /* make it handle the possibly big ins->inst_offset */
2943 gboolean swap = FALSE;
2947 /* Optimized away */
2952 /* Some fp compares require swapped operands */
2953 switch (ins->next->opcode) {
2955 ins->next->opcode = OP_FBLT;
2959 ins->next->opcode = OP_FBLT_UN;
2963 ins->next->opcode = OP_FBGE;
2967 ins->next->opcode = OP_FBGE_UN;
2975 ins->sreg1 = ins->sreg2;
2984 bb->last_ins = last_ins;
2985 bb->max_vreg = cfg->next_vreg;
2989 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2993 if (long_ins->opcode == OP_LNEG) {
2995 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
2996 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3002 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3004 /* sreg is a float, dreg is an integer reg */
3006 ARM_FPA_FIXZ (code, dreg, sreg);
3009 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
3011 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
3012 ARM_FMRS (code, dreg, ARM_VFP_F0);
3016 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3017 else if (size == 2) {
3018 ARM_SHL_IMM (code, dreg, dreg, 16);
3019 ARM_SHR_IMM (code, dreg, dreg, 16);
3023 ARM_SHL_IMM (code, dreg, dreg, 24);
3024 ARM_SAR_IMM (code, dreg, dreg, 24);
3025 } else if (size == 2) {
3026 ARM_SHL_IMM (code, dreg, dreg, 16);
3027 ARM_SAR_IMM (code, dreg, dreg, 16);
3033 #endif /* #ifndef DISABLE_JIT */
3037 const guchar *target;
3042 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3045 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
3046 PatchData *pdata = (PatchData*)user_data;
3047 guchar *code = data;
3048 guint32 *thunks = data;
3049 guint32 *endthunks = (guint32*)(code + bsize);
3051 int difflow, diffhigh;
3053 /* always ensure a call from pdata->code can reach to the thunks without further thunks */
3054 difflow = (char*)pdata->code - (char*)thunks;
3055 diffhigh = (char*)pdata->code - (char*)endthunks;
3056 if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
3060 * The thunk is composed of 3 words:
3061 * load constant from thunks [2] into ARM_IP
3064 * Note that the LR register is already setup
3066 //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
3067 if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
3068 while (thunks < endthunks) {
3069 //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
3070 if (thunks [2] == (guint32)pdata->target) {
3071 arm_patch (pdata->code, (guchar*)thunks);
3072 mono_arch_flush_icache (pdata->code, 4);
3075 } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
3076 /* found a free slot instead: emit thunk */
3077 /* ARMREG_IP is fine to use since this can't be an IMT call
3080 code = (guchar*)thunks;
3081 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3082 if (thumb_supported)
3083 ARM_BX (code, ARMREG_IP);
3085 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3086 thunks [2] = (guint32)pdata->target;
3087 mono_arch_flush_icache ((guchar*)thunks, 12);
3089 arm_patch (pdata->code, (guchar*)thunks);
3090 mono_arch_flush_icache (pdata->code, 4);
3094 /* skip 12 bytes, the size of the thunk */
3098 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
3104 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3109 domain = mono_domain_get ();
3112 pdata.target = target;
3113 pdata.absolute = absolute;
3117 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
3120 if (pdata.found != 1) {
3121 mono_domain_lock (domain);
3122 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3125 /* this uses the first available slot */
3127 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3129 mono_domain_unlock (domain);
3132 if (pdata.found != 1) {
3134 GHashTableIter iter;
3135 MonoJitDynamicMethodInfo *ji;
3138 * This might be a dynamic method, search its code manager. We can only
3139 * use the dynamic method containing CODE, since the others might be freed later.
3143 mono_domain_lock (domain);
3144 hash = domain_jit_info (domain)->dynamic_code_hash;
3146 /* FIXME: Speed this up */
3147 g_hash_table_iter_init (&iter, hash);
3148 while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
3149 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
3150 if (pdata.found == 1)
3154 mono_domain_unlock (domain);
3156 if (pdata.found != 1)
3157 g_print ("thunk failed for %p from %p\n", target, code);
3158 g_assert (pdata.found == 1);
3162 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3164 guint32 *code32 = (void*)code;
3165 guint32 ins = *code32;
3166 guint32 prim = (ins >> 25) & 7;
3167 guint32 tval = GPOINTER_TO_UINT (target);
3169 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3170 if (prim == 5) { /* 101b */
3171 /* the diff starts 8 bytes from the branch opcode */
3172 gint diff = target - code - 8;
3174 gint tmask = 0xffffffff;
3175 if (tval & 1) { /* entering thumb mode */
3176 diff = target - 1 - code - 8;
3177 g_assert (thumb_supported);
3178 tbits = 0xf << 28; /* bl->blx bit pattern */
3179 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3180 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3184 tmask = ~(1 << 24); /* clear the link bit */
3185 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3190 if (diff <= 33554431) {
3192 ins = (ins & 0xff000000) | diff;
3194 *code32 = ins | tbits;
3198 /* diff between 0 and -33554432 */
3199 if (diff >= -33554432) {
3201 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3203 *code32 = ins | tbits;
3208 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3213 * The alternative call sequences looks like this:
3215 * ldr ip, [pc] // loads the address constant
3216 * b 1f // jumps around the constant
3217 * address constant embedded in the code
3222 * There are two cases for patching:
3223 * a) at the end of method emission: in this case code points to the start
3224 * of the call sequence
3225 * b) during runtime patching of the call site: in this case code points
3226 * to the mov pc, ip instruction
3228 * We have to handle also the thunk jump code sequence:
3232 * address constant // execution never reaches here
3234 if ((ins & 0x0ffffff0) == 0x12fff10) {
3235 /* Branch and exchange: the address is constructed in a reg
3236 * We can patch BX when the code sequence is the following:
3237 * ldr ip, [pc, #0] ; 0x8
3244 guint8 *emit = (guint8*)ccode;
3245 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3247 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3248 ARM_BX (emit, ARMREG_IP);
3250 /*patching from magic trampoline*/
3251 if (ins == ccode [3]) {
3252 g_assert (code32 [-4] == ccode [0]);
3253 g_assert (code32 [-3] == ccode [1]);
3254 g_assert (code32 [-1] == ccode [2]);
3255 code32 [-2] = (guint32)target;
3258 /*patching from JIT*/
3259 if (ins == ccode [0]) {
3260 g_assert (code32 [1] == ccode [1]);
3261 g_assert (code32 [3] == ccode [2]);
3262 g_assert (code32 [4] == ccode [3]);
3263 code32 [2] = (guint32)target;
3266 g_assert_not_reached ();
3267 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3275 guint8 *emit = (guint8*)ccode;
3276 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3278 ARM_BLX_REG (emit, ARMREG_IP);
3280 g_assert (code32 [-3] == ccode [0]);
3281 g_assert (code32 [-2] == ccode [1]);
3282 g_assert (code32 [0] == ccode [2]);
3284 code32 [-1] = (guint32)target;
3287 guint32 *tmp = ccode;
3288 guint8 *emit = (guint8*)tmp;
3289 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3290 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3291 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3292 ARM_BX (emit, ARMREG_IP);
3293 if (ins == ccode [2]) {
3294 g_assert_not_reached (); // should be -2 ...
3295 code32 [-1] = (guint32)target;
3298 if (ins == ccode [0]) {
3299 /* handles both thunk jump code and the far call sequence */
3300 code32 [2] = (guint32)target;
3303 g_assert_not_reached ();
3305 // g_print ("patched with 0x%08x\n", ins);
3309 arm_patch (guchar *code, const guchar *target)
3311 arm_patch_general (NULL, code, target, NULL);
3315 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3316 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3317 * to be used with the emit macros.
3318 * Return -1 otherwise.
3321 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3324 for (i = 0; i < 31; i+= 2) {
3325 res = (val << (32 - i)) | (val >> i);
3328 *rot_amount = i? 32 - i: 0;
3335 * Emits in code a sequence of instructions that load the value 'val'
3336 * into the dreg register. Uses at most 4 instructions.
3339 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3341 int imm8, rot_amount;
3343 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3344 /* skip the constant pool */
3350 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3351 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3352 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3353 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3356 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3358 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3362 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3364 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3366 if (val & 0xFF0000) {
3367 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3369 if (val & 0xFF000000) {
3370 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3372 } else if (val & 0xFF00) {
3373 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3374 if (val & 0xFF0000) {
3375 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3377 if (val & 0xFF000000) {
3378 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3380 } else if (val & 0xFF0000) {
3381 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3382 if (val & 0xFF000000) {
3383 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3386 //g_assert_not_reached ();
3392 mono_arm_thumb_supported (void)
3394 return thumb_supported;
3400 * emit_load_volatile_arguments:
3402 * Load volatile arguments from the stack to the original input registers.
3403 * Required before a tail call.
3406 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3408 MonoMethod *method = cfg->method;
3409 MonoMethodSignature *sig;
3414 /* FIXME: Generate intermediate code instead */
3416 sig = mono_method_signature (method);
3418 /* This is the opposite of the code in emit_prolog */
3422 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3424 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
3425 ArgInfo *ainfo = &cinfo->ret;
3426 inst = cfg->vret_addr;
3427 g_assert (arm_is_imm12 (inst->inst_offset));
3428 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3430 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3431 ArgInfo *ainfo = cinfo->args + i;
3432 inst = cfg->args [pos];
3434 if (cfg->verbose_level > 2)
3435 g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3436 if (inst->opcode == OP_REGVAR) {
3437 if (ainfo->storage == RegTypeGeneral)
3438 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3439 else if (ainfo->storage == RegTypeFP) {
3440 g_assert_not_reached ();
3441 } else if (ainfo->storage == RegTypeBase) {
3445 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3446 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3448 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3449 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3453 g_assert_not_reached ();
3455 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3456 switch (ainfo->size) {
3463 g_assert (arm_is_imm12 (inst->inst_offset));
3464 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3465 g_assert (arm_is_imm12 (inst->inst_offset + 4));
3466 ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3469 if (arm_is_imm12 (inst->inst_offset)) {
3470 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3472 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3473 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3477 } else if (ainfo->storage == RegTypeBaseGen) {
3480 } else if (ainfo->storage == RegTypeBase) {
3482 } else if (ainfo->storage == RegTypeFP) {
3483 g_assert_not_reached ();
3484 } else if (ainfo->storage == RegTypeStructByVal) {
3485 int doffset = inst->inst_offset;
3489 if (mono_class_from_mono_type (inst->inst_vtype))
3490 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3491 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3492 if (arm_is_imm12 (doffset)) {
3493 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3495 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3496 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3498 soffset += sizeof (gpointer);
3499 doffset += sizeof (gpointer);
3504 } else if (ainfo->storage == RegTypeStructByAddr) {
3519 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3524 guint8 *code = cfg->native_code + cfg->code_len;
3525 MonoInst *last_ins = NULL;
3526 guint last_offset = 0;
3528 int imm8, rot_amount;
3530 /* we don't align basic blocks of loops on arm */
3532 if (cfg->verbose_level > 2)
3533 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3535 cpos = bb->max_offset;
3537 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3538 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3539 //g_assert (!mono_compile_aot);
3542 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3543 /* this is not thread save, but good enough */
3544 /* fixme: howto handle overflows? */
3545 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3548 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3549 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3550 (gpointer)"mono_break");
3551 code = emit_call_seq (cfg, code);
3554 MONO_BB_FOR_EACH_INS (bb, ins) {
3555 offset = code - cfg->native_code;
3557 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3559 if (offset > (cfg->code_size - max_len - 16)) {
3560 cfg->code_size *= 2;
3561 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3562 code = cfg->native_code + offset;
3564 // if (ins->cil_code)
3565 // g_print ("cil code\n");
3566 mono_debug_record_line_number (cfg, ins, offset);
3568 switch (ins->opcode) {
3569 case OP_MEMORY_BARRIER:
3571 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
3572 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
3576 #ifdef HAVE_AEABI_READ_TP
3577 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3578 (gpointer)"__aeabi_read_tp");
3579 code = emit_call_seq (cfg, code);
3581 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3583 g_assert_not_reached ();
3587 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3588 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3591 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3592 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3594 case OP_STOREI1_MEMBASE_IMM:
3595 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3596 g_assert (arm_is_imm12 (ins->inst_offset));
3597 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3599 case OP_STOREI2_MEMBASE_IMM:
3600 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3601 g_assert (arm_is_imm8 (ins->inst_offset));
3602 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3604 case OP_STORE_MEMBASE_IMM:
3605 case OP_STOREI4_MEMBASE_IMM:
3606 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3607 g_assert (arm_is_imm12 (ins->inst_offset));
3608 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3610 case OP_STOREI1_MEMBASE_REG:
3611 g_assert (arm_is_imm12 (ins->inst_offset));
3612 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3614 case OP_STOREI2_MEMBASE_REG:
3615 g_assert (arm_is_imm8 (ins->inst_offset));
3616 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3618 case OP_STORE_MEMBASE_REG:
3619 case OP_STOREI4_MEMBASE_REG:
3620 /* this case is special, since it happens for spill code after lowering has been called */
3621 if (arm_is_imm12 (ins->inst_offset)) {
3622 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3624 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3625 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3628 case OP_STOREI1_MEMINDEX:
3629 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3631 case OP_STOREI2_MEMINDEX:
3632 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3634 case OP_STORE_MEMINDEX:
3635 case OP_STOREI4_MEMINDEX:
3636 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3639 g_assert_not_reached ();
3641 case OP_LOAD_MEMINDEX:
3642 case OP_LOADI4_MEMINDEX:
3643 case OP_LOADU4_MEMINDEX:
3644 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3646 case OP_LOADI1_MEMINDEX:
3647 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3649 case OP_LOADU1_MEMINDEX:
3650 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3652 case OP_LOADI2_MEMINDEX:
3653 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3655 case OP_LOADU2_MEMINDEX:
3656 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3658 case OP_LOAD_MEMBASE:
3659 case OP_LOADI4_MEMBASE:
3660 case OP_LOADU4_MEMBASE:
3661 /* this case is special, since it happens for spill code after lowering has been called */
3662 if (arm_is_imm12 (ins->inst_offset)) {
3663 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3665 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3666 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3669 case OP_LOADI1_MEMBASE:
3670 g_assert (arm_is_imm8 (ins->inst_offset));
3671 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3673 case OP_LOADU1_MEMBASE:
3674 g_assert (arm_is_imm12 (ins->inst_offset));
3675 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3677 case OP_LOADU2_MEMBASE:
3678 g_assert (arm_is_imm8 (ins->inst_offset));
3679 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3681 case OP_LOADI2_MEMBASE:
3682 g_assert (arm_is_imm8 (ins->inst_offset));
3683 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3685 case OP_ICONV_TO_I1:
3686 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3687 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3689 case OP_ICONV_TO_I2:
3690 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3691 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3693 case OP_ICONV_TO_U1:
3694 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3696 case OP_ICONV_TO_U2:
3697 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3698 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3702 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3704 case OP_COMPARE_IMM:
3705 case OP_ICOMPARE_IMM:
3706 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3707 g_assert (imm8 >= 0);
3708 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3712 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3713 * So instead of emitting a trap, we emit a call a C function and place a
3716 //*(int*)code = 0xef9f0001;
3719 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3720 (gpointer)"mono_break");
3721 code = emit_call_seq (cfg, code);
3723 case OP_RELAXED_NOP:
3728 case OP_DUMMY_STORE:
3729 case OP_NOT_REACHED:
3732 case OP_SEQ_POINT: {
3734 MonoInst *info_var = cfg->arch.seq_point_info_var;
3735 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3736 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
3737 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
3738 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
3740 int dreg = ARMREG_LR;
3742 if (cfg->soft_breakpoints) {
3743 g_assert (!cfg->compile_aot);
3747 * For AOT, we use one got slot per method, which will point to a
3748 * SeqPointInfo structure, containing all the information required
3749 * by the code below.
3751 if (cfg->compile_aot) {
3752 g_assert (info_var);
3753 g_assert (info_var->opcode == OP_REGOFFSET);
3754 g_assert (arm_is_imm12 (info_var->inst_offset));
3757 if (!cfg->soft_breakpoints) {
3759 * Read from the single stepping trigger page. This will cause a
3760 * SIGSEGV when single stepping is enabled.
3761 * We do this _before_ the breakpoint, so single stepping after
3762 * a breakpoint is hit will step to the next IL offset.
3764 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3767 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3768 if (cfg->soft_breakpoints) {
3769 /* Load the address of the sequence point trigger variable. */
3772 g_assert (var->opcode == OP_REGOFFSET);
3773 g_assert (arm_is_imm12 (var->inst_offset));
3774 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3776 /* Read the value and check whether it is non-zero. */
3777 ARM_LDR_IMM (code, dreg, dreg, 0);
3778 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3780 /* Load the address of the sequence point method. */
3781 var = ss_method_var;
3783 g_assert (var->opcode == OP_REGOFFSET);
3784 g_assert (arm_is_imm12 (var->inst_offset));
3785 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3787 /* Call it conditionally. */
3788 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
3790 if (cfg->compile_aot) {
3791 /* Load the trigger page addr from the variable initialized in the prolog */
3792 var = ss_trigger_page_var;
3794 g_assert (var->opcode == OP_REGOFFSET);
3795 g_assert (arm_is_imm12 (var->inst_offset));
3796 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3798 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3800 *(int*)code = (int)ss_trigger_page;
3803 ARM_LDR_IMM (code, dreg, dreg, 0);
3807 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3809 if (cfg->soft_breakpoints) {
3810 /* Load the address of the breakpoint method into ip. */
3811 var = bp_method_var;
3813 g_assert (var->opcode == OP_REGOFFSET);
3814 g_assert (arm_is_imm12 (var->inst_offset));
3815 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3818 * A placeholder for a possible breakpoint inserted by
3819 * mono_arch_set_breakpoint ().
3822 } else if (cfg->compile_aot) {
3823 guint32 offset = code - cfg->native_code;
3826 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3827 /* Add the offset */
3828 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3829 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3831 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3833 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3834 g_assert (!(val & 0xFF000000));
3835 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3836 ARM_LDR_IMM (code, dreg, dreg, 0);
3838 /* What is faster, a branch or a load ? */
3839 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3840 /* The breakpoint instruction */
3841 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3844 * A placeholder for a possible breakpoint inserted by
3845 * mono_arch_set_breakpoint ().
3847 for (i = 0; i < 4; ++i)
3854 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3857 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3861 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3864 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3865 g_assert (imm8 >= 0);
3866 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3870 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3871 g_assert (imm8 >= 0);
3872 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3876 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3877 g_assert (imm8 >= 0);
3878 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3881 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3882 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3884 case OP_IADD_OVF_UN:
3885 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3886 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3889 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3890 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3892 case OP_ISUB_OVF_UN:
3893 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3894 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3896 case OP_ADD_OVF_CARRY:
3897 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3898 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3900 case OP_ADD_OVF_UN_CARRY:
3901 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3902 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3904 case OP_SUB_OVF_CARRY:
3905 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3906 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3908 case OP_SUB_OVF_UN_CARRY:
3909 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3910 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3914 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3917 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3918 g_assert (imm8 >= 0);
3919 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3922 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3926 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3930 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3931 g_assert (imm8 >= 0);
3932 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3936 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3937 g_assert (imm8 >= 0);
3938 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3940 case OP_ARM_RSBS_IMM:
3941 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3942 g_assert (imm8 >= 0);
3943 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3945 case OP_ARM_RSC_IMM:
3946 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3947 g_assert (imm8 >= 0);
3948 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3951 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3955 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3956 g_assert (imm8 >= 0);
3957 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3965 /* crappy ARM arch doesn't have a DIV instruction */
3966 g_assert_not_reached ();
3968 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3972 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3973 g_assert (imm8 >= 0);
3974 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3977 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3981 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3982 g_assert (imm8 >= 0);
3983 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3986 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3991 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3992 else if (ins->dreg != ins->sreg1)
3993 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3996 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4001 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4002 else if (ins->dreg != ins->sreg1)
4003 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4006 case OP_ISHR_UN_IMM:
4008 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4009 else if (ins->dreg != ins->sreg1)
4010 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4013 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4016 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4019 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4022 if (ins->dreg == ins->sreg2)
4023 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4025 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4028 g_assert_not_reached ();
4031 /* FIXME: handle ovf/ sreg2 != dreg */
4032 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4033 /* FIXME: MUL doesn't set the C/O flags on ARM */
4035 case OP_IMUL_OVF_UN:
4036 /* FIXME: handle ovf/ sreg2 != dreg */
4037 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4038 /* FIXME: MUL doesn't set the C/O flags on ARM */
4041 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4044 /* Load the GOT offset */
4045 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4046 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4048 *(gpointer*)code = NULL;
4050 /* Load the value from the GOT */
4051 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4053 case OP_ICONV_TO_I4:
4054 case OP_ICONV_TO_U4:
4056 if (ins->dreg != ins->sreg1)
4057 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4060 int saved = ins->sreg2;
4061 if (ins->sreg2 == ARM_LSW_REG) {
4062 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4065 if (ins->sreg1 != ARM_LSW_REG)
4066 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4067 if (saved != ARM_MSW_REG)
4068 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4073 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4075 ARM_CPYD (code, ins->dreg, ins->sreg1);
4077 case OP_FCONV_TO_R4:
4079 ARM_FPA_MVFS (code, ins->dreg, ins->sreg1);
4081 ARM_CVTD (code, ins->dreg, ins->sreg1);
4082 ARM_CVTS (code, ins->dreg, ins->dreg);
4087 * Keep in sync with mono_arch_emit_epilog
4089 g_assert (!cfg->method->save_lmf);
4091 code = emit_load_volatile_arguments (cfg, code);
4093 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4095 if (cfg->used_int_regs)
4096 ARM_POP (code, cfg->used_int_regs);
4097 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4099 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4101 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4102 if (cfg->compile_aot) {
4103 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4105 *(gpointer*)code = NULL;
4107 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4113 /* ensure ins->sreg1 is not NULL */
4114 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4117 g_assert (cfg->sig_cookie < 128);
4118 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4119 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4128 call = (MonoCallInst*)ins;
4129 if (ins->flags & MONO_INST_HAS_METHOD)
4130 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4132 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4133 code = emit_call_seq (cfg, code);
4134 ins->flags |= MONO_INST_GC_CALLSITE;
4135 ins->backend.pc_offset = code - cfg->native_code;
4136 code = emit_move_return_value (cfg, ins, code);
4142 case OP_VOIDCALL_REG:
4144 code = emit_call_reg (code, ins->sreg1);
4145 ins->flags |= MONO_INST_GC_CALLSITE;
4146 ins->backend.pc_offset = code - cfg->native_code;
4147 code = emit_move_return_value (cfg, ins, code);
4149 case OP_FCALL_MEMBASE:
4150 case OP_LCALL_MEMBASE:
4151 case OP_VCALL_MEMBASE:
4152 case OP_VCALL2_MEMBASE:
4153 case OP_VOIDCALL_MEMBASE:
4154 case OP_CALL_MEMBASE:
4155 g_assert (arm_is_imm12 (ins->inst_offset));
4156 g_assert (ins->sreg1 != ARMREG_LR);
4157 call = (MonoCallInst*)ins;
4158 if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE) {
4159 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
4160 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4162 * We can't embed the method in the code stream in PIC code, or
4164 * Instead, we put it in V5 in code emitted by
4165 * mono_arch_emit_imt_argument (), and embed NULL here to
4166 * signal the IMT thunk that the value is in V5.
4168 if (call->dynamic_imt_arg)
4169 *((gpointer*)code) = NULL;
4171 *((gpointer*)code) = (gpointer)call->method;
4174 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4175 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4177 ins->flags |= MONO_INST_GC_CALLSITE;
4178 ins->backend.pc_offset = code - cfg->native_code;
4179 code = emit_move_return_value (cfg, ins, code);
4182 /* keep alignment */
4183 int alloca_waste = cfg->param_area;
4186 /* round the size to 8 bytes */
4187 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
4188 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
4190 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
4191 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
4192 /* memzero the area: dreg holds the size, sp is the pointer */
4193 if (ins->flags & MONO_INST_INIT) {
4194 guint8 *start_loop, *branch_to_cond;
4195 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
4196 branch_to_cond = code;
4199 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
4200 arm_patch (branch_to_cond, code);
4201 /* decrement by 4 and set flags */
4202 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
4203 ARM_B_COND (code, ARMCOND_GE, 0);
4204 arm_patch (code - 4, start_loop);
4206 ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
4211 MonoInst *var = cfg->dyn_call_var;
4213 g_assert (var->opcode == OP_REGOFFSET);
4214 g_assert (arm_is_imm12 (var->inst_offset));
4216 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
4217 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
4219 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
4221 /* Save args buffer */
4222 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4224 /* Set stack slots using R0 as scratch reg */
4225 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
4226 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4227 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
4228 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4231 /* Set argument registers */
4232 for (i = 0; i < PARAM_REGS; ++i)
4233 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
4236 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4237 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4240 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
4241 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
4242 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
4246 if (ins->sreg1 != ARMREG_R0)
4247 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4248 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4249 (gpointer)"mono_arch_throw_exception");
4250 code = emit_call_seq (cfg, code);
4254 if (ins->sreg1 != ARMREG_R0)
4255 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4256 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4257 (gpointer)"mono_arch_rethrow_exception");
4258 code = emit_call_seq (cfg, code);
4261 case OP_START_HANDLER: {
4262 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4265 /* Reserve a param area, see filter-stack.exe */
4266 if (cfg->param_area) {
4267 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4268 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4270 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4271 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4275 if (arm_is_imm12 (spvar->inst_offset)) {
4276 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4278 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4279 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
4283 case OP_ENDFILTER: {
4284 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4287 /* Free the param area */
4288 if (cfg->param_area) {
4289 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4290 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4292 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4293 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4297 if (ins->sreg1 != ARMREG_R0)
4298 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4299 if (arm_is_imm12 (spvar->inst_offset)) {
4300 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4302 g_assert (ARMREG_IP != spvar->inst_basereg);
4303 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4304 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4306 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4309 case OP_ENDFINALLY: {
4310 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4313 /* Free the param area */
4314 if (cfg->param_area) {
4315 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4316 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4318 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4319 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4323 if (arm_is_imm12 (spvar->inst_offset)) {
4324 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4326 g_assert (ARMREG_IP != spvar->inst_basereg);
4327 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4328 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4330 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4333 case OP_CALL_HANDLER:
4334 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4336 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4339 ins->inst_c0 = code - cfg->native_code;
4342 /*if (ins->inst_target_bb->native_offset) {
4344 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4346 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4351 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
4355 * In the normal case we have:
4356 * ldr pc, [pc, ins->sreg1 << 2]
4359 * ldr lr, [pc, ins->sreg1 << 2]
4361 * After follows the data.
4362 * FIXME: add aot support.
4364 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
4365 max_len += 4 * GPOINTER_TO_INT (ins->klass);
4366 if (offset + max_len > (cfg->code_size - 16)) {
4367 cfg->code_size += max_len;
4368 cfg->code_size *= 2;
4369 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4370 code = cfg->native_code + offset;
4372 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
4374 code += 4 * GPOINTER_TO_INT (ins->klass);
4378 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4379 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4383 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4384 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
4388 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4389 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
4393 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4394 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
4398 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4399 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
4401 case OP_COND_EXC_EQ:
4402 case OP_COND_EXC_NE_UN:
4403 case OP_COND_EXC_LT:
4404 case OP_COND_EXC_LT_UN:
4405 case OP_COND_EXC_GT:
4406 case OP_COND_EXC_GT_UN:
4407 case OP_COND_EXC_GE:
4408 case OP_COND_EXC_GE_UN:
4409 case OP_COND_EXC_LE:
4410 case OP_COND_EXC_LE_UN:
4411 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
4413 case OP_COND_EXC_IEQ:
4414 case OP_COND_EXC_INE_UN:
4415 case OP_COND_EXC_ILT:
4416 case OP_COND_EXC_ILT_UN:
4417 case OP_COND_EXC_IGT:
4418 case OP_COND_EXC_IGT_UN:
4419 case OP_COND_EXC_IGE:
4420 case OP_COND_EXC_IGE_UN:
4421 case OP_COND_EXC_ILE:
4422 case OP_COND_EXC_ILE_UN:
4423 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4426 case OP_COND_EXC_IC:
4427 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4429 case OP_COND_EXC_OV:
4430 case OP_COND_EXC_IOV:
4431 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4433 case OP_COND_EXC_NC:
4434 case OP_COND_EXC_INC:
4435 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4437 case OP_COND_EXC_NO:
4438 case OP_COND_EXC_INO:
4439 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4451 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4454 /* floating point opcodes */
4457 if (cfg->compile_aot) {
4458 ARM_FPA_LDFD (code, ins->dreg, ARMREG_PC, 0);
4460 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4462 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4465 /* FIXME: we can optimize the imm load by dealing with part of
4466 * the displacement in LDFD (aligning to 512).
4468 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4469 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4473 if (cfg->compile_aot) {
4474 ARM_FPA_LDFS (code, ins->dreg, ARMREG_PC, 0);
4476 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4479 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4480 ARM_FPA_LDFS (code, ins->dreg, ARMREG_LR, 0);
4483 case OP_STORER8_MEMBASE_REG:
4484 /* This is generated by the local regalloc pass which runs after the lowering pass */
4485 if (!arm_is_fpimm8 (ins->inst_offset)) {
4486 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4487 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4488 ARM_FPA_STFD (code, ins->sreg1, ARMREG_LR, 0);
4490 ARM_FPA_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4493 case OP_LOADR8_MEMBASE:
4494 /* This is generated by the local regalloc pass which runs after the lowering pass */
4495 if (!arm_is_fpimm8 (ins->inst_offset)) {
4496 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4497 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4498 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4500 ARM_FPA_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4503 case OP_STORER4_MEMBASE_REG:
4504 g_assert (arm_is_fpimm8 (ins->inst_offset));
4505 ARM_FPA_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4507 case OP_LOADR4_MEMBASE:
4508 g_assert (arm_is_fpimm8 (ins->inst_offset));
4509 ARM_FPA_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4511 case OP_ICONV_TO_R_UN: {
4513 tmpreg = ins->dreg == 0? 1: 0;
4514 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4515 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4516 ARM_B_COND (code, ARMCOND_GE, 8);
4517 /* save the temp register */
4518 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4519 ARM_FPA_STFD (code, tmpreg, ARMREG_SP, 0);
4520 ARM_FPA_LDFD (code, tmpreg, ARMREG_PC, 12);
4521 ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4522 ARM_FPA_LDFD (code, tmpreg, ARMREG_SP, 0);
4523 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4524 /* skip the constant pool */
4527 *(int*)code = 0x41f00000;
4532 * ldfltd ftemp, [pc, #8] 0x41f00000 0x00000000
4533 * adfltd fdest, fdest, ftemp
4537 case OP_ICONV_TO_R4:
4538 ARM_FPA_FLTS (code, ins->dreg, ins->sreg1);
4540 case OP_ICONV_TO_R8:
4541 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4544 #elif defined(ARM_FPU_VFP)
4547 if (cfg->compile_aot) {
4548 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4550 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4552 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4555 /* FIXME: we can optimize the imm load by dealing with part of
4556 * the displacement in LDFD (aligning to 512).
4558 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4559 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4563 if (cfg->compile_aot) {
4564 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4566 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4568 ARM_CVTS (code, ins->dreg, ins->dreg);
4570 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4571 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4572 ARM_CVTS (code, ins->dreg, ins->dreg);
4575 case OP_STORER8_MEMBASE_REG:
4576 /* This is generated by the local regalloc pass which runs after the lowering pass */
4577 if (!arm_is_fpimm8 (ins->inst_offset)) {
4578 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4579 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4580 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4582 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4585 case OP_LOADR8_MEMBASE:
4586 /* This is generated by the local regalloc pass which runs after the lowering pass */
4587 if (!arm_is_fpimm8 (ins->inst_offset)) {
4588 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4589 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4590 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4592 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4595 case OP_STORER4_MEMBASE_REG:
4596 g_assert (arm_is_fpimm8 (ins->inst_offset));
4597 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4598 ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4600 case OP_LOADR4_MEMBASE:
4601 g_assert (arm_is_fpimm8 (ins->inst_offset));
4602 ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4603 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4605 case OP_ICONV_TO_R_UN: {
4606 g_assert_not_reached ();
4609 case OP_ICONV_TO_R4:
4610 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4611 ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4612 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4614 case OP_ICONV_TO_R8:
4615 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4616 ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4620 if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4621 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4622 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4624 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4630 case OP_FCONV_TO_I1:
4631 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4633 case OP_FCONV_TO_U1:
4634 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4636 case OP_FCONV_TO_I2:
4637 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4639 case OP_FCONV_TO_U2:
4640 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4642 case OP_FCONV_TO_I4:
4644 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4646 case OP_FCONV_TO_U4:
4648 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4650 case OP_FCONV_TO_I8:
4651 case OP_FCONV_TO_U8:
4652 g_assert_not_reached ();
4653 /* Implemented as helper calls */
4655 case OP_LCONV_TO_R_UN:
4656 g_assert_not_reached ();
4657 /* Implemented as helper calls */
4659 case OP_LCONV_TO_OVF_I4_2: {
4660 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4662 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4665 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4666 high_bit_not_set = code;
4667 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4669 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4670 valid_negative = code;
4671 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4672 invalid_negative = code;
4673 ARM_B_COND (code, ARMCOND_AL, 0);
4675 arm_patch (high_bit_not_set, code);
4677 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4678 valid_positive = code;
4679 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4681 arm_patch (invalid_negative, code);
4682 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4684 arm_patch (valid_negative, code);
4685 arm_patch (valid_positive, code);
4687 if (ins->dreg != ins->sreg1)
4688 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4693 ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4696 ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4699 ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4702 ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4705 ARM_FPA_MNFD (code, ins->dreg, ins->sreg1);
4707 #elif defined(ARM_FPU_VFP)
4709 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4712 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4715 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4718 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4721 ARM_NEGD (code, ins->dreg, ins->sreg1);
4726 g_assert_not_reached ();
4730 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4731 } else if (IS_VFP) {
4732 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4738 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4739 } else if (IS_VFP) {
4740 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4743 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4744 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4748 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4750 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4753 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4754 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4758 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4759 } else if (IS_VFP) {
4760 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4763 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4764 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4765 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4770 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4771 } else if (IS_VFP) {
4772 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4775 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4776 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4781 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4782 } else if (IS_VFP) {
4783 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4786 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4787 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4788 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4790 /* ARM FPA flags table:
4791 * N Less than ARMCOND_MI
4792 * Z Equal ARMCOND_EQ
4793 * C Greater Than or Equal ARMCOND_CS
4794 * V Unordered ARMCOND_VS
4797 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4800 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4803 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4806 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4807 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4813 g_assert_not_reached ();
4817 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4819 /* FPA requires EQ even thou the docs suggests that just CS is enough */
4820 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4821 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4825 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4826 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4831 if (ins->dreg != ins->sreg1)
4832 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4833 } else if (IS_VFP) {
4834 ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4835 ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4837 *(guint32*)code = 0xffffffff;
4839 *(guint32*)code = 0x7fefffff;
4841 ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4843 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4844 ARM_CMPD (code, ins->sreg1, ins->sreg1);
4846 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4847 ARM_CPYD (code, ins->dreg, ins->sreg1);
4852 case OP_GC_LIVENESS_DEF:
4853 case OP_GC_LIVENESS_USE:
4854 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4855 ins->backend.pc_offset = code - cfg->native_code;
4857 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4858 ins->backend.pc_offset = code - cfg->native_code;
4859 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4863 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4864 g_assert_not_reached ();
4867 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4868 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4869 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4870 g_assert_not_reached ();
4876 last_offset = offset;
4879 cfg->code_len = code - cfg->native_code;
4882 #endif /* DISABLE_JIT */
4884 #ifdef HAVE_AEABI_READ_TP
4885 void __aeabi_read_tp (void);
4889 mono_arch_register_lowlevel_calls (void)
4891 /* The signature doesn't matter */
4892 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4893 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4895 #ifndef MONO_CROSS_COMPILE
4896 #ifdef HAVE_AEABI_READ_TP
4897 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4902 #define patch_lis_ori(ip,val) do {\
4903 guint16 *__lis_ori = (guint16*)(ip); \
4904 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
4905 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
4909 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4911 MonoJumpInfo *patch_info;
4912 gboolean compile_aot = !run_cctors;
4914 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4915 unsigned char *ip = patch_info->ip.i + code;
4916 const unsigned char *target;
4918 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4919 gpointer *jt = (gpointer*)(ip + 8);
4921 /* jt is the inlined jump table, 2 instructions after ip
4922 * In the normal case we store the absolute addresses,
4923 * otherwise the displacements.
4925 for (i = 0; i < patch_info->data.table->table_size; i++)
4926 jt [i] = code + (int)patch_info->data.table->table [i];
4929 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4932 switch (patch_info->type) {
4933 case MONO_PATCH_INFO_BB:
4934 case MONO_PATCH_INFO_LABEL:
4937 /* No need to patch these */
4942 switch (patch_info->type) {
4943 case MONO_PATCH_INFO_IP:
4944 g_assert_not_reached ();
4945 patch_lis_ori (ip, ip);
4947 case MONO_PATCH_INFO_METHOD_REL:
4948 g_assert_not_reached ();
4949 *((gpointer *)(ip)) = code + patch_info->data.offset;
4951 case MONO_PATCH_INFO_METHODCONST:
4952 case MONO_PATCH_INFO_CLASS:
4953 case MONO_PATCH_INFO_IMAGE:
4954 case MONO_PATCH_INFO_FIELD:
4955 case MONO_PATCH_INFO_VTABLE:
4956 case MONO_PATCH_INFO_IID:
4957 case MONO_PATCH_INFO_SFLDA:
4958 case MONO_PATCH_INFO_LDSTR:
4959 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4960 case MONO_PATCH_INFO_LDTOKEN:
4961 g_assert_not_reached ();
4962 /* from OP_AOTCONST : lis + ori */
4963 patch_lis_ori (ip, target);
4965 case MONO_PATCH_INFO_R4:
4966 case MONO_PATCH_INFO_R8:
4967 g_assert_not_reached ();
4968 *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4970 case MONO_PATCH_INFO_EXC_NAME:
4971 g_assert_not_reached ();
4972 *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4974 case MONO_PATCH_INFO_NONE:
4975 case MONO_PATCH_INFO_BB_OVF:
4976 case MONO_PATCH_INFO_EXC_OVF:
4977 /* everything is dealt with at epilog output time */
4982 arm_patch_general (domain, ip, target, dyn_code_mp);
4989 * Stack frame layout:
4991 * ------------------- fp
4992 * MonoLMF structure or saved registers
4993 * -------------------
4995 * -------------------
4997 * -------------------
4998 * optional 8 bytes for tracing
4999 * -------------------
5000 * param area size is cfg->param_area
5001 * ------------------- sp
5004 mono_arch_emit_prolog (MonoCompile *cfg)
5006 MonoMethod *method = cfg->method;
5008 MonoMethodSignature *sig;
5010 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount;
5015 int prev_sp_offset, reg_offset;
5017 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5020 sig = mono_method_signature (method);
5021 cfg->code_size = 256 + sig->param_count * 64;
5022 code = cfg->native_code = g_malloc (cfg->code_size);
5024 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
5026 alloc_size = cfg->stack_offset;
5030 if (!method->save_lmf) {
5033 * The iphone uses R7 as the frame pointer, and it points at the saved
5038 * We can't use r7 as a frame pointer since it points into the middle of
5039 * the frame, so we keep using our own frame pointer.
5040 * FIXME: Optimize this.
5043 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5044 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
5045 prev_sp_offset += 8; /* r7 and lr */
5046 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5047 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
5049 /* No need to push LR again */
5050 if (cfg->used_int_regs)
5051 ARM_PUSH (code, cfg->used_int_regs);
5053 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
5054 prev_sp_offset += 4;
5056 for (i = 0; i < 16; ++i) {
5057 if (cfg->used_int_regs & (1 << i))
5058 prev_sp_offset += 4;
5060 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5062 for (i = 0; i < 16; ++i) {
5063 if ((cfg->used_int_regs & (1 << i))) {
5064 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5065 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
5070 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5071 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5073 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5074 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5077 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
5078 ARM_PUSH (code, 0x5ff0);
5079 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
5080 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5082 for (i = 0; i < 16; ++i) {
5083 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
5084 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5088 pos += sizeof (MonoLMF) - prev_sp_offset;
5092 orig_alloc_size = alloc_size;
5093 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
5094 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
5095 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
5096 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
5099 /* the stack used in the pushed regs */
5100 if (prev_sp_offset & 4)
5102 cfg->stack_usage = alloc_size;
5104 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
5105 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5107 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
5108 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5110 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
5112 if (cfg->frame_reg != ARMREG_SP) {
5113 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
5114 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
5116 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
5117 prev_sp_offset += alloc_size;
5119 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
5120 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
5122 /* compute max_offset in order to use short forward jumps
5123 * we could skip do it on arm because the immediate displacement
5124 * for jumps is large enough, it may be useful later for constant pools
5127 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5128 MonoInst *ins = bb->code;
5129 bb->max_offset = max_offset;
5131 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5134 MONO_BB_FOR_EACH_INS (bb, ins)
5135 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5138 /* store runtime generic context */
5139 if (cfg->rgctx_var) {
5140 MonoInst *ins = cfg->rgctx_var;
5142 g_assert (ins->opcode == OP_REGOFFSET);
5144 if (arm_is_imm12 (ins->inst_offset)) {
5145 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
5147 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5148 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
5152 /* load arguments allocated to register from the stack */
5155 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
5157 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
5158 ArgInfo *ainfo = &cinfo->ret;
5159 inst = cfg->vret_addr;
5160 g_assert (arm_is_imm12 (inst->inst_offset));
5161 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5164 if (sig->call_convention == MONO_CALL_VARARG) {
5165 ArgInfo *cookie = &cinfo->sig_cookie;
5167 /* Save the sig cookie address */
5168 g_assert (cookie->storage == RegTypeBase);
5170 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
5171 g_assert (arm_is_imm12 (cfg->sig_cookie));
5172 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
5173 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5176 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5177 ArgInfo *ainfo = cinfo->args + i;
5178 inst = cfg->args [pos];
5180 if (cfg->verbose_level > 2)
5181 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
5182 if (inst->opcode == OP_REGVAR) {
5183 if (ainfo->storage == RegTypeGeneral)
5184 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
5185 else if (ainfo->storage == RegTypeFP) {
5186 g_assert_not_reached ();
5187 } else if (ainfo->storage == RegTypeBase) {
5188 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5189 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5191 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5192 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
5195 g_assert_not_reached ();
5197 if (cfg->verbose_level > 2)
5198 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5200 /* the argument should be put on the stack: FIXME handle size != word */
5201 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
5202 switch (ainfo->size) {
5204 if (arm_is_imm12 (inst->inst_offset))
5205 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5207 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5208 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5212 if (arm_is_imm8 (inst->inst_offset)) {
5213 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5215 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5216 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5220 if (arm_is_imm12 (inst->inst_offset)) {
5221 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5223 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5224 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5226 if (arm_is_imm12 (inst->inst_offset + 4)) {
5227 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
5229 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5230 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
5234 if (arm_is_imm12 (inst->inst_offset)) {
5235 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5237 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5238 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5242 } else if (ainfo->storage == RegTypeBaseGen) {
5243 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
5244 g_assert (arm_is_imm12 (inst->inst_offset));
5245 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5246 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5247 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
5248 } else if (ainfo->storage == RegTypeBase) {
5249 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5250 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5252 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
5253 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5256 switch (ainfo->size) {
5258 if (arm_is_imm8 (inst->inst_offset)) {
5259 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5261 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5262 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5266 if (arm_is_imm8 (inst->inst_offset)) {
5267 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5269 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5270 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5274 if (arm_is_imm12 (inst->inst_offset)) {
5275 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5277 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5278 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5280 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
5281 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
5283 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
5284 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5286 if (arm_is_imm12 (inst->inst_offset + 4)) {
5287 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5289 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5290 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5294 if (arm_is_imm12 (inst->inst_offset)) {
5295 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5297 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5298 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5302 } else if (ainfo->storage == RegTypeFP) {
5303 g_assert_not_reached ();
5304 } else if (ainfo->storage == RegTypeStructByVal) {
5305 int doffset = inst->inst_offset;
5309 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
5310 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
5311 if (arm_is_imm12 (doffset)) {
5312 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
5314 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
5315 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
5317 soffset += sizeof (gpointer);
5318 doffset += sizeof (gpointer);
5320 if (ainfo->vtsize) {
5321 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5322 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
5323 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
5325 } else if (ainfo->storage == RegTypeStructByAddr) {
5326 g_assert_not_reached ();
5327 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5328 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
5330 g_assert_not_reached ();
5335 if (method->save_lmf)
5336 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
5339 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5341 if (cfg->arch.seq_point_info_var) {
5342 MonoInst *ins = cfg->arch.seq_point_info_var;
5344 /* Initialize the variable from a GOT slot */
5345 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
5346 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5348 *(gpointer*)code = NULL;
5350 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
5352 g_assert (ins->opcode == OP_REGOFFSET);
5354 if (arm_is_imm12 (ins->inst_offset)) {
5355 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5357 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5358 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5362 /* Initialize ss_trigger_page_var */
5363 if (!cfg->soft_breakpoints) {
5364 MonoInst *info_var = cfg->arch.seq_point_info_var;
5365 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
5366 int dreg = ARMREG_LR;
5369 g_assert (info_var->opcode == OP_REGOFFSET);
5370 g_assert (arm_is_imm12 (info_var->inst_offset));
5372 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
5373 /* Load the trigger page addr */
5374 ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
5375 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
5379 if (cfg->arch.seq_point_read_var) {
5380 MonoInst *read_ins = cfg->arch.seq_point_read_var;
5381 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
5382 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
5384 g_assert (read_ins->opcode == OP_REGOFFSET);
5385 g_assert (arm_is_imm12 (read_ins->inst_offset));
5386 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
5387 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
5388 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
5389 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
5391 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5393 *(volatile int **)code = &ss_trigger_var;
5395 *(gpointer*)code = single_step_func_wrapper;
5397 *(gpointer*)code = breakpoint_func_wrapper;
5400 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
5401 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
5402 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
5403 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
5404 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
5405 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
5408 cfg->code_len = code - cfg->native_code;
5409 g_assert (cfg->code_len < cfg->code_size);
5416 mono_arch_emit_epilog (MonoCompile *cfg)
5418 MonoMethod *method = cfg->method;
5419 int pos, i, rot_amount;
5420 int max_epilog_size = 16 + 20*4;
5424 if (cfg->method->save_lmf)
5425 max_epilog_size += 128;
5427 if (mono_jit_trace_calls != NULL)
5428 max_epilog_size += 50;
5430 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5431 max_epilog_size += 50;
5433 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5434 cfg->code_size *= 2;
5435 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5436 cfg->stat_code_reallocs++;
5440 * Keep in sync with OP_JMP
5442 code = cfg->native_code + cfg->code_len;
5444 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5445 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5449 /* Load returned vtypes into registers if needed */
5450 cinfo = cfg->arch.cinfo;
5451 if (cinfo->ret.storage == RegTypeStructByVal) {
5452 MonoInst *ins = cfg->ret;
5454 if (arm_is_imm12 (ins->inst_offset)) {
5455 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5457 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5458 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5462 if (method->save_lmf) {
5463 int lmf_offset, reg, sp_adj, regmask;
5464 /* all but r0-r3, sp and pc */
5465 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5468 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
5470 /* This points to r4 inside MonoLMF->iregs */
5471 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5473 regmask = 0x9ff0; /* restore lr to pc */
5474 /* Skip caller saved registers not used by the method */
5475 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5476 regmask &= ~(1 << reg);
5480 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5481 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
5483 ARM_POP (code, regmask);
5485 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5486 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5488 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5489 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5493 /* Restore saved gregs */
5494 if (cfg->used_int_regs)
5495 ARM_POP (code, cfg->used_int_regs);
5496 /* Restore saved r7, restore LR to PC */
5497 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5499 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5503 cfg->code_len = code - cfg->native_code;
5505 g_assert (cfg->code_len < cfg->code_size);
5509 /* remove once throw_exception_by_name is eliminated */
5511 exception_id_by_name (const char *name)
5513 if (strcmp (name, "IndexOutOfRangeException") == 0)
5514 return MONO_EXC_INDEX_OUT_OF_RANGE;
5515 if (strcmp (name, "OverflowException") == 0)
5516 return MONO_EXC_OVERFLOW;
5517 if (strcmp (name, "ArithmeticException") == 0)
5518 return MONO_EXC_ARITHMETIC;
5519 if (strcmp (name, "DivideByZeroException") == 0)
5520 return MONO_EXC_DIVIDE_BY_ZERO;
5521 if (strcmp (name, "InvalidCastException") == 0)
5522 return MONO_EXC_INVALID_CAST;
5523 if (strcmp (name, "NullReferenceException") == 0)
5524 return MONO_EXC_NULL_REF;
5525 if (strcmp (name, "ArrayTypeMismatchException") == 0)
5526 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5527 if (strcmp (name, "ArgumentException") == 0)
5528 return MONO_EXC_ARGUMENT;
5529 g_error ("Unknown intrinsic exception %s\n", name);
5534 mono_arch_emit_exceptions (MonoCompile *cfg)
5536 MonoJumpInfo *patch_info;
5539 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5540 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5541 int max_epilog_size = 50;
5543 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5544 exc_throw_pos [i] = NULL;
5545 exc_throw_found [i] = 0;
5548 /* count the number of exception infos */
5551 * make sure we have enough space for exceptions
5553 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5554 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5555 i = exception_id_by_name (patch_info->data.target);
5556 if (!exc_throw_found [i]) {
5557 max_epilog_size += 32;
5558 exc_throw_found [i] = TRUE;
5563 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5564 cfg->code_size *= 2;
5565 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5566 cfg->stat_code_reallocs++;
5569 code = cfg->native_code + cfg->code_len;
5571 /* add code to raise exceptions */
5572 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5573 switch (patch_info->type) {
5574 case MONO_PATCH_INFO_EXC: {
5575 MonoClass *exc_class;
5576 unsigned char *ip = patch_info->ip.i + cfg->native_code;
5578 i = exception_id_by_name (patch_info->data.target);
5579 if (exc_throw_pos [i]) {
5580 arm_patch (ip, exc_throw_pos [i]);
5581 patch_info->type = MONO_PATCH_INFO_NONE;
5584 exc_throw_pos [i] = code;
5586 arm_patch (ip, code);
5588 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5589 g_assert (exc_class);
5591 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5592 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5593 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5594 patch_info->data.name = "mono_arch_throw_corlib_exception";
5595 patch_info->ip.i = code - cfg->native_code;
5597 *(guint32*)(gpointer)code = exc_class->type_token;
5607 cfg->code_len = code - cfg->native_code;
5609 g_assert (cfg->code_len < cfg->code_size);
5613 #endif /* #ifndef DISABLE_JIT */
5616 mono_arch_finish_init (void)
5618 lmf_tls_offset = mono_get_lmf_tls_offset ();
5619 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5623 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5628 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5635 mono_arch_print_tree (MonoInst *tree, int arity)
5641 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5643 return mono_get_domain_intrinsic (cfg);
5647 mono_arch_get_patch_offset (guint8 *code)
5654 mono_arch_flush_register_windows (void)
5658 #ifdef MONO_ARCH_HAVE_IMT
5663 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5665 if (cfg->compile_aot) {
5666 int method_reg = mono_alloc_ireg (cfg);
5669 call->dynamic_imt_arg = TRUE;
5672 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5674 MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5675 ins->dreg = method_reg;
5676 ins->inst_p0 = call->method;
5677 ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5678 MONO_ADD_INS (cfg->cbb, ins);
5680 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5682 } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5684 /* Always pass in a register for simplicity */
5685 call->dynamic_imt_arg = TRUE;
5687 cfg->uses_rgctx_reg = TRUE;
5690 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5693 int method_reg = mono_alloc_preg (cfg);
5695 MONO_INST_NEW (cfg, ins, OP_PCONST);
5696 ins->inst_p0 = call->method;
5697 ins->dreg = method_reg;
5698 MONO_ADD_INS (cfg->cbb, ins);
5700 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5705 #endif /* DISABLE_JIT */
5708 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5710 guint32 *code_ptr = (guint32*)code;
5715 return (MonoMethod*)regs [ARMREG_V5];
5717 /* The IMT value is stored in the code stream right after the LDC instruction. */
5718 if (!IS_LDR_PC (code_ptr [0])) {
5719 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5720 g_assert (IS_LDR_PC (code_ptr [0]));
5722 if (code_ptr [1] == 0)
5723 /* This is AOTed code, the IMT method is in V5 */
5724 return (MonoMethod*)regs [ARMREG_V5];
5726 return (MonoMethod*) code_ptr [1];
5730 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5732 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5735 #define ENABLE_WRONG_METHOD_CHECK 0
5736 #define BASE_SIZE (6 * 4)
5737 #define BSEARCH_ENTRY_SIZE (4 * 4)
5738 #define CMP_SIZE (3 * 4)
5739 #define BRANCH_SIZE (1 * 4)
5740 #define CALL_SIZE (2 * 4)
5741 #define WMC_SIZE (5 * 4)
5742 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5745 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5747 guint32 delta = DISTANCE (target, code);
5749 g_assert (delta >= 0 && delta <= 0xFFF);
5750 *target = *target | delta;
5756 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5757 gpointer fail_tramp)
5759 int size, i, extra_space = 0;
5760 arminstr_t *code, *start, *vtable_target = NULL;
5761 gboolean large_offsets = FALSE;
5762 guint32 **constant_pool_starts;
5765 constant_pool_starts = g_new0 (guint32*, count);
5767 for (i = 0; i < count; ++i) {
5768 MonoIMTCheckItem *item = imt_entries [i];
5769 if (item->is_equals) {
5770 gboolean fail_case = !item->check_target_idx && fail_tramp;
5772 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5773 item->chunk_size += 32;
5774 large_offsets = TRUE;
5777 if (item->check_target_idx || fail_case) {
5778 if (!item->compare_done || fail_case)
5779 item->chunk_size += CMP_SIZE;
5780 item->chunk_size += BRANCH_SIZE;
5782 #if ENABLE_WRONG_METHOD_CHECK
5783 item->chunk_size += WMC_SIZE;
5787 item->chunk_size += 16;
5788 large_offsets = TRUE;
5790 item->chunk_size += CALL_SIZE;
5792 item->chunk_size += BSEARCH_ENTRY_SIZE;
5793 imt_entries [item->check_target_idx]->compare_done = TRUE;
5795 size += item->chunk_size;
5799 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5802 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5804 code = mono_domain_code_reserve (domain, size);
5808 printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5809 for (i = 0; i < count; ++i) {
5810 MonoIMTCheckItem *item = imt_entries [i];
5811 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5816 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5818 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5819 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5820 vtable_target = code;
5821 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5823 if (mono_use_llvm) {
5824 /* LLVM always passes the IMT method in R5 */
5825 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5827 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5828 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5829 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5832 for (i = 0; i < count; ++i) {
5833 MonoIMTCheckItem *item = imt_entries [i];
5834 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5835 gint32 vtable_offset;
5837 item->code_target = (guint8*)code;
5839 if (item->is_equals) {
5840 gboolean fail_case = !item->check_target_idx && fail_tramp;
5842 if (item->check_target_idx || fail_case) {
5843 if (!item->compare_done || fail_case) {
5845 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5846 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5848 item->jmp_code = (guint8*)code;
5849 ARM_B_COND (code, ARMCOND_NE, 0);
5851 /*Enable the commented code to assert on wrong method*/
5852 #if ENABLE_WRONG_METHOD_CHECK
5854 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5855 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5856 ARM_B_COND (code, ARMCOND_NE, 1);
5862 if (item->has_target_code) {
5863 target_code_ins = code;
5864 /* Load target address */
5865 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5866 /* Save it to the fourth slot */
5867 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5868 /* Restore registers and branch */
5869 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5871 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5873 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5874 if (!arm_is_imm12 (vtable_offset)) {
5876 * We need to branch to a computed address but we don't have
5877 * a free register to store it, since IP must contain the
5878 * vtable address. So we push the two values to the stack, and
5879 * load them both using LDM.
5881 /* Compute target address */
5882 vtable_offset_ins = code;
5883 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5884 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5885 /* Save it to the fourth slot */
5886 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5887 /* Restore registers and branch */
5888 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5890 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5892 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5894 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5895 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5900 arm_patch (item->jmp_code, (guchar*)code);
5902 target_code_ins = code;
5903 /* Load target address */
5904 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5905 /* Save it to the fourth slot */
5906 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5907 /* Restore registers and branch */
5908 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5910 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5911 item->jmp_code = NULL;
5915 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5917 /*must emit after unconditional branch*/
5918 if (vtable_target) {
5919 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5920 item->chunk_size += 4;
5921 vtable_target = NULL;
5924 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5925 constant_pool_starts [i] = code;
5927 code += extra_space;
5931 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5932 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5934 item->jmp_code = (guint8*)code;
5935 ARM_B_COND (code, ARMCOND_GE, 0);
5940 for (i = 0; i < count; ++i) {
5941 MonoIMTCheckItem *item = imt_entries [i];
5942 if (item->jmp_code) {
5943 if (item->check_target_idx)
5944 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5946 if (i > 0 && item->is_equals) {
5948 arminstr_t *space_start = constant_pool_starts [i];
5949 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5950 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5957 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5958 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5963 g_free (constant_pool_starts);
5965 mono_arch_flush_icache ((guint8*)start, size);
5966 mono_stats.imt_thunks_size += code - start;
5968 g_assert (DISTANCE (start, code) <= size);
5975 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5977 return ctx->regs [reg];
5981 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
5983 ctx->regs [reg] = val;
5987 * mono_arch_get_trampolines:
5989 * Return a list of MonoTrampInfo structures describing arch specific trampolines
5993 mono_arch_get_trampolines (gboolean aot)
5995 return mono_arm_get_exception_trampolines (aot);
5999 * mono_arch_set_breakpoint:
6001 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6002 * The location should contain code emitted by OP_SEQ_POINT.
6005 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6008 guint32 native_offset = ip - (guint8*)ji->code_start;
6009 MonoDebugOptions *opt = mini_get_debug_options ();
6011 if (opt->soft_breakpoints) {
6012 g_assert (!ji->from_aot);
6014 ARM_BLX_REG (code, ARMREG_LR);
6015 mono_arch_flush_icache (code - 4, 4);
6016 } else if (ji->from_aot) {
6017 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6019 g_assert (native_offset % 4 == 0);
6020 g_assert (info->bp_addrs [native_offset / 4] == 0);
6021 info->bp_addrs [native_offset / 4] = bp_trigger_page;
6023 int dreg = ARMREG_LR;
6025 /* Read from another trigger page */
6026 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
6028 *(int*)code = (int)bp_trigger_page;
6030 ARM_LDR_IMM (code, dreg, dreg, 0);
6032 mono_arch_flush_icache (code - 16, 16);
6035 /* This is currently implemented by emitting an SWI instruction, which
6036 * qemu/linux seems to convert to a SIGILL.
6038 *(int*)code = (0xef << 24) | 8;
6040 mono_arch_flush_icache (code - 4, 4);
6046 * mono_arch_clear_breakpoint:
6048 * Clear the breakpoint at IP.
6051 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6053 MonoDebugOptions *opt = mini_get_debug_options ();
6057 if (opt->soft_breakpoints) {
6058 g_assert (!ji->from_aot);
6061 mono_arch_flush_icache (code - 4, 4);
6062 } else if (ji->from_aot) {
6063 guint32 native_offset = ip - (guint8*)ji->code_start;
6064 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6066 g_assert (native_offset % 4 == 0);
6067 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
6068 info->bp_addrs [native_offset / 4] = 0;
6070 for (i = 0; i < 4; ++i)
6073 mono_arch_flush_icache (ip, code - ip);
6078 * mono_arch_start_single_stepping:
6080 * Start single stepping.
6083 mono_arch_start_single_stepping (void)
6085 if (ss_trigger_page)
6086 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6092 * mono_arch_stop_single_stepping:
6094 * Stop single stepping.
6097 mono_arch_stop_single_stepping (void)
6099 if (ss_trigger_page)
6100 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6106 #define DBG_SIGNAL SIGBUS
6108 #define DBG_SIGNAL SIGSEGV
6112 * mono_arch_is_single_step_event:
6114 * Return whenever the machine state in SIGCTX corresponds to a single
6118 mono_arch_is_single_step_event (void *info, void *sigctx)
6120 siginfo_t *sinfo = info;
6122 if (!ss_trigger_page)
6125 /* Sometimes the address is off by 4 */
6126 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
6133 * mono_arch_is_breakpoint_event:
6135 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
6138 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6140 siginfo_t *sinfo = info;
6142 if (!ss_trigger_page)
6145 if (sinfo->si_signo == DBG_SIGNAL) {
6146 /* Sometimes the address is off by 4 */
6147 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
6157 * mono_arch_skip_breakpoint:
6159 * See mini-amd64.c for docs.
6162 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6164 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6168 * mono_arch_skip_single_step:
6170 * See mini-amd64.c for docs.
6173 mono_arch_skip_single_step (MonoContext *ctx)
6175 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6179 * mono_arch_get_seq_point_info:
6181 * See mini-amd64.c for docs.
6184 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6189 // FIXME: Add a free function
6191 mono_domain_lock (domain);
6192 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
6194 mono_domain_unlock (domain);
6197 ji = mono_jit_info_table_find (domain, (char*)code);
6200 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
6202 info->ss_trigger_page = ss_trigger_page;
6203 info->bp_trigger_page = bp_trigger_page;
6205 mono_domain_lock (domain);
6206 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
6208 mono_domain_unlock (domain);
6215 * mono_arch_set_target:
6217 * Set the target architecture the JIT backend should generate code for, in the form
6218 * of a GNU target triplet. Only used in AOT mode.
6221 mono_arch_set_target (char *mtriple)
6223 /* The GNU target triple format is not very well documented */
6224 if (strstr (mtriple, "armv7")) {
6225 v6_supported = TRUE;
6226 v7_supported = TRUE;
6228 if (strstr (mtriple, "armv6")) {
6229 v6_supported = TRUE;
6231 if (strstr (mtriple, "darwin")) {
6232 v5_supported = TRUE;
6233 thumb_supported = TRUE;
6237 if (strstr (mtriple, "gnueabi"))
6238 eabi_supported = TRUE;