2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
27 #include "debugger-agent.h"
29 #include "mono/arch/arm/arm-vfp-codegen.h"
31 /* Sanity check: This makes no sense */
32 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
33 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
37 * IS_SOFT_FLOAT: Is full software floating point used?
38 * IS_HARD_FLOAT: Is full hardware floating point used?
39 * IS_VFP: Is hardware floating point with software ABI used?
41 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
42 * IS_VFP may delegate to mono_arch_is_soft_float ().
45 #if defined(ARM_FPU_VFP_HARD)
46 #define IS_SOFT_FLOAT (FALSE)
47 #define IS_HARD_FLOAT (TRUE)
49 #elif defined(ARM_FPU_NONE)
50 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
51 #define IS_HARD_FLOAT (FALSE)
52 #define IS_VFP (!mono_arch_is_soft_float ())
54 #define IS_SOFT_FLOAT (FALSE)
55 #define IS_HARD_FLOAT (FALSE)
59 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(__native_client__)
60 #define HAVE_AEABI_READ_TP 1
63 #define THUNK_SIZE (3 * 4)
65 #ifdef __native_client_codegen__
66 const guint kNaClAlignment = kNaClAlignmentARM;
67 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
68 gint8 nacl_align_byte = -1; /* 0xff */
71 mono_arch_nacl_pad (guint8 *code, int pad)
73 /* Not yet properly implemented. */
74 g_assert_not_reached ();
79 mono_arch_nacl_skip_nops (guint8 *code)
81 /* Not yet properly implemented. */
82 g_assert_not_reached ();
86 #endif /* __native_client_codegen__ */
88 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
91 void sys_icache_invalidate (void *start, size_t len);
94 /* This mutex protects architecture specific caches */
95 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
96 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
97 static mono_mutex_t mini_arch_mutex;
99 static gboolean v5_supported = FALSE;
100 static gboolean v6_supported = FALSE;
101 static gboolean v7_supported = FALSE;
102 static gboolean v7s_supported = FALSE;
103 static gboolean thumb_supported = FALSE;
104 static gboolean thumb2_supported = FALSE;
106 * Whenever to use the ARM EABI
108 static gboolean eabi_supported = FALSE;
111 * Whenever to use the iphone ABI extensions:
112 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
113 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
114 * This is required for debugging/profiling tools to work, but it has some overhead so it should
115 * only be turned on in debug builds.
117 static gboolean iphone_abi = FALSE;
120 * The FPU we are generating code for. This is NOT runtime configurable right now,
121 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
123 static MonoArmFPU arm_fpu;
125 #if defined(ARM_FPU_VFP_HARD)
127 * On armhf, d0-d7 are used for argument passing and d8-d15
128 * must be preserved across calls, which leaves us no room
129 * for scratch registers. So we use d14-d15 but back up their
130 * previous contents to a stack slot before using them - see
131 * mono_arm_emit_vfp_scratch_save/_restore ().
133 static int vfp_scratch1 = ARM_VFP_D14;
134 static int vfp_scratch2 = ARM_VFP_D15;
137 * On armel, d0-d7 do not need to be preserved, so we can
138 * freely make use of them as scratch registers.
140 static int vfp_scratch1 = ARM_VFP_D0;
141 static int vfp_scratch2 = ARM_VFP_D1;
146 static volatile int ss_trigger_var = 0;
148 static gpointer single_step_tramp, breakpoint_tramp;
151 * The code generated for sequence points reads from this location, which is
152 * made read-only when single stepping is enabled.
154 static gpointer ss_trigger_page;
156 /* Enabled breakpoints read from this trigger page */
157 static gpointer bp_trigger_page;
161 * floating point support: on ARM it is a mess, there are at least 3
162 * different setups, each of which binary incompat with the other.
163 * 1) FPA: old and ugly, but unfortunately what current distros use
164 * the double binary format has the two words swapped. 8 double registers.
165 * Implemented usually by kernel emulation.
166 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
167 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
168 * 3) VFP: the new and actually sensible and useful FP support. Implemented
169 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
171 * We do not care about FPA. We will support soft float and VFP.
173 int mono_exc_esp_offset = 0;
175 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
176 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
177 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
179 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
180 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
181 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
183 //#define DEBUG_IMT 0
186 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
190 mono_arch_regname (int reg)
192 static const char * rnames[] = {
193 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
194 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
195 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
198 if (reg >= 0 && reg < 16)
204 mono_arch_fregname (int reg)
206 static const char * rnames[] = {
207 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
208 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
209 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
210 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
211 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
212 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
215 if (reg >= 0 && reg < 32)
223 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
225 int imm8, rot_amount;
226 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
227 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
231 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
232 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
234 code = mono_arm_emit_load_imm (code, dreg, imm);
235 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
240 /* If dreg == sreg, this clobbers IP */
242 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
244 int imm8, rot_amount;
245 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
246 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
250 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
251 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
253 code = mono_arm_emit_load_imm (code, dreg, imm);
254 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
260 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
262 /* we can use r0-r3, since this is called only for incoming args on the stack */
263 if (size > sizeof (gpointer) * 4) {
265 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
266 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
267 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
268 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
269 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
270 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
271 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
272 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
273 ARM_B_COND (code, ARMCOND_NE, 0);
274 arm_patch (code - 4, start_loop);
277 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
278 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
280 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
281 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
287 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
288 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
289 doffset = soffset = 0;
291 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
292 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
298 g_assert (size == 0);
303 emit_call_reg (guint8 *code, int reg)
306 ARM_BLX_REG (code, reg);
308 #ifdef USE_JUMP_TABLES
309 g_assert_not_reached ();
311 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
315 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
321 emit_call_seq (MonoCompile *cfg, guint8 *code)
323 #ifdef USE_JUMP_TABLES
324 code = mono_arm_patchable_bl (code, ARMCOND_AL);
326 if (cfg->method->dynamic) {
327 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
329 *(gpointer*)code = NULL;
331 code = emit_call_reg (code, ARMREG_IP);
335 cfg->thunk_area += THUNK_SIZE;
341 mono_arm_patchable_b (guint8 *code, int cond)
343 #ifdef USE_JUMP_TABLES
346 jte = mono_jumptable_add_entry ();
347 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
348 ARM_BX_COND (code, cond, ARMREG_IP);
350 ARM_B_COND (code, cond, 0);
356 mono_arm_patchable_bl (guint8 *code, int cond)
358 #ifdef USE_JUMP_TABLES
361 jte = mono_jumptable_add_entry ();
362 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
363 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
365 ARM_BL_COND (code, cond, 0);
370 #ifdef USE_JUMP_TABLES
372 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
374 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
375 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
380 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
382 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
383 ARM_LDR_IMM (code, reg, reg, 0);
391 * Emit code to push an LMF structure on the LMF stack.
392 * On arm, this is intermixed with the initialization of other fields of the structure.
395 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
397 gboolean get_lmf_fast = FALSE;
400 #ifdef HAVE_AEABI_READ_TP
401 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
403 if (lmf_addr_tls_offset != -1) {
406 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
407 (gpointer)"__aeabi_read_tp");
408 code = emit_call_seq (cfg, code);
410 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
416 if (cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) {
419 /* Inline mono_get_lmf_addr () */
420 /* jit_tls = pthread_getspecific (mono_jit_tls_id); lmf_addr = &jit_tls->lmf; */
422 /* Load mono_jit_tls_id */
424 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_TLS_ID, NULL);
425 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
427 *(gpointer*)code = NULL;
429 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
430 /* call pthread_getspecific () */
431 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
432 (gpointer)"pthread_getspecific");
433 code = emit_call_seq (cfg, code);
434 /* lmf_addr = &jit_tls->lmf */
435 lmf_offset = MONO_STRUCT_OFFSET (MonoJitTlsData, lmf);
436 g_assert (arm_is_imm8 (lmf_offset));
437 ARM_ADD_REG_IMM (code, ARMREG_R0, ARMREG_R0, lmf_offset, 0);
444 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
445 (gpointer)"mono_get_lmf_addr");
446 code = emit_call_seq (cfg, code);
448 /* we build the MonoLMF structure on the stack - see mini-arm.h */
449 /* lmf_offset is the offset from the previous stack pointer,
450 * alloc_size is the total stack space allocated, so the offset
451 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
452 * The pointer to the struct is put in r1 (new_lmf).
453 * ip is used as scratch
454 * The callee-saved registers are already in the MonoLMF structure
456 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
457 /* r0 is the result from mono_get_lmf_addr () */
458 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
459 /* new_lmf->previous_lmf = *lmf_addr */
460 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
461 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
462 /* *(lmf_addr) = r1 */
463 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
464 /* Skip method (only needed for trampoline LMF frames) */
465 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
466 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
467 /* save the current IP */
468 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
469 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
471 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
472 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
483 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
487 g_assert (!cfg->r4fp);
489 for (list = inst->float_args; list; list = list->next) {
490 FloatArgData *fad = list->data;
491 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
492 gboolean imm = arm_is_fpimm8 (var->inst_offset);
494 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
500 if (*offset + *max_len > cfg->code_size) {
501 cfg->code_size += *max_len;
502 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
504 code = cfg->native_code + *offset;
508 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
509 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
511 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
513 *offset = code - cfg->native_code;
520 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
524 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
526 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
529 if (!arm_is_fpimm8 (inst->inst_offset)) {
530 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
531 ARM_FSTD (code, reg, ARMREG_LR, 0);
533 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
540 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
544 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
546 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
549 if (!arm_is_fpimm8 (inst->inst_offset)) {
550 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
551 ARM_FLDD (code, reg, ARMREG_LR, 0);
553 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
562 * Emit code to pop an LMF structure from the LMF stack.
565 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
569 if (lmf_offset < 32) {
570 basereg = cfg->frame_reg;
575 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
578 /* ip = previous_lmf */
579 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
581 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
582 /* *(lmf_addr) = previous_lmf */
583 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
588 #endif /* #ifndef DISABLE_JIT */
591 * mono_arch_get_argument_info:
592 * @csig: a method signature
593 * @param_count: the number of parameters to consider
594 * @arg_info: an array to store the result infos
596 * Gathers information on parameters such as size, alignment and
597 * padding. arg_info should be large enought to hold param_count + 1 entries.
599 * Returns the size of the activation frame.
602 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
604 int k, frame_size = 0;
605 guint32 size, align, pad;
609 t = mini_type_get_underlying_type (gsctx, csig->ret);
610 if (MONO_TYPE_ISSTRUCT (t)) {
611 frame_size += sizeof (gpointer);
615 arg_info [0].offset = offset;
618 frame_size += sizeof (gpointer);
622 arg_info [0].size = frame_size;
624 for (k = 0; k < param_count; k++) {
625 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
627 /* ignore alignment for now */
630 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
631 arg_info [k].pad = pad;
633 arg_info [k + 1].pad = 0;
634 arg_info [k + 1].size = size;
636 arg_info [k + 1].offset = offset;
640 align = MONO_ARCH_FRAME_ALIGNMENT;
641 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
642 arg_info [k].pad = pad;
647 #define MAX_ARCH_DELEGATE_PARAMS 3
650 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
652 guint8 *code, *start;
655 start = code = mono_global_codeman_reserve (12);
657 /* Replace the this argument with the target */
658 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
659 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
660 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
662 g_assert ((code - start) <= 12);
664 mono_arch_flush_icache (start, 12);
668 size = 8 + param_count * 4;
669 start = code = mono_global_codeman_reserve (size);
671 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
672 /* slide down the arguments */
673 for (i = 0; i < param_count; ++i) {
674 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
676 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
678 g_assert ((code - start) <= size);
680 mono_arch_flush_icache (start, size);
683 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
685 *code_size = code - start;
691 * mono_arch_get_delegate_invoke_impls:
693 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
697 mono_arch_get_delegate_invoke_impls (void)
705 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
706 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
708 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
709 code = get_delegate_invoke_impl (FALSE, i, &code_len);
710 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
711 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
719 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
721 guint8 *code, *start;
724 /* FIXME: Support more cases */
725 sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
726 if (MONO_TYPE_ISSTRUCT (sig_ret))
730 static guint8* cached = NULL;
731 mono_mini_arch_lock ();
733 mono_mini_arch_unlock ();
738 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
740 start = get_delegate_invoke_impl (TRUE, 0, NULL);
742 mono_mini_arch_unlock ();
745 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
748 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
750 for (i = 0; i < sig->param_count; ++i)
751 if (!mono_is_regsize_var (sig->params [i]))
754 mono_mini_arch_lock ();
755 code = cache [sig->param_count];
757 mono_mini_arch_unlock ();
762 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
763 start = mono_aot_get_trampoline (name);
766 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
768 cache [sig->param_count] = start;
769 mono_mini_arch_unlock ();
777 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
783 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
785 return (gpointer)regs [ARMREG_R0];
789 * Initialize the cpu to execute managed code.
792 mono_arch_cpu_init (void)
794 i8_align = MONO_ABI_ALIGNOF (gint64);
795 #ifdef MONO_CROSS_COMPILE
796 /* Need to set the alignment of i8 since it can different on the target */
797 #ifdef TARGET_ANDROID
799 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
805 * Initialize architecture specific code.
808 mono_arch_init (void)
810 const char *cpu_arch;
812 mono_mutex_init_recursive (&mini_arch_mutex);
813 if (mini_get_debug_options ()->soft_breakpoints) {
814 single_step_tramp = mini_get_single_step_trampoline ();
815 breakpoint_tramp = mini_get_breakpoint_trampoline ();
817 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
818 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
819 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
822 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
823 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
824 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
825 #if defined(ENABLE_GSHAREDVT)
826 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
829 #if defined(__ARM_EABI__)
830 eabi_supported = TRUE;
833 #if defined(ARM_FPU_VFP_HARD)
834 arm_fpu = MONO_ARM_FPU_VFP_HARD;
836 arm_fpu = MONO_ARM_FPU_VFP;
838 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
840 * If we're compiling with a soft float fallback and it
841 * turns out that no VFP unit is available, we need to
842 * switch to soft float. We don't do this for iOS, since
843 * iOS devices always have a VFP unit.
845 if (!mono_hwcap_arm_has_vfp)
846 arm_fpu = MONO_ARM_FPU_NONE;
849 * This environment variable can be useful in testing
850 * environments to make sure the soft float fallback
851 * works. Most ARM devices have VFP units these days, so
852 * normally soft float code would not be exercised much.
854 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
856 if (soft && !strncmp (soft, "1", 1))
857 arm_fpu = MONO_ARM_FPU_NONE;
861 v5_supported = mono_hwcap_arm_is_v5;
862 v6_supported = mono_hwcap_arm_is_v6;
863 v7_supported = mono_hwcap_arm_is_v7;
864 v7s_supported = mono_hwcap_arm_is_v7s;
866 #if defined(__APPLE__)
867 /* iOS is special-cased here because we don't yet
868 have a way to properly detect CPU features on it. */
869 thumb_supported = TRUE;
872 thumb_supported = mono_hwcap_arm_has_thumb;
873 thumb2_supported = mono_hwcap_arm_has_thumb2;
876 /* Format: armv(5|6|7[s])[-thumb[2]] */
877 cpu_arch = g_getenv ("MONO_CPU_ARCH");
879 /* Do this here so it overrides any detection. */
881 if (strncmp (cpu_arch, "armv", 4) == 0) {
882 v5_supported = cpu_arch [4] >= '5';
883 v6_supported = cpu_arch [4] >= '6';
884 v7_supported = cpu_arch [4] >= '7';
885 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
888 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
889 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
894 * Cleanup architecture specific code.
897 mono_arch_cleanup (void)
902 * This function returns the optimizations supported on this cpu.
905 mono_arch_cpu_optimizations (guint32 *exclude_mask)
907 /* no arm-specific optimizations yet */
913 * This function test for all SIMD functions supported.
915 * Returns a bitmask corresponding to all supported versions.
919 mono_arch_cpu_enumerate_simd_versions (void)
921 /* SIMD is currently unimplemented */
929 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
945 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
947 mono_arch_is_soft_float (void)
949 return arm_fpu == MONO_ARM_FPU_NONE;
954 mono_arm_is_hard_float (void)
956 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
960 is_regsize_var (MonoGenericSharingContext *gsctx, MonoType *t) {
963 t = mini_type_get_underlying_type (gsctx, t);
970 case MONO_TYPE_FNPTR:
972 case MONO_TYPE_OBJECT:
973 case MONO_TYPE_STRING:
974 case MONO_TYPE_CLASS:
975 case MONO_TYPE_SZARRAY:
976 case MONO_TYPE_ARRAY:
978 case MONO_TYPE_GENERICINST:
979 if (!mono_type_generic_inst_is_valuetype (t))
982 case MONO_TYPE_VALUETYPE:
989 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
994 for (i = 0; i < cfg->num_varinfo; i++) {
995 MonoInst *ins = cfg->varinfo [i];
996 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
999 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1002 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1005 /* we can only allocate 32 bit values */
1006 if (is_regsize_var (cfg->generic_sharing_context, ins->inst_vtype)) {
1007 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1008 g_assert (i == vmv->idx);
1009 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1017 mono_arch_get_global_int_regs (MonoCompile *cfg)
1021 mono_arch_compute_omit_fp (cfg);
1024 * FIXME: Interface calls might go through a static rgctx trampoline which
1025 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1028 if (cfg->flags & MONO_CFG_HAS_CALLS)
1029 cfg->uses_rgctx_reg = TRUE;
1031 if (cfg->arch.omit_fp)
1032 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1033 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1034 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1035 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1037 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1038 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1040 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1041 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1042 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1043 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1044 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1045 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1051 * mono_arch_regalloc_cost:
1053 * Return the cost, in number of memory references, of the action of
1054 * allocating the variable VMV into a register during global register
1058 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1064 #endif /* #ifndef DISABLE_JIT */
1066 #ifndef __GNUC_PREREQ
1067 #define __GNUC_PREREQ(maj, min) (0)
1071 mono_arch_flush_icache (guint8 *code, gint size)
1073 #if defined(__native_client__)
1074 // For Native Client we don't have to flush i-cache here,
1075 // as it's being done by dyncode interface.
1078 #ifdef MONO_CROSS_COMPILE
1080 sys_icache_invalidate (code, size);
1081 #elif __GNUC_PREREQ(4, 3)
1082 __builtin___clear_cache (code, code + size);
1083 #elif __GNUC_PREREQ(4, 1)
1084 __clear_cache (code, code + size);
1085 #elif defined(PLATFORM_ANDROID)
1086 const int syscall = 0xf0002;
1094 : "r" (code), "r" (code + size), "r" (syscall)
1095 : "r0", "r1", "r7", "r2"
1098 __asm __volatile ("mov r0, %0\n"
1101 "swi 0x9f0002 @ sys_cacheflush"
1103 : "r" (code), "r" (code + size), "r" (0)
1104 : "r0", "r1", "r3" );
1106 #endif /* !__native_client__ */
1117 RegTypeStructByAddr,
1118 /* gsharedvt argument passed by addr in greg */
1119 RegTypeGSharedVtInReg,
1120 /* gsharedvt argument passed by addr on stack */
1121 RegTypeGSharedVtOnStack,
1127 guint16 vtsize; /* in param area */
1135 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1140 guint32 stack_usage;
1141 /* The index of the vret arg in the argument list for RegTypeStructByAddr */
1151 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1154 if (*gr > ARMREG_R3) {
1156 ainfo->offset = *stack_size;
1157 ainfo->reg = ARMREG_SP; /* in the caller */
1158 ainfo->storage = RegTypeBase;
1161 ainfo->storage = RegTypeGeneral;
1168 split = i8_align == 4;
1173 if (*gr == ARMREG_R3 && split) {
1174 /* first word in r3 and the second on the stack */
1175 ainfo->offset = *stack_size;
1176 ainfo->reg = ARMREG_SP; /* in the caller */
1177 ainfo->storage = RegTypeBaseGen;
1179 } else if (*gr >= ARMREG_R3) {
1180 if (eabi_supported) {
1181 /* darwin aligns longs to 4 byte only */
1182 if (i8_align == 8) {
1187 ainfo->offset = *stack_size;
1188 ainfo->reg = ARMREG_SP; /* in the caller */
1189 ainfo->storage = RegTypeBase;
1192 if (eabi_supported) {
1193 if (i8_align == 8 && ((*gr) & 1))
1196 ainfo->storage = RegTypeIRegPair;
1205 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1208 * If we're calling a function like this:
1210 * void foo(float a, double b, float c)
1212 * We pass a in s0 and b in d1. That leaves us
1213 * with s1 being unused. The armhf ABI recognizes
1214 * this and requires register assignment to then
1215 * use that for the next single-precision arg,
1216 * i.e. c in this example. So float_spare either
1217 * tells us which reg to use for the next single-
1218 * precision arg, or it's -1, meaning use *fpr.
1220 * Note that even though most of the JIT speaks
1221 * double-precision, fpr represents single-
1222 * precision registers.
1224 * See parts 5.5 and 6.1.2 of the AAPCS for how
1228 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1229 ainfo->storage = RegTypeFP;
1233 * If we're passing a double-precision value
1234 * and *fpr is odd (e.g. it's s1, s3, ...)
1235 * we need to use the next even register. So
1236 * we mark the current *fpr as a spare that
1237 * can be used for the next single-precision
1241 *float_spare = *fpr;
1246 * At this point, we have an even register
1247 * so we assign that and move along.
1251 } else if (*float_spare >= 0) {
1253 * We're passing a single-precision value
1254 * and it looks like a spare single-
1255 * precision register is available. Let's
1259 ainfo->reg = *float_spare;
1263 * If we hit this branch, we're passing a
1264 * single-precision value and we can simply
1265 * use the next available register.
1273 * We've exhausted available floating point
1274 * regs, so pass the rest on the stack.
1282 ainfo->offset = *stack_size;
1283 ainfo->reg = ARMREG_SP;
1284 ainfo->storage = RegTypeBase;
1291 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1295 MonoClassField *field;
1296 MonoType *ftype, *prev_ftype = NULL;
1299 klass = mono_class_from_mono_type (t);
1301 while ((field = mono_class_get_fields (klass, &iter))) {
1302 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1304 ftype = mono_field_get_type (field);
1305 ftype = mini_type_get_underlying_type (NULL, ftype);
1307 if (MONO_TYPE_ISSTRUCT (ftype)) {
1308 int nested_nfields, nested_esize;
1310 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1312 if (nested_esize == 4)
1313 ftype = &mono_defaults.single_class->byval_arg;
1315 ftype = &mono_defaults.double_class->byval_arg;
1316 if (prev_ftype && prev_ftype->type != ftype->type)
1319 nfields += nested_nfields;
1321 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1323 if (prev_ftype && prev_ftype->type != ftype->type)
1329 if (nfields == 0 || nfields > 4)
1331 *out_nfields = nfields;
1332 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1337 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
1339 guint i, gr, fpr, pstart;
1341 int n = sig->hasthis + sig->param_count;
1345 guint32 stack_size = 0;
1347 gboolean is_pinvoke = sig->pinvoke;
1348 gboolean vtype_retaddr = FALSE;
1351 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1353 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1360 t = mini_type_get_underlying_type (gsctx, sig->ret);
1371 case MONO_TYPE_FNPTR:
1372 case MONO_TYPE_CLASS:
1373 case MONO_TYPE_OBJECT:
1374 case MONO_TYPE_SZARRAY:
1375 case MONO_TYPE_ARRAY:
1376 case MONO_TYPE_STRING:
1377 cinfo->ret.storage = RegTypeGeneral;
1378 cinfo->ret.reg = ARMREG_R0;
1382 cinfo->ret.storage = RegTypeIRegPair;
1383 cinfo->ret.reg = ARMREG_R0;
1387 cinfo->ret.storage = RegTypeFP;
1389 if (t->type == MONO_TYPE_R4)
1390 cinfo->ret.size = 4;
1392 cinfo->ret.size = 8;
1394 if (IS_HARD_FLOAT) {
1395 cinfo->ret.reg = ARM_VFP_F0;
1397 cinfo->ret.reg = ARMREG_R0;
1400 case MONO_TYPE_GENERICINST:
1401 if (!mono_type_generic_inst_is_valuetype (t)) {
1402 cinfo->ret.storage = RegTypeGeneral;
1403 cinfo->ret.reg = ARMREG_R0;
1406 // FIXME: Only for variable types
1407 if (mini_is_gsharedvt_type_gsctx (gsctx, t)) {
1408 cinfo->ret.storage = RegTypeStructByAddr;
1412 case MONO_TYPE_VALUETYPE:
1413 case MONO_TYPE_TYPEDBYREF:
1414 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1415 cinfo->ret.storage = RegTypeHFA;
1417 cinfo->ret.nregs = nfields;
1418 cinfo->ret.esize = esize;
1420 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1421 cinfo->ret.storage = RegTypeStructByVal;
1423 cinfo->ret.storage = RegTypeStructByAddr;
1427 case MONO_TYPE_MVAR:
1428 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, t));
1429 cinfo->ret.storage = RegTypeStructByAddr;
1431 case MONO_TYPE_VOID:
1434 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1437 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1442 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1443 * the first argument, allowing 'this' to be always passed in the first arg reg.
1444 * Also do this if the first argument is a reference type, since virtual calls
1445 * are sometimes made using calli without sig->hasthis set, like in the delegate
1448 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1450 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1452 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1456 cinfo->ret.reg = gr;
1458 cinfo->vret_arg_index = 1;
1462 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1465 if (vtype_retaddr) {
1466 cinfo->ret.reg = gr;
1471 DEBUG(printf("params: %d\n", sig->param_count));
1472 for (i = pstart; i < sig->param_count; ++i) {
1473 ArgInfo *ainfo = &cinfo->args [n];
1475 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1476 /* Prevent implicit arguments and sig_cookie from
1477 being passed in registers */
1480 /* Emit the signature cookie just before the implicit arguments */
1481 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1483 DEBUG(printf("param %d: ", i));
1484 if (sig->params [i]->byref) {
1485 DEBUG(printf("byref\n"));
1486 add_general (&gr, &stack_size, ainfo, TRUE);
1490 t = mini_type_get_underlying_type (gsctx, sig->params [i]);
1494 cinfo->args [n].size = 1;
1495 add_general (&gr, &stack_size, ainfo, TRUE);
1499 cinfo->args [n].size = 2;
1500 add_general (&gr, &stack_size, ainfo, TRUE);
1504 cinfo->args [n].size = 4;
1505 add_general (&gr, &stack_size, ainfo, TRUE);
1510 case MONO_TYPE_FNPTR:
1511 case MONO_TYPE_CLASS:
1512 case MONO_TYPE_OBJECT:
1513 case MONO_TYPE_STRING:
1514 case MONO_TYPE_SZARRAY:
1515 case MONO_TYPE_ARRAY:
1516 cinfo->args [n].size = sizeof (gpointer);
1517 add_general (&gr, &stack_size, ainfo, TRUE);
1519 case MONO_TYPE_GENERICINST:
1520 if (!mono_type_generic_inst_is_valuetype (t)) {
1521 cinfo->args [n].size = sizeof (gpointer);
1522 add_general (&gr, &stack_size, ainfo, TRUE);
1525 if (mini_is_gsharedvt_type_gsctx (gsctx, t)) {
1526 /* gsharedvt arguments are passed by ref */
1527 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, t));
1528 add_general (&gr, &stack_size, ainfo, TRUE);
1529 switch (ainfo->storage) {
1530 case RegTypeGeneral:
1531 ainfo->storage = RegTypeGSharedVtInReg;
1534 ainfo->storage = RegTypeGSharedVtOnStack;
1537 g_assert_not_reached ();
1542 case MONO_TYPE_TYPEDBYREF:
1543 case MONO_TYPE_VALUETYPE: {
1546 int nwords, nfields, esize;
1549 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1550 if (fpr + nfields < ARM_VFP_F16) {
1551 ainfo->storage = RegTypeHFA;
1553 ainfo->nregs = nfields;
1554 ainfo->esize = esize;
1562 if (t->type == MONO_TYPE_TYPEDBYREF) {
1563 size = sizeof (MonoTypedRef);
1564 align = sizeof (gpointer);
1566 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1568 size = mono_class_native_size (klass, &align);
1570 size = mini_type_stack_size_full (gsctx, t, &align, FALSE);
1572 DEBUG(printf ("load %d bytes struct\n", size));
1575 align_size += (sizeof (gpointer) - 1);
1576 align_size &= ~(sizeof (gpointer) - 1);
1577 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1578 ainfo->storage = RegTypeStructByVal;
1579 ainfo->struct_size = size;
1580 /* FIXME: align stack_size if needed */
1581 if (eabi_supported) {
1582 if (align >= 8 && (gr & 1))
1585 if (gr > ARMREG_R3) {
1587 ainfo->vtsize = nwords;
1589 int rest = ARMREG_R3 - gr + 1;
1590 int n_in_regs = rest >= nwords? nwords: rest;
1592 ainfo->size = n_in_regs;
1593 ainfo->vtsize = nwords - n_in_regs;
1596 nwords -= n_in_regs;
1598 if (sig->call_convention == MONO_CALL_VARARG)
1599 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1600 stack_size = ALIGN_TO (stack_size, align);
1601 ainfo->offset = stack_size;
1602 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1603 stack_size += nwords * sizeof (gpointer);
1609 add_general (&gr, &stack_size, ainfo, FALSE);
1615 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1617 add_general (&gr, &stack_size, ainfo, TRUE);
1623 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1625 add_general (&gr, &stack_size, ainfo, FALSE);
1628 case MONO_TYPE_MVAR:
1629 /* gsharedvt arguments are passed by ref */
1630 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, t));
1631 add_general (&gr, &stack_size, ainfo, TRUE);
1632 switch (ainfo->storage) {
1633 case RegTypeGeneral:
1634 ainfo->storage = RegTypeGSharedVtInReg;
1637 ainfo->storage = RegTypeGSharedVtOnStack;
1640 g_assert_not_reached ();
1644 g_error ("Can't handle 0x%x", sig->params [i]->type);
1649 /* Handle the case where there are no implicit arguments */
1650 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1651 /* Prevent implicit arguments and sig_cookie from
1652 being passed in registers */
1655 /* Emit the signature cookie just before the implicit arguments */
1656 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1659 /* align stack size to 8 */
1660 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1661 stack_size = (stack_size + 7) & ~7;
1663 cinfo->stack_usage = stack_size;
1669 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1671 MonoType *callee_ret;
1675 c1 = get_call_info (NULL, NULL, caller_sig);
1676 c2 = get_call_info (NULL, NULL, callee_sig);
1679 * Tail calls with more callee stack usage than the caller cannot be supported, since
1680 * the extra stack space would be left on the stack after the tail call.
1682 res = c1->stack_usage >= c2->stack_usage;
1683 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1684 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1685 /* An address on the callee's stack is passed as the first argument */
1688 if (c2->stack_usage > 16 * 4)
1700 debug_omit_fp (void)
1703 return mono_debug_count ();
1710 * mono_arch_compute_omit_fp:
1712 * Determine whenever the frame pointer can be eliminated.
1715 mono_arch_compute_omit_fp (MonoCompile *cfg)
1717 MonoMethodSignature *sig;
1718 MonoMethodHeader *header;
1722 if (cfg->arch.omit_fp_computed)
1725 header = cfg->header;
1727 sig = mono_method_signature (cfg->method);
1729 if (!cfg->arch.cinfo)
1730 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1731 cinfo = cfg->arch.cinfo;
1734 * FIXME: Remove some of the restrictions.
1736 cfg->arch.omit_fp = TRUE;
1737 cfg->arch.omit_fp_computed = TRUE;
1739 if (cfg->disable_omit_fp)
1740 cfg->arch.omit_fp = FALSE;
1741 if (!debug_omit_fp ())
1742 cfg->arch.omit_fp = FALSE;
1744 if (cfg->method->save_lmf)
1745 cfg->arch.omit_fp = FALSE;
1747 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1748 cfg->arch.omit_fp = FALSE;
1749 if (header->num_clauses)
1750 cfg->arch.omit_fp = FALSE;
1751 if (cfg->param_area)
1752 cfg->arch.omit_fp = FALSE;
1753 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1754 cfg->arch.omit_fp = FALSE;
1755 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1756 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1757 cfg->arch.omit_fp = FALSE;
1758 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1759 ArgInfo *ainfo = &cinfo->args [i];
1761 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1763 * The stack offset can only be determined when the frame
1766 cfg->arch.omit_fp = FALSE;
1771 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1772 MonoInst *ins = cfg->varinfo [i];
1775 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1780 * Set var information according to the calling convention. arm version.
1781 * The locals var stuff should most likely be split in another method.
1784 mono_arch_allocate_vars (MonoCompile *cfg)
1786 MonoMethodSignature *sig;
1787 MonoMethodHeader *header;
1790 int i, offset, size, align, curinst;
1795 sig = mono_method_signature (cfg->method);
1797 if (!cfg->arch.cinfo)
1798 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1799 cinfo = cfg->arch.cinfo;
1800 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1802 mono_arch_compute_omit_fp (cfg);
1804 if (cfg->arch.omit_fp)
1805 cfg->frame_reg = ARMREG_SP;
1807 cfg->frame_reg = ARMREG_FP;
1809 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1811 /* allow room for the vararg method args: void* and long/double */
1812 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1813 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1815 header = cfg->header;
1817 /* See mono_arch_get_global_int_regs () */
1818 if (cfg->flags & MONO_CFG_HAS_CALLS)
1819 cfg->uses_rgctx_reg = TRUE;
1821 if (cfg->frame_reg != ARMREG_SP)
1822 cfg->used_int_regs |= 1 << cfg->frame_reg;
1824 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1825 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1826 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1830 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1831 if (sig_ret->type != MONO_TYPE_VOID) {
1832 cfg->ret->opcode = OP_REGVAR;
1833 cfg->ret->inst_c0 = ARMREG_R0;
1836 /* local vars are at a positive offset from the stack pointer */
1838 * also note that if the function uses alloca, we use FP
1839 * to point at the local variables.
1841 offset = 0; /* linkage area */
1842 /* align the offset to 16 bytes: not sure this is needed here */
1844 //offset &= ~(8 - 1);
1846 /* add parameter area size for called functions */
1847 offset += cfg->param_area;
1850 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1853 /* allow room to save the return value */
1854 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1857 switch (cinfo->ret.storage) {
1858 case RegTypeStructByVal:
1859 cfg->ret->opcode = OP_REGOFFSET;
1860 cfg->ret->inst_basereg = cfg->frame_reg;
1861 offset += sizeof (gpointer) - 1;
1862 offset &= ~(sizeof (gpointer) - 1);
1863 cfg->ret->inst_offset = - offset;
1864 offset += sizeof(gpointer);
1867 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1868 offset = ALIGN_TO (offset, 8);
1869 cfg->ret->opcode = OP_REGOFFSET;
1870 cfg->ret->inst_basereg = cfg->frame_reg;
1871 cfg->ret->inst_offset = offset;
1875 case RegTypeStructByAddr:
1876 ins = cfg->vret_addr;
1877 offset += sizeof(gpointer) - 1;
1878 offset &= ~(sizeof(gpointer) - 1);
1879 ins->inst_offset = offset;
1880 ins->opcode = OP_REGOFFSET;
1881 ins->inst_basereg = cfg->frame_reg;
1882 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1883 printf ("vret_addr =");
1884 mono_print_ins (cfg->vret_addr);
1886 offset += sizeof(gpointer);
1892 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1893 if (cfg->arch.seq_point_info_var) {
1896 ins = cfg->arch.seq_point_info_var;
1900 offset += align - 1;
1901 offset &= ~(align - 1);
1902 ins->opcode = OP_REGOFFSET;
1903 ins->inst_basereg = cfg->frame_reg;
1904 ins->inst_offset = offset;
1907 ins = cfg->arch.ss_trigger_page_var;
1910 offset += align - 1;
1911 offset &= ~(align - 1);
1912 ins->opcode = OP_REGOFFSET;
1913 ins->inst_basereg = cfg->frame_reg;
1914 ins->inst_offset = offset;
1918 if (cfg->arch.seq_point_read_var) {
1921 ins = cfg->arch.seq_point_read_var;
1925 offset += align - 1;
1926 offset &= ~(align - 1);
1927 ins->opcode = OP_REGOFFSET;
1928 ins->inst_basereg = cfg->frame_reg;
1929 ins->inst_offset = offset;
1932 ins = cfg->arch.seq_point_ss_method_var;
1935 offset += align - 1;
1936 offset &= ~(align - 1);
1937 ins->opcode = OP_REGOFFSET;
1938 ins->inst_basereg = cfg->frame_reg;
1939 ins->inst_offset = offset;
1942 ins = cfg->arch.seq_point_bp_method_var;
1945 offset += align - 1;
1946 offset &= ~(align - 1);
1947 ins->opcode = OP_REGOFFSET;
1948 ins->inst_basereg = cfg->frame_reg;
1949 ins->inst_offset = offset;
1953 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1954 /* Allocate a temporary used by the atomic ops */
1958 /* Allocate a local slot to hold the sig cookie address */
1959 offset += align - 1;
1960 offset &= ~(align - 1);
1961 cfg->arch.atomic_tmp_offset = offset;
1964 cfg->arch.atomic_tmp_offset = -1;
1967 cfg->locals_min_stack_offset = offset;
1969 curinst = cfg->locals_start;
1970 for (i = curinst; i < cfg->num_varinfo; ++i) {
1973 ins = cfg->varinfo [i];
1974 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1977 t = ins->inst_vtype;
1978 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (cfg, t))
1981 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1982 * pinvoke wrappers when they call functions returning structure */
1983 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1984 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1988 size = mono_type_size (t, &align);
1990 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1991 * since it loads/stores misaligned words, which don't do the right thing.
1993 if (align < 4 && size >= 4)
1995 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1996 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1997 offset += align - 1;
1998 offset &= ~(align - 1);
1999 ins->opcode = OP_REGOFFSET;
2000 ins->inst_offset = offset;
2001 ins->inst_basereg = cfg->frame_reg;
2003 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2006 cfg->locals_max_stack_offset = offset;
2010 ins = cfg->args [curinst];
2011 if (ins->opcode != OP_REGVAR) {
2012 ins->opcode = OP_REGOFFSET;
2013 ins->inst_basereg = cfg->frame_reg;
2014 offset += sizeof (gpointer) - 1;
2015 offset &= ~(sizeof (gpointer) - 1);
2016 ins->inst_offset = offset;
2017 offset += sizeof (gpointer);
2022 if (sig->call_convention == MONO_CALL_VARARG) {
2026 /* Allocate a local slot to hold the sig cookie address */
2027 offset += align - 1;
2028 offset &= ~(align - 1);
2029 cfg->sig_cookie = offset;
2033 for (i = 0; i < sig->param_count; ++i) {
2034 ainfo = cinfo->args + i;
2036 ins = cfg->args [curinst];
2038 switch (ainfo->storage) {
2040 offset = ALIGN_TO (offset, 8);
2041 ins->opcode = OP_REGOFFSET;
2042 ins->inst_basereg = cfg->frame_reg;
2043 /* These arguments are saved to the stack in the prolog */
2044 ins->inst_offset = offset;
2045 if (cfg->verbose_level >= 2)
2046 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2054 if (ins->opcode != OP_REGVAR) {
2055 ins->opcode = OP_REGOFFSET;
2056 ins->inst_basereg = cfg->frame_reg;
2057 size = mini_type_stack_size_full (cfg->generic_sharing_context, sig->params [i], &ualign, sig->pinvoke);
2059 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2060 * since it loads/stores misaligned words, which don't do the right thing.
2062 if (align < 4 && size >= 4)
2064 /* The code in the prolog () stores words when storing vtypes received in a register */
2065 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2067 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2068 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2069 offset += align - 1;
2070 offset &= ~(align - 1);
2071 ins->inst_offset = offset;
2077 /* align the offset to 8 bytes */
2078 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2079 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2084 cfg->stack_offset = offset;
2088 mono_arch_create_vars (MonoCompile *cfg)
2090 MonoMethodSignature *sig;
2094 sig = mono_method_signature (cfg->method);
2096 if (!cfg->arch.cinfo)
2097 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2098 cinfo = cfg->arch.cinfo;
2100 if (IS_HARD_FLOAT) {
2101 for (i = 0; i < 2; i++) {
2102 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2103 inst->flags |= MONO_INST_VOLATILE;
2105 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2109 if (cinfo->ret.storage == RegTypeStructByVal)
2110 cfg->ret_var_is_local = TRUE;
2112 if (cinfo->ret.storage == RegTypeStructByAddr) {
2113 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2114 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2115 printf ("vret_addr = ");
2116 mono_print_ins (cfg->vret_addr);
2120 if (cfg->gen_sdb_seq_points) {
2121 if (cfg->soft_breakpoints) {
2122 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2123 ins->flags |= MONO_INST_VOLATILE;
2124 cfg->arch.seq_point_read_var = ins;
2126 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2127 ins->flags |= MONO_INST_VOLATILE;
2128 cfg->arch.seq_point_ss_method_var = ins;
2130 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2131 ins->flags |= MONO_INST_VOLATILE;
2132 cfg->arch.seq_point_bp_method_var = ins;
2134 g_assert (!cfg->compile_aot);
2135 } else if (cfg->compile_aot) {
2136 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2137 ins->flags |= MONO_INST_VOLATILE;
2138 cfg->arch.seq_point_info_var = ins;
2140 /* Allocate a separate variable for this to save 1 load per seq point */
2141 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2142 ins->flags |= MONO_INST_VOLATILE;
2143 cfg->arch.ss_trigger_page_var = ins;
2149 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2151 MonoMethodSignature *tmp_sig;
2154 if (call->tail_call)
2157 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2160 * mono_ArgIterator_Setup assumes the signature cookie is
2161 * passed first and all the arguments which were before it are
2162 * passed on the stack after the signature. So compensate by
2163 * passing a different signature.
2165 tmp_sig = mono_metadata_signature_dup (call->signature);
2166 tmp_sig->param_count -= call->signature->sentinelpos;
2167 tmp_sig->sentinelpos = 0;
2168 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2170 sig_reg = mono_alloc_ireg (cfg);
2171 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2173 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2178 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2183 LLVMCallInfo *linfo;
2185 n = sig->param_count + sig->hasthis;
2187 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2189 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2192 * LLVM always uses the native ABI while we use our own ABI, the
2193 * only difference is the handling of vtypes:
2194 * - we only pass/receive them in registers in some cases, and only
2195 * in 1 or 2 integer registers.
2197 if (cinfo->ret.storage == RegTypeStructByAddr) {
2198 /* Vtype returned using a hidden argument */
2199 linfo->ret.storage = LLVMArgVtypeRetAddr;
2200 linfo->vret_arg_index = cinfo->vret_arg_index;
2201 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
2202 cfg->exception_message = g_strdup ("unknown ret conv");
2203 cfg->disable_llvm = TRUE;
2207 for (i = 0; i < n; ++i) {
2208 ainfo = cinfo->args + i;
2210 linfo->args [i].storage = LLVMArgNone;
2212 switch (ainfo->storage) {
2213 case RegTypeGeneral:
2214 case RegTypeIRegPair:
2216 linfo->args [i].storage = LLVMArgInIReg;
2218 case RegTypeStructByVal:
2219 linfo->args [i].storage = LLVMArgAsIArgs;
2220 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2223 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2224 cfg->disable_llvm = TRUE;
2234 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2237 MonoMethodSignature *sig;
2241 sig = call->signature;
2242 n = sig->param_count + sig->hasthis;
2244 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2246 switch (cinfo->ret.storage) {
2247 case RegTypeStructByVal:
2248 /* The JIT will transform this into a normal call */
2249 call->vret_in_reg = TRUE;
2253 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2254 * the location pointed to by it after call in emit_move_return_value ().
2256 if (!cfg->arch.vret_addr_loc) {
2257 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2258 /* Prevent it from being register allocated or optimized away */
2259 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2262 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2264 case RegTypeStructByAddr: {
2266 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2267 vtarg->sreg1 = call->vret_var->dreg;
2268 vtarg->dreg = mono_alloc_preg (cfg);
2269 MONO_ADD_INS (cfg->cbb, vtarg);
2271 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2278 for (i = 0; i < n; ++i) {
2279 ArgInfo *ainfo = cinfo->args + i;
2282 if (i >= sig->hasthis)
2283 t = sig->params [i - sig->hasthis];
2285 t = &mono_defaults.int_class->byval_arg;
2286 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
2288 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2289 /* Emit the signature cookie just before the implicit arguments */
2290 emit_sig_cookie (cfg, call, cinfo);
2293 in = call->args [i];
2295 switch (ainfo->storage) {
2296 case RegTypeGeneral:
2297 case RegTypeIRegPair:
2298 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2299 MONO_INST_NEW (cfg, ins, OP_MOVE);
2300 ins->dreg = mono_alloc_ireg (cfg);
2301 ins->sreg1 = in->dreg + 1;
2302 MONO_ADD_INS (cfg->cbb, ins);
2303 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2305 MONO_INST_NEW (cfg, ins, OP_MOVE);
2306 ins->dreg = mono_alloc_ireg (cfg);
2307 ins->sreg1 = in->dreg + 2;
2308 MONO_ADD_INS (cfg->cbb, ins);
2309 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2310 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2311 if (ainfo->size == 4) {
2312 if (IS_SOFT_FLOAT) {
2313 /* mono_emit_call_args () have already done the r8->r4 conversion */
2314 /* The converted value is in an int vreg */
2315 MONO_INST_NEW (cfg, ins, OP_MOVE);
2316 ins->dreg = mono_alloc_ireg (cfg);
2317 ins->sreg1 = in->dreg;
2318 MONO_ADD_INS (cfg->cbb, ins);
2319 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2323 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2324 creg = mono_alloc_ireg (cfg);
2325 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2326 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2329 if (IS_SOFT_FLOAT) {
2330 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2331 ins->dreg = mono_alloc_ireg (cfg);
2332 ins->sreg1 = in->dreg;
2333 MONO_ADD_INS (cfg->cbb, ins);
2334 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2336 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2337 ins->dreg = mono_alloc_ireg (cfg);
2338 ins->sreg1 = in->dreg;
2339 MONO_ADD_INS (cfg->cbb, ins);
2340 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2344 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2345 creg = mono_alloc_ireg (cfg);
2346 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2347 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2348 creg = mono_alloc_ireg (cfg);
2349 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2350 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2353 cfg->flags |= MONO_CFG_HAS_FPOUT;
2355 MONO_INST_NEW (cfg, ins, OP_MOVE);
2356 ins->dreg = mono_alloc_ireg (cfg);
2357 ins->sreg1 = in->dreg;
2358 MONO_ADD_INS (cfg->cbb, ins);
2360 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2363 case RegTypeStructByAddr:
2366 /* FIXME: where si the data allocated? */
2367 arg->backend.reg3 = ainfo->reg;
2368 call->used_iregs |= 1 << ainfo->reg;
2369 g_assert_not_reached ();
2372 case RegTypeStructByVal:
2373 case RegTypeGSharedVtInReg:
2374 case RegTypeGSharedVtOnStack:
2376 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2377 ins->opcode = OP_OUTARG_VT;
2378 ins->sreg1 = in->dreg;
2379 ins->klass = in->klass;
2380 ins->inst_p0 = call;
2381 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2382 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2383 mono_call_inst_add_outarg_vt (cfg, call, ins);
2384 MONO_ADD_INS (cfg->cbb, ins);
2387 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2388 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2389 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2390 if (t->type == MONO_TYPE_R8) {
2391 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2394 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2396 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2399 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2402 case RegTypeBaseGen:
2403 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2404 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
2405 MONO_INST_NEW (cfg, ins, OP_MOVE);
2406 ins->dreg = mono_alloc_ireg (cfg);
2407 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
2408 MONO_ADD_INS (cfg->cbb, ins);
2409 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2410 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2413 /* This should work for soft-float as well */
2415 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2416 creg = mono_alloc_ireg (cfg);
2417 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2418 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2419 creg = mono_alloc_ireg (cfg);
2420 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2421 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2422 cfg->flags |= MONO_CFG_HAS_FPOUT;
2424 g_assert_not_reached ();
2428 int fdreg = mono_alloc_freg (cfg);
2430 if (ainfo->size == 8) {
2431 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2432 ins->sreg1 = in->dreg;
2434 MONO_ADD_INS (cfg->cbb, ins);
2436 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2441 * Mono's register allocator doesn't speak single-precision registers that
2442 * overlap double-precision registers (i.e. armhf). So we have to work around
2443 * the register allocator and load the value from memory manually.
2445 * So we create a variable for the float argument and an instruction to store
2446 * the argument into the variable. We then store the list of these arguments
2447 * in cfg->float_args. This list is then used by emit_float_args later to
2448 * pass the arguments in the various call opcodes.
2450 * This is not very nice, and we should really try to fix the allocator.
2453 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2455 /* Make sure the instruction isn't seen as pointless and removed.
2457 float_arg->flags |= MONO_INST_VOLATILE;
2459 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2461 /* We use the dreg to look up the instruction later. The hreg is used to
2462 * emit the instruction that loads the value into the FP reg.
2464 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2465 fad->vreg = float_arg->dreg;
2466 fad->hreg = ainfo->reg;
2468 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2471 call->used_iregs |= 1 << ainfo->reg;
2472 cfg->flags |= MONO_CFG_HAS_FPOUT;
2476 g_assert_not_reached ();
2480 /* Handle the case where there are no implicit arguments */
2481 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2482 emit_sig_cookie (cfg, call, cinfo);
2484 call->call_info = cinfo;
2485 call->stack_usage = cinfo->stack_usage;
2489 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2495 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2496 ins->dreg = mono_alloc_freg (cfg);
2497 ins->sreg1 = arg->dreg;
2498 MONO_ADD_INS (cfg->cbb, ins);
2499 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2502 g_assert_not_reached ();
2508 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2510 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2512 ArgInfo *ainfo = ins->inst_p1;
2513 int ovf_size = ainfo->vtsize;
2514 int doffset = ainfo->offset;
2515 int struct_size = ainfo->struct_size;
2516 int i, soffset, dreg, tmpreg;
2518 switch (ainfo->storage) {
2519 case RegTypeGSharedVtInReg:
2521 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2523 case RegTypeGSharedVtOnStack:
2524 /* Pass by addr on stack */
2525 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2528 for (i = 0; i < ainfo->nregs; ++i) {
2529 if (ainfo->esize == 4)
2530 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2532 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2533 load->dreg = mono_alloc_freg (cfg);
2534 load->inst_basereg = src->dreg;
2535 load->inst_offset = i * ainfo->esize;
2536 MONO_ADD_INS (cfg->cbb, load);
2538 if (ainfo->esize == 4) {
2541 /* See RegTypeFP in mono_arch_emit_call () */
2542 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2543 float_arg->flags |= MONO_INST_VOLATILE;
2544 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2546 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2547 fad->vreg = float_arg->dreg;
2548 fad->hreg = ainfo->reg + i;
2550 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2552 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + i, load);
2558 for (i = 0; i < ainfo->size; ++i) {
2559 dreg = mono_alloc_ireg (cfg);
2560 switch (struct_size) {
2562 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2565 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2568 tmpreg = mono_alloc_ireg (cfg);
2569 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2570 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2571 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2572 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2573 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2574 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2575 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2578 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2581 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2582 soffset += sizeof (gpointer);
2583 struct_size -= sizeof (gpointer);
2585 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2587 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2593 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2595 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2598 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2601 if (COMPILE_LLVM (cfg)) {
2602 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2604 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2605 ins->sreg1 = val->dreg + 1;
2606 ins->sreg2 = val->dreg + 2;
2607 MONO_ADD_INS (cfg->cbb, ins);
2612 case MONO_ARM_FPU_NONE:
2613 if (ret->type == MONO_TYPE_R8) {
2616 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2617 ins->dreg = cfg->ret->dreg;
2618 ins->sreg1 = val->dreg;
2619 MONO_ADD_INS (cfg->cbb, ins);
2622 if (ret->type == MONO_TYPE_R4) {
2623 /* Already converted to an int in method_to_ir () */
2624 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2628 case MONO_ARM_FPU_VFP:
2629 case MONO_ARM_FPU_VFP_HARD:
2630 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2633 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2634 ins->dreg = cfg->ret->dreg;
2635 ins->sreg1 = val->dreg;
2636 MONO_ADD_INS (cfg->cbb, ins);
2641 g_assert_not_reached ();
2645 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2648 #endif /* #ifndef DISABLE_JIT */
2651 mono_arch_is_inst_imm (gint64 imm)
2657 MonoMethodSignature *sig;
2660 MonoType **param_types;
2664 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2668 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2671 switch (cinfo->ret.storage) {
2673 case RegTypeGeneral:
2674 case RegTypeIRegPair:
2675 case RegTypeStructByAddr:
2686 for (i = 0; i < cinfo->nargs; ++i) {
2687 ArgInfo *ainfo = &cinfo->args [i];
2690 switch (ainfo->storage) {
2691 case RegTypeGeneral:
2693 case RegTypeIRegPair:
2696 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2699 case RegTypeStructByVal:
2700 if (ainfo->size == 0)
2701 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2703 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2704 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2712 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2713 for (i = 0; i < sig->param_count; ++i) {
2714 MonoType *t = sig->params [i];
2719 t = mini_replace_type (t);
2742 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2744 ArchDynCallInfo *info;
2748 cinfo = get_call_info (NULL, NULL, sig);
2750 if (!dyn_call_supported (cinfo, sig)) {
2755 info = g_new0 (ArchDynCallInfo, 1);
2756 // FIXME: Preprocess the info to speed up start_dyn_call ()
2758 info->cinfo = cinfo;
2759 info->rtype = mini_type_get_underlying_type (NULL, sig->ret);
2760 info->param_types = g_new0 (MonoType*, sig->param_count);
2761 for (i = 0; i < sig->param_count; ++i)
2762 info->param_types [i] = mini_type_get_underlying_type (NULL, sig->params [i]);
2764 return (MonoDynCallInfo*)info;
2768 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2770 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2772 g_free (ainfo->cinfo);
2777 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2779 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2780 DynCallArgs *p = (DynCallArgs*)buf;
2781 int arg_index, greg, i, j, pindex;
2782 MonoMethodSignature *sig = dinfo->sig;
2784 g_assert (buf_len >= sizeof (DynCallArgs));
2793 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2794 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2799 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2800 p->regs [greg ++] = (mgreg_t)ret;
2802 for (i = pindex; i < sig->param_count; i++) {
2803 MonoType *t = dinfo->param_types [i];
2804 gpointer *arg = args [arg_index ++];
2805 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2808 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2810 else if (ainfo->storage == RegTypeBase)
2811 slot = PARAM_REGS + (ainfo->offset / 4);
2813 g_assert_not_reached ();
2816 p->regs [slot] = (mgreg_t)*arg;
2821 case MONO_TYPE_STRING:
2822 case MONO_TYPE_CLASS:
2823 case MONO_TYPE_ARRAY:
2824 case MONO_TYPE_SZARRAY:
2825 case MONO_TYPE_OBJECT:
2829 p->regs [slot] = (mgreg_t)*arg;
2832 p->regs [slot] = *(guint8*)arg;
2835 p->regs [slot] = *(gint8*)arg;
2838 p->regs [slot] = *(gint16*)arg;
2841 p->regs [slot] = *(guint16*)arg;
2844 p->regs [slot] = *(gint32*)arg;
2847 p->regs [slot] = *(guint32*)arg;
2851 p->regs [slot ++] = (mgreg_t)arg [0];
2852 p->regs [slot] = (mgreg_t)arg [1];
2855 p->regs [slot] = *(mgreg_t*)arg;
2858 p->regs [slot ++] = (mgreg_t)arg [0];
2859 p->regs [slot] = (mgreg_t)arg [1];
2861 case MONO_TYPE_GENERICINST:
2862 if (MONO_TYPE_IS_REFERENCE (t)) {
2863 p->regs [slot] = (mgreg_t)*arg;
2868 case MONO_TYPE_VALUETYPE:
2869 g_assert (ainfo->storage == RegTypeStructByVal);
2871 if (ainfo->size == 0)
2872 slot = PARAM_REGS + (ainfo->offset / 4);
2876 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2877 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2880 g_assert_not_reached ();
2886 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2888 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2889 MonoType *ptype = ainfo->rtype;
2890 guint8 *ret = ((DynCallArgs*)buf)->ret;
2891 mgreg_t res = ((DynCallArgs*)buf)->res;
2892 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2894 switch (ptype->type) {
2895 case MONO_TYPE_VOID:
2896 *(gpointer*)ret = NULL;
2898 case MONO_TYPE_STRING:
2899 case MONO_TYPE_CLASS:
2900 case MONO_TYPE_ARRAY:
2901 case MONO_TYPE_SZARRAY:
2902 case MONO_TYPE_OBJECT:
2906 *(gpointer*)ret = (gpointer)res;
2912 *(guint8*)ret = res;
2915 *(gint16*)ret = res;
2918 *(guint16*)ret = res;
2921 *(gint32*)ret = res;
2924 *(guint32*)ret = res;
2928 /* This handles endianness as well */
2929 ((gint32*)ret) [0] = res;
2930 ((gint32*)ret) [1] = res2;
2932 case MONO_TYPE_GENERICINST:
2933 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2934 *(gpointer*)ret = (gpointer)res;
2939 case MONO_TYPE_VALUETYPE:
2940 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2945 *(float*)ret = *(float*)&res;
2947 case MONO_TYPE_R8: {
2954 *(double*)ret = *(double*)®s;
2958 g_assert_not_reached ();
2965 * Allow tracing to work with this interface (with an optional argument)
2969 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2973 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2974 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2975 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2976 code = emit_call_reg (code, ARMREG_R2);
2990 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2993 int save_mode = SAVE_NONE;
2995 MonoMethod *method = cfg->method;
2996 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2997 int rtype = ret_type->type;
2998 int save_offset = cfg->param_area;
3002 offset = code - cfg->native_code;
3003 /* we need about 16 instructions */
3004 if (offset > (cfg->code_size - 16 * 4)) {
3005 cfg->code_size *= 2;
3006 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3007 code = cfg->native_code + offset;
3010 case MONO_TYPE_VOID:
3011 /* special case string .ctor icall */
3012 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3013 save_mode = SAVE_ONE;
3015 save_mode = SAVE_NONE;
3019 save_mode = SAVE_TWO;
3023 save_mode = SAVE_ONE_FP;
3025 save_mode = SAVE_ONE;
3029 save_mode = SAVE_TWO_FP;
3031 save_mode = SAVE_TWO;
3033 case MONO_TYPE_GENERICINST:
3034 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3035 save_mode = SAVE_ONE;
3039 case MONO_TYPE_VALUETYPE:
3040 save_mode = SAVE_STRUCT;
3043 save_mode = SAVE_ONE;
3047 switch (save_mode) {
3049 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3050 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3051 if (enable_arguments) {
3052 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3053 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3057 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3058 if (enable_arguments) {
3059 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3063 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3064 if (enable_arguments) {
3065 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3069 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3070 if (enable_arguments) {
3071 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3075 if (enable_arguments) {
3076 /* FIXME: get the actual address */
3077 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3085 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3086 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3087 code = emit_call_reg (code, ARMREG_IP);
3089 switch (save_mode) {
3091 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3092 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3095 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3098 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3101 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3112 * The immediate field for cond branches is big enough for all reasonable methods
3114 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3115 if (0 && ins->inst_true_bb->native_offset) { \
3116 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3118 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3119 ARM_B_COND (code, (condcode), 0); \
3122 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3124 /* emit an exception if condition is fail
3126 * We assign the extra code used to throw the implicit exceptions
3127 * to cfg->bb_exit as far as the big branch handling is concerned
3129 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3131 mono_add_patch_info (cfg, code - cfg->native_code, \
3132 MONO_PATCH_INFO_EXC, exc_name); \
3133 ARM_BL_COND (code, (condcode), 0); \
3136 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3139 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3144 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3148 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3149 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3151 switch (ins->opcode) {
3154 /* Already done by an arch-independent pass */
3156 case OP_LOAD_MEMBASE:
3157 case OP_LOADI4_MEMBASE:
3159 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3160 * OP_LOAD_MEMBASE offset(basereg), reg
3162 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3163 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3164 ins->inst_basereg == last_ins->inst_destbasereg &&
3165 ins->inst_offset == last_ins->inst_offset) {
3166 if (ins->dreg == last_ins->sreg1) {
3167 MONO_DELETE_INS (bb, ins);
3170 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3171 ins->opcode = OP_MOVE;
3172 ins->sreg1 = last_ins->sreg1;
3176 * Note: reg1 must be different from the basereg in the second load
3177 * OP_LOAD_MEMBASE offset(basereg), reg1
3178 * OP_LOAD_MEMBASE offset(basereg), reg2
3180 * OP_LOAD_MEMBASE offset(basereg), reg1
3181 * OP_MOVE reg1, reg2
3183 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3184 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3185 ins->inst_basereg != last_ins->dreg &&
3186 ins->inst_basereg == last_ins->inst_basereg &&
3187 ins->inst_offset == last_ins->inst_offset) {
3189 if (ins->dreg == last_ins->dreg) {
3190 MONO_DELETE_INS (bb, ins);
3193 ins->opcode = OP_MOVE;
3194 ins->sreg1 = last_ins->dreg;
3197 //g_assert_not_reached ();
3201 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3202 * OP_LOAD_MEMBASE offset(basereg), reg
3204 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3205 * OP_ICONST reg, imm
3207 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3208 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3209 ins->inst_basereg == last_ins->inst_destbasereg &&
3210 ins->inst_offset == last_ins->inst_offset) {
3211 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3212 ins->opcode = OP_ICONST;
3213 ins->inst_c0 = last_ins->inst_imm;
3214 g_assert_not_reached (); // check this rule
3218 case OP_LOADU1_MEMBASE:
3219 case OP_LOADI1_MEMBASE:
3220 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3221 ins->inst_basereg == last_ins->inst_destbasereg &&
3222 ins->inst_offset == last_ins->inst_offset) {
3223 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3224 ins->sreg1 = last_ins->sreg1;
3227 case OP_LOADU2_MEMBASE:
3228 case OP_LOADI2_MEMBASE:
3229 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3230 ins->inst_basereg == last_ins->inst_destbasereg &&
3231 ins->inst_offset == last_ins->inst_offset) {
3232 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3233 ins->sreg1 = last_ins->sreg1;
3237 ins->opcode = OP_MOVE;
3241 if (ins->dreg == ins->sreg1) {
3242 MONO_DELETE_INS (bb, ins);
3246 * OP_MOVE sreg, dreg
3247 * OP_MOVE dreg, sreg
3249 if (last_ins && last_ins->opcode == OP_MOVE &&
3250 ins->sreg1 == last_ins->dreg &&
3251 ins->dreg == last_ins->sreg1) {
3252 MONO_DELETE_INS (bb, ins);
3261 * the branch_cc_table should maintain the order of these
3275 branch_cc_table [] = {
3289 #define ADD_NEW_INS(cfg,dest,op) do { \
3290 MONO_INST_NEW ((cfg), (dest), (op)); \
3291 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3295 map_to_reg_reg_op (int op)
3304 case OP_COMPARE_IMM:
3306 case OP_ICOMPARE_IMM:
3320 case OP_LOAD_MEMBASE:
3321 return OP_LOAD_MEMINDEX;
3322 case OP_LOADI4_MEMBASE:
3323 return OP_LOADI4_MEMINDEX;
3324 case OP_LOADU4_MEMBASE:
3325 return OP_LOADU4_MEMINDEX;
3326 case OP_LOADU1_MEMBASE:
3327 return OP_LOADU1_MEMINDEX;
3328 case OP_LOADI2_MEMBASE:
3329 return OP_LOADI2_MEMINDEX;
3330 case OP_LOADU2_MEMBASE:
3331 return OP_LOADU2_MEMINDEX;
3332 case OP_LOADI1_MEMBASE:
3333 return OP_LOADI1_MEMINDEX;
3334 case OP_STOREI1_MEMBASE_REG:
3335 return OP_STOREI1_MEMINDEX;
3336 case OP_STOREI2_MEMBASE_REG:
3337 return OP_STOREI2_MEMINDEX;
3338 case OP_STOREI4_MEMBASE_REG:
3339 return OP_STOREI4_MEMINDEX;
3340 case OP_STORE_MEMBASE_REG:
3341 return OP_STORE_MEMINDEX;
3342 case OP_STORER4_MEMBASE_REG:
3343 return OP_STORER4_MEMINDEX;
3344 case OP_STORER8_MEMBASE_REG:
3345 return OP_STORER8_MEMINDEX;
3346 case OP_STORE_MEMBASE_IMM:
3347 return OP_STORE_MEMBASE_REG;
3348 case OP_STOREI1_MEMBASE_IMM:
3349 return OP_STOREI1_MEMBASE_REG;
3350 case OP_STOREI2_MEMBASE_IMM:
3351 return OP_STOREI2_MEMBASE_REG;
3352 case OP_STOREI4_MEMBASE_IMM:
3353 return OP_STOREI4_MEMBASE_REG;
3355 g_assert_not_reached ();
3359 * Remove from the instruction list the instructions that can't be
3360 * represented with very simple instructions with no register
3364 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3366 MonoInst *ins, *temp, *last_ins = NULL;
3367 int rot_amount, imm8, low_imm;
3369 MONO_BB_FOR_EACH_INS (bb, ins) {
3371 switch (ins->opcode) {
3375 case OP_COMPARE_IMM:
3376 case OP_ICOMPARE_IMM:
3390 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3391 ADD_NEW_INS (cfg, temp, OP_ICONST);
3392 temp->inst_c0 = ins->inst_imm;
3393 temp->dreg = mono_alloc_ireg (cfg);
3394 ins->sreg2 = temp->dreg;
3395 ins->opcode = mono_op_imm_to_op (ins->opcode);
3397 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3403 if (ins->inst_imm == 1) {
3404 ins->opcode = OP_MOVE;
3407 if (ins->inst_imm == 0) {
3408 ins->opcode = OP_ICONST;
3412 imm8 = mono_is_power_of_two (ins->inst_imm);
3414 ins->opcode = OP_SHL_IMM;
3415 ins->inst_imm = imm8;
3418 ADD_NEW_INS (cfg, temp, OP_ICONST);
3419 temp->inst_c0 = ins->inst_imm;
3420 temp->dreg = mono_alloc_ireg (cfg);
3421 ins->sreg2 = temp->dreg;
3422 ins->opcode = OP_IMUL;
3428 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3429 /* ARM sets the C flag to 1 if there was _no_ overflow */
3430 ins->next->opcode = OP_COND_EXC_NC;
3433 case OP_IDIV_UN_IMM:
3435 case OP_IREM_UN_IMM:
3436 ADD_NEW_INS (cfg, temp, OP_ICONST);
3437 temp->inst_c0 = ins->inst_imm;
3438 temp->dreg = mono_alloc_ireg (cfg);
3439 ins->sreg2 = temp->dreg;
3440 ins->opcode = mono_op_imm_to_op (ins->opcode);
3442 case OP_LOCALLOC_IMM:
3443 ADD_NEW_INS (cfg, temp, OP_ICONST);
3444 temp->inst_c0 = ins->inst_imm;
3445 temp->dreg = mono_alloc_ireg (cfg);
3446 ins->sreg1 = temp->dreg;
3447 ins->opcode = OP_LOCALLOC;
3449 case OP_LOAD_MEMBASE:
3450 case OP_LOADI4_MEMBASE:
3451 case OP_LOADU4_MEMBASE:
3452 case OP_LOADU1_MEMBASE:
3453 /* we can do two things: load the immed in a register
3454 * and use an indexed load, or see if the immed can be
3455 * represented as an ad_imm + a load with a smaller offset
3456 * that fits. We just do the first for now, optimize later.
3458 if (arm_is_imm12 (ins->inst_offset))
3460 ADD_NEW_INS (cfg, temp, OP_ICONST);
3461 temp->inst_c0 = ins->inst_offset;
3462 temp->dreg = mono_alloc_ireg (cfg);
3463 ins->sreg2 = temp->dreg;
3464 ins->opcode = map_to_reg_reg_op (ins->opcode);
3466 case OP_LOADI2_MEMBASE:
3467 case OP_LOADU2_MEMBASE:
3468 case OP_LOADI1_MEMBASE:
3469 if (arm_is_imm8 (ins->inst_offset))
3471 ADD_NEW_INS (cfg, temp, OP_ICONST);
3472 temp->inst_c0 = ins->inst_offset;
3473 temp->dreg = mono_alloc_ireg (cfg);
3474 ins->sreg2 = temp->dreg;
3475 ins->opcode = map_to_reg_reg_op (ins->opcode);
3477 case OP_LOADR4_MEMBASE:
3478 case OP_LOADR8_MEMBASE:
3479 if (arm_is_fpimm8 (ins->inst_offset))
3481 low_imm = ins->inst_offset & 0x1ff;
3482 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3483 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3484 temp->inst_imm = ins->inst_offset & ~0x1ff;
3485 temp->sreg1 = ins->inst_basereg;
3486 temp->dreg = mono_alloc_ireg (cfg);
3487 ins->inst_basereg = temp->dreg;
3488 ins->inst_offset = low_imm;
3492 ADD_NEW_INS (cfg, temp, OP_ICONST);
3493 temp->inst_c0 = ins->inst_offset;
3494 temp->dreg = mono_alloc_ireg (cfg);
3496 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3497 add_ins->sreg1 = ins->inst_basereg;
3498 add_ins->sreg2 = temp->dreg;
3499 add_ins->dreg = mono_alloc_ireg (cfg);
3501 ins->inst_basereg = add_ins->dreg;
3502 ins->inst_offset = 0;
3505 case OP_STORE_MEMBASE_REG:
3506 case OP_STOREI4_MEMBASE_REG:
3507 case OP_STOREI1_MEMBASE_REG:
3508 if (arm_is_imm12 (ins->inst_offset))
3510 ADD_NEW_INS (cfg, temp, OP_ICONST);
3511 temp->inst_c0 = ins->inst_offset;
3512 temp->dreg = mono_alloc_ireg (cfg);
3513 ins->sreg2 = temp->dreg;
3514 ins->opcode = map_to_reg_reg_op (ins->opcode);
3516 case OP_STOREI2_MEMBASE_REG:
3517 if (arm_is_imm8 (ins->inst_offset))
3519 ADD_NEW_INS (cfg, temp, OP_ICONST);
3520 temp->inst_c0 = ins->inst_offset;
3521 temp->dreg = mono_alloc_ireg (cfg);
3522 ins->sreg2 = temp->dreg;
3523 ins->opcode = map_to_reg_reg_op (ins->opcode);
3525 case OP_STORER4_MEMBASE_REG:
3526 case OP_STORER8_MEMBASE_REG:
3527 if (arm_is_fpimm8 (ins->inst_offset))
3529 low_imm = ins->inst_offset & 0x1ff;
3530 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3531 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3532 temp->inst_imm = ins->inst_offset & ~0x1ff;
3533 temp->sreg1 = ins->inst_destbasereg;
3534 temp->dreg = mono_alloc_ireg (cfg);
3535 ins->inst_destbasereg = temp->dreg;
3536 ins->inst_offset = low_imm;
3540 ADD_NEW_INS (cfg, temp, OP_ICONST);
3541 temp->inst_c0 = ins->inst_offset;
3542 temp->dreg = mono_alloc_ireg (cfg);
3544 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3545 add_ins->sreg1 = ins->inst_destbasereg;
3546 add_ins->sreg2 = temp->dreg;
3547 add_ins->dreg = mono_alloc_ireg (cfg);
3549 ins->inst_destbasereg = add_ins->dreg;
3550 ins->inst_offset = 0;
3553 case OP_STORE_MEMBASE_IMM:
3554 case OP_STOREI1_MEMBASE_IMM:
3555 case OP_STOREI2_MEMBASE_IMM:
3556 case OP_STOREI4_MEMBASE_IMM:
3557 ADD_NEW_INS (cfg, temp, OP_ICONST);
3558 temp->inst_c0 = ins->inst_imm;
3559 temp->dreg = mono_alloc_ireg (cfg);
3560 ins->sreg1 = temp->dreg;
3561 ins->opcode = map_to_reg_reg_op (ins->opcode);
3563 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3566 gboolean swap = FALSE;
3570 /* Optimized away */
3575 /* Some fp compares require swapped operands */
3576 switch (ins->next->opcode) {
3578 ins->next->opcode = OP_FBLT;
3582 ins->next->opcode = OP_FBLT_UN;
3586 ins->next->opcode = OP_FBGE;
3590 ins->next->opcode = OP_FBGE_UN;
3598 ins->sreg1 = ins->sreg2;
3607 bb->last_ins = last_ins;
3608 bb->max_vreg = cfg->next_vreg;
3612 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3616 if (long_ins->opcode == OP_LNEG) {
3618 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3619 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3625 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3627 /* sreg is a float, dreg is an integer reg */
3629 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3631 ARM_TOSIZD (code, vfp_scratch1, sreg);
3633 ARM_TOUIZD (code, vfp_scratch1, sreg);
3634 ARM_FMRS (code, dreg, vfp_scratch1);
3635 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3639 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3640 else if (size == 2) {
3641 ARM_SHL_IMM (code, dreg, dreg, 16);
3642 ARM_SHR_IMM (code, dreg, dreg, 16);
3646 ARM_SHL_IMM (code, dreg, dreg, 24);
3647 ARM_SAR_IMM (code, dreg, dreg, 24);
3648 } else if (size == 2) {
3649 ARM_SHL_IMM (code, dreg, dreg, 16);
3650 ARM_SAR_IMM (code, dreg, dreg, 16);
3657 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3659 /* sreg is a float, dreg is an integer reg */
3661 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3663 ARM_TOSIZS (code, vfp_scratch1, sreg);
3665 ARM_TOUIZS (code, vfp_scratch1, sreg);
3666 ARM_FMRS (code, dreg, vfp_scratch1);
3667 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3671 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3672 else if (size == 2) {
3673 ARM_SHL_IMM (code, dreg, dreg, 16);
3674 ARM_SHR_IMM (code, dreg, dreg, 16);
3678 ARM_SHL_IMM (code, dreg, dreg, 24);
3679 ARM_SAR_IMM (code, dreg, dreg, 24);
3680 } else if (size == 2) {
3681 ARM_SHL_IMM (code, dreg, dreg, 16);
3682 ARM_SAR_IMM (code, dreg, dreg, 16);
3688 #endif /* #ifndef DISABLE_JIT */
3690 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3693 emit_thunk (guint8 *code, gconstpointer target)
3697 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3698 if (thumb_supported)
3699 ARM_BX (code, ARMREG_IP);
3701 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3702 *(guint32*)code = (guint32)target;
3704 mono_arch_flush_icache (p, code - p);
3708 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3710 MonoJitInfo *ji = NULL;
3711 MonoThunkJitInfo *info;
3714 guint8 *orig_target;
3715 guint8 *target_thunk;
3718 domain = mono_domain_get ();
3722 * This can be called multiple times during JITting,
3723 * save the current position in cfg->arch to avoid
3724 * doing a O(n^2) search.
3726 if (!cfg->arch.thunks) {
3727 cfg->arch.thunks = cfg->thunks;
3728 cfg->arch.thunks_size = cfg->thunk_area;
3730 thunks = cfg->arch.thunks;
3731 thunks_size = cfg->arch.thunks_size;
3733 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3734 g_assert_not_reached ();
3737 g_assert (*(guint32*)thunks == 0);
3738 emit_thunk (thunks, target);
3739 arm_patch (code, thunks);
3741 cfg->arch.thunks += THUNK_SIZE;
3742 cfg->arch.thunks_size -= THUNK_SIZE;
3744 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3746 info = mono_jit_info_get_thunk_info (ji);
3749 thunks = (guint8*)ji->code_start + info->thunks_offset;
3750 thunks_size = info->thunks_size;
3752 orig_target = mono_arch_get_call_target (code + 4);
3754 mono_mini_arch_lock ();
3756 target_thunk = NULL;
3757 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3758 /* The call already points to a thunk, because of trampolines etc. */
3759 target_thunk = orig_target;
3761 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3762 if (((guint32*)p) [0] == 0) {
3770 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
3772 if (!target_thunk) {
3773 mono_mini_arch_unlock ();
3774 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3775 g_assert_not_reached ();
3778 emit_thunk (target_thunk, target);
3779 arm_patch (code, target_thunk);
3780 mono_arch_flush_icache (code, 4);
3782 mono_mini_arch_unlock ();
3787 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3789 guint32 *code32 = (void*)code;
3790 guint32 ins = *code32;
3791 guint32 prim = (ins >> 25) & 7;
3792 guint32 tval = GPOINTER_TO_UINT (target);
3794 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3795 if (prim == 5) { /* 101b */
3796 /* the diff starts 8 bytes from the branch opcode */
3797 gint diff = target - code - 8;
3799 gint tmask = 0xffffffff;
3800 if (tval & 1) { /* entering thumb mode */
3801 diff = target - 1 - code - 8;
3802 g_assert (thumb_supported);
3803 tbits = 0xf << 28; /* bl->blx bit pattern */
3804 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3805 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3809 tmask = ~(1 << 24); /* clear the link bit */
3810 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3815 if (diff <= 33554431) {
3817 ins = (ins & 0xff000000) | diff;
3819 *code32 = ins | tbits;
3823 /* diff between 0 and -33554432 */
3824 if (diff >= -33554432) {
3826 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3828 *code32 = ins | tbits;
3833 handle_thunk (cfg, domain, code, target);
3837 #ifdef USE_JUMP_TABLES
3839 gpointer *jte = mono_jumptable_get_entry (code);
3841 jte [0] = (gpointer) target;
3845 * The alternative call sequences looks like this:
3847 * ldr ip, [pc] // loads the address constant
3848 * b 1f // jumps around the constant
3849 * address constant embedded in the code
3854 * There are two cases for patching:
3855 * a) at the end of method emission: in this case code points to the start
3856 * of the call sequence
3857 * b) during runtime patching of the call site: in this case code points
3858 * to the mov pc, ip instruction
3860 * We have to handle also the thunk jump code sequence:
3864 * address constant // execution never reaches here
3866 if ((ins & 0x0ffffff0) == 0x12fff10) {
3867 /* Branch and exchange: the address is constructed in a reg
3868 * We can patch BX when the code sequence is the following:
3869 * ldr ip, [pc, #0] ; 0x8
3876 guint8 *emit = (guint8*)ccode;
3877 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3879 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3880 ARM_BX (emit, ARMREG_IP);
3882 /*patching from magic trampoline*/
3883 if (ins == ccode [3]) {
3884 g_assert (code32 [-4] == ccode [0]);
3885 g_assert (code32 [-3] == ccode [1]);
3886 g_assert (code32 [-1] == ccode [2]);
3887 code32 [-2] = (guint32)target;
3890 /*patching from JIT*/
3891 if (ins == ccode [0]) {
3892 g_assert (code32 [1] == ccode [1]);
3893 g_assert (code32 [3] == ccode [2]);
3894 g_assert (code32 [4] == ccode [3]);
3895 code32 [2] = (guint32)target;
3898 g_assert_not_reached ();
3899 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3907 guint8 *emit = (guint8*)ccode;
3908 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3910 ARM_BLX_REG (emit, ARMREG_IP);
3912 g_assert (code32 [-3] == ccode [0]);
3913 g_assert (code32 [-2] == ccode [1]);
3914 g_assert (code32 [0] == ccode [2]);
3916 code32 [-1] = (guint32)target;
3919 guint32 *tmp = ccode;
3920 guint8 *emit = (guint8*)tmp;
3921 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3922 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3923 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3924 ARM_BX (emit, ARMREG_IP);
3925 if (ins == ccode [2]) {
3926 g_assert_not_reached (); // should be -2 ...
3927 code32 [-1] = (guint32)target;
3930 if (ins == ccode [0]) {
3931 /* handles both thunk jump code and the far call sequence */
3932 code32 [2] = (guint32)target;
3935 g_assert_not_reached ();
3937 // g_print ("patched with 0x%08x\n", ins);
3942 arm_patch (guchar *code, const guchar *target)
3944 arm_patch_general (NULL, NULL, code, target);
3948 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3949 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3950 * to be used with the emit macros.
3951 * Return -1 otherwise.
3954 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3957 for (i = 0; i < 31; i+= 2) {
3958 res = (val << (32 - i)) | (val >> i);
3961 *rot_amount = i? 32 - i: 0;
3968 * Emits in code a sequence of instructions that load the value 'val'
3969 * into the dreg register. Uses at most 4 instructions.
3972 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3974 int imm8, rot_amount;
3976 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3977 /* skip the constant pool */
3983 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3984 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3985 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3986 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3989 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3991 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3995 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3997 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3999 if (val & 0xFF0000) {
4000 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4002 if (val & 0xFF000000) {
4003 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4005 } else if (val & 0xFF00) {
4006 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4007 if (val & 0xFF0000) {
4008 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4010 if (val & 0xFF000000) {
4011 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4013 } else if (val & 0xFF0000) {
4014 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4015 if (val & 0xFF000000) {
4016 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4019 //g_assert_not_reached ();
4025 mono_arm_thumb_supported (void)
4027 return thumb_supported;
4033 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4038 call = (MonoCallInst*)ins;
4039 cinfo = call->call_info;
4041 switch (cinfo->ret.storage) {
4043 MonoInst *loc = cfg->arch.vret_addr_loc;
4046 /* Load the destination address */
4047 g_assert (loc && loc->opcode == OP_REGOFFSET);
4049 if (arm_is_imm12 (loc->inst_offset)) {
4050 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4052 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4053 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4055 for (i = 0; i < cinfo->ret.nregs; ++i) {
4056 if (cinfo->ret.esize == 4)
4057 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4059 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4067 switch (ins->opcode) {
4070 case OP_FCALL_MEMBASE:
4072 MonoType *sig_ret = mini_type_get_underlying_type (NULL, ((MonoCallInst*)ins)->signature->ret);
4073 if (sig_ret->type == MONO_TYPE_R4) {
4074 if (IS_HARD_FLOAT) {
4075 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4077 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4078 ARM_CVTS (code, ins->dreg, ins->dreg);
4081 if (IS_HARD_FLOAT) {
4082 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4084 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4091 case OP_RCALL_MEMBASE: {
4096 sig_ret = mini_type_get_underlying_type (NULL, ((MonoCallInst*)ins)->signature->ret);
4097 g_assert (sig_ret->type == MONO_TYPE_R4);
4098 if (IS_HARD_FLOAT) {
4099 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4101 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4102 ARM_CPYS (code, ins->dreg, ins->dreg);
4114 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4119 guint8 *code = cfg->native_code + cfg->code_len;
4120 MonoInst *last_ins = NULL;
4121 guint last_offset = 0;
4123 int imm8, rot_amount;
4125 /* we don't align basic blocks of loops on arm */
4127 if (cfg->verbose_level > 2)
4128 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4130 cpos = bb->max_offset;
4132 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4133 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4134 //g_assert (!mono_compile_aot);
4137 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4138 /* this is not thread save, but good enough */
4139 /* fixme: howto handle overflows? */
4140 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4143 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4144 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4145 (gpointer)"mono_break");
4146 code = emit_call_seq (cfg, code);
4149 MONO_BB_FOR_EACH_INS (bb, ins) {
4150 offset = code - cfg->native_code;
4152 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4154 if (offset > (cfg->code_size - max_len - 16)) {
4155 cfg->code_size *= 2;
4156 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4157 code = cfg->native_code + offset;
4159 // if (ins->cil_code)
4160 // g_print ("cil code\n");
4161 mono_debug_record_line_number (cfg, ins, offset);
4163 switch (ins->opcode) {
4164 case OP_MEMORY_BARRIER:
4166 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4167 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4171 #ifdef HAVE_AEABI_READ_TP
4172 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4173 (gpointer)"__aeabi_read_tp");
4174 code = emit_call_seq (cfg, code);
4176 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
4178 g_assert_not_reached ();
4181 case OP_ATOMIC_EXCHANGE_I4:
4182 case OP_ATOMIC_CAS_I4:
4183 case OP_ATOMIC_ADD_I4: {
4187 g_assert (v7_supported);
4190 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4192 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4194 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4198 g_assert (cfg->arch.atomic_tmp_offset != -1);
4199 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4201 switch (ins->opcode) {
4202 case OP_ATOMIC_EXCHANGE_I4:
4204 ARM_DMB (code, ARM_DMB_SY);
4205 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4206 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4207 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4209 ARM_B_COND (code, ARMCOND_NE, 0);
4210 arm_patch (buf [1], buf [0]);
4212 case OP_ATOMIC_CAS_I4:
4213 ARM_DMB (code, ARM_DMB_SY);
4215 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4216 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4218 ARM_B_COND (code, ARMCOND_NE, 0);
4219 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4220 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4222 ARM_B_COND (code, ARMCOND_NE, 0);
4223 arm_patch (buf [2], buf [0]);
4224 arm_patch (buf [1], code);
4226 case OP_ATOMIC_ADD_I4:
4228 ARM_DMB (code, ARM_DMB_SY);
4229 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4230 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4231 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4232 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4234 ARM_B_COND (code, ARMCOND_NE, 0);
4235 arm_patch (buf [1], buf [0]);
4238 g_assert_not_reached ();
4241 ARM_DMB (code, ARM_DMB_SY);
4242 if (tmpreg != ins->dreg)
4243 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4244 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4247 case OP_ATOMIC_LOAD_I1:
4248 case OP_ATOMIC_LOAD_U1:
4249 case OP_ATOMIC_LOAD_I2:
4250 case OP_ATOMIC_LOAD_U2:
4251 case OP_ATOMIC_LOAD_I4:
4252 case OP_ATOMIC_LOAD_U4:
4253 case OP_ATOMIC_LOAD_R4:
4254 case OP_ATOMIC_LOAD_R8: {
4255 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4256 ARM_DMB (code, ARM_DMB_SY);
4258 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4260 switch (ins->opcode) {
4261 case OP_ATOMIC_LOAD_I1:
4262 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4264 case OP_ATOMIC_LOAD_U1:
4265 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4267 case OP_ATOMIC_LOAD_I2:
4268 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4270 case OP_ATOMIC_LOAD_U2:
4271 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4273 case OP_ATOMIC_LOAD_I4:
4274 case OP_ATOMIC_LOAD_U4:
4275 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4277 case OP_ATOMIC_LOAD_R4:
4278 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4279 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4280 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4281 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4282 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4284 case OP_ATOMIC_LOAD_R8:
4285 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4286 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4290 ARM_DMB (code, ARM_DMB_SY);
4293 case OP_ATOMIC_STORE_I1:
4294 case OP_ATOMIC_STORE_U1:
4295 case OP_ATOMIC_STORE_I2:
4296 case OP_ATOMIC_STORE_U2:
4297 case OP_ATOMIC_STORE_I4:
4298 case OP_ATOMIC_STORE_U4:
4299 case OP_ATOMIC_STORE_R4:
4300 case OP_ATOMIC_STORE_R8: {
4301 ARM_DMB (code, ARM_DMB_SY);
4303 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4305 switch (ins->opcode) {
4306 case OP_ATOMIC_STORE_I1:
4307 case OP_ATOMIC_STORE_U1:
4308 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4310 case OP_ATOMIC_STORE_I2:
4311 case OP_ATOMIC_STORE_U2:
4312 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4314 case OP_ATOMIC_STORE_I4:
4315 case OP_ATOMIC_STORE_U4:
4316 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4318 case OP_ATOMIC_STORE_R4:
4319 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4320 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4321 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4322 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4323 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4325 case OP_ATOMIC_STORE_R8:
4326 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4327 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4331 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4332 ARM_DMB (code, ARM_DMB_SY);
4336 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4337 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4340 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4341 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4343 case OP_STOREI1_MEMBASE_IMM:
4344 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4345 g_assert (arm_is_imm12 (ins->inst_offset));
4346 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4348 case OP_STOREI2_MEMBASE_IMM:
4349 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4350 g_assert (arm_is_imm8 (ins->inst_offset));
4351 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4353 case OP_STORE_MEMBASE_IMM:
4354 case OP_STOREI4_MEMBASE_IMM:
4355 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4356 g_assert (arm_is_imm12 (ins->inst_offset));
4357 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4359 case OP_STOREI1_MEMBASE_REG:
4360 g_assert (arm_is_imm12 (ins->inst_offset));
4361 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4363 case OP_STOREI2_MEMBASE_REG:
4364 g_assert (arm_is_imm8 (ins->inst_offset));
4365 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4367 case OP_STORE_MEMBASE_REG:
4368 case OP_STOREI4_MEMBASE_REG:
4369 /* this case is special, since it happens for spill code after lowering has been called */
4370 if (arm_is_imm12 (ins->inst_offset)) {
4371 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4373 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4374 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4377 case OP_STOREI1_MEMINDEX:
4378 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4380 case OP_STOREI2_MEMINDEX:
4381 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4383 case OP_STORE_MEMINDEX:
4384 case OP_STOREI4_MEMINDEX:
4385 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4388 g_assert_not_reached ();
4390 case OP_LOAD_MEMINDEX:
4391 case OP_LOADI4_MEMINDEX:
4392 case OP_LOADU4_MEMINDEX:
4393 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4395 case OP_LOADI1_MEMINDEX:
4396 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4398 case OP_LOADU1_MEMINDEX:
4399 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4401 case OP_LOADI2_MEMINDEX:
4402 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4404 case OP_LOADU2_MEMINDEX:
4405 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4407 case OP_LOAD_MEMBASE:
4408 case OP_LOADI4_MEMBASE:
4409 case OP_LOADU4_MEMBASE:
4410 /* this case is special, since it happens for spill code after lowering has been called */
4411 if (arm_is_imm12 (ins->inst_offset)) {
4412 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4414 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4415 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4418 case OP_LOADI1_MEMBASE:
4419 g_assert (arm_is_imm8 (ins->inst_offset));
4420 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4422 case OP_LOADU1_MEMBASE:
4423 g_assert (arm_is_imm12 (ins->inst_offset));
4424 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4426 case OP_LOADU2_MEMBASE:
4427 g_assert (arm_is_imm8 (ins->inst_offset));
4428 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4430 case OP_LOADI2_MEMBASE:
4431 g_assert (arm_is_imm8 (ins->inst_offset));
4432 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4434 case OP_ICONV_TO_I1:
4435 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4436 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4438 case OP_ICONV_TO_I2:
4439 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4440 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4442 case OP_ICONV_TO_U1:
4443 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4445 case OP_ICONV_TO_U2:
4446 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4447 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4451 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4453 case OP_COMPARE_IMM:
4454 case OP_ICOMPARE_IMM:
4455 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4456 g_assert (imm8 >= 0);
4457 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4461 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4462 * So instead of emitting a trap, we emit a call a C function and place a
4465 //*(int*)code = 0xef9f0001;
4468 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4469 (gpointer)"mono_break");
4470 code = emit_call_seq (cfg, code);
4472 case OP_RELAXED_NOP:
4477 case OP_DUMMY_STORE:
4478 case OP_DUMMY_ICONST:
4479 case OP_DUMMY_R8CONST:
4480 case OP_NOT_REACHED:
4483 case OP_IL_SEQ_POINT:
4484 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4486 case OP_SEQ_POINT: {
4488 MonoInst *info_var = cfg->arch.seq_point_info_var;
4489 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4490 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
4491 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4492 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4494 int dreg = ARMREG_LR;
4496 if (cfg->soft_breakpoints) {
4497 g_assert (!cfg->compile_aot);
4501 * For AOT, we use one got slot per method, which will point to a
4502 * SeqPointInfo structure, containing all the information required
4503 * by the code below.
4505 if (cfg->compile_aot) {
4506 g_assert (info_var);
4507 g_assert (info_var->opcode == OP_REGOFFSET);
4508 g_assert (arm_is_imm12 (info_var->inst_offset));
4511 if (!cfg->soft_breakpoints) {
4513 * Read from the single stepping trigger page. This will cause a
4514 * SIGSEGV when single stepping is enabled.
4515 * We do this _before_ the breakpoint, so single stepping after
4516 * a breakpoint is hit will step to the next IL offset.
4518 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4521 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4522 if (cfg->soft_breakpoints) {
4523 /* Load the address of the sequence point trigger variable. */
4526 g_assert (var->opcode == OP_REGOFFSET);
4527 g_assert (arm_is_imm12 (var->inst_offset));
4528 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4530 /* Read the value and check whether it is non-zero. */
4531 ARM_LDR_IMM (code, dreg, dreg, 0);
4532 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4534 /* Load the address of the sequence point method. */
4535 var = ss_method_var;
4537 g_assert (var->opcode == OP_REGOFFSET);
4538 g_assert (arm_is_imm12 (var->inst_offset));
4539 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4541 /* Call it conditionally. */
4542 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4544 if (cfg->compile_aot) {
4545 /* Load the trigger page addr from the variable initialized in the prolog */
4546 var = ss_trigger_page_var;
4548 g_assert (var->opcode == OP_REGOFFSET);
4549 g_assert (arm_is_imm12 (var->inst_offset));
4550 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4552 #ifdef USE_JUMP_TABLES
4553 gpointer *jte = mono_jumptable_add_entry ();
4554 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4555 jte [0] = ss_trigger_page;
4557 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4559 *(int*)code = (int)ss_trigger_page;
4563 ARM_LDR_IMM (code, dreg, dreg, 0);
4567 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4569 if (cfg->soft_breakpoints) {
4570 /* Load the address of the breakpoint method into ip. */
4571 var = bp_method_var;
4573 g_assert (var->opcode == OP_REGOFFSET);
4574 g_assert (arm_is_imm12 (var->inst_offset));
4575 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4578 * A placeholder for a possible breakpoint inserted by
4579 * mono_arch_set_breakpoint ().
4582 } else if (cfg->compile_aot) {
4583 guint32 offset = code - cfg->native_code;
4586 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4587 /* Add the offset */
4588 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4589 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4590 if (arm_is_imm12 ((int)val)) {
4591 ARM_LDR_IMM (code, dreg, dreg, val);
4593 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4595 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4597 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4598 g_assert (!(val & 0xFF000000));
4600 ARM_LDR_IMM (code, dreg, dreg, 0);
4602 /* What is faster, a branch or a load ? */
4603 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4604 /* The breakpoint instruction */
4605 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4608 * A placeholder for a possible breakpoint inserted by
4609 * mono_arch_set_breakpoint ().
4611 for (i = 0; i < 4; ++i)
4618 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4621 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4625 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4628 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4629 g_assert (imm8 >= 0);
4630 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4634 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4635 g_assert (imm8 >= 0);
4636 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4640 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4641 g_assert (imm8 >= 0);
4642 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4645 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4646 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4648 case OP_IADD_OVF_UN:
4649 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4650 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4653 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4654 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4656 case OP_ISUB_OVF_UN:
4657 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4658 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4660 case OP_ADD_OVF_CARRY:
4661 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4662 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4664 case OP_ADD_OVF_UN_CARRY:
4665 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4666 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4668 case OP_SUB_OVF_CARRY:
4669 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4670 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4672 case OP_SUB_OVF_UN_CARRY:
4673 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4674 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4678 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4681 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4682 g_assert (imm8 >= 0);
4683 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4686 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4690 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4694 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4695 g_assert (imm8 >= 0);
4696 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4700 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4701 g_assert (imm8 >= 0);
4702 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4704 case OP_ARM_RSBS_IMM:
4705 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4706 g_assert (imm8 >= 0);
4707 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4709 case OP_ARM_RSC_IMM:
4710 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4711 g_assert (imm8 >= 0);
4712 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4715 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4719 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4720 g_assert (imm8 >= 0);
4721 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4724 g_assert (v7s_supported);
4725 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4728 g_assert (v7s_supported);
4729 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4732 g_assert (v7s_supported);
4733 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4734 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4737 g_assert (v7s_supported);
4738 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4739 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4743 g_assert_not_reached ();
4745 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4749 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4750 g_assert (imm8 >= 0);
4751 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4754 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4758 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4759 g_assert (imm8 >= 0);
4760 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4763 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4768 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4769 else if (ins->dreg != ins->sreg1)
4770 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4773 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4778 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4779 else if (ins->dreg != ins->sreg1)
4780 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4783 case OP_ISHR_UN_IMM:
4785 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4786 else if (ins->dreg != ins->sreg1)
4787 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4790 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4793 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4796 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4799 if (ins->dreg == ins->sreg2)
4800 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4802 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4805 g_assert_not_reached ();
4808 /* FIXME: handle ovf/ sreg2 != dreg */
4809 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4810 /* FIXME: MUL doesn't set the C/O flags on ARM */
4812 case OP_IMUL_OVF_UN:
4813 /* FIXME: handle ovf/ sreg2 != dreg */
4814 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4815 /* FIXME: MUL doesn't set the C/O flags on ARM */
4818 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4821 /* Load the GOT offset */
4822 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4823 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4825 *(gpointer*)code = NULL;
4827 /* Load the value from the GOT */
4828 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4830 case OP_OBJC_GET_SELECTOR:
4831 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4832 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4834 *(gpointer*)code = NULL;
4836 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4838 case OP_ICONV_TO_I4:
4839 case OP_ICONV_TO_U4:
4841 if (ins->dreg != ins->sreg1)
4842 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4845 int saved = ins->sreg2;
4846 if (ins->sreg2 == ARM_LSW_REG) {
4847 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4850 if (ins->sreg1 != ARM_LSW_REG)
4851 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4852 if (saved != ARM_MSW_REG)
4853 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4857 if (IS_VFP && ins->dreg != ins->sreg1)
4858 ARM_CPYD (code, ins->dreg, ins->sreg1);
4860 case OP_MOVE_F_TO_I4:
4861 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4862 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4863 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4864 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4866 case OP_MOVE_I4_TO_F:
4867 ARM_FMSR (code, ins->dreg, ins->sreg1);
4868 ARM_CVTS (code, ins->dreg, ins->dreg);
4870 case OP_FCONV_TO_R4:
4873 ARM_CVTD (code, ins->dreg, ins->sreg1);
4875 ARM_CVTD (code, ins->dreg, ins->sreg1);
4876 ARM_CVTS (code, ins->dreg, ins->dreg);
4881 MonoCallInst *call = (MonoCallInst*)ins;
4884 * The stack looks like the following:
4885 * <caller argument area>
4888 * <callee argument area>
4889 * Need to copy the arguments from the callee argument area to
4890 * the caller argument area, and pop the frame.
4892 if (call->stack_usage) {
4893 int i, prev_sp_offset = 0;
4895 /* Compute size of saved registers restored below */
4897 prev_sp_offset = 2 * 4;
4899 prev_sp_offset = 1 * 4;
4900 for (i = 0; i < 16; ++i) {
4901 if (cfg->used_int_regs & (1 << i))
4902 prev_sp_offset += 4;
4905 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4907 /* Copy arguments on the stack to our argument area */
4908 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4909 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4910 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4915 * Keep in sync with mono_arch_emit_epilog
4917 g_assert (!cfg->method->save_lmf);
4919 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4921 if (cfg->used_int_regs)
4922 ARM_POP (code, cfg->used_int_regs);
4923 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4925 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4928 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4929 if (cfg->compile_aot) {
4930 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4932 *(gpointer*)code = NULL;
4934 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4936 code = mono_arm_patchable_b (code, ARMCOND_AL);
4941 /* ensure ins->sreg1 is not NULL */
4942 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4945 g_assert (cfg->sig_cookie < 128);
4946 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4947 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4957 call = (MonoCallInst*)ins;
4960 code = emit_float_args (cfg, call, code, &max_len, &offset);
4962 if (ins->flags & MONO_INST_HAS_METHOD)
4963 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4965 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4966 code = emit_call_seq (cfg, code);
4967 ins->flags |= MONO_INST_GC_CALLSITE;
4968 ins->backend.pc_offset = code - cfg->native_code;
4969 code = emit_move_return_value (cfg, ins, code);
4976 case OP_VOIDCALL_REG:
4979 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
4981 code = emit_call_reg (code, ins->sreg1);
4982 ins->flags |= MONO_INST_GC_CALLSITE;
4983 ins->backend.pc_offset = code - cfg->native_code;
4984 code = emit_move_return_value (cfg, ins, code);
4986 case OP_FCALL_MEMBASE:
4987 case OP_RCALL_MEMBASE:
4988 case OP_LCALL_MEMBASE:
4989 case OP_VCALL_MEMBASE:
4990 case OP_VCALL2_MEMBASE:
4991 case OP_VOIDCALL_MEMBASE:
4992 case OP_CALL_MEMBASE: {
4993 g_assert (ins->sreg1 != ARMREG_LR);
4994 call = (MonoCallInst*)ins;
4997 code = emit_float_args (cfg, call, code, &max_len, &offset);
4998 if (!arm_is_imm12 (ins->inst_offset))
4999 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5000 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5001 if (!arm_is_imm12 (ins->inst_offset))
5002 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5004 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5005 ins->flags |= MONO_INST_GC_CALLSITE;
5006 ins->backend.pc_offset = code - cfg->native_code;
5007 code = emit_move_return_value (cfg, ins, code);
5010 case OP_GENERIC_CLASS_INIT: {
5011 static int byte_offset = -1;
5012 static guint8 bitmask;
5016 if (byte_offset < 0)
5017 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5019 g_assert (arm_is_imm8 (byte_offset));
5020 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5021 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5022 g_assert (imm8 >= 0);
5023 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5024 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5026 ARM_B_COND (code, ARMCOND_NE, 0);
5028 /* Uninitialized case */
5029 g_assert (ins->sreg1 == ARMREG_R0);
5031 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5032 (gpointer)"specific_trampoline_generic_class_init");
5033 code = emit_call_seq (cfg, code);
5035 /* Initialized case */
5036 arm_patch (jump, code);
5040 /* round the size to 8 bytes */
5041 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
5042 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
5043 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5044 /* memzero the area: dreg holds the size, sp is the pointer */
5045 if (ins->flags & MONO_INST_INIT) {
5046 guint8 *start_loop, *branch_to_cond;
5047 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5048 branch_to_cond = code;
5051 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5052 arm_patch (branch_to_cond, code);
5053 /* decrement by 4 and set flags */
5054 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5055 ARM_B_COND (code, ARMCOND_GE, 0);
5056 arm_patch (code - 4, start_loop);
5058 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5059 if (cfg->param_area)
5060 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5065 MonoInst *var = cfg->dyn_call_var;
5067 g_assert (var->opcode == OP_REGOFFSET);
5068 g_assert (arm_is_imm12 (var->inst_offset));
5070 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5071 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5073 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5075 /* Save args buffer */
5076 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5078 /* Set stack slots using R0 as scratch reg */
5079 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5080 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5081 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5082 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5085 /* Set argument registers */
5086 for (i = 0; i < PARAM_REGS; ++i)
5087 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5090 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5091 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5094 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5095 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5096 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5100 if (ins->sreg1 != ARMREG_R0)
5101 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5102 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5103 (gpointer)"mono_arch_throw_exception");
5104 code = emit_call_seq (cfg, code);
5108 if (ins->sreg1 != ARMREG_R0)
5109 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5110 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5111 (gpointer)"mono_arch_rethrow_exception");
5112 code = emit_call_seq (cfg, code);
5115 case OP_START_HANDLER: {
5116 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5119 /* Reserve a param area, see filter-stack.exe */
5120 if (cfg->param_area) {
5121 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5122 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5124 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5125 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5129 if (arm_is_imm12 (spvar->inst_offset)) {
5130 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5132 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5133 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5137 case OP_ENDFILTER: {
5138 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5141 /* Free the param area */
5142 if (cfg->param_area) {
5143 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5144 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5146 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5147 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5151 if (ins->sreg1 != ARMREG_R0)
5152 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5153 if (arm_is_imm12 (spvar->inst_offset)) {
5154 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5156 g_assert (ARMREG_IP != spvar->inst_basereg);
5157 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5158 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5160 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5163 case OP_ENDFINALLY: {
5164 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5167 /* Free the param area */
5168 if (cfg->param_area) {
5169 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5170 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5172 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5173 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5177 if (arm_is_imm12 (spvar->inst_offset)) {
5178 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5180 g_assert (ARMREG_IP != spvar->inst_basereg);
5181 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5182 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5184 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5187 case OP_CALL_HANDLER:
5188 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5189 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5190 cfg->thunk_area += THUNK_SIZE;
5191 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5194 if (ins->dreg != ARMREG_R0)
5195 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5199 ins->inst_c0 = code - cfg->native_code;
5202 /*if (ins->inst_target_bb->native_offset) {
5204 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5206 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5207 code = mono_arm_patchable_b (code, ARMCOND_AL);
5211 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5215 * In the normal case we have:
5216 * ldr pc, [pc, ins->sreg1 << 2]
5219 * ldr lr, [pc, ins->sreg1 << 2]
5221 * After follows the data.
5222 * FIXME: add aot support.
5224 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5225 #ifdef USE_JUMP_TABLES
5227 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5228 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5229 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5233 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5234 if (offset + max_len > (cfg->code_size - 16)) {
5235 cfg->code_size += max_len;
5236 cfg->code_size *= 2;
5237 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5238 code = cfg->native_code + offset;
5240 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5242 code += 4 * GPOINTER_TO_INT (ins->klass);
5247 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5248 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5252 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5253 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5257 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5258 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5262 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5263 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5267 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5268 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5271 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5272 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5275 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5276 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5279 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5280 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5283 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5284 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5287 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5288 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5290 case OP_COND_EXC_EQ:
5291 case OP_COND_EXC_NE_UN:
5292 case OP_COND_EXC_LT:
5293 case OP_COND_EXC_LT_UN:
5294 case OP_COND_EXC_GT:
5295 case OP_COND_EXC_GT_UN:
5296 case OP_COND_EXC_GE:
5297 case OP_COND_EXC_GE_UN:
5298 case OP_COND_EXC_LE:
5299 case OP_COND_EXC_LE_UN:
5300 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5302 case OP_COND_EXC_IEQ:
5303 case OP_COND_EXC_INE_UN:
5304 case OP_COND_EXC_ILT:
5305 case OP_COND_EXC_ILT_UN:
5306 case OP_COND_EXC_IGT:
5307 case OP_COND_EXC_IGT_UN:
5308 case OP_COND_EXC_IGE:
5309 case OP_COND_EXC_IGE_UN:
5310 case OP_COND_EXC_ILE:
5311 case OP_COND_EXC_ILE_UN:
5312 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5315 case OP_COND_EXC_IC:
5316 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5318 case OP_COND_EXC_OV:
5319 case OP_COND_EXC_IOV:
5320 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5322 case OP_COND_EXC_NC:
5323 case OP_COND_EXC_INC:
5324 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5326 case OP_COND_EXC_NO:
5327 case OP_COND_EXC_INO:
5328 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5340 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5343 /* floating point opcodes */
5345 if (cfg->compile_aot) {
5346 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5348 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5350 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5353 /* FIXME: we can optimize the imm load by dealing with part of
5354 * the displacement in LDFD (aligning to 512).
5356 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5357 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5361 if (cfg->compile_aot) {
5362 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5364 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5367 ARM_CVTS (code, ins->dreg, ins->dreg);
5369 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5370 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5372 ARM_CVTS (code, ins->dreg, ins->dreg);
5375 case OP_STORER8_MEMBASE_REG:
5376 /* This is generated by the local regalloc pass which runs after the lowering pass */
5377 if (!arm_is_fpimm8 (ins->inst_offset)) {
5378 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5379 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5380 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5382 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5385 case OP_LOADR8_MEMBASE:
5386 /* This is generated by the local regalloc pass which runs after the lowering pass */
5387 if (!arm_is_fpimm8 (ins->inst_offset)) {
5388 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5389 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5390 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5392 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5395 case OP_STORER4_MEMBASE_REG:
5396 g_assert (arm_is_fpimm8 (ins->inst_offset));
5398 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5400 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5401 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5402 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5403 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5406 case OP_LOADR4_MEMBASE:
5408 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5410 g_assert (arm_is_fpimm8 (ins->inst_offset));
5411 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5412 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5413 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5414 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5417 case OP_ICONV_TO_R_UN: {
5418 g_assert_not_reached ();
5421 case OP_ICONV_TO_R4:
5423 ARM_FMSR (code, ins->dreg, ins->sreg1);
5424 ARM_FSITOS (code, ins->dreg, ins->dreg);
5426 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5427 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5428 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5429 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5430 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5433 case OP_ICONV_TO_R8:
5434 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5435 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5436 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5437 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5441 MonoType *sig_ret = mini_type_get_underlying_type (NULL, mono_method_signature (cfg->method)->ret);
5442 if (sig_ret->type == MONO_TYPE_R4) {
5444 g_assert (!IS_HARD_FLOAT);
5445 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5447 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5450 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5454 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5456 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5460 case OP_FCONV_TO_I1:
5461 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5463 case OP_FCONV_TO_U1:
5464 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5466 case OP_FCONV_TO_I2:
5467 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5469 case OP_FCONV_TO_U2:
5470 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5472 case OP_FCONV_TO_I4:
5474 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5476 case OP_FCONV_TO_U4:
5478 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5480 case OP_FCONV_TO_I8:
5481 case OP_FCONV_TO_U8:
5482 g_assert_not_reached ();
5483 /* Implemented as helper calls */
5485 case OP_LCONV_TO_R_UN:
5486 g_assert_not_reached ();
5487 /* Implemented as helper calls */
5489 case OP_LCONV_TO_OVF_I4_2: {
5490 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5492 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5495 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5496 high_bit_not_set = code;
5497 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5499 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5500 valid_negative = code;
5501 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5502 invalid_negative = code;
5503 ARM_B_COND (code, ARMCOND_AL, 0);
5505 arm_patch (high_bit_not_set, code);
5507 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5508 valid_positive = code;
5509 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5511 arm_patch (invalid_negative, code);
5512 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5514 arm_patch (valid_negative, code);
5515 arm_patch (valid_positive, code);
5517 if (ins->dreg != ins->sreg1)
5518 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5522 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5525 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5528 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5531 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5534 ARM_NEGD (code, ins->dreg, ins->sreg1);
5538 g_assert_not_reached ();
5542 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5548 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5553 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5556 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5557 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5561 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5564 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5565 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5569 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5572 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5573 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5574 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5578 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5581 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5582 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5586 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5589 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5590 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5591 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5595 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5598 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5599 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5603 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5606 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5607 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5611 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5614 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5615 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5618 /* ARM FPA flags table:
5619 * N Less than ARMCOND_MI
5620 * Z Equal ARMCOND_EQ
5621 * C Greater Than or Equal ARMCOND_CS
5622 * V Unordered ARMCOND_VS
5625 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5628 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5631 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5634 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5635 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5641 g_assert_not_reached ();
5645 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5647 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5648 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5649 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5653 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5654 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5659 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5660 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5662 #ifdef USE_JUMP_TABLES
5664 gpointer *jte = mono_jumptable_add_entries (2);
5665 jte [0] = GUINT_TO_POINTER (0xffffffff);
5666 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5667 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5668 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5671 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5672 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5674 *(guint32*)code = 0xffffffff;
5676 *(guint32*)code = 0x7fefffff;
5679 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5681 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5682 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5684 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5685 ARM_CPYD (code, ins->dreg, ins->sreg1);
5687 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5688 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5693 case OP_RCONV_TO_I1:
5694 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5696 case OP_RCONV_TO_U1:
5697 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5699 case OP_RCONV_TO_I2:
5700 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5702 case OP_RCONV_TO_U2:
5703 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5705 case OP_RCONV_TO_I4:
5706 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5708 case OP_RCONV_TO_U4:
5709 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5711 case OP_RCONV_TO_R4:
5713 if (ins->dreg != ins->sreg1)
5714 ARM_CPYS (code, ins->dreg, ins->sreg1);
5716 case OP_RCONV_TO_R8:
5718 ARM_CVTS (code, ins->dreg, ins->sreg1);
5721 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5724 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5727 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5730 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5733 ARM_NEGS (code, ins->dreg, ins->sreg1);
5737 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5740 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5741 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5745 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5748 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5749 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5753 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5756 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5757 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5758 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5762 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5765 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5766 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5770 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5773 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5774 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5775 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5779 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5782 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5783 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5787 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5790 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5791 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5795 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5798 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5799 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5802 case OP_GC_LIVENESS_DEF:
5803 case OP_GC_LIVENESS_USE:
5804 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5805 ins->backend.pc_offset = code - cfg->native_code;
5807 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5808 ins->backend.pc_offset = code - cfg->native_code;
5809 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5813 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5814 g_assert_not_reached ();
5817 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5818 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5819 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5820 g_assert_not_reached ();
5826 last_offset = offset;
5829 cfg->code_len = code - cfg->native_code;
5832 #endif /* DISABLE_JIT */
5834 #ifdef HAVE_AEABI_READ_TP
5835 void __aeabi_read_tp (void);
5839 mono_arch_register_lowlevel_calls (void)
5841 /* The signature doesn't matter */
5842 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5843 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5845 #ifndef MONO_CROSS_COMPILE
5846 #ifdef HAVE_AEABI_READ_TP
5847 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
5852 #define patch_lis_ori(ip,val) do {\
5853 guint16 *__lis_ori = (guint16*)(ip); \
5854 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5855 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5859 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5861 unsigned char *ip = ji->ip.i + code;
5863 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5867 case MONO_PATCH_INFO_SWITCH: {
5868 #ifdef USE_JUMP_TABLES
5869 gpointer *jt = mono_jumptable_get_entry (ip);
5871 gpointer *jt = (gpointer*)(ip + 8);
5874 /* jt is the inlined jump table, 2 instructions after ip
5875 * In the normal case we store the absolute addresses,
5876 * otherwise the displacements.
5878 for (i = 0; i < ji->data.table->table_size; i++)
5879 jt [i] = code + (int)ji->data.table->table [i];
5882 case MONO_PATCH_INFO_IP:
5883 g_assert_not_reached ();
5884 patch_lis_ori (ip, ip);
5886 case MONO_PATCH_INFO_METHOD_REL:
5887 g_assert_not_reached ();
5888 *((gpointer *)(ip)) = target;
5890 case MONO_PATCH_INFO_METHODCONST:
5891 case MONO_PATCH_INFO_CLASS:
5892 case MONO_PATCH_INFO_IMAGE:
5893 case MONO_PATCH_INFO_FIELD:
5894 case MONO_PATCH_INFO_VTABLE:
5895 case MONO_PATCH_INFO_IID:
5896 case MONO_PATCH_INFO_SFLDA:
5897 case MONO_PATCH_INFO_LDSTR:
5898 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5899 case MONO_PATCH_INFO_LDTOKEN:
5900 g_assert_not_reached ();
5901 /* from OP_AOTCONST : lis + ori */
5902 patch_lis_ori (ip, target);
5904 case MONO_PATCH_INFO_R4:
5905 case MONO_PATCH_INFO_R8:
5906 g_assert_not_reached ();
5907 *((gconstpointer *)(ip + 2)) = target;
5909 case MONO_PATCH_INFO_EXC_NAME:
5910 g_assert_not_reached ();
5911 *((gconstpointer *)(ip + 1)) = target;
5913 case MONO_PATCH_INFO_NONE:
5914 case MONO_PATCH_INFO_BB_OVF:
5915 case MONO_PATCH_INFO_EXC_OVF:
5916 /* everything is dealt with at epilog output time */
5919 arm_patch_general (cfg, domain, ip, target);
5927 * Stack frame layout:
5929 * ------------------- fp
5930 * MonoLMF structure or saved registers
5931 * -------------------
5933 * -------------------
5935 * -------------------
5936 * optional 8 bytes for tracing
5937 * -------------------
5938 * param area size is cfg->param_area
5939 * ------------------- sp
5942 mono_arch_emit_prolog (MonoCompile *cfg)
5944 MonoMethod *method = cfg->method;
5946 MonoMethodSignature *sig;
5948 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
5953 int prev_sp_offset, reg_offset;
5955 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5958 sig = mono_method_signature (method);
5959 cfg->code_size = 256 + sig->param_count * 64;
5960 code = cfg->native_code = g_malloc (cfg->code_size);
5962 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
5964 alloc_size = cfg->stack_offset;
5970 * The iphone uses R7 as the frame pointer, and it points at the saved
5975 * We can't use r7 as a frame pointer since it points into the middle of
5976 * the frame, so we keep using our own frame pointer.
5977 * FIXME: Optimize this.
5979 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5980 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
5981 prev_sp_offset += 8; /* r7 and lr */
5982 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5983 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
5986 if (!method->save_lmf) {
5988 /* No need to push LR again */
5989 if (cfg->used_int_regs)
5990 ARM_PUSH (code, cfg->used_int_regs);
5992 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
5993 prev_sp_offset += 4;
5995 for (i = 0; i < 16; ++i) {
5996 if (cfg->used_int_regs & (1 << i))
5997 prev_sp_offset += 4;
5999 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6001 for (i = 0; i < 16; ++i) {
6002 if ((cfg->used_int_regs & (1 << i))) {
6003 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6004 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6009 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6010 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6012 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6013 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6016 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6017 ARM_PUSH (code, 0x5ff0);
6018 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6019 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6021 for (i = 0; i < 16; ++i) {
6022 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6023 /* The original r7 is saved at the start */
6024 if (!(iphone_abi && i == ARMREG_R7))
6025 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6029 g_assert (reg_offset == 4 * 10);
6030 pos += sizeof (MonoLMF) - (4 * 10);
6034 orig_alloc_size = alloc_size;
6035 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6036 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6037 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6038 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6041 /* the stack used in the pushed regs */
6042 if (prev_sp_offset & 4)
6044 cfg->stack_usage = alloc_size;
6046 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6047 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6049 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6050 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6052 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6054 if (cfg->frame_reg != ARMREG_SP) {
6055 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6056 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6058 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6059 prev_sp_offset += alloc_size;
6061 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6062 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6064 /* compute max_offset in order to use short forward jumps
6065 * we could skip do it on arm because the immediate displacement
6066 * for jumps is large enough, it may be useful later for constant pools
6069 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6070 MonoInst *ins = bb->code;
6071 bb->max_offset = max_offset;
6073 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6076 MONO_BB_FOR_EACH_INS (bb, ins)
6077 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6080 /* store runtime generic context */
6081 if (cfg->rgctx_var) {
6082 MonoInst *ins = cfg->rgctx_var;
6084 g_assert (ins->opcode == OP_REGOFFSET);
6086 if (arm_is_imm12 (ins->inst_offset)) {
6087 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6089 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6090 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6094 /* load arguments allocated to register from the stack */
6097 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
6099 if (cinfo->ret.storage == RegTypeStructByAddr) {
6100 ArgInfo *ainfo = &cinfo->ret;
6101 inst = cfg->vret_addr;
6102 g_assert (arm_is_imm12 (inst->inst_offset));
6103 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6106 if (sig->call_convention == MONO_CALL_VARARG) {
6107 ArgInfo *cookie = &cinfo->sig_cookie;
6109 /* Save the sig cookie address */
6110 g_assert (cookie->storage == RegTypeBase);
6112 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6113 g_assert (arm_is_imm12 (cfg->sig_cookie));
6114 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6115 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6118 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6119 ArgInfo *ainfo = cinfo->args + i;
6120 inst = cfg->args [pos];
6122 if (cfg->verbose_level > 2)
6123 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6125 if (inst->opcode == OP_REGVAR) {
6126 if (ainfo->storage == RegTypeGeneral)
6127 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6128 else if (ainfo->storage == RegTypeFP) {
6129 g_assert_not_reached ();
6130 } else if (ainfo->storage == RegTypeBase) {
6131 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6132 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6134 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6135 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6138 g_assert_not_reached ();
6140 if (cfg->verbose_level > 2)
6141 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6143 switch (ainfo->storage) {
6145 for (part = 0; part < ainfo->nregs; part ++) {
6146 if (ainfo->esize == 4)
6147 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6149 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6152 case RegTypeGeneral:
6153 case RegTypeIRegPair:
6154 case RegTypeGSharedVtInReg:
6155 switch (ainfo->size) {
6157 if (arm_is_imm12 (inst->inst_offset))
6158 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6160 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6161 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6165 if (arm_is_imm8 (inst->inst_offset)) {
6166 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6168 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6169 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6173 if (arm_is_imm12 (inst->inst_offset)) {
6174 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6176 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6177 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6179 if (arm_is_imm12 (inst->inst_offset + 4)) {
6180 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6182 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6183 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6187 if (arm_is_imm12 (inst->inst_offset)) {
6188 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6190 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6191 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6196 case RegTypeBaseGen:
6197 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6198 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6200 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6201 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6203 if (arm_is_imm12 (inst->inst_offset + 4)) {
6204 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6205 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6207 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6208 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6209 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6210 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6214 case RegTypeGSharedVtOnStack:
6215 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6216 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6218 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6219 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6222 switch (ainfo->size) {
6224 if (arm_is_imm8 (inst->inst_offset)) {
6225 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6227 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6228 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6232 if (arm_is_imm8 (inst->inst_offset)) {
6233 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6235 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6236 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6240 if (arm_is_imm12 (inst->inst_offset)) {
6241 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6243 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6244 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6246 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6247 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6249 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6250 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6252 if (arm_is_imm12 (inst->inst_offset + 4)) {
6253 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6255 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6256 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6260 if (arm_is_imm12 (inst->inst_offset)) {
6261 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6263 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6264 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6270 int imm8, rot_amount;
6272 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6273 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6274 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6276 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6278 if (ainfo->size == 8)
6279 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6281 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6284 case RegTypeStructByVal: {
6285 int doffset = inst->inst_offset;
6289 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
6290 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6291 if (arm_is_imm12 (doffset)) {
6292 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6294 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6295 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6297 soffset += sizeof (gpointer);
6298 doffset += sizeof (gpointer);
6300 if (ainfo->vtsize) {
6301 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6302 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6303 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6307 case RegTypeStructByAddr:
6308 g_assert_not_reached ();
6309 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6310 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6312 g_assert_not_reached ();
6319 if (method->save_lmf)
6320 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6323 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6325 if (cfg->arch.seq_point_info_var) {
6326 MonoInst *ins = cfg->arch.seq_point_info_var;
6328 /* Initialize the variable from a GOT slot */
6329 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6330 #ifdef USE_JUMP_TABLES
6332 gpointer *jte = mono_jumptable_add_entry ();
6333 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6334 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6336 /** XXX: is it correct? */
6338 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6340 *(gpointer*)code = NULL;
6343 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6345 g_assert (ins->opcode == OP_REGOFFSET);
6347 if (arm_is_imm12 (ins->inst_offset)) {
6348 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6350 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6351 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6355 /* Initialize ss_trigger_page_var */
6356 if (!cfg->soft_breakpoints) {
6357 MonoInst *info_var = cfg->arch.seq_point_info_var;
6358 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6359 int dreg = ARMREG_LR;
6362 g_assert (info_var->opcode == OP_REGOFFSET);
6363 g_assert (arm_is_imm12 (info_var->inst_offset));
6365 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6366 /* Load the trigger page addr */
6367 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6368 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6372 if (cfg->arch.seq_point_read_var) {
6373 MonoInst *read_ins = cfg->arch.seq_point_read_var;
6374 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6375 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6376 #ifdef USE_JUMP_TABLES
6379 g_assert (read_ins->opcode == OP_REGOFFSET);
6380 g_assert (arm_is_imm12 (read_ins->inst_offset));
6381 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6382 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6383 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6384 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6386 #ifdef USE_JUMP_TABLES
6387 jte = mono_jumptable_add_entries (3);
6388 jte [0] = (gpointer)&ss_trigger_var;
6389 jte [1] = single_step_tramp;
6390 jte [2] = breakpoint_tramp;
6391 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6393 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6395 *(volatile int **)code = &ss_trigger_var;
6397 *(gpointer*)code = single_step_tramp;
6399 *(gpointer*)code = breakpoint_tramp;
6403 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6404 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
6405 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6406 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6407 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
6408 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6411 cfg->code_len = code - cfg->native_code;
6412 g_assert (cfg->code_len < cfg->code_size);
6419 mono_arch_emit_epilog (MonoCompile *cfg)
6421 MonoMethod *method = cfg->method;
6422 int pos, i, rot_amount;
6423 int max_epilog_size = 16 + 20*4;
6427 if (cfg->method->save_lmf)
6428 max_epilog_size += 128;
6430 if (mono_jit_trace_calls != NULL)
6431 max_epilog_size += 50;
6433 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6434 max_epilog_size += 50;
6436 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6437 cfg->code_size *= 2;
6438 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6439 cfg->stat_code_reallocs++;
6443 * Keep in sync with OP_JMP
6445 code = cfg->native_code + cfg->code_len;
6447 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6448 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6452 /* Load returned vtypes into registers if needed */
6453 cinfo = cfg->arch.cinfo;
6454 switch (cinfo->ret.storage) {
6455 case RegTypeStructByVal: {
6456 MonoInst *ins = cfg->ret;
6458 if (arm_is_imm12 (ins->inst_offset)) {
6459 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6461 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6462 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6467 MonoInst *ins = cfg->ret;
6469 for (i = 0; i < cinfo->ret.nregs; ++i) {
6470 if (cinfo->ret.esize == 4)
6471 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6473 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6481 if (method->save_lmf) {
6482 int lmf_offset, reg, sp_adj, regmask;
6483 /* all but r0-r3, sp and pc */
6484 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6487 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6489 /* This points to r4 inside MonoLMF->iregs */
6490 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6492 regmask = 0x9ff0; /* restore lr to pc */
6493 /* Skip caller saved registers not used by the method */
6494 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6495 regmask &= ~(1 << reg);
6500 /* Restored later */
6501 regmask &= ~(1 << ARMREG_PC);
6502 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6503 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6505 ARM_POP (code, regmask);
6507 /* Restore saved r7, restore LR to PC */
6508 /* Skip lr from the lmf */
6509 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6510 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6513 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6514 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6516 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6517 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6521 /* Restore saved gregs */
6522 if (cfg->used_int_regs)
6523 ARM_POP (code, cfg->used_int_regs);
6524 /* Restore saved r7, restore LR to PC */
6525 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6527 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6531 cfg->code_len = code - cfg->native_code;
6533 g_assert (cfg->code_len < cfg->code_size);
6538 mono_arch_emit_exceptions (MonoCompile *cfg)
6540 MonoJumpInfo *patch_info;
6543 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6544 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6545 int max_epilog_size = 50;
6547 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6548 exc_throw_pos [i] = NULL;
6549 exc_throw_found [i] = 0;
6552 /* count the number of exception infos */
6555 * make sure we have enough space for exceptions
6557 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6558 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6559 i = mini_exception_id_by_name (patch_info->data.target);
6560 if (!exc_throw_found [i]) {
6561 max_epilog_size += 32;
6562 exc_throw_found [i] = TRUE;
6567 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6568 cfg->code_size *= 2;
6569 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6570 cfg->stat_code_reallocs++;
6573 code = cfg->native_code + cfg->code_len;
6575 /* add code to raise exceptions */
6576 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6577 switch (patch_info->type) {
6578 case MONO_PATCH_INFO_EXC: {
6579 MonoClass *exc_class;
6580 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6582 i = mini_exception_id_by_name (patch_info->data.target);
6583 if (exc_throw_pos [i]) {
6584 arm_patch (ip, exc_throw_pos [i]);
6585 patch_info->type = MONO_PATCH_INFO_NONE;
6588 exc_throw_pos [i] = code;
6590 arm_patch (ip, code);
6592 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6593 g_assert (exc_class);
6595 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6596 #ifdef USE_JUMP_TABLES
6598 gpointer *jte = mono_jumptable_add_entries (2);
6599 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6600 patch_info->data.name = "mono_arch_throw_corlib_exception";
6601 patch_info->ip.i = code - cfg->native_code;
6602 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6603 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6604 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6605 ARM_BLX_REG (code, ARMREG_IP);
6606 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6609 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6610 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6611 patch_info->data.name = "mono_arch_throw_corlib_exception";
6612 patch_info->ip.i = code - cfg->native_code;
6614 cfg->thunk_area += THUNK_SIZE;
6615 *(guint32*)(gpointer)code = exc_class->type_token;
6626 cfg->code_len = code - cfg->native_code;
6628 g_assert (cfg->code_len < cfg->code_size);
6632 #endif /* #ifndef DISABLE_JIT */
6635 mono_arch_finish_init (void)
6640 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6645 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6652 mono_arch_print_tree (MonoInst *tree, int arity)
6662 mono_arch_get_patch_offset (guint8 *code)
6669 mono_arch_flush_register_windows (void)
6674 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6676 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6680 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6682 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6685 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6686 #define BASE_SIZE (6 * 4)
6687 #define BSEARCH_ENTRY_SIZE (4 * 4)
6688 #define CMP_SIZE (3 * 4)
6689 #define BRANCH_SIZE (1 * 4)
6690 #define CALL_SIZE (2 * 4)
6691 #define WMC_SIZE (8 * 4)
6692 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6694 #ifdef USE_JUMP_TABLES
6696 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6698 g_assert (base [index] == NULL);
6699 base [index] = value;
6702 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6704 if (arm_is_imm12 (jti * 4)) {
6705 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6707 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6708 if ((jti * 4) >> 16)
6709 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6710 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6716 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6718 guint32 delta = DISTANCE (target, code);
6720 g_assert (delta >= 0 && delta <= 0xFFF);
6721 *target = *target | delta;
6727 #ifdef ENABLE_WRONG_METHOD_CHECK
6729 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6731 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6737 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6738 gpointer fail_tramp)
6741 arminstr_t *code, *start;
6742 #ifdef USE_JUMP_TABLES
6745 gboolean large_offsets = FALSE;
6746 guint32 **constant_pool_starts;
6747 arminstr_t *vtable_target = NULL;
6748 int extra_space = 0;
6750 #ifdef ENABLE_WRONG_METHOD_CHECK
6755 #ifdef USE_JUMP_TABLES
6756 for (i = 0; i < count; ++i) {
6757 MonoIMTCheckItem *item = imt_entries [i];
6758 item->chunk_size += 4 * 16;
6759 if (!item->is_equals)
6760 imt_entries [item->check_target_idx]->compare_done = TRUE;
6761 size += item->chunk_size;
6764 constant_pool_starts = g_new0 (guint32*, count);
6766 for (i = 0; i < count; ++i) {
6767 MonoIMTCheckItem *item = imt_entries [i];
6768 if (item->is_equals) {
6769 gboolean fail_case = !item->check_target_idx && fail_tramp;
6771 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6772 item->chunk_size += 32;
6773 large_offsets = TRUE;
6776 if (item->check_target_idx || fail_case) {
6777 if (!item->compare_done || fail_case)
6778 item->chunk_size += CMP_SIZE;
6779 item->chunk_size += BRANCH_SIZE;
6781 #ifdef ENABLE_WRONG_METHOD_CHECK
6782 item->chunk_size += WMC_SIZE;
6786 item->chunk_size += 16;
6787 large_offsets = TRUE;
6789 item->chunk_size += CALL_SIZE;
6791 item->chunk_size += BSEARCH_ENTRY_SIZE;
6792 imt_entries [item->check_target_idx]->compare_done = TRUE;
6794 size += item->chunk_size;
6798 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6802 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6804 code = mono_domain_code_reserve (domain, size);
6808 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6809 for (i = 0; i < count; ++i) {
6810 MonoIMTCheckItem *item = imt_entries [i];
6811 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6815 #ifdef USE_JUMP_TABLES
6816 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6817 #define VTABLE_JTI 0
6818 #define IMT_METHOD_OFFSET 0
6819 #define TARGET_CODE_OFFSET 1
6820 #define JUMP_CODE_OFFSET 2
6821 #define RECORDS_PER_ENTRY 3
6822 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
6823 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
6824 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
6826 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
6827 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
6828 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
6829 set_jumptable_element (jte, VTABLE_JTI, vtable);
6832 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6834 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6835 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6836 vtable_target = code;
6837 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6839 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6841 for (i = 0; i < count; ++i) {
6842 MonoIMTCheckItem *item = imt_entries [i];
6843 #ifdef USE_JUMP_TABLES
6844 guint32 imt_method_jti = 0, target_code_jti = 0;
6846 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6848 gint32 vtable_offset;
6850 item->code_target = (guint8*)code;
6852 if (item->is_equals) {
6853 gboolean fail_case = !item->check_target_idx && fail_tramp;
6855 if (item->check_target_idx || fail_case) {
6856 if (!item->compare_done || fail_case) {
6857 #ifdef USE_JUMP_TABLES
6858 imt_method_jti = IMT_METHOD_JTI (i);
6859 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
6862 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6864 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6866 #ifdef USE_JUMP_TABLES
6867 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
6868 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
6869 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
6871 item->jmp_code = (guint8*)code;
6872 ARM_B_COND (code, ARMCOND_NE, 0);
6875 /*Enable the commented code to assert on wrong method*/
6876 #ifdef ENABLE_WRONG_METHOD_CHECK
6877 #ifdef USE_JUMP_TABLES
6878 imt_method_jti = IMT_METHOD_JTI (i);
6879 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
6882 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6884 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6886 ARM_B_COND (code, ARMCOND_EQ, 0);
6888 /* Define this if your system is so bad that gdb is failing. */
6889 #ifdef BROKEN_DEV_ENV
6890 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6892 arm_patch (code - 1, mini_dump_bad_imt);
6896 arm_patch (cond, code);
6900 if (item->has_target_code) {
6901 /* Load target address */
6902 #ifdef USE_JUMP_TABLES
6903 target_code_jti = TARGET_CODE_JTI (i);
6904 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
6905 /* Restore registers */
6906 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6908 ARM_BX (code, ARMREG_R1);
6909 set_jumptable_element (jte, target_code_jti, item->value.target_code);
6911 target_code_ins = code;
6912 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6913 /* Save it to the fourth slot */
6914 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6915 /* Restore registers and branch */
6916 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6918 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
6921 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
6922 if (!arm_is_imm12 (vtable_offset)) {
6924 * We need to branch to a computed address but we don't have
6925 * a free register to store it, since IP must contain the
6926 * vtable address. So we push the two values to the stack, and
6927 * load them both using LDM.
6929 /* Compute target address */
6930 #ifdef USE_JUMP_TABLES
6931 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
6932 if (vtable_offset >> 16)
6933 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
6934 /* IP had vtable base. */
6935 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
6936 /* Restore registers and branch */
6937 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6938 ARM_BX (code, ARMREG_IP);
6940 vtable_offset_ins = code;
6941 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6942 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
6943 /* Save it to the fourth slot */
6944 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6945 /* Restore registers and branch */
6946 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6948 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
6951 #ifdef USE_JUMP_TABLES
6952 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
6953 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6954 ARM_BX (code, ARMREG_IP);
6956 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
6958 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
6959 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
6965 #ifdef USE_JUMP_TABLES
6966 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
6967 target_code_jti = TARGET_CODE_JTI (i);
6968 /* Load target address */
6969 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
6970 /* Restore registers */
6971 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6973 ARM_BX (code, ARMREG_R1);
6974 set_jumptable_element (jte, target_code_jti, fail_tramp);
6976 arm_patch (item->jmp_code, (guchar*)code);
6978 target_code_ins = code;
6979 /* Load target address */
6980 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6981 /* Save it to the fourth slot */
6982 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6983 /* Restore registers and branch */
6984 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6986 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
6988 item->jmp_code = NULL;
6991 #ifdef USE_JUMP_TABLES
6993 set_jumptable_element (jte, imt_method_jti, item->key);
6996 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
6998 /*must emit after unconditional branch*/
6999 if (vtable_target) {
7000 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7001 item->chunk_size += 4;
7002 vtable_target = NULL;
7005 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7006 constant_pool_starts [i] = code;
7008 code += extra_space;
7013 #ifdef USE_JUMP_TABLES
7014 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7015 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7016 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7017 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7018 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7020 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7021 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7023 item->jmp_code = (guint8*)code;
7024 ARM_B_COND (code, ARMCOND_HS, 0);
7030 for (i = 0; i < count; ++i) {
7031 MonoIMTCheckItem *item = imt_entries [i];
7032 if (item->jmp_code) {
7033 if (item->check_target_idx)
7034 #ifdef USE_JUMP_TABLES
7035 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7037 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7040 if (i > 0 && item->is_equals) {
7042 #ifdef USE_JUMP_TABLES
7043 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7044 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7046 arminstr_t *space_start = constant_pool_starts [i];
7047 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7048 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7056 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7057 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7062 #ifndef USE_JUMP_TABLES
7063 g_free (constant_pool_starts);
7066 mono_arch_flush_icache ((guint8*)start, size);
7067 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7068 mono_stats.imt_thunks_size += code - start;
7070 g_assert (DISTANCE (start, code) <= size);
7075 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7077 return ctx->regs [reg];
7081 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7083 ctx->regs [reg] = val;
7087 * mono_arch_get_trampolines:
7089 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7093 mono_arch_get_trampolines (gboolean aot)
7095 return mono_arm_get_exception_trampolines (aot);
7099 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7106 bp = MONO_CONTEXT_GET_BP (ctx);
7107 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7109 old_value = *lr_loc;
7110 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7113 *lr_loc = new_value;
7118 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7120 * mono_arch_set_breakpoint:
7122 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7123 * The location should contain code emitted by OP_SEQ_POINT.
7126 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7129 guint32 native_offset = ip - (guint8*)ji->code_start;
7130 MonoDebugOptions *opt = mini_get_debug_options ();
7132 if (opt->soft_breakpoints) {
7133 g_assert (!ji->from_aot);
7135 ARM_BLX_REG (code, ARMREG_LR);
7136 mono_arch_flush_icache (code - 4, 4);
7137 } else if (ji->from_aot) {
7138 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7140 g_assert (native_offset % 4 == 0);
7141 g_assert (info->bp_addrs [native_offset / 4] == 0);
7142 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7144 int dreg = ARMREG_LR;
7146 /* Read from another trigger page */
7147 #ifdef USE_JUMP_TABLES
7148 gpointer *jte = mono_jumptable_add_entry ();
7149 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7150 jte [0] = bp_trigger_page;
7152 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7154 *(int*)code = (int)bp_trigger_page;
7157 ARM_LDR_IMM (code, dreg, dreg, 0);
7159 mono_arch_flush_icache (code - 16, 16);
7162 /* This is currently implemented by emitting an SWI instruction, which
7163 * qemu/linux seems to convert to a SIGILL.
7165 *(int*)code = (0xef << 24) | 8;
7167 mono_arch_flush_icache (code - 4, 4);
7173 * mono_arch_clear_breakpoint:
7175 * Clear the breakpoint at IP.
7178 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7180 MonoDebugOptions *opt = mini_get_debug_options ();
7184 if (opt->soft_breakpoints) {
7185 g_assert (!ji->from_aot);
7188 mono_arch_flush_icache (code - 4, 4);
7189 } else if (ji->from_aot) {
7190 guint32 native_offset = ip - (guint8*)ji->code_start;
7191 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7193 g_assert (native_offset % 4 == 0);
7194 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7195 info->bp_addrs [native_offset / 4] = 0;
7197 for (i = 0; i < 4; ++i)
7200 mono_arch_flush_icache (ip, code - ip);
7205 * mono_arch_start_single_stepping:
7207 * Start single stepping.
7210 mono_arch_start_single_stepping (void)
7212 if (ss_trigger_page)
7213 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7219 * mono_arch_stop_single_stepping:
7221 * Stop single stepping.
7224 mono_arch_stop_single_stepping (void)
7226 if (ss_trigger_page)
7227 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7233 #define DBG_SIGNAL SIGBUS
7235 #define DBG_SIGNAL SIGSEGV
7239 * mono_arch_is_single_step_event:
7241 * Return whenever the machine state in SIGCTX corresponds to a single
7245 mono_arch_is_single_step_event (void *info, void *sigctx)
7247 siginfo_t *sinfo = info;
7249 if (!ss_trigger_page)
7252 /* Sometimes the address is off by 4 */
7253 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7260 * mono_arch_is_breakpoint_event:
7262 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7265 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7267 siginfo_t *sinfo = info;
7269 if (!ss_trigger_page)
7272 if (sinfo->si_signo == DBG_SIGNAL) {
7273 /* Sometimes the address is off by 4 */
7274 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7284 * mono_arch_skip_breakpoint:
7286 * See mini-amd64.c for docs.
7289 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7291 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7295 * mono_arch_skip_single_step:
7297 * See mini-amd64.c for docs.
7300 mono_arch_skip_single_step (MonoContext *ctx)
7302 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7305 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7308 * mono_arch_get_seq_point_info:
7310 * See mini-amd64.c for docs.
7313 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7318 // FIXME: Add a free function
7320 mono_domain_lock (domain);
7321 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7323 mono_domain_unlock (domain);
7326 ji = mono_jit_info_table_find (domain, (char*)code);
7329 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7331 info->ss_trigger_page = ss_trigger_page;
7332 info->bp_trigger_page = bp_trigger_page;
7334 mono_domain_lock (domain);
7335 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7337 mono_domain_unlock (domain);
7344 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7346 ext->lmf.previous_lmf = prev_lmf;
7347 /* Mark that this is a MonoLMFExt */
7348 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7349 ext->lmf.sp = (gssize)ext;
7353 * mono_arch_set_target:
7355 * Set the target architecture the JIT backend should generate code for, in the form
7356 * of a GNU target triplet. Only used in AOT mode.
7359 mono_arch_set_target (char *mtriple)
7361 /* The GNU target triple format is not very well documented */
7362 if (strstr (mtriple, "armv7")) {
7363 v5_supported = TRUE;
7364 v6_supported = TRUE;
7365 v7_supported = TRUE;
7367 if (strstr (mtriple, "armv6")) {
7368 v5_supported = TRUE;
7369 v6_supported = TRUE;
7371 if (strstr (mtriple, "armv7s")) {
7372 v7s_supported = TRUE;
7374 if (strstr (mtriple, "thumbv7s")) {
7375 v5_supported = TRUE;
7376 v6_supported = TRUE;
7377 v7_supported = TRUE;
7378 v7s_supported = TRUE;
7379 thumb_supported = TRUE;
7380 thumb2_supported = TRUE;
7382 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7383 v5_supported = TRUE;
7384 v6_supported = TRUE;
7385 thumb_supported = TRUE;
7388 if (strstr (mtriple, "gnueabi"))
7389 eabi_supported = TRUE;
7393 mono_arch_opcode_supported (int opcode)
7396 case OP_ATOMIC_ADD_I4:
7397 case OP_ATOMIC_EXCHANGE_I4:
7398 case OP_ATOMIC_CAS_I4:
7399 case OP_ATOMIC_LOAD_I1:
7400 case OP_ATOMIC_LOAD_I2:
7401 case OP_ATOMIC_LOAD_I4:
7402 case OP_ATOMIC_LOAD_U1:
7403 case OP_ATOMIC_LOAD_U2:
7404 case OP_ATOMIC_LOAD_U4:
7405 case OP_ATOMIC_STORE_I1:
7406 case OP_ATOMIC_STORE_I2:
7407 case OP_ATOMIC_STORE_I4:
7408 case OP_ATOMIC_STORE_U1:
7409 case OP_ATOMIC_STORE_U2:
7410 case OP_ATOMIC_STORE_U4:
7411 return v7_supported;
7412 case OP_ATOMIC_LOAD_R4:
7413 case OP_ATOMIC_LOAD_R8:
7414 case OP_ATOMIC_STORE_R4:
7415 case OP_ATOMIC_STORE_R8:
7416 return v7_supported && IS_VFP;
7422 #if defined(ENABLE_GSHAREDVT)
7424 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7426 #endif /* !MONOTOUCH */