mono/mini/mini-arm.c

   1 /*
   2  * mini-arm.c: ARM backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *
   8  * (C) 2003 Ximian, Inc.
   9  */
  10 #include "mini.h"
  11 #include <string.h>
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/utils/mono-mmap.h>
  16
  17 #include "mini-arm.h"
  18 #include "cpu-arm.h"
  19 #include "trace.h"
  20 #include "ir-emit.h"
  21 #ifdef ARM_FPU_FPA
  22 #include "mono/arch/arm/arm-fpa-codegen.h"
  23 #elif defined(ARM_FPU_VFP)
  24 #include "mono/arch/arm/arm-vfp-codegen.h"
  25 #endif
  26
  27 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
  28 #define HAVE_AEABI_READ_TP 1
  29 #endif
  30
  31 static gint lmf_tls_offset = -1;
  32 static gint lmf_addr_tls_offset = -1;
  33
  34 /* This mutex protects architecture specific caches */
  35 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  36 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  37 static CRITICAL_SECTION mini_arch_mutex;
  38
  39 static int v5_supported = 0;
  40 static int v7_supported = 0;
  41 static int thumb_supported = 0;
  42 /*
  43  * Whenever to use the ARM EABI
  44  */
  45 static int eabi_supported = 0;
  46
  47 /*
  48  * Whenever we are on arm/darwin aka the iphone.
  49  */
  50 static int darwin = 0;
  51 /*
  52  * Whenever to use the iphone ABI extensions:
  53  * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
  54  * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
  55  * This is required for debugging/profiling tools to work, but it has some overhead so it should
  56  * only be turned on in debug builds.
  57  */
  58 static int iphone_abi = 0;
  59 static int i8_align;
  60
  61 /*
  62  * The code generated for sequence points reads from this location, which is
  63  * made read-only when single stepping is enabled.
  64  */
  65 static gpointer ss_trigger_page;
  66
  67 /* Enabled breakpoints read from this trigger page */
  68 static gpointer bp_trigger_page;
  69
  70 /* Structure used by the sequence points in AOTed code */
  71 typedef struct {
  72         gpointer ss_trigger_page;
  73         gpointer bp_trigger_page;
  74         guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
  75 } SeqPointInfo;
  76
  77 /*
  78  * TODO:
  79  * floating point support: on ARM it is a mess, there are at least 3
  80  * different setups, each of which binary incompat with the other.
  81  * 1) FPA: old and ugly, but unfortunately what current distros use
  82  *    the double binary format has the two words swapped. 8 double registers.
  83  *    Implemented usually by kernel emulation.
  84  * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
  85  *    ugly swapped double format (I guess a softfloat-vfp exists, too, though).
  86  * 3) VFP: the new and actually sensible and useful FP support. Implemented
  87  *    in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
  88  *
  89  * The plan is to write the FPA support first. softfloat can be tested in a chroot.
  90  */
  91 int mono_exc_esp_offset = 0;
  92
  93 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
  94 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
  95 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
  96
  97 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
  98 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
  99 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
 100
 101 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
 102 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) |  (ARMREG_LR << 12) | ARMREG_PC)
 103 #define DEBUG_IMT 0
 104
 105 /* A variant of ARM_LDR_IMM which can handle large offsets */
 106 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
 107         if (arm_is_imm12 ((offset))) { \
 108                 ARM_LDR_IMM (code, (dreg), (basereg), (offset));        \
 109         } else {                                                                                                \
 110                 g_assert ((scratch_reg) != (basereg));                                     \
 111                 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset));  \
 112                 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg));               \
 113         }                                                                                                                                       \
 114         } while (0)
 115
 116 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do {      \
 117         if (arm_is_imm12 ((offset))) { \
 118                 ARM_STR_IMM (code, (dreg), (basereg), (offset));        \
 119         } else {                                                                                                \
 120                 g_assert ((scratch_reg) != (basereg));                                     \
 121                 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset));  \
 122                 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg));               \
 123         }                                                                                                                                       \
 124         } while (0)
 125
 126 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
 127
 128 const char*
 129 mono_arch_regname (int reg)
 130 {
 131         static const char * rnames[] = {
 132                 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
 133                 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
 134                 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
 135                 "arm_pc"
 136         };
 137         if (reg >= 0 && reg < 16)
 138                 return rnames [reg];
 139         return "unknown";
 140 }
 141
 142 const char*
 143 mono_arch_fregname (int reg)
 144 {
 145         static const char * rnames[] = {
 146                 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
 147                 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
 148                 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
 149                 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
 150                 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
 151                 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
 152                 "arm_f30", "arm_f31"
 153         };
 154         if (reg >= 0 && reg < 32)
 155                 return rnames [reg];
 156         return "unknown";
 157 }
 158
 159 #ifndef DISABLE_JIT
 160
 161 static guint8*
 162 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
 163 {
 164         int imm8, rot_amount;
 165         if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
 166                 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
 167                 return code;
 168         }
 169         g_assert (dreg != sreg);
 170         code = mono_arm_emit_load_imm (code, dreg, imm);
 171         ARM_ADD_REG_REG (code, dreg, dreg, sreg);
 172         return code;
 173 }
 174
 175 static guint8*
 176 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
 177 {
 178         /* we can use r0-r3, since this is called only for incoming args on the stack */
 179         if (size > sizeof (gpointer) * 4) {
 180                 guint8 *start_loop;
 181                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
 182                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
 183                 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
 184                 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
 185                 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
 186                 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
 187                 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
 188                 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
 189                 ARM_B_COND (code, ARMCOND_NE, 0);
 190                 arm_patch (code - 4, start_loop);
 191                 return code;
 192         }
 193         if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
 194                         arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
 195                 while (size >= 4) {
 196                         ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
 197                         ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
 198                         doffset += 4;
 199                         soffset += 4;
 200                         size -= 4;
 201                 }
 202         } else if (size) {
 203                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
 204                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
 205                 doffset = soffset = 0;
 206                 while (size >= 4) {
 207                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
 208                         ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
 209                         doffset += 4;
 210                         soffset += 4;
 211                         size -= 4;
 212                 }
 213         }
 214         g_assert (size == 0);
 215         return code;
 216 }
 217
 218 static guint8*
 219 emit_call_reg (guint8 *code, int reg)
 220 {
 221         if (v5_supported) {
 222                 ARM_BLX_REG (code, reg);
 223         } else {
 224                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
 225                 if (thumb_supported)
 226                         ARM_BX (code, reg);
 227                 else
 228                         ARM_MOV_REG_REG (code, ARMREG_PC, reg);
 229         }
 230         return code;
 231 }
 232
 233 static guint8*
 234 emit_call_seq (MonoCompile *cfg, guint8 *code)
 235 {
 236         if (cfg->method->dynamic) {
 237                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
 238                 ARM_B (code, 0);
 239                 *(gpointer*)code = NULL;
 240                 code += 4;
 241                 code = emit_call_reg (code, ARMREG_IP);
 242         } else {
 243                 ARM_BL (code, 0);
 244         }
 245         return code;
 246 }
 247
 248 static guint8*
 249 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
 250 {
 251         switch (ins->opcode) {
 252         case OP_FCALL:
 253         case OP_FCALL_REG:
 254         case OP_FCALL_MEMBASE:
 255 #ifdef ARM_FPU_FPA
 256                 if (ins->dreg != ARM_FPA_F0)
 257                         ARM_MVFD (code, ins->dreg, ARM_FPA_F0);
 258 #elif defined(ARM_FPU_VFP)
 259                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
 260                         ARM_FMSR (code, ins->dreg, ARMREG_R0);
 261                         ARM_CVTS (code, ins->dreg, ins->dreg);
 262                 } else {
 263                         ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
 264                 }
 265 #endif
 266                 break;
 267         }
 268
 269         return code;
 270 }
 271
 272 #endif /* #ifndef DISABLE_JIT */
 273
 274 /*
 275  * mono_arch_get_argument_info:
 276  * @csig:  a method signature
 277  * @param_count: the number of parameters to consider
 278  * @arg_info: an array to store the result infos
 279  *
 280  * Gathers information on parameters such as size, alignment and
 281  * padding. arg_info should be large enought to hold param_count + 1 entries.
 282  *
 283  * Returns the size of the activation frame.
 284  */
 285 int
 286 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 287 {
 288         int k, frame_size = 0;
 289         guint32 size, align, pad;
 290         int offset = 8;
 291
 292         if (MONO_TYPE_ISSTRUCT (csig->ret)) {
 293                 frame_size += sizeof (gpointer);
 294                 offset += 4;
 295         }
 296
 297         arg_info [0].offset = offset;
 298
 299         if (csig->hasthis) {
 300                 frame_size += sizeof (gpointer);
 301                 offset += 4;
 302         }
 303
 304         arg_info [0].size = frame_size;
 305
 306         for (k = 0; k < param_count; k++) {
 307                 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
 308
 309                 /* ignore alignment for now */
 310                 align = 1;
 311
 312                 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 313                 arg_info [k].pad = pad;
 314                 frame_size += size;
 315                 arg_info [k + 1].pad = 0;
 316                 arg_info [k + 1].size = size;
 317                 offset += pad;
 318                 arg_info [k + 1].offset = offset;
 319                 offset += size;
 320         }
 321
 322         align = MONO_ARCH_FRAME_ALIGNMENT;
 323         frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 324         arg_info [k].pad = pad;
 325
 326         return frame_size;
 327 }
 328
 329 #define MAX_ARCH_DELEGATE_PARAMS 3
 330
 331 static gpointer
 332 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
 333 {
 334         guint8 *code, *start;
 335
 336         if (has_target) {
 337                 start = code = mono_global_codeman_reserve (12);
 338
 339                 /* Replace the this argument with the target */
 340                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
 341                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
 342                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 343
 344                 g_assert ((code - start) <= 12);
 345
 346                 mono_arch_flush_icache (start, 12);
 347         } else {
 348                 int size, i;
 349
 350                 size = 8 + param_count * 4;
 351                 start = code = mono_global_codeman_reserve (size);
 352
 353                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
 354                 /* slide down the arguments */
 355                 for (i = 0; i < param_count; ++i) {
 356                         ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
 357                 }
 358                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 359
 360                 g_assert ((code - start) <= size);
 361
 362                 mono_arch_flush_icache (start, size);
 363         }
 364
 365         if (code_size)
 366                 *code_size = code - start;
 367
 368         return start;
 369 }
 370
 371 /*
 372  * mono_arch_get_delegate_invoke_impls:
 373  *
 374  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
 375  * trampolines.
 376  */
 377 GSList*
 378 mono_arch_get_delegate_invoke_impls (void)
 379 {
 380         GSList *res = NULL;
 381         guint8 *code;
 382         guint32 code_len;
 383         int i;
 384
 385         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
 386         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
 387
 388         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
 389                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
 390                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
 391         }
 392
 393         return res;
 394 }
 395
 396 gpointer
 397 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
 398 {
 399         guint8 *code, *start;
 400
 401         /* FIXME: Support more cases */
 402         if (MONO_TYPE_ISSTRUCT (sig->ret))
 403                 return NULL;
 404
 405         if (has_target) {
 406                 static guint8* cached = NULL;
 407                 mono_mini_arch_lock ();
 408                 if (cached) {
 409                         mono_mini_arch_unlock ();
 410                         return cached;
 411                 }
 412
 413                 if (mono_aot_only)
 414                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
 415                 else
 416                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
 417                 cached = start;
 418                 mono_mini_arch_unlock ();
 419                 return cached;
 420         } else {
 421                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
 422                 int i;
 423
 424                 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
 425                         return NULL;
 426                 for (i = 0; i < sig->param_count; ++i)
 427                         if (!mono_is_regsize_var (sig->params [i]))
 428                                 return NULL;
 429
 430                 mono_mini_arch_lock ();
 431                 code = cache [sig->param_count];
 432                 if (code) {
 433                         mono_mini_arch_unlock ();
 434                         return code;
 435                 }
 436
 437                 if (mono_aot_only) {
 438                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
 439                         start = mono_aot_get_trampoline (name);
 440                         g_free (name);
 441                 } else {
 442                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
 443                 }
 444                 cache [sig->param_count] = start;
 445                 mono_mini_arch_unlock ();
 446                 return start;
 447         }
 448
 449         return NULL;
 450 }
 451
 452 gpointer
 453 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
 454 {
 455         return (gpointer)regs [ARMREG_R0];
 456 }
 457
 458 /*
 459  * Initialize the cpu to execute managed code.
 460  */
 461 void
 462 mono_arch_cpu_init (void)
 463 {
 464 #if defined(__ARM_EABI__)
 465         eabi_supported = TRUE;
 466 #endif
 467 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
 468                 i8_align = 4;
 469 #else
 470                 i8_align = __alignof__ (gint64);
 471 #endif
 472 }
 473
 474 /*
 475  * Initialize architecture specific code.
 476  */
 477 void
 478 mono_arch_init (void)
 479 {
 480         InitializeCriticalSection (&mini_arch_mutex);
 481
 482         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 483         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 484         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 485
 486         mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
 487         mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
 488         mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
 489 }
 490
 491 /*
 492  * Cleanup architecture specific code.
 493  */
 494 void
 495 mono_arch_cleanup (void)
 496 {
 497 }
 498
 499 /*
 500  * This function returns the optimizations supported on this cpu.
 501  */
 502 guint32
 503 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 504 {
 505         guint32 opts = 0;
 506         const char *cpu_arch = getenv ("MONO_CPU_ARCH");
 507         if (cpu_arch != NULL) {
 508                 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
 509                 if (strncmp (cpu_arch, "armv", 4) == 0) {
 510                         v5_supported = cpu_arch [4] >= '5';
 511                         v7_supported = cpu_arch [4] >= '7';
 512                 }
 513         } else {
 514 #if __APPLE__
 515         thumb_supported = TRUE;
 516         v5_supported = TRUE;
 517         darwin = TRUE;
 518         iphone_abi = TRUE;
 519 #else
 520         char buf [512];
 521         char *line;
 522         FILE *file = fopen ("/proc/cpuinfo", "r");
 523         if (file) {
 524                 while ((line = fgets (buf, 512, file))) {
 525                         if (strncmp (line, "Processor", 9) == 0) {
 526                                 char *ver = strstr (line, "(v");
 527                                 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
 528                                         v5_supported = TRUE;
 529                                 if (ver && (ver [2] == '7'))
 530                                         v7_supported = TRUE;
 531                                 continue;
 532                         }
 533                         if (strncmp (line, "Features", 8) == 0) {
 534                                 char *th = strstr (line, "thumb");
 535                                 if (th) {
 536                                         thumb_supported = TRUE;
 537                                         if (v5_supported)
 538                                                 break;
 539                                 }
 540                                 continue;
 541                         }
 542                 }
 543                 fclose (file);
 544                 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
 545         }
 546 #endif
 547         }
 548
 549         /* no arm-specific optimizations yet */
 550         *exclude_mask = 0;
 551         return opts;
 552 }
 553
 554 #ifndef DISABLE_JIT
 555
 556 static gboolean
 557 is_regsize_var (MonoType *t) {
 558         if (t->byref)
 559                 return TRUE;
 560         t = mini_type_get_underlying_type (NULL, t);
 561         switch (t->type) {
 562         case MONO_TYPE_I4:
 563         case MONO_TYPE_U4:
 564         case MONO_TYPE_I:
 565         case MONO_TYPE_U:
 566         case MONO_TYPE_PTR:
 567         case MONO_TYPE_FNPTR:
 568                 return TRUE;
 569         case MONO_TYPE_OBJECT:
 570         case MONO_TYPE_STRING:
 571         case MONO_TYPE_CLASS:
 572         case MONO_TYPE_SZARRAY:
 573         case MONO_TYPE_ARRAY:
 574                 return TRUE;
 575         case MONO_TYPE_GENERICINST:
 576                 if (!mono_type_generic_inst_is_valuetype (t))
 577                         return TRUE;
 578                 return FALSE;
 579         case MONO_TYPE_VALUETYPE:
 580                 return FALSE;
 581         }
 582         return FALSE;
 583 }
 584
 585 GList *
 586 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 587 {
 588         GList *vars = NULL;
 589         int i;
 590
 591         for (i = 0; i < cfg->num_varinfo; i++) {
 592                 MonoInst *ins = cfg->varinfo [i];
 593                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 594
 595                 /* unused vars */
 596                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 597                         continue;
 598
 599                 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 600                         continue;
 601
 602                 /* we can only allocate 32 bit values */
 603                 if (is_regsize_var (ins->inst_vtype)) {
 604                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 605                         g_assert (i == vmv->idx);
 606                         vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
 607                 }
 608         }
 609
 610         return vars;
 611 }
 612
 613 #define USE_EXTRA_TEMPS 0
 614
 615 GList *
 616 mono_arch_get_global_int_regs (MonoCompile *cfg)
 617 {
 618         GList *regs = NULL;
 619
 620         mono_arch_compute_omit_fp (cfg);
 621
 622         /*
 623          * FIXME: Interface calls might go through a static rgctx trampoline which
 624          * sets V5, but it doesn't save it, so we need to save it ourselves, and
 625          * avoid using it.
 626          */
 627         if (cfg->flags & MONO_CFG_HAS_CALLS)
 628                 cfg->uses_rgctx_reg = TRUE;
 629
 630         if (cfg->arch.omit_fp)
 631                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
 632         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
 633         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
 634         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
 635         if (darwin)
 636                 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
 637                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
 638         else
 639                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
 640         if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
 641                 /* V5 is reserved for passing the vtable/rgctx/IMT method */
 642                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
 643         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
 644         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
 645
 646         return regs;
 647 }
 648
 649 /*
 650  * mono_arch_regalloc_cost:
 651  *
 652  *  Return the cost, in number of memory references, of the action of
 653  * allocating the variable VMV into a register during global register
 654  * allocation.
 655  */
 656 guint32
 657 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 658 {
 659         /* FIXME: */
 660         return 2;
 661 }
 662
 663 #endif /* #ifndef DISABLE_JIT */
 664
 665 #ifndef __GNUC_PREREQ
 666 #define __GNUC_PREREQ(maj, min) (0)
 667 #endif
 668
 669 void
 670 mono_arch_flush_icache (guint8 *code, gint size)
 671 {
 672 #if __APPLE__
 673         sys_icache_invalidate (code, size);
 674 #elif __GNUC_PREREQ(4, 1)
 675         __clear_cache (code, code + size);
 676 #elif defined(PLATFORM_ANDROID)
 677         const int syscall = 0xf0002;
 678         __asm __volatile (
 679                 "mov     r0, %0\n"
 680                 "mov     r1, %1\n"
 681                 "mov     r7, %2\n"
 682                 "mov     r2, #0x0\n"
 683                 "svc     0x00000000\n"
 684                 :
 685                 :       "r" (code), "r" (code + size), "r" (syscall)
 686                 :       "r0", "r1", "r7", "r2"
 687                 );
 688 #else
 689         __asm __volatile ("mov r0, %0\n"
 690                         "mov r1, %1\n"
 691                         "mov r2, %2\n"
 692                         "swi 0x9f0002       @ sys_cacheflush"
 693                         : /* no outputs */
 694                         : "r" (code), "r" (code + size), "r" (0)
 695                         : "r0", "r1", "r3" );
 696 #endif
 697 }
 698
 699 typedef enum {
 700         RegTypeNone,
 701         RegTypeGeneral,
 702         RegTypeIRegPair,
 703         RegTypeBase,
 704         RegTypeBaseGen,
 705         RegTypeFP,
 706         RegTypeStructByVal,
 707         RegTypeStructByAddr
 708 } ArgStorage;
 709
 710 typedef struct {
 711         gint32  offset;
 712         guint16 vtsize; /* in param area */
 713         guint8  reg;
 714         ArgStorage  storage;
 715         guint8  size    : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
 716 } ArgInfo;
 717
 718 typedef struct {
 719         int nargs;
 720         guint32 stack_usage;
 721         gboolean vtype_retaddr;
 722         /* The index of the vret arg in the argument list */
 723         int vret_arg_index;
 724         ArgInfo ret;
 725         ArgInfo sig_cookie;
 726         ArgInfo args [1];
 727 } CallInfo;
 728
 729 #define DEBUG(a)
 730
 731 #ifndef __GNUC__
 732 /*#define __alignof__(a) sizeof(a)*/
 733 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
 734 #endif
 735
 736 #define PARAM_REGS 4
 737
 738 static void inline
 739 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
 740 {
 741         if (simple) {
 742                 if (*gr > ARMREG_R3) {
 743                         ainfo->offset = *stack_size;
 744                         ainfo->reg = ARMREG_SP; /* in the caller */
 745                         ainfo->storage = RegTypeBase;
 746                         *stack_size += 4;
 747                 } else {
 748                         ainfo->storage = RegTypeGeneral;
 749                         ainfo->reg = *gr;
 750                 }
 751         } else {
 752                 gboolean split;
 753
 754                 if (eabi_supported)
 755                         split = i8_align == 4;
 756                 else
 757                         split = TRUE;
 758
 759                 if (*gr == ARMREG_R3 && split) {
 760                         /* first word in r3 and the second on the stack */
 761                         ainfo->offset = *stack_size;
 762                         ainfo->reg = ARMREG_SP; /* in the caller */
 763                         ainfo->storage = RegTypeBaseGen;
 764                         *stack_size += 4;
 765                 } else if (*gr >= ARMREG_R3) {
 766                         if (eabi_supported) {
 767                                 /* darwin aligns longs to 4 byte only */
 768                                 if (i8_align == 8) {
 769                                         *stack_size += 7;
 770                                         *stack_size &= ~7;
 771                                 }
 772                         }
 773                         ainfo->offset = *stack_size;
 774                         ainfo->reg = ARMREG_SP; /* in the caller */
 775                         ainfo->storage = RegTypeBase;
 776                         *stack_size += 8;
 777                 } else {
 778                         if (eabi_supported) {
 779                                 if (i8_align == 8 && ((*gr) & 1))
 780                                         (*gr) ++;
 781                         }
 782                         ainfo->storage = RegTypeIRegPair;
 783                         ainfo->reg = *gr;
 784                 }
 785                 (*gr) ++;
 786         }
 787         (*gr) ++;
 788 }
 789
 790 static CallInfo*
 791 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 792 {
 793         guint i, gr, pstart;
 794         int n = sig->hasthis + sig->param_count;
 795         MonoType *simpletype;
 796         guint32 stack_size = 0;
 797         CallInfo *cinfo;
 798         gboolean is_pinvoke = sig->pinvoke;
 799
 800         if (mp)
 801                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 802         else
 803                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 804
 805         cinfo->nargs = n;
 806         gr = ARMREG_R0;
 807
 808         /* FIXME: handle returning a struct */
 809         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 810                 guint32 align;
 811
 812                 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (sig->ret), &align) <= sizeof (gpointer)) {
 813                         cinfo->ret.storage = RegTypeStructByVal;
 814                 } else {
 815                         cinfo->vtype_retaddr = TRUE;
 816                 }
 817         }
 818
 819         pstart = 0;
 820         n = 0;
 821         /*
 822          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 823          * the first argument, allowing 'this' to be always passed in the first arg reg.
 824          * Also do this if the first argument is a reference type, since virtual calls
 825          * are sometimes made using calli without sig->hasthis set, like in the delegate
 826          * invoke wrappers.
 827          */
 828         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
 829                 if (sig->hasthis) {
 830                         add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
 831                 } else {
 832                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
 833                         pstart = 1;
 834                 }
 835                 n ++;
 836                 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
 837                 cinfo->vret_arg_index = 1;
 838         } else {
 839                 /* this */
 840                 if (sig->hasthis) {
 841                         add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
 842                         n ++;
 843                 }
 844
 845                 if (cinfo->vtype_retaddr)
 846                         add_general (&gr, &stack_size, &cinfo->ret, TRUE);
 847         }
 848
 849         DEBUG(printf("params: %d\n", sig->param_count));
 850         for (i = pstart; i < sig->param_count; ++i) {
 851                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 852                         /* Prevent implicit arguments and sig_cookie from
 853                            being passed in registers */
 854                         gr = ARMREG_R3 + 1;
 855                         /* Emit the signature cookie just before the implicit arguments */
 856                         add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
 857                 }
 858                 DEBUG(printf("param %d: ", i));
 859                 if (sig->params [i]->byref) {
 860                         DEBUG(printf("byref\n"));
 861                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 862                         n++;
 863                         continue;
 864                 }
 865                 simpletype = mini_type_get_underlying_type (NULL, sig->params [i]);
 866                 switch (simpletype->type) {
 867                 case MONO_TYPE_BOOLEAN:
 868                 case MONO_TYPE_I1:
 869                 case MONO_TYPE_U1:
 870                         cinfo->args [n].size = 1;
 871                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 872                         n++;
 873                         break;
 874                 case MONO_TYPE_CHAR:
 875                 case MONO_TYPE_I2:
 876                 case MONO_TYPE_U2:
 877                         cinfo->args [n].size = 2;
 878                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 879                         n++;
 880                         break;
 881                 case MONO_TYPE_I4:
 882                 case MONO_TYPE_U4:
 883                         cinfo->args [n].size = 4;
 884                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 885                         n++;
 886                         break;
 887                 case MONO_TYPE_I:
 888                 case MONO_TYPE_U:
 889                 case MONO_TYPE_PTR:
 890                 case MONO_TYPE_FNPTR:
 891                 case MONO_TYPE_CLASS:
 892                 case MONO_TYPE_OBJECT:
 893                 case MONO_TYPE_STRING:
 894                 case MONO_TYPE_SZARRAY:
 895                 case MONO_TYPE_ARRAY:
 896                 case MONO_TYPE_R4:
 897                         cinfo->args [n].size = sizeof (gpointer);
 898                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 899                         n++;
 900                         break;
 901                 case MONO_TYPE_GENERICINST:
 902                         if (!mono_type_generic_inst_is_valuetype (simpletype)) {
 903                                 cinfo->args [n].size = sizeof (gpointer);
 904                                 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 905                                 n++;
 906                                 break;
 907                         }
 908                         /* Fall through */
 909                 case MONO_TYPE_TYPEDBYREF:
 910                 case MONO_TYPE_VALUETYPE: {
 911                         gint size;
 912                         int align_size;
 913                         int nwords;
 914                         guint32 align;
 915
 916                         if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
 917                                 size = sizeof (MonoTypedRef);
 918                                 align = sizeof (gpointer);
 919                         } else {
 920                                 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
 921                                 if (is_pinvoke)
 922                                         size = mono_class_native_size (klass, &align);
 923                                 else
 924                                         size = mono_class_value_size (klass, &align);
 925                         }
 926                         DEBUG(printf ("load %d bytes struct\n",
 927                                       mono_class_native_size (sig->params [i]->data.klass, NULL)));
 928                         align_size = size;
 929                         nwords = 0;
 930                         align_size += (sizeof (gpointer) - 1);
 931                         align_size &= ~(sizeof (gpointer) - 1);
 932                         nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
 933                         cinfo->args [n].storage = RegTypeStructByVal;
 934                         /* FIXME: align stack_size if needed */
 935                         if (eabi_supported) {
 936                                 if (align >= 8 && (gr & 1))
 937                                         gr ++;
 938                         }
 939                         if (gr > ARMREG_R3) {
 940                                 cinfo->args [n].size = 0;
 941                                 cinfo->args [n].vtsize = nwords;
 942                         } else {
 943                                 int rest = ARMREG_R3 - gr + 1;
 944                                 int n_in_regs = rest >= nwords? nwords: rest;
 945
 946                                 cinfo->args [n].size = n_in_regs;
 947                                 cinfo->args [n].vtsize = nwords - n_in_regs;
 948                                 cinfo->args [n].reg = gr;
 949                                 gr += n_in_regs;
 950                                 nwords -= n_in_regs;
 951                         }
 952                         cinfo->args [n].offset = stack_size;
 953                         /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
 954                         stack_size += nwords * sizeof (gpointer);
 955                         n++;
 956                         break;
 957                 }
 958                 case MONO_TYPE_U8:
 959                 case MONO_TYPE_I8:
 960                 case MONO_TYPE_R8:
 961                         cinfo->args [n].size = 8;
 962                         add_general (&gr, &stack_size, cinfo->args + n, FALSE);
 963                         n++;
 964                         break;
 965                 default:
 966                         g_error ("Can't trampoline 0x%x", sig->params [i]->type);
 967                 }
 968         }
 969
 970         /* Handle the case where there are no implicit arguments */
 971         if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 972                 /* Prevent implicit arguments and sig_cookie from
 973                    being passed in registers */
 974                 gr = ARMREG_R3 + 1;
 975                 /* Emit the signature cookie just before the implicit arguments */
 976                 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
 977         }
 978
 979         {
 980                 simpletype = mini_type_get_underlying_type (NULL, sig->ret);
 981                 switch (simpletype->type) {
 982                 case MONO_TYPE_BOOLEAN:
 983                 case MONO_TYPE_I1:
 984                 case MONO_TYPE_U1:
 985                 case MONO_TYPE_I2:
 986                 case MONO_TYPE_U2:
 987                 case MONO_TYPE_CHAR:
 988                 case MONO_TYPE_I4:
 989                 case MONO_TYPE_U4:
 990                 case MONO_TYPE_I:
 991                 case MONO_TYPE_U:
 992                 case MONO_TYPE_PTR:
 993                 case MONO_TYPE_FNPTR:
 994                 case MONO_TYPE_CLASS:
 995                 case MONO_TYPE_OBJECT:
 996                 case MONO_TYPE_SZARRAY:
 997                 case MONO_TYPE_ARRAY:
 998                 case MONO_TYPE_STRING:
 999                         cinfo->ret.storage = RegTypeGeneral;
1000                         cinfo->ret.reg = ARMREG_R0;
1001                         break;
1002                 case MONO_TYPE_U8:
1003                 case MONO_TYPE_I8:
1004                         cinfo->ret.storage = RegTypeIRegPair;
1005                         cinfo->ret.reg = ARMREG_R0;
1006                         break;
1007                 case MONO_TYPE_R4:
1008                 case MONO_TYPE_R8:
1009                         cinfo->ret.storage = RegTypeFP;
1010                         cinfo->ret.reg = ARMREG_R0;
1011                         /* FIXME: cinfo->ret.reg = ???;
1012                         cinfo->ret.storage = RegTypeFP;*/
1013                         break;
1014                 case MONO_TYPE_GENERICINST:
1015                         if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1016                                 cinfo->ret.storage = RegTypeGeneral;
1017                                 cinfo->ret.reg = ARMREG_R0;
1018                                 break;
1019                         }
1020                         /* Fall through */
1021                 case MONO_TYPE_VALUETYPE:
1022                 case MONO_TYPE_TYPEDBYREF:
1023                         if (cinfo->ret.storage != RegTypeStructByVal)
1024                                 cinfo->ret.storage = RegTypeStructByAddr;
1025                         break;
1026                 case MONO_TYPE_VOID:
1027                         break;
1028                 default:
1029                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
1030                 }
1031         }
1032
1033         /* align stack size to 8 */
1034         DEBUG (printf ("      stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1035         stack_size = (stack_size + 7) & ~7;
1036
1037         cinfo->stack_usage = stack_size;
1038         return cinfo;
1039 }
1040
1041 #ifndef DISABLE_JIT
1042
1043 G_GNUC_UNUSED static void
1044 break_count (void)
1045 {
1046 }
1047
1048 G_GNUC_UNUSED static gboolean
1049 debug_count (void)
1050 {
1051         static int count = 0;
1052         count ++;
1053
1054         if (!getenv ("COUNT"))
1055                 return TRUE;
1056
1057         if (count == atoi (getenv ("COUNT"))) {
1058                 break_count ();
1059         }
1060
1061         if (count > atoi (getenv ("COUNT"))) {
1062                 return FALSE;
1063         }
1064
1065         return TRUE;
1066 }
1067
1068 static gboolean
1069 debug_omit_fp (void)
1070 {
1071 #if 0
1072         return debug_count ();
1073 #else
1074         return TRUE;
1075 #endif
1076 }
1077
1078 /**
1079  * mono_arch_compute_omit_fp:
1080  *
1081  *   Determine whenever the frame pointer can be eliminated.
1082  */
1083 static void
1084 mono_arch_compute_omit_fp (MonoCompile *cfg)
1085 {
1086         MonoMethodSignature *sig;
1087         MonoMethodHeader *header;
1088         int i, locals_size;
1089         CallInfo *cinfo;
1090
1091         if (cfg->arch.omit_fp_computed)
1092                 return;
1093
1094         header = cfg->header;
1095
1096         sig = mono_method_signature (cfg->method);
1097
1098         if (!cfg->arch.cinfo)
1099                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1100         cinfo = cfg->arch.cinfo;
1101
1102         /*
1103          * FIXME: Remove some of the restrictions.
1104          */
1105         cfg->arch.omit_fp = TRUE;
1106         cfg->arch.omit_fp_computed = TRUE;
1107
1108         if (cfg->disable_omit_fp)
1109                 cfg->arch.omit_fp = FALSE;
1110         if (!debug_omit_fp ())
1111                 cfg->arch.omit_fp = FALSE;
1112         /*
1113         if (cfg->method->save_lmf)
1114                 cfg->arch.omit_fp = FALSE;
1115         */
1116         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1117                 cfg->arch.omit_fp = FALSE;
1118         if (header->num_clauses)
1119                 cfg->arch.omit_fp = FALSE;
1120         if (cfg->param_area)
1121                 cfg->arch.omit_fp = FALSE;
1122         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1123                 cfg->arch.omit_fp = FALSE;
1124         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1125                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1126                 cfg->arch.omit_fp = FALSE;
1127         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1128                 ArgInfo *ainfo = &cinfo->args [i];
1129
1130                 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1131                         /*
1132                          * The stack offset can only be determined when the frame
1133                          * size is known.
1134                          */
1135                         cfg->arch.omit_fp = FALSE;
1136                 }
1137         }
1138
1139         locals_size = 0;
1140         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1141                 MonoInst *ins = cfg->varinfo [i];
1142                 int ialign;
1143
1144                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1145         }
1146 }
1147
1148 /*
1149  * Set var information according to the calling convention. arm version.
1150  * The locals var stuff should most likely be split in another method.
1151  */
1152 void
1153 mono_arch_allocate_vars (MonoCompile *cfg)
1154 {
1155         MonoMethodSignature *sig;
1156         MonoMethodHeader *header;
1157         MonoInst *ins;
1158         int i, offset, size, align, curinst;
1159         CallInfo *cinfo;
1160         guint32 ualign;
1161
1162         sig = mono_method_signature (cfg->method);
1163
1164         if (!cfg->arch.cinfo)
1165                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1166         cinfo = cfg->arch.cinfo;
1167
1168         mono_arch_compute_omit_fp (cfg);
1169
1170         if (cfg->arch.omit_fp)
1171                 cfg->frame_reg = ARMREG_SP;
1172         else
1173                 cfg->frame_reg = ARMREG_FP;
1174
1175         cfg->flags |= MONO_CFG_HAS_SPILLUP;
1176
1177         /* allow room for the vararg method args: void* and long/double */
1178         if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1179                 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1180
1181         header = cfg->header;
1182
1183         if (cfg->frame_reg != ARMREG_SP)
1184                 cfg->used_int_regs |= 1 << cfg->frame_reg;
1185
1186         if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1187                 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1188                 cfg->used_int_regs |= (1 << ARMREG_V5);
1189
1190         offset = 0;
1191         curinst = 0;
1192         if (!MONO_TYPE_ISSTRUCT (sig->ret)) {
1193                 switch (mini_type_get_underlying_type (NULL, sig->ret)->type) {
1194                 case MONO_TYPE_VOID:
1195                         break;
1196                 default:
1197                         cfg->ret->opcode = OP_REGVAR;
1198                         cfg->ret->inst_c0 = ARMREG_R0;
1199                         break;
1200                 }
1201         }
1202         /* local vars are at a positive offset from the stack pointer */
1203         /*
1204          * also note that if the function uses alloca, we use FP
1205          * to point at the local variables.
1206          */
1207         offset = 0; /* linkage area */
1208         /* align the offset to 16 bytes: not sure this is needed here  */
1209         //offset += 8 - 1;
1210         //offset &= ~(8 - 1);
1211
1212         /* add parameter area size for called functions */
1213         offset += cfg->param_area;
1214         offset += 8 - 1;
1215         offset &= ~(8 - 1);
1216         if (cfg->flags & MONO_CFG_HAS_FPOUT)
1217                 offset += 8;
1218
1219         /* allow room to save the return value */
1220         if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1221                 offset += 8;
1222
1223         /* the MonoLMF structure is stored just below the stack pointer */
1224         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1225                 if (cinfo->ret.storage == RegTypeStructByVal) {
1226                         cfg->ret->opcode = OP_REGOFFSET;
1227                         cfg->ret->inst_basereg = cfg->frame_reg;
1228                         offset += sizeof (gpointer) - 1;
1229                         offset &= ~(sizeof (gpointer) - 1);
1230                         cfg->ret->inst_offset = - offset;
1231                 } else {
1232                         ins = cfg->vret_addr;
1233                         offset += sizeof(gpointer) - 1;
1234                         offset &= ~(sizeof(gpointer) - 1);
1235                         ins->inst_offset = offset;
1236                         ins->opcode = OP_REGOFFSET;
1237                         ins->inst_basereg = cfg->frame_reg;
1238                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1239                                 printf ("vret_addr =");
1240                                 mono_print_ins (cfg->vret_addr);
1241                         }
1242                 }
1243                 offset += sizeof(gpointer);
1244         }
1245
1246         /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1247         if (cfg->arch.seq_point_info_var) {
1248                 MonoInst *ins;
1249
1250                 ins = cfg->arch.seq_point_info_var;
1251
1252                 size = 4;
1253                 align = 4;
1254                 offset += align - 1;
1255                 offset &= ~(align - 1);
1256                 ins->opcode = OP_REGOFFSET;
1257                 ins->inst_basereg = cfg->frame_reg;
1258                 ins->inst_offset = offset;
1259                 offset += size;
1260
1261                 ins = cfg->arch.ss_trigger_page_var;
1262                 size = 4;
1263                 align = 4;
1264                 offset += align - 1;
1265                 offset &= ~(align - 1);
1266                 ins->opcode = OP_REGOFFSET;
1267                 ins->inst_basereg = cfg->frame_reg;
1268                 ins->inst_offset = offset;
1269                 offset += size;
1270         }
1271
1272         curinst = cfg->locals_start;
1273         for (i = curinst; i < cfg->num_varinfo; ++i) {
1274                 ins = cfg->varinfo [i];
1275                 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1276                         continue;
1277
1278                 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1279                 * pinvoke wrappers when they call functions returning structure */
1280                 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (ins->inst_vtype) && ins->inst_vtype->type != MONO_TYPE_TYPEDBYREF) {
1281                         size = mono_class_native_size (mono_class_from_mono_type (ins->inst_vtype), &ualign);
1282                         align = ualign;
1283                 }
1284                 else
1285                         size = mono_type_size (ins->inst_vtype, &align);
1286
1287                 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1288                  * since it loads/stores misaligned words, which don't do the right thing.
1289                  */
1290                 if (align < 4 && size >= 4)
1291                         align = 4;
1292                 offset += align - 1;
1293                 offset &= ~(align - 1);
1294                 ins->opcode = OP_REGOFFSET;
1295                 ins->inst_offset = offset;
1296                 ins->inst_basereg = cfg->frame_reg;
1297                 offset += size;
1298                 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1299         }
1300
1301         curinst = 0;
1302         if (sig->hasthis) {
1303                 ins = cfg->args [curinst];
1304                 if (ins->opcode != OP_REGVAR) {
1305                         ins->opcode = OP_REGOFFSET;
1306                         ins->inst_basereg = cfg->frame_reg;
1307                         offset += sizeof (gpointer) - 1;
1308                         offset &= ~(sizeof (gpointer) - 1);
1309                         ins->inst_offset = offset;
1310                         offset += sizeof (gpointer);
1311                 }
1312                 curinst++;
1313         }
1314
1315         if (sig->call_convention == MONO_CALL_VARARG) {
1316                 size = 4;
1317                 align = 4;
1318
1319                 /* Allocate a local slot to hold the sig cookie address */
1320                 offset += align - 1;
1321                 offset &= ~(align - 1);
1322                 cfg->sig_cookie = offset;
1323                 offset += size;
1324         }
1325
1326         for (i = 0; i < sig->param_count; ++i) {
1327                 ins = cfg->args [curinst];
1328
1329                 if (ins->opcode != OP_REGVAR) {
1330                         ins->opcode = OP_REGOFFSET;
1331                         ins->inst_basereg = cfg->frame_reg;
1332                         size = mini_type_stack_size_full (NULL, sig->params [i], &ualign, sig->pinvoke);
1333                         align = ualign;
1334                         /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1335                          * since it loads/stores misaligned words, which don't do the right thing.
1336                          */
1337                         if (align < 4 && size >= 4)
1338                                 align = 4;
1339                         /* The code in the prolog () stores words when storing vtypes received in a register */
1340                         if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1341                                 align = 4;
1342                         offset += align - 1;
1343                         offset &= ~(align - 1);
1344                         ins->inst_offset = offset;
1345                         offset += size;
1346                 }
1347                 curinst++;
1348         }
1349
1350         /* align the offset to 8 bytes */
1351         offset += 8 - 1;
1352         offset &= ~(8 - 1);
1353
1354         /* change sign? */
1355         cfg->stack_offset = offset;
1356 }
1357
1358 void
1359 mono_arch_create_vars (MonoCompile *cfg)
1360 {
1361         MonoMethodSignature *sig;
1362         CallInfo *cinfo;
1363
1364         sig = mono_method_signature (cfg->method);
1365
1366         if (!cfg->arch.cinfo)
1367                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1368         cinfo = cfg->arch.cinfo;
1369
1370         if (cinfo->ret.storage == RegTypeStructByVal)
1371                 cfg->ret_var_is_local = TRUE;
1372
1373         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
1374                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1375                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1376                         printf ("vret_addr = ");
1377                         mono_print_ins (cfg->vret_addr);
1378                 }
1379         }
1380
1381         if (cfg->gen_seq_points && cfg->compile_aot) {
1382             MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1383                 ins->flags |= MONO_INST_VOLATILE;
1384                 cfg->arch.seq_point_info_var = ins;
1385
1386                 /* Allocate a separate variable for this to save 1 load per seq point */
1387             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1388                 ins->flags |= MONO_INST_VOLATILE;
1389                 cfg->arch.ss_trigger_page_var = ins;
1390         }
1391 }
1392
1393 static void
1394 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1395 {
1396         MonoMethodSignature *tmp_sig;
1397         MonoInst *sig_arg;
1398
1399         if (call->tail_call)
1400                 NOT_IMPLEMENTED;
1401
1402         /* FIXME: Add support for signature tokens to AOT */
1403         cfg->disable_aot = TRUE;
1404
1405         g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1406
1407         /*
1408          * mono_ArgIterator_Setup assumes the signature cookie is
1409          * passed first and all the arguments which were before it are
1410          * passed on the stack after the signature. So compensate by
1411          * passing a different signature.
1412          */
1413         tmp_sig = mono_metadata_signature_dup (call->signature);
1414         tmp_sig->param_count -= call->signature->sentinelpos;
1415         tmp_sig->sentinelpos = 0;
1416         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1417
1418         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1419         sig_arg->dreg = mono_alloc_ireg (cfg);
1420         sig_arg->inst_p0 = tmp_sig;
1421         MONO_ADD_INS (cfg->cbb, sig_arg);
1422
1423         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_arg->dreg);
1424 }
1425
1426 #ifdef ENABLE_LLVM
1427 LLVMCallInfo*
1428 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1429 {
1430         int i, n;
1431         CallInfo *cinfo;
1432         ArgInfo *ainfo;
1433         LLVMCallInfo *linfo;
1434
1435         n = sig->param_count + sig->hasthis;
1436
1437         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1438
1439         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1440
1441         /*
1442          * LLVM always uses the native ABI while we use our own ABI, the
1443          * only difference is the handling of vtypes:
1444          * - we only pass/receive them in registers in some cases, and only
1445          *   in 1 or 2 integer registers.
1446          */
1447         if (cinfo->vtype_retaddr) {
1448                 /* Vtype returned using a hidden argument */
1449                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1450                 linfo->vret_arg_index = cinfo->vret_arg_index;
1451         } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1452                 cfg->exception_message = g_strdup ("unknown ret conv");
1453                 cfg->disable_llvm = TRUE;
1454                 return linfo;
1455         }
1456
1457         for (i = 0; i < n; ++i) {
1458                 ainfo = cinfo->args + i;
1459
1460                 linfo->args [i].storage = LLVMArgNone;
1461
1462                 switch (ainfo->storage) {
1463                 case RegTypeGeneral:
1464                 case RegTypeIRegPair:
1465                 case RegTypeBase:
1466                         linfo->args [i].storage = LLVMArgInIReg;
1467                         break;
1468                 case RegTypeStructByVal:
1469                         // FIXME: Passing entirely on the stack or split reg/stack
1470                         if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1471                                 linfo->args [i].storage = LLVMArgVtypeInReg;
1472                                 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1473                                 if (ainfo->size == 2)
1474                                         linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1475                                 else
1476                                         linfo->args [i].pair_storage [1] = LLVMArgNone;
1477                         } else {
1478                                 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1479                                 cfg->disable_llvm = TRUE;
1480                         }
1481                         break;
1482                 default:
1483                         cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1484                         cfg->disable_llvm = TRUE;
1485                         break;
1486                 }
1487         }
1488
1489         return linfo;
1490 }
1491 #endif
1492
1493 void
1494 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1495 {
1496         MonoInst *in, *ins;
1497         MonoMethodSignature *sig;
1498         int i, n;
1499         CallInfo *cinfo;
1500
1501         sig = call->signature;
1502         n = sig->param_count + sig->hasthis;
1503
1504         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1505
1506         for (i = 0; i < n; ++i) {
1507                 ArgInfo *ainfo = cinfo->args + i;
1508                 MonoType *t;
1509
1510                 if (i >= sig->hasthis)
1511                         t = sig->params [i - sig->hasthis];
1512                 else
1513                         t = &mono_defaults.int_class->byval_arg;
1514                 t = mini_type_get_underlying_type (NULL, t);
1515
1516                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1517                         /* Emit the signature cookie just before the implicit arguments */
1518                         emit_sig_cookie (cfg, call, cinfo);
1519                 }
1520
1521                 in = call->args [i];
1522
1523                 switch (ainfo->storage) {
1524                 case RegTypeGeneral:
1525                 case RegTypeIRegPair:
1526                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1527                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1528                                 ins->dreg = mono_alloc_ireg (cfg);
1529                                 ins->sreg1 = in->dreg + 1;
1530                                 MONO_ADD_INS (cfg->cbb, ins);
1531                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1532
1533                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1534                                 ins->dreg = mono_alloc_ireg (cfg);
1535                                 ins->sreg1 = in->dreg + 2;
1536                                 MONO_ADD_INS (cfg->cbb, ins);
1537                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1538                         } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1539 #ifndef MONO_ARCH_SOFT_FLOAT
1540                                 int creg;
1541 #endif
1542
1543                                 if (ainfo->size == 4) {
1544 #ifdef MONO_ARCH_SOFT_FLOAT
1545                                         /* mono_emit_call_args () have already done the r8->r4 conversion */
1546                                         /* The converted value is in an int vreg */
1547                                         MONO_INST_NEW (cfg, ins, OP_MOVE);
1548                                         ins->dreg = mono_alloc_ireg (cfg);
1549                                         ins->sreg1 = in->dreg;
1550                                         MONO_ADD_INS (cfg->cbb, ins);
1551                                         mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1552 #else
1553                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1554                                         creg = mono_alloc_ireg (cfg);
1555                                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1556                                         mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1557 #endif
1558                                 } else {
1559 #ifdef MONO_ARCH_SOFT_FLOAT
1560                                         MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1561                                         ins->dreg = mono_alloc_ireg (cfg);
1562                                         ins->sreg1 = in->dreg;
1563                                         MONO_ADD_INS (cfg->cbb, ins);
1564                                         mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1565
1566                                         MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1567                                         ins->dreg = mono_alloc_ireg (cfg);
1568                                         ins->sreg1 = in->dreg;
1569                                         MONO_ADD_INS (cfg->cbb, ins);
1570                                         mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1571 #else
1572                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1573                                         creg = mono_alloc_ireg (cfg);
1574                                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1575                                         mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1576                                         creg = mono_alloc_ireg (cfg);
1577                                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1578                                         mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1579 #endif
1580                                 }
1581                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
1582                         } else {
1583                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1584                                 ins->dreg = mono_alloc_ireg (cfg);
1585                                 ins->sreg1 = in->dreg;
1586                                 MONO_ADD_INS (cfg->cbb, ins);
1587
1588                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1589                         }
1590                         break;
1591                 case RegTypeStructByAddr:
1592                         NOT_IMPLEMENTED;
1593 #if 0
1594                         /* FIXME: where si the data allocated? */
1595                         arg->backend.reg3 = ainfo->reg;
1596                         call->used_iregs |= 1 << ainfo->reg;
1597                         g_assert_not_reached ();
1598 #endif
1599                         break;
1600                 case RegTypeStructByVal:
1601                         MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1602                         ins->opcode = OP_OUTARG_VT;
1603                         ins->sreg1 = in->dreg;
1604                         ins->klass = in->klass;
1605                         ins->inst_p0 = call;
1606                         ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1607                         memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1608                         MONO_ADD_INS (cfg->cbb, ins);
1609                         break;
1610                 case RegTypeBase:
1611                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1612                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1613                         } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1614                                 if (t->type == MONO_TYPE_R8) {
1615                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1616                                 } else {
1617 #ifdef MONO_ARCH_SOFT_FLOAT
1618                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1619 #else
1620                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1621 #endif
1622                                 }
1623                         } else {
1624                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1625                         }
1626                         break;
1627                 case RegTypeBaseGen:
1628                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1629                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1630                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1631                                 ins->dreg = mono_alloc_ireg (cfg);
1632                                 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1633                                 MONO_ADD_INS (cfg->cbb, ins);
1634                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1635                         } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1636                                 int creg;
1637
1638                                 /* This should work for soft-float as well */
1639
1640                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1641                                 creg = mono_alloc_ireg (cfg);
1642                                 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1643                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1644                                 creg = mono_alloc_ireg (cfg);
1645                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1646                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1647                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
1648                         } else {
1649                                 g_assert_not_reached ();
1650                         }
1651                         break;
1652                 case RegTypeFP: {
1653                         /* FIXME: */
1654                         NOT_IMPLEMENTED;
1655 #if 0
1656                         arg->backend.reg3 = ainfo->reg;
1657                         /* FP args are passed in int regs */
1658                         call->used_iregs |= 1 << ainfo->reg;
1659                         if (ainfo->size == 8) {
1660                                 arg->opcode = OP_OUTARG_R8;
1661                                 call->used_iregs |= 1 << (ainfo->reg + 1);
1662                         } else {
1663                                 arg->opcode = OP_OUTARG_R4;
1664                         }
1665 #endif
1666                         cfg->flags |= MONO_CFG_HAS_FPOUT;
1667                         break;
1668                 }
1669                 default:
1670                         g_assert_not_reached ();
1671                 }
1672         }
1673
1674         /* Handle the case where there are no implicit arguments */
1675         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1676                 emit_sig_cookie (cfg, call, cinfo);
1677
1678         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1679                 MonoInst *vtarg;
1680
1681                 if (cinfo->ret.storage == RegTypeStructByVal) {
1682                         /* The JIT will transform this into a normal call */
1683                         call->vret_in_reg = TRUE;
1684                 } else {
1685                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1686                         vtarg->sreg1 = call->vret_var->dreg;
1687                         vtarg->dreg = mono_alloc_preg (cfg);
1688                         MONO_ADD_INS (cfg->cbb, vtarg);
1689
1690                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1691                 }
1692         }
1693
1694         call->stack_usage = cinfo->stack_usage;
1695
1696         g_free (cinfo);
1697 }
1698
1699 void
1700 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1701 {
1702         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1703         ArgInfo *ainfo = ins->inst_p1;
1704         int ovf_size = ainfo->vtsize;
1705         int doffset = ainfo->offset;
1706         int i, soffset, dreg;
1707
1708         soffset = 0;
1709         for (i = 0; i < ainfo->size; ++i) {
1710                 dreg = mono_alloc_ireg (cfg);
1711                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1712                 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
1713                 soffset += sizeof (gpointer);
1714         }
1715         //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
1716         if (ovf_size != 0)
1717                 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, ovf_size * sizeof (gpointer), 0);
1718 }
1719
1720 void
1721 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1722 {
1723         MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1724
1725         if (!ret->byref) {
1726                 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1727                         MonoInst *ins;
1728
1729                         if (COMPILE_LLVM (cfg)) {
1730                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1731                         } else {
1732                                 MONO_INST_NEW (cfg, ins, OP_SETLRET);
1733                                 ins->sreg1 = val->dreg + 1;
1734                                 ins->sreg2 = val->dreg + 2;
1735                                 MONO_ADD_INS (cfg->cbb, ins);
1736                         }
1737                         return;
1738                 }
1739 #ifdef MONO_ARCH_SOFT_FLOAT
1740                 if (ret->type == MONO_TYPE_R8) {
1741                         MonoInst *ins;
1742
1743                         MONO_INST_NEW (cfg, ins, OP_SETFRET);
1744                         ins->dreg = cfg->ret->dreg;
1745                         ins->sreg1 = val->dreg;
1746                         MONO_ADD_INS (cfg->cbb, ins);
1747                         return;
1748                 }
1749                 if (ret->type == MONO_TYPE_R4) {
1750                         /* Already converted to an int in method_to_ir () */
1751                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1752                         return;
1753                 }
1754 #elif defined(ARM_FPU_VFP)
1755                 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
1756                         MonoInst *ins;
1757
1758                         MONO_INST_NEW (cfg, ins, OP_SETFRET);
1759                         ins->dreg = cfg->ret->dreg;
1760                         ins->sreg1 = val->dreg;
1761                         MONO_ADD_INS (cfg->cbb, ins);
1762                         return;
1763                 }
1764 #else
1765                 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
1766                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1767                         return;
1768                 }
1769 #endif
1770         }
1771
1772         /* FIXME: */
1773         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1774 }
1775
1776 #endif /* #ifndef DISABLE_JIT */
1777
1778 gboolean
1779 mono_arch_is_inst_imm (gint64 imm)
1780 {
1781         return TRUE;
1782 }
1783
1784 #define DYN_CALL_STACK_ARGS 6
1785
1786 typedef struct {
1787         MonoMethodSignature *sig;
1788         CallInfo *cinfo;
1789 } ArchDynCallInfo;
1790
1791 typedef struct {
1792         mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
1793         mgreg_t res, res2;
1794         guint8 *ret;
1795 } DynCallArgs;
1796
1797 static gboolean
1798 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
1799 {
1800         int i;
1801
1802         if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
1803                 return FALSE;
1804
1805         switch (cinfo->ret.storage) {
1806         case RegTypeNone:
1807         case RegTypeGeneral:
1808         case RegTypeIRegPair:
1809         case RegTypeStructByAddr:
1810                 break;
1811         case RegTypeFP:
1812 #ifdef ARM_FPU_FPA
1813                 return FALSE;
1814 #elif defined(ARM_FPU_VFP)
1815                 break;
1816 #else
1817                 return FALSE;
1818 #endif
1819         default:
1820                 return FALSE;
1821         }
1822
1823         for (i = 0; i < cinfo->nargs; ++i) {
1824                 switch (cinfo->args [i].storage) {
1825                 case RegTypeGeneral:
1826                         break;
1827                 case RegTypeIRegPair:
1828                         break;
1829                 case RegTypeBase:
1830                         if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
1831                                 return FALSE;
1832                         break;
1833                 case RegTypeStructByVal:
1834                         if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
1835                                 return FALSE;
1836                         break;
1837                 default:
1838                         return FALSE;
1839                 }
1840         }
1841
1842         // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
1843         for (i = 0; i < sig->param_count; ++i) {
1844                 MonoType *t = sig->params [i];
1845
1846                 if (t->byref)
1847                         continue;
1848
1849                 switch (t->type) {
1850                 case MONO_TYPE_R4:
1851                 case MONO_TYPE_R8:
1852 #ifdef MONO_ARCH_SOFT_FLOAT
1853                         return FALSE;
1854 #else
1855                         break;
1856 #endif
1857                         /*
1858                 case MONO_TYPE_I8:
1859                 case MONO_TYPE_U8:
1860                         return FALSE;
1861                         */
1862                 default:
1863                         break;
1864                 }
1865         }
1866
1867         return TRUE;
1868 }
1869
1870 MonoDynCallInfo*
1871 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
1872 {
1873         ArchDynCallInfo *info;
1874         CallInfo *cinfo;
1875
1876         cinfo = get_call_info (NULL, NULL, sig);
1877
1878         if (!dyn_call_supported (cinfo, sig)) {
1879                 g_free (cinfo);
1880                 return NULL;
1881         }
1882
1883         info = g_new0 (ArchDynCallInfo, 1);
1884         // FIXME: Preprocess the info to speed up start_dyn_call ()
1885         info->sig = sig;
1886         info->cinfo = cinfo;
1887
1888         return (MonoDynCallInfo*)info;
1889 }
1890
1891 void
1892 mono_arch_dyn_call_free (MonoDynCallInfo *info)
1893 {
1894         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1895
1896         g_free (ainfo->cinfo);
1897         g_free (ainfo);
1898 }
1899
1900 void
1901 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
1902 {
1903         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
1904         DynCallArgs *p = (DynCallArgs*)buf;
1905         int arg_index, greg, i, j;
1906         MonoMethodSignature *sig = dinfo->sig;
1907
1908         g_assert (buf_len >= sizeof (DynCallArgs));
1909
1910         p->res = 0;
1911         p->ret = ret;
1912
1913         arg_index = 0;
1914         greg = 0;
1915
1916         if (dinfo->cinfo->vtype_retaddr)
1917                 p->regs [greg ++] = (mgreg_t)ret;
1918
1919         if (sig->hasthis)
1920                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
1921
1922         for (i = 0; i < sig->param_count; i++) {
1923                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
1924                 gpointer *arg = args [arg_index ++];
1925                 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
1926                 int slot = -1;
1927
1928                 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
1929                         slot = ainfo->reg;
1930                 else if (ainfo->storage == RegTypeBase)
1931                         slot = PARAM_REGS + (ainfo->offset / 4);
1932                 else
1933                         g_assert_not_reached ();
1934
1935                 if (t->byref) {
1936                         p->regs [slot] = (mgreg_t)*arg;
1937                         continue;
1938                 }
1939
1940                 switch (t->type) {
1941                 case MONO_TYPE_STRING:
1942                 case MONO_TYPE_CLASS:
1943                 case MONO_TYPE_ARRAY:
1944                 case MONO_TYPE_SZARRAY:
1945                 case MONO_TYPE_OBJECT:
1946                 case MONO_TYPE_PTR:
1947                 case MONO_TYPE_I:
1948                 case MONO_TYPE_U:
1949                         p->regs [slot] = (mgreg_t)*arg;
1950                         break;
1951                 case MONO_TYPE_BOOLEAN:
1952                 case MONO_TYPE_U1:
1953                         p->regs [slot] = *(guint8*)arg;
1954                         break;
1955                 case MONO_TYPE_I1:
1956                         p->regs [slot] = *(gint8*)arg;
1957                         break;
1958                 case MONO_TYPE_I2:
1959                         p->regs [slot] = *(gint16*)arg;
1960                         break;
1961                 case MONO_TYPE_U2:
1962                 case MONO_TYPE_CHAR:
1963                         p->regs [slot] = *(guint16*)arg;
1964                         break;
1965                 case MONO_TYPE_I4:
1966                         p->regs [slot] = *(gint32*)arg;
1967                         break;
1968                 case MONO_TYPE_U4:
1969                         p->regs [slot] = *(guint32*)arg;
1970                         break;
1971                 case MONO_TYPE_I8:
1972                 case MONO_TYPE_U8:
1973                         p->regs [slot ++] = (mgreg_t)arg [0];
1974                         p->regs [slot] = (mgreg_t)arg [1];
1975                         break;
1976                 case MONO_TYPE_R4:
1977                         p->regs [slot] = *(mgreg_t*)arg;
1978                         break;
1979                 case MONO_TYPE_R8:
1980                         p->regs [slot ++] = (mgreg_t)arg [0];
1981                         p->regs [slot] = (mgreg_t)arg [1];
1982                         break;
1983                 case MONO_TYPE_GENERICINST:
1984                         if (MONO_TYPE_IS_REFERENCE (t)) {
1985                                 p->regs [slot] = (mgreg_t)*arg;
1986                                 break;
1987                         } else {
1988                                 /* Fall though */
1989                         }
1990                 case MONO_TYPE_VALUETYPE:
1991                         g_assert (ainfo->storage == RegTypeStructByVal);
1992
1993                         if (ainfo->size == 0)
1994                                 slot = PARAM_REGS + (ainfo->offset / 4);
1995                         else
1996                                 slot = ainfo->reg;
1997
1998                         for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
1999                                 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2000                         break;
2001                 default:
2002                         g_assert_not_reached ();
2003                 }
2004         }
2005 }
2006
2007 void
2008 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2009 {
2010         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2011         MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2012         guint8 *ret = ((DynCallArgs*)buf)->ret;
2013         mgreg_t res = ((DynCallArgs*)buf)->res;
2014         mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2015
2016         switch (mono_type_get_underlying_type (sig->ret)->type) {
2017         case MONO_TYPE_VOID:
2018                 *(gpointer*)ret = NULL;
2019                 break;
2020         case MONO_TYPE_STRING:
2021         case MONO_TYPE_CLASS:
2022         case MONO_TYPE_ARRAY:
2023         case MONO_TYPE_SZARRAY:
2024         case MONO_TYPE_OBJECT:
2025         case MONO_TYPE_I:
2026         case MONO_TYPE_U:
2027         case MONO_TYPE_PTR:
2028                 *(gpointer*)ret = (gpointer)res;
2029                 break;
2030         case MONO_TYPE_I1:
2031                 *(gint8*)ret = res;
2032                 break;
2033         case MONO_TYPE_U1:
2034         case MONO_TYPE_BOOLEAN:
2035                 *(guint8*)ret = res;
2036                 break;
2037         case MONO_TYPE_I2:
2038                 *(gint16*)ret = res;
2039                 break;
2040         case MONO_TYPE_U2:
2041         case MONO_TYPE_CHAR:
2042                 *(guint16*)ret = res;
2043                 break;
2044         case MONO_TYPE_I4:
2045                 *(gint32*)ret = res;
2046                 break;
2047         case MONO_TYPE_U4:
2048                 *(guint32*)ret = res;
2049                 break;
2050         case MONO_TYPE_I8:
2051         case MONO_TYPE_U8:
2052                 /* This handles endianness as well */
2053                 ((gint32*)ret) [0] = res;
2054                 ((gint32*)ret) [1] = res2;
2055                 break;
2056         case MONO_TYPE_GENERICINST:
2057                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2058                         *(gpointer*)ret = (gpointer)res;
2059                         break;
2060                 } else {
2061                         /* Fall though */
2062                 }
2063         case MONO_TYPE_VALUETYPE:
2064                 g_assert (ainfo->cinfo->vtype_retaddr);
2065                 /* Nothing to do */
2066                 break;
2067 #if defined(ARM_FPU_VFP)
2068         case MONO_TYPE_R4:
2069                 *(float*)ret = *(float*)&res;
2070                 break;
2071         case MONO_TYPE_R8: {
2072                 mgreg_t regs [2];
2073
2074                 regs [0] = res;
2075                 regs [1] = res2;
2076
2077                 *(double*)ret = *(double*)&regs;
2078                 break;
2079         }
2080 #endif
2081         default:
2082                 g_assert_not_reached ();
2083         }
2084 }
2085
2086 #ifndef DISABLE_JIT
2087
2088 /*
2089  * Allow tracing to work with this interface (with an optional argument)
2090  */
2091
2092 void*
2093 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2094 {
2095         guchar *code = p;
2096
2097         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2098         ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2099         code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2100         code = emit_call_reg (code, ARMREG_R2);
2101         return code;
2102 }
2103
2104 enum {
2105         SAVE_NONE,
2106         SAVE_STRUCT,
2107         SAVE_ONE,
2108         SAVE_TWO,
2109         SAVE_FP
2110 };
2111
2112 void*
2113 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2114 {
2115         guchar *code = p;
2116         int save_mode = SAVE_NONE;
2117         int offset;
2118         MonoMethod *method = cfg->method;
2119         int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2120         int save_offset = cfg->param_area;
2121         save_offset += 7;
2122         save_offset &= ~7;
2123
2124         offset = code - cfg->native_code;
2125         /* we need about 16 instructions */
2126         if (offset > (cfg->code_size - 16 * 4)) {
2127                 cfg->code_size *= 2;
2128                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2129                 code = cfg->native_code + offset;
2130         }
2131         switch (rtype) {
2132         case MONO_TYPE_VOID:
2133                 /* special case string .ctor icall */
2134                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2135                         save_mode = SAVE_ONE;
2136                 else
2137                         save_mode = SAVE_NONE;
2138                 break;
2139         case MONO_TYPE_I8:
2140         case MONO_TYPE_U8:
2141                 save_mode = SAVE_TWO;
2142                 break;
2143         case MONO_TYPE_R4:
2144         case MONO_TYPE_R8:
2145                 save_mode = SAVE_FP;
2146                 break;
2147         case MONO_TYPE_VALUETYPE:
2148                 save_mode = SAVE_STRUCT;
2149                 break;
2150         default:
2151                 save_mode = SAVE_ONE;
2152                 break;
2153         }
2154
2155         switch (save_mode) {
2156         case SAVE_TWO:
2157                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2158                 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2159                 if (enable_arguments) {
2160                         ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2161                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2162                 }
2163                 break;
2164         case SAVE_ONE:
2165                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2166                 if (enable_arguments) {
2167                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2168                 }
2169                 break;
2170         case SAVE_FP:
2171                 /* FIXME: what reg?  */
2172                 if (enable_arguments) {
2173                         /* FIXME: what reg?  */
2174                 }
2175                 break;
2176         case SAVE_STRUCT:
2177                 if (enable_arguments) {
2178                         /* FIXME: get the actual address  */
2179                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2180                 }
2181                 break;
2182         case SAVE_NONE:
2183         default:
2184                 break;
2185         }
2186
2187         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2188         code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2189         code = emit_call_reg (code, ARMREG_IP);
2190
2191         switch (save_mode) {
2192         case SAVE_TWO:
2193                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2194                 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2195                 break;
2196         case SAVE_ONE:
2197                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2198                 break;
2199         case SAVE_FP:
2200                 /* FIXME */
2201                 break;
2202         case SAVE_NONE:
2203         default:
2204                 break;
2205         }
2206
2207         return code;
2208 }
2209
2210 /*
2211  * The immediate field for cond branches is big enough for all reasonable methods
2212  */
2213 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2214 if (0 && ins->inst_true_bb->native_offset) { \
2215         ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2216 } else { \
2217         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2218         ARM_B_COND (code, (condcode), 0);       \
2219 }
2220
2221 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2222
2223 /* emit an exception if condition is fail
2224  *
2225  * We assign the extra code used to throw the implicit exceptions
2226  * to cfg->bb_exit as far as the big branch handling is concerned
2227  */
2228 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name)            \
2229         do {                                                        \
2230                 mono_add_patch_info (cfg, code - cfg->native_code,   \
2231                                     MONO_PATCH_INFO_EXC, exc_name);  \
2232                 ARM_BL_COND (code, (condcode), 0);      \
2233         } while (0);
2234
2235 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2236
2237 void
2238 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2239 {
2240 }
2241
2242 void
2243 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2244 {
2245         MonoInst *ins, *n, *last_ins = NULL;
2246
2247         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2248                 switch (ins->opcode) {
2249                 case OP_MUL_IMM:
2250                 case OP_IMUL_IMM:
2251                         /* Already done by an arch-independent pass */
2252                         break;
2253                 case OP_LOAD_MEMBASE:
2254                 case OP_LOADI4_MEMBASE:
2255                         /*
2256                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2257                          * OP_LOAD_MEMBASE offset(basereg), reg
2258                          */
2259                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2260                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2261                             ins->inst_basereg == last_ins->inst_destbasereg &&
2262                             ins->inst_offset == last_ins->inst_offset) {
2263                                 if (ins->dreg == last_ins->sreg1) {
2264                                         MONO_DELETE_INS (bb, ins);
2265                                         continue;
2266                                 } else {
2267                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2268                                         ins->opcode = OP_MOVE;
2269                                         ins->sreg1 = last_ins->sreg1;
2270                                 }
2271
2272                         /*
2273                          * Note: reg1 must be different from the basereg in the second load
2274                          * OP_LOAD_MEMBASE offset(basereg), reg1
2275                          * OP_LOAD_MEMBASE offset(basereg), reg2
2276                          * -->
2277                          * OP_LOAD_MEMBASE offset(basereg), reg1
2278                          * OP_MOVE reg1, reg2
2279                          */
2280                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2281                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
2282                               ins->inst_basereg != last_ins->dreg &&
2283                               ins->inst_basereg == last_ins->inst_basereg &&
2284                               ins->inst_offset == last_ins->inst_offset) {
2285
2286                                 if (ins->dreg == last_ins->dreg) {
2287                                         MONO_DELETE_INS (bb, ins);
2288                                         continue;
2289                                 } else {
2290                                         ins->opcode = OP_MOVE;
2291                                         ins->sreg1 = last_ins->dreg;
2292                                 }
2293
2294                                 //g_assert_not_reached ();
2295
2296 #if 0
2297                         /*
2298                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2299                          * OP_LOAD_MEMBASE offset(basereg), reg
2300                          * -->
2301                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2302                          * OP_ICONST reg, imm
2303                          */
2304                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2305                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2306                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2307                                    ins->inst_offset == last_ins->inst_offset) {
2308                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2309                                 ins->opcode = OP_ICONST;
2310                                 ins->inst_c0 = last_ins->inst_imm;
2311                                 g_assert_not_reached (); // check this rule
2312 #endif
2313                         }
2314                         break;
2315                 case OP_LOADU1_MEMBASE:
2316                 case OP_LOADI1_MEMBASE:
2317                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2318                                         ins->inst_basereg == last_ins->inst_destbasereg &&
2319                                         ins->inst_offset == last_ins->inst_offset) {
2320                                 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2321                                 ins->sreg1 = last_ins->sreg1;
2322                         }
2323                         break;
2324                 case OP_LOADU2_MEMBASE:
2325                 case OP_LOADI2_MEMBASE:
2326                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2327                                         ins->inst_basereg == last_ins->inst_destbasereg &&
2328                                         ins->inst_offset == last_ins->inst_offset) {
2329                                 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2330                                 ins->sreg1 = last_ins->sreg1;
2331                         }
2332                         break;
2333                 case OP_MOVE:
2334                         ins->opcode = OP_MOVE;
2335                         /*
2336                          * OP_MOVE reg, reg
2337                          */
2338                         if (ins->dreg == ins->sreg1) {
2339                                 MONO_DELETE_INS (bb, ins);
2340                                 continue;
2341                         }
2342                         /*
2343                          * OP_MOVE sreg, dreg
2344                          * OP_MOVE dreg, sreg
2345                          */
2346                         if (last_ins && last_ins->opcode == OP_MOVE &&
2347                             ins->sreg1 == last_ins->dreg &&
2348                             ins->dreg == last_ins->sreg1) {
2349                                 MONO_DELETE_INS (bb, ins);
2350                                 continue;
2351                         }
2352                         break;
2353                 }
2354                 last_ins = ins;
2355                 ins = ins->next;
2356         }
2357         bb->last_ins = last_ins;
2358 }
2359
2360 /*
2361  * the branch_cc_table should maintain the order of these
2362  * opcodes.
2363 case CEE_BEQ:
2364 case CEE_BGE:
2365 case CEE_BGT:
2366 case CEE_BLE:
2367 case CEE_BLT:
2368 case CEE_BNE_UN:
2369 case CEE_BGE_UN:
2370 case CEE_BGT_UN:
2371 case CEE_BLE_UN:
2372 case CEE_BLT_UN:
2373  */
2374 static const guchar
2375 branch_cc_table [] = {
2376         ARMCOND_EQ,
2377         ARMCOND_GE,
2378         ARMCOND_GT,
2379         ARMCOND_LE,
2380         ARMCOND_LT,
2381
2382         ARMCOND_NE,
2383         ARMCOND_HS,
2384         ARMCOND_HI,
2385         ARMCOND_LS,
2386         ARMCOND_LO
2387 };
2388
2389 #define NEW_INS(cfg,dest,op) do {       \
2390                 MONO_INST_NEW ((cfg), (dest), (op)); \
2391         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2392         } while (0)
2393
2394 static int
2395 map_to_reg_reg_op (int op)
2396 {
2397         switch (op) {
2398         case OP_ADD_IMM:
2399                 return OP_IADD;
2400         case OP_SUB_IMM:
2401                 return OP_ISUB;
2402         case OP_AND_IMM:
2403                 return OP_IAND;
2404         case OP_COMPARE_IMM:
2405                 return OP_COMPARE;
2406         case OP_ICOMPARE_IMM:
2407                 return OP_ICOMPARE;
2408         case OP_ADDCC_IMM:
2409                 return OP_ADDCC;
2410         case OP_ADC_IMM:
2411                 return OP_ADC;
2412         case OP_SUBCC_IMM:
2413                 return OP_SUBCC;
2414         case OP_SBB_IMM:
2415                 return OP_SBB;
2416         case OP_OR_IMM:
2417                 return OP_IOR;
2418         case OP_XOR_IMM:
2419                 return OP_IXOR;
2420         case OP_LOAD_MEMBASE:
2421                 return OP_LOAD_MEMINDEX;
2422         case OP_LOADI4_MEMBASE:
2423                 return OP_LOADI4_MEMINDEX;
2424         case OP_LOADU4_MEMBASE:
2425                 return OP_LOADU4_MEMINDEX;
2426         case OP_LOADU1_MEMBASE:
2427                 return OP_LOADU1_MEMINDEX;
2428         case OP_LOADI2_MEMBASE:
2429                 return OP_LOADI2_MEMINDEX;
2430         case OP_LOADU2_MEMBASE:
2431                 return OP_LOADU2_MEMINDEX;
2432         case OP_LOADI1_MEMBASE:
2433                 return OP_LOADI1_MEMINDEX;
2434         case OP_STOREI1_MEMBASE_REG:
2435                 return OP_STOREI1_MEMINDEX;
2436         case OP_STOREI2_MEMBASE_REG:
2437                 return OP_STOREI2_MEMINDEX;
2438         case OP_STOREI4_MEMBASE_REG:
2439                 return OP_STOREI4_MEMINDEX;
2440         case OP_STORE_MEMBASE_REG:
2441                 return OP_STORE_MEMINDEX;
2442         case OP_STORER4_MEMBASE_REG:
2443                 return OP_STORER4_MEMINDEX;
2444         case OP_STORER8_MEMBASE_REG:
2445                 return OP_STORER8_MEMINDEX;
2446         case OP_STORE_MEMBASE_IMM:
2447                 return OP_STORE_MEMBASE_REG;
2448         case OP_STOREI1_MEMBASE_IMM:
2449                 return OP_STOREI1_MEMBASE_REG;
2450         case OP_STOREI2_MEMBASE_IMM:
2451                 return OP_STOREI2_MEMBASE_REG;
2452         case OP_STOREI4_MEMBASE_IMM:
2453                 return OP_STOREI4_MEMBASE_REG;
2454         }
2455         g_assert_not_reached ();
2456 }
2457
2458 /*
2459  * Remove from the instruction list the instructions that can't be
2460  * represented with very simple instructions with no register
2461  * requirements.
2462  */
2463 void
2464 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2465 {
2466         MonoInst *ins, *temp, *last_ins = NULL;
2467         int rot_amount, imm8, low_imm;
2468
2469         MONO_BB_FOR_EACH_INS (bb, ins) {
2470 loop_start:
2471                 switch (ins->opcode) {
2472                 case OP_ADD_IMM:
2473                 case OP_SUB_IMM:
2474                 case OP_AND_IMM:
2475                 case OP_COMPARE_IMM:
2476                 case OP_ICOMPARE_IMM:
2477                 case OP_ADDCC_IMM:
2478                 case OP_ADC_IMM:
2479                 case OP_SUBCC_IMM:
2480                 case OP_SBB_IMM:
2481                 case OP_OR_IMM:
2482                 case OP_XOR_IMM:
2483                 case OP_IADD_IMM:
2484                 case OP_ISUB_IMM:
2485                 case OP_IAND_IMM:
2486                 case OP_IADC_IMM:
2487                 case OP_ISBB_IMM:
2488                 case OP_IOR_IMM:
2489                 case OP_IXOR_IMM:
2490                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2491                                 NEW_INS (cfg, temp, OP_ICONST);
2492                                 temp->inst_c0 = ins->inst_imm;
2493                                 temp->dreg = mono_alloc_ireg (cfg);
2494                                 ins->sreg2 = temp->dreg;
2495                                 ins->opcode = mono_op_imm_to_op (ins->opcode);
2496                         }
2497                         if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2498                                 goto loop_start;
2499                         else
2500                                 break;
2501                 case OP_MUL_IMM:
2502                 case OP_IMUL_IMM:
2503                         if (ins->inst_imm == 1) {
2504                                 ins->opcode = OP_MOVE;
2505                                 break;
2506                         }
2507                         if (ins->inst_imm == 0) {
2508                                 ins->opcode = OP_ICONST;
2509                                 ins->inst_c0 = 0;
2510                                 break;
2511                         }
2512                         imm8 = mono_is_power_of_two (ins->inst_imm);
2513                         if (imm8 > 0) {
2514                                 ins->opcode = OP_SHL_IMM;
2515                                 ins->inst_imm = imm8;
2516                                 break;
2517                         }
2518                         NEW_INS (cfg, temp, OP_ICONST);
2519                         temp->inst_c0 = ins->inst_imm;
2520                         temp->dreg = mono_alloc_ireg (cfg);
2521                         ins->sreg2 = temp->dreg;
2522                         ins->opcode = OP_IMUL;
2523                         break;
2524                 case OP_SBB:
2525                 case OP_ISBB:
2526                 case OP_SUBCC:
2527                 case OP_ISUBCC:
2528                         if (ins->next  && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2529                                 /* ARM sets the C flag to 1 if there was _no_ overflow */
2530                                 ins->next->opcode = OP_COND_EXC_NC;
2531                         break;
2532                 case OP_LOCALLOC_IMM:
2533                         NEW_INS (cfg, temp, OP_ICONST);
2534                         temp->inst_c0 = ins->inst_imm;
2535                         temp->dreg = mono_alloc_ireg (cfg);
2536                         ins->sreg1 = temp->dreg;
2537                         ins->opcode = OP_LOCALLOC;
2538                         break;
2539                 case OP_LOAD_MEMBASE:
2540                 case OP_LOADI4_MEMBASE:
2541                 case OP_LOADU4_MEMBASE:
2542                 case OP_LOADU1_MEMBASE:
2543                         /* we can do two things: load the immed in a register
2544                          * and use an indexed load, or see if the immed can be
2545                          * represented as an ad_imm + a load with a smaller offset
2546                          * that fits. We just do the first for now, optimize later.
2547                          */
2548                         if (arm_is_imm12 (ins->inst_offset))
2549                                 break;
2550                         NEW_INS (cfg, temp, OP_ICONST);
2551                         temp->inst_c0 = ins->inst_offset;
2552                         temp->dreg = mono_alloc_ireg (cfg);
2553                         ins->sreg2 = temp->dreg;
2554                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2555                         break;
2556                 case OP_LOADI2_MEMBASE:
2557                 case OP_LOADU2_MEMBASE:
2558                 case OP_LOADI1_MEMBASE:
2559                         if (arm_is_imm8 (ins->inst_offset))
2560                                 break;
2561                         NEW_INS (cfg, temp, OP_ICONST);
2562                         temp->inst_c0 = ins->inst_offset;
2563                         temp->dreg = mono_alloc_ireg (cfg);
2564                         ins->sreg2 = temp->dreg;
2565                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2566                         break;
2567                 case OP_LOADR4_MEMBASE:
2568                 case OP_LOADR8_MEMBASE:
2569                         if (arm_is_fpimm8 (ins->inst_offset))
2570                                 break;
2571                         low_imm = ins->inst_offset & 0x1ff;
2572                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2573                                 NEW_INS (cfg, temp, OP_ADD_IMM);
2574                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
2575                                 temp->sreg1 = ins->inst_basereg;
2576                                 temp->dreg = mono_alloc_ireg (cfg);
2577                                 ins->inst_basereg = temp->dreg;
2578                                 ins->inst_offset = low_imm;
2579                                 break;
2580                         }
2581                         /* VFP/FPA doesn't have indexed load instructions */
2582                         g_assert_not_reached ();
2583                         break;
2584                 case OP_STORE_MEMBASE_REG:
2585                 case OP_STOREI4_MEMBASE_REG:
2586                 case OP_STOREI1_MEMBASE_REG:
2587                         if (arm_is_imm12 (ins->inst_offset))
2588                                 break;
2589                         NEW_INS (cfg, temp, OP_ICONST);
2590                         temp->inst_c0 = ins->inst_offset;
2591                         temp->dreg = mono_alloc_ireg (cfg);
2592                         ins->sreg2 = temp->dreg;
2593                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2594                         break;
2595                 case OP_STOREI2_MEMBASE_REG:
2596                         if (arm_is_imm8 (ins->inst_offset))
2597                                 break;
2598                         NEW_INS (cfg, temp, OP_ICONST);
2599                         temp->inst_c0 = ins->inst_offset;
2600                         temp->dreg = mono_alloc_ireg (cfg);
2601                         ins->sreg2 = temp->dreg;
2602                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2603                         break;
2604                 case OP_STORER4_MEMBASE_REG:
2605                 case OP_STORER8_MEMBASE_REG:
2606                         if (arm_is_fpimm8 (ins->inst_offset))
2607                                 break;
2608                         low_imm = ins->inst_offset & 0x1ff;
2609                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2610                                 NEW_INS (cfg, temp, OP_ADD_IMM);
2611                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
2612                                 temp->sreg1 = ins->inst_destbasereg;
2613                                 temp->dreg = mono_alloc_ireg (cfg);
2614                                 ins->inst_destbasereg = temp->dreg;
2615                                 ins->inst_offset = low_imm;
2616                                 break;
2617                         }
2618                         /*g_print ("fail with: %d (%d, %d)\n", ins->inst_offset, ins->inst_offset & ~0x1ff, low_imm);*/
2619                         /* VFP/FPA doesn't have indexed store instructions */
2620                         g_assert_not_reached ();
2621                         break;
2622                 case OP_STORE_MEMBASE_IMM:
2623                 case OP_STOREI1_MEMBASE_IMM:
2624                 case OP_STOREI2_MEMBASE_IMM:
2625                 case OP_STOREI4_MEMBASE_IMM:
2626                         NEW_INS (cfg, temp, OP_ICONST);
2627                         temp->inst_c0 = ins->inst_imm;
2628                         temp->dreg = mono_alloc_ireg (cfg);
2629                         ins->sreg1 = temp->dreg;
2630                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2631                         last_ins = temp;
2632                         goto loop_start; /* make it handle the possibly big ins->inst_offset */
2633                 case OP_FCOMPARE: {
2634                         gboolean swap = FALSE;
2635                         int reg;
2636
2637                         if (!ins->next) {
2638                                 /* Optimized away */
2639                                 NULLIFY_INS (ins);
2640                                 break;
2641                         }
2642
2643                         /* Some fp compares require swapped operands */
2644                         switch (ins->next->opcode) {
2645                         case OP_FBGT:
2646                                 ins->next->opcode = OP_FBLT;
2647                                 swap = TRUE;
2648                                 break;
2649                         case OP_FBGT_UN:
2650                                 ins->next->opcode = OP_FBLT_UN;
2651                                 swap = TRUE;
2652                                 break;
2653                         case OP_FBLE:
2654                                 ins->next->opcode = OP_FBGE;
2655                                 swap = TRUE;
2656                                 break;
2657                         case OP_FBLE_UN:
2658                                 ins->next->opcode = OP_FBGE_UN;
2659                                 swap = TRUE;
2660                                 break;
2661                         default:
2662                                 break;
2663                         }
2664                         if (swap) {
2665                                 reg = ins->sreg1;
2666                                 ins->sreg1 = ins->sreg2;
2667                                 ins->sreg2 = reg;
2668                         }
2669                         break;
2670                 }
2671                 }
2672
2673                 last_ins = ins;
2674         }
2675         bb->last_ins = last_ins;
2676         bb->max_vreg = cfg->next_vreg;
2677 }
2678
2679 void
2680 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2681 {
2682         MonoInst *ins;
2683
2684         if (long_ins->opcode == OP_LNEG) {
2685                 ins = long_ins;
2686                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
2687                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
2688                 NULLIFY_INS (ins);
2689         }
2690 }
2691
2692 static guchar*
2693 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2694 {
2695         /* sreg is a float, dreg is an integer reg  */
2696 #ifdef ARM_FPU_FPA
2697         ARM_FIXZ (code, dreg, sreg);
2698 #elif defined(ARM_FPU_VFP)
2699         if (is_signed)
2700                 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
2701         else
2702                 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
2703         ARM_FMRS (code, dreg, ARM_VFP_F0);
2704 #endif
2705         if (!is_signed) {
2706                 if (size == 1)
2707                         ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
2708                 else if (size == 2) {
2709                         ARM_SHL_IMM (code, dreg, dreg, 16);
2710                         ARM_SHR_IMM (code, dreg, dreg, 16);
2711                 }
2712         } else {
2713                 if (size == 1) {
2714                         ARM_SHL_IMM (code, dreg, dreg, 24);
2715                         ARM_SAR_IMM (code, dreg, dreg, 24);
2716                 } else if (size == 2) {
2717                         ARM_SHL_IMM (code, dreg, dreg, 16);
2718                         ARM_SAR_IMM (code, dreg, dreg, 16);
2719                 }
2720         }
2721         return code;
2722 }
2723
2724 #endif /* #ifndef DISABLE_JIT */
2725
2726 typedef struct {
2727         guchar *code;
2728         const guchar *target;
2729         int absolute;
2730         int found;
2731 } PatchData;
2732
2733 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
2734
2735 static int
2736 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
2737         PatchData *pdata = (PatchData*)user_data;
2738         guchar *code = data;
2739         guint32 *thunks = data;
2740         guint32 *endthunks = (guint32*)(code + bsize);
2741         int count = 0;
2742         int difflow, diffhigh;
2743
2744         /* always ensure a call from pdata->code can reach to the thunks without further thunks */
2745         difflow = (char*)pdata->code - (char*)thunks;
2746         diffhigh = (char*)pdata->code - (char*)endthunks;
2747         if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
2748                 return 0;
2749
2750         /*
2751          * The thunk is composed of 3 words:
2752          * load constant from thunks [2] into ARM_IP
2753          * bx to ARM_IP
2754          * address constant
2755          * Note that the LR register is already setup
2756          */
2757         //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
2758         if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
2759                 while (thunks < endthunks) {
2760                         //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
2761                         if (thunks [2] == (guint32)pdata->target) {
2762                                 arm_patch (pdata->code, (guchar*)thunks);
2763                                 mono_arch_flush_icache (pdata->code, 4);
2764                                 pdata->found = 1;
2765                                 return 1;
2766                         } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
2767                                 /* found a free slot instead: emit thunk */
2768                                 /* ARMREG_IP is fine to use since this can't be an IMT call
2769                                  * which is indirect
2770                                  */
2771                                 code = (guchar*)thunks;
2772                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2773                                 if (thumb_supported)
2774                                         ARM_BX (code, ARMREG_IP);
2775                                 else
2776                                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2777                                 thunks [2] = (guint32)pdata->target;
2778                                 mono_arch_flush_icache ((guchar*)thunks, 12);
2779
2780                                 arm_patch (pdata->code, (guchar*)thunks);
2781                                 mono_arch_flush_icache (pdata->code, 4);
2782                                 pdata->found = 1;
2783                                 return 1;
2784                         }
2785                         /* skip 12 bytes, the size of the thunk */
2786                         thunks += 3;
2787                         count++;
2788                 }
2789                 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
2790         }
2791         return 0;
2792 }
2793
2794 static void
2795 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target)
2796 {
2797         PatchData pdata;
2798
2799         if (!domain)
2800                 domain = mono_domain_get ();
2801
2802         pdata.code = code;
2803         pdata.target = target;
2804         pdata.absolute = absolute;
2805         pdata.found = 0;
2806
2807         mono_domain_lock (domain);
2808         mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
2809
2810         if (!pdata.found) {
2811                 /* this uses the first available slot */
2812                 pdata.found = 2;
2813                 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
2814         }
2815         mono_domain_unlock (domain);
2816
2817         if (pdata.found != 1)
2818                 g_print ("thunk failed for %p from %p\n", target, code);
2819         g_assert (pdata.found == 1);
2820 }
2821
2822 static void
2823 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target)
2824 {
2825         guint32 *code32 = (void*)code;
2826         guint32 ins = *code32;
2827         guint32 prim = (ins >> 25) & 7;
2828         guint32 tval = GPOINTER_TO_UINT (target);
2829
2830         //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
2831         if (prim == 5) { /* 101b */
2832                 /* the diff starts 8 bytes from the branch opcode */
2833                 gint diff = target - code - 8;
2834                 gint tbits;
2835                 gint tmask = 0xffffffff;
2836                 if (tval & 1) { /* entering thumb mode */
2837                         diff = target - 1 - code - 8;
2838                         g_assert (thumb_supported);
2839                         tbits = 0xf << 28; /* bl->blx bit pattern */
2840                         g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
2841                         /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
2842                         if (diff & 2) {
2843                                 tbits |= 1 << 24;
2844                         }
2845                         tmask = ~(1 << 24); /* clear the link bit */
2846                         /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
2847                 } else {
2848                         tbits = 0;
2849                 }
2850                 if (diff >= 0) {
2851                         if (diff <= 33554431) {
2852                                 diff >>= 2;
2853                                 ins = (ins & 0xff000000) | diff;
2854                                 ins &= tmask;
2855                                 *code32 = ins | tbits;
2856                                 return;
2857                         }
2858                 } else {
2859                         /* diff between 0 and -33554432 */
2860                         if (diff >= -33554432) {
2861                                 diff >>= 2;
2862                                 ins = (ins & 0xff000000) | (diff & ~0xff000000);
2863                                 ins &= tmask;
2864                                 *code32 = ins | tbits;
2865                                 return;
2866                         }
2867                 }
2868
2869                 handle_thunk (domain, TRUE, code, target);
2870                 return;
2871         }
2872
2873         /*
2874          * The alternative call sequences looks like this:
2875          *
2876          *      ldr ip, [pc] // loads the address constant
2877          *      b 1f         // jumps around the constant
2878          *      address constant embedded in the code
2879          *   1f:
2880          *      mov lr, pc
2881          *      mov pc, ip
2882          *
2883          * There are two cases for patching:
2884          * a) at the end of method emission: in this case code points to the start
2885          *    of the call sequence
2886          * b) during runtime patching of the call site: in this case code points
2887          *    to the mov pc, ip instruction
2888          *
2889          * We have to handle also the thunk jump code sequence:
2890          *
2891          *      ldr ip, [pc]
2892          *      mov pc, ip
2893          *      address constant // execution never reaches here
2894          */
2895         if ((ins & 0x0ffffff0) == 0x12fff10) {
2896                 /* Branch and exchange: the address is constructed in a reg
2897                  * We can patch BX when the code sequence is the following:
2898                  *  ldr     ip, [pc, #0]    ; 0x8
2899                  *  b       0xc
2900                  *  .word code_ptr
2901                  *  mov     lr, pc
2902                  *  bx      ips
2903                  * */
2904                 guint32 ccode [4];
2905                 guint8 *emit = (guint8*)ccode;
2906                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
2907                 ARM_B (emit, 0);
2908                 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
2909                 ARM_BX (emit, ARMREG_IP);
2910
2911                 /*patching from magic trampoline*/
2912                 if (ins == ccode [3]) {
2913                         g_assert (code32 [-4] == ccode [0]);
2914                         g_assert (code32 [-3] == ccode [1]);
2915                         g_assert (code32 [-1] == ccode [2]);
2916                         code32 [-2] = (guint32)target;
2917                         return;
2918                 }
2919                 /*patching from JIT*/
2920                 if (ins == ccode [0]) {
2921                         g_assert (code32 [1] == ccode [1]);
2922                         g_assert (code32 [3] == ccode [2]);
2923                         g_assert (code32 [4] == ccode [3]);
2924                         code32 [2] = (guint32)target;
2925                         return;
2926                 }
2927                 g_assert_not_reached ();
2928         } else if ((ins & 0x0ffffff0) == 0x12fff30) {
2929                 /*
2930                  * ldr ip, [pc, #0]
2931                  * b 0xc
2932                  * .word code_ptr
2933                  * blx ip
2934                  */
2935                 guint32 ccode [4];
2936                 guint8 *emit = (guint8*)ccode;
2937                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
2938                 ARM_B (emit, 0);
2939                 ARM_BLX_REG (emit, ARMREG_IP);
2940
2941                 g_assert (code32 [-3] == ccode [0]);
2942                 g_assert (code32 [-2] == ccode [1]);
2943                 g_assert (code32 [0] == ccode [2]);
2944
2945                 code32 [-1] = (guint32)target;
2946         } else {
2947                 guint32 ccode [4];
2948                 guint32 *tmp = ccode;
2949                 guint8 *emit = (guint8*)tmp;
2950                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
2951                 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
2952                 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
2953                 ARM_BX (emit, ARMREG_IP);
2954                 if (ins == ccode [2]) {
2955                         g_assert_not_reached (); // should be -2 ...
2956                         code32 [-1] = (guint32)target;
2957                         return;
2958                 }
2959                 if (ins == ccode [0]) {
2960                         /* handles both thunk jump code and the far call sequence */
2961                         code32 [2] = (guint32)target;
2962                         return;
2963                 }
2964                 g_assert_not_reached ();
2965         }
2966 //      g_print ("patched with 0x%08x\n", ins);
2967 }
2968
2969 void
2970 arm_patch (guchar *code, const guchar *target)
2971 {
2972         arm_patch_general (NULL, code, target);
2973 }
2974
2975 /*
2976  * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
2977  * (with the rotation amount in *rot_amount. rot_amount is already adjusted
2978  * to be used with the emit macros.
2979  * Return -1 otherwise.
2980  */
2981 int
2982 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
2983 {
2984         guint32 res, i;
2985         for (i = 0; i < 31; i+= 2) {
2986                 res = (val << (32 - i)) | (val >> i);
2987                 if (res & ~0xff)
2988                         continue;
2989                 *rot_amount = i? 32 - i: 0;
2990                 return res;
2991         }
2992         return -1;
2993 }
2994
2995 /*
2996  * Emits in code a sequence of instructions that load the value 'val'
2997  * into the dreg register. Uses at most 4 instructions.
2998  */
2999 guint8*
3000 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3001 {
3002         int imm8, rot_amount;
3003 #if 0
3004         ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3005         /* skip the constant pool */
3006         ARM_B (code, 0);
3007         *(int*)code = val;
3008         code += 4;
3009         return code;
3010 #endif
3011         if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3012                 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3013         } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3014                 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3015         } else {
3016                 if (v7_supported) {
3017                         ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3018                         if (val >> 16)
3019                                 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3020                         return code;
3021                 }
3022                 if (val & 0xFF) {
3023                         ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3024                         if (val & 0xFF00) {
3025                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3026                         }
3027                         if (val & 0xFF0000) {
3028                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3029                         }
3030                         if (val & 0xFF000000) {
3031                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3032                         }
3033                 } else if (val & 0xFF00) {
3034                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3035                         if (val & 0xFF0000) {
3036                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3037                         }
3038                         if (val & 0xFF000000) {
3039                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3040                         }
3041                 } else if (val & 0xFF0000) {
3042                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3043                         if (val & 0xFF000000) {
3044                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3045                         }
3046                 }
3047                 //g_assert_not_reached ();
3048         }
3049         return code;
3050 }
3051
3052 gboolean
3053 mono_arm_thumb_supported (void)
3054 {
3055         return thumb_supported;
3056 }
3057
3058 #ifndef DISABLE_JIT
3059
3060 /*
3061  * emit_load_volatile_arguments:
3062  *
3063  *  Load volatile arguments from the stack to the original input registers.
3064  * Required before a tail call.
3065  */
3066 static guint8*
3067 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3068 {
3069         MonoMethod *method = cfg->method;
3070         MonoMethodSignature *sig;
3071         MonoInst *inst;
3072         CallInfo *cinfo;
3073         guint32 i, pos;
3074
3075         /* FIXME: Generate intermediate code instead */
3076
3077         sig = mono_method_signature (method);
3078
3079         /* This is the opposite of the code in emit_prolog */
3080
3081         pos = 0;
3082
3083         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3084
3085         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
3086                 ArgInfo *ainfo = &cinfo->ret;
3087                 inst = cfg->vret_addr;
3088                 g_assert (arm_is_imm12 (inst->inst_offset));
3089                 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3090         }
3091         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3092                 ArgInfo *ainfo = cinfo->args + i;
3093                 inst = cfg->args [pos];
3094
3095                 if (cfg->verbose_level > 2)
3096                         g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3097                 if (inst->opcode == OP_REGVAR) {
3098                         if (ainfo->storage == RegTypeGeneral)
3099                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3100                         else if (ainfo->storage == RegTypeFP) {
3101                                 g_assert_not_reached ();
3102                         } else if (ainfo->storage == RegTypeBase) {
3103                                 // FIXME:
3104                                 NOT_IMPLEMENTED;
3105                                 /*
3106                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3107                                         ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3108                                 } else {
3109                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3110                                         ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3111                                 }
3112                                 */
3113                         } else
3114                                 g_assert_not_reached ();
3115                 } else {
3116                         if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3117                                 switch (ainfo->size) {
3118                                 case 1:
3119                                 case 2:
3120                                         // FIXME:
3121                                         NOT_IMPLEMENTED;
3122                                         break;
3123                                 case 8:
3124                                         g_assert (arm_is_imm12 (inst->inst_offset));
3125                                         ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3126                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
3127                                         ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3128                                         break;
3129                                 default:
3130                                         if (arm_is_imm12 (inst->inst_offset)) {
3131                                                 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3132                                         } else {
3133                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3134                                                 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3135                                         }
3136                                         break;
3137                                 }
3138                         } else if (ainfo->storage == RegTypeBaseGen) {
3139                                 // FIXME:
3140                                 NOT_IMPLEMENTED;
3141                         } else if (ainfo->storage == RegTypeBase) {
3142                                 /* Nothing to do */
3143                         } else if (ainfo->storage == RegTypeFP) {
3144                                 g_assert_not_reached ();
3145                         } else if (ainfo->storage == RegTypeStructByVal) {
3146                                 int doffset = inst->inst_offset;
3147                                 int soffset = 0;
3148                                 int cur_reg;
3149                                 int size = 0;
3150                                 if (mono_class_from_mono_type (inst->inst_vtype))
3151                                         size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3152                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3153                                         if (arm_is_imm12 (doffset)) {
3154                                                 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3155                                         } else {
3156                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3157                                                 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3158                                         }
3159                                         soffset += sizeof (gpointer);
3160                                         doffset += sizeof (gpointer);
3161                                 }
3162                                 if (ainfo->vtsize)
3163                                         // FIXME:
3164                                         NOT_IMPLEMENTED;
3165                         } else if (ainfo->storage == RegTypeStructByAddr) {
3166                         } else {
3167                                 // FIXME:
3168                                 NOT_IMPLEMENTED;
3169                         }
3170                 }
3171                 pos ++;
3172         }
3173
3174         g_free (cinfo);
3175
3176         return code;
3177 }
3178
3179 void
3180 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3181 {
3182         MonoInst *ins;
3183         MonoCallInst *call;
3184         guint offset;
3185         guint8 *code = cfg->native_code + cfg->code_len;
3186         MonoInst *last_ins = NULL;
3187         guint last_offset = 0;
3188         int max_len, cpos;
3189         int imm8, rot_amount;
3190
3191         /* we don't align basic blocks of loops on arm */
3192
3193         if (cfg->verbose_level > 2)
3194                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3195
3196         cpos = bb->max_offset;
3197
3198         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3199                 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3200                 //g_assert (!mono_compile_aot);
3201                 //cpos += 6;
3202                 //if (bb->cil_code)
3203                 //      cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3204                 /* this is not thread save, but good enough */
3205                 /* fixme: howto handle overflows? */
3206                 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3207         }
3208
3209     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3210                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3211                                                          (gpointer)"mono_break");
3212                 code = emit_call_seq (cfg, code);
3213         }
3214
3215         MONO_BB_FOR_EACH_INS (bb, ins) {
3216                 offset = code - cfg->native_code;
3217
3218                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3219
3220                 if (offset > (cfg->code_size - max_len - 16)) {
3221                         cfg->code_size *= 2;
3222                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3223                         code = cfg->native_code + offset;
3224                 }
3225         //      if (ins->cil_code)
3226         //              g_print ("cil code\n");
3227                 mono_debug_record_line_number (cfg, ins, offset);
3228
3229                 switch (ins->opcode) {
3230                 case OP_MEMORY_BARRIER:
3231                         break;
3232                 case OP_TLS_GET:
3233 #ifdef HAVE_AEABI_READ_TP
3234                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3235                                                                  (gpointer)"__aeabi_read_tp");
3236                         code = emit_call_seq (cfg, code);
3237
3238                         ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3239 #else
3240                         g_assert_not_reached ();
3241 #endif
3242                         break;
3243                 /*case OP_BIGMUL:
3244                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3245                         ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3246                         break;
3247                 case OP_BIGMUL_UN:
3248                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3249                         ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3250                         break;*/
3251                 case OP_STOREI1_MEMBASE_IMM:
3252                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3253                         g_assert (arm_is_imm12 (ins->inst_offset));
3254                         ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3255                         break;
3256                 case OP_STOREI2_MEMBASE_IMM:
3257                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3258                         g_assert (arm_is_imm8 (ins->inst_offset));
3259                         ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3260                         break;
3261                 case OP_STORE_MEMBASE_IMM:
3262                 case OP_STOREI4_MEMBASE_IMM:
3263                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3264                         g_assert (arm_is_imm12 (ins->inst_offset));
3265                         ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3266                         break;
3267                 case OP_STOREI1_MEMBASE_REG:
3268                         g_assert (arm_is_imm12 (ins->inst_offset));
3269                         ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3270                         break;
3271                 case OP_STOREI2_MEMBASE_REG:
3272                         g_assert (arm_is_imm8 (ins->inst_offset));
3273                         ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3274                         break;
3275                 case OP_STORE_MEMBASE_REG:
3276                 case OP_STOREI4_MEMBASE_REG:
3277                         /* this case is special, since it happens for spill code after lowering has been called */
3278                         if (arm_is_imm12 (ins->inst_offset)) {
3279                                 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3280                         } else {
3281                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3282                                 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3283                         }
3284                         break;
3285                 case OP_STOREI1_MEMINDEX:
3286                         ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3287                         break;
3288                 case OP_STOREI2_MEMINDEX:
3289                         ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3290                         break;
3291                 case OP_STORE_MEMINDEX:
3292                 case OP_STOREI4_MEMINDEX:
3293                         ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3294                         break;
3295                 case OP_LOADU4_MEM:
3296                         g_assert_not_reached ();
3297                         break;
3298                 case OP_LOAD_MEMINDEX:
3299                 case OP_LOADI4_MEMINDEX:
3300                 case OP_LOADU4_MEMINDEX:
3301                         ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3302                         break;
3303                 case OP_LOADI1_MEMINDEX:
3304                         ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3305                         break;
3306                 case OP_LOADU1_MEMINDEX:
3307                         ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3308                         break;
3309                 case OP_LOADI2_MEMINDEX:
3310                         ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3311                         break;
3312                 case OP_LOADU2_MEMINDEX:
3313                         ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3314                         break;
3315                 case OP_LOAD_MEMBASE:
3316                 case OP_LOADI4_MEMBASE:
3317                 case OP_LOADU4_MEMBASE:
3318                         /* this case is special, since it happens for spill code after lowering has been called */
3319                         if (arm_is_imm12 (ins->inst_offset)) {
3320                                 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3321                         } else {
3322                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3323                                 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3324                         }
3325                         break;
3326                 case OP_LOADI1_MEMBASE:
3327                         g_assert (arm_is_imm8 (ins->inst_offset));
3328                         ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3329                         break;
3330                 case OP_LOADU1_MEMBASE:
3331                         g_assert (arm_is_imm12 (ins->inst_offset));
3332                         ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3333                         break;
3334                 case OP_LOADU2_MEMBASE:
3335                         g_assert (arm_is_imm8 (ins->inst_offset));
3336                         ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3337                         break;
3338                 case OP_LOADI2_MEMBASE:
3339                         g_assert (arm_is_imm8 (ins->inst_offset));
3340                         ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3341                         break;
3342                 case OP_ICONV_TO_I1:
3343                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3344                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3345                         break;
3346                 case OP_ICONV_TO_I2:
3347                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3348                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3349                         break;
3350                 case OP_ICONV_TO_U1:
3351                         ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3352                         break;
3353                 case OP_ICONV_TO_U2:
3354                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3355                         ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3356                         break;
3357                 case OP_COMPARE:
3358                 case OP_ICOMPARE:
3359                         ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3360                         break;
3361                 case OP_COMPARE_IMM:
3362                 case OP_ICOMPARE_IMM:
3363                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3364                         g_assert (imm8 >= 0);
3365                         ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3366                         break;
3367                 case OP_BREAK:
3368                         /*
3369                          * gdb does not like encountering the hw breakpoint ins in the debugged code.
3370                          * So instead of emitting a trap, we emit a call a C function and place a
3371                          * breakpoint there.
3372                          */
3373                         //*(int*)code = 0xef9f0001;
3374                         //code += 4;
3375                         //ARM_DBRK (code);
3376                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3377                                                                  (gpointer)"mono_break");
3378                         code = emit_call_seq (cfg, code);
3379                         break;
3380                 case OP_RELAXED_NOP:
3381                         ARM_NOP (code);
3382                         break;
3383                 case OP_NOP:
3384                 case OP_DUMMY_USE:
3385                 case OP_DUMMY_STORE:
3386                 case OP_NOT_REACHED:
3387                 case OP_NOT_NULL:
3388                         break;
3389                 case OP_SEQ_POINT: {
3390                         int i;
3391                         MonoInst *info_var = cfg->arch.seq_point_info_var;
3392                         MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3393                         MonoInst *var;
3394                         int dreg = ARMREG_LR;
3395
3396                         /*
3397                          * For AOT, we use one got slot per method, which will point to a
3398                          * SeqPointInfo structure, containing all the information required
3399                          * by the code below.
3400                          */
3401                         if (cfg->compile_aot) {
3402                                 g_assert (info_var);
3403                                 g_assert (info_var->opcode == OP_REGOFFSET);
3404                                 g_assert (arm_is_imm12 (info_var->inst_offset));
3405                         }
3406
3407                         /*
3408                          * Read from the single stepping trigger page. This will cause a
3409                          * SIGSEGV when single stepping is enabled.
3410                          * We do this _before_ the breakpoint, so single stepping after
3411                          * a breakpoint is hit will step to the next IL offset.
3412                          */
3413                         g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3414
3415                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3416                                 if (cfg->compile_aot) {
3417                                         /* Load the trigger page addr from the variable initialized in the prolog */
3418                                         var = ss_trigger_page_var;
3419                                         g_assert (var);
3420                                         g_assert (var->opcode == OP_REGOFFSET);
3421                                         g_assert (arm_is_imm12 (var->inst_offset));
3422                                         ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3423                                 } else {
3424                                         ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3425                                         ARM_B (code, 0);
3426                                         *(int*)code = (int)ss_trigger_page;
3427                                         code += 4;
3428                                 }
3429                                 ARM_LDR_IMM (code, dreg, dreg, 0);
3430                         }
3431
3432                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3433
3434                         if (cfg->compile_aot) {
3435                                 guint32 offset = code - cfg->native_code;
3436                                 guint32 val;
3437
3438                                 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3439                                 /* Add the offset */
3440                                 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3441                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3442                                 /*
3443                                  * Have to emit nops to keep the difference between the offset
3444                                  * stored in seq_points and breakpoint instruction constant,
3445                                  * mono_arch_get_ip_for_breakpoint () depends on this.
3446                                  */
3447                                 if (val & 0xFF00)
3448                                         ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3449                                 else
3450                                         ARM_NOP (code);
3451                                 if (val & 0xFF0000)
3452                                         ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3453                                 else
3454                                         ARM_NOP (code);
3455                                 g_assert (!(val & 0xFF000000));
3456                                 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3457                                 ARM_LDR_IMM (code, dreg, dreg, 0);
3458
3459                                 /* What is faster, a branch or a load ? */
3460                                 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3461                                 /* The breakpoint instruction */
3462                                 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3463                         } else {
3464                                 /*
3465                                  * A placeholder for a possible breakpoint inserted by
3466                                  * mono_arch_set_breakpoint ().
3467                                  */
3468                                 for (i = 0; i < 4; ++i)
3469                                         ARM_NOP (code);
3470                         }
3471                         break;
3472                 }
3473                 case OP_ADDCC:
3474                 case OP_IADDCC:
3475                         ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3476                         break;
3477                 case OP_IADD:
3478                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3479                         break;
3480                 case OP_ADC:
3481                 case OP_IADC:
3482                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3483                         break;
3484                 case OP_ADDCC_IMM:
3485                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3486                         g_assert (imm8 >= 0);
3487                         ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3488                         break;
3489                 case OP_ADD_IMM:
3490                 case OP_IADD_IMM:
3491                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3492                         g_assert (imm8 >= 0);
3493                         ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3494                         break;
3495                 case OP_ADC_IMM:
3496                 case OP_IADC_IMM:
3497                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3498                         g_assert (imm8 >= 0);
3499                         ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3500                         break;
3501                 case OP_IADD_OVF:
3502                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3503                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3504                         break;
3505                 case OP_IADD_OVF_UN:
3506                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3507                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3508                         break;
3509                 case OP_ISUB_OVF:
3510                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3511                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3512                         break;
3513                 case OP_ISUB_OVF_UN:
3514                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3515                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3516                         break;
3517                 case OP_ADD_OVF_CARRY:
3518                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3519                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3520                         break;
3521                 case OP_ADD_OVF_UN_CARRY:
3522                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3523                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3524                         break;
3525                 case OP_SUB_OVF_CARRY:
3526                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3527                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3528                         break;
3529                 case OP_SUB_OVF_UN_CARRY:
3530                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3531                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3532                         break;
3533                 case OP_SUBCC:
3534                 case OP_ISUBCC:
3535                         ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3536                         break;
3537                 case OP_SUBCC_IMM:
3538                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3539                         g_assert (imm8 >= 0);
3540                         ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3541                         break;
3542                 case OP_ISUB:
3543                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3544                         break;
3545                 case OP_SBB:
3546                 case OP_ISBB:
3547                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3548                         break;
3549                 case OP_SUB_IMM:
3550                 case OP_ISUB_IMM:
3551                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3552                         g_assert (imm8 >= 0);
3553                         ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3554                         break;
3555                 case OP_SBB_IMM:
3556                 case OP_ISBB_IMM:
3557                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3558                         g_assert (imm8 >= 0);
3559                         ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3560                         break;
3561                 case OP_ARM_RSBS_IMM:
3562                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3563                         g_assert (imm8 >= 0);
3564                         ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3565                         break;
3566                 case OP_ARM_RSC_IMM:
3567                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3568                         g_assert (imm8 >= 0);
3569                         ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3570                         break;
3571                 case OP_IAND:
3572                         ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3573                         break;
3574                 case OP_AND_IMM:
3575                 case OP_IAND_IMM:
3576                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3577                         g_assert (imm8 >= 0);
3578                         ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3579                         break;
3580                 case OP_IDIV:
3581                 case OP_IDIV_UN:
3582                 case OP_DIV_IMM:
3583                 case OP_IREM:
3584                 case OP_IREM_UN:
3585                 case OP_REM_IMM:
3586                         /* crappy ARM arch doesn't have a DIV instruction */
3587                         g_assert_not_reached ();
3588                 case OP_IOR:
3589                         ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3590                         break;
3591                 case OP_OR_IMM:
3592                 case OP_IOR_IMM:
3593                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3594                         g_assert (imm8 >= 0);
3595                         ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3596                         break;
3597                 case OP_IXOR:
3598                         ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3599                         break;
3600                 case OP_XOR_IMM:
3601                 case OP_IXOR_IMM:
3602                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3603                         g_assert (imm8 >= 0);
3604                         ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3605                         break;
3606                 case OP_ISHL:
3607                         ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3608                         break;
3609                 case OP_SHL_IMM:
3610                 case OP_ISHL_IMM:
3611                         if (ins->inst_imm)
3612                                 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3613                         else if (ins->dreg != ins->sreg1)
3614                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3615                         break;
3616                 case OP_ISHR:
3617                         ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3618                         break;
3619                 case OP_SHR_IMM:
3620                 case OP_ISHR_IMM:
3621                         if (ins->inst_imm)
3622                                 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3623                         else if (ins->dreg != ins->sreg1)
3624                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3625                         break;
3626                 case OP_SHR_UN_IMM:
3627                 case OP_ISHR_UN_IMM:
3628                         if (ins->inst_imm)
3629                                 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3630                         else if (ins->dreg != ins->sreg1)
3631                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3632                         break;
3633                 case OP_ISHR_UN:
3634                         ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3635                         break;
3636                 case OP_INOT:
3637                         ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
3638                         break;
3639                 case OP_INEG:
3640                         ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
3641                         break;
3642                 case OP_IMUL:
3643                         if (ins->dreg == ins->sreg2)
3644                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3645                         else
3646                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
3647                         break;
3648                 case OP_MUL_IMM:
3649                         g_assert_not_reached ();
3650                         break;
3651                 case OP_IMUL_OVF:
3652                         /* FIXME: handle ovf/ sreg2 != dreg */
3653                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3654                         /* FIXME: MUL doesn't set the C/O flags on ARM */
3655                         break;
3656                 case OP_IMUL_OVF_UN:
3657                         /* FIXME: handle ovf/ sreg2 != dreg */
3658                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3659                         /* FIXME: MUL doesn't set the C/O flags on ARM */
3660                         break;
3661                 case OP_ICONST:
3662                         code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
3663                         break;
3664                 case OP_AOTCONST:
3665                         /* Load the GOT offset */
3666                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3667                         ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
3668                         ARM_B (code, 0);
3669                         *(gpointer*)code = NULL;
3670                         code += 4;
3671                         /* Load the value from the GOT */
3672                         ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
3673                         break;
3674                 case OP_ICONV_TO_I4:
3675                 case OP_ICONV_TO_U4:
3676                 case OP_MOVE:
3677                         if (ins->dreg != ins->sreg1)
3678                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3679                         break;
3680                 case OP_SETLRET: {
3681                         int saved = ins->sreg2;
3682                         if (ins->sreg2 == ARM_LSW_REG) {
3683                                 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
3684                                 saved = ARMREG_LR;
3685                         }
3686                         if (ins->sreg1 != ARM_LSW_REG)
3687                                 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
3688                         if (saved != ARM_MSW_REG)
3689                                 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
3690                         break;
3691                 }
3692                 case OP_FMOVE:
3693 #ifdef ARM_FPU_FPA
3694                         ARM_MVFD (code, ins->dreg, ins->sreg1);
3695 #elif defined(ARM_FPU_VFP)
3696                         ARM_CPYD (code, ins->dreg, ins->sreg1);
3697 #endif
3698                         break;
3699                 case OP_FCONV_TO_R4:
3700 #ifdef ARM_FPU_FPA
3701                         ARM_MVFS (code, ins->dreg, ins->sreg1);
3702 #elif defined(ARM_FPU_VFP)
3703                         ARM_CVTD (code, ins->dreg, ins->sreg1);
3704                         ARM_CVTS (code, ins->dreg, ins->dreg);
3705 #endif
3706                         break;
3707                 case OP_JMP:
3708                         /*
3709                          * Keep in sync with mono_arch_emit_epilog
3710                          */
3711                         g_assert (!cfg->method->save_lmf);
3712
3713                         code = emit_load_volatile_arguments (cfg, code);
3714
3715                         code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
3716                         if (iphone_abi) {
3717                                 if (cfg->used_int_regs)
3718                                         ARM_POP (code, cfg->used_int_regs);
3719                                 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
3720                         } else {
3721                                 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
3722                         }
3723                         mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3724                         if (cfg->compile_aot) {
3725                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3726                                 ARM_B (code, 0);
3727                                 *(gpointer*)code = NULL;
3728                                 code += 4;
3729                                 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
3730                         } else {
3731                                 ARM_B (code, 0);
3732                         }
3733                         break;
3734                 case OP_CHECK_THIS:
3735                         /* ensure ins->sreg1 is not NULL */
3736                         ARM_LDR_IMM (code, ARMREG_LR, ins->sreg1, 0);
3737                         break;
3738                 case OP_ARGLIST: {
3739                         g_assert (cfg->sig_cookie < 128);
3740                         ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
3741                         ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
3742                         break;
3743                 }
3744                 case OP_FCALL:
3745                 case OP_LCALL:
3746                 case OP_VCALL:
3747                 case OP_VCALL2:
3748                 case OP_VOIDCALL:
3749                 case OP_CALL:
3750                         call = (MonoCallInst*)ins;
3751                         if (ins->flags & MONO_INST_HAS_METHOD)
3752                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
3753                         else
3754                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
3755                         code = emit_call_seq (cfg, code);
3756                         code = emit_move_return_value (cfg, ins, code);
3757                         break;
3758                 case OP_FCALL_REG:
3759                 case OP_LCALL_REG:
3760                 case OP_VCALL_REG:
3761                 case OP_VCALL2_REG:
3762                 case OP_VOIDCALL_REG:
3763                 case OP_CALL_REG:
3764                         code = emit_call_reg (code, ins->sreg1);
3765                         code = emit_move_return_value (cfg, ins, code);
3766                         break;
3767                 case OP_FCALL_MEMBASE:
3768                 case OP_LCALL_MEMBASE:
3769                 case OP_VCALL_MEMBASE:
3770                 case OP_VCALL2_MEMBASE:
3771                 case OP_VOIDCALL_MEMBASE:
3772                 case OP_CALL_MEMBASE:
3773                         g_assert (arm_is_imm12 (ins->inst_offset));
3774                         g_assert (ins->sreg1 != ARMREG_LR);
3775                         call = (MonoCallInst*)ins;
3776                         if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE) {
3777                                 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
3778                                 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
3779                                 /*
3780                                  * We can't embed the method in the code stream in PIC code, or
3781                                  * in gshared code.
3782                                  * Instead, we put it in V5 in code emitted by
3783                                  * mono_arch_emit_imt_argument (), and embed NULL here to
3784                                  * signal the IMT thunk that the value is in V5.
3785                                  */
3786                                 if (call->dynamic_imt_arg)
3787                                         *((gpointer*)code) = NULL;
3788                                 else
3789                                         *((gpointer*)code) = (gpointer)call->method;
3790                                 code += 4;
3791                         } else {
3792                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
3793                                 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
3794                         }
3795                         code = emit_move_return_value (cfg, ins, code);
3796                         break;
3797                 case OP_LOCALLOC: {
3798                         /* keep alignment */
3799                         int alloca_waste = cfg->param_area;
3800                         alloca_waste += 7;
3801                         alloca_waste &= ~7;
3802                         /* round the size to 8 bytes */
3803                         ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
3804                         ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
3805                         if (alloca_waste)
3806                                 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
3807                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
3808                         /* memzero the area: dreg holds the size, sp is the pointer */
3809                         if (ins->flags & MONO_INST_INIT) {
3810                                 guint8 *start_loop, *branch_to_cond;
3811                                 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
3812                                 branch_to_cond = code;
3813                                 ARM_B (code, 0);
3814                                 start_loop = code;
3815                                 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
3816                                 arm_patch (branch_to_cond, code);
3817                                 /* decrement by 4 and set flags */
3818                                 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, 4);
3819                                 ARM_B_COND (code, ARMCOND_GE, 0);
3820                                 arm_patch (code - 4, start_loop);
3821                         }
3822                         ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
3823                         break;
3824                 }
3825                 case OP_DYN_CALL: {
3826                         int i;
3827                         MonoInst *var = cfg->dyn_call_var;
3828
3829                         g_assert (var->opcode == OP_REGOFFSET);
3830                         g_assert (arm_is_imm12 (var->inst_offset));
3831
3832                         /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
3833                         ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
3834                         /* ip = ftn */
3835                         ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
3836
3837                         /* Save args buffer */
3838                         ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
3839
3840                         /* Set stack slots using R0 as scratch reg */
3841                         /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
3842                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
3843                                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (gpointer));
3844                                 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (gpointer));
3845                         }
3846
3847                         /* Set argument registers */
3848                         for (i = 0; i < PARAM_REGS; ++i)
3849                                 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (gpointer));
3850
3851                         /* Make the call */
3852                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
3853                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3854
3855                         /* Save result */
3856                         ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
3857                         ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
3858                         ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
3859                         break;
3860                 }
3861                 case OP_THROW: {
3862                         if (ins->sreg1 != ARMREG_R0)
3863                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
3864                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3865                                              (gpointer)"mono_arch_throw_exception");
3866                         code = emit_call_seq (cfg, code);
3867                         break;
3868                 }
3869                 case OP_RETHROW: {
3870                         if (ins->sreg1 != ARMREG_R0)
3871                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
3872                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3873                                              (gpointer)"mono_arch_rethrow_exception");
3874                         code = emit_call_seq (cfg, code);
3875                         break;
3876                 }
3877                 case OP_START_HANDLER: {
3878                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3879
3880                         if (arm_is_imm12 (spvar->inst_offset)) {
3881                                 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
3882                         } else {
3883                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
3884                                 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
3885                         }
3886                         break;
3887                 }
3888                 case OP_ENDFILTER: {
3889                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3890
3891                         if (ins->sreg1 != ARMREG_R0)
3892                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
3893                         if (arm_is_imm12 (spvar->inst_offset)) {
3894                                 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
3895                         } else {
3896                                 g_assert (ARMREG_IP != spvar->inst_basereg);
3897                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
3898                                 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
3899                         }
3900                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3901                         break;
3902                 }
3903                 case OP_ENDFINALLY: {
3904                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3905
3906                         if (arm_is_imm12 (spvar->inst_offset)) {
3907                                 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
3908                         } else {
3909                                 g_assert (ARMREG_IP != spvar->inst_basereg);
3910                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
3911                                 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
3912                         }
3913                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3914                         break;
3915                 }
3916                 case OP_CALL_HANDLER:
3917                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3918                         ARM_BL (code, 0);
3919                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3920                         break;
3921                 case OP_LABEL:
3922                         ins->inst_c0 = code - cfg->native_code;
3923                         break;
3924                 case OP_BR:
3925                         /*if (ins->inst_target_bb->native_offset) {
3926                                 ARM_B (code, 0);
3927                                 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3928                         } else*/ {
3929                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3930                                 ARM_B (code, 0);
3931                         }
3932                         break;
3933                 case OP_BR_REG:
3934                         ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
3935                         break;
3936                 case OP_SWITCH:
3937                         /*
3938                          * In the normal case we have:
3939                          *      ldr pc, [pc, ins->sreg1 << 2]
3940                          *      nop
3941                          * If aot, we have:
3942                          *      ldr lr, [pc, ins->sreg1 << 2]
3943                          *      add pc, pc, lr
3944                          * After follows the data.
3945                          * FIXME: add aot support.
3946                          */
3947                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
3948                         max_len += 4 * GPOINTER_TO_INT (ins->klass);
3949                         if (offset + max_len > (cfg->code_size - 16)) {
3950                                 cfg->code_size += max_len;
3951                                 cfg->code_size *= 2;
3952                                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3953                                 code = cfg->native_code + offset;
3954                         }
3955                         ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
3956                         ARM_NOP (code);
3957                         code += 4 * GPOINTER_TO_INT (ins->klass);
3958                         break;
3959                 case OP_CEQ:
3960                 case OP_ICEQ:
3961                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
3962                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
3963                         break;
3964                 case OP_CLT:
3965                 case OP_ICLT:
3966                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
3967                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
3968                         break;
3969                 case OP_CLT_UN:
3970                 case OP_ICLT_UN:
3971                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
3972                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
3973                         break;
3974                 case OP_CGT:
3975                 case OP_ICGT:
3976                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
3977                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
3978                         break;
3979                 case OP_CGT_UN:
3980                 case OP_ICGT_UN:
3981                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
3982                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
3983                         break;
3984                 case OP_COND_EXC_EQ:
3985                 case OP_COND_EXC_NE_UN:
3986                 case OP_COND_EXC_LT:
3987                 case OP_COND_EXC_LT_UN:
3988                 case OP_COND_EXC_GT:
3989                 case OP_COND_EXC_GT_UN:
3990                 case OP_COND_EXC_GE:
3991                 case OP_COND_EXC_GE_UN:
3992                 case OP_COND_EXC_LE:
3993                 case OP_COND_EXC_LE_UN:
3994                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
3995                         break;
3996                 case OP_COND_EXC_IEQ:
3997                 case OP_COND_EXC_INE_UN:
3998                 case OP_COND_EXC_ILT:
3999                 case OP_COND_EXC_ILT_UN:
4000                 case OP_COND_EXC_IGT:
4001                 case OP_COND_EXC_IGT_UN:
4002                 case OP_COND_EXC_IGE:
4003                 case OP_COND_EXC_IGE_UN:
4004                 case OP_COND_EXC_ILE:
4005                 case OP_COND_EXC_ILE_UN:
4006                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4007                         break;
4008                 case OP_COND_EXC_C:
4009                 case OP_COND_EXC_IC:
4010                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4011                         break;
4012                 case OP_COND_EXC_OV:
4013                 case OP_COND_EXC_IOV:
4014                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4015                         break;
4016                 case OP_COND_EXC_NC:
4017                 case OP_COND_EXC_INC:
4018                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4019                         break;
4020                 case OP_COND_EXC_NO:
4021                 case OP_COND_EXC_INO:
4022                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4023                         break;
4024                 case OP_IBEQ:
4025                 case OP_IBNE_UN:
4026                 case OP_IBLT:
4027                 case OP_IBLT_UN:
4028                 case OP_IBGT:
4029                 case OP_IBGT_UN:
4030                 case OP_IBGE:
4031                 case OP_IBGE_UN:
4032                 case OP_IBLE:
4033                 case OP_IBLE_UN:
4034                         EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4035                         break;
4036
4037                 /* floating point opcodes */
4038 #ifdef ARM_FPU_FPA
4039                 case OP_R8CONST:
4040                         if (cfg->compile_aot) {
4041                                 ARM_LDFD (code, ins->dreg, ARMREG_PC, 0);
4042                                 ARM_B (code, 1);
4043                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4044                                 code += 4;
4045                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4046                                 code += 4;
4047                         } else {
4048                                 /* FIXME: we can optimize the imm load by dealing with part of
4049                                  * the displacement in LDFD (aligning to 512).
4050                                  */
4051                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4052                                 ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
4053                         }
4054                         break;
4055                 case OP_R4CONST:
4056                         if (cfg->compile_aot) {
4057                                 ARM_LDFS (code, ins->dreg, ARMREG_PC, 0);
4058                                 ARM_B (code, 0);
4059                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4060                                 code += 4;
4061                         } else {
4062                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4063                                 ARM_LDFS (code, ins->dreg, ARMREG_LR, 0);
4064                         }
4065                         break;
4066                 case OP_STORER8_MEMBASE_REG:
4067                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4068                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4069                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4070                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4071                                 ARM_STFD (code, ins->sreg1, ARMREG_LR, 0);
4072                         } else {
4073                                 ARM_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4074                         }
4075                         break;
4076                 case OP_LOADR8_MEMBASE:
4077                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4078                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4079                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4080                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4081                                 ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
4082                         } else {
4083                                 ARM_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4084                         }
4085                         break;
4086                 case OP_STORER4_MEMBASE_REG:
4087                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4088                         ARM_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4089                         break;
4090                 case OP_LOADR4_MEMBASE:
4091                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4092                         ARM_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4093                         break;
4094                 case OP_ICONV_TO_R_UN: {
4095                         int tmpreg;
4096                         tmpreg = ins->dreg == 0? 1: 0;
4097                         ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4098                         ARM_FLTD (code, ins->dreg, ins->sreg1);
4099                         ARM_B_COND (code, ARMCOND_GE, 8);
4100                         /* save the temp register */
4101                         ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4102                         ARM_STFD (code, tmpreg, ARMREG_SP, 0);
4103                         ARM_LDFD (code, tmpreg, ARMREG_PC, 12);
4104                         ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4105                         ARM_LDFD (code, tmpreg, ARMREG_SP, 0);
4106                         ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4107                         /* skip the constant pool */
4108                         ARM_B (code, 8);
4109                         code += 4;
4110                         *(int*)code = 0x41f00000;
4111                         code += 4;
4112                         *(int*)code = 0;
4113                         code += 4;
4114                         /* FIXME: adjust:
4115                          * ldfltd  ftemp, [pc, #8] 0x41f00000 0x00000000
4116                          * adfltd  fdest, fdest, ftemp
4117                          */
4118                         break;
4119                 }
4120                 case OP_ICONV_TO_R4:
4121                         ARM_FLTS (code, ins->dreg, ins->sreg1);
4122                         break;
4123                 case OP_ICONV_TO_R8:
4124                         ARM_FLTD (code, ins->dreg, ins->sreg1);
4125                         break;
4126
4127 #elif defined(ARM_FPU_VFP)
4128
4129                 case OP_R8CONST:
4130                         if (cfg->compile_aot) {
4131                                 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4132                                 ARM_B (code, 1);
4133                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4134                                 code += 4;
4135                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4136                                 code += 4;
4137                         } else {
4138                                 /* FIXME: we can optimize the imm load by dealing with part of
4139                                  * the displacement in LDFD (aligning to 512).
4140                                  */
4141                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4142                                 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4143                         }
4144                         break;
4145                 case OP_R4CONST:
4146                         if (cfg->compile_aot) {
4147                                 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4148                                 ARM_B (code, 0);
4149                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4150                                 code += 4;
4151                                 ARM_CVTS (code, ins->dreg, ins->dreg);
4152                         } else {
4153                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4154                                 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4155                                 ARM_CVTS (code, ins->dreg, ins->dreg);
4156                         }
4157                         break;
4158                 case OP_STORER8_MEMBASE_REG:
4159                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4160                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4161                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4162                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4163                                 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4164                         } else {
4165                                 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4166                         }
4167                         break;
4168                 case OP_LOADR8_MEMBASE:
4169                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4170                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4171                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4172                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4173                                 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4174                         } else {
4175                                 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4176                         }
4177                         break;
4178                 case OP_STORER4_MEMBASE_REG:
4179                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4180                         ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4181                         ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4182                         break;
4183                 case OP_LOADR4_MEMBASE:
4184                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4185                         ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4186                         ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4187                         break;
4188                 case OP_ICONV_TO_R_UN: {
4189                         g_assert_not_reached ();
4190                         break;
4191                 }
4192                 case OP_ICONV_TO_R4:
4193                         ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4194                         ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4195                         ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4196                         break;
4197                 case OP_ICONV_TO_R8:
4198                         ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4199                         ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4200                         break;
4201
4202                 case OP_SETFRET:
4203                         if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4204                                 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4205                                 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4206                         } else {
4207                                 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4208                         }
4209                         break;
4210
4211 #endif
4212
4213                 case OP_FCONV_TO_I1:
4214                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4215                         break;
4216                 case OP_FCONV_TO_U1:
4217                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4218                         break;
4219                 case OP_FCONV_TO_I2:
4220                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4221                         break;
4222                 case OP_FCONV_TO_U2:
4223                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4224                         break;
4225                 case OP_FCONV_TO_I4:
4226                 case OP_FCONV_TO_I:
4227                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4228                         break;
4229                 case OP_FCONV_TO_U4:
4230                 case OP_FCONV_TO_U:
4231                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4232                         break;
4233                 case OP_FCONV_TO_I8:
4234                 case OP_FCONV_TO_U8:
4235                         g_assert_not_reached ();
4236                         /* Implemented as helper calls */
4237                         break;
4238                 case OP_LCONV_TO_R_UN:
4239                         g_assert_not_reached ();
4240                         /* Implemented as helper calls */
4241                         break;
4242                 case OP_LCONV_TO_OVF_I4_2: {
4243                         guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4244                         /*
4245                          * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4246                          */
4247
4248                         ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4249                         high_bit_not_set = code;
4250                         ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4251
4252                         ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4253                         valid_negative = code;
4254                         ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4255                         invalid_negative = code;
4256                         ARM_B_COND (code, ARMCOND_AL, 0);
4257
4258                         arm_patch (high_bit_not_set, code);
4259
4260                         ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4261                         valid_positive = code;
4262                         ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4263
4264                         arm_patch (invalid_negative, code);
4265                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4266
4267                         arm_patch (valid_negative, code);
4268                         arm_patch (valid_positive, code);
4269
4270                         if (ins->dreg != ins->sreg1)
4271                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4272                         break;
4273                 }
4274 #ifdef ARM_FPU_FPA
4275                 case OP_FADD:
4276                         ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4277                         break;
4278                 case OP_FSUB:
4279                         ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4280                         break;
4281                 case OP_FMUL:
4282                         ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4283                         break;
4284                 case OP_FDIV:
4285                         ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4286                         break;
4287                 case OP_FNEG:
4288                         ARM_MNFD (code, ins->dreg, ins->sreg1);
4289                         break;
4290 #elif defined(ARM_FPU_VFP)
4291                 case OP_FADD:
4292                         ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4293                         break;
4294                 case OP_FSUB:
4295                         ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4296                         break;
4297                 case OP_FMUL:
4298                         ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4299                         break;
4300                 case OP_FDIV:
4301                         ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4302                         break;
4303                 case OP_FNEG:
4304                         ARM_NEGD (code, ins->dreg, ins->sreg1);
4305                         break;
4306 #endif
4307                 case OP_FREM:
4308                         /* emulated */
4309                         g_assert_not_reached ();
4310                         break;
4311                 case OP_FCOMPARE:
4312 #ifdef ARM_FPU_FPA
4313                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4314 #elif defined(ARM_FPU_VFP)
4315                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4316                         ARM_FMSTAT (code);
4317 #endif
4318                         break;
4319                 case OP_FCEQ:
4320 #ifdef ARM_FPU_FPA
4321                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4322 #elif defined(ARM_FPU_VFP)
4323                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4324                         ARM_FMSTAT (code);
4325 #endif
4326                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4327                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4328                         break;
4329                 case OP_FCLT:
4330 #ifdef ARM_FPU_FPA
4331                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4332 #elif defined(ARM_FPU_VFP)
4333                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4334                         ARM_FMSTAT (code);
4335 #endif
4336                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4337                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4338                         break;
4339                 case OP_FCLT_UN:
4340 #ifdef ARM_FPU_FPA
4341                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4342 #elif defined(ARM_FPU_VFP)
4343                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4344                         ARM_FMSTAT (code);
4345 #endif
4346                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4347                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4348                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4349                         break;
4350                 case OP_FCGT:
4351                         /* swapped */
4352 #ifdef ARM_FPU_FPA
4353                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4354 #elif defined(ARM_FPU_VFP)
4355                         ARM_CMPD (code, ins->sreg2, ins->sreg1);
4356                         ARM_FMSTAT (code);
4357 #endif
4358                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4359                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4360                         break;
4361                 case OP_FCGT_UN:
4362                         /* swapped */
4363 #ifdef ARM_FPU_FPA
4364                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4365 #elif defined(ARM_FPU_VFP)
4366                         ARM_CMPD (code, ins->sreg2, ins->sreg1);
4367                         ARM_FMSTAT (code);
4368 #endif
4369                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4370                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4371                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4372                         break;
4373                 /* ARM FPA flags table:
4374                  * N        Less than               ARMCOND_MI
4375                  * Z        Equal                   ARMCOND_EQ
4376                  * C        Greater Than or Equal   ARMCOND_CS
4377                  * V        Unordered               ARMCOND_VS
4378                  */
4379                 case OP_FBEQ:
4380                         EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4381                         break;
4382                 case OP_FBNE_UN:
4383                         EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4384                         break;
4385                 case OP_FBLT:
4386                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4387                         break;
4388                 case OP_FBLT_UN:
4389                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4390                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4391                         break;
4392                 case OP_FBGT:
4393                 case OP_FBGT_UN:
4394                 case OP_FBLE:
4395                 case OP_FBLE_UN:
4396                         g_assert_not_reached ();
4397                         break;
4398                 case OP_FBGE:
4399 #ifdef ARM_FPU_VFP
4400                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4401 #else
4402                         /* FPA requires EQ even thou the docs suggests that just CS is enough */
4403                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4404                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4405 #endif
4406                         break;
4407                 case OP_FBGE_UN:
4408                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4409                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4410                         break;
4411
4412                 case OP_CKFINITE: {
4413 #ifdef ARM_FPU_FPA
4414                         if (ins->dreg != ins->sreg1)
4415                                 ARM_MVFD (code, ins->dreg, ins->sreg1);
4416 #elif defined(ARM_FPU_VFP)
4417                         ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4418                         ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4419                         ARM_B (code, 1);
4420                         *(guint32*)code = 0xffffffff;
4421                         code += 4;
4422                         *(guint32*)code = 0x7fefffff;
4423                         code += 4;
4424                         ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4425                         ARM_FMSTAT (code);
4426                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4427                         ARM_CMPD (code, ins->sreg1, ins->sreg1);
4428                         ARM_FMSTAT (code);
4429                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4430
4431                         ARM_CPYD (code, ins->dreg, ins->sreg1);
4432 #endif
4433                         break;
4434                 }
4435                 default:
4436                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4437                         g_assert_not_reached ();
4438                 }
4439
4440                 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4441                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4442                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4443                         g_assert_not_reached ();
4444                 }
4445
4446                 cpos += max_len;
4447
4448                 last_ins = ins;
4449                 last_offset = offset;
4450         }
4451
4452         cfg->code_len = code - cfg->native_code;
4453 }
4454
4455 #endif /* DISABLE_JIT */
4456
4457 #ifdef HAVE_AEABI_READ_TP
4458 void __aeabi_read_tp (void);
4459 #endif
4460
4461 void
4462 mono_arch_register_lowlevel_calls (void)
4463 {
4464         /* The signature doesn't matter */
4465         mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4466         mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4467
4468 #ifndef MONO_CROSS_COMPILE
4469 #ifdef HAVE_AEABI_READ_TP
4470         mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4471 #endif
4472 #endif
4473 }
4474
4475 #define patch_lis_ori(ip,val) do {\
4476                 guint16 *__lis_ori = (guint16*)(ip);    \
4477                 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff;      \
4478                 __lis_ori [3] = ((guint32)(val)) & 0xffff;      \
4479         } while (0)
4480
4481 void
4482 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4483 {
4484         MonoJumpInfo *patch_info;
4485         gboolean compile_aot = !run_cctors;
4486
4487         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4488                 unsigned char *ip = patch_info->ip.i + code;
4489                 const unsigned char *target;
4490
4491                 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4492                         gpointer *jt = (gpointer*)(ip + 8);
4493                         int i;
4494                         /* jt is the inlined jump table, 2 instructions after ip
4495                          * In the normal case we store the absolute addresses,
4496                          * otherwise the displacements.
4497                          */
4498                         for (i = 0; i < patch_info->data.table->table_size; i++)
4499                                 jt [i] = code + (int)patch_info->data.table->table [i];
4500                         continue;
4501                 }
4502                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4503
4504                 if (compile_aot) {
4505                         switch (patch_info->type) {
4506                         case MONO_PATCH_INFO_BB:
4507                         case MONO_PATCH_INFO_LABEL:
4508                                 break;
4509                         default:
4510                                 /* No need to patch these */
4511                                 continue;
4512                         }
4513                 }
4514
4515                 switch (patch_info->type) {
4516                 case MONO_PATCH_INFO_IP:
4517                         g_assert_not_reached ();
4518                         patch_lis_ori (ip, ip);
4519                         continue;
4520                 case MONO_PATCH_INFO_METHOD_REL:
4521                         g_assert_not_reached ();
4522                         *((gpointer *)(ip)) = code + patch_info->data.offset;
4523                         continue;
4524                 case MONO_PATCH_INFO_METHODCONST:
4525                 case MONO_PATCH_INFO_CLASS:
4526                 case MONO_PATCH_INFO_IMAGE:
4527                 case MONO_PATCH_INFO_FIELD:
4528                 case MONO_PATCH_INFO_VTABLE:
4529                 case MONO_PATCH_INFO_IID:
4530                 case MONO_PATCH_INFO_SFLDA:
4531                 case MONO_PATCH_INFO_LDSTR:
4532                 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4533                 case MONO_PATCH_INFO_LDTOKEN:
4534                         g_assert_not_reached ();
4535                         /* from OP_AOTCONST : lis + ori */
4536                         patch_lis_ori (ip, target);
4537                         continue;
4538                 case MONO_PATCH_INFO_R4:
4539                 case MONO_PATCH_INFO_R8:
4540                         g_assert_not_reached ();
4541                         *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4542                         continue;
4543                 case MONO_PATCH_INFO_EXC_NAME:
4544                         g_assert_not_reached ();
4545                         *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4546                         continue;
4547                 case MONO_PATCH_INFO_NONE:
4548                 case MONO_PATCH_INFO_BB_OVF:
4549                 case MONO_PATCH_INFO_EXC_OVF:
4550                         /* everything is dealt with at epilog output time */
4551                         continue;
4552                 default:
4553                         break;
4554                 }
4555                 arm_patch_general (domain, ip, target);
4556         }
4557 }
4558
4559 #ifndef DISABLE_JIT
4560
4561 /*
4562  * Stack frame layout:
4563  *
4564  *   ------------------- fp
4565  *      MonoLMF structure or saved registers
4566  *   -------------------
4567  *      locals
4568  *   -------------------
4569  *      spilled regs
4570  *   -------------------
4571  *      optional 8 bytes for tracing
4572  *   -------------------
4573  *      param area             size is cfg->param_area
4574  *   ------------------- sp
4575  */
4576 guint8 *
4577 mono_arch_emit_prolog (MonoCompile *cfg)
4578 {
4579         MonoMethod *method = cfg->method;
4580         MonoBasicBlock *bb;
4581         MonoMethodSignature *sig;
4582         MonoInst *inst;
4583         int alloc_size, pos, max_offset, i, rot_amount;
4584         guint8 *code;
4585         CallInfo *cinfo;
4586         int tracing = 0;
4587         int lmf_offset = 0;
4588         int prev_sp_offset, reg_offset;
4589
4590         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4591                 tracing = 1;
4592
4593         sig = mono_method_signature (method);
4594         cfg->code_size = 256 + sig->param_count * 64;
4595         code = cfg->native_code = g_malloc (cfg->code_size);
4596
4597         mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
4598
4599         alloc_size = cfg->stack_offset;
4600         pos = 0;
4601         prev_sp_offset = 0;
4602
4603         if (!method->save_lmf) {
4604                 if (iphone_abi) {
4605                         /*
4606                          * The iphone uses R7 as the frame pointer, and it points at the saved
4607                          * r7+lr:
4608                          *         <lr>
4609                          * r7 ->   <r7>
4610                          *         <rest of frame>
4611                          * We can't use r7 as a frame pointer since it points into the middle of
4612                          * the frame, so we keep using our own frame pointer.
4613                          * FIXME: Optimize this.
4614                          */
4615                         g_assert (darwin);
4616                         ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4617                         ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
4618                         prev_sp_offset += 8; /* r7 and lr */
4619                         mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4620                         mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
4621
4622                         /* No need to push LR again */
4623                         if (cfg->used_int_regs)
4624                                 ARM_PUSH (code, cfg->used_int_regs);
4625                 } else {
4626                         ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
4627                         prev_sp_offset += 4;
4628                 }
4629                 for (i = 0; i < 16; ++i) {
4630                         if (cfg->used_int_regs & (1 << i))
4631                                 prev_sp_offset += 4;
4632                 }
4633                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4634                 reg_offset = 0;
4635                 for (i = 0; i < 16; ++i) {
4636                         if ((cfg->used_int_regs & (1 << i))) {
4637                                 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
4638                                 reg_offset += 4;
4639                         }
4640                 }
4641                 if (iphone_abi) {
4642                         mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
4643                 } else {
4644                         mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
4645                 }
4646         } else {
4647                 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
4648                 ARM_PUSH (code, 0x5ff0);
4649                 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
4650                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4651                 reg_offset = 0;
4652                 for (i = 0; i < 16; ++i) {
4653                         if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
4654                                 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
4655                                 reg_offset += 4;
4656                         }
4657                 }
4658                 pos += sizeof (MonoLMF) - prev_sp_offset;
4659                 lmf_offset = pos;
4660         }
4661         alloc_size += pos;
4662         // align to MONO_ARCH_FRAME_ALIGNMENT bytes
4663         if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
4664                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
4665                 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
4666         }
4667
4668         /* the stack used in the pushed regs */
4669         if (prev_sp_offset & 4)
4670                 alloc_size += 4;
4671         cfg->stack_usage = alloc_size;
4672         if (alloc_size) {
4673                 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
4674                         ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4675                 } else {
4676                         code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
4677                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4678                 }
4679                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
4680         }
4681         if (cfg->frame_reg != ARMREG_SP) {
4682                 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
4683                 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
4684         }
4685         //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
4686         prev_sp_offset += alloc_size;
4687
4688         /* compute max_offset in order to use short forward jumps
4689          * we could skip do it on arm because the immediate displacement
4690          * for jumps is large enough, it may be useful later for constant pools
4691          */
4692         max_offset = 0;
4693         for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4694                 MonoInst *ins = bb->code;
4695                 bb->max_offset = max_offset;
4696
4697                 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4698                         max_offset += 6;
4699
4700                 MONO_BB_FOR_EACH_INS (bb, ins)
4701                         max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4702         }
4703
4704         /* store runtime generic context */
4705         if (cfg->rgctx_var) {
4706                 MonoInst *ins = cfg->rgctx_var;
4707
4708                 g_assert (ins->opcode == OP_REGOFFSET);
4709
4710                 if (arm_is_imm12 (ins->inst_offset)) {
4711                         ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
4712                 } else {
4713                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4714                         ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
4715                 }
4716         }
4717
4718         /* load arguments allocated to register from the stack */
4719         pos = 0;
4720
4721         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
4722
4723         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
4724                 ArgInfo *ainfo = &cinfo->ret;
4725                 inst = cfg->vret_addr;
4726                 g_assert (arm_is_imm12 (inst->inst_offset));
4727                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4728         }
4729
4730         if (sig->call_convention == MONO_CALL_VARARG) {
4731                 ArgInfo *cookie = &cinfo->sig_cookie;
4732
4733                 /* Save the sig cookie address */
4734                 g_assert (cookie->storage == RegTypeBase);
4735
4736                 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
4737                 g_assert (arm_is_imm12 (cfg->sig_cookie));
4738                 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
4739                 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4740         }
4741
4742         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4743                 ArgInfo *ainfo = cinfo->args + i;
4744                 inst = cfg->args [pos];
4745
4746                 if (cfg->verbose_level > 2)
4747                         g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
4748                 if (inst->opcode == OP_REGVAR) {
4749                         if (ainfo->storage == RegTypeGeneral)
4750                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
4751                         else if (ainfo->storage == RegTypeFP) {
4752                                 g_assert_not_reached ();
4753                         } else if (ainfo->storage == RegTypeBase) {
4754                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
4755                                         ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4756                                 } else {
4757                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4758                                         ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
4759                                 }
4760                         } else
4761                                 g_assert_not_reached ();
4762
4763                         if (cfg->verbose_level > 2)
4764                                 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
4765                 } else {
4766                         /* the argument should be put on the stack: FIXME handle size != word  */
4767                         if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
4768                                 switch (ainfo->size) {
4769                                 case 1:
4770                                         if (arm_is_imm12 (inst->inst_offset))
4771                                                 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4772                                         else {
4773                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4774                                                 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4775                                         }
4776                                         break;
4777                                 case 2:
4778                                         if (arm_is_imm8 (inst->inst_offset)) {
4779                                                 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4780                                         } else {
4781                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4782                                                 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4783                                         }
4784                                         break;
4785                                 case 8:
4786                                         g_assert (arm_is_imm12 (inst->inst_offset));
4787                                         ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4788                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
4789                                         ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
4790                                         break;
4791                                 default:
4792                                         if (arm_is_imm12 (inst->inst_offset)) {
4793                                                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4794                                         } else {
4795                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4796                                                 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4797                                         }
4798                                         break;
4799                                 }
4800                         } else if (ainfo->storage == RegTypeBaseGen) {
4801                                 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
4802                                 g_assert (arm_is_imm12 (inst->inst_offset));
4803                                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4804                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
4805                                 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
4806                         } else if (ainfo->storage == RegTypeBase) {
4807                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
4808                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4809                                 } else {
4810                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
4811                                         ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
4812                                 }
4813
4814                                 switch (ainfo->size) {
4815                                 case 1:
4816                                         if (arm_is_imm8 (inst->inst_offset)) {
4817                                                 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4818                                         } else {
4819                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4820                                                 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4821                                         }
4822                                         break;
4823                                 case 2:
4824                                         if (arm_is_imm8 (inst->inst_offset)) {
4825                                                 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4826                                         } else {
4827                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4828                                                 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4829                                         }
4830                                         break;
4831                                 case 8:
4832                                         if (arm_is_imm12 (inst->inst_offset)) {
4833                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4834                                         } else {
4835                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4836                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4837                                         }
4838                                         if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
4839                                                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
4840                                         } else {
4841                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
4842                                                 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
4843                                         }
4844                                         if (arm_is_imm12 (inst->inst_offset + 4)) {
4845                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
4846                                         } else {
4847                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
4848                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4849                                         }
4850                                         break;
4851                                 default:
4852                                         if (arm_is_imm12 (inst->inst_offset)) {
4853                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4854                                         } else {
4855                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4856                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4857                                         }
4858                                         break;
4859                                 }
4860                         } else if (ainfo->storage == RegTypeFP) {
4861                                 g_assert_not_reached ();
4862                         } else if (ainfo->storage == RegTypeStructByVal) {
4863                                 int doffset = inst->inst_offset;
4864                                 int soffset = 0;
4865                                 int cur_reg;
4866                                 int size = 0;
4867                                 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
4868                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
4869                                         if (arm_is_imm12 (doffset)) {
4870                                                 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
4871                                         } else {
4872                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
4873                                                 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
4874                                         }
4875                                         soffset += sizeof (gpointer);
4876                                         doffset += sizeof (gpointer);
4877                                 }
4878                                 if (ainfo->vtsize) {
4879                                         /* FIXME: handle overrun! with struct sizes not multiple of 4 */
4880                                         //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
4881                                         code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
4882                                 }
4883                         } else if (ainfo->storage == RegTypeStructByAddr) {
4884                                 g_assert_not_reached ();
4885                                 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
4886                                 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
4887                         } else
4888                                 g_assert_not_reached ();
4889                 }
4890                 pos++;
4891         }
4892
4893         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4894                 if (cfg->compile_aot)
4895                         /* AOT code is only used in the root domain */
4896                         code = mono_arm_emit_load_imm (code, ARMREG_R0, 0);
4897                 else
4898                         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->domain);
4899                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4900                              (gpointer)"mono_jit_thread_attach");
4901                 code = emit_call_seq (cfg, code);
4902         }
4903
4904         if (method->save_lmf) {
4905                 gboolean get_lmf_fast = FALSE;
4906
4907 #ifdef HAVE_AEABI_READ_TP
4908                 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
4909
4910                 if (lmf_addr_tls_offset != -1) {
4911                         get_lmf_fast = TRUE;
4912
4913                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4914                                                                  (gpointer)"__aeabi_read_tp");
4915                         code = emit_call_seq (cfg, code);
4916
4917                         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
4918                         get_lmf_fast = TRUE;
4919                 }
4920 #endif
4921                 if (!get_lmf_fast) {
4922                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4923                                                                  (gpointer)"mono_get_lmf_addr");
4924                         code = emit_call_seq (cfg, code);
4925                 }
4926                 /* we build the MonoLMF structure on the stack - see mini-arm.h */
4927                 /* lmf_offset is the offset from the previous stack pointer,
4928                  * alloc_size is the total stack space allocated, so the offset
4929                  * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
4930                  * The pointer to the struct is put in r1 (new_lmf).
4931                  * r2 is used as scratch
4932                  * The callee-saved registers are already in the MonoLMF structure
4933                  */
4934                 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, alloc_size - lmf_offset);
4935                 /* r0 is the result from mono_get_lmf_addr () */
4936                 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
4937                 /* new_lmf->previous_lmf = *lmf_addr */
4938                 ARM_LDR_IMM (code, ARMREG_R2, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
4939                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
4940                 /* *(lmf_addr) = r1 */
4941                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
4942                 /* Skip method (only needed for trampoline LMF frames) */
4943                 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, esp));
4944                 /* save the current IP */
4945                 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
4946                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, eip));
4947         }
4948
4949         if (tracing)
4950                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4951
4952         if (cfg->arch.seq_point_info_var) {
4953                 MonoInst *ins = cfg->arch.seq_point_info_var;
4954
4955                 /* Initialize the variable from a GOT slot */
4956                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
4957                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
4958                 ARM_B (code, 0);
4959                 *(gpointer*)code = NULL;
4960                 code += 4;
4961                 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
4962
4963                 g_assert (ins->opcode == OP_REGOFFSET);
4964
4965                 if (arm_is_imm12 (ins->inst_offset)) {
4966                         ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
4967                 } else {
4968                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4969                         ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
4970                 }
4971         }
4972
4973         /* Initialize ss_trigger_page_var */
4974         {
4975                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4976                 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4977                 int dreg = ARMREG_LR;
4978
4979                 if (info_var) {
4980                         g_assert (info_var->opcode == OP_REGOFFSET);
4981                         g_assert (arm_is_imm12 (info_var->inst_offset));
4982
4983                         ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4984                         /* Load the trigger page addr */
4985                         ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
4986                         ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
4987                 }
4988         }
4989
4990         cfg->code_len = code - cfg->native_code;
4991         g_assert (cfg->code_len < cfg->code_size);
4992         g_free (cinfo);
4993
4994         return code;
4995 }
4996
4997 void
4998 mono_arch_emit_epilog (MonoCompile *cfg)
4999 {
5000         MonoMethod *method = cfg->method;
5001         int pos, i, rot_amount;
5002         int max_epilog_size = 16 + 20*4;
5003         guint8 *code;
5004         CallInfo *cinfo;
5005
5006         if (cfg->method->save_lmf)
5007                 max_epilog_size += 128;
5008
5009         if (mono_jit_trace_calls != NULL)
5010                 max_epilog_size += 50;
5011
5012         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5013                 max_epilog_size += 50;
5014
5015         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5016                 cfg->code_size *= 2;
5017                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5018                 mono_jit_stats.code_reallocs++;
5019         }
5020
5021         /*
5022          * Keep in sync with OP_JMP
5023          */
5024         code = cfg->native_code + cfg->code_len;
5025
5026         if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5027                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5028         }
5029         pos = 0;
5030
5031         /* Load returned vtypes into registers if needed */
5032         cinfo = cfg->arch.cinfo;
5033         if (cinfo->ret.storage == RegTypeStructByVal) {
5034                 MonoInst *ins = cfg->ret;
5035
5036                 if (arm_is_imm12 (ins->inst_offset)) {
5037                         ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5038                 } else {
5039                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5040                         ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5041                 }
5042         }
5043
5044         if (method->save_lmf) {
5045                 int lmf_offset, reg, sp_adj, regmask;
5046                 /* all but r0-r3, sp and pc */
5047                 pos += sizeof (MonoLMF) - (4 * 10);
5048                 lmf_offset = pos;
5049                 /* r2 contains the pointer to the current LMF */
5050                 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, cfg->stack_usage - lmf_offset);
5051                 /* ip = previous_lmf */
5052                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
5053                 /* lr = lmf_addr */
5054                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
5055                 /* *(lmf_addr) = previous_lmf */
5056                 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
5057                 /* This points to r4 inside MonoLMF->iregs */
5058                 sp_adj = (sizeof (MonoLMF) - 10 * sizeof (gulong));
5059                 reg = ARMREG_R4;
5060                 regmask = 0x9ff0; /* restore lr to pc */
5061                 /* Skip caller saved registers not used by the method */
5062                 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5063                         regmask &= ~(1 << reg);
5064                         sp_adj += 4;
5065                         reg ++;
5066                 }
5067                 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5068                 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_R2, sp_adj);
5069                 /* restore iregs */
5070                 ARM_POP (code, regmask);
5071         } else {
5072                 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5073                         ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5074                 } else {
5075                         code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5076                         ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5077                 }
5078
5079                 if (iphone_abi) {
5080                         /* Restore saved gregs */
5081                         if (cfg->used_int_regs)
5082                                 ARM_POP (code, cfg->used_int_regs);
5083                         /* Restore saved r7, restore LR to PC */
5084                         ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5085                 } else {
5086                         ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5087                 }
5088         }
5089
5090         cfg->code_len = code - cfg->native_code;
5091
5092         g_assert (cfg->code_len < cfg->code_size);
5093
5094 }
5095
5096 /* remove once throw_exception_by_name is eliminated */
5097 static int
5098 exception_id_by_name (const char *name)
5099 {
5100         if (strcmp (name, "IndexOutOfRangeException") == 0)
5101                 return MONO_EXC_INDEX_OUT_OF_RANGE;
5102         if (strcmp (name, "OverflowException") == 0)
5103                 return MONO_EXC_OVERFLOW;
5104         if (strcmp (name, "ArithmeticException") == 0)
5105                 return MONO_EXC_ARITHMETIC;
5106         if (strcmp (name, "DivideByZeroException") == 0)
5107                 return MONO_EXC_DIVIDE_BY_ZERO;
5108         if (strcmp (name, "InvalidCastException") == 0)
5109                 return MONO_EXC_INVALID_CAST;
5110         if (strcmp (name, "NullReferenceException") == 0)
5111                 return MONO_EXC_NULL_REF;
5112         if (strcmp (name, "ArrayTypeMismatchException") == 0)
5113                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5114         if (strcmp (name, "ArgumentException") == 0)
5115                 return MONO_EXC_ARGUMENT;
5116         g_error ("Unknown intrinsic exception %s\n", name);
5117         return -1;
5118 }
5119
5120 void
5121 mono_arch_emit_exceptions (MonoCompile *cfg)
5122 {
5123         MonoJumpInfo *patch_info;
5124         int i;
5125         guint8 *code;
5126         guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5127         guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5128         int max_epilog_size = 50;
5129
5130         for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5131                 exc_throw_pos [i] = NULL;
5132                 exc_throw_found [i] = 0;
5133         }
5134
5135         /* count the number of exception infos */
5136
5137         /*
5138          * make sure we have enough space for exceptions
5139          */
5140         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5141                 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5142                         i = exception_id_by_name (patch_info->data.target);
5143                         if (!exc_throw_found [i]) {
5144                                 max_epilog_size += 32;
5145                                 exc_throw_found [i] = TRUE;
5146                         }
5147                 }
5148         }
5149
5150         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5151                 cfg->code_size *= 2;
5152                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5153                 mono_jit_stats.code_reallocs++;
5154         }
5155
5156         code = cfg->native_code + cfg->code_len;
5157
5158         /* add code to raise exceptions */
5159         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5160                 switch (patch_info->type) {
5161                 case MONO_PATCH_INFO_EXC: {
5162                         MonoClass *exc_class;
5163                         unsigned char *ip = patch_info->ip.i + cfg->native_code;
5164
5165                         i = exception_id_by_name (patch_info->data.target);
5166                         if (exc_throw_pos [i]) {
5167                                 arm_patch (ip, exc_throw_pos [i]);
5168                                 patch_info->type = MONO_PATCH_INFO_NONE;
5169                                 break;
5170                         } else {
5171                                 exc_throw_pos [i] = code;
5172                         }
5173                         arm_patch (ip, code);
5174
5175                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5176                         g_assert (exc_class);
5177
5178                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5179                         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5180                         patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5181                         patch_info->data.name = "mono_arch_throw_corlib_exception";
5182                         patch_info->ip.i = code - cfg->native_code;
5183                         ARM_BL (code, 0);
5184                         *(guint32*)(gpointer)code = exc_class->type_token;
5185                         code += 4;
5186                         break;
5187                 }
5188                 default:
5189                         /* do nothing */
5190                         break;
5191                 }
5192         }
5193
5194         cfg->code_len = code - cfg->native_code;
5195
5196         g_assert (cfg->code_len < cfg->code_size);
5197
5198 }
5199
5200 #endif /* #ifndef DISABLE_JIT */
5201
5202 static gboolean tls_offset_inited = FALSE;
5203
5204 void
5205 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5206 {
5207         if (!tls_offset_inited) {
5208                 tls_offset_inited = TRUE;
5209
5210                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5211                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5212         }
5213 }
5214
5215 void
5216 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5217 {
5218 }
5219
5220 MonoInst*
5221 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5222 {
5223         /* FIXME: */
5224         return NULL;
5225 }
5226
5227 gboolean
5228 mono_arch_print_tree (MonoInst *tree, int arity)
5229 {
5230         return 0;
5231 }
5232
5233 MonoInst*
5234 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5235 {
5236         return mono_get_domain_intrinsic (cfg);
5237 }
5238
5239 guint32
5240 mono_arch_get_patch_offset (guint8 *code)
5241 {
5242         /* OP_AOTCONST */
5243         return 8;
5244 }
5245
5246 void
5247 mono_arch_flush_register_windows (void)
5248 {
5249 }
5250
5251 #ifdef MONO_ARCH_HAVE_IMT
5252
5253 #ifndef DISABLE_JIT
5254
5255 void
5256 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5257 {
5258         if (cfg->compile_aot) {
5259                 int method_reg = mono_alloc_ireg (cfg);
5260                 MonoInst *ins;
5261
5262                 call->dynamic_imt_arg = TRUE;
5263
5264                 if (imt_arg) {
5265                         mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5266                 } else {
5267                         MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5268                         ins->dreg = method_reg;
5269                         ins->inst_p0 = call->method;
5270                         ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5271                         MONO_ADD_INS (cfg->cbb, ins);
5272
5273                         mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5274                 }
5275         } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5276
5277                 /* Always pass in a register for simplicity */
5278                 call->dynamic_imt_arg = TRUE;
5279
5280                 cfg->uses_rgctx_reg = TRUE;
5281
5282                 if (imt_arg) {
5283                         mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5284                 } else {
5285                         MonoInst *ins;
5286                         int method_reg = mono_alloc_preg (cfg);
5287
5288                         MONO_INST_NEW (cfg, ins, OP_PCONST);
5289                         ins->inst_p0 = call->method;
5290                         ins->dreg = method_reg;
5291                         MONO_ADD_INS (cfg->cbb, ins);
5292
5293                         mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5294                 }
5295         }
5296 }
5297
5298 #endif /* DISABLE_JIT */
5299
5300 MonoMethod*
5301 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5302 {
5303         guint32 *code_ptr = (guint32*)code;
5304         code_ptr -= 2;
5305
5306         if (mono_use_llvm)
5307                 /* Passed in V5 */
5308                 return (MonoMethod*)regs [ARMREG_V5];
5309
5310         /* The IMT value is stored in the code stream right after the LDC instruction. */
5311         if (!IS_LDR_PC (code_ptr [0])) {
5312                 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5313                 g_assert (IS_LDR_PC (code_ptr [0]));
5314         }
5315         if (code_ptr [1] == 0)
5316                 /* This is AOTed code, the IMT method is in V5 */
5317                 return (MonoMethod*)regs [ARMREG_V5];
5318         else
5319                 return (MonoMethod*) code_ptr [1];
5320 }
5321
5322 MonoVTable*
5323 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5324 {
5325         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5326 }
5327
5328 #define ENABLE_WRONG_METHOD_CHECK 0
5329 #define BASE_SIZE (6 * 4)
5330 #define BSEARCH_ENTRY_SIZE (4 * 4)
5331 #define CMP_SIZE (3 * 4)
5332 #define BRANCH_SIZE (1 * 4)
5333 #define CALL_SIZE (2 * 4)
5334 #define WMC_SIZE (5 * 4)
5335 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5336
5337 static arminstr_t *
5338 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5339 {
5340         guint32 delta = DISTANCE (target, code);
5341         delta -= 8;
5342         g_assert (delta >= 0 && delta <= 0xFFF);
5343         *target = *target | delta;
5344         *code = value;
5345         return code + 1;
5346 }
5347
5348 gpointer
5349 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5350         gpointer fail_tramp)
5351 {
5352         int size, i, extra_space = 0;
5353         arminstr_t *code, *start, *vtable_target = NULL;
5354         gboolean large_offsets = FALSE;
5355         guint32 **constant_pool_starts;
5356
5357         size = BASE_SIZE;
5358         constant_pool_starts = g_new0 (guint32*, count);
5359
5360         for (i = 0; i < count; ++i) {
5361                 MonoIMTCheckItem *item = imt_entries [i];
5362                 if (item->is_equals) {
5363                         gboolean fail_case = !item->check_target_idx && fail_tramp;
5364
5365                         if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5366                                 item->chunk_size += 32;
5367                                 large_offsets = TRUE;
5368                         }
5369
5370                         if (item->check_target_idx || fail_case) {
5371                                 if (!item->compare_done || fail_case)
5372                                         item->chunk_size += CMP_SIZE;
5373                                 item->chunk_size += BRANCH_SIZE;
5374                         } else {
5375 #if ENABLE_WRONG_METHOD_CHECK
5376                                 item->chunk_size += WMC_SIZE;
5377 #endif
5378                         }
5379                         if (fail_case) {
5380                                 item->chunk_size += 16;
5381                                 large_offsets = TRUE;
5382                         }
5383                         item->chunk_size += CALL_SIZE;
5384                 } else {
5385                         item->chunk_size += BSEARCH_ENTRY_SIZE;
5386                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5387                 }
5388                 size += item->chunk_size;
5389         }
5390
5391         if (large_offsets)
5392                 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5393
5394         if (fail_tramp)
5395                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5396         else
5397                 code = mono_domain_code_reserve (domain, size);
5398         start = code;
5399
5400 #if DEBUG_IMT
5401         printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5402         for (i = 0; i < count; ++i) {
5403                 MonoIMTCheckItem *item = imt_entries [i];
5404                 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5405         }
5406 #endif
5407
5408         if (large_offsets)
5409                 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5410         else
5411                 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5412         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5413         vtable_target = code;
5414         ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5415
5416         if (mono_use_llvm) {
5417                 /* LLVM always passes the IMT method in R5 */
5418                 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5419         } else {
5420                 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5421                 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5422                 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5423         }
5424
5425         for (i = 0; i < count; ++i) {
5426                 MonoIMTCheckItem *item = imt_entries [i];
5427                 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5428                 gint32 vtable_offset;
5429
5430                 item->code_target = (guint8*)code;
5431
5432                 if (item->is_equals) {
5433                         gboolean fail_case = !item->check_target_idx && fail_tramp;
5434
5435                         if (item->check_target_idx || fail_case) {
5436                                 if (!item->compare_done || fail_case) {
5437                                         imt_method = code;
5438                                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5439                                         ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5440                                 }
5441                                 item->jmp_code = (guint8*)code;
5442                                 ARM_B_COND (code, ARMCOND_NE, 0);
5443                         } else {
5444                                 /*Enable the commented code to assert on wrong method*/
5445 #if ENABLE_WRONG_METHOD_CHECK
5446                                 imt_method = code;
5447                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5448                                 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5449                                 ARM_B_COND (code, ARMCOND_NE, 1);
5450
5451                                 ARM_DBRK (code);
5452 #endif
5453                         }
5454
5455                         if (item->has_target_code) {
5456                                 target_code_ins = code;
5457                                 /* Load target address */
5458                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5459                                 /* Save it to the fourth slot */
5460                                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5461                                 /* Restore registers and branch */
5462                                 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5463
5464                                 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5465                         } else {
5466                                 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5467                                 if (!arm_is_imm12 (vtable_offset)) {
5468                                         /*
5469                                          * We need to branch to a computed address but we don't have
5470                                          * a free register to store it, since IP must contain the
5471                                          * vtable address. So we push the two values to the stack, and
5472                                          * load them both using LDM.
5473                                          */
5474                                         /* Compute target address */
5475                                         vtable_offset_ins = code;
5476                                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5477                                         ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5478                                         /* Save it to the fourth slot */
5479                                         ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5480                                         /* Restore registers and branch */
5481                                         ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5482
5483                                         code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5484                                 } else {
5485                                         ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5486                                         if (large_offsets)
5487                                                 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5488                                         ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5489                                 }
5490                         }
5491
5492                         if (fail_case) {
5493                                 arm_patch (item->jmp_code, (guchar*)code);
5494
5495                                 target_code_ins = code;
5496                                 /* Load target address */
5497                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5498                                 /* Save it to the fourth slot */
5499                                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5500                                 /* Restore registers and branch */
5501                                 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5502
5503                                 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5504                                 item->jmp_code = NULL;
5505                         }
5506
5507                         if (imt_method)
5508                                 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5509
5510                         /*must emit after unconditional branch*/
5511                         if (vtable_target) {
5512                                 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5513                                 item->chunk_size += 4;
5514                                 vtable_target = NULL;
5515                         }
5516
5517                         /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5518                         constant_pool_starts [i] = code;
5519                         if (extra_space) {
5520                                 code += extra_space;
5521                                 extra_space = 0;
5522                         }
5523                 } else {
5524                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5525                         ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5526
5527                         item->jmp_code = (guint8*)code;
5528                         ARM_B_COND (code, ARMCOND_GE, 0);
5529                         ++extra_space;
5530                 }
5531         }
5532
5533         for (i = 0; i < count; ++i) {
5534                 MonoIMTCheckItem *item = imt_entries [i];
5535                 if (item->jmp_code) {
5536                         if (item->check_target_idx)
5537                                 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5538                 }
5539                 if (i > 0 && item->is_equals) {
5540                         int j;
5541                         arminstr_t *space_start = constant_pool_starts [i];
5542                         for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5543                                 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5544                         }
5545                 }
5546         }
5547
5548 #if DEBUG_IMT
5549         {
5550                 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5551                 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5552                 g_free (buff);
5553         }
5554 #endif
5555
5556         g_free (constant_pool_starts);
5557
5558         mono_arch_flush_icache ((guint8*)start, size);
5559         mono_stats.imt_thunks_size += code - start;
5560
5561         g_assert (DISTANCE (start, code) <= size);
5562         return start;
5563 }
5564
5565 #endif
5566
5567 gpointer
5568 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5569 {
5570         if (reg == ARMREG_SP)
5571                 return (gpointer)ctx->esp;
5572         else
5573                 return (gpointer)ctx->regs [reg];
5574 }
5575
5576 /*
5577  * mono_arch_get_trampolines:
5578  *
5579  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
5580  * for AOT.
5581  */
5582 GSList *
5583 mono_arch_get_trampolines (gboolean aot)
5584 {
5585         return mono_arm_get_exception_trampolines (aot);
5586 }
5587
5588 /*
5589  * mono_arch_set_breakpoint:
5590  *
5591  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
5592  * The location should contain code emitted by OP_SEQ_POINT.
5593  */
5594 void
5595 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5596 {
5597         guint8 *code = ip;
5598         guint32 native_offset = ip - (guint8*)ji->code_start;
5599
5600         if (ji->from_aot) {
5601                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5602
5603                 g_assert (native_offset % 4 == 0);
5604                 g_assert (info->bp_addrs [native_offset / 4] == 0);
5605                 info->bp_addrs [native_offset / 4] = bp_trigger_page;
5606         } else {
5607                 int dreg = ARMREG_LR;
5608
5609                 /* Read from another trigger page */
5610                 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
5611                 ARM_B (code, 0);
5612                 *(int*)code = (int)bp_trigger_page;
5613                 code += 4;
5614                 ARM_LDR_IMM (code, dreg, dreg, 0);
5615
5616                 mono_arch_flush_icache (code - 16, 16);
5617
5618 #if 0
5619                 /* This is currently implemented by emitting an SWI instruction, which
5620                  * qemu/linux seems to convert to a SIGILL.
5621                  */
5622                 *(int*)code = (0xef << 24) | 8;
5623                 code += 4;
5624                 mono_arch_flush_icache (code - 4, 4);
5625 #endif
5626         }
5627 }
5628
5629 /*
5630  * mono_arch_clear_breakpoint:
5631  *
5632  *   Clear the breakpoint at IP.
5633  */
5634 void
5635 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5636 {
5637         guint8 *code = ip;
5638         int i;
5639
5640         if (ji->from_aot) {
5641                 guint32 native_offset = ip - (guint8*)ji->code_start;
5642                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5643
5644                 g_assert (native_offset % 4 == 0);
5645                 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
5646                 info->bp_addrs [native_offset / 4] = 0;
5647         } else {
5648                 for (i = 0; i < 4; ++i)
5649                         ARM_NOP (code);
5650
5651                 mono_arch_flush_icache (ip, code - ip);
5652         }
5653 }
5654
5655 /*
5656  * mono_arch_start_single_stepping:
5657  *
5658  *   Start single stepping.
5659  */
5660 void
5661 mono_arch_start_single_stepping (void)
5662 {
5663         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
5664 }
5665
5666 /*
5667  * mono_arch_stop_single_stepping:
5668  *
5669  *   Stop single stepping.
5670  */
5671 void
5672 mono_arch_stop_single_stepping (void)
5673 {
5674         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
5675 }
5676
5677 #if __APPLE__
5678 #define DBG_SIGNAL SIGBUS
5679 #else
5680 #define DBG_SIGNAL SIGSEGV
5681 #endif
5682
5683 /*
5684  * mono_arch_is_single_step_event:
5685  *
5686  *   Return whenever the machine state in SIGCTX corresponds to a single
5687  * step event.
5688  */
5689 gboolean
5690 mono_arch_is_single_step_event (void *info, void *sigctx)
5691 {
5692         siginfo_t *sinfo = info;
5693
5694         /* Sometimes the address is off by 4 */
5695         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
5696                 return TRUE;
5697         else
5698                 return FALSE;
5699 }
5700
5701 /*
5702  * mono_arch_is_breakpoint_event:
5703  *
5704  *   Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
5705  */
5706 gboolean
5707 mono_arch_is_breakpoint_event (void *info, void *sigctx)
5708 {
5709         siginfo_t *sinfo = info;
5710
5711         if (sinfo->si_signo == DBG_SIGNAL) {
5712                 /* Sometimes the address is off by 4 */
5713                 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
5714                         return TRUE;
5715                 else
5716                         return FALSE;
5717         } else {
5718                 return FALSE;
5719         }
5720 }
5721
5722 guint8*
5723 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
5724 {
5725         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
5726
5727         if (ji->from_aot)
5728                 ip -= 6 * 4;
5729         else
5730                 ip -= 12;
5731
5732         return ip;
5733 }
5734
5735 guint8*
5736 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
5737 {
5738         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
5739
5740         ip += 4;
5741
5742         return ip;
5743 }
5744
5745 /*
5746  * mono_arch_skip_breakpoint:
5747  *
5748  *   See mini-amd64.c for docs.
5749  */
5750 void
5751 mono_arch_skip_breakpoint (MonoContext *ctx)
5752 {
5753         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
5754 }
5755
5756 /*
5757  * mono_arch_skip_single_step:
5758  *
5759  *   See mini-amd64.c for docs.
5760  */
5761 void
5762 mono_arch_skip_single_step (MonoContext *ctx)
5763 {
5764         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
5765 }
5766
5767 /*
5768  * mono_arch_get_seq_point_info:
5769  *
5770  *   See mini-amd64.c for docs.
5771  */
5772 gpointer
5773 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
5774 {
5775         SeqPointInfo *info;
5776         MonoJitInfo *ji;
5777
5778         // FIXME: Add a free function
5779
5780         mono_domain_lock (domain);
5781         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
5782                                                                 code);
5783         mono_domain_unlock (domain);
5784
5785         if (!info) {
5786                 ji = mono_jit_info_table_find (domain, (char*)code);
5787                 g_assert (ji);
5788
5789                 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
5790
5791                 info->ss_trigger_page = ss_trigger_page;
5792                 info->bp_trigger_page = bp_trigger_page;
5793
5794                 mono_domain_lock (domain);
5795                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
5796                                                          code, info);
5797                 mono_domain_unlock (domain);
5798         }
5799
5800         return info;
5801 }
5802
5803 /*
5804  * mono_arch_set_target:
5805  *
5806  *   Set the target architecture the JIT backend should generate code for, in the form
5807  * of a GNU target triplet. Only used in AOT mode.
5808  */
5809 void
5810 mono_arch_set_target (char *mtriple)
5811 {
5812         /* The GNU target triple format is not very well documented */
5813         if (strstr (mtriple, "armv7"))
5814                 v7_supported = TRUE;
5815         if (strstr (mtriple, "darwin")) {
5816                 v5_supported = TRUE;
5817                 thumb_supported = TRUE;
5818                 darwin = TRUE;
5819                 iphone_abi = TRUE;
5820         }
5821         if (strstr (mtriple, "gnueabi"))
5822                 eabi_supported = TRUE;
5823 }
5824