2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
24 #include "mini-arm-tls.h"
28 #include "debugger-agent.h"
30 #include "mono/arch/arm/arm-vfp-codegen.h"
32 #if defined(HAVE_KW_THREAD) && defined(__linux__) \
33 || defined(TARGET_ANDROID) \
34 || defined(TARGET_IOS)
38 /* Sanity check: This makes no sense */
39 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
40 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
44 * IS_SOFT_FLOAT: Is full software floating point used?
45 * IS_HARD_FLOAT: Is full hardware floating point used?
46 * IS_VFP: Is hardware floating point with software ABI used?
48 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
49 * IS_VFP may delegate to mono_arch_is_soft_float ().
52 #if defined(ARM_FPU_VFP_HARD)
53 #define IS_SOFT_FLOAT (FALSE)
54 #define IS_HARD_FLOAT (TRUE)
56 #elif defined(ARM_FPU_NONE)
57 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
58 #define IS_HARD_FLOAT (FALSE)
59 #define IS_VFP (!mono_arch_is_soft_float ())
61 #define IS_SOFT_FLOAT (FALSE)
62 #define IS_HARD_FLOAT (FALSE)
66 #define THUNK_SIZE (3 * 4)
68 #ifdef __native_client_codegen__
69 const guint kNaClAlignment = kNaClAlignmentARM;
70 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
71 gint8 nacl_align_byte = -1; /* 0xff */
74 mono_arch_nacl_pad (guint8 *code, int pad)
76 /* Not yet properly implemented. */
77 g_assert_not_reached ();
82 mono_arch_nacl_skip_nops (guint8 *code)
84 /* Not yet properly implemented. */
85 g_assert_not_reached ();
89 #endif /* __native_client_codegen__ */
91 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
94 void sys_icache_invalidate (void *start, size_t len);
97 /* This mutex protects architecture specific caches */
98 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
99 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
100 static mono_mutex_t mini_arch_mutex;
102 static gboolean v5_supported = FALSE;
103 static gboolean v6_supported = FALSE;
104 static gboolean v7_supported = FALSE;
105 static gboolean v7s_supported = FALSE;
106 static gboolean thumb_supported = FALSE;
107 static gboolean thumb2_supported = FALSE;
109 * Whenever to use the ARM EABI
111 static gboolean eabi_supported = FALSE;
114 * Whenever to use the iphone ABI extensions:
115 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
116 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
117 * This is required for debugging/profiling tools to work, but it has some overhead so it should
118 * only be turned on in debug builds.
120 static gboolean iphone_abi = FALSE;
123 * The FPU we are generating code for. This is NOT runtime configurable right now,
124 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
126 static MonoArmFPU arm_fpu;
128 #if defined(ARM_FPU_VFP_HARD)
130 * On armhf, d0-d7 are used for argument passing and d8-d15
131 * must be preserved across calls, which leaves us no room
132 * for scratch registers. So we use d14-d15 but back up their
133 * previous contents to a stack slot before using them - see
134 * mono_arm_emit_vfp_scratch_save/_restore ().
136 static int vfp_scratch1 = ARM_VFP_D14;
137 static int vfp_scratch2 = ARM_VFP_D15;
140 * On armel, d0-d7 do not need to be preserved, so we can
141 * freely make use of them as scratch registers.
143 static int vfp_scratch1 = ARM_VFP_D0;
144 static int vfp_scratch2 = ARM_VFP_D1;
149 static volatile int ss_trigger_var = 0;
151 static gpointer single_step_tramp, breakpoint_tramp;
154 * The code generated for sequence points reads from this location, which is
155 * made read-only when single stepping is enabled.
157 static gpointer ss_trigger_page;
159 /* Enabled breakpoints read from this trigger page */
160 static gpointer bp_trigger_page;
164 * floating point support: on ARM it is a mess, there are at least 3
165 * different setups, each of which binary incompat with the other.
166 * 1) FPA: old and ugly, but unfortunately what current distros use
167 * the double binary format has the two words swapped. 8 double registers.
168 * Implemented usually by kernel emulation.
169 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
170 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
171 * 3) VFP: the new and actually sensible and useful FP support. Implemented
172 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
174 * We do not care about FPA. We will support soft float and VFP.
176 int mono_exc_esp_offset = 0;
178 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
179 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
180 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
182 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
183 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
184 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
186 //#define DEBUG_IMT 0
189 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
193 mono_arch_regname (int reg)
195 static const char * rnames[] = {
196 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
197 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
198 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
201 if (reg >= 0 && reg < 16)
207 mono_arch_fregname (int reg)
209 static const char * rnames[] = {
210 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
211 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
212 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
213 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
214 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
215 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
218 if (reg >= 0 && reg < 32)
226 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
228 int imm8, rot_amount;
229 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
230 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
234 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
235 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
237 code = mono_arm_emit_load_imm (code, dreg, imm);
238 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
243 /* If dreg == sreg, this clobbers IP */
245 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
247 int imm8, rot_amount;
248 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
249 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
253 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
254 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
256 code = mono_arm_emit_load_imm (code, dreg, imm);
257 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
263 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
265 /* we can use r0-r3, since this is called only for incoming args on the stack */
266 if (size > sizeof (gpointer) * 4) {
268 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
269 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
270 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
271 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
272 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
273 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
274 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
275 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
276 ARM_B_COND (code, ARMCOND_NE, 0);
277 arm_patch (code - 4, start_loop);
280 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
281 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
283 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
284 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
290 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
291 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
292 doffset = soffset = 0;
294 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
295 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
301 g_assert (size == 0);
306 emit_call_reg (guint8 *code, int reg)
309 ARM_BLX_REG (code, reg);
311 #ifdef USE_JUMP_TABLES
312 g_assert_not_reached ();
314 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
318 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
324 emit_call_seq (MonoCompile *cfg, guint8 *code)
326 #ifdef USE_JUMP_TABLES
327 code = mono_arm_patchable_bl (code, ARMCOND_AL);
329 if (cfg->method->dynamic) {
330 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
332 *(gpointer*)code = NULL;
334 code = emit_call_reg (code, ARMREG_IP);
338 cfg->thunk_area += THUNK_SIZE;
344 mono_arm_patchable_b (guint8 *code, int cond)
346 #ifdef USE_JUMP_TABLES
349 jte = mono_jumptable_add_entry ();
350 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
351 ARM_BX_COND (code, cond, ARMREG_IP);
353 ARM_B_COND (code, cond, 0);
359 mono_arm_patchable_bl (guint8 *code, int cond)
361 #ifdef USE_JUMP_TABLES
364 jte = mono_jumptable_add_entry ();
365 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
366 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
368 ARM_BL_COND (code, cond, 0);
373 #ifdef USE_JUMP_TABLES
375 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
377 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
378 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
383 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
385 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
386 ARM_LDR_IMM (code, reg, reg, 0);
392 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
395 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
396 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
398 code = emit_call_seq (cfg, code);
399 if (dreg != ARMREG_R0)
400 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
402 g_assert_not_reached ();
408 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
411 if (tls_offset_reg != ARMREG_R0)
412 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
413 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
415 code = emit_call_seq (cfg, code);
416 if (dreg != ARMREG_R0)
417 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
419 g_assert_not_reached ();
425 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
428 if (sreg != ARMREG_R1)
429 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
430 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
431 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
433 code = emit_call_seq (cfg, code);
435 g_assert_not_reached ();
441 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
444 /* Get sreg in R1 and tls_offset_reg in R0 */
445 if (tls_offset_reg == ARMREG_R1) {
446 if (sreg == ARMREG_R0) {
447 /* swap sreg and tls_offset_reg */
448 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
449 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
450 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
452 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
453 if (sreg != ARMREG_R1)
454 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
457 if (sreg != ARMREG_R1)
458 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
459 if (tls_offset_reg != ARMREG_R0)
460 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
462 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
464 code = emit_call_seq (cfg, code);
466 g_assert_not_reached ();
474 * Emit code to push an LMF structure on the LMF stack.
475 * On arm, this is intermixed with the initialization of other fields of the structure.
478 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
480 gboolean get_lmf_fast = FALSE;
483 if (mono_arm_have_tls_get ()) {
485 if (cfg->compile_aot) {
487 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
488 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
490 *(gpointer*)code = NULL;
492 /* Load the value from the GOT */
493 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
494 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
496 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
497 g_assert (lmf_addr_tls_offset != -1);
498 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
503 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
504 (gpointer)"mono_get_lmf_addr");
505 code = emit_call_seq (cfg, code);
507 /* we build the MonoLMF structure on the stack - see mini-arm.h */
508 /* lmf_offset is the offset from the previous stack pointer,
509 * alloc_size is the total stack space allocated, so the offset
510 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
511 * The pointer to the struct is put in r1 (new_lmf).
512 * ip is used as scratch
513 * The callee-saved registers are already in the MonoLMF structure
515 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
516 /* r0 is the result from mono_get_lmf_addr () */
517 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
518 /* new_lmf->previous_lmf = *lmf_addr */
519 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
520 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
521 /* *(lmf_addr) = r1 */
522 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
523 /* Skip method (only needed for trampoline LMF frames) */
524 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
525 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
526 /* save the current IP */
527 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
528 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
530 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
531 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
542 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
546 g_assert (!cfg->r4fp);
548 for (list = inst->float_args; list; list = list->next) {
549 FloatArgData *fad = list->data;
550 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
551 gboolean imm = arm_is_fpimm8 (var->inst_offset);
553 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
559 if (*offset + *max_len > cfg->code_size) {
560 cfg->code_size += *max_len;
561 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
563 code = cfg->native_code + *offset;
567 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
568 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
570 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
572 *offset = code - cfg->native_code;
579 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
583 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
585 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
588 if (!arm_is_fpimm8 (inst->inst_offset)) {
589 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
590 ARM_FSTD (code, reg, ARMREG_LR, 0);
592 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
599 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
603 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
605 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
608 if (!arm_is_fpimm8 (inst->inst_offset)) {
609 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
610 ARM_FLDD (code, reg, ARMREG_LR, 0);
612 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
621 * Emit code to pop an LMF structure from the LMF stack.
624 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
628 if (lmf_offset < 32) {
629 basereg = cfg->frame_reg;
634 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
637 /* ip = previous_lmf */
638 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
640 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
641 /* *(lmf_addr) = previous_lmf */
642 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
647 #endif /* #ifndef DISABLE_JIT */
649 #ifndef MONO_CROSS_COMPILE
651 mono_arm_have_fast_tls (void)
653 if (mini_get_debug_options ()->arm_use_fallback_tls)
655 #if (defined(HAVE_KW_THREAD) && defined(__linux__)) \
656 || defined(TARGET_ANDROID)
657 guint32* kuser_get_tls = (void*)0xffff0fe0;
658 guint32 expected [] = {0xee1d0f70, 0xe12fff1e};
660 /* Expecting mrc + bx lr in the kuser_get_tls kernel helper */
661 return memcmp (kuser_get_tls, expected, 8) == 0;
662 #elif defined(TARGET_IOS)
663 guint32 expected [] = {0x1f70ee1d, 0x0103f021, 0x0020f851, 0xbf004770};
664 /* Discard thumb bit */
665 guint32* pthread_getspecific_addr = (guint32*) ((guint32)pthread_getspecific & 0xfffffffe);
666 return memcmp ((void*)pthread_getspecific_addr, expected, 16) == 0;
674 * mono_arm_have_tls_get:
676 * Returns whether we have tls access implemented on the current
680 mono_arm_have_tls_get (void)
690 * mono_arch_get_argument_info:
691 * @csig: a method signature
692 * @param_count: the number of parameters to consider
693 * @arg_info: an array to store the result infos
695 * Gathers information on parameters such as size, alignment and
696 * padding. arg_info should be large enought to hold param_count + 1 entries.
698 * Returns the size of the activation frame.
701 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
703 int k, frame_size = 0;
704 guint32 size, align, pad;
708 t = mini_get_underlying_type (csig->ret);
709 if (MONO_TYPE_ISSTRUCT (t)) {
710 frame_size += sizeof (gpointer);
714 arg_info [0].offset = offset;
717 frame_size += sizeof (gpointer);
721 arg_info [0].size = frame_size;
723 for (k = 0; k < param_count; k++) {
724 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
726 /* ignore alignment for now */
729 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
730 arg_info [k].pad = pad;
732 arg_info [k + 1].pad = 0;
733 arg_info [k + 1].size = size;
735 arg_info [k + 1].offset = offset;
739 align = MONO_ARCH_FRAME_ALIGNMENT;
740 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
741 arg_info [k].pad = pad;
746 #define MAX_ARCH_DELEGATE_PARAMS 3
749 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
751 guint8 *code, *start;
752 GSList *unwind_ops = mono_arch_get_cie_program ();
755 start = code = mono_global_codeman_reserve (12);
757 /* Replace the this argument with the target */
758 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
759 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
760 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
762 g_assert ((code - start) <= 12);
764 mono_arch_flush_icache (start, 12);
768 size = 8 + param_count * 4;
769 start = code = mono_global_codeman_reserve (size);
771 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
772 /* slide down the arguments */
773 for (i = 0; i < param_count; ++i) {
774 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
776 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
778 g_assert ((code - start) <= size);
780 mono_arch_flush_icache (start, size);
784 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
786 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
787 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
791 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
797 * mono_arch_get_delegate_invoke_impls:
799 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
803 mono_arch_get_delegate_invoke_impls (void)
809 get_delegate_invoke_impl (&info, TRUE, 0);
810 res = g_slist_prepend (res, info);
812 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
813 get_delegate_invoke_impl (&info, FALSE, i);
814 res = g_slist_prepend (res, info);
821 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
823 guint8 *code, *start;
826 /* FIXME: Support more cases */
827 sig_ret = mini_get_underlying_type (sig->ret);
828 if (MONO_TYPE_ISSTRUCT (sig_ret))
832 static guint8* cached = NULL;
833 mono_mini_arch_lock ();
835 mono_mini_arch_unlock ();
840 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
843 start = get_delegate_invoke_impl (&info, TRUE, 0);
844 mono_tramp_info_register (info, NULL);
847 mono_mini_arch_unlock ();
850 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
853 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
855 for (i = 0; i < sig->param_count; ++i)
856 if (!mono_is_regsize_var (sig->params [i]))
859 mono_mini_arch_lock ();
860 code = cache [sig->param_count];
862 mono_mini_arch_unlock ();
867 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
868 start = mono_aot_get_trampoline (name);
872 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
873 mono_tramp_info_register (info, NULL);
875 cache [sig->param_count] = start;
876 mono_mini_arch_unlock ();
884 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
890 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
892 return (gpointer)regs [ARMREG_R0];
896 * Initialize the cpu to execute managed code.
899 mono_arch_cpu_init (void)
901 i8_align = MONO_ABI_ALIGNOF (gint64);
902 #ifdef MONO_CROSS_COMPILE
903 /* Need to set the alignment of i8 since it can different on the target */
904 #ifdef TARGET_ANDROID
906 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
912 * Initialize architecture specific code.
915 mono_arch_init (void)
917 const char *cpu_arch;
919 mono_mutex_init_recursive (&mini_arch_mutex);
920 if (mini_get_debug_options ()->soft_breakpoints) {
921 single_step_tramp = mini_get_single_step_trampoline ();
922 breakpoint_tramp = mini_get_breakpoint_trampoline ();
924 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
925 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
926 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
929 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
930 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
931 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
932 #if defined(ENABLE_GSHAREDVT)
933 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
935 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
937 #if defined(__ARM_EABI__)
938 eabi_supported = TRUE;
941 #if defined(ARM_FPU_VFP_HARD)
942 arm_fpu = MONO_ARM_FPU_VFP_HARD;
944 arm_fpu = MONO_ARM_FPU_VFP;
946 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
948 * If we're compiling with a soft float fallback and it
949 * turns out that no VFP unit is available, we need to
950 * switch to soft float. We don't do this for iOS, since
951 * iOS devices always have a VFP unit.
953 if (!mono_hwcap_arm_has_vfp)
954 arm_fpu = MONO_ARM_FPU_NONE;
957 * This environment variable can be useful in testing
958 * environments to make sure the soft float fallback
959 * works. Most ARM devices have VFP units these days, so
960 * normally soft float code would not be exercised much.
962 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
964 if (soft && !strncmp (soft, "1", 1))
965 arm_fpu = MONO_ARM_FPU_NONE;
969 v5_supported = mono_hwcap_arm_is_v5;
970 v6_supported = mono_hwcap_arm_is_v6;
971 v7_supported = mono_hwcap_arm_is_v7;
972 v7s_supported = mono_hwcap_arm_is_v7s;
973 v7k_supported = mono_hwcap_arm_is_v7k;
975 #if defined(__APPLE__)
976 /* iOS is special-cased here because we don't yet
977 have a way to properly detect CPU features on it. */
978 thumb_supported = TRUE;
981 thumb_supported = mono_hwcap_arm_has_thumb;
982 thumb2_supported = mono_hwcap_arm_has_thumb2;
985 /* Format: armv(5|6|7[s])[-thumb[2]] */
986 cpu_arch = g_getenv ("MONO_CPU_ARCH");
988 /* Do this here so it overrides any detection. */
990 if (strncmp (cpu_arch, "armv", 4) == 0) {
991 v5_supported = cpu_arch [4] >= '5';
992 v6_supported = cpu_arch [4] >= '6';
993 v7_supported = cpu_arch [4] >= '7';
994 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
995 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
998 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
999 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
1004 * Cleanup architecture specific code.
1007 mono_arch_cleanup (void)
1012 * This function returns the optimizations supported on this cpu.
1015 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1017 /* no arm-specific optimizations yet */
1023 * This function test for all SIMD functions supported.
1025 * Returns a bitmask corresponding to all supported versions.
1029 mono_arch_cpu_enumerate_simd_versions (void)
1031 /* SIMD is currently unimplemented */
1039 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1041 if (v7s_supported) {
1055 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1057 mono_arch_is_soft_float (void)
1059 return arm_fpu == MONO_ARM_FPU_NONE;
1064 mono_arm_is_hard_float (void)
1066 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1070 is_regsize_var (MonoType *t)
1074 t = mini_get_underlying_type (t);
1081 case MONO_TYPE_FNPTR:
1083 case MONO_TYPE_OBJECT:
1084 case MONO_TYPE_STRING:
1085 case MONO_TYPE_CLASS:
1086 case MONO_TYPE_SZARRAY:
1087 case MONO_TYPE_ARRAY:
1089 case MONO_TYPE_GENERICINST:
1090 if (!mono_type_generic_inst_is_valuetype (t))
1093 case MONO_TYPE_VALUETYPE:
1100 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1105 for (i = 0; i < cfg->num_varinfo; i++) {
1106 MonoInst *ins = cfg->varinfo [i];
1107 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1110 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1113 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1116 /* we can only allocate 32 bit values */
1117 if (is_regsize_var (ins->inst_vtype)) {
1118 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1119 g_assert (i == vmv->idx);
1120 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1128 mono_arch_get_global_int_regs (MonoCompile *cfg)
1132 mono_arch_compute_omit_fp (cfg);
1135 * FIXME: Interface calls might go through a static rgctx trampoline which
1136 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1139 if (cfg->flags & MONO_CFG_HAS_CALLS)
1140 cfg->uses_rgctx_reg = TRUE;
1142 if (cfg->arch.omit_fp)
1143 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1144 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1145 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1146 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1148 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1149 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1151 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1152 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1153 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1154 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1155 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1156 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1162 * mono_arch_regalloc_cost:
1164 * Return the cost, in number of memory references, of the action of
1165 * allocating the variable VMV into a register during global register
1169 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1175 #endif /* #ifndef DISABLE_JIT */
1177 #ifndef __GNUC_PREREQ
1178 #define __GNUC_PREREQ(maj, min) (0)
1182 mono_arch_flush_icache (guint8 *code, gint size)
1184 #if defined(__native_client__)
1185 // For Native Client we don't have to flush i-cache here,
1186 // as it's being done by dyncode interface.
1189 #ifdef MONO_CROSS_COMPILE
1191 sys_icache_invalidate (code, size);
1192 #elif __GNUC_PREREQ(4, 3)
1193 __builtin___clear_cache (code, code + size);
1194 #elif __GNUC_PREREQ(4, 1)
1195 __clear_cache (code, code + size);
1196 #elif defined(PLATFORM_ANDROID)
1197 const int syscall = 0xf0002;
1205 : "r" (code), "r" (code + size), "r" (syscall)
1206 : "r0", "r1", "r7", "r2"
1209 __asm __volatile ("mov r0, %0\n"
1212 "swi 0x9f0002 @ sys_cacheflush"
1214 : "r" (code), "r" (code + size), "r" (0)
1215 : "r0", "r1", "r3" );
1217 #endif /* !__native_client__ */
1222 /* Passed/returned in an ireg */
1224 /* Passed/returned in a pair of iregs */
1226 /* Passed on the stack */
1228 /* First word in r3, second word on the stack */
1230 /* FP value passed in either an ireg or a vfp reg */
1233 RegTypeStructByAddr,
1234 /* gsharedvt argument passed by addr in greg */
1235 RegTypeGSharedVtInReg,
1236 /* gsharedvt argument passed by addr on stack */
1237 RegTypeGSharedVtOnStack,
1243 guint16 vtsize; /* in param area */
1251 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1256 guint32 stack_usage;
1257 /* The index of the vret arg in the argument list for RegTypeStructByAddr */
1267 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1270 if (*gr > ARMREG_R3) {
1272 ainfo->offset = *stack_size;
1273 ainfo->reg = ARMREG_SP; /* in the caller */
1274 ainfo->storage = RegTypeBase;
1277 ainfo->storage = RegTypeGeneral;
1284 split = i8_align == 4;
1289 if (*gr == ARMREG_R3 && split) {
1290 /* first word in r3 and the second on the stack */
1291 ainfo->offset = *stack_size;
1292 ainfo->reg = ARMREG_SP; /* in the caller */
1293 ainfo->storage = RegTypeBaseGen;
1295 } else if (*gr >= ARMREG_R3) {
1296 if (eabi_supported) {
1297 /* darwin aligns longs to 4 byte only */
1298 if (i8_align == 8) {
1303 ainfo->offset = *stack_size;
1304 ainfo->reg = ARMREG_SP; /* in the caller */
1305 ainfo->storage = RegTypeBase;
1308 if (eabi_supported) {
1309 if (i8_align == 8 && ((*gr) & 1))
1312 ainfo->storage = RegTypeIRegPair;
1321 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1324 * If we're calling a function like this:
1326 * void foo(float a, double b, float c)
1328 * We pass a in s0 and b in d1. That leaves us
1329 * with s1 being unused. The armhf ABI recognizes
1330 * this and requires register assignment to then
1331 * use that for the next single-precision arg,
1332 * i.e. c in this example. So float_spare either
1333 * tells us which reg to use for the next single-
1334 * precision arg, or it's -1, meaning use *fpr.
1336 * Note that even though most of the JIT speaks
1337 * double-precision, fpr represents single-
1338 * precision registers.
1340 * See parts 5.5 and 6.1.2 of the AAPCS for how
1344 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1345 ainfo->storage = RegTypeFP;
1349 * If we're passing a double-precision value
1350 * and *fpr is odd (e.g. it's s1, s3, ...)
1351 * we need to use the next even register. So
1352 * we mark the current *fpr as a spare that
1353 * can be used for the next single-precision
1357 *float_spare = *fpr;
1362 * At this point, we have an even register
1363 * so we assign that and move along.
1367 } else if (*float_spare >= 0) {
1369 * We're passing a single-precision value
1370 * and it looks like a spare single-
1371 * precision register is available. Let's
1375 ainfo->reg = *float_spare;
1379 * If we hit this branch, we're passing a
1380 * single-precision value and we can simply
1381 * use the next available register.
1389 * We've exhausted available floating point
1390 * regs, so pass the rest on the stack.
1398 ainfo->offset = *stack_size;
1399 ainfo->reg = ARMREG_SP;
1400 ainfo->storage = RegTypeBase;
1407 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1411 MonoClassField *field;
1412 MonoType *ftype, *prev_ftype = NULL;
1415 klass = mono_class_from_mono_type (t);
1417 while ((field = mono_class_get_fields (klass, &iter))) {
1418 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1420 ftype = mono_field_get_type (field);
1421 ftype = mini_get_underlying_type (ftype);
1423 if (MONO_TYPE_ISSTRUCT (ftype)) {
1424 int nested_nfields, nested_esize;
1426 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1428 if (nested_esize == 4)
1429 ftype = &mono_defaults.single_class->byval_arg;
1431 ftype = &mono_defaults.double_class->byval_arg;
1432 if (prev_ftype && prev_ftype->type != ftype->type)
1435 nfields += nested_nfields;
1437 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1439 if (prev_ftype && prev_ftype->type != ftype->type)
1445 if (nfields == 0 || nfields > 4)
1447 *out_nfields = nfields;
1448 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1453 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1455 guint i, gr, fpr, pstart;
1457 int n = sig->hasthis + sig->param_count;
1461 guint32 stack_size = 0;
1463 gboolean is_pinvoke = sig->pinvoke;
1464 gboolean vtype_retaddr = FALSE;
1467 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1469 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1476 t = mini_get_underlying_type (sig->ret);
1487 case MONO_TYPE_FNPTR:
1488 case MONO_TYPE_CLASS:
1489 case MONO_TYPE_OBJECT:
1490 case MONO_TYPE_SZARRAY:
1491 case MONO_TYPE_ARRAY:
1492 case MONO_TYPE_STRING:
1493 cinfo->ret.storage = RegTypeGeneral;
1494 cinfo->ret.reg = ARMREG_R0;
1498 cinfo->ret.storage = RegTypeIRegPair;
1499 cinfo->ret.reg = ARMREG_R0;
1503 cinfo->ret.storage = RegTypeFP;
1505 if (t->type == MONO_TYPE_R4)
1506 cinfo->ret.size = 4;
1508 cinfo->ret.size = 8;
1510 if (IS_HARD_FLOAT) {
1511 cinfo->ret.reg = ARM_VFP_F0;
1513 cinfo->ret.reg = ARMREG_R0;
1516 case MONO_TYPE_GENERICINST:
1517 if (!mono_type_generic_inst_is_valuetype (t)) {
1518 cinfo->ret.storage = RegTypeGeneral;
1519 cinfo->ret.reg = ARMREG_R0;
1522 if (mini_is_gsharedvt_variable_type (t)) {
1523 cinfo->ret.storage = RegTypeStructByAddr;
1527 case MONO_TYPE_VALUETYPE:
1528 case MONO_TYPE_TYPEDBYREF:
1529 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1530 cinfo->ret.storage = RegTypeHFA;
1532 cinfo->ret.nregs = nfields;
1533 cinfo->ret.esize = esize;
1535 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1536 cinfo->ret.storage = RegTypeStructByVal;
1538 cinfo->ret.storage = RegTypeStructByAddr;
1542 case MONO_TYPE_MVAR:
1543 g_assert (mini_is_gsharedvt_type (t));
1544 cinfo->ret.storage = RegTypeStructByAddr;
1546 case MONO_TYPE_VOID:
1549 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1552 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1557 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1558 * the first argument, allowing 'this' to be always passed in the first arg reg.
1559 * Also do this if the first argument is a reference type, since virtual calls
1560 * are sometimes made using calli without sig->hasthis set, like in the delegate
1563 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1565 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1567 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1571 cinfo->ret.reg = gr;
1573 cinfo->vret_arg_index = 1;
1577 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1580 if (vtype_retaddr) {
1581 cinfo->ret.reg = gr;
1586 DEBUG(printf("params: %d\n", sig->param_count));
1587 for (i = pstart; i < sig->param_count; ++i) {
1588 ArgInfo *ainfo = &cinfo->args [n];
1590 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1591 /* Prevent implicit arguments and sig_cookie from
1592 being passed in registers */
1595 /* Emit the signature cookie just before the implicit arguments */
1596 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1598 DEBUG(printf("param %d: ", i));
1599 if (sig->params [i]->byref) {
1600 DEBUG(printf("byref\n"));
1601 add_general (&gr, &stack_size, ainfo, TRUE);
1605 t = mini_get_underlying_type (sig->params [i]);
1609 cinfo->args [n].size = 1;
1610 add_general (&gr, &stack_size, ainfo, TRUE);
1614 cinfo->args [n].size = 2;
1615 add_general (&gr, &stack_size, ainfo, TRUE);
1619 cinfo->args [n].size = 4;
1620 add_general (&gr, &stack_size, ainfo, TRUE);
1625 case MONO_TYPE_FNPTR:
1626 case MONO_TYPE_CLASS:
1627 case MONO_TYPE_OBJECT:
1628 case MONO_TYPE_STRING:
1629 case MONO_TYPE_SZARRAY:
1630 case MONO_TYPE_ARRAY:
1631 cinfo->args [n].size = sizeof (gpointer);
1632 add_general (&gr, &stack_size, ainfo, TRUE);
1634 case MONO_TYPE_GENERICINST:
1635 if (!mono_type_generic_inst_is_valuetype (t)) {
1636 cinfo->args [n].size = sizeof (gpointer);
1637 add_general (&gr, &stack_size, ainfo, TRUE);
1640 if (mini_is_gsharedvt_variable_type (t)) {
1641 /* gsharedvt arguments are passed by ref */
1642 g_assert (mini_is_gsharedvt_type (t));
1643 add_general (&gr, &stack_size, ainfo, TRUE);
1644 switch (ainfo->storage) {
1645 case RegTypeGeneral:
1646 ainfo->storage = RegTypeGSharedVtInReg;
1649 ainfo->storage = RegTypeGSharedVtOnStack;
1652 g_assert_not_reached ();
1657 case MONO_TYPE_TYPEDBYREF:
1658 case MONO_TYPE_VALUETYPE: {
1661 int nwords, nfields, esize;
1664 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1665 if (fpr + nfields < ARM_VFP_F16) {
1666 ainfo->storage = RegTypeHFA;
1668 ainfo->nregs = nfields;
1669 ainfo->esize = esize;
1677 if (t->type == MONO_TYPE_TYPEDBYREF) {
1678 size = sizeof (MonoTypedRef);
1679 align = sizeof (gpointer);
1681 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1683 size = mono_class_native_size (klass, &align);
1685 size = mini_type_stack_size_full (t, &align, FALSE);
1687 DEBUG(printf ("load %d bytes struct\n", size));
1690 align_size += (sizeof (gpointer) - 1);
1691 align_size &= ~(sizeof (gpointer) - 1);
1692 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1693 ainfo->storage = RegTypeStructByVal;
1694 ainfo->struct_size = size;
1695 /* FIXME: align stack_size if needed */
1696 if (eabi_supported) {
1697 if (align >= 8 && (gr & 1))
1700 if (gr > ARMREG_R3) {
1702 ainfo->vtsize = nwords;
1704 int rest = ARMREG_R3 - gr + 1;
1705 int n_in_regs = rest >= nwords? nwords: rest;
1707 ainfo->size = n_in_regs;
1708 ainfo->vtsize = nwords - n_in_regs;
1711 nwords -= n_in_regs;
1713 if (sig->call_convention == MONO_CALL_VARARG)
1714 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1715 stack_size = ALIGN_TO (stack_size, align);
1716 ainfo->offset = stack_size;
1717 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1718 stack_size += nwords * sizeof (gpointer);
1724 add_general (&gr, &stack_size, ainfo, FALSE);
1730 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1732 add_general (&gr, &stack_size, ainfo, TRUE);
1738 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1740 add_general (&gr, &stack_size, ainfo, FALSE);
1743 case MONO_TYPE_MVAR:
1744 /* gsharedvt arguments are passed by ref */
1745 g_assert (mini_is_gsharedvt_type (t));
1746 add_general (&gr, &stack_size, ainfo, TRUE);
1747 switch (ainfo->storage) {
1748 case RegTypeGeneral:
1749 ainfo->storage = RegTypeGSharedVtInReg;
1752 ainfo->storage = RegTypeGSharedVtOnStack;
1755 g_assert_not_reached ();
1759 g_error ("Can't handle 0x%x", sig->params [i]->type);
1764 /* Handle the case where there are no implicit arguments */
1765 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1766 /* Prevent implicit arguments and sig_cookie from
1767 being passed in registers */
1770 /* Emit the signature cookie just before the implicit arguments */
1771 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1774 /* align stack size to 8 */
1775 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1776 stack_size = (stack_size + 7) & ~7;
1778 cinfo->stack_usage = stack_size;
1784 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1786 MonoType *callee_ret;
1790 c1 = get_call_info (NULL, caller_sig);
1791 c2 = get_call_info (NULL, callee_sig);
1794 * Tail calls with more callee stack usage than the caller cannot be supported, since
1795 * the extra stack space would be left on the stack after the tail call.
1797 res = c1->stack_usage >= c2->stack_usage;
1798 callee_ret = mini_get_underlying_type (callee_sig->ret);
1799 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1800 /* An address on the callee's stack is passed as the first argument */
1803 if (c2->stack_usage > 16 * 4)
1815 debug_omit_fp (void)
1818 return mono_debug_count ();
1825 * mono_arch_compute_omit_fp:
1827 * Determine whenever the frame pointer can be eliminated.
1830 mono_arch_compute_omit_fp (MonoCompile *cfg)
1832 MonoMethodSignature *sig;
1833 MonoMethodHeader *header;
1837 if (cfg->arch.omit_fp_computed)
1840 header = cfg->header;
1842 sig = mono_method_signature (cfg->method);
1844 if (!cfg->arch.cinfo)
1845 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1846 cinfo = cfg->arch.cinfo;
1849 * FIXME: Remove some of the restrictions.
1851 cfg->arch.omit_fp = TRUE;
1852 cfg->arch.omit_fp_computed = TRUE;
1854 if (cfg->disable_omit_fp)
1855 cfg->arch.omit_fp = FALSE;
1856 if (!debug_omit_fp ())
1857 cfg->arch.omit_fp = FALSE;
1859 if (cfg->method->save_lmf)
1860 cfg->arch.omit_fp = FALSE;
1862 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1863 cfg->arch.omit_fp = FALSE;
1864 if (header->num_clauses)
1865 cfg->arch.omit_fp = FALSE;
1866 if (cfg->param_area)
1867 cfg->arch.omit_fp = FALSE;
1868 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1869 cfg->arch.omit_fp = FALSE;
1870 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1871 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1872 cfg->arch.omit_fp = FALSE;
1873 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1874 ArgInfo *ainfo = &cinfo->args [i];
1876 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1878 * The stack offset can only be determined when the frame
1881 cfg->arch.omit_fp = FALSE;
1886 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1887 MonoInst *ins = cfg->varinfo [i];
1890 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1895 * Set var information according to the calling convention. arm version.
1896 * The locals var stuff should most likely be split in another method.
1899 mono_arch_allocate_vars (MonoCompile *cfg)
1901 MonoMethodSignature *sig;
1902 MonoMethodHeader *header;
1905 int i, offset, size, align, curinst;
1910 sig = mono_method_signature (cfg->method);
1912 if (!cfg->arch.cinfo)
1913 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1914 cinfo = cfg->arch.cinfo;
1915 sig_ret = mini_get_underlying_type (sig->ret);
1917 mono_arch_compute_omit_fp (cfg);
1919 if (cfg->arch.omit_fp)
1920 cfg->frame_reg = ARMREG_SP;
1922 cfg->frame_reg = ARMREG_FP;
1924 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1926 /* allow room for the vararg method args: void* and long/double */
1927 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1928 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1930 header = cfg->header;
1932 /* See mono_arch_get_global_int_regs () */
1933 if (cfg->flags & MONO_CFG_HAS_CALLS)
1934 cfg->uses_rgctx_reg = TRUE;
1936 if (cfg->frame_reg != ARMREG_SP)
1937 cfg->used_int_regs |= 1 << cfg->frame_reg;
1939 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1940 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1941 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1945 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1946 if (sig_ret->type != MONO_TYPE_VOID) {
1947 cfg->ret->opcode = OP_REGVAR;
1948 cfg->ret->inst_c0 = ARMREG_R0;
1951 /* local vars are at a positive offset from the stack pointer */
1953 * also note that if the function uses alloca, we use FP
1954 * to point at the local variables.
1956 offset = 0; /* linkage area */
1957 /* align the offset to 16 bytes: not sure this is needed here */
1959 //offset &= ~(8 - 1);
1961 /* add parameter area size for called functions */
1962 offset += cfg->param_area;
1965 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1968 /* allow room to save the return value */
1969 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1972 switch (cinfo->ret.storage) {
1973 case RegTypeStructByVal:
1974 cfg->ret->opcode = OP_REGOFFSET;
1975 cfg->ret->inst_basereg = cfg->frame_reg;
1976 offset += sizeof (gpointer) - 1;
1977 offset &= ~(sizeof (gpointer) - 1);
1978 cfg->ret->inst_offset = - offset;
1979 offset += sizeof(gpointer);
1982 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1983 offset = ALIGN_TO (offset, 8);
1984 cfg->ret->opcode = OP_REGOFFSET;
1985 cfg->ret->inst_basereg = cfg->frame_reg;
1986 cfg->ret->inst_offset = offset;
1990 case RegTypeStructByAddr:
1991 ins = cfg->vret_addr;
1992 offset += sizeof(gpointer) - 1;
1993 offset &= ~(sizeof(gpointer) - 1);
1994 ins->inst_offset = offset;
1995 ins->opcode = OP_REGOFFSET;
1996 ins->inst_basereg = cfg->frame_reg;
1997 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1998 printf ("vret_addr =");
1999 mono_print_ins (cfg->vret_addr);
2001 offset += sizeof(gpointer);
2007 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
2008 if (cfg->arch.seq_point_info_var) {
2011 ins = cfg->arch.seq_point_info_var;
2015 offset += align - 1;
2016 offset &= ~(align - 1);
2017 ins->opcode = OP_REGOFFSET;
2018 ins->inst_basereg = cfg->frame_reg;
2019 ins->inst_offset = offset;
2022 ins = cfg->arch.ss_trigger_page_var;
2025 offset += align - 1;
2026 offset &= ~(align - 1);
2027 ins->opcode = OP_REGOFFSET;
2028 ins->inst_basereg = cfg->frame_reg;
2029 ins->inst_offset = offset;
2033 if (cfg->arch.seq_point_read_var) {
2036 ins = cfg->arch.seq_point_read_var;
2040 offset += align - 1;
2041 offset &= ~(align - 1);
2042 ins->opcode = OP_REGOFFSET;
2043 ins->inst_basereg = cfg->frame_reg;
2044 ins->inst_offset = offset;
2047 ins = cfg->arch.seq_point_ss_method_var;
2050 offset += align - 1;
2051 offset &= ~(align - 1);
2052 ins->opcode = OP_REGOFFSET;
2053 ins->inst_basereg = cfg->frame_reg;
2054 ins->inst_offset = offset;
2057 ins = cfg->arch.seq_point_bp_method_var;
2060 offset += align - 1;
2061 offset &= ~(align - 1);
2062 ins->opcode = OP_REGOFFSET;
2063 ins->inst_basereg = cfg->frame_reg;
2064 ins->inst_offset = offset;
2068 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
2069 /* Allocate a temporary used by the atomic ops */
2073 /* Allocate a local slot to hold the sig cookie address */
2074 offset += align - 1;
2075 offset &= ~(align - 1);
2076 cfg->arch.atomic_tmp_offset = offset;
2079 cfg->arch.atomic_tmp_offset = -1;
2082 cfg->locals_min_stack_offset = offset;
2084 curinst = cfg->locals_start;
2085 for (i = curinst; i < cfg->num_varinfo; ++i) {
2088 ins = cfg->varinfo [i];
2089 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
2092 t = ins->inst_vtype;
2093 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
2096 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
2097 * pinvoke wrappers when they call functions returning structure */
2098 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2099 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
2103 size = mono_type_size (t, &align);
2105 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2106 * since it loads/stores misaligned words, which don't do the right thing.
2108 if (align < 4 && size >= 4)
2110 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2111 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2112 offset += align - 1;
2113 offset &= ~(align - 1);
2114 ins->opcode = OP_REGOFFSET;
2115 ins->inst_offset = offset;
2116 ins->inst_basereg = cfg->frame_reg;
2118 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2121 cfg->locals_max_stack_offset = offset;
2125 ins = cfg->args [curinst];
2126 if (ins->opcode != OP_REGVAR) {
2127 ins->opcode = OP_REGOFFSET;
2128 ins->inst_basereg = cfg->frame_reg;
2129 offset += sizeof (gpointer) - 1;
2130 offset &= ~(sizeof (gpointer) - 1);
2131 ins->inst_offset = offset;
2132 offset += sizeof (gpointer);
2137 if (sig->call_convention == MONO_CALL_VARARG) {
2141 /* Allocate a local slot to hold the sig cookie address */
2142 offset += align - 1;
2143 offset &= ~(align - 1);
2144 cfg->sig_cookie = offset;
2148 for (i = 0; i < sig->param_count; ++i) {
2149 ainfo = cinfo->args + i;
2151 ins = cfg->args [curinst];
2153 switch (ainfo->storage) {
2155 offset = ALIGN_TO (offset, 8);
2156 ins->opcode = OP_REGOFFSET;
2157 ins->inst_basereg = cfg->frame_reg;
2158 /* These arguments are saved to the stack in the prolog */
2159 ins->inst_offset = offset;
2160 if (cfg->verbose_level >= 2)
2161 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2169 if (ins->opcode != OP_REGVAR) {
2170 ins->opcode = OP_REGOFFSET;
2171 ins->inst_basereg = cfg->frame_reg;
2172 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2174 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2175 * since it loads/stores misaligned words, which don't do the right thing.
2177 if (align < 4 && size >= 4)
2179 /* The code in the prolog () stores words when storing vtypes received in a register */
2180 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2182 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2183 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2184 offset += align - 1;
2185 offset &= ~(align - 1);
2186 ins->inst_offset = offset;
2192 /* align the offset to 8 bytes */
2193 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2194 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2199 cfg->stack_offset = offset;
2203 mono_arch_create_vars (MonoCompile *cfg)
2205 MonoMethodSignature *sig;
2209 sig = mono_method_signature (cfg->method);
2211 if (!cfg->arch.cinfo)
2212 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2213 cinfo = cfg->arch.cinfo;
2215 if (IS_HARD_FLOAT) {
2216 for (i = 0; i < 2; i++) {
2217 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2218 inst->flags |= MONO_INST_VOLATILE;
2220 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2224 if (cinfo->ret.storage == RegTypeStructByVal)
2225 cfg->ret_var_is_local = TRUE;
2227 if (cinfo->ret.storage == RegTypeStructByAddr) {
2228 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2229 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2230 printf ("vret_addr = ");
2231 mono_print_ins (cfg->vret_addr);
2235 if (cfg->gen_sdb_seq_points) {
2236 if (cfg->soft_breakpoints) {
2237 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2238 ins->flags |= MONO_INST_VOLATILE;
2239 cfg->arch.seq_point_read_var = ins;
2241 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2242 ins->flags |= MONO_INST_VOLATILE;
2243 cfg->arch.seq_point_ss_method_var = ins;
2245 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2246 ins->flags |= MONO_INST_VOLATILE;
2247 cfg->arch.seq_point_bp_method_var = ins;
2249 g_assert (!cfg->compile_aot);
2250 } else if (cfg->compile_aot) {
2251 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2252 ins->flags |= MONO_INST_VOLATILE;
2253 cfg->arch.seq_point_info_var = ins;
2255 /* Allocate a separate variable for this to save 1 load per seq point */
2256 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2257 ins->flags |= MONO_INST_VOLATILE;
2258 cfg->arch.ss_trigger_page_var = ins;
2264 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2266 MonoMethodSignature *tmp_sig;
2269 if (call->tail_call)
2272 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2275 * mono_ArgIterator_Setup assumes the signature cookie is
2276 * passed first and all the arguments which were before it are
2277 * passed on the stack after the signature. So compensate by
2278 * passing a different signature.
2280 tmp_sig = mono_metadata_signature_dup (call->signature);
2281 tmp_sig->param_count -= call->signature->sentinelpos;
2282 tmp_sig->sentinelpos = 0;
2283 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2285 sig_reg = mono_alloc_ireg (cfg);
2286 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2288 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2293 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2298 LLVMCallInfo *linfo;
2300 n = sig->param_count + sig->hasthis;
2302 cinfo = get_call_info (cfg->mempool, sig);
2304 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2307 * LLVM always uses the native ABI while we use our own ABI, the
2308 * only difference is the handling of vtypes:
2309 * - we only pass/receive them in registers in some cases, and only
2310 * in 1 or 2 integer registers.
2312 switch (cinfo->ret.storage) {
2313 case RegTypeGeneral:
2316 case RegTypeIRegPair:
2318 case RegTypeStructByAddr:
2319 /* Vtype returned using a hidden argument */
2320 linfo->ret.storage = LLVMArgVtypeRetAddr;
2321 linfo->vret_arg_index = cinfo->vret_arg_index;
2324 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2325 cfg->disable_llvm = TRUE;
2329 for (i = 0; i < n; ++i) {
2330 ainfo = cinfo->args + i;
2332 linfo->args [i].storage = LLVMArgNone;
2334 switch (ainfo->storage) {
2335 case RegTypeGeneral:
2336 case RegTypeIRegPair:
2338 case RegTypeBaseGen:
2339 linfo->args [i].storage = LLVMArgInIReg;
2341 case RegTypeStructByVal:
2342 linfo->args [i].storage = LLVMArgAsIArgs;
2343 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2346 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2347 cfg->disable_llvm = TRUE;
2357 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2360 MonoMethodSignature *sig;
2364 sig = call->signature;
2365 n = sig->param_count + sig->hasthis;
2367 cinfo = get_call_info (cfg->mempool, sig);
2369 switch (cinfo->ret.storage) {
2370 case RegTypeStructByVal:
2371 /* The JIT will transform this into a normal call */
2372 call->vret_in_reg = TRUE;
2376 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2377 * the location pointed to by it after call in emit_move_return_value ().
2379 if (!cfg->arch.vret_addr_loc) {
2380 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2381 /* Prevent it from being register allocated or optimized away */
2382 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2385 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2387 case RegTypeStructByAddr: {
2389 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2390 vtarg->sreg1 = call->vret_var->dreg;
2391 vtarg->dreg = mono_alloc_preg (cfg);
2392 MONO_ADD_INS (cfg->cbb, vtarg);
2394 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2401 for (i = 0; i < n; ++i) {
2402 ArgInfo *ainfo = cinfo->args + i;
2405 if (i >= sig->hasthis)
2406 t = sig->params [i - sig->hasthis];
2408 t = &mono_defaults.int_class->byval_arg;
2409 t = mini_get_underlying_type (t);
2411 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2412 /* Emit the signature cookie just before the implicit arguments */
2413 emit_sig_cookie (cfg, call, cinfo);
2416 in = call->args [i];
2418 switch (ainfo->storage) {
2419 case RegTypeGeneral:
2420 case RegTypeIRegPair:
2421 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2422 MONO_INST_NEW (cfg, ins, OP_MOVE);
2423 ins->dreg = mono_alloc_ireg (cfg);
2424 ins->sreg1 = in->dreg + 1;
2425 MONO_ADD_INS (cfg->cbb, ins);
2426 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2428 MONO_INST_NEW (cfg, ins, OP_MOVE);
2429 ins->dreg = mono_alloc_ireg (cfg);
2430 ins->sreg1 = in->dreg + 2;
2431 MONO_ADD_INS (cfg->cbb, ins);
2432 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2433 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2434 if (ainfo->size == 4) {
2435 if (IS_SOFT_FLOAT) {
2436 /* mono_emit_call_args () have already done the r8->r4 conversion */
2437 /* The converted value is in an int vreg */
2438 MONO_INST_NEW (cfg, ins, OP_MOVE);
2439 ins->dreg = mono_alloc_ireg (cfg);
2440 ins->sreg1 = in->dreg;
2441 MONO_ADD_INS (cfg->cbb, ins);
2442 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2446 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2447 creg = mono_alloc_ireg (cfg);
2448 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2449 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2452 if (IS_SOFT_FLOAT) {
2453 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2454 ins->dreg = mono_alloc_ireg (cfg);
2455 ins->sreg1 = in->dreg;
2456 MONO_ADD_INS (cfg->cbb, ins);
2457 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2459 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2460 ins->dreg = mono_alloc_ireg (cfg);
2461 ins->sreg1 = in->dreg;
2462 MONO_ADD_INS (cfg->cbb, ins);
2463 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2467 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2468 creg = mono_alloc_ireg (cfg);
2469 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2470 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2471 creg = mono_alloc_ireg (cfg);
2472 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2473 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2476 cfg->flags |= MONO_CFG_HAS_FPOUT;
2478 MONO_INST_NEW (cfg, ins, OP_MOVE);
2479 ins->dreg = mono_alloc_ireg (cfg);
2480 ins->sreg1 = in->dreg;
2481 MONO_ADD_INS (cfg->cbb, ins);
2483 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2486 case RegTypeStructByAddr:
2489 /* FIXME: where si the data allocated? */
2490 arg->backend.reg3 = ainfo->reg;
2491 call->used_iregs |= 1 << ainfo->reg;
2492 g_assert_not_reached ();
2495 case RegTypeStructByVal:
2496 case RegTypeGSharedVtInReg:
2497 case RegTypeGSharedVtOnStack:
2499 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2500 ins->opcode = OP_OUTARG_VT;
2501 ins->sreg1 = in->dreg;
2502 ins->klass = in->klass;
2503 ins->inst_p0 = call;
2504 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2505 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2506 mono_call_inst_add_outarg_vt (cfg, call, ins);
2507 MONO_ADD_INS (cfg->cbb, ins);
2510 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2511 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2512 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2513 if (t->type == MONO_TYPE_R8) {
2514 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2517 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2519 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2522 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2525 case RegTypeBaseGen:
2526 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2527 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
2528 MONO_INST_NEW (cfg, ins, OP_MOVE);
2529 ins->dreg = mono_alloc_ireg (cfg);
2530 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
2531 MONO_ADD_INS (cfg->cbb, ins);
2532 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2533 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2536 /* This should work for soft-float as well */
2538 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2539 creg = mono_alloc_ireg (cfg);
2540 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2541 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2542 creg = mono_alloc_ireg (cfg);
2543 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2544 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2545 cfg->flags |= MONO_CFG_HAS_FPOUT;
2547 g_assert_not_reached ();
2551 int fdreg = mono_alloc_freg (cfg);
2553 if (ainfo->size == 8) {
2554 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2555 ins->sreg1 = in->dreg;
2557 MONO_ADD_INS (cfg->cbb, ins);
2559 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2564 * Mono's register allocator doesn't speak single-precision registers that
2565 * overlap double-precision registers (i.e. armhf). So we have to work around
2566 * the register allocator and load the value from memory manually.
2568 * So we create a variable for the float argument and an instruction to store
2569 * the argument into the variable. We then store the list of these arguments
2570 * in cfg->float_args. This list is then used by emit_float_args later to
2571 * pass the arguments in the various call opcodes.
2573 * This is not very nice, and we should really try to fix the allocator.
2576 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2578 /* Make sure the instruction isn't seen as pointless and removed.
2580 float_arg->flags |= MONO_INST_VOLATILE;
2582 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2584 /* We use the dreg to look up the instruction later. The hreg is used to
2585 * emit the instruction that loads the value into the FP reg.
2587 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2588 fad->vreg = float_arg->dreg;
2589 fad->hreg = ainfo->reg;
2591 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2594 call->used_iregs |= 1 << ainfo->reg;
2595 cfg->flags |= MONO_CFG_HAS_FPOUT;
2599 g_assert_not_reached ();
2603 /* Handle the case where there are no implicit arguments */
2604 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2605 emit_sig_cookie (cfg, call, cinfo);
2607 call->call_info = cinfo;
2608 call->stack_usage = cinfo->stack_usage;
2612 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2618 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2619 ins->dreg = mono_alloc_freg (cfg);
2620 ins->sreg1 = arg->dreg;
2621 MONO_ADD_INS (cfg->cbb, ins);
2622 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2625 g_assert_not_reached ();
2631 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2633 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2635 ArgInfo *ainfo = ins->inst_p1;
2636 int ovf_size = ainfo->vtsize;
2637 int doffset = ainfo->offset;
2638 int struct_size = ainfo->struct_size;
2639 int i, soffset, dreg, tmpreg;
2641 switch (ainfo->storage) {
2642 case RegTypeGSharedVtInReg:
2644 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2646 case RegTypeGSharedVtOnStack:
2647 /* Pass by addr on stack */
2648 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2651 for (i = 0; i < ainfo->nregs; ++i) {
2652 if (ainfo->esize == 4)
2653 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2655 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2656 load->dreg = mono_alloc_freg (cfg);
2657 load->inst_basereg = src->dreg;
2658 load->inst_offset = i * ainfo->esize;
2659 MONO_ADD_INS (cfg->cbb, load);
2661 if (ainfo->esize == 4) {
2664 /* See RegTypeFP in mono_arch_emit_call () */
2665 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2666 float_arg->flags |= MONO_INST_VOLATILE;
2667 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2669 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2670 fad->vreg = float_arg->dreg;
2671 fad->hreg = ainfo->reg + i;
2673 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2675 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + i, load);
2681 for (i = 0; i < ainfo->size; ++i) {
2682 dreg = mono_alloc_ireg (cfg);
2683 switch (struct_size) {
2685 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2688 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2691 tmpreg = mono_alloc_ireg (cfg);
2692 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2693 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2694 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2695 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2696 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2697 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2698 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2701 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2704 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2705 soffset += sizeof (gpointer);
2706 struct_size -= sizeof (gpointer);
2708 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2710 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2716 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2718 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2721 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2724 if (COMPILE_LLVM (cfg)) {
2725 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2727 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2728 ins->sreg1 = val->dreg + 1;
2729 ins->sreg2 = val->dreg + 2;
2730 MONO_ADD_INS (cfg->cbb, ins);
2735 case MONO_ARM_FPU_NONE:
2736 if (ret->type == MONO_TYPE_R8) {
2739 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2740 ins->dreg = cfg->ret->dreg;
2741 ins->sreg1 = val->dreg;
2742 MONO_ADD_INS (cfg->cbb, ins);
2745 if (ret->type == MONO_TYPE_R4) {
2746 /* Already converted to an int in method_to_ir () */
2747 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2751 case MONO_ARM_FPU_VFP:
2752 case MONO_ARM_FPU_VFP_HARD:
2753 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2756 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2757 ins->dreg = cfg->ret->dreg;
2758 ins->sreg1 = val->dreg;
2759 MONO_ADD_INS (cfg->cbb, ins);
2764 g_assert_not_reached ();
2768 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2771 #endif /* #ifndef DISABLE_JIT */
2774 mono_arch_is_inst_imm (gint64 imm)
2780 MonoMethodSignature *sig;
2783 MonoType **param_types;
2787 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2791 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2794 switch (cinfo->ret.storage) {
2796 case RegTypeGeneral:
2797 case RegTypeIRegPair:
2798 case RegTypeStructByAddr:
2809 for (i = 0; i < cinfo->nargs; ++i) {
2810 ArgInfo *ainfo = &cinfo->args [i];
2813 switch (ainfo->storage) {
2814 case RegTypeGeneral:
2815 case RegTypeIRegPair:
2816 case RegTypeBaseGen:
2819 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2822 case RegTypeStructByVal:
2823 if (ainfo->size == 0)
2824 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2826 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2827 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2835 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2836 for (i = 0; i < sig->param_count; ++i) {
2837 MonoType *t = sig->params [i];
2842 t = mini_get_underlying_type (t);
2865 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2867 ArchDynCallInfo *info;
2871 cinfo = get_call_info (NULL, sig);
2873 if (!dyn_call_supported (cinfo, sig)) {
2878 info = g_new0 (ArchDynCallInfo, 1);
2879 // FIXME: Preprocess the info to speed up start_dyn_call ()
2881 info->cinfo = cinfo;
2882 info->rtype = mini_get_underlying_type (sig->ret);
2883 info->param_types = g_new0 (MonoType*, sig->param_count);
2884 for (i = 0; i < sig->param_count; ++i)
2885 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2887 return (MonoDynCallInfo*)info;
2891 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2893 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2895 g_free (ainfo->cinfo);
2900 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2902 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2903 DynCallArgs *p = (DynCallArgs*)buf;
2904 int arg_index, greg, i, j, pindex;
2905 MonoMethodSignature *sig = dinfo->sig;
2907 g_assert (buf_len >= sizeof (DynCallArgs));
2916 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2917 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2922 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2923 p->regs [greg ++] = (mgreg_t)ret;
2925 for (i = pindex; i < sig->param_count; i++) {
2926 MonoType *t = dinfo->param_types [i];
2927 gpointer *arg = args [arg_index ++];
2928 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2931 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2933 } else if (ainfo->storage == RegTypeBase) {
2934 slot = PARAM_REGS + (ainfo->offset / 4);
2935 } else if (ainfo->storage == RegTypeBaseGen) {
2936 /* slot + 1 is the first stack slot, so the code below will work */
2939 g_assert_not_reached ();
2943 p->regs [slot] = (mgreg_t)*arg;
2948 case MONO_TYPE_STRING:
2949 case MONO_TYPE_CLASS:
2950 case MONO_TYPE_ARRAY:
2951 case MONO_TYPE_SZARRAY:
2952 case MONO_TYPE_OBJECT:
2956 p->regs [slot] = (mgreg_t)*arg;
2959 p->regs [slot] = *(guint8*)arg;
2962 p->regs [slot] = *(gint8*)arg;
2965 p->regs [slot] = *(gint16*)arg;
2968 p->regs [slot] = *(guint16*)arg;
2971 p->regs [slot] = *(gint32*)arg;
2974 p->regs [slot] = *(guint32*)arg;
2978 p->regs [slot ++] = (mgreg_t)arg [0];
2979 p->regs [slot] = (mgreg_t)arg [1];
2982 p->regs [slot] = *(mgreg_t*)arg;
2985 p->regs [slot ++] = (mgreg_t)arg [0];
2986 p->regs [slot] = (mgreg_t)arg [1];
2988 case MONO_TYPE_GENERICINST:
2989 if (MONO_TYPE_IS_REFERENCE (t)) {
2990 p->regs [slot] = (mgreg_t)*arg;
2993 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2994 MonoClass *klass = mono_class_from_mono_type (t);
2995 guint8 *nullable_buf;
2998 size = mono_class_value_size (klass, NULL);
2999 nullable_buf = g_alloca (size);
3000 g_assert (nullable_buf);
3002 /* The argument pointed to by arg is either a boxed vtype or null */
3003 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
3005 arg = (gpointer*)nullable_buf;
3011 case MONO_TYPE_VALUETYPE:
3012 g_assert (ainfo->storage == RegTypeStructByVal);
3014 if (ainfo->size == 0)
3015 slot = PARAM_REGS + (ainfo->offset / 4);
3019 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
3020 p->regs [slot ++] = ((mgreg_t*)arg) [j];
3023 g_assert_not_reached ();
3029 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
3031 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
3032 MonoType *ptype = ainfo->rtype;
3033 guint8 *ret = ((DynCallArgs*)buf)->ret;
3034 mgreg_t res = ((DynCallArgs*)buf)->res;
3035 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
3037 switch (ptype->type) {
3038 case MONO_TYPE_VOID:
3039 *(gpointer*)ret = NULL;
3041 case MONO_TYPE_STRING:
3042 case MONO_TYPE_CLASS:
3043 case MONO_TYPE_ARRAY:
3044 case MONO_TYPE_SZARRAY:
3045 case MONO_TYPE_OBJECT:
3049 *(gpointer*)ret = (gpointer)res;
3055 *(guint8*)ret = res;
3058 *(gint16*)ret = res;
3061 *(guint16*)ret = res;
3064 *(gint32*)ret = res;
3067 *(guint32*)ret = res;
3071 /* This handles endianness as well */
3072 ((gint32*)ret) [0] = res;
3073 ((gint32*)ret) [1] = res2;
3075 case MONO_TYPE_GENERICINST:
3076 if (MONO_TYPE_IS_REFERENCE (ptype)) {
3077 *(gpointer*)ret = (gpointer)res;
3082 case MONO_TYPE_VALUETYPE:
3083 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
3088 *(float*)ret = *(float*)&res;
3090 case MONO_TYPE_R8: {
3097 *(double*)ret = *(double*)®s;
3101 g_assert_not_reached ();
3108 * Allow tracing to work with this interface (with an optional argument)
3112 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3116 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3117 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3118 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3119 code = emit_call_reg (code, ARMREG_R2);
3133 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3136 int save_mode = SAVE_NONE;
3138 MonoMethod *method = cfg->method;
3139 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3140 int rtype = ret_type->type;
3141 int save_offset = cfg->param_area;
3145 offset = code - cfg->native_code;
3146 /* we need about 16 instructions */
3147 if (offset > (cfg->code_size - 16 * 4)) {
3148 cfg->code_size *= 2;
3149 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3150 code = cfg->native_code + offset;
3153 case MONO_TYPE_VOID:
3154 /* special case string .ctor icall */
3155 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3156 save_mode = SAVE_ONE;
3158 save_mode = SAVE_NONE;
3162 save_mode = SAVE_TWO;
3166 save_mode = SAVE_ONE_FP;
3168 save_mode = SAVE_ONE;
3172 save_mode = SAVE_TWO_FP;
3174 save_mode = SAVE_TWO;
3176 case MONO_TYPE_GENERICINST:
3177 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3178 save_mode = SAVE_ONE;
3182 case MONO_TYPE_VALUETYPE:
3183 save_mode = SAVE_STRUCT;
3186 save_mode = SAVE_ONE;
3190 switch (save_mode) {
3192 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3193 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3194 if (enable_arguments) {
3195 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3196 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3200 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3201 if (enable_arguments) {
3202 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3206 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3207 if (enable_arguments) {
3208 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3212 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3213 if (enable_arguments) {
3214 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3218 if (enable_arguments) {
3219 /* FIXME: get the actual address */
3220 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3228 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3229 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3230 code = emit_call_reg (code, ARMREG_IP);
3232 switch (save_mode) {
3234 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3235 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3238 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3241 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3244 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3255 * The immediate field for cond branches is big enough for all reasonable methods
3257 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3258 if (0 && ins->inst_true_bb->native_offset) { \
3259 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3261 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3262 ARM_B_COND (code, (condcode), 0); \
3265 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3267 /* emit an exception if condition is fail
3269 * We assign the extra code used to throw the implicit exceptions
3270 * to cfg->bb_exit as far as the big branch handling is concerned
3272 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3274 mono_add_patch_info (cfg, code - cfg->native_code, \
3275 MONO_PATCH_INFO_EXC, exc_name); \
3276 ARM_BL_COND (code, (condcode), 0); \
3279 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3282 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3287 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3291 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3292 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3294 switch (ins->opcode) {
3297 /* Already done by an arch-independent pass */
3299 case OP_LOAD_MEMBASE:
3300 case OP_LOADI4_MEMBASE:
3302 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3303 * OP_LOAD_MEMBASE offset(basereg), reg
3305 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3306 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3307 ins->inst_basereg == last_ins->inst_destbasereg &&
3308 ins->inst_offset == last_ins->inst_offset) {
3309 if (ins->dreg == last_ins->sreg1) {
3310 MONO_DELETE_INS (bb, ins);
3313 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3314 ins->opcode = OP_MOVE;
3315 ins->sreg1 = last_ins->sreg1;
3319 * Note: reg1 must be different from the basereg in the second load
3320 * OP_LOAD_MEMBASE offset(basereg), reg1
3321 * OP_LOAD_MEMBASE offset(basereg), reg2
3323 * OP_LOAD_MEMBASE offset(basereg), reg1
3324 * OP_MOVE reg1, reg2
3326 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3327 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3328 ins->inst_basereg != last_ins->dreg &&
3329 ins->inst_basereg == last_ins->inst_basereg &&
3330 ins->inst_offset == last_ins->inst_offset) {
3332 if (ins->dreg == last_ins->dreg) {
3333 MONO_DELETE_INS (bb, ins);
3336 ins->opcode = OP_MOVE;
3337 ins->sreg1 = last_ins->dreg;
3340 //g_assert_not_reached ();
3344 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3345 * OP_LOAD_MEMBASE offset(basereg), reg
3347 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3348 * OP_ICONST reg, imm
3350 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3351 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3352 ins->inst_basereg == last_ins->inst_destbasereg &&
3353 ins->inst_offset == last_ins->inst_offset) {
3354 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3355 ins->opcode = OP_ICONST;
3356 ins->inst_c0 = last_ins->inst_imm;
3357 g_assert_not_reached (); // check this rule
3361 case OP_LOADU1_MEMBASE:
3362 case OP_LOADI1_MEMBASE:
3363 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3364 ins->inst_basereg == last_ins->inst_destbasereg &&
3365 ins->inst_offset == last_ins->inst_offset) {
3366 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3367 ins->sreg1 = last_ins->sreg1;
3370 case OP_LOADU2_MEMBASE:
3371 case OP_LOADI2_MEMBASE:
3372 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3373 ins->inst_basereg == last_ins->inst_destbasereg &&
3374 ins->inst_offset == last_ins->inst_offset) {
3375 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3376 ins->sreg1 = last_ins->sreg1;
3380 ins->opcode = OP_MOVE;
3384 if (ins->dreg == ins->sreg1) {
3385 MONO_DELETE_INS (bb, ins);
3389 * OP_MOVE sreg, dreg
3390 * OP_MOVE dreg, sreg
3392 if (last_ins && last_ins->opcode == OP_MOVE &&
3393 ins->sreg1 == last_ins->dreg &&
3394 ins->dreg == last_ins->sreg1) {
3395 MONO_DELETE_INS (bb, ins);
3404 * the branch_cc_table should maintain the order of these
3418 branch_cc_table [] = {
3432 #define ADD_NEW_INS(cfg,dest,op) do { \
3433 MONO_INST_NEW ((cfg), (dest), (op)); \
3434 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3438 map_to_reg_reg_op (int op)
3447 case OP_COMPARE_IMM:
3449 case OP_ICOMPARE_IMM:
3463 case OP_LOAD_MEMBASE:
3464 return OP_LOAD_MEMINDEX;
3465 case OP_LOADI4_MEMBASE:
3466 return OP_LOADI4_MEMINDEX;
3467 case OP_LOADU4_MEMBASE:
3468 return OP_LOADU4_MEMINDEX;
3469 case OP_LOADU1_MEMBASE:
3470 return OP_LOADU1_MEMINDEX;
3471 case OP_LOADI2_MEMBASE:
3472 return OP_LOADI2_MEMINDEX;
3473 case OP_LOADU2_MEMBASE:
3474 return OP_LOADU2_MEMINDEX;
3475 case OP_LOADI1_MEMBASE:
3476 return OP_LOADI1_MEMINDEX;
3477 case OP_STOREI1_MEMBASE_REG:
3478 return OP_STOREI1_MEMINDEX;
3479 case OP_STOREI2_MEMBASE_REG:
3480 return OP_STOREI2_MEMINDEX;
3481 case OP_STOREI4_MEMBASE_REG:
3482 return OP_STOREI4_MEMINDEX;
3483 case OP_STORE_MEMBASE_REG:
3484 return OP_STORE_MEMINDEX;
3485 case OP_STORER4_MEMBASE_REG:
3486 return OP_STORER4_MEMINDEX;
3487 case OP_STORER8_MEMBASE_REG:
3488 return OP_STORER8_MEMINDEX;
3489 case OP_STORE_MEMBASE_IMM:
3490 return OP_STORE_MEMBASE_REG;
3491 case OP_STOREI1_MEMBASE_IMM:
3492 return OP_STOREI1_MEMBASE_REG;
3493 case OP_STOREI2_MEMBASE_IMM:
3494 return OP_STOREI2_MEMBASE_REG;
3495 case OP_STOREI4_MEMBASE_IMM:
3496 return OP_STOREI4_MEMBASE_REG;
3498 g_assert_not_reached ();
3502 * Remove from the instruction list the instructions that can't be
3503 * represented with very simple instructions with no register
3507 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3509 MonoInst *ins, *temp, *last_ins = NULL;
3510 int rot_amount, imm8, low_imm;
3512 MONO_BB_FOR_EACH_INS (bb, ins) {
3514 switch (ins->opcode) {
3518 case OP_COMPARE_IMM:
3519 case OP_ICOMPARE_IMM:
3533 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3534 ADD_NEW_INS (cfg, temp, OP_ICONST);
3535 temp->inst_c0 = ins->inst_imm;
3536 temp->dreg = mono_alloc_ireg (cfg);
3537 ins->sreg2 = temp->dreg;
3538 ins->opcode = mono_op_imm_to_op (ins->opcode);
3540 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3546 if (ins->inst_imm == 1) {
3547 ins->opcode = OP_MOVE;
3550 if (ins->inst_imm == 0) {
3551 ins->opcode = OP_ICONST;
3555 imm8 = mono_is_power_of_two (ins->inst_imm);
3557 ins->opcode = OP_SHL_IMM;
3558 ins->inst_imm = imm8;
3561 ADD_NEW_INS (cfg, temp, OP_ICONST);
3562 temp->inst_c0 = ins->inst_imm;
3563 temp->dreg = mono_alloc_ireg (cfg);
3564 ins->sreg2 = temp->dreg;
3565 ins->opcode = OP_IMUL;
3571 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3572 /* ARM sets the C flag to 1 if there was _no_ overflow */
3573 ins->next->opcode = OP_COND_EXC_NC;
3576 case OP_IDIV_UN_IMM:
3578 case OP_IREM_UN_IMM:
3579 ADD_NEW_INS (cfg, temp, OP_ICONST);
3580 temp->inst_c0 = ins->inst_imm;
3581 temp->dreg = mono_alloc_ireg (cfg);
3582 ins->sreg2 = temp->dreg;
3583 ins->opcode = mono_op_imm_to_op (ins->opcode);
3585 case OP_LOCALLOC_IMM:
3586 ADD_NEW_INS (cfg, temp, OP_ICONST);
3587 temp->inst_c0 = ins->inst_imm;
3588 temp->dreg = mono_alloc_ireg (cfg);
3589 ins->sreg1 = temp->dreg;
3590 ins->opcode = OP_LOCALLOC;
3592 case OP_LOAD_MEMBASE:
3593 case OP_LOADI4_MEMBASE:
3594 case OP_LOADU4_MEMBASE:
3595 case OP_LOADU1_MEMBASE:
3596 /* we can do two things: load the immed in a register
3597 * and use an indexed load, or see if the immed can be
3598 * represented as an ad_imm + a load with a smaller offset
3599 * that fits. We just do the first for now, optimize later.
3601 if (arm_is_imm12 (ins->inst_offset))
3603 ADD_NEW_INS (cfg, temp, OP_ICONST);
3604 temp->inst_c0 = ins->inst_offset;
3605 temp->dreg = mono_alloc_ireg (cfg);
3606 ins->sreg2 = temp->dreg;
3607 ins->opcode = map_to_reg_reg_op (ins->opcode);
3609 case OP_LOADI2_MEMBASE:
3610 case OP_LOADU2_MEMBASE:
3611 case OP_LOADI1_MEMBASE:
3612 if (arm_is_imm8 (ins->inst_offset))
3614 ADD_NEW_INS (cfg, temp, OP_ICONST);
3615 temp->inst_c0 = ins->inst_offset;
3616 temp->dreg = mono_alloc_ireg (cfg);
3617 ins->sreg2 = temp->dreg;
3618 ins->opcode = map_to_reg_reg_op (ins->opcode);
3620 case OP_LOADR4_MEMBASE:
3621 case OP_LOADR8_MEMBASE:
3622 if (arm_is_fpimm8 (ins->inst_offset))
3624 low_imm = ins->inst_offset & 0x1ff;
3625 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3626 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3627 temp->inst_imm = ins->inst_offset & ~0x1ff;
3628 temp->sreg1 = ins->inst_basereg;
3629 temp->dreg = mono_alloc_ireg (cfg);
3630 ins->inst_basereg = temp->dreg;
3631 ins->inst_offset = low_imm;
3635 ADD_NEW_INS (cfg, temp, OP_ICONST);
3636 temp->inst_c0 = ins->inst_offset;
3637 temp->dreg = mono_alloc_ireg (cfg);
3639 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3640 add_ins->sreg1 = ins->inst_basereg;
3641 add_ins->sreg2 = temp->dreg;
3642 add_ins->dreg = mono_alloc_ireg (cfg);
3644 ins->inst_basereg = add_ins->dreg;
3645 ins->inst_offset = 0;
3648 case OP_STORE_MEMBASE_REG:
3649 case OP_STOREI4_MEMBASE_REG:
3650 case OP_STOREI1_MEMBASE_REG:
3651 if (arm_is_imm12 (ins->inst_offset))
3653 ADD_NEW_INS (cfg, temp, OP_ICONST);
3654 temp->inst_c0 = ins->inst_offset;
3655 temp->dreg = mono_alloc_ireg (cfg);
3656 ins->sreg2 = temp->dreg;
3657 ins->opcode = map_to_reg_reg_op (ins->opcode);
3659 case OP_STOREI2_MEMBASE_REG:
3660 if (arm_is_imm8 (ins->inst_offset))
3662 ADD_NEW_INS (cfg, temp, OP_ICONST);
3663 temp->inst_c0 = ins->inst_offset;
3664 temp->dreg = mono_alloc_ireg (cfg);
3665 ins->sreg2 = temp->dreg;
3666 ins->opcode = map_to_reg_reg_op (ins->opcode);
3668 case OP_STORER4_MEMBASE_REG:
3669 case OP_STORER8_MEMBASE_REG:
3670 if (arm_is_fpimm8 (ins->inst_offset))
3672 low_imm = ins->inst_offset & 0x1ff;
3673 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3674 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3675 temp->inst_imm = ins->inst_offset & ~0x1ff;
3676 temp->sreg1 = ins->inst_destbasereg;
3677 temp->dreg = mono_alloc_ireg (cfg);
3678 ins->inst_destbasereg = temp->dreg;
3679 ins->inst_offset = low_imm;
3683 ADD_NEW_INS (cfg, temp, OP_ICONST);
3684 temp->inst_c0 = ins->inst_offset;
3685 temp->dreg = mono_alloc_ireg (cfg);
3687 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3688 add_ins->sreg1 = ins->inst_destbasereg;
3689 add_ins->sreg2 = temp->dreg;
3690 add_ins->dreg = mono_alloc_ireg (cfg);
3692 ins->inst_destbasereg = add_ins->dreg;
3693 ins->inst_offset = 0;
3696 case OP_STORE_MEMBASE_IMM:
3697 case OP_STOREI1_MEMBASE_IMM:
3698 case OP_STOREI2_MEMBASE_IMM:
3699 case OP_STOREI4_MEMBASE_IMM:
3700 ADD_NEW_INS (cfg, temp, OP_ICONST);
3701 temp->inst_c0 = ins->inst_imm;
3702 temp->dreg = mono_alloc_ireg (cfg);
3703 ins->sreg1 = temp->dreg;
3704 ins->opcode = map_to_reg_reg_op (ins->opcode);
3706 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3709 gboolean swap = FALSE;
3713 /* Optimized away */
3718 /* Some fp compares require swapped operands */
3719 switch (ins->next->opcode) {
3721 ins->next->opcode = OP_FBLT;
3725 ins->next->opcode = OP_FBLT_UN;
3729 ins->next->opcode = OP_FBGE;
3733 ins->next->opcode = OP_FBGE_UN;
3741 ins->sreg1 = ins->sreg2;
3750 bb->last_ins = last_ins;
3751 bb->max_vreg = cfg->next_vreg;
3755 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3759 if (long_ins->opcode == OP_LNEG) {
3761 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3762 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3768 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3770 /* sreg is a float, dreg is an integer reg */
3772 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3774 ARM_TOSIZD (code, vfp_scratch1, sreg);
3776 ARM_TOUIZD (code, vfp_scratch1, sreg);
3777 ARM_FMRS (code, dreg, vfp_scratch1);
3778 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3782 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3783 else if (size == 2) {
3784 ARM_SHL_IMM (code, dreg, dreg, 16);
3785 ARM_SHR_IMM (code, dreg, dreg, 16);
3789 ARM_SHL_IMM (code, dreg, dreg, 24);
3790 ARM_SAR_IMM (code, dreg, dreg, 24);
3791 } else if (size == 2) {
3792 ARM_SHL_IMM (code, dreg, dreg, 16);
3793 ARM_SAR_IMM (code, dreg, dreg, 16);
3800 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3802 /* sreg is a float, dreg is an integer reg */
3804 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3806 ARM_TOSIZS (code, vfp_scratch1, sreg);
3808 ARM_TOUIZS (code, vfp_scratch1, sreg);
3809 ARM_FMRS (code, dreg, vfp_scratch1);
3810 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3814 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3815 else if (size == 2) {
3816 ARM_SHL_IMM (code, dreg, dreg, 16);
3817 ARM_SHR_IMM (code, dreg, dreg, 16);
3821 ARM_SHL_IMM (code, dreg, dreg, 24);
3822 ARM_SAR_IMM (code, dreg, dreg, 24);
3823 } else if (size == 2) {
3824 ARM_SHL_IMM (code, dreg, dreg, 16);
3825 ARM_SAR_IMM (code, dreg, dreg, 16);
3831 #endif /* #ifndef DISABLE_JIT */
3833 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3836 emit_thunk (guint8 *code, gconstpointer target)
3840 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3841 if (thumb_supported)
3842 ARM_BX (code, ARMREG_IP);
3844 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3845 *(guint32*)code = (guint32)target;
3847 mono_arch_flush_icache (p, code - p);
3851 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3853 MonoJitInfo *ji = NULL;
3854 MonoThunkJitInfo *info;
3857 guint8 *orig_target;
3858 guint8 *target_thunk;
3861 domain = mono_domain_get ();
3865 * This can be called multiple times during JITting,
3866 * save the current position in cfg->arch to avoid
3867 * doing a O(n^2) search.
3869 if (!cfg->arch.thunks) {
3870 cfg->arch.thunks = cfg->thunks;
3871 cfg->arch.thunks_size = cfg->thunk_area;
3873 thunks = cfg->arch.thunks;
3874 thunks_size = cfg->arch.thunks_size;
3876 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3877 g_assert_not_reached ();
3880 g_assert (*(guint32*)thunks == 0);
3881 emit_thunk (thunks, target);
3882 arm_patch (code, thunks);
3884 cfg->arch.thunks += THUNK_SIZE;
3885 cfg->arch.thunks_size -= THUNK_SIZE;
3887 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3889 info = mono_jit_info_get_thunk_info (ji);
3892 thunks = (guint8*)ji->code_start + info->thunks_offset;
3893 thunks_size = info->thunks_size;
3895 orig_target = mono_arch_get_call_target (code + 4);
3897 mono_mini_arch_lock ();
3899 target_thunk = NULL;
3900 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3901 /* The call already points to a thunk, because of trampolines etc. */
3902 target_thunk = orig_target;
3904 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3905 if (((guint32*)p) [0] == 0) {
3909 } else if (((guint32*)p) [2] == (guint32)target) {
3910 /* Thunk already points to target */
3917 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
3919 if (!target_thunk) {
3920 mono_mini_arch_unlock ();
3921 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3922 g_assert_not_reached ();
3925 emit_thunk (target_thunk, target);
3926 arm_patch (code, target_thunk);
3927 mono_arch_flush_icache (code, 4);
3929 mono_mini_arch_unlock ();
3934 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3936 guint32 *code32 = (void*)code;
3937 guint32 ins = *code32;
3938 guint32 prim = (ins >> 25) & 7;
3939 guint32 tval = GPOINTER_TO_UINT (target);
3941 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3942 if (prim == 5) { /* 101b */
3943 /* the diff starts 8 bytes from the branch opcode */
3944 gint diff = target - code - 8;
3946 gint tmask = 0xffffffff;
3947 if (tval & 1) { /* entering thumb mode */
3948 diff = target - 1 - code - 8;
3949 g_assert (thumb_supported);
3950 tbits = 0xf << 28; /* bl->blx bit pattern */
3951 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3952 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3956 tmask = ~(1 << 24); /* clear the link bit */
3957 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3962 if (diff <= 33554431) {
3964 ins = (ins & 0xff000000) | diff;
3966 *code32 = ins | tbits;
3970 /* diff between 0 and -33554432 */
3971 if (diff >= -33554432) {
3973 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3975 *code32 = ins | tbits;
3980 handle_thunk (cfg, domain, code, target);
3984 #ifdef USE_JUMP_TABLES
3986 gpointer *jte = mono_jumptable_get_entry (code);
3988 jte [0] = (gpointer) target;
3992 * The alternative call sequences looks like this:
3994 * ldr ip, [pc] // loads the address constant
3995 * b 1f // jumps around the constant
3996 * address constant embedded in the code
4001 * There are two cases for patching:
4002 * a) at the end of method emission: in this case code points to the start
4003 * of the call sequence
4004 * b) during runtime patching of the call site: in this case code points
4005 * to the mov pc, ip instruction
4007 * We have to handle also the thunk jump code sequence:
4011 * address constant // execution never reaches here
4013 if ((ins & 0x0ffffff0) == 0x12fff10) {
4014 /* Branch and exchange: the address is constructed in a reg
4015 * We can patch BX when the code sequence is the following:
4016 * ldr ip, [pc, #0] ; 0x8
4023 guint8 *emit = (guint8*)ccode;
4024 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4026 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4027 ARM_BX (emit, ARMREG_IP);
4029 /*patching from magic trampoline*/
4030 if (ins == ccode [3]) {
4031 g_assert (code32 [-4] == ccode [0]);
4032 g_assert (code32 [-3] == ccode [1]);
4033 g_assert (code32 [-1] == ccode [2]);
4034 code32 [-2] = (guint32)target;
4037 /*patching from JIT*/
4038 if (ins == ccode [0]) {
4039 g_assert (code32 [1] == ccode [1]);
4040 g_assert (code32 [3] == ccode [2]);
4041 g_assert (code32 [4] == ccode [3]);
4042 code32 [2] = (guint32)target;
4045 g_assert_not_reached ();
4046 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
4054 guint8 *emit = (guint8*)ccode;
4055 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4057 ARM_BLX_REG (emit, ARMREG_IP);
4059 g_assert (code32 [-3] == ccode [0]);
4060 g_assert (code32 [-2] == ccode [1]);
4061 g_assert (code32 [0] == ccode [2]);
4063 code32 [-1] = (guint32)target;
4066 guint32 *tmp = ccode;
4067 guint8 *emit = (guint8*)tmp;
4068 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4069 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4070 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
4071 ARM_BX (emit, ARMREG_IP);
4072 if (ins == ccode [2]) {
4073 g_assert_not_reached (); // should be -2 ...
4074 code32 [-1] = (guint32)target;
4077 if (ins == ccode [0]) {
4078 /* handles both thunk jump code and the far call sequence */
4079 code32 [2] = (guint32)target;
4082 g_assert_not_reached ();
4084 // g_print ("patched with 0x%08x\n", ins);
4089 arm_patch (guchar *code, const guchar *target)
4091 arm_patch_general (NULL, NULL, code, target);
4095 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4096 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4097 * to be used with the emit macros.
4098 * Return -1 otherwise.
4101 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4104 for (i = 0; i < 31; i+= 2) {
4105 res = (val << (32 - i)) | (val >> i);
4108 *rot_amount = i? 32 - i: 0;
4115 * Emits in code a sequence of instructions that load the value 'val'
4116 * into the dreg register. Uses at most 4 instructions.
4119 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4121 int imm8, rot_amount;
4123 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4124 /* skip the constant pool */
4130 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4131 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4132 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4133 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4136 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4138 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4142 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4144 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4146 if (val & 0xFF0000) {
4147 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4149 if (val & 0xFF000000) {
4150 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4152 } else if (val & 0xFF00) {
4153 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4154 if (val & 0xFF0000) {
4155 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4157 if (val & 0xFF000000) {
4158 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4160 } else if (val & 0xFF0000) {
4161 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4162 if (val & 0xFF000000) {
4163 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4166 //g_assert_not_reached ();
4172 mono_arm_thumb_supported (void)
4174 return thumb_supported;
4180 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4185 call = (MonoCallInst*)ins;
4186 cinfo = call->call_info;
4188 switch (cinfo->ret.storage) {
4190 MonoInst *loc = cfg->arch.vret_addr_loc;
4193 /* Load the destination address */
4194 g_assert (loc && loc->opcode == OP_REGOFFSET);
4196 if (arm_is_imm12 (loc->inst_offset)) {
4197 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4199 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4200 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4202 for (i = 0; i < cinfo->ret.nregs; ++i) {
4203 if (cinfo->ret.esize == 4)
4204 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4206 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4214 switch (ins->opcode) {
4217 case OP_FCALL_MEMBASE:
4219 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4220 if (sig_ret->type == MONO_TYPE_R4) {
4221 if (IS_HARD_FLOAT) {
4222 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4224 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4225 ARM_CVTS (code, ins->dreg, ins->dreg);
4228 if (IS_HARD_FLOAT) {
4229 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4231 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4238 case OP_RCALL_MEMBASE: {
4243 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4244 g_assert (sig_ret->type == MONO_TYPE_R4);
4245 if (IS_HARD_FLOAT) {
4246 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4248 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4249 ARM_CPYS (code, ins->dreg, ins->dreg);
4261 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4266 guint8 *code = cfg->native_code + cfg->code_len;
4267 MonoInst *last_ins = NULL;
4268 guint last_offset = 0;
4270 int imm8, rot_amount;
4272 /* we don't align basic blocks of loops on arm */
4274 if (cfg->verbose_level > 2)
4275 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4277 cpos = bb->max_offset;
4279 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4280 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4281 //g_assert (!mono_compile_aot);
4284 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4285 /* this is not thread save, but good enough */
4286 /* fixme: howto handle overflows? */
4287 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4290 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4291 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4292 (gpointer)"mono_break");
4293 code = emit_call_seq (cfg, code);
4296 MONO_BB_FOR_EACH_INS (bb, ins) {
4297 offset = code - cfg->native_code;
4299 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4301 if (offset > (cfg->code_size - max_len - 16)) {
4302 cfg->code_size *= 2;
4303 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4304 code = cfg->native_code + offset;
4306 // if (ins->cil_code)
4307 // g_print ("cil code\n");
4308 mono_debug_record_line_number (cfg, ins, offset);
4310 switch (ins->opcode) {
4311 case OP_MEMORY_BARRIER:
4313 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4314 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4318 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4320 case OP_TLS_GET_REG:
4321 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4324 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4326 case OP_TLS_SET_REG:
4327 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4329 case OP_ATOMIC_EXCHANGE_I4:
4330 case OP_ATOMIC_CAS_I4:
4331 case OP_ATOMIC_ADD_I4: {
4335 g_assert (v7_supported);
4338 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4340 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4342 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4346 g_assert (cfg->arch.atomic_tmp_offset != -1);
4347 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4349 switch (ins->opcode) {
4350 case OP_ATOMIC_EXCHANGE_I4:
4352 ARM_DMB (code, ARM_DMB_SY);
4353 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4354 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4355 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4357 ARM_B_COND (code, ARMCOND_NE, 0);
4358 arm_patch (buf [1], buf [0]);
4360 case OP_ATOMIC_CAS_I4:
4361 ARM_DMB (code, ARM_DMB_SY);
4363 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4364 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4366 ARM_B_COND (code, ARMCOND_NE, 0);
4367 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4368 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4370 ARM_B_COND (code, ARMCOND_NE, 0);
4371 arm_patch (buf [2], buf [0]);
4372 arm_patch (buf [1], code);
4374 case OP_ATOMIC_ADD_I4:
4376 ARM_DMB (code, ARM_DMB_SY);
4377 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4378 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4379 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4380 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4382 ARM_B_COND (code, ARMCOND_NE, 0);
4383 arm_patch (buf [1], buf [0]);
4386 g_assert_not_reached ();
4389 ARM_DMB (code, ARM_DMB_SY);
4390 if (tmpreg != ins->dreg)
4391 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4392 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4395 case OP_ATOMIC_LOAD_I1:
4396 case OP_ATOMIC_LOAD_U1:
4397 case OP_ATOMIC_LOAD_I2:
4398 case OP_ATOMIC_LOAD_U2:
4399 case OP_ATOMIC_LOAD_I4:
4400 case OP_ATOMIC_LOAD_U4:
4401 case OP_ATOMIC_LOAD_R4:
4402 case OP_ATOMIC_LOAD_R8: {
4403 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4404 ARM_DMB (code, ARM_DMB_SY);
4406 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4408 switch (ins->opcode) {
4409 case OP_ATOMIC_LOAD_I1:
4410 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4412 case OP_ATOMIC_LOAD_U1:
4413 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4415 case OP_ATOMIC_LOAD_I2:
4416 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4418 case OP_ATOMIC_LOAD_U2:
4419 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4421 case OP_ATOMIC_LOAD_I4:
4422 case OP_ATOMIC_LOAD_U4:
4423 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4425 case OP_ATOMIC_LOAD_R4:
4427 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4428 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4430 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4431 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4432 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4433 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4434 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4437 case OP_ATOMIC_LOAD_R8:
4438 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4439 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4443 ARM_DMB (code, ARM_DMB_SY);
4446 case OP_ATOMIC_STORE_I1:
4447 case OP_ATOMIC_STORE_U1:
4448 case OP_ATOMIC_STORE_I2:
4449 case OP_ATOMIC_STORE_U2:
4450 case OP_ATOMIC_STORE_I4:
4451 case OP_ATOMIC_STORE_U4:
4452 case OP_ATOMIC_STORE_R4:
4453 case OP_ATOMIC_STORE_R8: {
4454 ARM_DMB (code, ARM_DMB_SY);
4456 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4458 switch (ins->opcode) {
4459 case OP_ATOMIC_STORE_I1:
4460 case OP_ATOMIC_STORE_U1:
4461 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4463 case OP_ATOMIC_STORE_I2:
4464 case OP_ATOMIC_STORE_U2:
4465 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4467 case OP_ATOMIC_STORE_I4:
4468 case OP_ATOMIC_STORE_U4:
4469 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4471 case OP_ATOMIC_STORE_R4:
4473 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4474 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4476 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4477 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4478 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4479 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4480 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4483 case OP_ATOMIC_STORE_R8:
4484 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4485 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4489 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4490 ARM_DMB (code, ARM_DMB_SY);
4494 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4495 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4498 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4499 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4501 case OP_STOREI1_MEMBASE_IMM:
4502 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4503 g_assert (arm_is_imm12 (ins->inst_offset));
4504 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4506 case OP_STOREI2_MEMBASE_IMM:
4507 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4508 g_assert (arm_is_imm8 (ins->inst_offset));
4509 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4511 case OP_STORE_MEMBASE_IMM:
4512 case OP_STOREI4_MEMBASE_IMM:
4513 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4514 g_assert (arm_is_imm12 (ins->inst_offset));
4515 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4517 case OP_STOREI1_MEMBASE_REG:
4518 g_assert (arm_is_imm12 (ins->inst_offset));
4519 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4521 case OP_STOREI2_MEMBASE_REG:
4522 g_assert (arm_is_imm8 (ins->inst_offset));
4523 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4525 case OP_STORE_MEMBASE_REG:
4526 case OP_STOREI4_MEMBASE_REG:
4527 /* this case is special, since it happens for spill code after lowering has been called */
4528 if (arm_is_imm12 (ins->inst_offset)) {
4529 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4531 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4532 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4535 case OP_STOREI1_MEMINDEX:
4536 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4538 case OP_STOREI2_MEMINDEX:
4539 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4541 case OP_STORE_MEMINDEX:
4542 case OP_STOREI4_MEMINDEX:
4543 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4546 g_assert_not_reached ();
4548 case OP_LOAD_MEMINDEX:
4549 case OP_LOADI4_MEMINDEX:
4550 case OP_LOADU4_MEMINDEX:
4551 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4553 case OP_LOADI1_MEMINDEX:
4554 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4556 case OP_LOADU1_MEMINDEX:
4557 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4559 case OP_LOADI2_MEMINDEX:
4560 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4562 case OP_LOADU2_MEMINDEX:
4563 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4565 case OP_LOAD_MEMBASE:
4566 case OP_LOADI4_MEMBASE:
4567 case OP_LOADU4_MEMBASE:
4568 /* this case is special, since it happens for spill code after lowering has been called */
4569 if (arm_is_imm12 (ins->inst_offset)) {
4570 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4572 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4573 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4576 case OP_LOADI1_MEMBASE:
4577 g_assert (arm_is_imm8 (ins->inst_offset));
4578 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4580 case OP_LOADU1_MEMBASE:
4581 g_assert (arm_is_imm12 (ins->inst_offset));
4582 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4584 case OP_LOADU2_MEMBASE:
4585 g_assert (arm_is_imm8 (ins->inst_offset));
4586 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4588 case OP_LOADI2_MEMBASE:
4589 g_assert (arm_is_imm8 (ins->inst_offset));
4590 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4592 case OP_ICONV_TO_I1:
4593 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4594 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4596 case OP_ICONV_TO_I2:
4597 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4598 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4600 case OP_ICONV_TO_U1:
4601 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4603 case OP_ICONV_TO_U2:
4604 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4605 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4609 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4611 case OP_COMPARE_IMM:
4612 case OP_ICOMPARE_IMM:
4613 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4614 g_assert (imm8 >= 0);
4615 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4619 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4620 * So instead of emitting a trap, we emit a call a C function and place a
4623 //*(int*)code = 0xef9f0001;
4626 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4627 (gpointer)"mono_break");
4628 code = emit_call_seq (cfg, code);
4630 case OP_RELAXED_NOP:
4635 case OP_DUMMY_STORE:
4636 case OP_DUMMY_ICONST:
4637 case OP_DUMMY_R8CONST:
4638 case OP_NOT_REACHED:
4641 case OP_IL_SEQ_POINT:
4642 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4644 case OP_SEQ_POINT: {
4646 MonoInst *info_var = cfg->arch.seq_point_info_var;
4647 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4648 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
4649 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4650 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4652 int dreg = ARMREG_LR;
4654 if (cfg->soft_breakpoints) {
4655 g_assert (!cfg->compile_aot);
4659 * For AOT, we use one got slot per method, which will point to a
4660 * SeqPointInfo structure, containing all the information required
4661 * by the code below.
4663 if (cfg->compile_aot) {
4664 g_assert (info_var);
4665 g_assert (info_var->opcode == OP_REGOFFSET);
4666 g_assert (arm_is_imm12 (info_var->inst_offset));
4669 if (!cfg->soft_breakpoints) {
4671 * Read from the single stepping trigger page. This will cause a
4672 * SIGSEGV when single stepping is enabled.
4673 * We do this _before_ the breakpoint, so single stepping after
4674 * a breakpoint is hit will step to the next IL offset.
4676 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4679 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4680 if (cfg->soft_breakpoints) {
4681 /* Load the address of the sequence point trigger variable. */
4684 g_assert (var->opcode == OP_REGOFFSET);
4685 g_assert (arm_is_imm12 (var->inst_offset));
4686 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4688 /* Read the value and check whether it is non-zero. */
4689 ARM_LDR_IMM (code, dreg, dreg, 0);
4690 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4692 /* Load the address of the sequence point method. */
4693 var = ss_method_var;
4695 g_assert (var->opcode == OP_REGOFFSET);
4696 g_assert (arm_is_imm12 (var->inst_offset));
4697 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4699 /* Call it conditionally. */
4700 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4702 if (cfg->compile_aot) {
4703 /* Load the trigger page addr from the variable initialized in the prolog */
4704 var = ss_trigger_page_var;
4706 g_assert (var->opcode == OP_REGOFFSET);
4707 g_assert (arm_is_imm12 (var->inst_offset));
4708 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4710 #ifdef USE_JUMP_TABLES
4711 gpointer *jte = mono_jumptable_add_entry ();
4712 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4713 jte [0] = ss_trigger_page;
4715 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4717 *(int*)code = (int)ss_trigger_page;
4721 ARM_LDR_IMM (code, dreg, dreg, 0);
4725 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4727 if (cfg->soft_breakpoints) {
4728 /* Load the address of the breakpoint method into ip. */
4729 var = bp_method_var;
4731 g_assert (var->opcode == OP_REGOFFSET);
4732 g_assert (arm_is_imm12 (var->inst_offset));
4733 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4736 * A placeholder for a possible breakpoint inserted by
4737 * mono_arch_set_breakpoint ().
4740 } else if (cfg->compile_aot) {
4741 guint32 offset = code - cfg->native_code;
4744 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4745 /* Add the offset */
4746 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4747 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4748 if (arm_is_imm12 ((int)val)) {
4749 ARM_LDR_IMM (code, dreg, dreg, val);
4751 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4753 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4755 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4756 g_assert (!(val & 0xFF000000));
4758 ARM_LDR_IMM (code, dreg, dreg, 0);
4760 /* What is faster, a branch or a load ? */
4761 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4762 /* The breakpoint instruction */
4763 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4766 * A placeholder for a possible breakpoint inserted by
4767 * mono_arch_set_breakpoint ().
4769 for (i = 0; i < 4; ++i)
4774 * Add an additional nop so skipping the bp doesn't cause the ip to point
4775 * to another IL offset.
4783 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4786 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4790 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4793 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4794 g_assert (imm8 >= 0);
4795 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4799 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4800 g_assert (imm8 >= 0);
4801 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4805 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4806 g_assert (imm8 >= 0);
4807 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4810 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4811 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4813 case OP_IADD_OVF_UN:
4814 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4815 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4818 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4819 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4821 case OP_ISUB_OVF_UN:
4822 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4823 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4825 case OP_ADD_OVF_CARRY:
4826 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4827 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4829 case OP_ADD_OVF_UN_CARRY:
4830 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4831 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4833 case OP_SUB_OVF_CARRY:
4834 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4835 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4837 case OP_SUB_OVF_UN_CARRY:
4838 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4839 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4843 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4846 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4847 g_assert (imm8 >= 0);
4848 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4851 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4855 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4859 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4860 g_assert (imm8 >= 0);
4861 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4865 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4866 g_assert (imm8 >= 0);
4867 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4869 case OP_ARM_RSBS_IMM:
4870 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4871 g_assert (imm8 >= 0);
4872 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4874 case OP_ARM_RSC_IMM:
4875 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4876 g_assert (imm8 >= 0);
4877 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4880 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4884 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4885 g_assert (imm8 >= 0);
4886 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4889 g_assert (v7s_supported);
4890 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4893 g_assert (v7s_supported);
4894 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4897 g_assert (v7s_supported);
4898 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4899 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4902 g_assert (v7s_supported);
4903 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4904 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4908 g_assert_not_reached ();
4910 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4914 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4915 g_assert (imm8 >= 0);
4916 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4919 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4923 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4924 g_assert (imm8 >= 0);
4925 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4928 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4933 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4934 else if (ins->dreg != ins->sreg1)
4935 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4938 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4943 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4944 else if (ins->dreg != ins->sreg1)
4945 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4948 case OP_ISHR_UN_IMM:
4950 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4951 else if (ins->dreg != ins->sreg1)
4952 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4955 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4958 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4961 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4964 if (ins->dreg == ins->sreg2)
4965 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4967 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4970 g_assert_not_reached ();
4973 /* FIXME: handle ovf/ sreg2 != dreg */
4974 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4975 /* FIXME: MUL doesn't set the C/O flags on ARM */
4977 case OP_IMUL_OVF_UN:
4978 /* FIXME: handle ovf/ sreg2 != dreg */
4979 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4980 /* FIXME: MUL doesn't set the C/O flags on ARM */
4983 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4986 /* Load the GOT offset */
4987 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4988 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4990 *(gpointer*)code = NULL;
4992 /* Load the value from the GOT */
4993 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4995 case OP_OBJC_GET_SELECTOR:
4996 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4997 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4999 *(gpointer*)code = NULL;
5001 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
5003 case OP_ICONV_TO_I4:
5004 case OP_ICONV_TO_U4:
5006 if (ins->dreg != ins->sreg1)
5007 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5010 int saved = ins->sreg2;
5011 if (ins->sreg2 == ARM_LSW_REG) {
5012 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
5015 if (ins->sreg1 != ARM_LSW_REG)
5016 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
5017 if (saved != ARM_MSW_REG)
5018 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
5022 if (IS_VFP && ins->dreg != ins->sreg1)
5023 ARM_CPYD (code, ins->dreg, ins->sreg1);
5026 if (IS_VFP && ins->dreg != ins->sreg1)
5027 ARM_CPYS (code, ins->dreg, ins->sreg1);
5029 case OP_MOVE_F_TO_I4:
5031 ARM_FMRS (code, ins->dreg, ins->sreg1);
5033 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5034 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5035 ARM_FMRS (code, ins->dreg, vfp_scratch1);
5036 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5039 case OP_MOVE_I4_TO_F:
5041 ARM_FMSR (code, ins->dreg, ins->sreg1);
5043 ARM_FMSR (code, ins->dreg, ins->sreg1);
5044 ARM_CVTS (code, ins->dreg, ins->dreg);
5047 case OP_FCONV_TO_R4:
5050 ARM_CVTD (code, ins->dreg, ins->sreg1);
5052 ARM_CVTD (code, ins->dreg, ins->sreg1);
5053 ARM_CVTS (code, ins->dreg, ins->dreg);
5058 MonoCallInst *call = (MonoCallInst*)ins;
5061 * The stack looks like the following:
5062 * <caller argument area>
5065 * <callee argument area>
5066 * Need to copy the arguments from the callee argument area to
5067 * the caller argument area, and pop the frame.
5069 if (call->stack_usage) {
5070 int i, prev_sp_offset = 0;
5072 /* Compute size of saved registers restored below */
5074 prev_sp_offset = 2 * 4;
5076 prev_sp_offset = 1 * 4;
5077 for (i = 0; i < 16; ++i) {
5078 if (cfg->used_int_regs & (1 << i))
5079 prev_sp_offset += 4;
5082 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5084 /* Copy arguments on the stack to our argument area */
5085 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5086 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5087 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5092 * Keep in sync with mono_arch_emit_epilog
5094 g_assert (!cfg->method->save_lmf);
5096 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5098 if (cfg->used_int_regs)
5099 ARM_POP (code, cfg->used_int_regs);
5100 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5102 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5105 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5106 if (cfg->compile_aot) {
5107 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5109 *(gpointer*)code = NULL;
5111 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5113 code = mono_arm_patchable_b (code, ARMCOND_AL);
5114 cfg->thunk_area += THUNK_SIZE;
5119 /* ensure ins->sreg1 is not NULL */
5120 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5123 g_assert (cfg->sig_cookie < 128);
5124 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5125 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5135 call = (MonoCallInst*)ins;
5138 code = emit_float_args (cfg, call, code, &max_len, &offset);
5140 if (ins->flags & MONO_INST_HAS_METHOD)
5141 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5143 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5144 code = emit_call_seq (cfg, code);
5145 ins->flags |= MONO_INST_GC_CALLSITE;
5146 ins->backend.pc_offset = code - cfg->native_code;
5147 code = emit_move_return_value (cfg, ins, code);
5154 case OP_VOIDCALL_REG:
5157 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5159 code = emit_call_reg (code, ins->sreg1);
5160 ins->flags |= MONO_INST_GC_CALLSITE;
5161 ins->backend.pc_offset = code - cfg->native_code;
5162 code = emit_move_return_value (cfg, ins, code);
5164 case OP_FCALL_MEMBASE:
5165 case OP_RCALL_MEMBASE:
5166 case OP_LCALL_MEMBASE:
5167 case OP_VCALL_MEMBASE:
5168 case OP_VCALL2_MEMBASE:
5169 case OP_VOIDCALL_MEMBASE:
5170 case OP_CALL_MEMBASE: {
5171 g_assert (ins->sreg1 != ARMREG_LR);
5172 call = (MonoCallInst*)ins;
5175 code = emit_float_args (cfg, call, code, &max_len, &offset);
5176 if (!arm_is_imm12 (ins->inst_offset))
5177 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5178 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5179 if (!arm_is_imm12 (ins->inst_offset))
5180 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5182 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5183 ins->flags |= MONO_INST_GC_CALLSITE;
5184 ins->backend.pc_offset = code - cfg->native_code;
5185 code = emit_move_return_value (cfg, ins, code);
5188 case OP_GENERIC_CLASS_INIT: {
5189 static int byte_offset = -1;
5190 static guint8 bitmask;
5194 if (byte_offset < 0)
5195 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5197 g_assert (arm_is_imm8 (byte_offset));
5198 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5199 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5200 g_assert (imm8 >= 0);
5201 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5202 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5204 ARM_B_COND (code, ARMCOND_NE, 0);
5206 /* Uninitialized case */
5207 g_assert (ins->sreg1 == ARMREG_R0);
5209 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5210 (gpointer)"mono_generic_class_init");
5211 code = emit_call_seq (cfg, code);
5213 /* Initialized case */
5214 arm_patch (jump, code);
5218 /* round the size to 8 bytes */
5219 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5220 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5221 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5222 /* memzero the area: dreg holds the size, sp is the pointer */
5223 if (ins->flags & MONO_INST_INIT) {
5224 guint8 *start_loop, *branch_to_cond;
5225 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5226 branch_to_cond = code;
5229 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5230 arm_patch (branch_to_cond, code);
5231 /* decrement by 4 and set flags */
5232 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5233 ARM_B_COND (code, ARMCOND_GE, 0);
5234 arm_patch (code - 4, start_loop);
5236 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5237 if (cfg->param_area)
5238 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5243 MonoInst *var = cfg->dyn_call_var;
5245 g_assert (var->opcode == OP_REGOFFSET);
5246 g_assert (arm_is_imm12 (var->inst_offset));
5248 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5249 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5251 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5253 /* Save args buffer */
5254 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5256 /* Set stack slots using R0 as scratch reg */
5257 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5258 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5259 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5260 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5263 /* Set argument registers */
5264 for (i = 0; i < PARAM_REGS; ++i)
5265 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5268 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5269 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5272 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5273 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5274 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5278 if (ins->sreg1 != ARMREG_R0)
5279 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5280 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5281 (gpointer)"mono_arch_throw_exception");
5282 code = emit_call_seq (cfg, code);
5286 if (ins->sreg1 != ARMREG_R0)
5287 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5288 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5289 (gpointer)"mono_arch_rethrow_exception");
5290 code = emit_call_seq (cfg, code);
5293 case OP_START_HANDLER: {
5294 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5295 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5298 /* Reserve a param area, see filter-stack.exe */
5300 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5301 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5303 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5304 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5308 if (arm_is_imm12 (spvar->inst_offset)) {
5309 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5311 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5312 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5316 case OP_ENDFILTER: {
5317 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5318 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5321 /* Free the param area */
5323 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5324 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5326 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5327 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5331 if (ins->sreg1 != ARMREG_R0)
5332 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5333 if (arm_is_imm12 (spvar->inst_offset)) {
5334 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5336 g_assert (ARMREG_IP != spvar->inst_basereg);
5337 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5338 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5340 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5343 case OP_ENDFINALLY: {
5344 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5345 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5348 /* Free the param area */
5350 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5351 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5353 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5354 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5358 if (arm_is_imm12 (spvar->inst_offset)) {
5359 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5361 g_assert (ARMREG_IP != spvar->inst_basereg);
5362 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5363 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5365 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5368 case OP_CALL_HANDLER:
5369 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5370 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5371 cfg->thunk_area += THUNK_SIZE;
5372 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5375 if (ins->dreg != ARMREG_R0)
5376 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5380 ins->inst_c0 = code - cfg->native_code;
5383 /*if (ins->inst_target_bb->native_offset) {
5385 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5387 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5388 code = mono_arm_patchable_b (code, ARMCOND_AL);
5392 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5396 * In the normal case we have:
5397 * ldr pc, [pc, ins->sreg1 << 2]
5400 * ldr lr, [pc, ins->sreg1 << 2]
5402 * After follows the data.
5403 * FIXME: add aot support.
5405 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5406 #ifdef USE_JUMP_TABLES
5408 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5409 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5410 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5414 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5415 if (offset + max_len > (cfg->code_size - 16)) {
5416 cfg->code_size += max_len;
5417 cfg->code_size *= 2;
5418 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5419 code = cfg->native_code + offset;
5421 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5423 code += 4 * GPOINTER_TO_INT (ins->klass);
5428 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5429 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5433 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5434 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5438 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5439 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5443 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5444 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5448 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5449 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5452 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5453 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5456 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5457 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5460 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5461 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5464 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5465 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5468 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5469 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5471 case OP_COND_EXC_EQ:
5472 case OP_COND_EXC_NE_UN:
5473 case OP_COND_EXC_LT:
5474 case OP_COND_EXC_LT_UN:
5475 case OP_COND_EXC_GT:
5476 case OP_COND_EXC_GT_UN:
5477 case OP_COND_EXC_GE:
5478 case OP_COND_EXC_GE_UN:
5479 case OP_COND_EXC_LE:
5480 case OP_COND_EXC_LE_UN:
5481 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5483 case OP_COND_EXC_IEQ:
5484 case OP_COND_EXC_INE_UN:
5485 case OP_COND_EXC_ILT:
5486 case OP_COND_EXC_ILT_UN:
5487 case OP_COND_EXC_IGT:
5488 case OP_COND_EXC_IGT_UN:
5489 case OP_COND_EXC_IGE:
5490 case OP_COND_EXC_IGE_UN:
5491 case OP_COND_EXC_ILE:
5492 case OP_COND_EXC_ILE_UN:
5493 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5496 case OP_COND_EXC_IC:
5497 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5499 case OP_COND_EXC_OV:
5500 case OP_COND_EXC_IOV:
5501 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5503 case OP_COND_EXC_NC:
5504 case OP_COND_EXC_INC:
5505 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5507 case OP_COND_EXC_NO:
5508 case OP_COND_EXC_INO:
5509 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5521 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5524 /* floating point opcodes */
5526 if (cfg->compile_aot) {
5527 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5529 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5531 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5534 /* FIXME: we can optimize the imm load by dealing with part of
5535 * the displacement in LDFD (aligning to 512).
5537 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5538 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5542 if (cfg->compile_aot) {
5543 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5545 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5548 ARM_CVTS (code, ins->dreg, ins->dreg);
5550 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5551 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5553 ARM_CVTS (code, ins->dreg, ins->dreg);
5556 case OP_STORER8_MEMBASE_REG:
5557 /* This is generated by the local regalloc pass which runs after the lowering pass */
5558 if (!arm_is_fpimm8 (ins->inst_offset)) {
5559 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5560 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5561 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5563 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5566 case OP_LOADR8_MEMBASE:
5567 /* This is generated by the local regalloc pass which runs after the lowering pass */
5568 if (!arm_is_fpimm8 (ins->inst_offset)) {
5569 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5570 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5571 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5573 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5576 case OP_STORER4_MEMBASE_REG:
5577 g_assert (arm_is_fpimm8 (ins->inst_offset));
5579 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5581 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5582 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5583 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5584 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5587 case OP_LOADR4_MEMBASE:
5589 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5591 g_assert (arm_is_fpimm8 (ins->inst_offset));
5592 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5593 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5594 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5595 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5598 case OP_ICONV_TO_R_UN: {
5599 g_assert_not_reached ();
5602 case OP_ICONV_TO_R4:
5604 ARM_FMSR (code, ins->dreg, ins->sreg1);
5605 ARM_FSITOS (code, ins->dreg, ins->dreg);
5607 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5608 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5609 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5610 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5611 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5614 case OP_ICONV_TO_R8:
5615 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5616 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5617 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5618 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5622 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5623 if (sig_ret->type == MONO_TYPE_R4) {
5625 g_assert (!IS_HARD_FLOAT);
5626 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5628 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5631 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5635 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5637 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5641 case OP_FCONV_TO_I1:
5642 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5644 case OP_FCONV_TO_U1:
5645 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5647 case OP_FCONV_TO_I2:
5648 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5650 case OP_FCONV_TO_U2:
5651 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5653 case OP_FCONV_TO_I4:
5655 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5657 case OP_FCONV_TO_U4:
5659 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5661 case OP_FCONV_TO_I8:
5662 case OP_FCONV_TO_U8:
5663 g_assert_not_reached ();
5664 /* Implemented as helper calls */
5666 case OP_LCONV_TO_R_UN:
5667 g_assert_not_reached ();
5668 /* Implemented as helper calls */
5670 case OP_LCONV_TO_OVF_I4_2: {
5671 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5673 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5676 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5677 high_bit_not_set = code;
5678 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5680 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5681 valid_negative = code;
5682 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5683 invalid_negative = code;
5684 ARM_B_COND (code, ARMCOND_AL, 0);
5686 arm_patch (high_bit_not_set, code);
5688 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5689 valid_positive = code;
5690 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5692 arm_patch (invalid_negative, code);
5693 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5695 arm_patch (valid_negative, code);
5696 arm_patch (valid_positive, code);
5698 if (ins->dreg != ins->sreg1)
5699 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5703 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5706 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5709 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5712 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5715 ARM_NEGD (code, ins->dreg, ins->sreg1);
5719 g_assert_not_reached ();
5723 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5729 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5734 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5737 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5738 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5742 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5745 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5746 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5750 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5753 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5754 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5755 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5759 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5762 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5763 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5767 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5770 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5771 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5772 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5776 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5779 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5780 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5784 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5787 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5788 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5792 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5795 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5796 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5799 /* ARM FPA flags table:
5800 * N Less than ARMCOND_MI
5801 * Z Equal ARMCOND_EQ
5802 * C Greater Than or Equal ARMCOND_CS
5803 * V Unordered ARMCOND_VS
5806 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5809 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5812 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5815 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5816 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5822 g_assert_not_reached ();
5826 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5828 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5829 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5830 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5834 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5835 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5840 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5841 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5843 #ifdef USE_JUMP_TABLES
5845 gpointer *jte = mono_jumptable_add_entries (2);
5846 jte [0] = GUINT_TO_POINTER (0xffffffff);
5847 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5848 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5849 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5852 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5853 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5855 *(guint32*)code = 0xffffffff;
5857 *(guint32*)code = 0x7fefffff;
5860 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5862 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5863 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5865 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5866 ARM_CPYD (code, ins->dreg, ins->sreg1);
5868 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5869 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5874 case OP_RCONV_TO_I1:
5875 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5877 case OP_RCONV_TO_U1:
5878 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5880 case OP_RCONV_TO_I2:
5881 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5883 case OP_RCONV_TO_U2:
5884 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5886 case OP_RCONV_TO_I4:
5887 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5889 case OP_RCONV_TO_U4:
5890 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5892 case OP_RCONV_TO_R4:
5894 if (ins->dreg != ins->sreg1)
5895 ARM_CPYS (code, ins->dreg, ins->sreg1);
5897 case OP_RCONV_TO_R8:
5899 ARM_CVTS (code, ins->dreg, ins->sreg1);
5902 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5905 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5908 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5911 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5914 ARM_NEGS (code, ins->dreg, ins->sreg1);
5918 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5921 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5922 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5926 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5929 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5930 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5934 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5937 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5938 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5939 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5943 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5946 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5947 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5951 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5954 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5955 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5956 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5960 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5963 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5964 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5968 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5971 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5972 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5976 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5979 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5980 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5983 case OP_GC_LIVENESS_DEF:
5984 case OP_GC_LIVENESS_USE:
5985 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5986 ins->backend.pc_offset = code - cfg->native_code;
5988 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5989 ins->backend.pc_offset = code - cfg->native_code;
5990 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5992 case OP_GC_SAFE_POINT: {
5993 #if defined (USE_COOP_GC)
5994 const char *polling_func = NULL;
5997 polling_func = "mono_threads_state_poll";
5998 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5999 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
6001 ARM_B_COND (code, ARMCOND_EQ, 0);
6002 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
6003 code = emit_call_seq (cfg, code);
6004 arm_patch (buf [0], code);
6010 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6011 g_assert_not_reached ();
6014 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
6015 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
6016 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6017 g_assert_not_reached ();
6023 last_offset = offset;
6026 cfg->code_len = code - cfg->native_code;
6029 #endif /* DISABLE_JIT */
6032 mono_arch_register_lowlevel_calls (void)
6034 /* The signature doesn't matter */
6035 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
6036 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
6037 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
6039 #ifndef MONO_CROSS_COMPILE
6040 if (mono_arm_have_tls_get ()) {
6041 if (mono_arm_have_fast_tls ()) {
6042 mono_register_jit_icall (mono_fast_get_tls_key, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
6043 mono_register_jit_icall (mono_fast_set_tls_key, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
6045 mono_tramp_info_register (
6046 mono_tramp_info_create (
6048 (guint8*)mono_fast_get_tls_key,
6049 (guint8*)mono_fast_get_tls_key_end - (guint8*)mono_fast_get_tls_key,
6051 mono_arch_get_cie_program ()
6055 mono_tramp_info_register (
6056 mono_tramp_info_create (
6058 (guint8*)mono_fast_set_tls_key,
6059 (guint8*)mono_fast_set_tls_key_end - (guint8*)mono_fast_set_tls_key,
6061 mono_arch_get_cie_program ()
6066 g_warning ("No fast tls on device. Using fallbacks.");
6067 mono_register_jit_icall (mono_fallback_get_tls_key, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
6068 mono_register_jit_icall (mono_fallback_set_tls_key, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
6074 #define patch_lis_ori(ip,val) do {\
6075 guint16 *__lis_ori = (guint16*)(ip); \
6076 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
6077 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
6081 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6083 unsigned char *ip = ji->ip.i + code;
6085 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6089 case MONO_PATCH_INFO_SWITCH: {
6090 #ifdef USE_JUMP_TABLES
6091 gpointer *jt = mono_jumptable_get_entry (ip);
6093 gpointer *jt = (gpointer*)(ip + 8);
6096 /* jt is the inlined jump table, 2 instructions after ip
6097 * In the normal case we store the absolute addresses,
6098 * otherwise the displacements.
6100 for (i = 0; i < ji->data.table->table_size; i++)
6101 jt [i] = code + (int)ji->data.table->table [i];
6104 case MONO_PATCH_INFO_IP:
6105 g_assert_not_reached ();
6106 patch_lis_ori (ip, ip);
6108 case MONO_PATCH_INFO_METHOD_REL:
6109 g_assert_not_reached ();
6110 *((gpointer *)(ip)) = target;
6112 case MONO_PATCH_INFO_METHODCONST:
6113 case MONO_PATCH_INFO_CLASS:
6114 case MONO_PATCH_INFO_IMAGE:
6115 case MONO_PATCH_INFO_FIELD:
6116 case MONO_PATCH_INFO_VTABLE:
6117 case MONO_PATCH_INFO_IID:
6118 case MONO_PATCH_INFO_SFLDA:
6119 case MONO_PATCH_INFO_LDSTR:
6120 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6121 case MONO_PATCH_INFO_LDTOKEN:
6122 g_assert_not_reached ();
6123 /* from OP_AOTCONST : lis + ori */
6124 patch_lis_ori (ip, target);
6126 case MONO_PATCH_INFO_R4:
6127 case MONO_PATCH_INFO_R8:
6128 g_assert_not_reached ();
6129 *((gconstpointer *)(ip + 2)) = target;
6131 case MONO_PATCH_INFO_EXC_NAME:
6132 g_assert_not_reached ();
6133 *((gconstpointer *)(ip + 1)) = target;
6135 case MONO_PATCH_INFO_NONE:
6136 case MONO_PATCH_INFO_BB_OVF:
6137 case MONO_PATCH_INFO_EXC_OVF:
6138 /* everything is dealt with at epilog output time */
6141 arm_patch_general (cfg, domain, ip, target);
6147 mono_arm_unaligned_stack (MonoMethod *method)
6149 g_assert_not_reached ();
6155 * Stack frame layout:
6157 * ------------------- fp
6158 * MonoLMF structure or saved registers
6159 * -------------------
6161 * -------------------
6163 * -------------------
6164 * optional 8 bytes for tracing
6165 * -------------------
6166 * param area size is cfg->param_area
6167 * ------------------- sp
6170 mono_arch_emit_prolog (MonoCompile *cfg)
6172 MonoMethod *method = cfg->method;
6174 MonoMethodSignature *sig;
6176 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6181 int prev_sp_offset, reg_offset;
6183 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6186 sig = mono_method_signature (method);
6187 cfg->code_size = 256 + sig->param_count * 64;
6188 code = cfg->native_code = g_malloc (cfg->code_size);
6190 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6192 alloc_size = cfg->stack_offset;
6198 * The iphone uses R7 as the frame pointer, and it points at the saved
6203 * We can't use r7 as a frame pointer since it points into the middle of
6204 * the frame, so we keep using our own frame pointer.
6205 * FIXME: Optimize this.
6207 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6208 prev_sp_offset += 8; /* r7 and lr */
6209 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6210 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6211 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6214 if (!method->save_lmf) {
6216 /* No need to push LR again */
6217 if (cfg->used_int_regs)
6218 ARM_PUSH (code, cfg->used_int_regs);
6220 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6221 prev_sp_offset += 4;
6223 for (i = 0; i < 16; ++i) {
6224 if (cfg->used_int_regs & (1 << i))
6225 prev_sp_offset += 4;
6227 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6229 for (i = 0; i < 16; ++i) {
6230 if ((cfg->used_int_regs & (1 << i))) {
6231 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6232 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6237 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6238 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6240 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6241 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6244 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6245 ARM_PUSH (code, 0x5ff0);
6246 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6247 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6249 for (i = 0; i < 16; ++i) {
6250 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6251 /* The original r7 is saved at the start */
6252 if (!(iphone_abi && i == ARMREG_R7))
6253 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6257 g_assert (reg_offset == 4 * 10);
6258 pos += sizeof (MonoLMF) - (4 * 10);
6262 orig_alloc_size = alloc_size;
6263 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6264 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6265 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6266 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6269 /* the stack used in the pushed regs */
6270 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6271 cfg->stack_usage = alloc_size;
6273 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6274 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6276 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6277 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6279 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6281 if (cfg->frame_reg != ARMREG_SP) {
6282 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6283 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6285 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6286 prev_sp_offset += alloc_size;
6288 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6289 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6291 /* compute max_offset in order to use short forward jumps
6292 * we could skip do it on arm because the immediate displacement
6293 * for jumps is large enough, it may be useful later for constant pools
6296 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6297 MonoInst *ins = bb->code;
6298 bb->max_offset = max_offset;
6300 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6303 MONO_BB_FOR_EACH_INS (bb, ins)
6304 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6307 /* stack alignment check */
6311 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6312 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6313 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6314 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6316 ARM_B_COND (code, ARMCOND_EQ, 0);
6317 if (cfg->compile_aot)
6318 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6320 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6321 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6322 code = emit_call_seq (cfg, code);
6323 arm_patch (buf [0], code);
6327 /* store runtime generic context */
6328 if (cfg->rgctx_var) {
6329 MonoInst *ins = cfg->rgctx_var;
6331 g_assert (ins->opcode == OP_REGOFFSET);
6333 if (arm_is_imm12 (ins->inst_offset)) {
6334 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6336 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6337 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6341 /* load arguments allocated to register from the stack */
6344 cinfo = get_call_info (NULL, sig);
6346 if (cinfo->ret.storage == RegTypeStructByAddr) {
6347 ArgInfo *ainfo = &cinfo->ret;
6348 inst = cfg->vret_addr;
6349 g_assert (arm_is_imm12 (inst->inst_offset));
6350 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6353 if (sig->call_convention == MONO_CALL_VARARG) {
6354 ArgInfo *cookie = &cinfo->sig_cookie;
6356 /* Save the sig cookie address */
6357 g_assert (cookie->storage == RegTypeBase);
6359 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6360 g_assert (arm_is_imm12 (cfg->sig_cookie));
6361 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6362 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6365 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6366 ArgInfo *ainfo = cinfo->args + i;
6367 inst = cfg->args [pos];
6369 if (cfg->verbose_level > 2)
6370 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6372 if (inst->opcode == OP_REGVAR) {
6373 if (ainfo->storage == RegTypeGeneral)
6374 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6375 else if (ainfo->storage == RegTypeFP) {
6376 g_assert_not_reached ();
6377 } else if (ainfo->storage == RegTypeBase) {
6378 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6379 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6381 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6382 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6385 g_assert_not_reached ();
6387 if (cfg->verbose_level > 2)
6388 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6390 switch (ainfo->storage) {
6392 for (part = 0; part < ainfo->nregs; part ++) {
6393 if (ainfo->esize == 4)
6394 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6396 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6399 case RegTypeGeneral:
6400 case RegTypeIRegPair:
6401 case RegTypeGSharedVtInReg:
6402 switch (ainfo->size) {
6404 if (arm_is_imm12 (inst->inst_offset))
6405 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6407 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6408 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6412 if (arm_is_imm8 (inst->inst_offset)) {
6413 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6415 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6416 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6420 if (arm_is_imm12 (inst->inst_offset)) {
6421 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6423 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6424 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6426 if (arm_is_imm12 (inst->inst_offset + 4)) {
6427 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6429 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6430 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6434 if (arm_is_imm12 (inst->inst_offset)) {
6435 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6437 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6438 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6443 case RegTypeBaseGen:
6444 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6445 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6447 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6448 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6450 if (arm_is_imm12 (inst->inst_offset + 4)) {
6451 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6452 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6454 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6455 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6456 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6457 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6461 case RegTypeGSharedVtOnStack:
6462 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6463 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6465 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6466 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6469 switch (ainfo->size) {
6471 if (arm_is_imm8 (inst->inst_offset)) {
6472 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6474 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6475 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6479 if (arm_is_imm8 (inst->inst_offset)) {
6480 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6482 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6483 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6487 if (arm_is_imm12 (inst->inst_offset)) {
6488 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6490 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6491 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6493 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6494 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6496 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6497 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6499 if (arm_is_imm12 (inst->inst_offset + 4)) {
6500 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6502 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6503 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6507 if (arm_is_imm12 (inst->inst_offset)) {
6508 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6510 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6511 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6517 int imm8, rot_amount;
6519 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6520 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6521 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6523 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6525 if (ainfo->size == 8)
6526 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6528 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6531 case RegTypeStructByVal: {
6532 int doffset = inst->inst_offset;
6536 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6537 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6538 if (arm_is_imm12 (doffset)) {
6539 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6541 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6542 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6544 soffset += sizeof (gpointer);
6545 doffset += sizeof (gpointer);
6547 if (ainfo->vtsize) {
6548 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6549 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6550 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6554 case RegTypeStructByAddr:
6555 g_assert_not_reached ();
6556 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6557 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6559 g_assert_not_reached ();
6566 if (method->save_lmf)
6567 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6570 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6572 if (cfg->arch.seq_point_info_var) {
6573 MonoInst *ins = cfg->arch.seq_point_info_var;
6575 /* Initialize the variable from a GOT slot */
6576 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6577 #ifdef USE_JUMP_TABLES
6579 gpointer *jte = mono_jumptable_add_entry ();
6580 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6581 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6583 /** XXX: is it correct? */
6585 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6587 *(gpointer*)code = NULL;
6590 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6592 g_assert (ins->opcode == OP_REGOFFSET);
6594 if (arm_is_imm12 (ins->inst_offset)) {
6595 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6597 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6598 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6602 /* Initialize ss_trigger_page_var */
6603 if (!cfg->soft_breakpoints) {
6604 MonoInst *info_var = cfg->arch.seq_point_info_var;
6605 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6606 int dreg = ARMREG_LR;
6609 g_assert (info_var->opcode == OP_REGOFFSET);
6610 g_assert (arm_is_imm12 (info_var->inst_offset));
6612 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6613 /* Load the trigger page addr */
6614 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6615 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6619 if (cfg->arch.seq_point_read_var) {
6620 MonoInst *read_ins = cfg->arch.seq_point_read_var;
6621 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6622 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6623 #ifdef USE_JUMP_TABLES
6626 g_assert (read_ins->opcode == OP_REGOFFSET);
6627 g_assert (arm_is_imm12 (read_ins->inst_offset));
6628 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6629 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6630 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6631 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6633 #ifdef USE_JUMP_TABLES
6634 jte = mono_jumptable_add_entries (3);
6635 jte [0] = (gpointer)&ss_trigger_var;
6636 jte [1] = single_step_tramp;
6637 jte [2] = breakpoint_tramp;
6638 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6640 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6642 *(volatile int **)code = &ss_trigger_var;
6644 *(gpointer*)code = single_step_tramp;
6646 *(gpointer*)code = breakpoint_tramp;
6650 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6651 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
6652 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6653 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6654 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
6655 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6658 cfg->code_len = code - cfg->native_code;
6659 g_assert (cfg->code_len < cfg->code_size);
6666 mono_arch_emit_epilog (MonoCompile *cfg)
6668 MonoMethod *method = cfg->method;
6669 int pos, i, rot_amount;
6670 int max_epilog_size = 16 + 20*4;
6674 if (cfg->method->save_lmf)
6675 max_epilog_size += 128;
6677 if (mono_jit_trace_calls != NULL)
6678 max_epilog_size += 50;
6680 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6681 max_epilog_size += 50;
6683 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6684 cfg->code_size *= 2;
6685 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6686 cfg->stat_code_reallocs++;
6690 * Keep in sync with OP_JMP
6692 code = cfg->native_code + cfg->code_len;
6694 /* Save the uwind state which is needed by the out-of-line code */
6695 mono_emit_unwind_op_remember_state (cfg, code);
6697 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6698 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6702 /* Load returned vtypes into registers if needed */
6703 cinfo = cfg->arch.cinfo;
6704 switch (cinfo->ret.storage) {
6705 case RegTypeStructByVal: {
6706 MonoInst *ins = cfg->ret;
6708 if (arm_is_imm12 (ins->inst_offset)) {
6709 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6711 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6712 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6717 MonoInst *ins = cfg->ret;
6719 for (i = 0; i < cinfo->ret.nregs; ++i) {
6720 if (cinfo->ret.esize == 4)
6721 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6723 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6731 if (method->save_lmf) {
6732 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6733 /* all but r0-r3, sp and pc */
6734 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6737 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6739 /* This points to r4 inside MonoLMF->iregs */
6740 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6742 regmask = 0x9ff0; /* restore lr to pc */
6743 /* Skip caller saved registers not used by the method */
6744 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6745 regmask &= ~(1 << reg);
6750 /* Restored later */
6751 regmask &= ~(1 << ARMREG_PC);
6752 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6753 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6754 for (i = 0; i < 16; i++) {
6755 if (regmask & (1 << i))
6758 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6760 ARM_POP (code, regmask);
6762 for (i = 0; i < 16; i++) {
6763 if (regmask & (1 << i))
6764 mono_emit_unwind_op_same_value (cfg, code, i);
6766 /* Restore saved r7, restore LR to PC */
6767 /* Skip lr from the lmf */
6768 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6769 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6770 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6771 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6774 int i, nused_int_regs = 0;
6776 for (i = 0; i < 16; i++) {
6777 if (cfg->used_int_regs & (1 << i))
6781 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6782 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6784 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6785 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6788 if (cfg->frame_reg != ARMREG_SP) {
6789 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6793 /* Restore saved gregs */
6794 if (cfg->used_int_regs) {
6795 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6796 ARM_POP (code, cfg->used_int_regs);
6797 for (i = 0; i < 16; i++) {
6798 if (cfg->used_int_regs & (1 << i))
6799 mono_emit_unwind_op_same_value (cfg, code, i);
6802 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6803 /* Restore saved r7, restore LR to PC */
6804 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6806 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6807 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6811 /* Restore the unwind state to be the same as before the epilog */
6812 mono_emit_unwind_op_restore_state (cfg, code);
6814 cfg->code_len = code - cfg->native_code;
6816 g_assert (cfg->code_len < cfg->code_size);
6821 mono_arch_emit_exceptions (MonoCompile *cfg)
6823 MonoJumpInfo *patch_info;
6826 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6827 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6828 int max_epilog_size = 50;
6830 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6831 exc_throw_pos [i] = NULL;
6832 exc_throw_found [i] = 0;
6835 /* count the number of exception infos */
6838 * make sure we have enough space for exceptions
6840 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6841 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6842 i = mini_exception_id_by_name (patch_info->data.target);
6843 if (!exc_throw_found [i]) {
6844 max_epilog_size += 32;
6845 exc_throw_found [i] = TRUE;
6850 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6851 cfg->code_size *= 2;
6852 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6853 cfg->stat_code_reallocs++;
6856 code = cfg->native_code + cfg->code_len;
6858 /* add code to raise exceptions */
6859 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6860 switch (patch_info->type) {
6861 case MONO_PATCH_INFO_EXC: {
6862 MonoClass *exc_class;
6863 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6865 i = mini_exception_id_by_name (patch_info->data.target);
6866 if (exc_throw_pos [i]) {
6867 arm_patch (ip, exc_throw_pos [i]);
6868 patch_info->type = MONO_PATCH_INFO_NONE;
6871 exc_throw_pos [i] = code;
6873 arm_patch (ip, code);
6875 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6876 g_assert (exc_class);
6878 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6879 #ifdef USE_JUMP_TABLES
6881 gpointer *jte = mono_jumptable_add_entries (2);
6882 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6883 patch_info->data.name = "mono_arch_throw_corlib_exception";
6884 patch_info->ip.i = code - cfg->native_code;
6885 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6886 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6887 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6888 ARM_BLX_REG (code, ARMREG_IP);
6889 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6892 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6893 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6894 patch_info->data.name = "mono_arch_throw_corlib_exception";
6895 patch_info->ip.i = code - cfg->native_code;
6897 cfg->thunk_area += THUNK_SIZE;
6898 *(guint32*)(gpointer)code = exc_class->type_token;
6909 cfg->code_len = code - cfg->native_code;
6911 g_assert (cfg->code_len < cfg->code_size);
6915 #endif /* #ifndef DISABLE_JIT */
6918 mono_arch_finish_init (void)
6923 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6928 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6935 mono_arch_print_tree (MonoInst *tree, int arity)
6945 mono_arch_get_patch_offset (guint8 *code)
6952 mono_arch_flush_register_windows (void)
6957 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6959 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6963 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6965 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6969 mono_arch_get_cie_program (void)
6973 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6978 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6979 #define BASE_SIZE (6 * 4)
6980 #define BSEARCH_ENTRY_SIZE (4 * 4)
6981 #define CMP_SIZE (3 * 4)
6982 #define BRANCH_SIZE (1 * 4)
6983 #define CALL_SIZE (2 * 4)
6984 #define WMC_SIZE (8 * 4)
6985 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6987 #ifdef USE_JUMP_TABLES
6989 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6991 g_assert (base [index] == NULL);
6992 base [index] = value;
6995 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6997 if (arm_is_imm12 (jti * 4)) {
6998 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
7000 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
7001 if ((jti * 4) >> 16)
7002 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
7003 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
7009 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
7011 guint32 delta = DISTANCE (target, code);
7013 g_assert (delta >= 0 && delta <= 0xFFF);
7014 *target = *target | delta;
7020 #ifdef ENABLE_WRONG_METHOD_CHECK
7022 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
7024 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
7030 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7031 gpointer fail_tramp)
7034 arminstr_t *code, *start;
7035 #ifdef USE_JUMP_TABLES
7038 gboolean large_offsets = FALSE;
7039 guint32 **constant_pool_starts;
7040 arminstr_t *vtable_target = NULL;
7041 int extra_space = 0;
7043 #ifdef ENABLE_WRONG_METHOD_CHECK
7049 #ifdef USE_JUMP_TABLES
7050 for (i = 0; i < count; ++i) {
7051 MonoIMTCheckItem *item = imt_entries [i];
7052 item->chunk_size += 4 * 16;
7053 if (!item->is_equals)
7054 imt_entries [item->check_target_idx]->compare_done = TRUE;
7055 size += item->chunk_size;
7058 constant_pool_starts = g_new0 (guint32*, count);
7060 for (i = 0; i < count; ++i) {
7061 MonoIMTCheckItem *item = imt_entries [i];
7062 if (item->is_equals) {
7063 gboolean fail_case = !item->check_target_idx && fail_tramp;
7065 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
7066 item->chunk_size += 32;
7067 large_offsets = TRUE;
7070 if (item->check_target_idx || fail_case) {
7071 if (!item->compare_done || fail_case)
7072 item->chunk_size += CMP_SIZE;
7073 item->chunk_size += BRANCH_SIZE;
7075 #ifdef ENABLE_WRONG_METHOD_CHECK
7076 item->chunk_size += WMC_SIZE;
7080 item->chunk_size += 16;
7081 large_offsets = TRUE;
7083 item->chunk_size += CALL_SIZE;
7085 item->chunk_size += BSEARCH_ENTRY_SIZE;
7086 imt_entries [item->check_target_idx]->compare_done = TRUE;
7088 size += item->chunk_size;
7092 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
7096 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7098 code = mono_domain_code_reserve (domain, size);
7101 unwind_ops = mono_arch_get_cie_program ();
7104 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
7105 for (i = 0; i < count; ++i) {
7106 MonoIMTCheckItem *item = imt_entries [i];
7107 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
7111 #ifdef USE_JUMP_TABLES
7112 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7113 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 3 * sizeof (mgreg_t));
7114 #define VTABLE_JTI 0
7115 #define IMT_METHOD_OFFSET 0
7116 #define TARGET_CODE_OFFSET 1
7117 #define JUMP_CODE_OFFSET 2
7118 #define RECORDS_PER_ENTRY 3
7119 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
7120 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
7121 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
7123 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
7124 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
7125 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
7126 set_jumptable_element (jte, VTABLE_JTI, vtable);
7128 if (large_offsets) {
7129 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7130 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
7132 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7133 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7135 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7136 vtable_target = code;
7137 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7139 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7141 for (i = 0; i < count; ++i) {
7142 MonoIMTCheckItem *item = imt_entries [i];
7143 #ifdef USE_JUMP_TABLES
7144 guint32 imt_method_jti = 0, target_code_jti = 0;
7146 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7148 gint32 vtable_offset;
7150 item->code_target = (guint8*)code;
7152 if (item->is_equals) {
7153 gboolean fail_case = !item->check_target_idx && fail_tramp;
7155 if (item->check_target_idx || fail_case) {
7156 if (!item->compare_done || fail_case) {
7157 #ifdef USE_JUMP_TABLES
7158 imt_method_jti = IMT_METHOD_JTI (i);
7159 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7162 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7164 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7166 #ifdef USE_JUMP_TABLES
7167 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7168 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7169 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7171 item->jmp_code = (guint8*)code;
7172 ARM_B_COND (code, ARMCOND_NE, 0);
7175 /*Enable the commented code to assert on wrong method*/
7176 #ifdef ENABLE_WRONG_METHOD_CHECK
7177 #ifdef USE_JUMP_TABLES
7178 imt_method_jti = IMT_METHOD_JTI (i);
7179 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7182 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7184 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7186 ARM_B_COND (code, ARMCOND_EQ, 0);
7188 /* Define this if your system is so bad that gdb is failing. */
7189 #ifdef BROKEN_DEV_ENV
7190 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7192 arm_patch (code - 1, mini_dump_bad_imt);
7196 arm_patch (cond, code);
7200 if (item->has_target_code) {
7201 /* Load target address */
7202 #ifdef USE_JUMP_TABLES
7203 target_code_jti = TARGET_CODE_JTI (i);
7204 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7205 /* Restore registers */
7206 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7207 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7209 ARM_BX (code, ARMREG_R1);
7210 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7212 target_code_ins = code;
7213 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7214 /* Save it to the fourth slot */
7215 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7216 /* Restore registers and branch */
7217 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7219 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7222 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7223 if (!arm_is_imm12 (vtable_offset)) {
7225 * We need to branch to a computed address but we don't have
7226 * a free register to store it, since IP must contain the
7227 * vtable address. So we push the two values to the stack, and
7228 * load them both using LDM.
7230 /* Compute target address */
7231 #ifdef USE_JUMP_TABLES
7232 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7233 if (vtable_offset >> 16)
7234 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7235 /* IP had vtable base. */
7236 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7237 /* Restore registers and branch */
7238 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7239 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7240 ARM_BX (code, ARMREG_IP);
7242 vtable_offset_ins = code;
7243 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7244 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7245 /* Save it to the fourth slot */
7246 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7247 /* Restore registers and branch */
7248 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7250 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7253 #ifdef USE_JUMP_TABLES
7254 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7255 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7256 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7257 ARM_BX (code, ARMREG_IP);
7259 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7260 if (large_offsets) {
7261 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7262 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7264 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7265 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7271 #ifdef USE_JUMP_TABLES
7272 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7273 target_code_jti = TARGET_CODE_JTI (i);
7274 /* Load target address */
7275 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7276 /* Restore registers */
7277 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7278 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7280 ARM_BX (code, ARMREG_R1);
7281 set_jumptable_element (jte, target_code_jti, fail_tramp);
7283 arm_patch (item->jmp_code, (guchar*)code);
7285 target_code_ins = code;
7286 /* Load target address */
7287 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7288 /* Save it to the fourth slot */
7289 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7290 /* Restore registers and branch */
7291 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7293 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7295 item->jmp_code = NULL;
7298 #ifdef USE_JUMP_TABLES
7300 set_jumptable_element (jte, imt_method_jti, item->key);
7303 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7305 /*must emit after unconditional branch*/
7306 if (vtable_target) {
7307 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7308 item->chunk_size += 4;
7309 vtable_target = NULL;
7312 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7313 constant_pool_starts [i] = code;
7315 code += extra_space;
7320 #ifdef USE_JUMP_TABLES
7321 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7322 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7323 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7324 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7325 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7327 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7328 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7330 item->jmp_code = (guint8*)code;
7331 ARM_B_COND (code, ARMCOND_HS, 0);
7337 for (i = 0; i < count; ++i) {
7338 MonoIMTCheckItem *item = imt_entries [i];
7339 if (item->jmp_code) {
7340 if (item->check_target_idx)
7341 #ifdef USE_JUMP_TABLES
7342 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7344 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7347 if (i > 0 && item->is_equals) {
7349 #ifdef USE_JUMP_TABLES
7350 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7351 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7353 arminstr_t *space_start = constant_pool_starts [i];
7354 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7355 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7363 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7364 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7369 #ifndef USE_JUMP_TABLES
7370 g_free (constant_pool_starts);
7373 mono_arch_flush_icache ((guint8*)start, size);
7374 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7375 mono_stats.imt_thunks_size += code - start;
7377 g_assert (DISTANCE (start, code) <= size);
7379 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7385 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7387 return ctx->regs [reg];
7391 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7393 ctx->regs [reg] = val;
7397 * mono_arch_get_trampolines:
7399 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7403 mono_arch_get_trampolines (gboolean aot)
7405 return mono_arm_get_exception_trampolines (aot);
7409 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7416 bp = MONO_CONTEXT_GET_BP (ctx);
7417 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7419 old_value = *lr_loc;
7420 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7423 *lr_loc = new_value;
7428 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7430 * mono_arch_set_breakpoint:
7432 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7433 * The location should contain code emitted by OP_SEQ_POINT.
7436 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7439 guint32 native_offset = ip - (guint8*)ji->code_start;
7440 MonoDebugOptions *opt = mini_get_debug_options ();
7442 if (opt->soft_breakpoints) {
7443 g_assert (!ji->from_aot);
7445 ARM_BLX_REG (code, ARMREG_LR);
7446 mono_arch_flush_icache (code - 4, 4);
7447 } else if (ji->from_aot) {
7448 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7450 g_assert (native_offset % 4 == 0);
7451 g_assert (info->bp_addrs [native_offset / 4] == 0);
7452 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7454 int dreg = ARMREG_LR;
7456 /* Read from another trigger page */
7457 #ifdef USE_JUMP_TABLES
7458 gpointer *jte = mono_jumptable_add_entry ();
7459 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7460 jte [0] = bp_trigger_page;
7462 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7464 *(int*)code = (int)bp_trigger_page;
7467 ARM_LDR_IMM (code, dreg, dreg, 0);
7469 mono_arch_flush_icache (code - 16, 16);
7472 /* This is currently implemented by emitting an SWI instruction, which
7473 * qemu/linux seems to convert to a SIGILL.
7475 *(int*)code = (0xef << 24) | 8;
7477 mono_arch_flush_icache (code - 4, 4);
7483 * mono_arch_clear_breakpoint:
7485 * Clear the breakpoint at IP.
7488 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7490 MonoDebugOptions *opt = mini_get_debug_options ();
7494 if (opt->soft_breakpoints) {
7495 g_assert (!ji->from_aot);
7498 mono_arch_flush_icache (code - 4, 4);
7499 } else if (ji->from_aot) {
7500 guint32 native_offset = ip - (guint8*)ji->code_start;
7501 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7503 g_assert (native_offset % 4 == 0);
7504 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7505 info->bp_addrs [native_offset / 4] = 0;
7507 for (i = 0; i < 4; ++i)
7510 mono_arch_flush_icache (ip, code - ip);
7515 * mono_arch_start_single_stepping:
7517 * Start single stepping.
7520 mono_arch_start_single_stepping (void)
7522 if (ss_trigger_page)
7523 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7529 * mono_arch_stop_single_stepping:
7531 * Stop single stepping.
7534 mono_arch_stop_single_stepping (void)
7536 if (ss_trigger_page)
7537 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7543 #define DBG_SIGNAL SIGBUS
7545 #define DBG_SIGNAL SIGSEGV
7549 * mono_arch_is_single_step_event:
7551 * Return whenever the machine state in SIGCTX corresponds to a single
7555 mono_arch_is_single_step_event (void *info, void *sigctx)
7557 siginfo_t *sinfo = info;
7559 if (!ss_trigger_page)
7562 /* Sometimes the address is off by 4 */
7563 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7570 * mono_arch_is_breakpoint_event:
7572 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7575 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7577 siginfo_t *sinfo = info;
7579 if (!ss_trigger_page)
7582 if (sinfo->si_signo == DBG_SIGNAL) {
7583 /* Sometimes the address is off by 4 */
7584 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7594 * mono_arch_skip_breakpoint:
7596 * See mini-amd64.c for docs.
7599 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7601 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7605 * mono_arch_skip_single_step:
7607 * See mini-amd64.c for docs.
7610 mono_arch_skip_single_step (MonoContext *ctx)
7612 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7615 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7618 * mono_arch_get_seq_point_info:
7620 * See mini-amd64.c for docs.
7623 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7628 // FIXME: Add a free function
7630 mono_domain_lock (domain);
7631 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7633 mono_domain_unlock (domain);
7636 ji = mono_jit_info_table_find (domain, (char*)code);
7639 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7641 info->ss_trigger_page = ss_trigger_page;
7642 info->bp_trigger_page = bp_trigger_page;
7644 mono_domain_lock (domain);
7645 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7647 mono_domain_unlock (domain);
7654 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7656 ext->lmf.previous_lmf = prev_lmf;
7657 /* Mark that this is a MonoLMFExt */
7658 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7659 ext->lmf.sp = (gssize)ext;
7663 * mono_arch_set_target:
7665 * Set the target architecture the JIT backend should generate code for, in the form
7666 * of a GNU target triplet. Only used in AOT mode.
7669 mono_arch_set_target (char *mtriple)
7671 /* The GNU target triple format is not very well documented */
7672 if (strstr (mtriple, "armv7")) {
7673 v5_supported = TRUE;
7674 v6_supported = TRUE;
7675 v7_supported = TRUE;
7677 if (strstr (mtriple, "armv6")) {
7678 v5_supported = TRUE;
7679 v6_supported = TRUE;
7681 if (strstr (mtriple, "armv7s")) {
7682 v7s_supported = TRUE;
7684 if (strstr (mtriple, "armv7k")) {
7685 v7k_supported = TRUE;
7687 if (strstr (mtriple, "thumbv7s")) {
7688 v5_supported = TRUE;
7689 v6_supported = TRUE;
7690 v7_supported = TRUE;
7691 v7s_supported = TRUE;
7692 thumb_supported = TRUE;
7693 thumb2_supported = TRUE;
7695 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7696 v5_supported = TRUE;
7697 v6_supported = TRUE;
7698 thumb_supported = TRUE;
7701 if (strstr (mtriple, "gnueabi"))
7702 eabi_supported = TRUE;
7706 mono_arch_opcode_supported (int opcode)
7709 case OP_ATOMIC_ADD_I4:
7710 case OP_ATOMIC_EXCHANGE_I4:
7711 case OP_ATOMIC_CAS_I4:
7712 case OP_ATOMIC_LOAD_I1:
7713 case OP_ATOMIC_LOAD_I2:
7714 case OP_ATOMIC_LOAD_I4:
7715 case OP_ATOMIC_LOAD_U1:
7716 case OP_ATOMIC_LOAD_U2:
7717 case OP_ATOMIC_LOAD_U4:
7718 case OP_ATOMIC_STORE_I1:
7719 case OP_ATOMIC_STORE_I2:
7720 case OP_ATOMIC_STORE_I4:
7721 case OP_ATOMIC_STORE_U1:
7722 case OP_ATOMIC_STORE_U2:
7723 case OP_ATOMIC_STORE_U4:
7724 return v7_supported;
7725 case OP_ATOMIC_LOAD_R4:
7726 case OP_ATOMIC_LOAD_R8:
7727 case OP_ATOMIC_STORE_R4:
7728 case OP_ATOMIC_STORE_R8:
7729 return v7_supported && IS_VFP;
7735 #if defined(ENABLE_GSHAREDVT)
7737 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7739 #endif /* !MONOTOUCH */