2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/appdomain.h>
16 #include <mono/metadata/debug-helpers.h>
17 #include <mono/utils/mono-mmap.h>
23 #include "debugger-agent.h"
25 #include "mono/arch/arm/arm-fpa-codegen.h"
26 #include "mono/arch/arm/arm-vfp-codegen.h"
28 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
29 #define HAVE_AEABI_READ_TP 1
32 #ifdef ARM_FPU_VFP_HARD
48 #ifdef MONO_ARCH_SOFT_FLOAT
49 #define IS_SOFT_FLOAT 1
51 #define IS_SOFT_FLOAT 0
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
57 void sys_icache_invalidate (void *start, size_t len);
60 static gint lmf_tls_offset = -1;
61 static gint lmf_addr_tls_offset = -1;
63 /* This mutex protects architecture specific caches */
64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
66 static CRITICAL_SECTION mini_arch_mutex;
68 static int v5_supported = 0;
69 static int v6_supported = 0;
70 static int v7_supported = 0;
71 static int thumb_supported = 0;
73 * Whenever to use the ARM EABI
75 static int eabi_supported = 0;
78 * Whenever we are on arm/darwin aka the iphone.
80 static int darwin = 0;
82 * Whenever to use the iphone ABI extensions:
83 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
84 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
85 * This is required for debugging/profiling tools to work, but it has some overhead so it should
86 * only be turned on in debug builds.
88 static int iphone_abi = 0;
91 * The FPU we are generating code for. This is NOT runtime configurable right now,
92 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
94 static MonoArmFPU arm_fpu;
98 static volatile int ss_trigger_var = 0;
100 static gpointer single_step_func_wrapper;
101 static gpointer breakpoint_func_wrapper;
104 * The code generated for sequence points reads from this location, which is
105 * made read-only when single stepping is enabled.
107 static gpointer ss_trigger_page;
109 /* Enabled breakpoints read from this trigger page */
110 static gpointer bp_trigger_page;
112 /* Structure used by the sequence points in AOTed code */
114 gpointer ss_trigger_page;
115 gpointer bp_trigger_page;
116 guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
121 * floating point support: on ARM it is a mess, there are at least 3
122 * different setups, each of which binary incompat with the other.
123 * 1) FPA: old and ugly, but unfortunately what current distros use
124 * the double binary format has the two words swapped. 8 double registers.
125 * Implemented usually by kernel emulation.
126 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
127 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
128 * 3) VFP: the new and actually sensible and useful FP support. Implemented
129 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
131 * The plan is to write the FPA support first. softfloat can be tested in a chroot.
133 int mono_exc_esp_offset = 0;
135 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
136 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
137 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
139 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
140 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
141 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
143 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
144 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) | (ARMREG_LR << 12) | ARMREG_PC)
147 /* A variant of ARM_LDR_IMM which can handle large offsets */
148 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
149 if (arm_is_imm12 ((offset))) { \
150 ARM_LDR_IMM (code, (dreg), (basereg), (offset)); \
152 g_assert ((scratch_reg) != (basereg)); \
153 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
154 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
158 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
159 if (arm_is_imm12 ((offset))) { \
160 ARM_STR_IMM (code, (dreg), (basereg), (offset)); \
162 g_assert ((scratch_reg) != (basereg)); \
163 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
164 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
168 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
171 mono_arch_regname (int reg)
173 static const char * rnames[] = {
174 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
175 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
176 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
179 if (reg >= 0 && reg < 16)
185 mono_arch_fregname (int reg)
187 static const char * rnames[] = {
188 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
189 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
190 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
191 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
192 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
193 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
196 if (reg >= 0 && reg < 32)
204 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
206 int imm8, rot_amount;
207 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
208 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
211 g_assert (dreg != sreg);
212 code = mono_arm_emit_load_imm (code, dreg, imm);
213 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
218 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
220 /* we can use r0-r3, since this is called only for incoming args on the stack */
221 if (size > sizeof (gpointer) * 4) {
223 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
224 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
225 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
226 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
227 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
228 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
229 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
230 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
231 ARM_B_COND (code, ARMCOND_NE, 0);
232 arm_patch (code - 4, start_loop);
235 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
236 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
238 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
239 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
245 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
246 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
247 doffset = soffset = 0;
249 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
250 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
256 g_assert (size == 0);
261 emit_call_reg (guint8 *code, int reg)
264 ARM_BLX_REG (code, reg);
266 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
270 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
276 emit_call_seq (MonoCompile *cfg, guint8 *code)
278 if (cfg->method->dynamic) {
279 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
281 *(gpointer*)code = NULL;
283 code = emit_call_reg (code, ARMREG_IP);
291 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
293 switch (ins->opcode) {
296 case OP_FCALL_MEMBASE:
298 if (ins->dreg != ARM_FPA_F0)
299 ARM_FPA_MVFD (code, ins->dreg, ARM_FPA_F0);
301 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
302 ARM_FMSR (code, ins->dreg, ARMREG_R0);
303 ARM_CVTS (code, ins->dreg, ins->dreg);
305 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
317 * Emit code to push an LMF structure on the LMF stack.
318 * On arm, this is intermixed with the initialization of other fields of the structure.
321 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
323 gboolean get_lmf_fast = FALSE;
326 #ifdef HAVE_AEABI_READ_TP
327 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
329 if (lmf_addr_tls_offset != -1) {
332 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
333 (gpointer)"__aeabi_read_tp");
334 code = emit_call_seq (cfg, code);
336 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
341 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
342 (gpointer)"mono_get_lmf_addr");
343 code = emit_call_seq (cfg, code);
345 /* we build the MonoLMF structure on the stack - see mini-arm.h */
346 /* lmf_offset is the offset from the previous stack pointer,
347 * alloc_size is the total stack space allocated, so the offset
348 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
349 * The pointer to the struct is put in r1 (new_lmf).
350 * ip is used as scratch
351 * The callee-saved registers are already in the MonoLMF structure
353 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
354 /* r0 is the result from mono_get_lmf_addr () */
355 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
356 /* new_lmf->previous_lmf = *lmf_addr */
357 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
358 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
359 /* *(lmf_addr) = r1 */
360 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
361 /* Skip method (only needed for trampoline LMF frames) */
362 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, sp));
363 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, fp));
364 /* save the current IP */
365 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
366 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ip));
368 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
369 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
377 * Emit code to pop an LMF structure from the LMF stack.
380 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
384 if (lmf_offset < 32) {
385 basereg = cfg->frame_reg;
390 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
393 /* ip = previous_lmf */
394 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
396 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
397 /* *(lmf_addr) = previous_lmf */
398 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
403 #endif /* #ifndef DISABLE_JIT */
406 * mono_arch_get_argument_info:
407 * @csig: a method signature
408 * @param_count: the number of parameters to consider
409 * @arg_info: an array to store the result infos
411 * Gathers information on parameters such as size, alignment and
412 * padding. arg_info should be large enought to hold param_count + 1 entries.
414 * Returns the size of the activation frame.
417 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
419 int k, frame_size = 0;
420 guint32 size, align, pad;
424 t = mini_type_get_underlying_type (gsctx, csig->ret);
425 if (MONO_TYPE_ISSTRUCT (t)) {
426 frame_size += sizeof (gpointer);
430 arg_info [0].offset = offset;
433 frame_size += sizeof (gpointer);
437 arg_info [0].size = frame_size;
439 for (k = 0; k < param_count; k++) {
440 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
442 /* ignore alignment for now */
445 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
446 arg_info [k].pad = pad;
448 arg_info [k + 1].pad = 0;
449 arg_info [k + 1].size = size;
451 arg_info [k + 1].offset = offset;
455 align = MONO_ARCH_FRAME_ALIGNMENT;
456 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
457 arg_info [k].pad = pad;
462 #define MAX_ARCH_DELEGATE_PARAMS 3
465 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
467 guint8 *code, *start;
470 start = code = mono_global_codeman_reserve (12);
472 /* Replace the this argument with the target */
473 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
474 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
475 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
477 g_assert ((code - start) <= 12);
479 mono_arch_flush_icache (start, 12);
483 size = 8 + param_count * 4;
484 start = code = mono_global_codeman_reserve (size);
486 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
487 /* slide down the arguments */
488 for (i = 0; i < param_count; ++i) {
489 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
491 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
493 g_assert ((code - start) <= size);
495 mono_arch_flush_icache (start, size);
499 *code_size = code - start;
505 * mono_arch_get_delegate_invoke_impls:
507 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
511 mono_arch_get_delegate_invoke_impls (void)
518 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
519 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
521 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
522 code = get_delegate_invoke_impl (FALSE, i, &code_len);
523 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
530 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
532 guint8 *code, *start;
534 /* FIXME: Support more cases */
535 if (MONO_TYPE_ISSTRUCT (sig->ret))
539 static guint8* cached = NULL;
540 mono_mini_arch_lock ();
542 mono_mini_arch_unlock ();
547 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
549 start = get_delegate_invoke_impl (TRUE, 0, NULL);
551 mono_mini_arch_unlock ();
554 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
557 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
559 for (i = 0; i < sig->param_count; ++i)
560 if (!mono_is_regsize_var (sig->params [i]))
563 mono_mini_arch_lock ();
564 code = cache [sig->param_count];
566 mono_mini_arch_unlock ();
571 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
572 start = mono_aot_get_trampoline (name);
575 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
577 cache [sig->param_count] = start;
578 mono_mini_arch_unlock ();
586 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
588 return (gpointer)regs [ARMREG_R0];
592 * Initialize the cpu to execute managed code.
595 mono_arch_cpu_init (void)
597 #if defined(__ARM_EABI__)
598 eabi_supported = TRUE;
600 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
603 i8_align = __alignof__ (gint64);
608 create_function_wrapper (gpointer function)
610 guint8 *start, *code;
612 start = code = mono_global_codeman_reserve (96);
615 * Construct the MonoContext structure on the stack.
618 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, sizeof (MonoContext));
620 /* save ip, lr and pc into their correspodings ctx.regs slots. */
621 ARM_STR_IMM (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + sizeof (mgreg_t) * ARMREG_IP);
622 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
623 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
625 /* save r0..r10 and fp */
626 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs));
627 ARM_STM (code, ARMREG_IP, 0x0fff);
629 /* now we can update fp. */
630 ARM_MOV_REG_REG (code, ARMREG_FP, ARMREG_SP);
632 /* make ctx.esp hold the actual value of sp at the beginning of this method. */
633 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_FP, sizeof (MonoContext));
634 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, 4 * ARMREG_SP);
635 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_SP);
637 /* make ctx.eip hold the address of the call. */
638 ARM_SUB_REG_IMM8 (code, ARMREG_LR, ARMREG_LR, 4);
639 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, pc));
641 /* r0 now points to the MonoContext */
642 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_FP);
645 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
647 *(gpointer*)code = function;
649 ARM_BLX_REG (code, ARMREG_IP);
651 /* we're back; save ctx.eip and ctx.esp into the corresponding regs slots. */
652 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, pc));
653 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
654 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
656 /* make ip point to the regs array, then restore everything, including pc. */
657 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs));
658 ARM_LDM (code, ARMREG_IP, 0xffff);
660 mono_arch_flush_icache (start, code - start);
666 * Initialize architecture specific code.
669 mono_arch_init (void)
671 InitializeCriticalSection (&mini_arch_mutex);
673 if (mini_get_debug_options ()->soft_breakpoints) {
674 single_step_func_wrapper = create_function_wrapper (debugger_agent_single_step_from_context);
675 breakpoint_func_wrapper = create_function_wrapper (debugger_agent_breakpoint_from_context);
677 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
678 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
679 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
682 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
683 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
684 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
685 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
686 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
690 arm_fpu = MONO_ARM_FPU_FPA;
691 #elif defined(ARM_FPU_VFP_HARD)
692 arm_fpu = MONO_ARM_FPU_VFP_HARD;
693 #elif defined(ARM_FPU_VFP)
694 arm_fpu = MONO_ARM_FPU_VFP;
696 arm_fpu = MONO_ARM_FPU_NONE;
701 * Cleanup architecture specific code.
704 mono_arch_cleanup (void)
709 * This function returns the optimizations supported on this cpu.
712 mono_arch_cpu_optimizations (guint32 *exclude_mask)
715 const char *cpu_arch = getenv ("MONO_CPU_ARCH");
716 if (cpu_arch != NULL) {
717 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
718 if (strncmp (cpu_arch, "armv", 4) == 0) {
719 v5_supported = cpu_arch [4] >= '5';
720 v6_supported = cpu_arch [4] >= '6';
721 v7_supported = cpu_arch [4] >= '7';
725 thumb_supported = TRUE;
732 FILE *file = fopen ("/proc/cpuinfo", "r");
734 while ((line = fgets (buf, 512, file))) {
735 if (strncmp (line, "Processor", 9) == 0) {
736 char *ver = strstr (line, "(v");
737 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
739 if (ver && (ver [2] == '6' || ver [2] == '7'))
741 if (ver && (ver [2] == '7'))
745 if (strncmp (line, "Features", 8) == 0) {
746 char *th = strstr (line, "thumb");
748 thumb_supported = TRUE;
756 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
761 /* no arm-specific optimizations yet */
767 * This function test for all SIMD functions supported.
769 * Returns a bitmask corresponding to all supported versions.
773 mono_arch_cpu_enumerate_simd_versions (void)
775 /* SIMD is currently unimplemented */
783 is_regsize_var (MonoGenericSharingContext *gsctx, MonoType *t) {
786 t = mini_type_get_underlying_type (gsctx, t);
793 case MONO_TYPE_FNPTR:
795 case MONO_TYPE_OBJECT:
796 case MONO_TYPE_STRING:
797 case MONO_TYPE_CLASS:
798 case MONO_TYPE_SZARRAY:
799 case MONO_TYPE_ARRAY:
801 case MONO_TYPE_GENERICINST:
802 if (!mono_type_generic_inst_is_valuetype (t))
805 case MONO_TYPE_VALUETYPE:
812 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
817 for (i = 0; i < cfg->num_varinfo; i++) {
818 MonoInst *ins = cfg->varinfo [i];
819 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
822 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
825 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
828 /* we can only allocate 32 bit values */
829 if (is_regsize_var (cfg->generic_sharing_context, ins->inst_vtype)) {
830 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
831 g_assert (i == vmv->idx);
832 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
839 #define USE_EXTRA_TEMPS 0
842 mono_arch_get_global_int_regs (MonoCompile *cfg)
846 mono_arch_compute_omit_fp (cfg);
849 * FIXME: Interface calls might go through a static rgctx trampoline which
850 * sets V5, but it doesn't save it, so we need to save it ourselves, and
853 if (cfg->flags & MONO_CFG_HAS_CALLS)
854 cfg->uses_rgctx_reg = TRUE;
856 if (cfg->arch.omit_fp)
857 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
858 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
859 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
860 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
862 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
863 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
865 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
866 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
867 /* V5 is reserved for passing the vtable/rgctx/IMT method */
868 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
869 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
870 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
876 * mono_arch_regalloc_cost:
878 * Return the cost, in number of memory references, of the action of
879 * allocating the variable VMV into a register during global register
883 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
889 #endif /* #ifndef DISABLE_JIT */
891 #ifndef __GNUC_PREREQ
892 #define __GNUC_PREREQ(maj, min) (0)
896 mono_arch_flush_icache (guint8 *code, gint size)
898 #ifdef MONO_CROSS_COMPILE
900 sys_icache_invalidate (code, size);
901 #elif __GNUC_PREREQ(4, 1)
902 __clear_cache (code, code + size);
903 #elif defined(PLATFORM_ANDROID)
904 const int syscall = 0xf0002;
912 : "r" (code), "r" (code + size), "r" (syscall)
913 : "r0", "r1", "r7", "r2"
916 __asm __volatile ("mov r0, %0\n"
919 "swi 0x9f0002 @ sys_cacheflush"
921 : "r" (code), "r" (code + size), "r" (0)
922 : "r0", "r1", "r3" );
939 guint16 vtsize; /* in param area */
943 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
949 gboolean vtype_retaddr;
950 /* The index of the vret arg in the argument list */
960 /*#define __alignof__(a) sizeof(a)*/
961 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
967 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
970 if (*gr > ARMREG_R3) {
971 ainfo->offset = *stack_size;
972 ainfo->reg = ARMREG_SP; /* in the caller */
973 ainfo->storage = RegTypeBase;
976 ainfo->storage = RegTypeGeneral;
983 split = i8_align == 4;
987 if (*gr == ARMREG_R3 && split) {
988 /* first word in r3 and the second on the stack */
989 ainfo->offset = *stack_size;
990 ainfo->reg = ARMREG_SP; /* in the caller */
991 ainfo->storage = RegTypeBaseGen;
993 } else if (*gr >= ARMREG_R3) {
994 if (eabi_supported) {
995 /* darwin aligns longs to 4 byte only */
1001 ainfo->offset = *stack_size;
1002 ainfo->reg = ARMREG_SP; /* in the caller */
1003 ainfo->storage = RegTypeBase;
1006 if (eabi_supported) {
1007 if (i8_align == 8 && ((*gr) & 1))
1010 ainfo->storage = RegTypeIRegPair;
1019 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
1021 guint i, gr, pstart;
1022 int n = sig->hasthis + sig->param_count;
1023 MonoType *simpletype;
1024 guint32 stack_size = 0;
1026 gboolean is_pinvoke = sig->pinvoke;
1030 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1032 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1037 /* FIXME: handle returning a struct */
1038 t = mini_type_get_underlying_type (gsctx, sig->ret);
1039 if (MONO_TYPE_ISSTRUCT (t)) {
1042 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer)) {
1043 cinfo->ret.storage = RegTypeStructByVal;
1045 cinfo->vtype_retaddr = TRUE;
1052 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1053 * the first argument, allowing 'this' to be always passed in the first arg reg.
1054 * Also do this if the first argument is a reference type, since virtual calls
1055 * are sometimes made using calli without sig->hasthis set, like in the delegate
1058 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1060 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1062 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1066 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1067 cinfo->vret_arg_index = 1;
1071 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1075 if (cinfo->vtype_retaddr)
1076 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1079 DEBUG(printf("params: %d\n", sig->param_count));
1080 for (i = pstart; i < sig->param_count; ++i) {
1081 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1082 /* Prevent implicit arguments and sig_cookie from
1083 being passed in registers */
1085 /* Emit the signature cookie just before the implicit arguments */
1086 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1088 DEBUG(printf("param %d: ", i));
1089 if (sig->params [i]->byref) {
1090 DEBUG(printf("byref\n"));
1091 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1095 simpletype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1096 switch (simpletype->type) {
1097 case MONO_TYPE_BOOLEAN:
1100 cinfo->args [n].size = 1;
1101 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1104 case MONO_TYPE_CHAR:
1107 cinfo->args [n].size = 2;
1108 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1113 cinfo->args [n].size = 4;
1114 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1120 case MONO_TYPE_FNPTR:
1121 case MONO_TYPE_CLASS:
1122 case MONO_TYPE_OBJECT:
1123 case MONO_TYPE_STRING:
1124 case MONO_TYPE_SZARRAY:
1125 case MONO_TYPE_ARRAY:
1127 cinfo->args [n].size = sizeof (gpointer);
1128 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1131 case MONO_TYPE_GENERICINST:
1132 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1133 cinfo->args [n].size = sizeof (gpointer);
1134 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1139 case MONO_TYPE_TYPEDBYREF:
1140 case MONO_TYPE_VALUETYPE: {
1146 if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1147 size = sizeof (MonoTypedRef);
1148 align = sizeof (gpointer);
1150 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1152 size = mono_class_native_size (klass, &align);
1154 size = mini_type_stack_size_full (gsctx, simpletype, &align, FALSE);
1156 DEBUG(printf ("load %d bytes struct\n", size));
1159 align_size += (sizeof (gpointer) - 1);
1160 align_size &= ~(sizeof (gpointer) - 1);
1161 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1162 cinfo->args [n].storage = RegTypeStructByVal;
1163 cinfo->args [n].struct_size = size;
1164 /* FIXME: align stack_size if needed */
1165 if (eabi_supported) {
1166 if (align >= 8 && (gr & 1))
1169 if (gr > ARMREG_R3) {
1170 cinfo->args [n].size = 0;
1171 cinfo->args [n].vtsize = nwords;
1173 int rest = ARMREG_R3 - gr + 1;
1174 int n_in_regs = rest >= nwords? nwords: rest;
1176 cinfo->args [n].size = n_in_regs;
1177 cinfo->args [n].vtsize = nwords - n_in_regs;
1178 cinfo->args [n].reg = gr;
1180 nwords -= n_in_regs;
1182 cinfo->args [n].offset = stack_size;
1183 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1184 stack_size += nwords * sizeof (gpointer);
1191 cinfo->args [n].size = 8;
1192 add_general (&gr, &stack_size, cinfo->args + n, FALSE);
1196 g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1200 /* Handle the case where there are no implicit arguments */
1201 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1202 /* Prevent implicit arguments and sig_cookie from
1203 being passed in registers */
1205 /* Emit the signature cookie just before the implicit arguments */
1206 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1210 simpletype = mini_type_get_underlying_type (gsctx, sig->ret);
1211 switch (simpletype->type) {
1212 case MONO_TYPE_BOOLEAN:
1217 case MONO_TYPE_CHAR:
1223 case MONO_TYPE_FNPTR:
1224 case MONO_TYPE_CLASS:
1225 case MONO_TYPE_OBJECT:
1226 case MONO_TYPE_SZARRAY:
1227 case MONO_TYPE_ARRAY:
1228 case MONO_TYPE_STRING:
1229 cinfo->ret.storage = RegTypeGeneral;
1230 cinfo->ret.reg = ARMREG_R0;
1234 cinfo->ret.storage = RegTypeIRegPair;
1235 cinfo->ret.reg = ARMREG_R0;
1239 cinfo->ret.storage = RegTypeFP;
1240 cinfo->ret.reg = ARMREG_R0;
1241 /* FIXME: cinfo->ret.reg = ???;
1242 cinfo->ret.storage = RegTypeFP;*/
1244 case MONO_TYPE_GENERICINST:
1245 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1246 cinfo->ret.storage = RegTypeGeneral;
1247 cinfo->ret.reg = ARMREG_R0;
1251 case MONO_TYPE_VALUETYPE:
1252 case MONO_TYPE_TYPEDBYREF:
1253 if (cinfo->ret.storage != RegTypeStructByVal)
1254 cinfo->ret.storage = RegTypeStructByAddr;
1256 case MONO_TYPE_VOID:
1259 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1263 /* align stack size to 8 */
1264 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1265 stack_size = (stack_size + 7) & ~7;
1267 cinfo->stack_usage = stack_size;
1274 debug_omit_fp (void)
1277 return mono_debug_count ();
1284 * mono_arch_compute_omit_fp:
1286 * Determine whenever the frame pointer can be eliminated.
1289 mono_arch_compute_omit_fp (MonoCompile *cfg)
1291 MonoMethodSignature *sig;
1292 MonoMethodHeader *header;
1296 if (cfg->arch.omit_fp_computed)
1299 header = cfg->header;
1301 sig = mono_method_signature (cfg->method);
1303 if (!cfg->arch.cinfo)
1304 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1305 cinfo = cfg->arch.cinfo;
1308 * FIXME: Remove some of the restrictions.
1310 cfg->arch.omit_fp = TRUE;
1311 cfg->arch.omit_fp_computed = TRUE;
1313 if (cfg->disable_omit_fp)
1314 cfg->arch.omit_fp = FALSE;
1315 if (!debug_omit_fp ())
1316 cfg->arch.omit_fp = FALSE;
1318 if (cfg->method->save_lmf)
1319 cfg->arch.omit_fp = FALSE;
1321 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1322 cfg->arch.omit_fp = FALSE;
1323 if (header->num_clauses)
1324 cfg->arch.omit_fp = FALSE;
1325 if (cfg->param_area)
1326 cfg->arch.omit_fp = FALSE;
1327 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1328 cfg->arch.omit_fp = FALSE;
1329 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1330 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1331 cfg->arch.omit_fp = FALSE;
1332 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1333 ArgInfo *ainfo = &cinfo->args [i];
1335 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1337 * The stack offset can only be determined when the frame
1340 cfg->arch.omit_fp = FALSE;
1345 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1346 MonoInst *ins = cfg->varinfo [i];
1349 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1354 * Set var information according to the calling convention. arm version.
1355 * The locals var stuff should most likely be split in another method.
1358 mono_arch_allocate_vars (MonoCompile *cfg)
1360 MonoMethodSignature *sig;
1361 MonoMethodHeader *header;
1363 int i, offset, size, align, curinst;
1367 sig = mono_method_signature (cfg->method);
1369 if (!cfg->arch.cinfo)
1370 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1371 cinfo = cfg->arch.cinfo;
1373 mono_arch_compute_omit_fp (cfg);
1375 if (cfg->arch.omit_fp)
1376 cfg->frame_reg = ARMREG_SP;
1378 cfg->frame_reg = ARMREG_FP;
1380 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1382 /* allow room for the vararg method args: void* and long/double */
1383 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1384 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1386 header = cfg->header;
1388 /* See mono_arch_get_global_int_regs () */
1389 if (cfg->flags & MONO_CFG_HAS_CALLS)
1390 cfg->uses_rgctx_reg = TRUE;
1392 if (cfg->frame_reg != ARMREG_SP)
1393 cfg->used_int_regs |= 1 << cfg->frame_reg;
1395 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1396 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1397 cfg->used_int_regs |= (1 << ARMREG_V5);
1401 if (!MONO_TYPE_ISSTRUCT (sig->ret) && !cinfo->vtype_retaddr) {
1402 if (sig->ret->type != MONO_TYPE_VOID) {
1403 cfg->ret->opcode = OP_REGVAR;
1404 cfg->ret->inst_c0 = ARMREG_R0;
1407 /* local vars are at a positive offset from the stack pointer */
1409 * also note that if the function uses alloca, we use FP
1410 * to point at the local variables.
1412 offset = 0; /* linkage area */
1413 /* align the offset to 16 bytes: not sure this is needed here */
1415 //offset &= ~(8 - 1);
1417 /* add parameter area size for called functions */
1418 offset += cfg->param_area;
1421 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1424 /* allow room to save the return value */
1425 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1428 /* the MonoLMF structure is stored just below the stack pointer */
1429 if (cinfo->ret.storage == RegTypeStructByVal) {
1430 cfg->ret->opcode = OP_REGOFFSET;
1431 cfg->ret->inst_basereg = cfg->frame_reg;
1432 offset += sizeof (gpointer) - 1;
1433 offset &= ~(sizeof (gpointer) - 1);
1434 cfg->ret->inst_offset = - offset;
1435 offset += sizeof(gpointer);
1436 } else if (cinfo->vtype_retaddr) {
1437 ins = cfg->vret_addr;
1438 offset += sizeof(gpointer) - 1;
1439 offset &= ~(sizeof(gpointer) - 1);
1440 ins->inst_offset = offset;
1441 ins->opcode = OP_REGOFFSET;
1442 ins->inst_basereg = cfg->frame_reg;
1443 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1444 printf ("vret_addr =");
1445 mono_print_ins (cfg->vret_addr);
1447 offset += sizeof(gpointer);
1450 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1451 if (cfg->arch.seq_point_info_var) {
1454 ins = cfg->arch.seq_point_info_var;
1458 offset += align - 1;
1459 offset &= ~(align - 1);
1460 ins->opcode = OP_REGOFFSET;
1461 ins->inst_basereg = cfg->frame_reg;
1462 ins->inst_offset = offset;
1465 ins = cfg->arch.ss_trigger_page_var;
1468 offset += align - 1;
1469 offset &= ~(align - 1);
1470 ins->opcode = OP_REGOFFSET;
1471 ins->inst_basereg = cfg->frame_reg;
1472 ins->inst_offset = offset;
1476 if (cfg->arch.seq_point_read_var) {
1479 ins = cfg->arch.seq_point_read_var;
1483 offset += align - 1;
1484 offset &= ~(align - 1);
1485 ins->opcode = OP_REGOFFSET;
1486 ins->inst_basereg = cfg->frame_reg;
1487 ins->inst_offset = offset;
1490 ins = cfg->arch.seq_point_ss_method_var;
1493 offset += align - 1;
1494 offset &= ~(align - 1);
1495 ins->opcode = OP_REGOFFSET;
1496 ins->inst_basereg = cfg->frame_reg;
1497 ins->inst_offset = offset;
1500 ins = cfg->arch.seq_point_bp_method_var;
1503 offset += align - 1;
1504 offset &= ~(align - 1);
1505 ins->opcode = OP_REGOFFSET;
1506 ins->inst_basereg = cfg->frame_reg;
1507 ins->inst_offset = offset;
1511 cfg->locals_min_stack_offset = offset;
1513 curinst = cfg->locals_start;
1514 for (i = curinst; i < cfg->num_varinfo; ++i) {
1517 ins = cfg->varinfo [i];
1518 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1521 t = ins->inst_vtype;
1522 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (cfg, t))
1523 t = mini_get_gsharedvt_alloc_type_for_type (cfg, t);
1525 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1526 * pinvoke wrappers when they call functions returning structure */
1527 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1528 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1532 size = mono_type_size (t, &align);
1534 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1535 * since it loads/stores misaligned words, which don't do the right thing.
1537 if (align < 4 && size >= 4)
1539 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1540 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1541 offset += align - 1;
1542 offset &= ~(align - 1);
1543 ins->opcode = OP_REGOFFSET;
1544 ins->inst_offset = offset;
1545 ins->inst_basereg = cfg->frame_reg;
1547 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1550 cfg->locals_max_stack_offset = offset;
1554 ins = cfg->args [curinst];
1555 if (ins->opcode != OP_REGVAR) {
1556 ins->opcode = OP_REGOFFSET;
1557 ins->inst_basereg = cfg->frame_reg;
1558 offset += sizeof (gpointer) - 1;
1559 offset &= ~(sizeof (gpointer) - 1);
1560 ins->inst_offset = offset;
1561 offset += sizeof (gpointer);
1566 if (sig->call_convention == MONO_CALL_VARARG) {
1570 /* Allocate a local slot to hold the sig cookie address */
1571 offset += align - 1;
1572 offset &= ~(align - 1);
1573 cfg->sig_cookie = offset;
1577 for (i = 0; i < sig->param_count; ++i) {
1578 ins = cfg->args [curinst];
1580 if (ins->opcode != OP_REGVAR) {
1581 ins->opcode = OP_REGOFFSET;
1582 ins->inst_basereg = cfg->frame_reg;
1583 size = mini_type_stack_size_full (cfg->generic_sharing_context, sig->params [i], &ualign, sig->pinvoke);
1585 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1586 * since it loads/stores misaligned words, which don't do the right thing.
1588 if (align < 4 && size >= 4)
1590 /* The code in the prolog () stores words when storing vtypes received in a register */
1591 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1593 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1594 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1595 offset += align - 1;
1596 offset &= ~(align - 1);
1597 ins->inst_offset = offset;
1603 /* align the offset to 8 bytes */
1604 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
1605 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1610 cfg->stack_offset = offset;
1614 mono_arch_create_vars (MonoCompile *cfg)
1616 MonoMethodSignature *sig;
1619 sig = mono_method_signature (cfg->method);
1621 if (!cfg->arch.cinfo)
1622 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1623 cinfo = cfg->arch.cinfo;
1625 if (cinfo->ret.storage == RegTypeStructByVal)
1626 cfg->ret_var_is_local = TRUE;
1628 if (cinfo->vtype_retaddr) {
1629 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1630 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1631 printf ("vret_addr = ");
1632 mono_print_ins (cfg->vret_addr);
1636 if (cfg->gen_seq_points) {
1637 if (cfg->soft_breakpoints) {
1638 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1639 ins->flags |= MONO_INST_VOLATILE;
1640 cfg->arch.seq_point_read_var = ins;
1642 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1643 ins->flags |= MONO_INST_VOLATILE;
1644 cfg->arch.seq_point_ss_method_var = ins;
1646 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1647 ins->flags |= MONO_INST_VOLATILE;
1648 cfg->arch.seq_point_bp_method_var = ins;
1650 g_assert (!cfg->compile_aot);
1651 } else if (cfg->compile_aot) {
1652 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1653 ins->flags |= MONO_INST_VOLATILE;
1654 cfg->arch.seq_point_info_var = ins;
1656 /* Allocate a separate variable for this to save 1 load per seq point */
1657 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1658 ins->flags |= MONO_INST_VOLATILE;
1659 cfg->arch.ss_trigger_page_var = ins;
1665 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1667 MonoMethodSignature *tmp_sig;
1670 if (call->tail_call)
1673 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1676 * mono_ArgIterator_Setup assumes the signature cookie is
1677 * passed first and all the arguments which were before it are
1678 * passed on the stack after the signature. So compensate by
1679 * passing a different signature.
1681 tmp_sig = mono_metadata_signature_dup (call->signature);
1682 tmp_sig->param_count -= call->signature->sentinelpos;
1683 tmp_sig->sentinelpos = 0;
1684 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1686 sig_reg = mono_alloc_ireg (cfg);
1687 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1689 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
1694 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1699 LLVMCallInfo *linfo;
1701 n = sig->param_count + sig->hasthis;
1703 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1705 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1708 * LLVM always uses the native ABI while we use our own ABI, the
1709 * only difference is the handling of vtypes:
1710 * - we only pass/receive them in registers in some cases, and only
1711 * in 1 or 2 integer registers.
1713 if (cinfo->vtype_retaddr) {
1714 /* Vtype returned using a hidden argument */
1715 linfo->ret.storage = LLVMArgVtypeRetAddr;
1716 linfo->vret_arg_index = cinfo->vret_arg_index;
1717 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1718 cfg->exception_message = g_strdup ("unknown ret conv");
1719 cfg->disable_llvm = TRUE;
1723 for (i = 0; i < n; ++i) {
1724 ainfo = cinfo->args + i;
1726 linfo->args [i].storage = LLVMArgNone;
1728 switch (ainfo->storage) {
1729 case RegTypeGeneral:
1730 case RegTypeIRegPair:
1732 linfo->args [i].storage = LLVMArgInIReg;
1734 case RegTypeStructByVal:
1735 // FIXME: Passing entirely on the stack or split reg/stack
1736 if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1737 linfo->args [i].storage = LLVMArgVtypeInReg;
1738 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1739 if (ainfo->size == 2)
1740 linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1742 linfo->args [i].pair_storage [1] = LLVMArgNone;
1744 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1745 cfg->disable_llvm = TRUE;
1749 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1750 cfg->disable_llvm = TRUE;
1760 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1763 MonoMethodSignature *sig;
1767 sig = call->signature;
1768 n = sig->param_count + sig->hasthis;
1770 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1772 for (i = 0; i < n; ++i) {
1773 ArgInfo *ainfo = cinfo->args + i;
1776 if (i >= sig->hasthis)
1777 t = sig->params [i - sig->hasthis];
1779 t = &mono_defaults.int_class->byval_arg;
1780 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1782 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1783 /* Emit the signature cookie just before the implicit arguments */
1784 emit_sig_cookie (cfg, call, cinfo);
1787 in = call->args [i];
1789 switch (ainfo->storage) {
1790 case RegTypeGeneral:
1791 case RegTypeIRegPair:
1792 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1793 MONO_INST_NEW (cfg, ins, OP_MOVE);
1794 ins->dreg = mono_alloc_ireg (cfg);
1795 ins->sreg1 = in->dreg + 1;
1796 MONO_ADD_INS (cfg->cbb, ins);
1797 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1799 MONO_INST_NEW (cfg, ins, OP_MOVE);
1800 ins->dreg = mono_alloc_ireg (cfg);
1801 ins->sreg1 = in->dreg + 2;
1802 MONO_ADD_INS (cfg->cbb, ins);
1803 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1804 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1805 if (ainfo->size == 4) {
1806 if (IS_SOFT_FLOAT) {
1807 /* mono_emit_call_args () have already done the r8->r4 conversion */
1808 /* The converted value is in an int vreg */
1809 MONO_INST_NEW (cfg, ins, OP_MOVE);
1810 ins->dreg = mono_alloc_ireg (cfg);
1811 ins->sreg1 = in->dreg;
1812 MONO_ADD_INS (cfg->cbb, ins);
1813 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1817 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1818 creg = mono_alloc_ireg (cfg);
1819 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1820 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1823 if (IS_SOFT_FLOAT) {
1824 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1825 ins->dreg = mono_alloc_ireg (cfg);
1826 ins->sreg1 = in->dreg;
1827 MONO_ADD_INS (cfg->cbb, ins);
1828 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1830 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1831 ins->dreg = mono_alloc_ireg (cfg);
1832 ins->sreg1 = in->dreg;
1833 MONO_ADD_INS (cfg->cbb, ins);
1834 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1838 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1839 creg = mono_alloc_ireg (cfg);
1840 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1841 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1842 creg = mono_alloc_ireg (cfg);
1843 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1844 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1847 cfg->flags |= MONO_CFG_HAS_FPOUT;
1849 MONO_INST_NEW (cfg, ins, OP_MOVE);
1850 ins->dreg = mono_alloc_ireg (cfg);
1851 ins->sreg1 = in->dreg;
1852 MONO_ADD_INS (cfg->cbb, ins);
1854 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1857 case RegTypeStructByAddr:
1860 /* FIXME: where si the data allocated? */
1861 arg->backend.reg3 = ainfo->reg;
1862 call->used_iregs |= 1 << ainfo->reg;
1863 g_assert_not_reached ();
1866 case RegTypeStructByVal:
1867 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1868 ins->opcode = OP_OUTARG_VT;
1869 ins->sreg1 = in->dreg;
1870 ins->klass = in->klass;
1871 ins->inst_p0 = call;
1872 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1873 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1874 mono_call_inst_add_outarg_vt (cfg, call, ins);
1875 MONO_ADD_INS (cfg->cbb, ins);
1878 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1879 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1880 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1881 if (t->type == MONO_TYPE_R8) {
1882 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1885 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1887 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1890 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1893 case RegTypeBaseGen:
1894 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1895 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1896 MONO_INST_NEW (cfg, ins, OP_MOVE);
1897 ins->dreg = mono_alloc_ireg (cfg);
1898 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1899 MONO_ADD_INS (cfg->cbb, ins);
1900 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1901 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1904 /* This should work for soft-float as well */
1906 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1907 creg = mono_alloc_ireg (cfg);
1908 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1909 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1910 creg = mono_alloc_ireg (cfg);
1911 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1912 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1913 cfg->flags |= MONO_CFG_HAS_FPOUT;
1915 g_assert_not_reached ();
1922 arg->backend.reg3 = ainfo->reg;
1923 /* FP args are passed in int regs */
1924 call->used_iregs |= 1 << ainfo->reg;
1925 if (ainfo->size == 8) {
1926 arg->opcode = OP_OUTARG_R8;
1927 call->used_iregs |= 1 << (ainfo->reg + 1);
1929 arg->opcode = OP_OUTARG_R4;
1932 cfg->flags |= MONO_CFG_HAS_FPOUT;
1936 g_assert_not_reached ();
1940 /* Handle the case where there are no implicit arguments */
1941 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1942 emit_sig_cookie (cfg, call, cinfo);
1944 if (cinfo->ret.storage == RegTypeStructByVal) {
1945 /* The JIT will transform this into a normal call */
1946 call->vret_in_reg = TRUE;
1947 } else if (cinfo->vtype_retaddr) {
1949 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1950 vtarg->sreg1 = call->vret_var->dreg;
1951 vtarg->dreg = mono_alloc_preg (cfg);
1952 MONO_ADD_INS (cfg->cbb, vtarg);
1954 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1957 call->stack_usage = cinfo->stack_usage;
1963 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1965 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1966 ArgInfo *ainfo = ins->inst_p1;
1967 int ovf_size = ainfo->vtsize;
1968 int doffset = ainfo->offset;
1969 int struct_size = ainfo->struct_size;
1970 int i, soffset, dreg, tmpreg;
1973 for (i = 0; i < ainfo->size; ++i) {
1974 dreg = mono_alloc_ireg (cfg);
1975 switch (struct_size) {
1977 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1980 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
1983 tmpreg = mono_alloc_ireg (cfg);
1984 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1985 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
1986 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
1987 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1988 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
1989 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
1990 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1993 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1996 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
1997 soffset += sizeof (gpointer);
1998 struct_size -= sizeof (gpointer);
2000 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2002 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2006 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2008 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2011 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2014 if (COMPILE_LLVM (cfg)) {
2015 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2017 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2018 ins->sreg1 = val->dreg + 1;
2019 ins->sreg2 = val->dreg + 2;
2020 MONO_ADD_INS (cfg->cbb, ins);
2025 case MONO_ARM_FPU_NONE:
2026 if (ret->type == MONO_TYPE_R8) {
2029 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2030 ins->dreg = cfg->ret->dreg;
2031 ins->sreg1 = val->dreg;
2032 MONO_ADD_INS (cfg->cbb, ins);
2035 if (ret->type == MONO_TYPE_R4) {
2036 /* Already converted to an int in method_to_ir () */
2037 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2041 case MONO_ARM_FPU_VFP:
2042 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2045 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2046 ins->dreg = cfg->ret->dreg;
2047 ins->sreg1 = val->dreg;
2048 MONO_ADD_INS (cfg->cbb, ins);
2052 case MONO_ARM_FPU_FPA:
2053 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
2054 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2059 g_assert_not_reached ();
2063 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2066 #endif /* #ifndef DISABLE_JIT */
2069 mono_arch_is_inst_imm (gint64 imm)
2074 #define DYN_CALL_STACK_ARGS 6
2077 MonoMethodSignature *sig;
2082 mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
2088 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2092 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2095 switch (cinfo->ret.storage) {
2097 case RegTypeGeneral:
2098 case RegTypeIRegPair:
2099 case RegTypeStructByAddr:
2112 for (i = 0; i < cinfo->nargs; ++i) {
2113 switch (cinfo->args [i].storage) {
2114 case RegTypeGeneral:
2116 case RegTypeIRegPair:
2119 if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2122 case RegTypeStructByVal:
2123 if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2131 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2132 for (i = 0; i < sig->param_count; ++i) {
2133 MonoType *t = sig->params [i];
2159 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2161 ArchDynCallInfo *info;
2164 cinfo = get_call_info (NULL, NULL, sig);
2166 if (!dyn_call_supported (cinfo, sig)) {
2171 info = g_new0 (ArchDynCallInfo, 1);
2172 // FIXME: Preprocess the info to speed up start_dyn_call ()
2174 info->cinfo = cinfo;
2176 return (MonoDynCallInfo*)info;
2180 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2182 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2184 g_free (ainfo->cinfo);
2189 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2191 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2192 DynCallArgs *p = (DynCallArgs*)buf;
2193 int arg_index, greg, i, j, pindex;
2194 MonoMethodSignature *sig = dinfo->sig;
2196 g_assert (buf_len >= sizeof (DynCallArgs));
2205 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2206 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2211 if (dinfo->cinfo->vtype_retaddr)
2212 p->regs [greg ++] = (mgreg_t)ret;
2214 for (i = pindex; i < sig->param_count; i++) {
2215 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2216 gpointer *arg = args [arg_index ++];
2217 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2220 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2222 else if (ainfo->storage == RegTypeBase)
2223 slot = PARAM_REGS + (ainfo->offset / 4);
2225 g_assert_not_reached ();
2228 p->regs [slot] = (mgreg_t)*arg;
2233 case MONO_TYPE_STRING:
2234 case MONO_TYPE_CLASS:
2235 case MONO_TYPE_ARRAY:
2236 case MONO_TYPE_SZARRAY:
2237 case MONO_TYPE_OBJECT:
2241 p->regs [slot] = (mgreg_t)*arg;
2243 case MONO_TYPE_BOOLEAN:
2245 p->regs [slot] = *(guint8*)arg;
2248 p->regs [slot] = *(gint8*)arg;
2251 p->regs [slot] = *(gint16*)arg;
2254 case MONO_TYPE_CHAR:
2255 p->regs [slot] = *(guint16*)arg;
2258 p->regs [slot] = *(gint32*)arg;
2261 p->regs [slot] = *(guint32*)arg;
2265 p->regs [slot ++] = (mgreg_t)arg [0];
2266 p->regs [slot] = (mgreg_t)arg [1];
2269 p->regs [slot] = *(mgreg_t*)arg;
2272 p->regs [slot ++] = (mgreg_t)arg [0];
2273 p->regs [slot] = (mgreg_t)arg [1];
2275 case MONO_TYPE_GENERICINST:
2276 if (MONO_TYPE_IS_REFERENCE (t)) {
2277 p->regs [slot] = (mgreg_t)*arg;
2282 case MONO_TYPE_VALUETYPE:
2283 g_assert (ainfo->storage == RegTypeStructByVal);
2285 if (ainfo->size == 0)
2286 slot = PARAM_REGS + (ainfo->offset / 4);
2290 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2291 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2294 g_assert_not_reached ();
2300 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2302 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2303 MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2304 guint8 *ret = ((DynCallArgs*)buf)->ret;
2305 mgreg_t res = ((DynCallArgs*)buf)->res;
2306 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2308 switch (mono_type_get_underlying_type (sig->ret)->type) {
2309 case MONO_TYPE_VOID:
2310 *(gpointer*)ret = NULL;
2312 case MONO_TYPE_STRING:
2313 case MONO_TYPE_CLASS:
2314 case MONO_TYPE_ARRAY:
2315 case MONO_TYPE_SZARRAY:
2316 case MONO_TYPE_OBJECT:
2320 *(gpointer*)ret = (gpointer)res;
2326 case MONO_TYPE_BOOLEAN:
2327 *(guint8*)ret = res;
2330 *(gint16*)ret = res;
2333 case MONO_TYPE_CHAR:
2334 *(guint16*)ret = res;
2337 *(gint32*)ret = res;
2340 *(guint32*)ret = res;
2344 /* This handles endianness as well */
2345 ((gint32*)ret) [0] = res;
2346 ((gint32*)ret) [1] = res2;
2348 case MONO_TYPE_GENERICINST:
2349 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2350 *(gpointer*)ret = (gpointer)res;
2355 case MONO_TYPE_VALUETYPE:
2356 g_assert (ainfo->cinfo->vtype_retaddr);
2361 *(float*)ret = *(float*)&res;
2363 case MONO_TYPE_R8: {
2370 *(double*)ret = *(double*)®s;
2374 g_assert_not_reached ();
2381 * Allow tracing to work with this interface (with an optional argument)
2385 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2389 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2390 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2391 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2392 code = emit_call_reg (code, ARMREG_R2);
2405 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2408 int save_mode = SAVE_NONE;
2410 MonoMethod *method = cfg->method;
2411 int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2412 int save_offset = cfg->param_area;
2416 offset = code - cfg->native_code;
2417 /* we need about 16 instructions */
2418 if (offset > (cfg->code_size - 16 * 4)) {
2419 cfg->code_size *= 2;
2420 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2421 code = cfg->native_code + offset;
2424 case MONO_TYPE_VOID:
2425 /* special case string .ctor icall */
2426 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2427 save_mode = SAVE_ONE;
2429 save_mode = SAVE_NONE;
2433 save_mode = SAVE_TWO;
2437 save_mode = SAVE_FP;
2439 case MONO_TYPE_VALUETYPE:
2440 save_mode = SAVE_STRUCT;
2443 save_mode = SAVE_ONE;
2447 switch (save_mode) {
2449 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2450 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2451 if (enable_arguments) {
2452 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2453 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2457 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2458 if (enable_arguments) {
2459 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2463 /* FIXME: what reg? */
2464 if (enable_arguments) {
2465 /* FIXME: what reg? */
2469 if (enable_arguments) {
2470 /* FIXME: get the actual address */
2471 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2479 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2480 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2481 code = emit_call_reg (code, ARMREG_IP);
2483 switch (save_mode) {
2485 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2486 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2489 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2503 * The immediate field for cond branches is big enough for all reasonable methods
2505 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2506 if (0 && ins->inst_true_bb->native_offset) { \
2507 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2509 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2510 ARM_B_COND (code, (condcode), 0); \
2513 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2515 /* emit an exception if condition is fail
2517 * We assign the extra code used to throw the implicit exceptions
2518 * to cfg->bb_exit as far as the big branch handling is concerned
2520 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
2522 mono_add_patch_info (cfg, code - cfg->native_code, \
2523 MONO_PATCH_INFO_EXC, exc_name); \
2524 ARM_BL_COND (code, (condcode), 0); \
2527 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2530 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2535 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2537 MonoInst *ins, *n, *last_ins = NULL;
2539 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2540 switch (ins->opcode) {
2543 /* Already done by an arch-independent pass */
2545 case OP_LOAD_MEMBASE:
2546 case OP_LOADI4_MEMBASE:
2548 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2549 * OP_LOAD_MEMBASE offset(basereg), reg
2551 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2552 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2553 ins->inst_basereg == last_ins->inst_destbasereg &&
2554 ins->inst_offset == last_ins->inst_offset) {
2555 if (ins->dreg == last_ins->sreg1) {
2556 MONO_DELETE_INS (bb, ins);
2559 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2560 ins->opcode = OP_MOVE;
2561 ins->sreg1 = last_ins->sreg1;
2565 * Note: reg1 must be different from the basereg in the second load
2566 * OP_LOAD_MEMBASE offset(basereg), reg1
2567 * OP_LOAD_MEMBASE offset(basereg), reg2
2569 * OP_LOAD_MEMBASE offset(basereg), reg1
2570 * OP_MOVE reg1, reg2
2572 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2573 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2574 ins->inst_basereg != last_ins->dreg &&
2575 ins->inst_basereg == last_ins->inst_basereg &&
2576 ins->inst_offset == last_ins->inst_offset) {
2578 if (ins->dreg == last_ins->dreg) {
2579 MONO_DELETE_INS (bb, ins);
2582 ins->opcode = OP_MOVE;
2583 ins->sreg1 = last_ins->dreg;
2586 //g_assert_not_reached ();
2590 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2591 * OP_LOAD_MEMBASE offset(basereg), reg
2593 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2594 * OP_ICONST reg, imm
2596 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2597 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2598 ins->inst_basereg == last_ins->inst_destbasereg &&
2599 ins->inst_offset == last_ins->inst_offset) {
2600 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2601 ins->opcode = OP_ICONST;
2602 ins->inst_c0 = last_ins->inst_imm;
2603 g_assert_not_reached (); // check this rule
2607 case OP_LOADU1_MEMBASE:
2608 case OP_LOADI1_MEMBASE:
2609 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2610 ins->inst_basereg == last_ins->inst_destbasereg &&
2611 ins->inst_offset == last_ins->inst_offset) {
2612 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2613 ins->sreg1 = last_ins->sreg1;
2616 case OP_LOADU2_MEMBASE:
2617 case OP_LOADI2_MEMBASE:
2618 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2619 ins->inst_basereg == last_ins->inst_destbasereg &&
2620 ins->inst_offset == last_ins->inst_offset) {
2621 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2622 ins->sreg1 = last_ins->sreg1;
2626 ins->opcode = OP_MOVE;
2630 if (ins->dreg == ins->sreg1) {
2631 MONO_DELETE_INS (bb, ins);
2635 * OP_MOVE sreg, dreg
2636 * OP_MOVE dreg, sreg
2638 if (last_ins && last_ins->opcode == OP_MOVE &&
2639 ins->sreg1 == last_ins->dreg &&
2640 ins->dreg == last_ins->sreg1) {
2641 MONO_DELETE_INS (bb, ins);
2649 bb->last_ins = last_ins;
2653 * the branch_cc_table should maintain the order of these
2667 branch_cc_table [] = {
2681 #define ADD_NEW_INS(cfg,dest,op) do { \
2682 MONO_INST_NEW ((cfg), (dest), (op)); \
2683 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2687 map_to_reg_reg_op (int op)
2696 case OP_COMPARE_IMM:
2698 case OP_ICOMPARE_IMM:
2712 case OP_LOAD_MEMBASE:
2713 return OP_LOAD_MEMINDEX;
2714 case OP_LOADI4_MEMBASE:
2715 return OP_LOADI4_MEMINDEX;
2716 case OP_LOADU4_MEMBASE:
2717 return OP_LOADU4_MEMINDEX;
2718 case OP_LOADU1_MEMBASE:
2719 return OP_LOADU1_MEMINDEX;
2720 case OP_LOADI2_MEMBASE:
2721 return OP_LOADI2_MEMINDEX;
2722 case OP_LOADU2_MEMBASE:
2723 return OP_LOADU2_MEMINDEX;
2724 case OP_LOADI1_MEMBASE:
2725 return OP_LOADI1_MEMINDEX;
2726 case OP_STOREI1_MEMBASE_REG:
2727 return OP_STOREI1_MEMINDEX;
2728 case OP_STOREI2_MEMBASE_REG:
2729 return OP_STOREI2_MEMINDEX;
2730 case OP_STOREI4_MEMBASE_REG:
2731 return OP_STOREI4_MEMINDEX;
2732 case OP_STORE_MEMBASE_REG:
2733 return OP_STORE_MEMINDEX;
2734 case OP_STORER4_MEMBASE_REG:
2735 return OP_STORER4_MEMINDEX;
2736 case OP_STORER8_MEMBASE_REG:
2737 return OP_STORER8_MEMINDEX;
2738 case OP_STORE_MEMBASE_IMM:
2739 return OP_STORE_MEMBASE_REG;
2740 case OP_STOREI1_MEMBASE_IMM:
2741 return OP_STOREI1_MEMBASE_REG;
2742 case OP_STOREI2_MEMBASE_IMM:
2743 return OP_STOREI2_MEMBASE_REG;
2744 case OP_STOREI4_MEMBASE_IMM:
2745 return OP_STOREI4_MEMBASE_REG;
2747 g_assert_not_reached ();
2751 * Remove from the instruction list the instructions that can't be
2752 * represented with very simple instructions with no register
2756 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2758 MonoInst *ins, *temp, *last_ins = NULL;
2759 int rot_amount, imm8, low_imm;
2761 MONO_BB_FOR_EACH_INS (bb, ins) {
2763 switch (ins->opcode) {
2767 case OP_COMPARE_IMM:
2768 case OP_ICOMPARE_IMM:
2782 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2783 ADD_NEW_INS (cfg, temp, OP_ICONST);
2784 temp->inst_c0 = ins->inst_imm;
2785 temp->dreg = mono_alloc_ireg (cfg);
2786 ins->sreg2 = temp->dreg;
2787 ins->opcode = mono_op_imm_to_op (ins->opcode);
2789 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2795 if (ins->inst_imm == 1) {
2796 ins->opcode = OP_MOVE;
2799 if (ins->inst_imm == 0) {
2800 ins->opcode = OP_ICONST;
2804 imm8 = mono_is_power_of_two (ins->inst_imm);
2806 ins->opcode = OP_SHL_IMM;
2807 ins->inst_imm = imm8;
2810 ADD_NEW_INS (cfg, temp, OP_ICONST);
2811 temp->inst_c0 = ins->inst_imm;
2812 temp->dreg = mono_alloc_ireg (cfg);
2813 ins->sreg2 = temp->dreg;
2814 ins->opcode = OP_IMUL;
2820 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2821 /* ARM sets the C flag to 1 if there was _no_ overflow */
2822 ins->next->opcode = OP_COND_EXC_NC;
2824 case OP_LOCALLOC_IMM:
2825 ADD_NEW_INS (cfg, temp, OP_ICONST);
2826 temp->inst_c0 = ins->inst_imm;
2827 temp->dreg = mono_alloc_ireg (cfg);
2828 ins->sreg1 = temp->dreg;
2829 ins->opcode = OP_LOCALLOC;
2831 case OP_LOAD_MEMBASE:
2832 case OP_LOADI4_MEMBASE:
2833 case OP_LOADU4_MEMBASE:
2834 case OP_LOADU1_MEMBASE:
2835 /* we can do two things: load the immed in a register
2836 * and use an indexed load, or see if the immed can be
2837 * represented as an ad_imm + a load with a smaller offset
2838 * that fits. We just do the first for now, optimize later.
2840 if (arm_is_imm12 (ins->inst_offset))
2842 ADD_NEW_INS (cfg, temp, OP_ICONST);
2843 temp->inst_c0 = ins->inst_offset;
2844 temp->dreg = mono_alloc_ireg (cfg);
2845 ins->sreg2 = temp->dreg;
2846 ins->opcode = map_to_reg_reg_op (ins->opcode);
2848 case OP_LOADI2_MEMBASE:
2849 case OP_LOADU2_MEMBASE:
2850 case OP_LOADI1_MEMBASE:
2851 if (arm_is_imm8 (ins->inst_offset))
2853 ADD_NEW_INS (cfg, temp, OP_ICONST);
2854 temp->inst_c0 = ins->inst_offset;
2855 temp->dreg = mono_alloc_ireg (cfg);
2856 ins->sreg2 = temp->dreg;
2857 ins->opcode = map_to_reg_reg_op (ins->opcode);
2859 case OP_LOADR4_MEMBASE:
2860 case OP_LOADR8_MEMBASE:
2861 if (arm_is_fpimm8 (ins->inst_offset))
2863 low_imm = ins->inst_offset & 0x1ff;
2864 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2865 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2866 temp->inst_imm = ins->inst_offset & ~0x1ff;
2867 temp->sreg1 = ins->inst_basereg;
2868 temp->dreg = mono_alloc_ireg (cfg);
2869 ins->inst_basereg = temp->dreg;
2870 ins->inst_offset = low_imm;
2874 ADD_NEW_INS (cfg, temp, OP_ICONST);
2875 temp->inst_c0 = ins->inst_offset;
2876 temp->dreg = mono_alloc_ireg (cfg);
2878 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2879 add_ins->sreg1 = ins->inst_basereg;
2880 add_ins->sreg2 = temp->dreg;
2881 add_ins->dreg = mono_alloc_ireg (cfg);
2883 ins->inst_basereg = add_ins->dreg;
2884 ins->inst_offset = 0;
2887 case OP_STORE_MEMBASE_REG:
2888 case OP_STOREI4_MEMBASE_REG:
2889 case OP_STOREI1_MEMBASE_REG:
2890 if (arm_is_imm12 (ins->inst_offset))
2892 ADD_NEW_INS (cfg, temp, OP_ICONST);
2893 temp->inst_c0 = ins->inst_offset;
2894 temp->dreg = mono_alloc_ireg (cfg);
2895 ins->sreg2 = temp->dreg;
2896 ins->opcode = map_to_reg_reg_op (ins->opcode);
2898 case OP_STOREI2_MEMBASE_REG:
2899 if (arm_is_imm8 (ins->inst_offset))
2901 ADD_NEW_INS (cfg, temp, OP_ICONST);
2902 temp->inst_c0 = ins->inst_offset;
2903 temp->dreg = mono_alloc_ireg (cfg);
2904 ins->sreg2 = temp->dreg;
2905 ins->opcode = map_to_reg_reg_op (ins->opcode);
2907 case OP_STORER4_MEMBASE_REG:
2908 case OP_STORER8_MEMBASE_REG:
2909 if (arm_is_fpimm8 (ins->inst_offset))
2911 low_imm = ins->inst_offset & 0x1ff;
2912 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2913 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2914 temp->inst_imm = ins->inst_offset & ~0x1ff;
2915 temp->sreg1 = ins->inst_destbasereg;
2916 temp->dreg = mono_alloc_ireg (cfg);
2917 ins->inst_destbasereg = temp->dreg;
2918 ins->inst_offset = low_imm;
2922 ADD_NEW_INS (cfg, temp, OP_ICONST);
2923 temp->inst_c0 = ins->inst_offset;
2924 temp->dreg = mono_alloc_ireg (cfg);
2926 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2927 add_ins->sreg1 = ins->inst_destbasereg;
2928 add_ins->sreg2 = temp->dreg;
2929 add_ins->dreg = mono_alloc_ireg (cfg);
2931 ins->inst_destbasereg = add_ins->dreg;
2932 ins->inst_offset = 0;
2935 case OP_STORE_MEMBASE_IMM:
2936 case OP_STOREI1_MEMBASE_IMM:
2937 case OP_STOREI2_MEMBASE_IMM:
2938 case OP_STOREI4_MEMBASE_IMM:
2939 ADD_NEW_INS (cfg, temp, OP_ICONST);
2940 temp->inst_c0 = ins->inst_imm;
2941 temp->dreg = mono_alloc_ireg (cfg);
2942 ins->sreg1 = temp->dreg;
2943 ins->opcode = map_to_reg_reg_op (ins->opcode);
2945 goto loop_start; /* make it handle the possibly big ins->inst_offset */
2947 gboolean swap = FALSE;
2951 /* Optimized away */
2956 /* Some fp compares require swapped operands */
2957 switch (ins->next->opcode) {
2959 ins->next->opcode = OP_FBLT;
2963 ins->next->opcode = OP_FBLT_UN;
2967 ins->next->opcode = OP_FBGE;
2971 ins->next->opcode = OP_FBGE_UN;
2979 ins->sreg1 = ins->sreg2;
2988 bb->last_ins = last_ins;
2989 bb->max_vreg = cfg->next_vreg;
2993 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2997 if (long_ins->opcode == OP_LNEG) {
2999 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3000 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3006 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3008 /* sreg is a float, dreg is an integer reg */
3010 ARM_FPA_FIXZ (code, dreg, sreg);
3013 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
3015 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
3016 ARM_FMRS (code, dreg, ARM_VFP_F0);
3020 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3021 else if (size == 2) {
3022 ARM_SHL_IMM (code, dreg, dreg, 16);
3023 ARM_SHR_IMM (code, dreg, dreg, 16);
3027 ARM_SHL_IMM (code, dreg, dreg, 24);
3028 ARM_SAR_IMM (code, dreg, dreg, 24);
3029 } else if (size == 2) {
3030 ARM_SHL_IMM (code, dreg, dreg, 16);
3031 ARM_SAR_IMM (code, dreg, dreg, 16);
3037 #endif /* #ifndef DISABLE_JIT */
3041 const guchar *target;
3046 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3049 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
3050 PatchData *pdata = (PatchData*)user_data;
3051 guchar *code = data;
3052 guint32 *thunks = data;
3053 guint32 *endthunks = (guint32*)(code + bsize);
3055 int difflow, diffhigh;
3057 /* always ensure a call from pdata->code can reach to the thunks without further thunks */
3058 difflow = (char*)pdata->code - (char*)thunks;
3059 diffhigh = (char*)pdata->code - (char*)endthunks;
3060 if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
3064 * The thunk is composed of 3 words:
3065 * load constant from thunks [2] into ARM_IP
3068 * Note that the LR register is already setup
3070 //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
3071 if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
3072 while (thunks < endthunks) {
3073 //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
3074 if (thunks [2] == (guint32)pdata->target) {
3075 arm_patch (pdata->code, (guchar*)thunks);
3076 mono_arch_flush_icache (pdata->code, 4);
3079 } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
3080 /* found a free slot instead: emit thunk */
3081 /* ARMREG_IP is fine to use since this can't be an IMT call
3084 code = (guchar*)thunks;
3085 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3086 if (thumb_supported)
3087 ARM_BX (code, ARMREG_IP);
3089 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3090 thunks [2] = (guint32)pdata->target;
3091 mono_arch_flush_icache ((guchar*)thunks, 12);
3093 arm_patch (pdata->code, (guchar*)thunks);
3094 mono_arch_flush_icache (pdata->code, 4);
3098 /* skip 12 bytes, the size of the thunk */
3102 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
3108 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3113 domain = mono_domain_get ();
3116 pdata.target = target;
3117 pdata.absolute = absolute;
3121 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
3124 if (pdata.found != 1) {
3125 mono_domain_lock (domain);
3126 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3129 /* this uses the first available slot */
3131 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3133 mono_domain_unlock (domain);
3136 if (pdata.found != 1) {
3138 GHashTableIter iter;
3139 MonoJitDynamicMethodInfo *ji;
3142 * This might be a dynamic method, search its code manager. We can only
3143 * use the dynamic method containing CODE, since the others might be freed later.
3147 mono_domain_lock (domain);
3148 hash = domain_jit_info (domain)->dynamic_code_hash;
3150 /* FIXME: Speed this up */
3151 g_hash_table_iter_init (&iter, hash);
3152 while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
3153 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
3154 if (pdata.found == 1)
3158 mono_domain_unlock (domain);
3160 if (pdata.found != 1)
3161 g_print ("thunk failed for %p from %p\n", target, code);
3162 g_assert (pdata.found == 1);
3166 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3168 guint32 *code32 = (void*)code;
3169 guint32 ins = *code32;
3170 guint32 prim = (ins >> 25) & 7;
3171 guint32 tval = GPOINTER_TO_UINT (target);
3173 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3174 if (prim == 5) { /* 101b */
3175 /* the diff starts 8 bytes from the branch opcode */
3176 gint diff = target - code - 8;
3178 gint tmask = 0xffffffff;
3179 if (tval & 1) { /* entering thumb mode */
3180 diff = target - 1 - code - 8;
3181 g_assert (thumb_supported);
3182 tbits = 0xf << 28; /* bl->blx bit pattern */
3183 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3184 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3188 tmask = ~(1 << 24); /* clear the link bit */
3189 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3194 if (diff <= 33554431) {
3196 ins = (ins & 0xff000000) | diff;
3198 *code32 = ins | tbits;
3202 /* diff between 0 and -33554432 */
3203 if (diff >= -33554432) {
3205 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3207 *code32 = ins | tbits;
3212 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3217 * The alternative call sequences looks like this:
3219 * ldr ip, [pc] // loads the address constant
3220 * b 1f // jumps around the constant
3221 * address constant embedded in the code
3226 * There are two cases for patching:
3227 * a) at the end of method emission: in this case code points to the start
3228 * of the call sequence
3229 * b) during runtime patching of the call site: in this case code points
3230 * to the mov pc, ip instruction
3232 * We have to handle also the thunk jump code sequence:
3236 * address constant // execution never reaches here
3238 if ((ins & 0x0ffffff0) == 0x12fff10) {
3239 /* Branch and exchange: the address is constructed in a reg
3240 * We can patch BX when the code sequence is the following:
3241 * ldr ip, [pc, #0] ; 0x8
3248 guint8 *emit = (guint8*)ccode;
3249 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3251 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3252 ARM_BX (emit, ARMREG_IP);
3254 /*patching from magic trampoline*/
3255 if (ins == ccode [3]) {
3256 g_assert (code32 [-4] == ccode [0]);
3257 g_assert (code32 [-3] == ccode [1]);
3258 g_assert (code32 [-1] == ccode [2]);
3259 code32 [-2] = (guint32)target;
3262 /*patching from JIT*/
3263 if (ins == ccode [0]) {
3264 g_assert (code32 [1] == ccode [1]);
3265 g_assert (code32 [3] == ccode [2]);
3266 g_assert (code32 [4] == ccode [3]);
3267 code32 [2] = (guint32)target;
3270 g_assert_not_reached ();
3271 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3279 guint8 *emit = (guint8*)ccode;
3280 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3282 ARM_BLX_REG (emit, ARMREG_IP);
3284 g_assert (code32 [-3] == ccode [0]);
3285 g_assert (code32 [-2] == ccode [1]);
3286 g_assert (code32 [0] == ccode [2]);
3288 code32 [-1] = (guint32)target;
3291 guint32 *tmp = ccode;
3292 guint8 *emit = (guint8*)tmp;
3293 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3294 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3295 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3296 ARM_BX (emit, ARMREG_IP);
3297 if (ins == ccode [2]) {
3298 g_assert_not_reached (); // should be -2 ...
3299 code32 [-1] = (guint32)target;
3302 if (ins == ccode [0]) {
3303 /* handles both thunk jump code and the far call sequence */
3304 code32 [2] = (guint32)target;
3307 g_assert_not_reached ();
3309 // g_print ("patched with 0x%08x\n", ins);
3313 arm_patch (guchar *code, const guchar *target)
3315 arm_patch_general (NULL, code, target, NULL);
3319 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3320 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3321 * to be used with the emit macros.
3322 * Return -1 otherwise.
3325 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3328 for (i = 0; i < 31; i+= 2) {
3329 res = (val << (32 - i)) | (val >> i);
3332 *rot_amount = i? 32 - i: 0;
3339 * Emits in code a sequence of instructions that load the value 'val'
3340 * into the dreg register. Uses at most 4 instructions.
3343 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3345 int imm8, rot_amount;
3347 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3348 /* skip the constant pool */
3354 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3355 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3356 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3357 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3360 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3362 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3366 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3368 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3370 if (val & 0xFF0000) {
3371 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3373 if (val & 0xFF000000) {
3374 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3376 } else if (val & 0xFF00) {
3377 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3378 if (val & 0xFF0000) {
3379 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3381 if (val & 0xFF000000) {
3382 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3384 } else if (val & 0xFF0000) {
3385 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3386 if (val & 0xFF000000) {
3387 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3390 //g_assert_not_reached ();
3396 mono_arm_thumb_supported (void)
3398 return thumb_supported;
3404 * emit_load_volatile_arguments:
3406 * Load volatile arguments from the stack to the original input registers.
3407 * Required before a tail call.
3410 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3412 MonoMethod *method = cfg->method;
3413 MonoMethodSignature *sig;
3418 /* FIXME: Generate intermediate code instead */
3420 sig = mono_method_signature (method);
3422 /* This is the opposite of the code in emit_prolog */
3426 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3428 if (cinfo->vtype_retaddr) {
3429 ArgInfo *ainfo = &cinfo->ret;
3430 inst = cfg->vret_addr;
3431 g_assert (arm_is_imm12 (inst->inst_offset));
3432 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3434 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3435 ArgInfo *ainfo = cinfo->args + i;
3436 inst = cfg->args [pos];
3438 if (cfg->verbose_level > 2)
3439 g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3440 if (inst->opcode == OP_REGVAR) {
3441 if (ainfo->storage == RegTypeGeneral)
3442 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3443 else if (ainfo->storage == RegTypeFP) {
3444 g_assert_not_reached ();
3445 } else if (ainfo->storage == RegTypeBase) {
3449 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3450 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3452 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3453 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3457 g_assert_not_reached ();
3459 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3460 switch (ainfo->size) {
3467 g_assert (arm_is_imm12 (inst->inst_offset));
3468 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3469 g_assert (arm_is_imm12 (inst->inst_offset + 4));
3470 ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3473 if (arm_is_imm12 (inst->inst_offset)) {
3474 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3476 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3477 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3481 } else if (ainfo->storage == RegTypeBaseGen) {
3484 } else if (ainfo->storage == RegTypeBase) {
3486 } else if (ainfo->storage == RegTypeFP) {
3487 g_assert_not_reached ();
3488 } else if (ainfo->storage == RegTypeStructByVal) {
3489 int doffset = inst->inst_offset;
3493 if (mono_class_from_mono_type (inst->inst_vtype))
3494 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3495 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3496 if (arm_is_imm12 (doffset)) {
3497 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3499 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3500 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3502 soffset += sizeof (gpointer);
3503 doffset += sizeof (gpointer);
3508 } else if (ainfo->storage == RegTypeStructByAddr) {
3523 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3528 guint8 *code = cfg->native_code + cfg->code_len;
3529 MonoInst *last_ins = NULL;
3530 guint last_offset = 0;
3532 int imm8, rot_amount;
3534 /* we don't align basic blocks of loops on arm */
3536 if (cfg->verbose_level > 2)
3537 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3539 cpos = bb->max_offset;
3541 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3542 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3543 //g_assert (!mono_compile_aot);
3546 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3547 /* this is not thread save, but good enough */
3548 /* fixme: howto handle overflows? */
3549 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3552 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3553 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3554 (gpointer)"mono_break");
3555 code = emit_call_seq (cfg, code);
3558 MONO_BB_FOR_EACH_INS (bb, ins) {
3559 offset = code - cfg->native_code;
3561 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3563 if (offset > (cfg->code_size - max_len - 16)) {
3564 cfg->code_size *= 2;
3565 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3566 code = cfg->native_code + offset;
3568 // if (ins->cil_code)
3569 // g_print ("cil code\n");
3570 mono_debug_record_line_number (cfg, ins, offset);
3572 switch (ins->opcode) {
3573 case OP_MEMORY_BARRIER:
3575 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
3576 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
3580 #ifdef HAVE_AEABI_READ_TP
3581 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3582 (gpointer)"__aeabi_read_tp");
3583 code = emit_call_seq (cfg, code);
3585 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3587 g_assert_not_reached ();
3591 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3592 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3595 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3596 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3598 case OP_STOREI1_MEMBASE_IMM:
3599 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3600 g_assert (arm_is_imm12 (ins->inst_offset));
3601 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3603 case OP_STOREI2_MEMBASE_IMM:
3604 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3605 g_assert (arm_is_imm8 (ins->inst_offset));
3606 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3608 case OP_STORE_MEMBASE_IMM:
3609 case OP_STOREI4_MEMBASE_IMM:
3610 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3611 g_assert (arm_is_imm12 (ins->inst_offset));
3612 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3614 case OP_STOREI1_MEMBASE_REG:
3615 g_assert (arm_is_imm12 (ins->inst_offset));
3616 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3618 case OP_STOREI2_MEMBASE_REG:
3619 g_assert (arm_is_imm8 (ins->inst_offset));
3620 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3622 case OP_STORE_MEMBASE_REG:
3623 case OP_STOREI4_MEMBASE_REG:
3624 /* this case is special, since it happens for spill code after lowering has been called */
3625 if (arm_is_imm12 (ins->inst_offset)) {
3626 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3628 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3629 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3632 case OP_STOREI1_MEMINDEX:
3633 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3635 case OP_STOREI2_MEMINDEX:
3636 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3638 case OP_STORE_MEMINDEX:
3639 case OP_STOREI4_MEMINDEX:
3640 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3643 g_assert_not_reached ();
3645 case OP_LOAD_MEMINDEX:
3646 case OP_LOADI4_MEMINDEX:
3647 case OP_LOADU4_MEMINDEX:
3648 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3650 case OP_LOADI1_MEMINDEX:
3651 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3653 case OP_LOADU1_MEMINDEX:
3654 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3656 case OP_LOADI2_MEMINDEX:
3657 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3659 case OP_LOADU2_MEMINDEX:
3660 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3662 case OP_LOAD_MEMBASE:
3663 case OP_LOADI4_MEMBASE:
3664 case OP_LOADU4_MEMBASE:
3665 /* this case is special, since it happens for spill code after lowering has been called */
3666 if (arm_is_imm12 (ins->inst_offset)) {
3667 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3669 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3670 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3673 case OP_LOADI1_MEMBASE:
3674 g_assert (arm_is_imm8 (ins->inst_offset));
3675 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3677 case OP_LOADU1_MEMBASE:
3678 g_assert (arm_is_imm12 (ins->inst_offset));
3679 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3681 case OP_LOADU2_MEMBASE:
3682 g_assert (arm_is_imm8 (ins->inst_offset));
3683 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3685 case OP_LOADI2_MEMBASE:
3686 g_assert (arm_is_imm8 (ins->inst_offset));
3687 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3689 case OP_ICONV_TO_I1:
3690 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3691 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3693 case OP_ICONV_TO_I2:
3694 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3695 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3697 case OP_ICONV_TO_U1:
3698 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3700 case OP_ICONV_TO_U2:
3701 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3702 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3706 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3708 case OP_COMPARE_IMM:
3709 case OP_ICOMPARE_IMM:
3710 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3711 g_assert (imm8 >= 0);
3712 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3716 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3717 * So instead of emitting a trap, we emit a call a C function and place a
3720 //*(int*)code = 0xef9f0001;
3723 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3724 (gpointer)"mono_break");
3725 code = emit_call_seq (cfg, code);
3727 case OP_RELAXED_NOP:
3732 case OP_DUMMY_STORE:
3733 case OP_NOT_REACHED:
3736 case OP_SEQ_POINT: {
3738 MonoInst *info_var = cfg->arch.seq_point_info_var;
3739 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3740 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
3741 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
3742 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
3744 int dreg = ARMREG_LR;
3746 if (cfg->soft_breakpoints) {
3747 g_assert (!cfg->compile_aot);
3751 * For AOT, we use one got slot per method, which will point to a
3752 * SeqPointInfo structure, containing all the information required
3753 * by the code below.
3755 if (cfg->compile_aot) {
3756 g_assert (info_var);
3757 g_assert (info_var->opcode == OP_REGOFFSET);
3758 g_assert (arm_is_imm12 (info_var->inst_offset));
3761 if (!cfg->soft_breakpoints) {
3763 * Read from the single stepping trigger page. This will cause a
3764 * SIGSEGV when single stepping is enabled.
3765 * We do this _before_ the breakpoint, so single stepping after
3766 * a breakpoint is hit will step to the next IL offset.
3768 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3771 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3772 if (cfg->soft_breakpoints) {
3773 /* Load the address of the sequence point trigger variable. */
3776 g_assert (var->opcode == OP_REGOFFSET);
3777 g_assert (arm_is_imm12 (var->inst_offset));
3778 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3780 /* Read the value and check whether it is non-zero. */
3781 ARM_LDR_IMM (code, dreg, dreg, 0);
3782 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3784 /* Load the address of the sequence point method. */
3785 var = ss_method_var;
3787 g_assert (var->opcode == OP_REGOFFSET);
3788 g_assert (arm_is_imm12 (var->inst_offset));
3789 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3791 /* Call it conditionally. */
3792 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
3794 if (cfg->compile_aot) {
3795 /* Load the trigger page addr from the variable initialized in the prolog */
3796 var = ss_trigger_page_var;
3798 g_assert (var->opcode == OP_REGOFFSET);
3799 g_assert (arm_is_imm12 (var->inst_offset));
3800 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3802 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3804 *(int*)code = (int)ss_trigger_page;
3807 ARM_LDR_IMM (code, dreg, dreg, 0);
3811 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3813 if (cfg->soft_breakpoints) {
3814 /* Load the address of the breakpoint method into ip. */
3815 var = bp_method_var;
3817 g_assert (var->opcode == OP_REGOFFSET);
3818 g_assert (arm_is_imm12 (var->inst_offset));
3819 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3822 * A placeholder for a possible breakpoint inserted by
3823 * mono_arch_set_breakpoint ().
3826 } else if (cfg->compile_aot) {
3827 guint32 offset = code - cfg->native_code;
3830 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3831 /* Add the offset */
3832 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3833 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3835 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3837 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3838 g_assert (!(val & 0xFF000000));
3839 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3840 ARM_LDR_IMM (code, dreg, dreg, 0);
3842 /* What is faster, a branch or a load ? */
3843 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3844 /* The breakpoint instruction */
3845 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3848 * A placeholder for a possible breakpoint inserted by
3849 * mono_arch_set_breakpoint ().
3851 for (i = 0; i < 4; ++i)
3858 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3861 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3865 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3868 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3869 g_assert (imm8 >= 0);
3870 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3874 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3875 g_assert (imm8 >= 0);
3876 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3880 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3881 g_assert (imm8 >= 0);
3882 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3885 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3886 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3888 case OP_IADD_OVF_UN:
3889 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3890 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3893 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3894 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3896 case OP_ISUB_OVF_UN:
3897 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3898 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3900 case OP_ADD_OVF_CARRY:
3901 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3902 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3904 case OP_ADD_OVF_UN_CARRY:
3905 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3906 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3908 case OP_SUB_OVF_CARRY:
3909 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3910 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3912 case OP_SUB_OVF_UN_CARRY:
3913 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3914 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3918 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3921 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3922 g_assert (imm8 >= 0);
3923 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3926 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3930 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3934 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3935 g_assert (imm8 >= 0);
3936 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3940 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3941 g_assert (imm8 >= 0);
3942 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3944 case OP_ARM_RSBS_IMM:
3945 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3946 g_assert (imm8 >= 0);
3947 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3949 case OP_ARM_RSC_IMM:
3950 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3951 g_assert (imm8 >= 0);
3952 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3955 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3959 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3960 g_assert (imm8 >= 0);
3961 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3969 /* crappy ARM arch doesn't have a DIV instruction */
3970 g_assert_not_reached ();
3972 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3976 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3977 g_assert (imm8 >= 0);
3978 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3981 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3985 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3986 g_assert (imm8 >= 0);
3987 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3990 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3995 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3996 else if (ins->dreg != ins->sreg1)
3997 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4000 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4005 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4006 else if (ins->dreg != ins->sreg1)
4007 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4010 case OP_ISHR_UN_IMM:
4012 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4013 else if (ins->dreg != ins->sreg1)
4014 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4017 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4020 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4023 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4026 if (ins->dreg == ins->sreg2)
4027 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4029 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4032 g_assert_not_reached ();
4035 /* FIXME: handle ovf/ sreg2 != dreg */
4036 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4037 /* FIXME: MUL doesn't set the C/O flags on ARM */
4039 case OP_IMUL_OVF_UN:
4040 /* FIXME: handle ovf/ sreg2 != dreg */
4041 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4042 /* FIXME: MUL doesn't set the C/O flags on ARM */
4045 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4048 /* Load the GOT offset */
4049 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4050 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4052 *(gpointer*)code = NULL;
4054 /* Load the value from the GOT */
4055 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4057 case OP_ICONV_TO_I4:
4058 case OP_ICONV_TO_U4:
4060 if (ins->dreg != ins->sreg1)
4061 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4064 int saved = ins->sreg2;
4065 if (ins->sreg2 == ARM_LSW_REG) {
4066 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4069 if (ins->sreg1 != ARM_LSW_REG)
4070 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4071 if (saved != ARM_MSW_REG)
4072 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4077 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4079 ARM_CPYD (code, ins->dreg, ins->sreg1);
4081 case OP_FCONV_TO_R4:
4083 ARM_FPA_MVFS (code, ins->dreg, ins->sreg1);
4085 ARM_CVTD (code, ins->dreg, ins->sreg1);
4086 ARM_CVTS (code, ins->dreg, ins->dreg);
4091 * Keep in sync with mono_arch_emit_epilog
4093 g_assert (!cfg->method->save_lmf);
4095 code = emit_load_volatile_arguments (cfg, code);
4097 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4099 if (cfg->used_int_regs)
4100 ARM_POP (code, cfg->used_int_regs);
4101 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4103 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4105 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4106 if (cfg->compile_aot) {
4107 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4109 *(gpointer*)code = NULL;
4111 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4117 /* ensure ins->sreg1 is not NULL */
4118 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4121 g_assert (cfg->sig_cookie < 128);
4122 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4123 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4132 call = (MonoCallInst*)ins;
4133 if (ins->flags & MONO_INST_HAS_METHOD)
4134 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4136 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4137 code = emit_call_seq (cfg, code);
4138 ins->flags |= MONO_INST_GC_CALLSITE;
4139 ins->backend.pc_offset = code - cfg->native_code;
4140 code = emit_move_return_value (cfg, ins, code);
4146 case OP_VOIDCALL_REG:
4148 code = emit_call_reg (code, ins->sreg1);
4149 ins->flags |= MONO_INST_GC_CALLSITE;
4150 ins->backend.pc_offset = code - cfg->native_code;
4151 code = emit_move_return_value (cfg, ins, code);
4153 case OP_FCALL_MEMBASE:
4154 case OP_LCALL_MEMBASE:
4155 case OP_VCALL_MEMBASE:
4156 case OP_VCALL2_MEMBASE:
4157 case OP_VOIDCALL_MEMBASE:
4158 case OP_CALL_MEMBASE: {
4159 gboolean imt_arg = FALSE;
4161 g_assert (ins->sreg1 != ARMREG_LR);
4162 call = (MonoCallInst*)ins;
4163 if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE)
4165 if (!arm_is_imm12 (ins->inst_offset))
4166 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
4168 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
4170 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4171 if (!arm_is_imm12 (ins->inst_offset))
4172 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
4174 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4177 * We can't embed the method in the code stream in PIC code, or
4179 * Instead, we put it in V5 in code emitted by
4180 * mono_arch_emit_imt_argument (), and embed NULL here to
4181 * signal the IMT thunk that the value is in V5.
4183 if (call->dynamic_imt_arg)
4184 *((gpointer*)code) = NULL;
4186 *((gpointer*)code) = (gpointer)call->method;
4189 ins->flags |= MONO_INST_GC_CALLSITE;
4190 ins->backend.pc_offset = code - cfg->native_code;
4191 code = emit_move_return_value (cfg, ins, code);
4195 /* keep alignment */
4196 int alloca_waste = cfg->param_area;
4199 /* round the size to 8 bytes */
4200 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
4201 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
4203 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
4204 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
4205 /* memzero the area: dreg holds the size, sp is the pointer */
4206 if (ins->flags & MONO_INST_INIT) {
4207 guint8 *start_loop, *branch_to_cond;
4208 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
4209 branch_to_cond = code;
4212 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
4213 arm_patch (branch_to_cond, code);
4214 /* decrement by 4 and set flags */
4215 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
4216 ARM_B_COND (code, ARMCOND_GE, 0);
4217 arm_patch (code - 4, start_loop);
4219 ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
4224 MonoInst *var = cfg->dyn_call_var;
4226 g_assert (var->opcode == OP_REGOFFSET);
4227 g_assert (arm_is_imm12 (var->inst_offset));
4229 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
4230 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
4232 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
4234 /* Save args buffer */
4235 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4237 /* Set stack slots using R0 as scratch reg */
4238 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
4239 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4240 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
4241 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4244 /* Set argument registers */
4245 for (i = 0; i < PARAM_REGS; ++i)
4246 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
4249 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4250 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4253 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
4254 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
4255 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
4259 if (ins->sreg1 != ARMREG_R0)
4260 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4261 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4262 (gpointer)"mono_arch_throw_exception");
4263 code = emit_call_seq (cfg, code);
4267 if (ins->sreg1 != ARMREG_R0)
4268 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4269 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4270 (gpointer)"mono_arch_rethrow_exception");
4271 code = emit_call_seq (cfg, code);
4274 case OP_START_HANDLER: {
4275 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4278 /* Reserve a param area, see filter-stack.exe */
4279 if (cfg->param_area) {
4280 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4281 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4283 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4284 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4288 if (arm_is_imm12 (spvar->inst_offset)) {
4289 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4291 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4292 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
4296 case OP_ENDFILTER: {
4297 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4300 /* Free the param area */
4301 if (cfg->param_area) {
4302 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4303 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4305 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4306 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4310 if (ins->sreg1 != ARMREG_R0)
4311 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4312 if (arm_is_imm12 (spvar->inst_offset)) {
4313 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4315 g_assert (ARMREG_IP != spvar->inst_basereg);
4316 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4317 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4319 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4322 case OP_ENDFINALLY: {
4323 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4326 /* Free the param area */
4327 if (cfg->param_area) {
4328 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4329 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4331 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4332 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4336 if (arm_is_imm12 (spvar->inst_offset)) {
4337 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4339 g_assert (ARMREG_IP != spvar->inst_basereg);
4340 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4341 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4343 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4346 case OP_CALL_HANDLER:
4347 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4349 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4352 ins->inst_c0 = code - cfg->native_code;
4355 /*if (ins->inst_target_bb->native_offset) {
4357 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4359 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4364 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
4368 * In the normal case we have:
4369 * ldr pc, [pc, ins->sreg1 << 2]
4372 * ldr lr, [pc, ins->sreg1 << 2]
4374 * After follows the data.
4375 * FIXME: add aot support.
4377 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
4378 max_len += 4 * GPOINTER_TO_INT (ins->klass);
4379 if (offset + max_len > (cfg->code_size - 16)) {
4380 cfg->code_size += max_len;
4381 cfg->code_size *= 2;
4382 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4383 code = cfg->native_code + offset;
4385 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
4387 code += 4 * GPOINTER_TO_INT (ins->klass);
4391 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4392 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4396 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4397 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
4401 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4402 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
4406 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4407 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
4411 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4412 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
4414 case OP_COND_EXC_EQ:
4415 case OP_COND_EXC_NE_UN:
4416 case OP_COND_EXC_LT:
4417 case OP_COND_EXC_LT_UN:
4418 case OP_COND_EXC_GT:
4419 case OP_COND_EXC_GT_UN:
4420 case OP_COND_EXC_GE:
4421 case OP_COND_EXC_GE_UN:
4422 case OP_COND_EXC_LE:
4423 case OP_COND_EXC_LE_UN:
4424 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
4426 case OP_COND_EXC_IEQ:
4427 case OP_COND_EXC_INE_UN:
4428 case OP_COND_EXC_ILT:
4429 case OP_COND_EXC_ILT_UN:
4430 case OP_COND_EXC_IGT:
4431 case OP_COND_EXC_IGT_UN:
4432 case OP_COND_EXC_IGE:
4433 case OP_COND_EXC_IGE_UN:
4434 case OP_COND_EXC_ILE:
4435 case OP_COND_EXC_ILE_UN:
4436 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4439 case OP_COND_EXC_IC:
4440 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4442 case OP_COND_EXC_OV:
4443 case OP_COND_EXC_IOV:
4444 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4446 case OP_COND_EXC_NC:
4447 case OP_COND_EXC_INC:
4448 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4450 case OP_COND_EXC_NO:
4451 case OP_COND_EXC_INO:
4452 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4464 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4467 /* floating point opcodes */
4470 if (cfg->compile_aot) {
4471 ARM_FPA_LDFD (code, ins->dreg, ARMREG_PC, 0);
4473 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4475 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4478 /* FIXME: we can optimize the imm load by dealing with part of
4479 * the displacement in LDFD (aligning to 512).
4481 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4482 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4486 if (cfg->compile_aot) {
4487 ARM_FPA_LDFS (code, ins->dreg, ARMREG_PC, 0);
4489 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4492 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4493 ARM_FPA_LDFS (code, ins->dreg, ARMREG_LR, 0);
4496 case OP_STORER8_MEMBASE_REG:
4497 /* This is generated by the local regalloc pass which runs after the lowering pass */
4498 if (!arm_is_fpimm8 (ins->inst_offset)) {
4499 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4500 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4501 ARM_FPA_STFD (code, ins->sreg1, ARMREG_LR, 0);
4503 ARM_FPA_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4506 case OP_LOADR8_MEMBASE:
4507 /* This is generated by the local regalloc pass which runs after the lowering pass */
4508 if (!arm_is_fpimm8 (ins->inst_offset)) {
4509 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4510 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4511 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4513 ARM_FPA_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4516 case OP_STORER4_MEMBASE_REG:
4517 g_assert (arm_is_fpimm8 (ins->inst_offset));
4518 ARM_FPA_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4520 case OP_LOADR4_MEMBASE:
4521 g_assert (arm_is_fpimm8 (ins->inst_offset));
4522 ARM_FPA_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4524 case OP_ICONV_TO_R_UN: {
4526 tmpreg = ins->dreg == 0? 1: 0;
4527 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4528 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4529 ARM_B_COND (code, ARMCOND_GE, 8);
4530 /* save the temp register */
4531 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4532 ARM_FPA_STFD (code, tmpreg, ARMREG_SP, 0);
4533 ARM_FPA_LDFD (code, tmpreg, ARMREG_PC, 12);
4534 ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4535 ARM_FPA_LDFD (code, tmpreg, ARMREG_SP, 0);
4536 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4537 /* skip the constant pool */
4540 *(int*)code = 0x41f00000;
4545 * ldfltd ftemp, [pc, #8] 0x41f00000 0x00000000
4546 * adfltd fdest, fdest, ftemp
4550 case OP_ICONV_TO_R4:
4551 ARM_FPA_FLTS (code, ins->dreg, ins->sreg1);
4553 case OP_ICONV_TO_R8:
4554 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4557 #elif defined(ARM_FPU_VFP)
4560 if (cfg->compile_aot) {
4561 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4563 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4565 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4568 /* FIXME: we can optimize the imm load by dealing with part of
4569 * the displacement in LDFD (aligning to 512).
4571 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4572 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4576 if (cfg->compile_aot) {
4577 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4579 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4581 ARM_CVTS (code, ins->dreg, ins->dreg);
4583 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4584 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4585 ARM_CVTS (code, ins->dreg, ins->dreg);
4588 case OP_STORER8_MEMBASE_REG:
4589 /* This is generated by the local regalloc pass which runs after the lowering pass */
4590 if (!arm_is_fpimm8 (ins->inst_offset)) {
4591 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4592 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4593 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4595 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4598 case OP_LOADR8_MEMBASE:
4599 /* This is generated by the local regalloc pass which runs after the lowering pass */
4600 if (!arm_is_fpimm8 (ins->inst_offset)) {
4601 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4602 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4603 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4605 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4608 case OP_STORER4_MEMBASE_REG:
4609 g_assert (arm_is_fpimm8 (ins->inst_offset));
4610 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4611 ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4613 case OP_LOADR4_MEMBASE:
4614 g_assert (arm_is_fpimm8 (ins->inst_offset));
4615 ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4616 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4618 case OP_ICONV_TO_R_UN: {
4619 g_assert_not_reached ();
4622 case OP_ICONV_TO_R4:
4623 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4624 ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4625 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4627 case OP_ICONV_TO_R8:
4628 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4629 ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4633 if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4634 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4635 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4637 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4643 case OP_FCONV_TO_I1:
4644 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4646 case OP_FCONV_TO_U1:
4647 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4649 case OP_FCONV_TO_I2:
4650 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4652 case OP_FCONV_TO_U2:
4653 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4655 case OP_FCONV_TO_I4:
4657 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4659 case OP_FCONV_TO_U4:
4661 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4663 case OP_FCONV_TO_I8:
4664 case OP_FCONV_TO_U8:
4665 g_assert_not_reached ();
4666 /* Implemented as helper calls */
4668 case OP_LCONV_TO_R_UN:
4669 g_assert_not_reached ();
4670 /* Implemented as helper calls */
4672 case OP_LCONV_TO_OVF_I4_2: {
4673 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4675 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4678 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4679 high_bit_not_set = code;
4680 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4682 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4683 valid_negative = code;
4684 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4685 invalid_negative = code;
4686 ARM_B_COND (code, ARMCOND_AL, 0);
4688 arm_patch (high_bit_not_set, code);
4690 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4691 valid_positive = code;
4692 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4694 arm_patch (invalid_negative, code);
4695 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4697 arm_patch (valid_negative, code);
4698 arm_patch (valid_positive, code);
4700 if (ins->dreg != ins->sreg1)
4701 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4706 ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4709 ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4712 ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4715 ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4718 ARM_FPA_MNFD (code, ins->dreg, ins->sreg1);
4720 #elif defined(ARM_FPU_VFP)
4722 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4725 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4728 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4731 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4734 ARM_NEGD (code, ins->dreg, ins->sreg1);
4739 g_assert_not_reached ();
4743 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4744 } else if (IS_VFP) {
4745 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4751 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4752 } else if (IS_VFP) {
4753 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4756 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4757 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4761 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4763 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4766 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4767 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4771 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4772 } else if (IS_VFP) {
4773 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4776 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4777 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4778 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4783 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4784 } else if (IS_VFP) {
4785 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4788 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4789 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4794 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4795 } else if (IS_VFP) {
4796 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4799 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4800 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4801 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4803 /* ARM FPA flags table:
4804 * N Less than ARMCOND_MI
4805 * Z Equal ARMCOND_EQ
4806 * C Greater Than or Equal ARMCOND_CS
4807 * V Unordered ARMCOND_VS
4810 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4813 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4816 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4819 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4820 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4826 g_assert_not_reached ();
4830 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4832 /* FPA requires EQ even thou the docs suggests that just CS is enough */
4833 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4834 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4838 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4839 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4844 if (ins->dreg != ins->sreg1)
4845 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4846 } else if (IS_VFP) {
4847 ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4848 ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4850 *(guint32*)code = 0xffffffff;
4852 *(guint32*)code = 0x7fefffff;
4854 ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4856 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4857 ARM_CMPD (code, ins->sreg1, ins->sreg1);
4859 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4860 ARM_CPYD (code, ins->dreg, ins->sreg1);
4865 case OP_GC_LIVENESS_DEF:
4866 case OP_GC_LIVENESS_USE:
4867 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4868 ins->backend.pc_offset = code - cfg->native_code;
4870 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4871 ins->backend.pc_offset = code - cfg->native_code;
4872 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4876 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4877 g_assert_not_reached ();
4880 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4881 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4882 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4883 g_assert_not_reached ();
4889 last_offset = offset;
4892 cfg->code_len = code - cfg->native_code;
4895 #endif /* DISABLE_JIT */
4897 #ifdef HAVE_AEABI_READ_TP
4898 void __aeabi_read_tp (void);
4902 mono_arch_register_lowlevel_calls (void)
4904 /* The signature doesn't matter */
4905 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4906 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4908 #ifndef MONO_CROSS_COMPILE
4909 #ifdef HAVE_AEABI_READ_TP
4910 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4915 #define patch_lis_ori(ip,val) do {\
4916 guint16 *__lis_ori = (guint16*)(ip); \
4917 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
4918 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
4922 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4924 MonoJumpInfo *patch_info;
4925 gboolean compile_aot = !run_cctors;
4927 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4928 unsigned char *ip = patch_info->ip.i + code;
4929 const unsigned char *target;
4931 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4932 gpointer *jt = (gpointer*)(ip + 8);
4934 /* jt is the inlined jump table, 2 instructions after ip
4935 * In the normal case we store the absolute addresses,
4936 * otherwise the displacements.
4938 for (i = 0; i < patch_info->data.table->table_size; i++)
4939 jt [i] = code + (int)patch_info->data.table->table [i];
4942 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4945 switch (patch_info->type) {
4946 case MONO_PATCH_INFO_BB:
4947 case MONO_PATCH_INFO_LABEL:
4950 /* No need to patch these */
4955 switch (patch_info->type) {
4956 case MONO_PATCH_INFO_IP:
4957 g_assert_not_reached ();
4958 patch_lis_ori (ip, ip);
4960 case MONO_PATCH_INFO_METHOD_REL:
4961 g_assert_not_reached ();
4962 *((gpointer *)(ip)) = code + patch_info->data.offset;
4964 case MONO_PATCH_INFO_METHODCONST:
4965 case MONO_PATCH_INFO_CLASS:
4966 case MONO_PATCH_INFO_IMAGE:
4967 case MONO_PATCH_INFO_FIELD:
4968 case MONO_PATCH_INFO_VTABLE:
4969 case MONO_PATCH_INFO_IID:
4970 case MONO_PATCH_INFO_SFLDA:
4971 case MONO_PATCH_INFO_LDSTR:
4972 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4973 case MONO_PATCH_INFO_LDTOKEN:
4974 g_assert_not_reached ();
4975 /* from OP_AOTCONST : lis + ori */
4976 patch_lis_ori (ip, target);
4978 case MONO_PATCH_INFO_R4:
4979 case MONO_PATCH_INFO_R8:
4980 g_assert_not_reached ();
4981 *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4983 case MONO_PATCH_INFO_EXC_NAME:
4984 g_assert_not_reached ();
4985 *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4987 case MONO_PATCH_INFO_NONE:
4988 case MONO_PATCH_INFO_BB_OVF:
4989 case MONO_PATCH_INFO_EXC_OVF:
4990 /* everything is dealt with at epilog output time */
4995 arm_patch_general (domain, ip, target, dyn_code_mp);
5002 * Stack frame layout:
5004 * ------------------- fp
5005 * MonoLMF structure or saved registers
5006 * -------------------
5008 * -------------------
5010 * -------------------
5011 * optional 8 bytes for tracing
5012 * -------------------
5013 * param area size is cfg->param_area
5014 * ------------------- sp
5017 mono_arch_emit_prolog (MonoCompile *cfg)
5019 MonoMethod *method = cfg->method;
5021 MonoMethodSignature *sig;
5023 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount;
5028 int prev_sp_offset, reg_offset;
5030 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5033 sig = mono_method_signature (method);
5034 cfg->code_size = 256 + sig->param_count * 64;
5035 code = cfg->native_code = g_malloc (cfg->code_size);
5037 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
5039 alloc_size = cfg->stack_offset;
5043 if (!method->save_lmf) {
5046 * The iphone uses R7 as the frame pointer, and it points at the saved
5051 * We can't use r7 as a frame pointer since it points into the middle of
5052 * the frame, so we keep using our own frame pointer.
5053 * FIXME: Optimize this.
5056 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5057 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
5058 prev_sp_offset += 8; /* r7 and lr */
5059 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5060 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
5062 /* No need to push LR again */
5063 if (cfg->used_int_regs)
5064 ARM_PUSH (code, cfg->used_int_regs);
5066 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
5067 prev_sp_offset += 4;
5069 for (i = 0; i < 16; ++i) {
5070 if (cfg->used_int_regs & (1 << i))
5071 prev_sp_offset += 4;
5073 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5075 for (i = 0; i < 16; ++i) {
5076 if ((cfg->used_int_regs & (1 << i))) {
5077 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5078 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
5083 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5084 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5086 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5087 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5090 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
5091 ARM_PUSH (code, 0x5ff0);
5092 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
5093 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5095 for (i = 0; i < 16; ++i) {
5096 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
5097 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5101 pos += sizeof (MonoLMF) - prev_sp_offset;
5105 orig_alloc_size = alloc_size;
5106 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
5107 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
5108 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
5109 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
5112 /* the stack used in the pushed regs */
5113 if (prev_sp_offset & 4)
5115 cfg->stack_usage = alloc_size;
5117 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
5118 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5120 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
5121 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5123 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
5125 if (cfg->frame_reg != ARMREG_SP) {
5126 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
5127 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
5129 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
5130 prev_sp_offset += alloc_size;
5132 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
5133 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
5135 /* compute max_offset in order to use short forward jumps
5136 * we could skip do it on arm because the immediate displacement
5137 * for jumps is large enough, it may be useful later for constant pools
5140 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5141 MonoInst *ins = bb->code;
5142 bb->max_offset = max_offset;
5144 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5147 MONO_BB_FOR_EACH_INS (bb, ins)
5148 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5151 /* store runtime generic context */
5152 if (cfg->rgctx_var) {
5153 MonoInst *ins = cfg->rgctx_var;
5155 g_assert (ins->opcode == OP_REGOFFSET);
5157 if (arm_is_imm12 (ins->inst_offset)) {
5158 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
5160 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5161 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
5165 /* load arguments allocated to register from the stack */
5168 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
5170 if (cinfo->vtype_retaddr) {
5171 ArgInfo *ainfo = &cinfo->ret;
5172 inst = cfg->vret_addr;
5173 g_assert (arm_is_imm12 (inst->inst_offset));
5174 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5177 if (sig->call_convention == MONO_CALL_VARARG) {
5178 ArgInfo *cookie = &cinfo->sig_cookie;
5180 /* Save the sig cookie address */
5181 g_assert (cookie->storage == RegTypeBase);
5183 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
5184 g_assert (arm_is_imm12 (cfg->sig_cookie));
5185 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
5186 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5189 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5190 ArgInfo *ainfo = cinfo->args + i;
5191 inst = cfg->args [pos];
5193 if (cfg->verbose_level > 2)
5194 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
5195 if (inst->opcode == OP_REGVAR) {
5196 if (ainfo->storage == RegTypeGeneral)
5197 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
5198 else if (ainfo->storage == RegTypeFP) {
5199 g_assert_not_reached ();
5200 } else if (ainfo->storage == RegTypeBase) {
5201 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5202 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5204 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5205 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
5208 g_assert_not_reached ();
5210 if (cfg->verbose_level > 2)
5211 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5213 /* the argument should be put on the stack: FIXME handle size != word */
5214 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
5215 switch (ainfo->size) {
5217 if (arm_is_imm12 (inst->inst_offset))
5218 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5220 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5221 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5225 if (arm_is_imm8 (inst->inst_offset)) {
5226 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5228 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5229 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5233 if (arm_is_imm12 (inst->inst_offset)) {
5234 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5236 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5237 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5239 if (arm_is_imm12 (inst->inst_offset + 4)) {
5240 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
5242 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5243 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
5247 if (arm_is_imm12 (inst->inst_offset)) {
5248 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5250 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5251 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5255 } else if (ainfo->storage == RegTypeBaseGen) {
5256 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
5257 g_assert (arm_is_imm12 (inst->inst_offset));
5258 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5259 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5260 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
5261 } else if (ainfo->storage == RegTypeBase) {
5262 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5263 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5265 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
5266 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5269 switch (ainfo->size) {
5271 if (arm_is_imm8 (inst->inst_offset)) {
5272 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5274 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5275 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5279 if (arm_is_imm8 (inst->inst_offset)) {
5280 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5282 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5283 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5287 if (arm_is_imm12 (inst->inst_offset)) {
5288 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5290 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5291 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5293 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
5294 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
5296 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
5297 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5299 if (arm_is_imm12 (inst->inst_offset + 4)) {
5300 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5302 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5303 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5307 if (arm_is_imm12 (inst->inst_offset)) {
5308 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5310 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5311 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5315 } else if (ainfo->storage == RegTypeFP) {
5316 g_assert_not_reached ();
5317 } else if (ainfo->storage == RegTypeStructByVal) {
5318 int doffset = inst->inst_offset;
5322 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
5323 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
5324 if (arm_is_imm12 (doffset)) {
5325 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
5327 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
5328 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
5330 soffset += sizeof (gpointer);
5331 doffset += sizeof (gpointer);
5333 if (ainfo->vtsize) {
5334 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5335 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
5336 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
5338 } else if (ainfo->storage == RegTypeStructByAddr) {
5339 g_assert_not_reached ();
5340 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5341 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
5343 g_assert_not_reached ();
5348 if (method->save_lmf)
5349 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
5352 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5354 if (cfg->arch.seq_point_info_var) {
5355 MonoInst *ins = cfg->arch.seq_point_info_var;
5357 /* Initialize the variable from a GOT slot */
5358 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
5359 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5361 *(gpointer*)code = NULL;
5363 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
5365 g_assert (ins->opcode == OP_REGOFFSET);
5367 if (arm_is_imm12 (ins->inst_offset)) {
5368 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5370 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5371 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5375 /* Initialize ss_trigger_page_var */
5376 if (!cfg->soft_breakpoints) {
5377 MonoInst *info_var = cfg->arch.seq_point_info_var;
5378 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
5379 int dreg = ARMREG_LR;
5382 g_assert (info_var->opcode == OP_REGOFFSET);
5383 g_assert (arm_is_imm12 (info_var->inst_offset));
5385 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
5386 /* Load the trigger page addr */
5387 ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
5388 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
5392 if (cfg->arch.seq_point_read_var) {
5393 MonoInst *read_ins = cfg->arch.seq_point_read_var;
5394 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
5395 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
5397 g_assert (read_ins->opcode == OP_REGOFFSET);
5398 g_assert (arm_is_imm12 (read_ins->inst_offset));
5399 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
5400 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
5401 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
5402 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
5404 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5406 *(volatile int **)code = &ss_trigger_var;
5408 *(gpointer*)code = single_step_func_wrapper;
5410 *(gpointer*)code = breakpoint_func_wrapper;
5413 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
5414 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
5415 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
5416 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
5417 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
5418 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
5421 cfg->code_len = code - cfg->native_code;
5422 g_assert (cfg->code_len < cfg->code_size);
5429 mono_arch_emit_epilog (MonoCompile *cfg)
5431 MonoMethod *method = cfg->method;
5432 int pos, i, rot_amount;
5433 int max_epilog_size = 16 + 20*4;
5437 if (cfg->method->save_lmf)
5438 max_epilog_size += 128;
5440 if (mono_jit_trace_calls != NULL)
5441 max_epilog_size += 50;
5443 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5444 max_epilog_size += 50;
5446 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5447 cfg->code_size *= 2;
5448 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5449 cfg->stat_code_reallocs++;
5453 * Keep in sync with OP_JMP
5455 code = cfg->native_code + cfg->code_len;
5457 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5458 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5462 /* Load returned vtypes into registers if needed */
5463 cinfo = cfg->arch.cinfo;
5464 if (cinfo->ret.storage == RegTypeStructByVal) {
5465 MonoInst *ins = cfg->ret;
5467 if (arm_is_imm12 (ins->inst_offset)) {
5468 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5470 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5471 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5475 if (method->save_lmf) {
5476 int lmf_offset, reg, sp_adj, regmask;
5477 /* all but r0-r3, sp and pc */
5478 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5481 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
5483 /* This points to r4 inside MonoLMF->iregs */
5484 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5486 regmask = 0x9ff0; /* restore lr to pc */
5487 /* Skip caller saved registers not used by the method */
5488 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5489 regmask &= ~(1 << reg);
5493 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5494 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
5496 ARM_POP (code, regmask);
5498 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5499 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5501 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5502 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5506 /* Restore saved gregs */
5507 if (cfg->used_int_regs)
5508 ARM_POP (code, cfg->used_int_regs);
5509 /* Restore saved r7, restore LR to PC */
5510 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5512 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5516 cfg->code_len = code - cfg->native_code;
5518 g_assert (cfg->code_len < cfg->code_size);
5522 /* remove once throw_exception_by_name is eliminated */
5524 exception_id_by_name (const char *name)
5526 if (strcmp (name, "IndexOutOfRangeException") == 0)
5527 return MONO_EXC_INDEX_OUT_OF_RANGE;
5528 if (strcmp (name, "OverflowException") == 0)
5529 return MONO_EXC_OVERFLOW;
5530 if (strcmp (name, "ArithmeticException") == 0)
5531 return MONO_EXC_ARITHMETIC;
5532 if (strcmp (name, "DivideByZeroException") == 0)
5533 return MONO_EXC_DIVIDE_BY_ZERO;
5534 if (strcmp (name, "InvalidCastException") == 0)
5535 return MONO_EXC_INVALID_CAST;
5536 if (strcmp (name, "NullReferenceException") == 0)
5537 return MONO_EXC_NULL_REF;
5538 if (strcmp (name, "ArrayTypeMismatchException") == 0)
5539 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5540 if (strcmp (name, "ArgumentException") == 0)
5541 return MONO_EXC_ARGUMENT;
5542 g_error ("Unknown intrinsic exception %s\n", name);
5547 mono_arch_emit_exceptions (MonoCompile *cfg)
5549 MonoJumpInfo *patch_info;
5552 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5553 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5554 int max_epilog_size = 50;
5556 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5557 exc_throw_pos [i] = NULL;
5558 exc_throw_found [i] = 0;
5561 /* count the number of exception infos */
5564 * make sure we have enough space for exceptions
5566 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5567 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5568 i = exception_id_by_name (patch_info->data.target);
5569 if (!exc_throw_found [i]) {
5570 max_epilog_size += 32;
5571 exc_throw_found [i] = TRUE;
5576 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5577 cfg->code_size *= 2;
5578 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5579 cfg->stat_code_reallocs++;
5582 code = cfg->native_code + cfg->code_len;
5584 /* add code to raise exceptions */
5585 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5586 switch (patch_info->type) {
5587 case MONO_PATCH_INFO_EXC: {
5588 MonoClass *exc_class;
5589 unsigned char *ip = patch_info->ip.i + cfg->native_code;
5591 i = exception_id_by_name (patch_info->data.target);
5592 if (exc_throw_pos [i]) {
5593 arm_patch (ip, exc_throw_pos [i]);
5594 patch_info->type = MONO_PATCH_INFO_NONE;
5597 exc_throw_pos [i] = code;
5599 arm_patch (ip, code);
5601 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5602 g_assert (exc_class);
5604 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5605 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5606 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5607 patch_info->data.name = "mono_arch_throw_corlib_exception";
5608 patch_info->ip.i = code - cfg->native_code;
5610 *(guint32*)(gpointer)code = exc_class->type_token;
5620 cfg->code_len = code - cfg->native_code;
5622 g_assert (cfg->code_len < cfg->code_size);
5626 #endif /* #ifndef DISABLE_JIT */
5629 mono_arch_finish_init (void)
5631 lmf_tls_offset = mono_get_lmf_tls_offset ();
5632 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5636 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5641 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5648 mono_arch_print_tree (MonoInst *tree, int arity)
5654 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5656 return mono_get_domain_intrinsic (cfg);
5660 mono_arch_get_patch_offset (guint8 *code)
5667 mono_arch_flush_register_windows (void)
5671 #ifdef MONO_ARCH_HAVE_IMT
5676 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5678 if (cfg->compile_aot) {
5679 int method_reg = mono_alloc_ireg (cfg);
5682 call->dynamic_imt_arg = TRUE;
5685 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5687 MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5688 ins->dreg = method_reg;
5689 ins->inst_p0 = call->method;
5690 ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5691 MONO_ADD_INS (cfg->cbb, ins);
5693 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5695 } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5697 /* Always pass in a register for simplicity */
5698 call->dynamic_imt_arg = TRUE;
5700 cfg->uses_rgctx_reg = TRUE;
5703 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5706 int method_reg = mono_alloc_preg (cfg);
5708 MONO_INST_NEW (cfg, ins, OP_PCONST);
5709 ins->inst_p0 = call->method;
5710 ins->dreg = method_reg;
5711 MONO_ADD_INS (cfg->cbb, ins);
5713 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5718 #endif /* DISABLE_JIT */
5721 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5723 guint32 *code_ptr = (guint32*)code;
5728 return (MonoMethod*)regs [ARMREG_V5];
5730 /* The IMT value is stored in the code stream right after the LDC instruction. */
5731 /* This is no longer true for the gsharedvt_in trampoline */
5733 if (!IS_LDR_PC (code_ptr [0])) {
5734 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5735 g_assert (IS_LDR_PC (code_ptr [0]));
5738 if (code_ptr [1] == 0)
5739 /* This is AOTed code, or the gsharedvt trampoline, the IMT method is in V5 */
5740 return (MonoMethod*)regs [ARMREG_V5];
5742 return (MonoMethod*) code_ptr [1];
5746 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5748 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5751 #define ENABLE_WRONG_METHOD_CHECK 0
5752 #define BASE_SIZE (6 * 4)
5753 #define BSEARCH_ENTRY_SIZE (4 * 4)
5754 #define CMP_SIZE (3 * 4)
5755 #define BRANCH_SIZE (1 * 4)
5756 #define CALL_SIZE (2 * 4)
5757 #define WMC_SIZE (5 * 4)
5758 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5761 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5763 guint32 delta = DISTANCE (target, code);
5765 g_assert (delta >= 0 && delta <= 0xFFF);
5766 *target = *target | delta;
5772 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5773 gpointer fail_tramp)
5775 int size, i, extra_space = 0;
5776 arminstr_t *code, *start, *vtable_target = NULL;
5777 gboolean large_offsets = FALSE;
5778 guint32 **constant_pool_starts;
5781 constant_pool_starts = g_new0 (guint32*, count);
5783 for (i = 0; i < count; ++i) {
5784 MonoIMTCheckItem *item = imt_entries [i];
5785 if (item->is_equals) {
5786 gboolean fail_case = !item->check_target_idx && fail_tramp;
5788 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5789 item->chunk_size += 32;
5790 large_offsets = TRUE;
5793 if (item->check_target_idx || fail_case) {
5794 if (!item->compare_done || fail_case)
5795 item->chunk_size += CMP_SIZE;
5796 item->chunk_size += BRANCH_SIZE;
5798 #if ENABLE_WRONG_METHOD_CHECK
5799 item->chunk_size += WMC_SIZE;
5803 item->chunk_size += 16;
5804 large_offsets = TRUE;
5806 item->chunk_size += CALL_SIZE;
5808 item->chunk_size += BSEARCH_ENTRY_SIZE;
5809 imt_entries [item->check_target_idx]->compare_done = TRUE;
5811 size += item->chunk_size;
5815 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5818 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5820 code = mono_domain_code_reserve (domain, size);
5824 printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5825 for (i = 0; i < count; ++i) {
5826 MonoIMTCheckItem *item = imt_entries [i];
5827 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5832 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5834 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5835 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5836 vtable_target = code;
5837 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5839 if (mono_use_llvm) {
5840 /* LLVM always passes the IMT method in R5 */
5841 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5843 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5844 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5845 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5848 for (i = 0; i < count; ++i) {
5849 MonoIMTCheckItem *item = imt_entries [i];
5850 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5851 gint32 vtable_offset;
5853 item->code_target = (guint8*)code;
5855 if (item->is_equals) {
5856 gboolean fail_case = !item->check_target_idx && fail_tramp;
5858 if (item->check_target_idx || fail_case) {
5859 if (!item->compare_done || fail_case) {
5861 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5862 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5864 item->jmp_code = (guint8*)code;
5865 ARM_B_COND (code, ARMCOND_NE, 0);
5867 /*Enable the commented code to assert on wrong method*/
5868 #if ENABLE_WRONG_METHOD_CHECK
5870 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5871 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5872 ARM_B_COND (code, ARMCOND_NE, 1);
5878 if (item->has_target_code) {
5879 target_code_ins = code;
5880 /* Load target address */
5881 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5882 /* Save it to the fourth slot */
5883 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5884 /* Restore registers and branch */
5885 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5887 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5889 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5890 if (!arm_is_imm12 (vtable_offset)) {
5892 * We need to branch to a computed address but we don't have
5893 * a free register to store it, since IP must contain the
5894 * vtable address. So we push the two values to the stack, and
5895 * load them both using LDM.
5897 /* Compute target address */
5898 vtable_offset_ins = code;
5899 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5900 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5901 /* Save it to the fourth slot */
5902 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5903 /* Restore registers and branch */
5904 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5906 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5908 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5910 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5911 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5916 arm_patch (item->jmp_code, (guchar*)code);
5918 target_code_ins = code;
5919 /* Load target address */
5920 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5921 /* Save it to the fourth slot */
5922 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5923 /* Restore registers and branch */
5924 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5926 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5927 item->jmp_code = NULL;
5931 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5933 /*must emit after unconditional branch*/
5934 if (vtable_target) {
5935 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5936 item->chunk_size += 4;
5937 vtable_target = NULL;
5940 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5941 constant_pool_starts [i] = code;
5943 code += extra_space;
5947 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5948 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5950 item->jmp_code = (guint8*)code;
5951 ARM_B_COND (code, ARMCOND_GE, 0);
5956 for (i = 0; i < count; ++i) {
5957 MonoIMTCheckItem *item = imt_entries [i];
5958 if (item->jmp_code) {
5959 if (item->check_target_idx)
5960 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5962 if (i > 0 && item->is_equals) {
5964 arminstr_t *space_start = constant_pool_starts [i];
5965 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5966 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5973 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5974 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5979 g_free (constant_pool_starts);
5981 mono_arch_flush_icache ((guint8*)start, size);
5982 mono_stats.imt_thunks_size += code - start;
5984 g_assert (DISTANCE (start, code) <= size);
5991 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5993 return ctx->regs [reg];
5997 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
5999 ctx->regs [reg] = val;
6003 * mono_arch_get_trampolines:
6005 * Return a list of MonoTrampInfo structures describing arch specific trampolines
6009 mono_arch_get_trampolines (gboolean aot)
6011 return mono_arm_get_exception_trampolines (aot);
6015 * mono_arch_set_breakpoint:
6017 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6018 * The location should contain code emitted by OP_SEQ_POINT.
6021 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6024 guint32 native_offset = ip - (guint8*)ji->code_start;
6025 MonoDebugOptions *opt = mini_get_debug_options ();
6027 if (opt->soft_breakpoints) {
6028 g_assert (!ji->from_aot);
6030 ARM_BLX_REG (code, ARMREG_LR);
6031 mono_arch_flush_icache (code - 4, 4);
6032 } else if (ji->from_aot) {
6033 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6035 g_assert (native_offset % 4 == 0);
6036 g_assert (info->bp_addrs [native_offset / 4] == 0);
6037 info->bp_addrs [native_offset / 4] = bp_trigger_page;
6039 int dreg = ARMREG_LR;
6041 /* Read from another trigger page */
6042 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
6044 *(int*)code = (int)bp_trigger_page;
6046 ARM_LDR_IMM (code, dreg, dreg, 0);
6048 mono_arch_flush_icache (code - 16, 16);
6051 /* This is currently implemented by emitting an SWI instruction, which
6052 * qemu/linux seems to convert to a SIGILL.
6054 *(int*)code = (0xef << 24) | 8;
6056 mono_arch_flush_icache (code - 4, 4);
6062 * mono_arch_clear_breakpoint:
6064 * Clear the breakpoint at IP.
6067 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6069 MonoDebugOptions *opt = mini_get_debug_options ();
6073 if (opt->soft_breakpoints) {
6074 g_assert (!ji->from_aot);
6077 mono_arch_flush_icache (code - 4, 4);
6078 } else if (ji->from_aot) {
6079 guint32 native_offset = ip - (guint8*)ji->code_start;
6080 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6082 g_assert (native_offset % 4 == 0);
6083 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
6084 info->bp_addrs [native_offset / 4] = 0;
6086 for (i = 0; i < 4; ++i)
6089 mono_arch_flush_icache (ip, code - ip);
6094 * mono_arch_start_single_stepping:
6096 * Start single stepping.
6099 mono_arch_start_single_stepping (void)
6101 if (ss_trigger_page)
6102 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6108 * mono_arch_stop_single_stepping:
6110 * Stop single stepping.
6113 mono_arch_stop_single_stepping (void)
6115 if (ss_trigger_page)
6116 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6122 #define DBG_SIGNAL SIGBUS
6124 #define DBG_SIGNAL SIGSEGV
6128 * mono_arch_is_single_step_event:
6130 * Return whenever the machine state in SIGCTX corresponds to a single
6134 mono_arch_is_single_step_event (void *info, void *sigctx)
6136 siginfo_t *sinfo = info;
6138 if (!ss_trigger_page)
6141 /* Sometimes the address is off by 4 */
6142 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
6149 * mono_arch_is_breakpoint_event:
6151 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
6154 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6156 siginfo_t *sinfo = info;
6158 if (!ss_trigger_page)
6161 if (sinfo->si_signo == DBG_SIGNAL) {
6162 /* Sometimes the address is off by 4 */
6163 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
6173 * mono_arch_skip_breakpoint:
6175 * See mini-amd64.c for docs.
6178 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6180 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6184 * mono_arch_skip_single_step:
6186 * See mini-amd64.c for docs.
6189 mono_arch_skip_single_step (MonoContext *ctx)
6191 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6195 * mono_arch_get_seq_point_info:
6197 * See mini-amd64.c for docs.
6200 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6205 // FIXME: Add a free function
6207 mono_domain_lock (domain);
6208 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
6210 mono_domain_unlock (domain);
6213 ji = mono_jit_info_table_find (domain, (char*)code);
6216 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
6218 info->ss_trigger_page = ss_trigger_page;
6219 info->bp_trigger_page = bp_trigger_page;
6221 mono_domain_lock (domain);
6222 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
6224 mono_domain_unlock (domain);
6231 * mono_arch_set_target:
6233 * Set the target architecture the JIT backend should generate code for, in the form
6234 * of a GNU target triplet. Only used in AOT mode.
6237 mono_arch_set_target (char *mtriple)
6239 /* The GNU target triple format is not very well documented */
6240 if (strstr (mtriple, "armv7")) {
6241 v6_supported = TRUE;
6242 v7_supported = TRUE;
6244 if (strstr (mtriple, "armv6")) {
6245 v6_supported = TRUE;
6247 if (strstr (mtriple, "darwin")) {
6248 v5_supported = TRUE;
6249 thumb_supported = TRUE;
6253 if (strstr (mtriple, "gnueabi"))
6254 eabi_supported = TRUE;
6257 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
6259 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
6264 mono_arch_gsharedvt_sig_supported (MonoMethodSignature *sig)
6270 mono_arch_get_gsharedvt_call_info (gpointer addr, MonoMethod *normal_method, MonoMethod *gsharedvt_method, MonoGenericSharingContext *gsctx, gboolean gsharedvt_in, gint32 vcall_offset)
6276 #endif /* !MONOTOUCH */