mono/mini/mini-arm.c

   1 /*
   2  * mini-arm.c: ARM backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *
   8  * (C) 2003 Ximian, Inc.
   9  */
  10 #include "mini.h"
  11 #include <string.h>
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15
  16 #include "mini-arm.h"
  17 #include "inssel.h"
  18 #include "cpu-arm.h"
  19 #include "trace.h"
  20 #include "mono/arch/arm/arm-fpa-codegen.h"
  21
  22 /*
  23  * TODO:
  24  * floating point support: on ARM it is a mess, there are at least 3
  25  * different setups, each of which binary incompat with the other.
  26  * 1) FPA: old and ugly, but unfortunately what current distros use
  27  *    the double binary format has the two words swapped. 8 double registers.
  28  *    Implemented usually by kernel emulation.
  29  * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
  30  *    ugly swapped double format (I guess a softfloat-vfp exists, too, though).
  31  * 3) VFP: the new and actually sensible and useful FP support. Implemented
  32  *    in HW or kernel-emulated, requires new tools. I think this ios what symbian uses.
  33  *
  34  * The plan is to write the FPA support first. softfloat can be tested in a chroot.
  35  */
  36 int mono_exc_esp_offset = 0;
  37
  38 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
  39 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
  40 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
  41
  42 const char*
  43 mono_arch_regname (int reg) {
  44         static const char * rnames[] = {
  45                 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
  46                 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
  47                 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
  48                 "arm_pc"
  49         };
  50         if (reg >= 0 && reg < 16)
  51                 return rnames [reg];
  52         return "unknown";
  53 }
  54
  55 const char*
  56 mono_arch_fregname (int reg) {
  57         static const char * rnames[] = {
  58                 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
  59                 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
  60                 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
  61                 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
  62                 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
  63                 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
  64                 "arm_f30", "arm_f31"
  65         };
  66         if (reg >= 0 && reg < 32)
  67                 return rnames [reg];
  68         return "unknown";
  69 }
  70
  71 static guint8*
  72 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
  73 {
  74         int imm8, rot_amount;
  75         if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
  76                 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
  77                 return code;
  78         }
  79         g_assert (dreg != sreg);
  80         code = mono_arm_emit_load_imm (code, dreg, imm);
  81         ARM_ADD_REG_REG (code, dreg, dreg, sreg);
  82         return code;
  83 }
  84
  85 static guint8*
  86 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
  87 {
  88         /* we can use r0-r3, since this is called only for incoming args on the stack */
  89         if (size > sizeof (gpointer) * 4) {
  90                 guint8 *start_loop;
  91                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
  92                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
  93                 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
  94                 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
  95                 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
  96                 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
  97                 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
  98                 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
  99                 ARM_B_COND (code, ARMCOND_NE, 0);
 100                 arm_patch (code - 4, start_loop);
 101                 return code;
 102         }
 103         g_assert (arm_is_imm12 (doffset));
 104         g_assert (arm_is_imm12 (doffset + size));
 105         g_assert (arm_is_imm12 (soffset));
 106         g_assert (arm_is_imm12 (soffset + size));
 107         while (size >= 4) {
 108                 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
 109                 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
 110                 doffset += 4;
 111                 soffset += 4;
 112                 size -= 4;
 113         }
 114         g_assert (size == 0);
 115         return code;
 116 }
 117
 118 /*
 119  * mono_arch_get_argument_info:
 120  * @csig:  a method signature
 121  * @param_count: the number of parameters to consider
 122  * @arg_info: an array to store the result infos
 123  *
 124  * Gathers information on parameters such as size, alignment and
 125  * padding. arg_info should be large enought to hold param_count + 1 entries.
 126  *
 127  * Returns the size of the activation frame.
 128  */
 129 int
 130 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 131 {
 132         int k, frame_size = 0;
 133         int size, align, pad;
 134         int offset = 8;
 135
 136         if (MONO_TYPE_ISSTRUCT (csig->ret)) {
 137                 frame_size += sizeof (gpointer);
 138                 offset += 4;
 139         }
 140
 141         arg_info [0].offset = offset;
 142
 143         if (csig->hasthis) {
 144                 frame_size += sizeof (gpointer);
 145                 offset += 4;
 146         }
 147
 148         arg_info [0].size = frame_size;
 149
 150         for (k = 0; k < param_count; k++) {
 151
 152                 if (csig->pinvoke)
 153                         size = mono_type_native_stack_size (csig->params [k], &align);
 154                 else
 155                         size = mono_type_stack_size (csig->params [k], &align);
 156
 157                 /* ignore alignment for now */
 158                 align = 1;
 159
 160                 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 161                 arg_info [k].pad = pad;
 162                 frame_size += size;
 163                 arg_info [k + 1].pad = 0;
 164                 arg_info [k + 1].size = size;
 165                 offset += pad;
 166                 arg_info [k + 1].offset = offset;
 167                 offset += size;
 168         }
 169
 170         align = MONO_ARCH_FRAME_ALIGNMENT;
 171         frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 172         arg_info [k].pad = pad;
 173
 174         return frame_size;
 175 }
 176
 177 /*
 178  * Initialize the cpu to execute managed code.
 179  */
 180 void
 181 mono_arch_cpu_init (void)
 182 {
 183 }
 184
 185 /*
 186  * This function returns the optimizations supported on this cpu.
 187  */
 188 guint32
 189 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 190 {
 191         guint32 opts = 0;
 192
 193         /* no arm-specific optimizations yet */
 194         *exclude_mask = 0;
 195         return opts;
 196 }
 197
 198 static gboolean
 199 is_regsize_var (MonoType *t) {
 200         if (t->byref)
 201                 return TRUE;
 202         t = mono_type_get_underlying_type (t);
 203         switch (t->type) {
 204         case MONO_TYPE_I4:
 205         case MONO_TYPE_U4:
 206         case MONO_TYPE_I:
 207         case MONO_TYPE_U:
 208         case MONO_TYPE_PTR:
 209         case MONO_TYPE_FNPTR:
 210                 return TRUE;
 211         case MONO_TYPE_OBJECT:
 212         case MONO_TYPE_STRING:
 213         case MONO_TYPE_CLASS:
 214         case MONO_TYPE_SZARRAY:
 215         case MONO_TYPE_ARRAY:
 216                 return TRUE;
 217         case MONO_TYPE_VALUETYPE:
 218                 return FALSE;
 219         }
 220         return FALSE;
 221 }
 222
 223 GList *
 224 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 225 {
 226         GList *vars = NULL;
 227         int i;
 228
 229         for (i = 0; i < cfg->num_varinfo; i++) {
 230                 MonoInst *ins = cfg->varinfo [i];
 231                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 232
 233                 /* unused vars */
 234                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 235                         continue;
 236
 237                 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 238                         continue;
 239
 240                 /* we can only allocate 32 bit values */
 241                 if (is_regsize_var (ins->inst_vtype)) {
 242                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 243                         g_assert (i == vmv->idx);
 244                         vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
 245                 }
 246         }
 247
 248         return vars;
 249 }
 250
 251 #define USE_EXTRA_TEMPS 0
 252
 253 GList *
 254 mono_arch_get_global_int_regs (MonoCompile *cfg)
 255 {
 256         GList *regs = NULL;
 257         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
 258         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
 259         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
 260         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
 261         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
 262         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
 263         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
 264
 265         return regs;
 266 }
 267
 268 /*
 269  * mono_arch_regalloc_cost:
 270  *
 271  *  Return the cost, in number of memory references, of the action of
 272  * allocating the variable VMV into a register during global register
 273  * allocation.
 274  */
 275 guint32
 276 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 277 {
 278         /* FIXME: */
 279         return 2;
 280 }
 281
 282 void
 283 mono_arch_flush_icache (guint8 *code, gint size)
 284 {
 285         __asm __volatile ("mov r0, %0\n"
 286                         "mov r1, %1\n"
 287                         "mov r2, %2\n"
 288                         "swi 0x9f0002       @ sys_cacheflush"
 289                         : /* no outputs */
 290                         : "r" (code), "r" (code + size), "r" (0)
 291                         : "r0", "r1", "r3" );
 292
 293 }
 294
 295 #define NOT_IMPLEMENTED(x) \
 296                 g_error ("FIXME: %s is not yet implemented. (trampoline)", x);
 297
 298 enum {
 299         RegTypeGeneral,
 300         RegTypeBase,
 301         RegTypeFP,
 302         RegTypeStructByVal,
 303         RegTypeStructByAddr
 304 };
 305
 306 typedef struct {
 307         gint32  offset;
 308         guint16 vtsize; /* in param area */
 309         guint8  reg;
 310         guint8  regtype : 4; /* 0 general, 1 basereg, 2 floating point register, see RegType* */
 311         guint8  size    : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
 312 } ArgInfo;
 313
 314 typedef struct {
 315         int nargs;
 316         guint32 stack_usage;
 317         guint32 struct_ret;
 318         ArgInfo ret;
 319         ArgInfo sig_cookie;
 320         ArgInfo args [1];
 321 } CallInfo;
 322
 323 #define DEBUG(a)
 324
 325 static void inline
 326 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
 327 {
 328         if (simple) {
 329                 if (*gr > ARMREG_R3) {
 330                         ainfo->offset = *stack_size;
 331                         ainfo->reg = ARMREG_SP; /* in the caller */
 332                         ainfo->regtype = RegTypeBase;
 333                         *stack_size += 4;
 334                 } else {
 335                         ainfo->reg = *gr;
 336                 }
 337         } else {
 338                 if (*gr > ARMREG_R2) {
 339                         *stack_size += 7;
 340                         *stack_size &= ~7;
 341                         ainfo->offset = *stack_size;
 342                         ainfo->reg = ARMREG_SP; /* in the caller */
 343                         ainfo->regtype = RegTypeBase;
 344                         *stack_size += 8;
 345                 } else {
 346                         /*if ((*gr) & 1)
 347                                 (*gr) ++;*/
 348                         ainfo->reg = *gr;
 349                 }
 350                 (*gr) ++;
 351         }
 352         (*gr) ++;
 353 }
 354
 355 static CallInfo*
 356 calculate_sizes (MonoMethodSignature *sig, gboolean is_pinvoke)
 357 {
 358         guint i, gr;
 359         int n = sig->hasthis + sig->param_count;
 360         guint32 simpletype;
 361         guint32 stack_size = 0;
 362         CallInfo *cinfo = g_malloc0 (sizeof (CallInfo) + sizeof (ArgInfo) * n);
 363
 364         gr = ARMREG_R0;
 365
 366         /* FIXME: handle returning a struct */
 367         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 368                 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
 369                 cinfo->struct_ret = ARMREG_R0;
 370         }
 371
 372         n = 0;
 373         if (sig->hasthis) {
 374                 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 375                 n++;
 376         }
 377         DEBUG(printf("params: %d\n", sig->param_count));
 378         for (i = 0; i < sig->param_count; ++i) {
 379                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 380                         /* Prevent implicit arguments and sig_cookie from
 381                            being passed in registers */
 382                         gr = ARMREG_R3 + 1;
 383                         /* Emit the signature cookie just before the implicit arguments */
 384                         add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
 385                 }
 386                 DEBUG(printf("param %d: ", i));
 387                 if (sig->params [i]->byref) {
 388                         DEBUG(printf("byref\n"));
 389                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 390                         n++;
 391                         continue;
 392                 }
 393                 simpletype = mono_type_get_underlying_type (sig->params [i])->type;
 394                 switch (simpletype) {
 395                 case MONO_TYPE_BOOLEAN:
 396                 case MONO_TYPE_I1:
 397                 case MONO_TYPE_U1:
 398                         cinfo->args [n].size = 1;
 399                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 400                         n++;
 401                         break;
 402                 case MONO_TYPE_CHAR:
 403                 case MONO_TYPE_I2:
 404                 case MONO_TYPE_U2:
 405                         cinfo->args [n].size = 2;
 406                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 407                         n++;
 408                         break;
 409                 case MONO_TYPE_I4:
 410                 case MONO_TYPE_U4:
 411                         cinfo->args [n].size = 4;
 412                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 413                         n++;
 414                         break;
 415                 case MONO_TYPE_I:
 416                 case MONO_TYPE_U:
 417                 case MONO_TYPE_PTR:
 418                 case MONO_TYPE_FNPTR:
 419                 case MONO_TYPE_CLASS:
 420                 case MONO_TYPE_OBJECT:
 421                 case MONO_TYPE_STRING:
 422                 case MONO_TYPE_SZARRAY:
 423                 case MONO_TYPE_ARRAY:
 424                 case MONO_TYPE_R4:
 425                         cinfo->args [n].size = sizeof (gpointer);
 426                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 427                         n++;
 428                         break;
 429                 case MONO_TYPE_TYPEDBYREF:
 430                 case MONO_TYPE_VALUETYPE: {
 431                         gint size;
 432                         int align_size;
 433                         int nwords;
 434
 435                         if (simpletype == MONO_TYPE_TYPEDBYREF) {
 436                                 size = sizeof (MonoTypedRef);
 437                         } else {
 438                                 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
 439                                 if (is_pinvoke)
 440                                         size = mono_class_native_size (klass, NULL);
 441                                 else
 442                                         size = mono_class_value_size (klass, NULL);
 443                         }
 444                         DEBUG(printf ("load %d bytes struct\n",
 445                                       mono_class_native_size (sig->params [i]->data.klass, NULL)));
 446                         align_size = size;
 447                         nwords = 0;
 448                         align_size += (sizeof (gpointer) - 1);
 449                         align_size &= ~(sizeof (gpointer) - 1);
 450                         nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
 451                         cinfo->args [n].regtype = RegTypeStructByVal;
 452                         /* FIXME: align gr and stack_size if needed */
 453                         if (gr > ARMREG_R3) {
 454                                 cinfo->args [n].size = 0;
 455                                 cinfo->args [n].vtsize = nwords;
 456                         } else {
 457                                 int rest = ARMREG_R3 - gr + 1;
 458                                 int n_in_regs = rest >= nwords? nwords: rest;
 459                                 cinfo->args [n].size = n_in_regs;
 460                                 cinfo->args [n].vtsize = nwords - n_in_regs;
 461                                 cinfo->args [n].reg = gr;
 462                                 gr += n_in_regs;
 463                         }
 464                         cinfo->args [n].offset = stack_size;
 465                         /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
 466                         stack_size += nwords * sizeof (gpointer);
 467                         n++;
 468                         break;
 469                 }
 470                 case MONO_TYPE_U8:
 471                 case MONO_TYPE_I8:
 472                 case MONO_TYPE_R8:
 473                         cinfo->args [n].size = 8;
 474                         add_general (&gr, &stack_size, cinfo->args + n, FALSE);
 475                         n++;
 476                         break;
 477                 default:
 478                         g_error ("Can't trampoline 0x%x", sig->params [i]->type);
 479                 }
 480         }
 481
 482         {
 483                 simpletype = mono_type_get_underlying_type (sig->ret)->type;
 484                 switch (simpletype) {
 485                 case MONO_TYPE_BOOLEAN:
 486                 case MONO_TYPE_I1:
 487                 case MONO_TYPE_U1:
 488                 case MONO_TYPE_I2:
 489                 case MONO_TYPE_U2:
 490                 case MONO_TYPE_CHAR:
 491                 case MONO_TYPE_I4:
 492                 case MONO_TYPE_U4:
 493                 case MONO_TYPE_I:
 494                 case MONO_TYPE_U:
 495                 case MONO_TYPE_PTR:
 496                 case MONO_TYPE_FNPTR:
 497                 case MONO_TYPE_CLASS:
 498                 case MONO_TYPE_OBJECT:
 499                 case MONO_TYPE_SZARRAY:
 500                 case MONO_TYPE_ARRAY:
 501                 case MONO_TYPE_STRING:
 502                         cinfo->ret.reg = ARMREG_R0;
 503                         break;
 504                 case MONO_TYPE_U8:
 505                 case MONO_TYPE_I8:
 506                         cinfo->ret.reg = ARMREG_R0;
 507                         break;
 508                 case MONO_TYPE_R4:
 509                 case MONO_TYPE_R8:
 510                         cinfo->ret.reg = ARMREG_R0;
 511                         /* FIXME: cinfo->ret.reg = ???;
 512                         cinfo->ret.regtype = RegTypeFP;*/
 513                         break;
 514                 case MONO_TYPE_VALUETYPE:
 515                         break;
 516                 case MONO_TYPE_TYPEDBYREF:
 517                 case MONO_TYPE_VOID:
 518                         break;
 519                 default:
 520                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 521                 }
 522         }
 523
 524         /* align stack size to 8 */
 525         DEBUG (printf ("      stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
 526         stack_size = (stack_size + 7) & ~7;
 527
 528         cinfo->stack_usage = stack_size;
 529         return cinfo;
 530 }
 531
 532
 533 /*
 534  * Set var information according to the calling convention. arm version.
 535  * The locals var stuff should most likely be split in another method.
 536  */
 537 void
 538 mono_arch_allocate_vars (MonoCompile *m)
 539 {
 540         MonoMethodSignature *sig;
 541         MonoMethodHeader *header;
 542         MonoInst *inst;
 543         int i, offset, size, align, curinst;
 544         int frame_reg = ARMREG_FP;
 545
 546         /* FIXME: this will change when we use FP as gcc does */
 547         m->flags |= MONO_CFG_HAS_SPILLUP;
 548
 549         /* allow room for the vararg method args: void* and long/double */
 550         if (mono_jit_trace_calls != NULL && mono_trace_eval (m->method))
 551                 m->param_area = MAX (m->param_area, sizeof (gpointer)*8);
 552
 553         header = mono_method_get_header (m->method);
 554
 555         /*
 556          * We use the frame register also for any method that has
 557          * exception clauses. This way, when the handlers are called,
 558          * the code will reference local variables using the frame reg instead of
 559          * the stack pointer: if we had to restore the stack pointer, we'd
 560          * corrupt the method frames that are already on the stack (since
 561          * filters get called before stack unwinding happens) when the filter
 562          * code would call any method (this also applies to finally etc.).
 563          */
 564         if ((m->flags & MONO_CFG_HAS_ALLOCA) || header->num_clauses)
 565                 frame_reg = ARMREG_FP;
 566         m->frame_reg = frame_reg;
 567         if (frame_reg != ARMREG_SP) {
 568                 m->used_int_regs |= 1 << frame_reg;
 569         }
 570
 571         sig = mono_method_signature (m->method);
 572
 573         offset = 0;
 574         curinst = 0;
 575         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 576                 m->ret->opcode = OP_REGVAR;
 577                 m->ret->inst_c0 = ARMREG_R0;
 578         } else {
 579                 /* FIXME: handle long and FP values */
 580                 switch (mono_type_get_underlying_type (sig->ret)->type) {
 581                 case MONO_TYPE_VOID:
 582                         break;
 583                 default:
 584                         m->ret->opcode = OP_REGVAR;
 585                         m->ret->inst_c0 = ARMREG_R0;
 586                         break;
 587                 }
 588         }
 589         /* local vars are at a positive offset from the stack pointer */
 590         /*
 591          * also note that if the function uses alloca, we use FP
 592          * to point at the local variables.
 593          */
 594         offset = 0; /* linkage area */
 595         /* align the offset to 16 bytes: not sure this is needed here  */
 596         //offset += 8 - 1;
 597         //offset &= ~(8 - 1);
 598
 599         /* add parameter area size for called functions */
 600         offset += m->param_area;
 601         offset += 8 - 1;
 602         offset &= ~(8 - 1);
 603         if (m->flags & MONO_CFG_HAS_FPOUT)
 604                 offset += 8;
 605
 606         /* allow room to save the return value */
 607         if (mono_jit_trace_calls != NULL && mono_trace_eval (m->method))
 608                 offset += 8;
 609
 610         /* the MonoLMF structure is stored just below the stack pointer */
 611
 612         if (sig->call_convention == MONO_CALL_VARARG) {
 613                 m->sig_cookie = 0;
 614         }
 615
 616         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 617                 inst = m->ret;
 618                 offset += sizeof(gpointer) - 1;
 619                 offset &= ~(sizeof(gpointer) - 1);
 620                 inst->inst_offset = offset;
 621                 inst->opcode = OP_REGOFFSET;
 622                 inst->inst_basereg = frame_reg;
 623                 offset += sizeof(gpointer);
 624                 if (sig->call_convention == MONO_CALL_VARARG)
 625                         m->sig_cookie += sizeof (gpointer);
 626         }
 627
 628         curinst = m->locals_start;
 629         for (i = curinst; i < m->num_varinfo; ++i) {
 630                 inst = m->varinfo [i];
 631                 if ((inst->flags & MONO_INST_IS_DEAD) || inst->opcode == OP_REGVAR)
 632                         continue;
 633
 634                 /* inst->unused indicates native sized value types, this is used by the
 635                 * pinvoke wrappers when they call functions returning structure */
 636                 if (inst->unused && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
 637                         size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), &align);
 638                 else
 639                         size = mono_type_size (inst->inst_vtype, &align);
 640
 641                 offset += align - 1;
 642                 offset &= ~(align - 1);
 643                 inst->inst_offset = offset;
 644                 inst->opcode = OP_REGOFFSET;
 645                 inst->inst_basereg = frame_reg;
 646                 offset += size;
 647                 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
 648         }
 649
 650         curinst = 0;
 651         if (sig->hasthis) {
 652                 inst = m->varinfo [curinst];
 653                 if (inst->opcode != OP_REGVAR) {
 654                         inst->opcode = OP_REGOFFSET;
 655                         inst->inst_basereg = frame_reg;
 656                         offset += sizeof (gpointer) - 1;
 657                         offset &= ~(sizeof (gpointer) - 1);
 658                         inst->inst_offset = offset;
 659                         offset += sizeof (gpointer);
 660                         if (sig->call_convention == MONO_CALL_VARARG)
 661                                 m->sig_cookie += sizeof (gpointer);
 662                 }
 663                 curinst++;
 664         }
 665
 666         for (i = 0; i < sig->param_count; ++i) {
 667                 inst = m->varinfo [curinst];
 668                 if (inst->opcode != OP_REGVAR) {
 669                         inst->opcode = OP_REGOFFSET;
 670                         inst->inst_basereg = frame_reg;
 671                         size = mono_type_size (sig->params [i], &align);
 672                         offset += align - 1;
 673                         offset &= ~(align - 1);
 674                         inst->inst_offset = offset;
 675                         offset += size;
 676                         if ((sig->call_convention == MONO_CALL_VARARG) && (i < sig->sentinelpos))
 677                                 m->sig_cookie += size;
 678                 }
 679                 curinst++;
 680         }
 681
 682         /* align the offset to 8 bytes */
 683         offset += 8 - 1;
 684         offset &= ~(8 - 1);
 685
 686         /* change sign? */
 687         m->stack_offset = offset;
 688
 689 }
 690
 691 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
 692  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
 693  */
 694
 695 /*
 696  * take the arguments and generate the arch-specific
 697  * instructions to properly call the function in call.
 698  * This includes pushing, moving arguments to the right register
 699  * etc.
 700  * Issue: who does the spilling if needed, and when?
 701  */
 702 MonoCallInst*
 703 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
 704         MonoInst *arg, *in;
 705         MonoMethodSignature *sig;
 706         int i, n;
 707         CallInfo *cinfo;
 708         ArgInfo *ainfo;
 709
 710         sig = call->signature;
 711         n = sig->param_count + sig->hasthis;
 712
 713         cinfo = calculate_sizes (sig, sig->pinvoke);
 714         if (cinfo->struct_ret)
 715                 call->used_iregs |= 1 << cinfo->struct_ret;
 716
 717         for (i = 0; i < n; ++i) {
 718                 ainfo = cinfo->args + i;
 719                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 720                         MonoInst *sig_arg;
 721                         cfg->disable_aot = TRUE;
 722
 723                         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
 724                         sig_arg->inst_p0 = call->signature;
 725
 726                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
 727                         arg->inst_imm = cinfo->sig_cookie.offset;
 728                         arg->inst_left = sig_arg;
 729
 730                         /* prepend, so they get reversed */
 731                         arg->next = call->out_args;
 732                         call->out_args = arg;
 733                 }
 734                 if (is_virtual && i == 0) {
 735                         /* the argument will be attached to the call instrucion */
 736                         in = call->args [i];
 737                         call->used_iregs |= 1 << ainfo->reg;
 738                 } else {
 739                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
 740                         in = call->args [i];
 741                         arg->cil_code = in->cil_code;
 742                         arg->inst_left = in;
 743                         arg->inst_right = (MonoInst*)call;
 744                         arg->type = in->type;
 745                         /* prepend, we'll need to reverse them later */
 746                         arg->next = call->out_args;
 747                         call->out_args = arg;
 748                         if (ainfo->regtype == RegTypeGeneral) {
 749                                 arg->unused = ainfo->reg;
 750                                 call->used_iregs |= 1 << ainfo->reg;
 751                                 if (arg->type == STACK_I8)
 752                                         call->used_iregs |= 1 << (ainfo->reg + 1);
 753                                 if (arg->type == STACK_R8) {
 754                                         if (ainfo->size == 4) {
 755                                                 arg->opcode = OP_OUTARG_R4;
 756                                         } else {
 757                                                 call->used_iregs |= 1 << (ainfo->reg + 1);
 758                                         }
 759                                         cfg->flags |= MONO_CFG_HAS_FPOUT;
 760                                 }
 761                         } else if (ainfo->regtype == RegTypeStructByAddr) {
 762                                 /* FIXME: where si the data allocated? */
 763                                 arg->unused = ainfo->reg;
 764                                 call->used_iregs |= 1 << ainfo->reg;
 765                                 g_assert_not_reached ();
 766                         } else if (ainfo->regtype == RegTypeStructByVal) {
 767                                 int cur_reg;
 768                                 /* mark the used regs */
 769                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
 770                                         call->used_iregs |= 1 << (ainfo->reg + cur_reg);
 771                                 }
 772                                 arg->opcode = OP_OUTARG_VT;
 773                                 /* vtsize and offset have just 12 bits of encoding in number of words */
 774                                 g_assert (((ainfo->vtsize | (ainfo->offset / 4)) & 0xfffff000) == 0);
 775                                 arg->unused = ainfo->reg | (ainfo->size << 4) | (ainfo->vtsize << 8) | ((ainfo->offset / 4) << 20);
 776                         } else if (ainfo->regtype == RegTypeBase) {
 777                                 arg->opcode = OP_OUTARG_MEMBASE;
 778                                 arg->unused = (ainfo->offset << 8) | ainfo->size;
 779                         } else if (ainfo->regtype == RegTypeFP) {
 780                                 arg->unused = ainfo->reg;
 781                                 /* FPA args are passed in int regs */
 782                                 call->used_iregs |= 1 << ainfo->reg;
 783                                 if (ainfo->size == 8) {
 784                                         arg->opcode = OP_OUTARG_R8;
 785                                         call->used_iregs |= 1 << (ainfo->reg + 1);
 786                                 } else {
 787                                         arg->opcode = OP_OUTARG_R4;
 788                                 }
 789                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
 790                         } else {
 791                                 g_assert_not_reached ();
 792                         }
 793                 }
 794         }
 795         /*
 796          * Reverse the call->out_args list.
 797          */
 798         {
 799                 MonoInst *prev = NULL, *list = call->out_args, *next;
 800                 while (list) {
 801                         next = list->next;
 802                         list->next = prev;
 803                         prev = list;
 804                         list = next;
 805                 }
 806                 call->out_args = prev;
 807         }
 808         call->stack_usage = cinfo->stack_usage;
 809         cfg->param_area = MAX (cfg->param_area, cinfo->stack_usage);
 810         cfg->flags |= MONO_CFG_HAS_CALLS;
 811         /*
 812          * should set more info in call, such as the stack space
 813          * used by the args that needs to be added back to esp
 814          */
 815
 816         g_free (cinfo);
 817         return call;
 818 }
 819
 820 /*
 821  * Allow tracing to work with this interface (with an optional argument)
 822  */
 823
 824 void*
 825 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
 826 {
 827         guchar *code = p;
 828
 829         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
 830         ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
 831         code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
 832         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
 833         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_R2);
 834         return code;
 835 }
 836
 837 enum {
 838         SAVE_NONE,
 839         SAVE_STRUCT,
 840         SAVE_ONE,
 841         SAVE_TWO,
 842         SAVE_FP
 843 };
 844
 845 void*
 846 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
 847 {
 848         guchar *code = p;
 849         int save_mode = SAVE_NONE;
 850         int offset;
 851         MonoMethod *method = cfg->method;
 852         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
 853         int save_offset = cfg->param_area;
 854         save_offset += 7;
 855         save_offset &= ~7;
 856
 857         offset = code - cfg->native_code;
 858         /* we need about 16 instructions */
 859         if (offset > (cfg->code_size - 16 * 4)) {
 860                 cfg->code_size *= 2;
 861                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
 862                 code = cfg->native_code + offset;
 863         }
 864 handle_enum:
 865         switch (rtype) {
 866         case MONO_TYPE_VOID:
 867                 /* special case string .ctor icall */
 868                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
 869                         save_mode = SAVE_ONE;
 870                 else
 871                         save_mode = SAVE_NONE;
 872                 break;
 873         case MONO_TYPE_I8:
 874         case MONO_TYPE_U8:
 875                 save_mode = SAVE_TWO;
 876                 break;
 877         case MONO_TYPE_R4:
 878         case MONO_TYPE_R8:
 879                 save_mode = SAVE_FP;
 880                 break;
 881         case MONO_TYPE_VALUETYPE:
 882                 save_mode = SAVE_STRUCT;
 883                 break;
 884         default:
 885                 save_mode = SAVE_ONE;
 886                 break;
 887         }
 888
 889         switch (save_mode) {
 890         case SAVE_TWO:
 891                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
 892                 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
 893                 if (enable_arguments) {
 894                         ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
 895                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
 896                 }
 897                 break;
 898         case SAVE_ONE:
 899                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
 900                 if (enable_arguments) {
 901                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
 902                 }
 903                 break;
 904         case SAVE_FP:
 905                 /* FIXME: what reg?  */
 906                 if (enable_arguments) {
 907                         /* FIXME: what reg?  */
 908                 }
 909                 break;
 910         case SAVE_STRUCT:
 911                 if (enable_arguments) {
 912                         /* FIXME: get the actual address  */
 913                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
 914                 }
 915                 break;
 916         case SAVE_NONE:
 917         default:
 918                 break;
 919         }
 920
 921         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
 922         code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
 923         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
 924         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 925
 926         switch (save_mode) {
 927         case SAVE_TWO:
 928                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
 929                 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
 930                 break;
 931         case SAVE_ONE:
 932                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
 933                 break;
 934         case SAVE_FP:
 935                 /* FIXME */
 936                 break;
 937         case SAVE_NONE:
 938         default:
 939                 break;
 940         }
 941
 942         return code;
 943 }
 944
 945 /*
 946  * The immediate field for cond branches is big enough for all reasonable methods
 947  */
 948 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
 949 if (ins->flags & MONO_INST_BRLABEL) { \
 950         if (0 && ins->inst_i0->inst_c0) { \
 951                 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_i0->inst_c0) & 0xffffff);    \
 952         } else { \
 953                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
 954                 ARM_B_COND (code, (condcode), 0);       \
 955         } \
 956 } else { \
 957         if (0 && ins->inst_true_bb->native_offset) { \
 958                 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
 959         } else { \
 960                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
 961                 ARM_B_COND (code, (condcode), 0);       \
 962         } \
 963 }
 964
 965 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
 966
 967 /* emit an exception if condition is fail
 968  *
 969  * We assign the extra code used to throw the implicit exceptions
 970  * to cfg->bb_exit as far as the big branch handling is concerned
 971  */
 972 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name)            \
 973         do {                                                        \
 974                 mono_add_patch_info (cfg, code - cfg->native_code,   \
 975                                     MONO_PATCH_INFO_EXC, exc_name);  \
 976                 ARM_BL_COND (code, (condcode), 0);      \
 977         } while (0);
 978
 979 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
 980
 981 static void
 982 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
 983 {
 984         MonoInst *ins, *last_ins = NULL;
 985         ins = bb->code;
 986
 987         while (ins) {
 988
 989                 switch (ins->opcode) {
 990                 case OP_MUL_IMM:
 991                         /* remove unnecessary multiplication with 1 */
 992                         if (ins->inst_imm == 1) {
 993                                 if (ins->dreg != ins->sreg1) {
 994                                         ins->opcode = OP_MOVE;
 995                                 } else {
 996                                         last_ins->next = ins->next;
 997                                         ins = ins->next;
 998                                         continue;
 999                                 }
1000                         } else {
1001                                 int power2 = mono_is_power_of_two (ins->inst_imm);
1002                                 if (power2 > 0) {
1003                                         ins->opcode = OP_SHL_IMM;
1004                                         ins->inst_imm = power2;
1005                                 }
1006                         }
1007                         break;
1008                 case OP_LOAD_MEMBASE:
1009                 case OP_LOADI4_MEMBASE:
1010                         /*
1011                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1012                          * OP_LOAD_MEMBASE offset(basereg), reg
1013                          */
1014                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1015                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1016                             ins->inst_basereg == last_ins->inst_destbasereg &&
1017                             ins->inst_offset == last_ins->inst_offset) {
1018                                 if (ins->dreg == last_ins->sreg1) {
1019                                         last_ins->next = ins->next;
1020                                         ins = ins->next;
1021                                         continue;
1022                                 } else {
1023                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1024                                         ins->opcode = OP_MOVE;
1025                                         ins->sreg1 = last_ins->sreg1;
1026                                 }
1027
1028                         /*
1029                          * Note: reg1 must be different from the basereg in the second load
1030                          * OP_LOAD_MEMBASE offset(basereg), reg1
1031                          * OP_LOAD_MEMBASE offset(basereg), reg2
1032                          * -->
1033                          * OP_LOAD_MEMBASE offset(basereg), reg1
1034                          * OP_MOVE reg1, reg2
1035                          */
1036                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1037                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1038                               ins->inst_basereg != last_ins->dreg &&
1039                               ins->inst_basereg == last_ins->inst_basereg &&
1040                               ins->inst_offset == last_ins->inst_offset) {
1041
1042                                 if (ins->dreg == last_ins->dreg) {
1043                                         last_ins->next = ins->next;
1044                                         ins = ins->next;
1045                                         continue;
1046                                 } else {
1047                                         ins->opcode = OP_MOVE;
1048                                         ins->sreg1 = last_ins->dreg;
1049                                 }
1050
1051                                 //g_assert_not_reached ();
1052
1053 #if 0
1054                         /*
1055                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1056                          * OP_LOAD_MEMBASE offset(basereg), reg
1057                          * -->
1058                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1059                          * OP_ICONST reg, imm
1060                          */
1061                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1062                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1063                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1064                                    ins->inst_offset == last_ins->inst_offset) {
1065                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1066                                 ins->opcode = OP_ICONST;
1067                                 ins->inst_c0 = last_ins->inst_imm;
1068                                 g_assert_not_reached (); // check this rule
1069 #endif
1070                         }
1071                         break;
1072                 case OP_LOADU1_MEMBASE:
1073                 case OP_LOADI1_MEMBASE:
1074                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1075                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1076                                         ins->inst_offset == last_ins->inst_offset) {
1077                                 if (ins->dreg == last_ins->sreg1) {
1078                                         last_ins->next = ins->next;
1079                                         ins = ins->next;
1080                                         continue;
1081                                 } else {
1082                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1083                                         ins->opcode = OP_MOVE;
1084                                         ins->sreg1 = last_ins->sreg1;
1085                                 }
1086                         }
1087                         break;
1088                 case OP_LOADU2_MEMBASE:
1089                 case OP_LOADI2_MEMBASE:
1090                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1091                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1092                                         ins->inst_offset == last_ins->inst_offset) {
1093                                 if (ins->dreg == last_ins->sreg1) {
1094                                         last_ins->next = ins->next;
1095                                         ins = ins->next;
1096                                         continue;
1097                                 } else {
1098                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1099                                         ins->opcode = OP_MOVE;
1100                                         ins->sreg1 = last_ins->sreg1;
1101                                 }
1102                         }
1103                         break;
1104                 case CEE_CONV_I4:
1105                 case CEE_CONV_U4:
1106                 case OP_MOVE:
1107                 case OP_SETREG:
1108                         ins->opcode = OP_MOVE;
1109                         /*
1110                          * OP_MOVE reg, reg
1111                          */
1112                         if (ins->dreg == ins->sreg1) {
1113                                 if (last_ins)
1114                                         last_ins->next = ins->next;
1115                                 ins = ins->next;
1116                                 continue;
1117                         }
1118                         /*
1119                          * OP_MOVE sreg, dreg
1120                          * OP_MOVE dreg, sreg
1121                          */
1122                         if (last_ins && last_ins->opcode == OP_MOVE &&
1123                             ins->sreg1 == last_ins->dreg &&
1124                             ins->dreg == last_ins->sreg1) {
1125                                 last_ins->next = ins->next;
1126                                 ins = ins->next;
1127                                 continue;
1128                         }
1129                         break;
1130                 }
1131                 last_ins = ins;
1132                 ins = ins->next;
1133         }
1134         bb->last_ins = last_ins;
1135 }
1136
1137 /*
1138  * the branch_cc_table should maintain the order of these
1139  * opcodes.
1140 case CEE_BEQ:
1141 case CEE_BGE:
1142 case CEE_BGT:
1143 case CEE_BLE:
1144 case CEE_BLT:
1145 case CEE_BNE_UN:
1146 case CEE_BGE_UN:
1147 case CEE_BGT_UN:
1148 case CEE_BLE_UN:
1149 case CEE_BLT_UN:
1150  */
1151 static const guchar
1152 branch_cc_table [] = {
1153         ARMCOND_EQ,
1154         ARMCOND_GE,
1155         ARMCOND_GT,
1156         ARMCOND_LE,
1157         ARMCOND_LT,
1158
1159         ARMCOND_NE,
1160         ARMCOND_HS,
1161         ARMCOND_HI,
1162         ARMCOND_LS,
1163         ARMCOND_LO
1164 };
1165
1166
1167 static void
1168 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *to_insert)
1169 {
1170         if (ins == NULL) {
1171                 ins = bb->code;
1172                 bb->code = to_insert;
1173                 to_insert->next = ins;
1174         } else {
1175                 to_insert->next = ins->next;
1176                 ins->next = to_insert;
1177         }
1178 }
1179
1180 #define NEW_INS(cfg,dest,op) do {       \
1181                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1182                 (dest)->opcode = (op);  \
1183                 insert_after_ins (bb, last_ins, (dest)); \
1184         } while (0)
1185
1186 static int
1187 map_to_reg_reg_op (int op)
1188 {
1189         switch (op) {
1190         case OP_ADD_IMM:
1191                 return CEE_ADD;
1192         case OP_SUB_IMM:
1193                 return CEE_SUB;
1194         case OP_AND_IMM:
1195                 return CEE_AND;
1196         case OP_COMPARE_IMM:
1197                 return OP_COMPARE;
1198         case OP_ADDCC_IMM:
1199                 return OP_ADDCC;
1200         case OP_ADC_IMM:
1201                 return OP_ADC;
1202         case OP_SUBCC_IMM:
1203                 return OP_SUBCC;
1204         case OP_SBB_IMM:
1205                 return OP_SBB;
1206         case OP_OR_IMM:
1207                 return CEE_OR;
1208         case OP_XOR_IMM:
1209                 return CEE_XOR;
1210         case OP_LOAD_MEMBASE:
1211                 return OP_LOAD_MEMINDEX;
1212         case OP_LOADI4_MEMBASE:
1213                 return OP_LOADI4_MEMINDEX;
1214         case OP_LOADU4_MEMBASE:
1215                 return OP_LOADU4_MEMINDEX;
1216         case OP_LOADU1_MEMBASE:
1217                 return OP_LOADU1_MEMINDEX;
1218         case OP_LOADI2_MEMBASE:
1219                 return OP_LOADI2_MEMINDEX;
1220         case OP_LOADU2_MEMBASE:
1221                 return OP_LOADU2_MEMINDEX;
1222         case OP_LOADI1_MEMBASE:
1223                 return OP_LOADI1_MEMINDEX;
1224         case OP_STOREI1_MEMBASE_REG:
1225                 return OP_STOREI1_MEMINDEX;
1226         case OP_STOREI2_MEMBASE_REG:
1227                 return OP_STOREI2_MEMINDEX;
1228         case OP_STOREI4_MEMBASE_REG:
1229                 return OP_STOREI4_MEMINDEX;
1230         case OP_STORE_MEMBASE_REG:
1231                 return OP_STORE_MEMINDEX;
1232         case OP_STORER4_MEMBASE_REG:
1233                 return OP_STORER4_MEMINDEX;
1234         case OP_STORER8_MEMBASE_REG:
1235                 return OP_STORER8_MEMINDEX;
1236         case OP_STORE_MEMBASE_IMM:
1237                 return OP_STORE_MEMBASE_REG;
1238         case OP_STOREI1_MEMBASE_IMM:
1239                 return OP_STOREI1_MEMBASE_REG;
1240         case OP_STOREI2_MEMBASE_IMM:
1241                 return OP_STOREI2_MEMBASE_REG;
1242         case OP_STOREI4_MEMBASE_IMM:
1243                 return OP_STOREI4_MEMBASE_REG;
1244         }
1245         g_assert_not_reached ();
1246 }
1247
1248 /*
1249  * Remove from the instruction list the instructions that can't be
1250  * represented with very simple instructions with no register
1251  * requirements.
1252  */
1253 static void
1254 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1255 {
1256         MonoInst *ins, *next, *temp, *last_ins = NULL;
1257         int rot_amount, imm8, low_imm;
1258
1259         /* setup the virtual reg allocator */
1260         if (bb->max_ireg > cfg->rs->next_vireg)
1261                 cfg->rs->next_vireg = bb->max_ireg;
1262
1263         ins = bb->code;
1264         while (ins) {
1265 loop_start:
1266                 switch (ins->opcode) {
1267                 case OP_ADD_IMM:
1268                 case OP_SUB_IMM:
1269                 case OP_AND_IMM:
1270                 case OP_COMPARE_IMM:
1271                 case OP_ADDCC_IMM:
1272                 case OP_ADC_IMM:
1273                 case OP_SUBCC_IMM:
1274                 case OP_SBB_IMM:
1275                 case OP_OR_IMM:
1276                 case OP_XOR_IMM:
1277                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
1278                                 NEW_INS (cfg, temp, OP_ICONST);
1279                                 temp->inst_c0 = ins->inst_imm;
1280                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1281                                 ins->sreg2 = temp->dreg;
1282                                 ins->opcode = map_to_reg_reg_op (ins->opcode);
1283                         }
1284                         break;
1285                 case OP_MUL_IMM:
1286                         if (ins->inst_imm == 1) {
1287                                 ins->opcode = OP_MOVE;
1288                                 break;
1289                         }
1290                         if (ins->inst_imm == 0) {
1291                                 ins->opcode = OP_ICONST;
1292                                 ins->inst_c0 = 0;
1293                                 break;
1294                         }
1295                         imm8 = mono_is_power_of_two (ins->inst_imm);
1296                         if (imm8 > 0) {
1297                                 ins->opcode = OP_SHL_IMM;
1298                                 ins->inst_imm = imm8;
1299                                 break;
1300                         }
1301                         NEW_INS (cfg, temp, OP_ICONST);
1302                         temp->inst_c0 = ins->inst_imm;
1303                         temp->dreg = mono_regstate_next_int (cfg->rs);
1304                         ins->sreg2 = temp->dreg;
1305                         ins->opcode = CEE_MUL;
1306                         break;
1307                 case OP_LOAD_MEMBASE:
1308                 case OP_LOADI4_MEMBASE:
1309                 case OP_LOADU4_MEMBASE:
1310                 case OP_LOADU1_MEMBASE:
1311                         /* we can do two things: load the immed in a register
1312                          * and use an indexed load, or see if the immed can be
1313                          * represented as an ad_imm + a load with a smaller offset
1314                          * that fits. We just do the first for now, optimize later.
1315                          */
1316                         if (arm_is_imm12 (ins->inst_offset))
1317                                 break;
1318                         NEW_INS (cfg, temp, OP_ICONST);
1319                         temp->inst_c0 = ins->inst_offset;
1320                         temp->dreg = mono_regstate_next_int (cfg->rs);
1321                         ins->sreg2 = temp->dreg;
1322                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1323                         break;
1324                 case OP_LOADI2_MEMBASE:
1325                 case OP_LOADU2_MEMBASE:
1326                 case OP_LOADI1_MEMBASE:
1327                         if (arm_is_imm8 (ins->inst_offset))
1328                                 break;
1329                         NEW_INS (cfg, temp, OP_ICONST);
1330                         temp->inst_c0 = ins->inst_offset;
1331                         temp->dreg = mono_regstate_next_int (cfg->rs);
1332                         ins->sreg2 = temp->dreg;
1333                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1334                         break;
1335                 case OP_LOADR4_MEMBASE:
1336                 case OP_LOADR8_MEMBASE:
1337                         if (arm_is_fpimm8 (ins->inst_offset))
1338                                 break;
1339                         low_imm = ins->inst_offset & 0x1ff;
1340                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
1341                                 NEW_INS (cfg, temp, OP_ADD_IMM);
1342                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
1343                                 temp->sreg1 = ins->inst_basereg;
1344                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1345                                 ins->inst_basereg = temp->dreg;
1346                                 ins->inst_offset = low_imm;
1347                                 break;
1348                         }
1349                         /* FPA doesn't have indexed load instructions */
1350                         g_assert_not_reached ();
1351                         break;
1352                 case OP_STORE_MEMBASE_REG:
1353                 case OP_STOREI4_MEMBASE_REG:
1354                 case OP_STOREI1_MEMBASE_REG:
1355                         if (arm_is_imm12 (ins->inst_offset))
1356                                 break;
1357                         NEW_INS (cfg, temp, OP_ICONST);
1358                         temp->inst_c0 = ins->inst_offset;
1359                         temp->dreg = mono_regstate_next_int (cfg->rs);
1360                         ins->sreg2 = temp->dreg;
1361                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1362                         break;
1363                 case OP_STOREI2_MEMBASE_REG:
1364                         if (arm_is_imm8 (ins->inst_offset))
1365                                 break;
1366                         NEW_INS (cfg, temp, OP_ICONST);
1367                         temp->inst_c0 = ins->inst_offset;
1368                         temp->dreg = mono_regstate_next_int (cfg->rs);
1369                         ins->sreg2 = temp->dreg;
1370                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1371                         break;
1372                 case OP_STORER4_MEMBASE_REG:
1373                 case OP_STORER8_MEMBASE_REG:
1374                         if (arm_is_fpimm8 (ins->inst_offset))
1375                                 break;
1376                         low_imm = ins->inst_offset & 0x1ff;
1377                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
1378                                 NEW_INS (cfg, temp, OP_ADD_IMM);
1379                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
1380                                 temp->sreg1 = ins->inst_destbasereg;
1381                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1382                                 ins->inst_destbasereg = temp->dreg;
1383                                 ins->inst_offset = low_imm;
1384                                 break;
1385                         }
1386                         /*g_print ("fail with: %d (%d, %d)\n", ins->inst_offset, ins->inst_offset & ~0x1ff, low_imm);*/
1387                         /* FPA doesn't have indexed store instructions */
1388                         g_assert_not_reached ();
1389                         break;
1390                 case OP_STORE_MEMBASE_IMM:
1391                 case OP_STOREI1_MEMBASE_IMM:
1392                 case OP_STOREI2_MEMBASE_IMM:
1393                 case OP_STOREI4_MEMBASE_IMM:
1394                         NEW_INS (cfg, temp, OP_ICONST);
1395                         temp->inst_c0 = ins->inst_imm;
1396                         temp->dreg = mono_regstate_next_int (cfg->rs);
1397                         ins->sreg1 = temp->dreg;
1398                         ins->opcode = map_to_reg_reg_op (ins->opcode);
1399                         last_ins = temp;
1400                         goto loop_start; /* make it handle the possibly big ins->inst_offset */
1401                 }
1402                 last_ins = ins;
1403                 ins = ins->next;
1404         }
1405         bb->last_ins = last_ins;
1406         bb->max_ireg = cfg->rs->next_vireg;
1407
1408 }
1409
1410 void
1411 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1412 {
1413         if (!bb->code)
1414                 return;
1415         mono_arch_lowering_pass (cfg, bb);
1416         mono_local_regalloc (cfg, bb);
1417 }
1418
1419 static guchar*
1420 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1421 {
1422         /* sreg is a float, dreg is an integer reg  */
1423         ARM_FIXZ (code, dreg, sreg);
1424         if (!is_signed) {
1425                 if (size == 1)
1426                         ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
1427                 else if (size == 2) {
1428                         ARM_SHL_IMM (code, dreg, dreg, 16);
1429                         ARM_SHR_IMM (code, dreg, dreg, 16);
1430                 }
1431         } else {
1432                 if (size == 1) {
1433                         ARM_SHL_IMM (code, dreg, dreg, 24);
1434                         ARM_SAR_IMM (code, dreg, dreg, 24);
1435                 } else if (size == 2) {
1436                         ARM_SHL_IMM (code, dreg, dreg, 16);
1437                         ARM_SAR_IMM (code, dreg, dreg, 16);
1438                 }
1439         }
1440         return code;
1441 }
1442
1443 typedef struct {
1444         guchar *code;
1445         const guchar *target;
1446         int absolute;
1447         int found;
1448 } PatchData;
1449
1450 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
1451
1452 static int
1453 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
1454         PatchData *pdata = (PatchData*)user_data;
1455         guchar *code = data;
1456         guint32 *thunks = data;
1457         guint32 *endthunks = (guint32*)(code + bsize);
1458         int i, count = 0;
1459         int difflow, diffhigh;
1460
1461         /* always ensure a call from pdata->code can reach to the thunks without further thunks */
1462         difflow = (char*)pdata->code - (char*)thunks;
1463         diffhigh = (char*)pdata->code - (char*)endthunks;
1464         if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
1465                 return 0;
1466
1467         /*
1468          * The thunk is composed of 3 words:
1469          * load constant from thunks [2] into ARM_IP
1470          * bx to ARM_IP
1471          * address constant
1472          * Note that the LR register is already setup
1473          */
1474         //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
1475         if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
1476                 while (thunks < endthunks) {
1477                         //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
1478                         if (thunks [2] == (guint32)pdata->target) {
1479                                 arm_patch (pdata->code, (guchar*)thunks);
1480                                 mono_arch_flush_icache (pdata->code, 4);
1481                                 pdata->found = 1;
1482                                 return 1;
1483                         } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
1484                                 /* found a free slot instead: emit thunk */
1485                                 code = (guchar*)thunks;
1486                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
1487                                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
1488                                 thunks [2] = (guint32)pdata->target;
1489                                 mono_arch_flush_icache ((guchar*)thunks, 12);
1490
1491                                 arm_patch (pdata->code, (guchar*)thunks);
1492                                 mono_arch_flush_icache (pdata->code, 4);
1493                                 pdata->found = 1;
1494                                 return 1;
1495                         }
1496                         /* skip 12 bytes, the size of the thunk */
1497                         thunks += 3;
1498                         count++;
1499                 }
1500                 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
1501         }
1502         return 0;
1503 }
1504
1505 static void
1506 handle_thunk (int absolute, guchar *code, const guchar *target) {
1507         MonoDomain *domain = mono_domain_get ();
1508         PatchData pdata;
1509
1510         pdata.code = code;
1511         pdata.target = target;
1512         pdata.absolute = absolute;
1513         pdata.found = 0;
1514
1515         mono_domain_lock (domain);
1516         mono_code_manager_foreach (domain->code_mp, search_thunk_slot, &pdata);
1517
1518         if (!pdata.found) {
1519                 /* this uses the first available slot */
1520                 pdata.found = 2;
1521                 mono_code_manager_foreach (domain->code_mp, search_thunk_slot, &pdata);
1522         }
1523         mono_domain_unlock (domain);
1524
1525         if (pdata.found != 1)
1526                 g_print ("thunk failed for %p from %p\n", target, code);
1527         g_assert (pdata.found == 1);
1528 }
1529
1530 void
1531 arm_patch (guchar *code, const guchar *target)
1532 {
1533         guint32 ins = *(guint32*)code;
1534         guint32 prim = (ins >> 25) & 7;
1535         guint32 ovf;
1536
1537         //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
1538         if (prim == 5) { /* 101b */
1539                 /* the diff starts 8 bytes from the branch opcode */
1540                 gint diff = target - code - 8;
1541                 if (diff >= 0) {
1542                         if (diff <= 33554431) {
1543                                 diff >>= 2;
1544                                 ins = (ins & 0xff000000) | diff;
1545                                 *(guint32*)code = ins;
1546                                 return;
1547                         }
1548                 } else {
1549                         /* diff between 0 and -33554432 */
1550                         if (diff >= -33554432) {
1551                                 diff >>= 2;
1552                                 ins = (ins & 0xff000000) | (diff & ~0xff000000);
1553                                 *(guint32*)code = ins;
1554                                 return;
1555                         }
1556                 }
1557
1558                 handle_thunk (TRUE, code, target);
1559                 return;
1560         }
1561
1562
1563         if ((ins & 0x0ffffff0) == 0x12fff10) {
1564                 /* branch and exchange: the address is constructed in a reg */
1565                 g_assert_not_reached ();
1566         } else {
1567                 g_assert_not_reached ();
1568         }
1569 //      g_print ("patched with 0x%08x\n", ins);
1570 }
1571
1572 /*
1573  * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
1574  * (with the rotation amount in *rot_amount. rot_amount is already adjusted
1575  * to be used with the emit macros.
1576  * Return -1 otherwise.
1577  */
1578 int
1579 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
1580 {
1581         guint32 res, i;
1582         for (i = 0; i < 31; i+= 2) {
1583                 res = (val << (32 - i)) | (val >> i);
1584                 if (res & ~0xff)
1585                         continue;
1586                 *rot_amount = i? 32 - i: 0;
1587                 return res;
1588         }
1589         return -1;
1590 }
1591
1592 /*
1593  * Emits in code a sequence of instructions that load the value 'val'
1594  * into the dreg register. Uses at most 4 instructions.
1595  */
1596 guint8*
1597 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
1598 {
1599         int imm8, rot_amount;
1600 #if 0
1601         ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
1602         /* skip the constant pool */
1603         ARM_B (code, 0);
1604         *(int*)code = val;
1605         code += 4;
1606         return code;
1607 #endif
1608         if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
1609                 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
1610         } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
1611                 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
1612         } else {
1613                 if (val & 0xFF) {
1614                         ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
1615                         if (val & 0xFF00) {
1616                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
1617                         }
1618                         if (val & 0xFF0000) {
1619                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
1620                         }
1621                         if (val & 0xFF000000) {
1622                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
1623                         }
1624                 } else if (val & 0xFF00) {
1625                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
1626                         if (val & 0xFF0000) {
1627                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
1628                         }
1629                         if (val & 0xFF000000) {
1630                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
1631                         }
1632                 } else if (val & 0xFF0000) {
1633                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
1634                         if (val & 0xFF000000) {
1635                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
1636                         }
1637                 }
1638                 //g_assert_not_reached ();
1639         }
1640         return code;
1641 }
1642
1643 void
1644 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
1645 {
1646         MonoInst *ins;
1647         MonoCallInst *call;
1648         guint offset;
1649         guint8 *code = cfg->native_code + cfg->code_len;
1650         MonoInst *last_ins = NULL;
1651         guint last_offset = 0;
1652         int max_len, cpos;
1653         int imm8, rot_amount;
1654
1655         if (cfg->opt & MONO_OPT_PEEPHOLE)
1656                 peephole_pass (cfg, bb);
1657
1658         /* we don't align basic blocks of loops on arm */
1659
1660         if (cfg->verbose_level > 2)
1661                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
1662
1663         cpos = bb->max_offset;
1664
1665         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
1666                 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
1667                 //g_assert (!mono_compile_aot);
1668                 //cpos += 6;
1669                 //if (bb->cil_code)
1670                 //      cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
1671                 /* this is not thread save, but good enough */
1672                 /* fixme: howto handle overflows? */
1673                 //x86_inc_mem (code, &cov->data [bb->dfn].count);
1674         }
1675
1676         ins = bb->code;
1677         while (ins) {
1678                 offset = code - cfg->native_code;
1679
1680                 max_len = ((guint8 *)arm_cpu_desc [ins->opcode])[MONO_INST_LEN];
1681
1682                 if (offset > (cfg->code_size - max_len - 16)) {
1683                         cfg->code_size *= 2;
1684                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
1685                         code = cfg->native_code + offset;
1686                 }
1687         //      if (ins->cil_code)
1688         //              g_print ("cil code\n");
1689                 mono_debug_record_line_number (cfg, ins, offset);
1690
1691                 switch (ins->opcode) {
1692                 case OP_TLS_GET:
1693                         g_assert_not_reached ();
1694                         break;
1695                 /*case OP_BIGMUL:
1696                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
1697                         ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
1698                         break;
1699                 case OP_BIGMUL_UN:
1700                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
1701                         ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
1702                         break;*/
1703                 case OP_STOREI1_MEMBASE_IMM:
1704                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
1705                         g_assert (arm_is_imm12 (ins->inst_offset));
1706                         ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
1707                         break;
1708                 case OP_STOREI2_MEMBASE_IMM:
1709                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
1710                         g_assert (arm_is_imm8 (ins->inst_offset));
1711                         ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
1712                         break;
1713                 case OP_STORE_MEMBASE_IMM:
1714                 case OP_STOREI4_MEMBASE_IMM:
1715                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
1716                         g_assert (arm_is_imm12 (ins->inst_offset));
1717                         ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
1718                         break;
1719                 case OP_STOREI1_MEMBASE_REG:
1720                         g_assert (arm_is_imm12 (ins->inst_offset));
1721                         ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
1722                         break;
1723                 case OP_STOREI2_MEMBASE_REG:
1724                         g_assert (arm_is_imm8 (ins->inst_offset));
1725                         ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
1726                         break;
1727                 case OP_STORE_MEMBASE_REG:
1728                 case OP_STOREI4_MEMBASE_REG:
1729                         /* this case is special, since it happens for spill code after lowering has been called */
1730                         if (arm_is_imm12 (ins->inst_offset)) {
1731                                 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
1732                         } else {
1733                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
1734                                 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
1735                         }
1736                         break;
1737                 case OP_STOREI1_MEMINDEX:
1738                         ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
1739                         break;
1740                 case OP_STOREI2_MEMINDEX:
1741                         /* note: the args are reversed in the macro */
1742                         ARM_STRH_REG_REG (code, ins->inst_destbasereg, ins->sreg1, ins->sreg2);
1743                         break;
1744                 case OP_STORE_MEMINDEX:
1745                 case OP_STOREI4_MEMINDEX:
1746                         ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
1747                         break;
1748                 case CEE_LDIND_I:
1749                 case CEE_LDIND_I4:
1750                 case CEE_LDIND_U4:
1751                         g_assert_not_reached ();
1752                         break;
1753                 case OP_LOADU4_MEM:
1754                         g_assert_not_reached ();
1755                         break;
1756                 case OP_LOAD_MEMINDEX:
1757                 case OP_LOADI4_MEMINDEX:
1758                 case OP_LOADU4_MEMINDEX:
1759                         ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1760                         break;
1761                 case OP_LOADI1_MEMINDEX:
1762                         ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1763                         break;
1764                 case OP_LOADU1_MEMINDEX:
1765                         ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1766                         break;
1767                 case OP_LOADI2_MEMINDEX:
1768                         ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1769                         break;
1770                 case OP_LOADU2_MEMINDEX:
1771                         ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
1772                         break;
1773                 case OP_LOAD_MEMBASE:
1774                 case OP_LOADI4_MEMBASE:
1775                 case OP_LOADU4_MEMBASE:
1776                         /* this case is special, since it happens for spill code after lowering has been called */
1777                         if (arm_is_imm12 (ins->inst_offset)) {
1778                                 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1779                         } else {
1780                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
1781                                 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
1782                         }
1783                         break;
1784                 case OP_LOADI1_MEMBASE:
1785                         g_assert (arm_is_imm8 (ins->inst_offset));
1786                         ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1787                         break;
1788                 case OP_LOADU1_MEMBASE:
1789                         g_assert (arm_is_imm12 (ins->inst_offset));
1790                         ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1791                         break;
1792                 case OP_LOADU2_MEMBASE:
1793                         g_assert (arm_is_imm8 (ins->inst_offset));
1794                         ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1795                         break;
1796                 case OP_LOADI2_MEMBASE:
1797                         g_assert (arm_is_imm8 (ins->inst_offset));
1798                         ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
1799                         break;
1800                 case CEE_CONV_I1:
1801                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
1802                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
1803                         break;
1804                 case CEE_CONV_I2:
1805                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
1806                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
1807                         break;
1808                 case CEE_CONV_U1:
1809                         ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
1810                         break;
1811                 case CEE_CONV_U2:
1812                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
1813                         ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
1814                         break;
1815                 case OP_COMPARE:
1816                         ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
1817                         break;
1818                 case OP_COMPARE_IMM:
1819                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1820                         g_assert (imm8 >= 0);
1821                         ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
1822                         break;
1823                 case OP_X86_TEST_NULL:
1824                         g_assert_not_reached ();
1825                         break;
1826                 case CEE_BREAK:
1827                         *(int*)code = 0xe7f001f0;
1828                         *(int*)code = 0xef9f0001;
1829                         code += 4;
1830                         //ARM_DBRK (code);
1831                         break;
1832                 case OP_ADDCC:
1833                         ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1834                         break;
1835                 case CEE_ADD:
1836                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1837                         break;
1838                 case OP_ADC:
1839                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1840                         break;
1841                 case OP_ADDCC_IMM:
1842                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1843                         g_assert (imm8 >= 0);
1844                         ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1845                         break;
1846                 case OP_ADD_IMM:
1847                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1848                         g_assert (imm8 >= 0);
1849                         ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1850                         break;
1851                 case OP_ADC_IMM:
1852                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1853                         g_assert (imm8 >= 0);
1854                         ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1855                         break;
1856                 case CEE_ADD_OVF:
1857                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1858                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1859                         break;
1860                 case CEE_ADD_OVF_UN:
1861                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1862                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1863                         break;
1864                 case CEE_SUB_OVF:
1865                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1866                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1867                         break;
1868                 case CEE_SUB_OVF_UN:
1869                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1870                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
1871                         break;
1872                 case OP_ADD_OVF_CARRY:
1873                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1874                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1875                         break;
1876                 case OP_ADD_OVF_UN_CARRY:
1877                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1878                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1879                         break;
1880                 case OP_SUB_OVF_CARRY:
1881                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1882                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
1883                         break;
1884                 case OP_SUB_OVF_UN_CARRY:
1885                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1886                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
1887                         break;
1888                 case OP_SUBCC:
1889                         ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1890                         break;
1891                 case OP_SUBCC_IMM:
1892                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1893                         g_assert (imm8 >= 0);
1894                         ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1895                         break;
1896                 case CEE_SUB:
1897                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1898                         break;
1899                 case OP_SBB:
1900                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1901                         break;
1902                 case OP_SUB_IMM:
1903                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1904                         g_assert (imm8 >= 0);
1905                         ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1906                         break;
1907                 case OP_SBB_IMM:
1908                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1909                         g_assert (imm8 >= 0);
1910                         ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1911                         break;
1912                 case OP_ARM_RSBS_IMM:
1913                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1914                         g_assert (imm8 >= 0);
1915                         ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1916                         break;
1917                 case OP_ARM_RSC_IMM:
1918                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1919                         g_assert (imm8 >= 0);
1920                         ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1921                         break;
1922                 case CEE_AND:
1923                         ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1924                         break;
1925                 case OP_AND_IMM:
1926                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1927                         g_assert (imm8 >= 0);
1928                         ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1929                         break;
1930                 case CEE_DIV:
1931                 case CEE_DIV_UN:
1932                 case OP_DIV_IMM:
1933                 case CEE_REM:
1934                 case CEE_REM_UN:
1935                 case OP_REM_IMM:
1936                         /* crappy ARM arch doesn't have a DIV instruction */
1937                         g_assert_not_reached ();
1938                 case CEE_OR:
1939                         ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1940                         break;
1941                 case OP_OR_IMM:
1942                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1943                         g_assert (imm8 >= 0);
1944                         ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1945                         break;
1946                 case CEE_XOR:
1947                         ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1948                         break;
1949                 case OP_XOR_IMM:
1950                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
1951                         g_assert (imm8 >= 0);
1952                         ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
1953                         break;
1954                 case CEE_SHL:
1955                         ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1956                         break;
1957                 case OP_SHL_IMM:
1958                         if (ins->inst_imm)
1959                                 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
1960                         break;
1961                 case CEE_SHR:
1962                         ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1963                         break;
1964                 case OP_SHR_IMM:
1965                         if (ins->inst_imm)
1966                                 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
1967                         break;
1968                 case OP_SHR_UN_IMM:
1969                         if (ins->inst_imm)
1970                                 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
1971                         break;
1972                 case CEE_SHR_UN:
1973                         ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1974                         break;
1975                 case CEE_NOT:
1976                         ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
1977                         break;
1978                 case CEE_NEG:
1979                         ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
1980                         break;
1981                 case CEE_MUL:
1982                         if (ins->dreg == ins->sreg2)
1983                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1984                         else
1985                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
1986                         break;
1987                 case OP_MUL_IMM:
1988                         g_assert_not_reached ();
1989                         break;
1990                 case CEE_MUL_OVF:
1991                         /* FIXME: handle ovf/ sreg2 != dreg */
1992                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1993                         break;
1994                 case CEE_MUL_OVF_UN:
1995                         /* FIXME: handle ovf/ sreg2 != dreg */
1996                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
1997                         break;
1998                 case OP_ICONST:
1999                 case OP_SETREGIMM:
2000                         code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
2001                         break;
2002                 case OP_AOTCONST:
2003                         g_assert_not_reached ();
2004                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2005                         break;
2006                 case CEE_CONV_I4:
2007                 case CEE_CONV_U4:
2008                 case OP_MOVE:
2009                 case OP_SETREG:
2010                         if (ins->dreg != ins->sreg1)
2011                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
2012                         break;
2013                 case OP_SETLRET: {
2014                         int saved = ins->sreg2;
2015                         if (ins->sreg2 == ARM_LSW_REG) {
2016                                 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
2017                                 saved = ARMREG_LR;
2018                         }
2019                         if (ins->sreg1 != ARM_LSW_REG)
2020                                 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
2021                         if (saved != ARM_MSW_REG)
2022                                 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
2023                         break;
2024                 }
2025                 case OP_SETFREG:
2026                 case OP_FMOVE:
2027                         ARM_MVFD (code, ins->dreg, ins->sreg1);
2028                         break;
2029                 case OP_FCONV_TO_R4:
2030                         ARM_MVFS (code, ins->dreg, ins->sreg1);
2031                         break;
2032                 case CEE_JMP:
2033                         /*
2034                          * Keep in sync with mono_arch_emit_epilog
2035                          */
2036                         g_assert (!cfg->method->save_lmf);
2037                         code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
2038                         ARM_POP_NWB (code, cfg->used_int_regs | ((1 << ARMREG_SP)) | ((1 << ARMREG_LR)));
2039                         mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2040                         ARM_B (code, 0);
2041                         break;
2042                 case OP_CHECK_THIS:
2043                         /* ensure ins->sreg1 is not NULL */
2044                         ARM_LDR_IMM (code, ARMREG_LR, ins->sreg1, 0);
2045                         break;
2046                 case OP_ARGLIST: {
2047 #if ARM_PORT
2048                         if (ppc_is_imm16 (cfg->sig_cookie + cfg->stack_usage)) {
2049                                 ppc_addi (code, ppc_r11, cfg->frame_reg, cfg->sig_cookie + cfg->stack_usage);
2050                         } else {
2051                                 ppc_load (code, ppc_r11, cfg->sig_cookie + cfg->stack_usage);
2052                                 ppc_add (code, ppc_r11, cfg->frame_reg, ppc_r11);
2053                         }
2054                         ppc_stw (code, ppc_r11, 0, ins->sreg1);
2055 #endif
2056                         break;
2057                 }
2058                 case OP_FCALL:
2059                 case OP_LCALL:
2060                 case OP_VCALL:
2061                 case OP_VOIDCALL:
2062                 case CEE_CALL:
2063                         call = (MonoCallInst*)ins;
2064                         if (ins->flags & MONO_INST_HAS_METHOD)
2065                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
2066                         else
2067                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
2068                         if (cfg->method->dynamic) {
2069                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2070                                 ARM_B (code, 0);
2071                                 *(gpointer*)code = NULL;
2072                                 code += 4;
2073                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2074                                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2075                         } else {
2076                                 ARM_BL (code, 0);
2077                         }
2078                         break;
2079                 case OP_FCALL_REG:
2080                 case OP_LCALL_REG:
2081                 case OP_VCALL_REG:
2082                 case OP_VOIDCALL_REG:
2083                 case OP_CALL_REG:
2084                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2085                         ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
2086                         break;
2087                 case OP_FCALL_MEMBASE:
2088                 case OP_LCALL_MEMBASE:
2089                 case OP_VCALL_MEMBASE:
2090                 case OP_VOIDCALL_MEMBASE:
2091                 case OP_CALL_MEMBASE:
2092                         g_assert (arm_is_imm12 (ins->inst_offset));
2093                         g_assert (ins->sreg1 != ARMREG_LR);
2094                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2095                         ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
2096                         break;
2097                 case OP_OUTARG:
2098                         g_assert_not_reached ();
2099                         break;
2100                 case OP_LOCALLOC: {
2101                         /* keep alignment */
2102                         int alloca_waste = cfg->param_area;
2103                         alloca_waste += 7;
2104                         alloca_waste &= ~7;
2105                         /* round the size to 8 bytes */
2106                         ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
2107                         ARM_BIC_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
2108                         ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
2109                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
2110                         /* memzero the area: dreg holds the size, sp is the pointer */
2111                         if (ins->flags & MONO_INST_INIT) {
2112                                 guint8 *start_loop, *branch_to_cond;
2113                                 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
2114                                 branch_to_cond = code;
2115                                 ARM_B (code, 0);
2116                                 start_loop = code;
2117                                 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
2118                                 arm_patch (branch_to_cond, code);
2119                                 /* decrement by 4 and set flags */
2120                                 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, 4);
2121                                 ARM_B_COND (code, ARMCOND_LT, 0);
2122                                 arm_patch (code - 4, start_loop);
2123                         }
2124                         ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
2125                         break;
2126                 }
2127                 case CEE_RET:
2128                         g_assert_not_reached ();
2129                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_LR);
2130                         break;
2131                 case CEE_THROW: {
2132                         if (ins->sreg1 != ARMREG_R0)
2133                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
2134                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2135                                              (gpointer)"mono_arch_throw_exception");
2136                         if (cfg->method->dynamic) {
2137                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2138                                 ARM_B (code, 0);
2139                                 *(gpointer*)code = NULL;
2140                                 code += 4;
2141                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2142                                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2143                         } else {
2144                                 ARM_BL (code, 0);
2145                         }
2146                         break;
2147                 }
2148                 case OP_RETHROW: {
2149                         if (ins->sreg1 != ARMREG_R0)
2150                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
2151                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2152                                              (gpointer)"mono_arch_rethrow_exception");
2153                         if (cfg->method->dynamic) {
2154                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2155                                 ARM_B (code, 0);
2156                                 *(gpointer*)code = NULL;
2157                                 code += 4;
2158                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2159                                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2160                         } else {
2161                                 ARM_BL (code, 0);
2162                         }
2163                         break;
2164                 }
2165                 case OP_START_HANDLER:
2166                         if (arm_is_imm12 (ins->inst_left->inst_offset)) {
2167                                 ARM_STR_IMM (code, ARMREG_LR, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
2168                         } else {
2169                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_left->inst_offset);
2170                                 ARM_STR_REG_REG (code, ARMREG_LR, ins->inst_left->inst_basereg, ARMREG_IP);
2171                         }
2172                         break;
2173                 case OP_ENDFILTER:
2174                         if (ins->sreg1 != ARMREG_R0)
2175                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
2176                         if (arm_is_imm12 (ins->inst_left->inst_offset)) {
2177                                 ARM_LDR_IMM (code, ARMREG_IP, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
2178                         } else {
2179                                 g_assert (ARMREG_IP != ins->inst_left->inst_basereg);
2180                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_left->inst_offset);
2181                                 ARM_LDR_REG_REG (code, ARMREG_IP, ins->inst_left->inst_basereg, ARMREG_IP);
2182                         }
2183                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2184                         break;
2185                 case CEE_ENDFINALLY:
2186                         if (arm_is_imm12 (ins->inst_left->inst_offset)) {
2187                                 ARM_LDR_IMM (code, ARMREG_IP, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
2188                         } else {
2189                                 g_assert (ARMREG_IP != ins->inst_left->inst_basereg);
2190                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_left->inst_offset);
2191                                 ARM_LDR_REG_REG (code, ARMREG_IP, ins->inst_left->inst_basereg, ARMREG_IP);
2192                         }
2193                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2194                         break;
2195                 case OP_CALL_HANDLER:
2196                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2197                         ARM_BL (code, 0);
2198                         break;
2199                 case OP_LABEL:
2200                         ins->inst_c0 = code - cfg->native_code;
2201                         break;
2202                 case CEE_BR:
2203                         if (ins->flags & MONO_INST_BRLABEL) {
2204                                 /*if (ins->inst_i0->inst_c0) {
2205                                         ARM_B (code, 0);
2206                                         //x86_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
2207                                 } else*/ {
2208                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2209                                         ARM_B (code, 0);
2210                                 }
2211                         } else {
2212                                 /*if (ins->inst_target_bb->native_offset) {
2213                                         ARM_B (code, 0);
2214                                         //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2215                                 } else*/ {
2216                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2217                                         ARM_B (code, 0);
2218                                 }
2219                         }
2220                         break;
2221                 case OP_BR_REG:
2222                         ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
2223                         break;
2224                 case CEE_SWITCH:
2225                         /*
2226                          * In the normal case we have:
2227                          *      ldr pc, [pc, ins->sreg1 << 2]
2228                          *      nop
2229                          * If aot, we have:
2230                          *      ldr lr, [pc, ins->sreg1 << 2]
2231                          *      add pc, pc, lr
2232                          * After follows the data.
2233                          * FIXME: add aot support.
2234                          */
2235                         max_len += 4 * GPOINTER_TO_INT (ins->klass);
2236                         if (offset > (cfg->code_size - max_len - 16)) {
2237                                 cfg->code_size += max_len;
2238                                 cfg->code_size *= 2;
2239                                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2240                                 code = cfg->native_code + offset;
2241                         }
2242                         ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
2243                         ARM_NOP (code);
2244                         code += 4 * GPOINTER_TO_INT (ins->klass);
2245                         break;
2246                 case OP_CEQ:
2247                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2248                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
2249                         break;
2250                 case OP_CLT:
2251                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2252                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
2253                         break;
2254                 case OP_CLT_UN:
2255                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2256                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
2257                         break;
2258                 case OP_CGT:
2259                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2260                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
2261                         break;
2262                 case OP_CGT_UN:
2263                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2264                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
2265                         break;
2266                 case OP_COND_EXC_EQ:
2267                 case OP_COND_EXC_NE_UN:
2268                 case OP_COND_EXC_LT:
2269                 case OP_COND_EXC_LT_UN:
2270                 case OP_COND_EXC_GT:
2271                 case OP_COND_EXC_GT_UN:
2272                 case OP_COND_EXC_GE:
2273                 case OP_COND_EXC_GE_UN:
2274                 case OP_COND_EXC_LE:
2275                 case OP_COND_EXC_LE_UN:
2276                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
2277                         break;
2278                 case OP_COND_EXC_C:
2279                 case OP_COND_EXC_OV:
2280                 case OP_COND_EXC_NC:
2281                 case OP_COND_EXC_NO:
2282                         g_assert_not_reached ();
2283                         break;
2284                 case CEE_BEQ:
2285                 case CEE_BNE_UN:
2286                 case CEE_BLT:
2287                 case CEE_BLT_UN:
2288                 case CEE_BGT:
2289                 case CEE_BGT_UN:
2290                 case CEE_BGE:
2291                 case CEE_BGE_UN:
2292                 case CEE_BLE:
2293                 case CEE_BLE_UN:
2294                         EMIT_COND_BRANCH (ins, ins->opcode - CEE_BEQ);
2295                         break;
2296
2297                 /* floating point opcodes */
2298                 case OP_R8CONST:
2299                         /* FIXME: we can optimize the imm load by dealing with part of
2300                          * the displacement in LDFD (aligning to 512).
2301                          */
2302                         code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
2303                         ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
2304                         break;
2305                 case OP_R4CONST:
2306                         code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
2307                         ARM_LDFS (code, ins->dreg, ARMREG_LR, 0);
2308                         break;
2309                 case OP_STORER8_MEMBASE_REG:
2310                         g_assert (arm_is_fpimm8 (ins->inst_offset));
2311                         ARM_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
2312                         break;
2313                 case OP_LOADR8_MEMBASE:
2314                         g_assert (arm_is_fpimm8 (ins->inst_offset));
2315                         ARM_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2316                         break;
2317                 case OP_STORER4_MEMBASE_REG:
2318                         g_assert (arm_is_fpimm8 (ins->inst_offset));
2319                         ARM_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
2320                         break;
2321                 case OP_LOADR4_MEMBASE:
2322                         g_assert (arm_is_fpimm8 (ins->inst_offset));
2323                         ARM_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2324                         break;
2325                 case CEE_CONV_R_UN: {
2326                         int tmpreg;
2327                         tmpreg = ins->dreg == 0? 1: 0;
2328                         ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
2329                         ARM_FLTD (code, ins->dreg, ins->sreg1);
2330                         ARM_B_COND (code, ARMCOND_GE, 8);
2331                         /* save the temp register */
2332                         ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
2333                         ARM_STFD (code, tmpreg, ARMREG_SP, 0);
2334                         ARM_LDFD (code, tmpreg, ARMREG_PC, 4);
2335                         ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
2336                         ARM_LDFD (code, tmpreg, ARMREG_SP, 0);
2337                         ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
2338                         /* skip the constant pool */
2339                         ARM_B (code, 4);
2340                         *(int*)code = 0x41f00000;
2341                         code += 4;
2342                         *(int*)code = 0;
2343                         code += 4;
2344                         /* FIXME: adjust:
2345                          * ldfltd  ftemp, [pc, #8] 0x41f00000 0x00000000
2346                          * adfltd  fdest, fdest, ftemp
2347                          */
2348                         break;
2349                 }
2350                 case CEE_CONV_R4:
2351                         ARM_FLTS (code, ins->dreg, ins->sreg1);
2352                         break;
2353                 case CEE_CONV_R8:
2354                         ARM_FLTD (code, ins->dreg, ins->sreg1);
2355                         break;
2356                 case OP_X86_FP_LOAD_I8:
2357                         g_assert_not_reached ();
2358                         /*x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);*/
2359                         break;
2360                 case OP_X86_FP_LOAD_I4:
2361                         g_assert_not_reached ();
2362                         /*x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);*/
2363                         break;
2364                 case OP_FCONV_TO_I1:
2365                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
2366                         break;
2367                 case OP_FCONV_TO_U1:
2368                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
2369                         break;
2370                 case OP_FCONV_TO_I2:
2371                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
2372                         break;
2373                 case OP_FCONV_TO_U2:
2374                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
2375                         break;
2376                 case OP_FCONV_TO_I4:
2377                 case OP_FCONV_TO_I:
2378                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
2379                         break;
2380                 case OP_FCONV_TO_U4:
2381                 case OP_FCONV_TO_U:
2382                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
2383                         break;
2384                 case OP_FCONV_TO_I8:
2385                 case OP_FCONV_TO_U8:
2386                         g_assert_not_reached ();
2387                         /* Implemented as helper calls */
2388                         break;
2389                 case OP_LCONV_TO_R_UN:
2390                         g_assert_not_reached ();
2391                         /* Implemented as helper calls */
2392                         break;
2393                 case OP_LCONV_TO_OVF_I: {
2394 #if ARM_PORT
2395                         guint32 *negative_branch, *msword_positive_branch, *msword_negative_branch, *ovf_ex_target;
2396                         // Check if its negative
2397                         ppc_cmpi (code, 0, 0, ins->sreg1, 0);
2398                         negative_branch = code;
2399                         ppc_bc (code, PPC_BR_TRUE, PPC_BR_LT, 0);
2400                         // Its positive msword == 0
2401                         ppc_cmpi (code, 0, 0, ins->sreg2, 0);
2402                         msword_positive_branch = code;
2403                         ppc_bc (code, PPC_BR_TRUE, PPC_BR_EQ, 0);
2404
2405                         ovf_ex_target = code;
2406                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_ALWAYS, 0, "OverflowException");
2407                         // Negative
2408                         ppc_patch (negative_branch, code);
2409                         ppc_cmpi (code, 0, 0, ins->sreg2, -1);
2410                         msword_negative_branch = code;
2411                         ppc_bc (code, PPC_BR_FALSE, PPC_BR_EQ, 0);
2412                         ppc_patch (msword_negative_branch, ovf_ex_target);
2413
2414                         ppc_patch (msword_positive_branch, code);
2415                         if (ins->dreg != ins->sreg1)
2416                                 ppc_mr (code, ins->dreg, ins->sreg1);
2417 #endif
2418                         if (ins->dreg != ins->sreg1)
2419                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
2420                         break;
2421                 }
2422                 case OP_FADD:
2423                         ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2424                         break;
2425                 case OP_FSUB:
2426                         ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2427                         break;
2428                 case OP_FMUL:
2429                         ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2430                         break;
2431                 case OP_FDIV:
2432                         ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
2433                         break;
2434                 case OP_FNEG:
2435                         ARM_MNFD (code, ins->dreg, ins->sreg1);
2436                         break;
2437                 case OP_FREM:
2438                         /* emulated */
2439                         g_assert_not_reached ();
2440                         break;
2441                 case OP_FCOMPARE:
2442                         /* each fp compare op needs to do its own */
2443                         g_assert_not_reached ();
2444                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2445                         break;
2446                 case OP_FCEQ:
2447                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2448                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2449                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
2450                         break;
2451                 case OP_FCLT:
2452                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2453                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2454                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2455                         break;
2456                 case OP_FCLT_UN:
2457                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2458                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2459                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2460                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
2461                         break;
2462                 case OP_FCGT:
2463                         /* swapped */
2464                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2465                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2466                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2467                         break;
2468                 case OP_FCGT_UN:
2469                         /* swapped */
2470                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2471                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
2472                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
2473                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
2474                         break;
2475                 /* ARM FPA flags table:
2476                  * N        Less than               ARMCOND_MI
2477                  * Z        Equal                   ARMCOND_EQ
2478                  * C        Greater Than or Equal   ARMCOND_CS
2479                  * V        Unordered               ARMCOND_VS
2480                  */
2481                 case OP_FBEQ:
2482                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2483                         EMIT_COND_BRANCH (ins, CEE_BEQ - CEE_BEQ);
2484                         break;
2485                 case OP_FBNE_UN:
2486                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2487                         EMIT_COND_BRANCH (ins, CEE_BNE_UN - CEE_BEQ);
2488                         break;
2489                 case OP_FBLT:
2490                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2491                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
2492                         break;
2493                 case OP_FBLT_UN:
2494                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2495                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2496                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
2497                         break;
2498                 case OP_FBGT:
2499                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2500                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set, swapped args */
2501                         break;
2502                 case OP_FBGT_UN:
2503                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2504                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2505                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set, swapped args */
2506                         break;
2507                 case OP_FBGE:
2508                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2509                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
2510                         break;
2511                 case OP_FBGE_UN:
2512                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
2513                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2514                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
2515                         break;
2516                 case OP_FBLE:
2517                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2518                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS); /* swapped */
2519                         break;
2520                 case OP_FBLE_UN:
2521                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
2522                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
2523                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS); /* swapped */
2524                         break;
2525                 case CEE_CKFINITE: {
2526                         /*ppc_stfd (code, ins->sreg1, -8, ppc_sp);
2527                         ppc_lwz (code, ppc_r11, -8, ppc_sp);
2528                         ppc_rlwinm (code, ppc_r11, ppc_r11, 0, 1, 31);
2529                         ppc_addis (code, ppc_r11, ppc_r11, -32752);
2530                         ppc_rlwinmd (code, ppc_r11, ppc_r11, 1, 31, 31);
2531                         EMIT_COND_SYSTEM_EXCEPTION (CEE_BEQ - CEE_BEQ, "ArithmeticException");*/
2532                         g_assert_not_reached ();
2533                         break;
2534                 }
2535                 default:
2536                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
2537                         g_assert_not_reached ();
2538                 }
2539
2540                 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
2541                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
2542                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
2543                         g_assert_not_reached ();
2544                 }
2545
2546                 cpos += max_len;
2547
2548                 last_ins = ins;
2549                 last_offset = offset;
2550
2551                 ins = ins->next;
2552         }
2553
2554         cfg->code_len = code - cfg->native_code;
2555 }
2556
2557 void
2558 mono_arch_register_lowlevel_calls (void)
2559 {
2560 }
2561
2562 #define patch_lis_ori(ip,val) do {\
2563                 guint16 *__lis_ori = (guint16*)(ip);    \
2564                 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff;      \
2565                 __lis_ori [3] = ((guint32)(val)) & 0xffff;      \
2566         } while (0)
2567
2568 void
2569 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
2570 {
2571         MonoJumpInfo *patch_info;
2572
2573         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
2574                 unsigned char *ip = patch_info->ip.i + code;
2575                 const unsigned char *target;
2576
2577                 if (patch_info->type == MONO_PATCH_INFO_SWITCH) {
2578                         gpointer *table = (gpointer *)patch_info->data.table->table;
2579                         gpointer *jt = (gpointer*)(ip + 8);
2580                         int i;
2581                         /* jt is the inlined jump table, 2 instructions after ip
2582                          * In the normal case we store the absolute addresses,
2583                          * otherwise the displacements.
2584                          */
2585                         for (i = 0; i < patch_info->data.table->table_size; i++) {
2586                                 jt [i] = code + (int)patch_info->data.table->table [i];
2587                         }
2588                         continue;
2589                 }
2590                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
2591
2592                 switch (patch_info->type) {
2593                 case MONO_PATCH_INFO_IP:
2594                         g_assert_not_reached ();
2595                         patch_lis_ori (ip, ip);
2596                         continue;
2597                 case MONO_PATCH_INFO_METHOD_REL:
2598                         g_assert_not_reached ();
2599                         *((gpointer *)(ip)) = code + patch_info->data.offset;
2600                         continue;
2601                 case MONO_PATCH_INFO_METHODCONST:
2602                 case MONO_PATCH_INFO_CLASS:
2603                 case MONO_PATCH_INFO_IMAGE:
2604                 case MONO_PATCH_INFO_FIELD:
2605                 case MONO_PATCH_INFO_VTABLE:
2606                 case MONO_PATCH_INFO_IID:
2607                 case MONO_PATCH_INFO_SFLDA:
2608                 case MONO_PATCH_INFO_LDSTR:
2609                 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
2610                 case MONO_PATCH_INFO_LDTOKEN:
2611                         g_assert_not_reached ();
2612                         /* from OP_AOTCONST : lis + ori */
2613                         patch_lis_ori (ip, target);
2614                         continue;
2615                 case MONO_PATCH_INFO_R4:
2616                 case MONO_PATCH_INFO_R8:
2617                         g_assert_not_reached ();
2618                         *((gconstpointer *)(ip + 2)) = patch_info->data.target;
2619                         continue;
2620                 case MONO_PATCH_INFO_EXC_NAME:
2621                         g_assert_not_reached ();
2622                         *((gconstpointer *)(ip + 1)) = patch_info->data.name;
2623                         continue;
2624                 case MONO_PATCH_INFO_NONE:
2625                 case MONO_PATCH_INFO_BB_OVF:
2626                 case MONO_PATCH_INFO_EXC_OVF:
2627                         /* everything is dealt with at epilog output time */
2628                         continue;
2629                 default:
2630                         break;
2631                 }
2632                 arm_patch (ip, target);
2633         }
2634 }
2635
2636 /*
2637  * Stack frame layout:
2638  *
2639  *   ------------------- fp
2640  *      MonoLMF structure or saved registers
2641  *   -------------------
2642  *      locals
2643  *   -------------------
2644  *      spilled regs
2645  *   -------------------
2646  *      optional 8 bytes for tracing
2647  *   -------------------
2648  *      param area             size is cfg->param_area
2649  *   ------------------- sp
2650  */
2651 guint8 *
2652 mono_arch_emit_prolog (MonoCompile *cfg)
2653 {
2654         MonoMethod *method = cfg->method;
2655         MonoBasicBlock *bb;
2656         MonoMethodSignature *sig;
2657         MonoInst *inst;
2658         int alloc_size, pos, max_offset, i, rot_amount;
2659         guint8 *code;
2660         CallInfo *cinfo;
2661         int tracing = 0;
2662         int lmf_offset = 0;
2663         int prev_sp_offset;
2664
2665         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
2666                 tracing = 1;
2667
2668         sig = mono_method_signature (method);
2669         cfg->code_size = 256 + sig->param_count * 20;
2670         code = cfg->native_code = g_malloc (cfg->code_size);
2671
2672         ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
2673
2674         alloc_size = cfg->stack_offset;
2675         pos = 0;
2676
2677         if (!method->save_lmf) {
2678                 ARM_PUSH (code, (cfg->used_int_regs | (1 << ARMREG_IP) | (1 << ARMREG_LR)));
2679                 prev_sp_offset = 8; /* ip and lr */
2680                 for (i = 0; i < 16; ++i) {
2681                         if (cfg->used_int_regs & (1 << i))
2682                                 prev_sp_offset += 4;
2683                 }
2684         } else {
2685                 ARM_PUSH (code, 0x5ff0);
2686                 prev_sp_offset = 4 * 10; /* all but r0-r3, sp and pc */
2687                 pos += sizeof (MonoLMF) - prev_sp_offset;
2688                 lmf_offset = pos;
2689         }
2690         alloc_size += pos;
2691         // align to MONO_ARCH_FRAME_ALIGNMENT bytes
2692         if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
2693                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
2694                 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
2695         }
2696
2697         /* the stack used in the pushed regs */
2698         if (prev_sp_offset & 4)
2699                 alloc_size += 4;
2700         cfg->stack_usage = alloc_size;
2701         if (alloc_size) {
2702                 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
2703                         ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
2704                 } else {
2705                         code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
2706                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
2707                 }
2708         }
2709         if (cfg->frame_reg != ARMREG_SP)
2710                 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
2711         //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
2712         prev_sp_offset += alloc_size;
2713
2714         /* compute max_offset in order to use short forward jumps
2715          * we could skip do it on arm because the immediate displacement
2716          * for jumps is large enough, it may be useful later for constant pools
2717          */
2718         max_offset = 0;
2719         for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
2720                 MonoInst *ins = bb->code;
2721                 bb->max_offset = max_offset;
2722
2723                 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
2724                         max_offset += 6;
2725
2726                 while (ins) {
2727                         max_offset += ((guint8 *)arm_cpu_desc [ins->opcode])[MONO_INST_LEN];
2728                         ins = ins->next;
2729                 }
2730         }
2731
2732         /* load arguments allocated to register from the stack */
2733         pos = 0;
2734
2735         cinfo = calculate_sizes (sig, sig->pinvoke);
2736
2737         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
2738                 ArgInfo *ainfo = &cinfo->ret;
2739                 inst = cfg->ret;
2740                 g_assert (arm_is_imm12 (inst->inst_offset));
2741                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2742         }
2743         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2744                 ArgInfo *ainfo = cinfo->args + i;
2745                 inst = cfg->varinfo [pos];
2746
2747                 if (cfg->verbose_level > 2)
2748                         g_print ("Saving argument %d (type: %d)\n", i, ainfo->regtype);
2749                 if (inst->opcode == OP_REGVAR) {
2750                         if (ainfo->regtype == RegTypeGeneral)
2751                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
2752                         else if (ainfo->regtype == RegTypeFP) {
2753                                 g_assert_not_reached ();
2754                         } else if (ainfo->regtype == RegTypeBase) {
2755                                 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
2756                                 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2757                         } else
2758                                 g_assert_not_reached ();
2759
2760                         if (cfg->verbose_level > 2)
2761                                 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
2762                 } else {
2763                         /* the argument should be put on the stack: FIXME handle size != word  */
2764                         if (ainfo->regtype == RegTypeGeneral) {
2765                                 switch (ainfo->size) {
2766                                 case 1:
2767                                         if (arm_is_imm12 (inst->inst_offset))
2768                                                 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2769                                         else {
2770                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
2771                                                 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
2772                                         }
2773                                         break;
2774                                 case 2:
2775                                         g_assert (arm_is_imm8 (inst->inst_offset));
2776                                         ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2777                                         break;
2778                                 case 8:
2779                                         g_assert (arm_is_imm12 (inst->inst_offset));
2780                                         ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2781                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
2782                                         ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
2783                                         break;
2784                                 default:
2785                                         if (arm_is_imm12 (inst->inst_offset)) {
2786                                                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2787                                         } else {
2788                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
2789                                                 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
2790                                         }
2791                                         break;
2792                                 }
2793                         } else if (ainfo->regtype == RegTypeBase) {
2794                                 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
2795                                 switch (ainfo->size) {
2796                                 case 1:
2797                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2798                                         g_assert (arm_is_imm12 (inst->inst_offset));
2799                                         ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2800                                         break;
2801                                 case 2:
2802                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2803                                         g_assert (arm_is_imm8 (inst->inst_offset));
2804                                         ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2805                                         break;
2806                                 case 8:
2807                                         g_assert (arm_is_imm12 (inst->inst_offset));
2808                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2809                                         ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2810                                         g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4));
2811                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
2812                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
2813                                         ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
2814                                         break;
2815                                 default:
2816                                         g_assert (arm_is_imm12 (inst->inst_offset));
2817                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
2818                                         ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
2819                                         break;
2820                                 }
2821                         } else if (ainfo->regtype == RegTypeFP) {
2822                                 g_assert_not_reached ();
2823                         } else if (ainfo->regtype == RegTypeStructByVal) {
2824                                 int doffset = inst->inst_offset;
2825                                 int soffset = 0;
2826                                 int cur_reg;
2827                                 int size = 0;
2828                                 if (mono_class_from_mono_type (inst->inst_vtype))
2829                                         size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
2830                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
2831                                         g_assert (arm_is_imm12 (doffset));
2832                                         ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
2833                                         soffset += sizeof (gpointer);
2834                                         doffset += sizeof (gpointer);
2835                                 }
2836                                 if (ainfo->vtsize) {
2837                                         /* FIXME: handle overrun! with struct sizes not multiple of 4 */
2838                                         //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
2839                                         code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
2840                                 }
2841                         } else if (ainfo->regtype == RegTypeStructByAddr) {
2842                                 g_assert_not_reached ();
2843                                 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
2844                                 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
2845                         } else
2846                                 g_assert_not_reached ();
2847                 }
2848                 pos++;
2849         }
2850
2851         if (method->save_lmf) {
2852
2853                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2854                              (gpointer)"mono_get_lmf_addr");
2855                 if (cfg->method->dynamic) {
2856                         ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2857                         ARM_B (code, 0);
2858                         *(gpointer*)code = NULL;
2859                         code += 4;
2860                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
2861                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2862                 } else {
2863                         ARM_BL (code, 0);
2864                 }
2865                 /* we build the MonoLMF structure on the stack - see mini-arm.h */
2866                 /* lmf_offset is the offset from the previous stack pointer,
2867                  * alloc_size is the total stack space allocated, so the offset
2868                  * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
2869                  * The pointer to the struct is put in r1 (new_lmf).
2870                  * r2 is used as scratch
2871                  * The callee-saved registers are already in the MonoLMF structure
2872                  */
2873                 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, alloc_size - lmf_offset);
2874                 /* r0 is the result from mono_get_lmf_addr () */
2875                 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
2876                 /* new_lmf->previous_lmf = *lmf_addr */
2877                 ARM_LDR_IMM (code, ARMREG_R2, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2878                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2879                 /* *(lmf_addr) = r1 */
2880                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2881                 /* save method info */
2882                 code = mono_arm_emit_load_imm (code, ARMREG_R2, method);
2883                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, method));
2884                 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ebp));
2885                 /* save the current IP */
2886                 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
2887                 ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, eip));
2888         }
2889
2890         if (tracing)
2891                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
2892
2893         cfg->code_len = code - cfg->native_code;
2894         g_assert (cfg->code_len < cfg->code_size);
2895         g_free (cinfo);
2896
2897         return code;
2898 }
2899
2900 void
2901 mono_arch_emit_epilog (MonoCompile *cfg)
2902 {
2903         MonoJumpInfo *patch_info;
2904         MonoMethod *method = cfg->method;
2905         int pos, i, rot_amount;
2906         int max_epilog_size = 16 + 20*4;
2907         guint8 *code;
2908
2909         if (cfg->method->save_lmf)
2910                 max_epilog_size += 128;
2911
2912         if (mono_jit_trace_calls != NULL)
2913                 max_epilog_size += 50;
2914
2915         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2916                 max_epilog_size += 50;
2917
2918         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
2919                 cfg->code_size *= 2;
2920                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2921                 mono_jit_stats.code_reallocs++;
2922         }
2923
2924         /*
2925          * Keep in sync with CEE_JMP
2926          */
2927         code = cfg->native_code + cfg->code_len;
2928
2929         if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
2930                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
2931         }
2932         pos = 0;
2933
2934         if (method->save_lmf) {
2935                 int lmf_offset;
2936                 /* all but r0-r3, sp and pc */
2937                 pos += sizeof (MonoLMF) - (4 * 10);
2938                 lmf_offset = pos;
2939                 /* r2 contains the pointer to the current LMF */
2940                 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, cfg->stack_usage - lmf_offset);
2941                 /* ip = previous_lmf */
2942                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2943                 /* lr = lmf_addr */
2944                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R2, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
2945                 /* *(lmf_addr) = previous_lmf */
2946                 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2947                 /* FIXME: speedup: there is no actual need to restore the registers if
2948                  * we didn't actually change them (idea from Zoltan).
2949                  */
2950                 /* restore iregs */
2951                 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
2952                 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_R2, (sizeof (MonoLMF) - 10 * sizeof (gulong)));
2953                 ARM_POP_NWB (code, 0xaff0); /* restore ip to sp and lr to pc */
2954         } else {
2955                 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
2956                         ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
2957                 } else {
2958                         code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
2959                         ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
2960                 }
2961                 ARM_POP_NWB (code, cfg->used_int_regs | ((1 << ARMREG_SP) | (1 << ARMREG_PC)));
2962         }
2963
2964         cfg->code_len = code - cfg->native_code;
2965
2966         g_assert (cfg->code_len < cfg->code_size);
2967
2968 }
2969
2970 /* remove once throw_exception_by_name is eliminated */
2971 static int
2972 exception_id_by_name (const char *name)
2973 {
2974         if (strcmp (name, "IndexOutOfRangeException") == 0)
2975                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2976         if (strcmp (name, "OverflowException") == 0)
2977                 return MONO_EXC_OVERFLOW;
2978         if (strcmp (name, "ArithmeticException") == 0)
2979                 return MONO_EXC_ARITHMETIC;
2980         if (strcmp (name, "DivideByZeroException") == 0)
2981                 return MONO_EXC_DIVIDE_BY_ZERO;
2982         if (strcmp (name, "InvalidCastException") == 0)
2983                 return MONO_EXC_INVALID_CAST;
2984         if (strcmp (name, "NullReferenceException") == 0)
2985                 return MONO_EXC_NULL_REF;
2986         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2987                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2988         g_error ("Unknown intrinsic exception %s\n", name);
2989 }
2990
2991 void
2992 mono_arch_emit_exceptions (MonoCompile *cfg)
2993 {
2994         MonoJumpInfo *patch_info;
2995         int nthrows, i;
2996         guint8 *code;
2997         const guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM] = {NULL};
2998         guint8 exc_throw_found [MONO_EXC_INTRINS_NUM] = {0};
2999         guint32 code_size;
3000         int exc_count = 0;
3001         int max_epilog_size = 50;
3002
3003         /* count the number of exception infos */
3004
3005         /*
3006          * make sure we have enough space for exceptions
3007          * 12 is the simulated call to throw_exception_by_name
3008          */
3009         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3010                 if (patch_info->type == MONO_PATCH_INFO_EXC) {
3011                         i = exception_id_by_name (patch_info->data.target);
3012                         if (!exc_throw_found [i]) {
3013                                 max_epilog_size += 12;
3014                                 exc_throw_found [i] = TRUE;
3015                         }
3016                 }
3017         }
3018
3019         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
3020                 cfg->code_size *= 2;
3021                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3022                 mono_jit_stats.code_reallocs++;
3023         }
3024
3025         code = cfg->native_code + cfg->code_len;
3026
3027         /* add code to raise exceptions */
3028         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3029                 switch (patch_info->type) {
3030                 case MONO_PATCH_INFO_EXC: {
3031                         unsigned char *ip = patch_info->ip.i + cfg->native_code;
3032                         const char *ex_name = patch_info->data.target;
3033                         i = exception_id_by_name (patch_info->data.target);
3034                         if (exc_throw_pos [i]) {
3035                                 arm_patch (ip, exc_throw_pos [i]);
3036                                 patch_info->type = MONO_PATCH_INFO_NONE;
3037                                 break;
3038                         } else {
3039                                 exc_throw_pos [i] = code;
3040                         }
3041                         arm_patch (ip, code);
3042                         //*(int*)code = 0xef9f0001;
3043                         code += 4;
3044                         /*mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC_NAME, patch_info->data.target);*/
3045                         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
3046                         /* we got here from a conditional call, so the calling ip is set in lr already */
3047                         patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
3048                         patch_info->data.name = "mono_arch_throw_exception_by_name";
3049                         patch_info->ip.i = code - cfg->native_code;
3050                         ARM_B (code, 0);
3051                         *(gpointer*)code = ex_name;
3052                         code += 4;
3053                         break;
3054                 }
3055                 default:
3056                         /* do nothing */
3057                         break;
3058                 }
3059         }
3060
3061         cfg->code_len = code - cfg->native_code;
3062
3063         g_assert (cfg->code_len < cfg->code_size);
3064
3065 }
3066
3067 void
3068 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
3069 {
3070 }
3071
3072 void
3073 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
3074 {
3075 }
3076
3077 void
3078 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
3079 {
3080
3081         int this_dreg = ARMREG_R0;
3082
3083         if (vt_reg != -1)
3084                 this_dreg = ARMREG_R1;
3085
3086         /* add the this argument */
3087         if (this_reg != -1) {
3088                 MonoInst *this;
3089                 MONO_INST_NEW (cfg, this, OP_SETREG);
3090                 this->type = this_type;
3091                 this->sreg1 = this_reg;
3092                 this->dreg = mono_regstate_next_int (cfg->rs);
3093                 mono_bblock_add_inst (cfg->cbb, this);
3094                 mono_call_inst_add_outarg_reg (inst, this->dreg, this_dreg, FALSE);
3095         }
3096
3097         if (vt_reg != -1) {
3098                 MonoInst *vtarg;
3099                 MONO_INST_NEW (cfg, vtarg, OP_SETREG);
3100                 vtarg->type = STACK_MP;
3101                 vtarg->sreg1 = vt_reg;
3102                 vtarg->dreg = mono_regstate_next_int (cfg->rs);
3103                 mono_bblock_add_inst (cfg->cbb, vtarg);
3104                 mono_call_inst_add_outarg_reg (inst, vtarg->dreg, ARMREG_R0, FALSE);
3105         }
3106 }
3107
3108 MonoInst*
3109 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
3110 {
3111         return NULL;
3112 }
3113
3114 gboolean
3115 mono_arch_print_tree (MonoInst *tree, int arity)
3116 {
3117         return 0;
3118 }
3119
3120 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
3121 {
3122         return NULL;
3123 }
3124
3125 MonoInst*
3126 mono_arch_get_thread_intrinsic (MonoCompile* cfg)
3127 {
3128         return NULL;
3129 }
3130
3131 void
3132 mono_arch_flush_register_windows (void)
3133 {
3134 }
3135
3136 void
3137 mono_arch_fixup_jinfo (MonoCompile *cfg)
3138 {
3139         /* max encoded stack usage is 64KB * 4 */
3140         g_assert ((cfg->stack_usage & ~(0xffff << 2)) == 0);
3141         cfg->jit_info->used_regs |= cfg->stack_usage << 14;
3142 }
3143