2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
27 #include "debugger-agent.h"
29 #include "mono/arch/arm/arm-vfp-codegen.h"
31 /* Sanity check: This makes no sense */
32 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
33 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
37 * IS_SOFT_FLOAT: Is full software floating point used?
38 * IS_HARD_FLOAT: Is full hardware floating point used?
39 * IS_VFP: Is hardware floating point with software ABI used?
41 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
42 * IS_VFP may delegate to mono_arch_is_soft_float ().
45 #if defined(ARM_FPU_VFP_HARD)
46 #define IS_SOFT_FLOAT (FALSE)
47 #define IS_HARD_FLOAT (TRUE)
49 #elif defined(ARM_FPU_NONE)
50 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
51 #define IS_HARD_FLOAT (FALSE)
52 #define IS_VFP (!mono_arch_is_soft_float ())
54 #define IS_SOFT_FLOAT (FALSE)
55 #define IS_HARD_FLOAT (FALSE)
59 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(__native_client__)
60 #define HAVE_AEABI_READ_TP 1
63 #define THUNK_SIZE (3 * 4)
65 #ifdef __native_client_codegen__
66 const guint kNaClAlignment = kNaClAlignmentARM;
67 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
68 gint8 nacl_align_byte = -1; /* 0xff */
71 mono_arch_nacl_pad (guint8 *code, int pad)
73 /* Not yet properly implemented. */
74 g_assert_not_reached ();
79 mono_arch_nacl_skip_nops (guint8 *code)
81 /* Not yet properly implemented. */
82 g_assert_not_reached ();
86 #endif /* __native_client_codegen__ */
88 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
91 void sys_icache_invalidate (void *start, size_t len);
94 /* This mutex protects architecture specific caches */
95 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
96 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
97 static mono_mutex_t mini_arch_mutex;
99 static gboolean v5_supported = FALSE;
100 static gboolean v6_supported = FALSE;
101 static gboolean v7_supported = FALSE;
102 static gboolean v7s_supported = FALSE;
103 static gboolean thumb_supported = FALSE;
104 static gboolean thumb2_supported = FALSE;
106 * Whenever to use the ARM EABI
108 static gboolean eabi_supported = FALSE;
111 * Whenever to use the iphone ABI extensions:
112 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
113 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
114 * This is required for debugging/profiling tools to work, but it has some overhead so it should
115 * only be turned on in debug builds.
117 static gboolean iphone_abi = FALSE;
120 * The FPU we are generating code for. This is NOT runtime configurable right now,
121 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
123 static MonoArmFPU arm_fpu;
125 #if defined(ARM_FPU_VFP_HARD)
127 * On armhf, d0-d7 are used for argument passing and d8-d15
128 * must be preserved across calls, which leaves us no room
129 * for scratch registers. So we use d14-d15 but back up their
130 * previous contents to a stack slot before using them - see
131 * mono_arm_emit_vfp_scratch_save/_restore ().
133 static int vfp_scratch1 = ARM_VFP_D14;
134 static int vfp_scratch2 = ARM_VFP_D15;
137 * On armel, d0-d7 do not need to be preserved, so we can
138 * freely make use of them as scratch registers.
140 static int vfp_scratch1 = ARM_VFP_D0;
141 static int vfp_scratch2 = ARM_VFP_D1;
146 static volatile int ss_trigger_var = 0;
148 static gpointer single_step_tramp, breakpoint_tramp;
151 * The code generated for sequence points reads from this location, which is
152 * made read-only when single stepping is enabled.
154 static gpointer ss_trigger_page;
156 /* Enabled breakpoints read from this trigger page */
157 static gpointer bp_trigger_page;
161 * floating point support: on ARM it is a mess, there are at least 3
162 * different setups, each of which binary incompat with the other.
163 * 1) FPA: old and ugly, but unfortunately what current distros use
164 * the double binary format has the two words swapped. 8 double registers.
165 * Implemented usually by kernel emulation.
166 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
167 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
168 * 3) VFP: the new and actually sensible and useful FP support. Implemented
169 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
171 * We do not care about FPA. We will support soft float and VFP.
173 int mono_exc_esp_offset = 0;
175 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
176 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
177 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
179 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
180 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
181 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
183 //#define DEBUG_IMT 0
186 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
190 mono_arch_regname (int reg)
192 static const char * rnames[] = {
193 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
194 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
195 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
198 if (reg >= 0 && reg < 16)
204 mono_arch_fregname (int reg)
206 static const char * rnames[] = {
207 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
208 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
209 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
210 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
211 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
212 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
215 if (reg >= 0 && reg < 32)
223 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
225 int imm8, rot_amount;
226 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
227 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
231 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
232 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
234 code = mono_arm_emit_load_imm (code, dreg, imm);
235 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
240 /* If dreg == sreg, this clobbers IP */
242 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
244 int imm8, rot_amount;
245 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
246 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
250 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
251 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
253 code = mono_arm_emit_load_imm (code, dreg, imm);
254 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
260 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
262 /* we can use r0-r3, since this is called only for incoming args on the stack */
263 if (size > sizeof (gpointer) * 4) {
265 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
266 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
267 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
268 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
269 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
270 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
271 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
272 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
273 ARM_B_COND (code, ARMCOND_NE, 0);
274 arm_patch (code - 4, start_loop);
277 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
278 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
280 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
281 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
287 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
288 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
289 doffset = soffset = 0;
291 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
292 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
298 g_assert (size == 0);
303 emit_call_reg (guint8 *code, int reg)
306 ARM_BLX_REG (code, reg);
308 #ifdef USE_JUMP_TABLES
309 g_assert_not_reached ();
311 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
315 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
321 emit_call_seq (MonoCompile *cfg, guint8 *code)
323 #ifdef USE_JUMP_TABLES
324 code = mono_arm_patchable_bl (code, ARMCOND_AL);
326 if (cfg->method->dynamic) {
327 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
329 *(gpointer*)code = NULL;
331 code = emit_call_reg (code, ARMREG_IP);
335 cfg->thunk_area += THUNK_SIZE;
341 mono_arm_patchable_b (guint8 *code, int cond)
343 #ifdef USE_JUMP_TABLES
346 jte = mono_jumptable_add_entry ();
347 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
348 ARM_BX_COND (code, cond, ARMREG_IP);
350 ARM_B_COND (code, cond, 0);
356 mono_arm_patchable_bl (guint8 *code, int cond)
358 #ifdef USE_JUMP_TABLES
361 jte = mono_jumptable_add_entry ();
362 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
363 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
365 ARM_BL_COND (code, cond, 0);
370 #ifdef USE_JUMP_TABLES
372 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
374 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
375 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
380 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
382 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
383 ARM_LDR_IMM (code, reg, reg, 0);
391 * Emit code to push an LMF structure on the LMF stack.
392 * On arm, this is intermixed with the initialization of other fields of the structure.
395 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
397 gboolean get_lmf_fast = FALSE;
400 #ifdef HAVE_AEABI_READ_TP
401 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
403 if (lmf_addr_tls_offset != -1) {
406 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
407 (gpointer)"__aeabi_read_tp");
408 code = emit_call_seq (cfg, code);
410 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
416 if (cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) {
419 /* Inline mono_get_lmf_addr () */
420 /* jit_tls = pthread_getspecific (mono_jit_tls_id); lmf_addr = &jit_tls->lmf; */
422 /* Load mono_jit_tls_id */
424 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_TLS_ID, NULL);
425 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
427 *(gpointer*)code = NULL;
429 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
430 /* call pthread_getspecific () */
431 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
432 (gpointer)"pthread_getspecific");
433 code = emit_call_seq (cfg, code);
434 /* lmf_addr = &jit_tls->lmf */
435 lmf_offset = MONO_STRUCT_OFFSET (MonoJitTlsData, lmf);
436 g_assert (arm_is_imm8 (lmf_offset));
437 ARM_ADD_REG_IMM (code, ARMREG_R0, ARMREG_R0, lmf_offset, 0);
444 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
445 (gpointer)"mono_get_lmf_addr");
446 code = emit_call_seq (cfg, code);
448 /* we build the MonoLMF structure on the stack - see mini-arm.h */
449 /* lmf_offset is the offset from the previous stack pointer,
450 * alloc_size is the total stack space allocated, so the offset
451 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
452 * The pointer to the struct is put in r1 (new_lmf).
453 * ip is used as scratch
454 * The callee-saved registers are already in the MonoLMF structure
456 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
457 /* r0 is the result from mono_get_lmf_addr () */
458 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
459 /* new_lmf->previous_lmf = *lmf_addr */
460 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
461 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
462 /* *(lmf_addr) = r1 */
463 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
464 /* Skip method (only needed for trampoline LMF frames) */
465 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
466 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
467 /* save the current IP */
468 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
469 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
471 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
472 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
483 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
487 g_assert (!cfg->r4fp);
489 for (list = inst->float_args; list; list = list->next) {
490 FloatArgData *fad = list->data;
491 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
492 gboolean imm = arm_is_fpimm8 (var->inst_offset);
494 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
500 if (*offset + *max_len > cfg->code_size) {
501 cfg->code_size += *max_len;
502 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
504 code = cfg->native_code + *offset;
508 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
509 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
511 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
513 *offset = code - cfg->native_code;
520 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
524 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
526 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
529 if (!arm_is_fpimm8 (inst->inst_offset)) {
530 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
531 ARM_FSTD (code, reg, ARMREG_LR, 0);
533 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
540 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
544 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
546 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
549 if (!arm_is_fpimm8 (inst->inst_offset)) {
550 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
551 ARM_FLDD (code, reg, ARMREG_LR, 0);
553 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
562 * Emit code to pop an LMF structure from the LMF stack.
565 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
569 if (lmf_offset < 32) {
570 basereg = cfg->frame_reg;
575 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
578 /* ip = previous_lmf */
579 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
581 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
582 /* *(lmf_addr) = previous_lmf */
583 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
588 #endif /* #ifndef DISABLE_JIT */
591 * mono_arch_get_argument_info:
592 * @csig: a method signature
593 * @param_count: the number of parameters to consider
594 * @arg_info: an array to store the result infos
596 * Gathers information on parameters such as size, alignment and
597 * padding. arg_info should be large enought to hold param_count + 1 entries.
599 * Returns the size of the activation frame.
602 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
604 int k, frame_size = 0;
605 guint32 size, align, pad;
609 t = mini_type_get_underlying_type (gsctx, csig->ret);
610 if (MONO_TYPE_ISSTRUCT (t)) {
611 frame_size += sizeof (gpointer);
615 arg_info [0].offset = offset;
618 frame_size += sizeof (gpointer);
622 arg_info [0].size = frame_size;
624 for (k = 0; k < param_count; k++) {
625 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
627 /* ignore alignment for now */
630 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
631 arg_info [k].pad = pad;
633 arg_info [k + 1].pad = 0;
634 arg_info [k + 1].size = size;
636 arg_info [k + 1].offset = offset;
640 align = MONO_ARCH_FRAME_ALIGNMENT;
641 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
642 arg_info [k].pad = pad;
647 #define MAX_ARCH_DELEGATE_PARAMS 3
650 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
652 guint8 *code, *start;
655 start = code = mono_global_codeman_reserve (12);
657 /* Replace the this argument with the target */
658 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
659 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
660 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
662 g_assert ((code - start) <= 12);
664 mono_arch_flush_icache (start, 12);
668 size = 8 + param_count * 4;
669 start = code = mono_global_codeman_reserve (size);
671 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
672 /* slide down the arguments */
673 for (i = 0; i < param_count; ++i) {
674 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
676 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
678 g_assert ((code - start) <= size);
680 mono_arch_flush_icache (start, size);
683 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
685 *code_size = code - start;
691 * mono_arch_get_delegate_invoke_impls:
693 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
697 mono_arch_get_delegate_invoke_impls (void)
705 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
706 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
708 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
709 code = get_delegate_invoke_impl (FALSE, i, &code_len);
710 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
711 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
719 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
721 guint8 *code, *start;
724 /* FIXME: Support more cases */
725 sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
726 if (MONO_TYPE_ISSTRUCT (sig_ret))
730 static guint8* cached = NULL;
731 mono_mini_arch_lock ();
733 mono_mini_arch_unlock ();
738 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
740 start = get_delegate_invoke_impl (TRUE, 0, NULL);
742 mono_mini_arch_unlock ();
745 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
748 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
750 for (i = 0; i < sig->param_count; ++i)
751 if (!mono_is_regsize_var (sig->params [i]))
754 mono_mini_arch_lock ();
755 code = cache [sig->param_count];
757 mono_mini_arch_unlock ();
762 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
763 start = mono_aot_get_trampoline (name);
766 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
768 cache [sig->param_count] = start;
769 mono_mini_arch_unlock ();
777 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
783 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
785 return (gpointer)regs [ARMREG_R0];
789 * Initialize the cpu to execute managed code.
792 mono_arch_cpu_init (void)
794 i8_align = MONO_ABI_ALIGNOF (gint64);
795 #ifdef MONO_CROSS_COMPILE
796 /* Need to set the alignment of i8 since it can different on the target */
797 #ifdef TARGET_ANDROID
799 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
805 * Initialize architecture specific code.
808 mono_arch_init (void)
810 const char *cpu_arch;
812 mono_mutex_init_recursive (&mini_arch_mutex);
813 if (mini_get_debug_options ()->soft_breakpoints) {
814 single_step_tramp = mini_get_single_step_trampoline ();
815 breakpoint_tramp = mini_get_breakpoint_trampoline ();
817 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
818 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
819 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
822 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
823 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
824 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
825 #if defined(ENABLE_GSHAREDVT)
826 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
829 #if defined(__ARM_EABI__)
830 eabi_supported = TRUE;
833 #if defined(ARM_FPU_VFP_HARD)
834 arm_fpu = MONO_ARM_FPU_VFP_HARD;
836 arm_fpu = MONO_ARM_FPU_VFP;
838 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
840 * If we're compiling with a soft float fallback and it
841 * turns out that no VFP unit is available, we need to
842 * switch to soft float. We don't do this for iOS, since
843 * iOS devices always have a VFP unit.
845 if (!mono_hwcap_arm_has_vfp)
846 arm_fpu = MONO_ARM_FPU_NONE;
849 * This environment variable can be useful in testing
850 * environments to make sure the soft float fallback
851 * works. Most ARM devices have VFP units these days, so
852 * normally soft float code would not be exercised much.
854 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
856 if (soft && !strncmp (soft, "1", 1))
857 arm_fpu = MONO_ARM_FPU_NONE;
861 v5_supported = mono_hwcap_arm_is_v5;
862 v6_supported = mono_hwcap_arm_is_v6;
863 v7_supported = mono_hwcap_arm_is_v7;
864 v7s_supported = mono_hwcap_arm_is_v7s;
866 #if defined(__APPLE__)
867 /* iOS is special-cased here because we don't yet
868 have a way to properly detect CPU features on it. */
869 thumb_supported = TRUE;
872 thumb_supported = mono_hwcap_arm_has_thumb;
873 thumb2_supported = mono_hwcap_arm_has_thumb2;
876 /* Format: armv(5|6|7[s])[-thumb[2]] */
877 cpu_arch = g_getenv ("MONO_CPU_ARCH");
879 /* Do this here so it overrides any detection. */
881 if (strncmp (cpu_arch, "armv", 4) == 0) {
882 v5_supported = cpu_arch [4] >= '5';
883 v6_supported = cpu_arch [4] >= '6';
884 v7_supported = cpu_arch [4] >= '7';
885 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
888 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
889 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
894 * Cleanup architecture specific code.
897 mono_arch_cleanup (void)
902 * This function returns the optimizations supported on this cpu.
905 mono_arch_cpu_optimizations (guint32 *exclude_mask)
907 /* no arm-specific optimizations yet */
913 * This function test for all SIMD functions supported.
915 * Returns a bitmask corresponding to all supported versions.
919 mono_arch_cpu_enumerate_simd_versions (void)
921 /* SIMD is currently unimplemented */
929 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
945 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
947 mono_arch_is_soft_float (void)
949 return arm_fpu == MONO_ARM_FPU_NONE;
954 mono_arm_is_hard_float (void)
956 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
960 is_regsize_var (MonoGenericSharingContext *gsctx, MonoType *t) {
963 t = mini_type_get_underlying_type (gsctx, t);
970 case MONO_TYPE_FNPTR:
972 case MONO_TYPE_OBJECT:
973 case MONO_TYPE_STRING:
974 case MONO_TYPE_CLASS:
975 case MONO_TYPE_SZARRAY:
976 case MONO_TYPE_ARRAY:
978 case MONO_TYPE_GENERICINST:
979 if (!mono_type_generic_inst_is_valuetype (t))
982 case MONO_TYPE_VALUETYPE:
989 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
994 for (i = 0; i < cfg->num_varinfo; i++) {
995 MonoInst *ins = cfg->varinfo [i];
996 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
999 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1002 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1005 /* we can only allocate 32 bit values */
1006 if (is_regsize_var (cfg->generic_sharing_context, ins->inst_vtype)) {
1007 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1008 g_assert (i == vmv->idx);
1009 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1017 mono_arch_get_global_int_regs (MonoCompile *cfg)
1021 mono_arch_compute_omit_fp (cfg);
1024 * FIXME: Interface calls might go through a static rgctx trampoline which
1025 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1028 if (cfg->flags & MONO_CFG_HAS_CALLS)
1029 cfg->uses_rgctx_reg = TRUE;
1031 if (cfg->arch.omit_fp)
1032 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1033 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1034 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1035 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1037 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1038 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1040 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1041 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1042 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1043 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1044 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1045 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1051 * mono_arch_regalloc_cost:
1053 * Return the cost, in number of memory references, of the action of
1054 * allocating the variable VMV into a register during global register
1058 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1064 #endif /* #ifndef DISABLE_JIT */
1066 #ifndef __GNUC_PREREQ
1067 #define __GNUC_PREREQ(maj, min) (0)
1071 mono_arch_flush_icache (guint8 *code, gint size)
1073 #if defined(__native_client__)
1074 // For Native Client we don't have to flush i-cache here,
1075 // as it's being done by dyncode interface.
1078 #ifdef MONO_CROSS_COMPILE
1080 sys_icache_invalidate (code, size);
1081 #elif __GNUC_PREREQ(4, 3)
1082 __builtin___clear_cache (code, code + size);
1083 #elif __GNUC_PREREQ(4, 1)
1084 __clear_cache (code, code + size);
1085 #elif defined(PLATFORM_ANDROID)
1086 const int syscall = 0xf0002;
1094 : "r" (code), "r" (code + size), "r" (syscall)
1095 : "r0", "r1", "r7", "r2"
1098 __asm __volatile ("mov r0, %0\n"
1101 "swi 0x9f0002 @ sys_cacheflush"
1103 : "r" (code), "r" (code + size), "r" (0)
1104 : "r0", "r1", "r3" );
1106 #endif /* !__native_client__ */
1117 RegTypeStructByAddr,
1118 /* gsharedvt argument passed by addr in greg */
1119 RegTypeGSharedVtInReg,
1120 /* gsharedvt argument passed by addr on stack */
1121 RegTypeGSharedVtOnStack,
1127 guint16 vtsize; /* in param area */
1135 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1140 guint32 stack_usage;
1141 /* The index of the vret arg in the argument list for RegTypeStructByAddr */
1151 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1154 if (*gr > ARMREG_R3) {
1156 ainfo->offset = *stack_size;
1157 ainfo->reg = ARMREG_SP; /* in the caller */
1158 ainfo->storage = RegTypeBase;
1161 ainfo->storage = RegTypeGeneral;
1168 split = i8_align == 4;
1173 if (*gr == ARMREG_R3 && split) {
1174 /* first word in r3 and the second on the stack */
1175 ainfo->offset = *stack_size;
1176 ainfo->reg = ARMREG_SP; /* in the caller */
1177 ainfo->storage = RegTypeBaseGen;
1179 } else if (*gr >= ARMREG_R3) {
1180 if (eabi_supported) {
1181 /* darwin aligns longs to 4 byte only */
1182 if (i8_align == 8) {
1187 ainfo->offset = *stack_size;
1188 ainfo->reg = ARMREG_SP; /* in the caller */
1189 ainfo->storage = RegTypeBase;
1192 if (eabi_supported) {
1193 if (i8_align == 8 && ((*gr) & 1))
1196 ainfo->storage = RegTypeIRegPair;
1205 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1208 * If we're calling a function like this:
1210 * void foo(float a, double b, float c)
1212 * We pass a in s0 and b in d1. That leaves us
1213 * with s1 being unused. The armhf ABI recognizes
1214 * this and requires register assignment to then
1215 * use that for the next single-precision arg,
1216 * i.e. c in this example. So float_spare either
1217 * tells us which reg to use for the next single-
1218 * precision arg, or it's -1, meaning use *fpr.
1220 * Note that even though most of the JIT speaks
1221 * double-precision, fpr represents single-
1222 * precision registers.
1224 * See parts 5.5 and 6.1.2 of the AAPCS for how
1228 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1229 ainfo->storage = RegTypeFP;
1233 * If we're passing a double-precision value
1234 * and *fpr is odd (e.g. it's s1, s3, ...)
1235 * we need to use the next even register. So
1236 * we mark the current *fpr as a spare that
1237 * can be used for the next single-precision
1241 *float_spare = *fpr;
1246 * At this point, we have an even register
1247 * so we assign that and move along.
1251 } else if (*float_spare >= 0) {
1253 * We're passing a single-precision value
1254 * and it looks like a spare single-
1255 * precision register is available. Let's
1259 ainfo->reg = *float_spare;
1263 * If we hit this branch, we're passing a
1264 * single-precision value and we can simply
1265 * use the next available register.
1273 * We've exhausted available floating point
1274 * regs, so pass the rest on the stack.
1282 ainfo->offset = *stack_size;
1283 ainfo->reg = ARMREG_SP;
1284 ainfo->storage = RegTypeBase;
1291 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1295 MonoClassField *field;
1296 MonoType *ftype, *prev_ftype = NULL;
1299 klass = mono_class_from_mono_type (t);
1301 while ((field = mono_class_get_fields (klass, &iter))) {
1302 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1304 ftype = mono_field_get_type (field);
1305 ftype = mini_type_get_underlying_type (NULL, ftype);
1307 if (MONO_TYPE_ISSTRUCT (ftype)) {
1308 int nested_nfields, nested_esize;
1310 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1312 if (nested_esize == 4)
1313 ftype = &mono_defaults.single_class->byval_arg;
1315 ftype = &mono_defaults.double_class->byval_arg;
1316 if (prev_ftype && prev_ftype->type != ftype->type)
1319 nfields += nested_nfields;
1321 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1323 if (prev_ftype && prev_ftype->type != ftype->type)
1329 if (nfields == 0 || nfields > 4)
1331 *out_nfields = nfields;
1332 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1337 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
1339 guint i, gr, fpr, pstart;
1341 int n = sig->hasthis + sig->param_count;
1345 guint32 stack_size = 0;
1347 gboolean is_pinvoke = sig->pinvoke;
1348 gboolean vtype_retaddr = FALSE;
1351 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1353 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1360 t = mini_type_get_underlying_type (gsctx, sig->ret);
1371 case MONO_TYPE_FNPTR:
1372 case MONO_TYPE_CLASS:
1373 case MONO_TYPE_OBJECT:
1374 case MONO_TYPE_SZARRAY:
1375 case MONO_TYPE_ARRAY:
1376 case MONO_TYPE_STRING:
1377 cinfo->ret.storage = RegTypeGeneral;
1378 cinfo->ret.reg = ARMREG_R0;
1382 cinfo->ret.storage = RegTypeIRegPair;
1383 cinfo->ret.reg = ARMREG_R0;
1387 cinfo->ret.storage = RegTypeFP;
1389 if (IS_HARD_FLOAT) {
1390 cinfo->ret.reg = ARM_VFP_F0;
1392 cinfo->ret.reg = ARMREG_R0;
1395 case MONO_TYPE_GENERICINST:
1396 if (!mono_type_generic_inst_is_valuetype (t)) {
1397 cinfo->ret.storage = RegTypeGeneral;
1398 cinfo->ret.reg = ARMREG_R0;
1401 // FIXME: Only for variable types
1402 if (mini_is_gsharedvt_type_gsctx (gsctx, t)) {
1403 cinfo->ret.storage = RegTypeStructByAddr;
1407 case MONO_TYPE_VALUETYPE:
1408 case MONO_TYPE_TYPEDBYREF:
1409 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1410 cinfo->ret.storage = RegTypeHFA;
1412 cinfo->ret.nregs = nfields;
1413 cinfo->ret.esize = esize;
1415 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1416 cinfo->ret.storage = RegTypeStructByVal;
1418 cinfo->ret.storage = RegTypeStructByAddr;
1422 case MONO_TYPE_MVAR:
1423 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, t));
1424 cinfo->ret.storage = RegTypeStructByAddr;
1426 case MONO_TYPE_VOID:
1429 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1432 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1437 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1438 * the first argument, allowing 'this' to be always passed in the first arg reg.
1439 * Also do this if the first argument is a reference type, since virtual calls
1440 * are sometimes made using calli without sig->hasthis set, like in the delegate
1443 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1445 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1447 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1451 cinfo->ret.reg = gr;
1453 cinfo->vret_arg_index = 1;
1457 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1460 if (vtype_retaddr) {
1461 cinfo->ret.reg = gr;
1466 DEBUG(printf("params: %d\n", sig->param_count));
1467 for (i = pstart; i < sig->param_count; ++i) {
1468 ArgInfo *ainfo = &cinfo->args [n];
1470 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1471 /* Prevent implicit arguments and sig_cookie from
1472 being passed in registers */
1475 /* Emit the signature cookie just before the implicit arguments */
1476 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1478 DEBUG(printf("param %d: ", i));
1479 if (sig->params [i]->byref) {
1480 DEBUG(printf("byref\n"));
1481 add_general (&gr, &stack_size, ainfo, TRUE);
1485 t = mini_type_get_underlying_type (gsctx, sig->params [i]);
1489 cinfo->args [n].size = 1;
1490 add_general (&gr, &stack_size, ainfo, TRUE);
1494 cinfo->args [n].size = 2;
1495 add_general (&gr, &stack_size, ainfo, TRUE);
1499 cinfo->args [n].size = 4;
1500 add_general (&gr, &stack_size, ainfo, TRUE);
1505 case MONO_TYPE_FNPTR:
1506 case MONO_TYPE_CLASS:
1507 case MONO_TYPE_OBJECT:
1508 case MONO_TYPE_STRING:
1509 case MONO_TYPE_SZARRAY:
1510 case MONO_TYPE_ARRAY:
1511 cinfo->args [n].size = sizeof (gpointer);
1512 add_general (&gr, &stack_size, ainfo, TRUE);
1514 case MONO_TYPE_GENERICINST:
1515 if (!mono_type_generic_inst_is_valuetype (t)) {
1516 cinfo->args [n].size = sizeof (gpointer);
1517 add_general (&gr, &stack_size, ainfo, TRUE);
1520 if (mini_is_gsharedvt_type_gsctx (gsctx, t)) {
1521 /* gsharedvt arguments are passed by ref */
1522 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, t));
1523 add_general (&gr, &stack_size, ainfo, TRUE);
1524 switch (ainfo->storage) {
1525 case RegTypeGeneral:
1526 ainfo->storage = RegTypeGSharedVtInReg;
1529 ainfo->storage = RegTypeGSharedVtOnStack;
1532 g_assert_not_reached ();
1537 case MONO_TYPE_TYPEDBYREF:
1538 case MONO_TYPE_VALUETYPE: {
1541 int nwords, nfields, esize;
1544 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1545 if (fpr + nfields < ARM_VFP_F16) {
1546 ainfo->storage = RegTypeHFA;
1548 ainfo->nregs = nfields;
1549 ainfo->esize = esize;
1557 if (t->type == MONO_TYPE_TYPEDBYREF) {
1558 size = sizeof (MonoTypedRef);
1559 align = sizeof (gpointer);
1561 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1563 size = mono_class_native_size (klass, &align);
1565 size = mini_type_stack_size_full (gsctx, t, &align, FALSE);
1567 DEBUG(printf ("load %d bytes struct\n", size));
1570 align_size += (sizeof (gpointer) - 1);
1571 align_size &= ~(sizeof (gpointer) - 1);
1572 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1573 ainfo->storage = RegTypeStructByVal;
1574 ainfo->struct_size = size;
1575 /* FIXME: align stack_size if needed */
1576 if (eabi_supported) {
1577 if (align >= 8 && (gr & 1))
1580 if (gr > ARMREG_R3) {
1582 ainfo->vtsize = nwords;
1584 int rest = ARMREG_R3 - gr + 1;
1585 int n_in_regs = rest >= nwords? nwords: rest;
1587 ainfo->size = n_in_regs;
1588 ainfo->vtsize = nwords - n_in_regs;
1591 nwords -= n_in_regs;
1593 if (sig->call_convention == MONO_CALL_VARARG)
1594 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1595 stack_size = ALIGN_TO (stack_size, align);
1596 ainfo->offset = stack_size;
1597 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1598 stack_size += nwords * sizeof (gpointer);
1604 add_general (&gr, &stack_size, ainfo, FALSE);
1610 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1612 add_general (&gr, &stack_size, ainfo, TRUE);
1618 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1620 add_general (&gr, &stack_size, ainfo, FALSE);
1623 case MONO_TYPE_MVAR:
1624 /* gsharedvt arguments are passed by ref */
1625 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, t));
1626 add_general (&gr, &stack_size, ainfo, TRUE);
1627 switch (ainfo->storage) {
1628 case RegTypeGeneral:
1629 ainfo->storage = RegTypeGSharedVtInReg;
1632 ainfo->storage = RegTypeGSharedVtOnStack;
1635 g_assert_not_reached ();
1639 g_error ("Can't handle 0x%x", sig->params [i]->type);
1644 /* Handle the case where there are no implicit arguments */
1645 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1646 /* Prevent implicit arguments and sig_cookie from
1647 being passed in registers */
1650 /* Emit the signature cookie just before the implicit arguments */
1651 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1654 /* align stack size to 8 */
1655 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1656 stack_size = (stack_size + 7) & ~7;
1658 cinfo->stack_usage = stack_size;
1664 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1666 MonoType *callee_ret;
1670 if (cfg->compile_aot && !cfg->full_aot)
1671 /* OP_TAILCALL doesn't work with AOT */
1674 c1 = get_call_info (NULL, NULL, caller_sig);
1675 c2 = get_call_info (NULL, NULL, callee_sig);
1678 * Tail calls with more callee stack usage than the caller cannot be supported, since
1679 * the extra stack space would be left on the stack after the tail call.
1681 res = c1->stack_usage >= c2->stack_usage;
1682 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1683 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1684 /* An address on the callee's stack is passed as the first argument */
1687 if (c2->stack_usage > 16 * 4)
1699 debug_omit_fp (void)
1702 return mono_debug_count ();
1709 * mono_arch_compute_omit_fp:
1711 * Determine whenever the frame pointer can be eliminated.
1714 mono_arch_compute_omit_fp (MonoCompile *cfg)
1716 MonoMethodSignature *sig;
1717 MonoMethodHeader *header;
1721 if (cfg->arch.omit_fp_computed)
1724 header = cfg->header;
1726 sig = mono_method_signature (cfg->method);
1728 if (!cfg->arch.cinfo)
1729 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1730 cinfo = cfg->arch.cinfo;
1733 * FIXME: Remove some of the restrictions.
1735 cfg->arch.omit_fp = TRUE;
1736 cfg->arch.omit_fp_computed = TRUE;
1738 if (cfg->disable_omit_fp)
1739 cfg->arch.omit_fp = FALSE;
1740 if (!debug_omit_fp ())
1741 cfg->arch.omit_fp = FALSE;
1743 if (cfg->method->save_lmf)
1744 cfg->arch.omit_fp = FALSE;
1746 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1747 cfg->arch.omit_fp = FALSE;
1748 if (header->num_clauses)
1749 cfg->arch.omit_fp = FALSE;
1750 if (cfg->param_area)
1751 cfg->arch.omit_fp = FALSE;
1752 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1753 cfg->arch.omit_fp = FALSE;
1754 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1755 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1756 cfg->arch.omit_fp = FALSE;
1757 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1758 ArgInfo *ainfo = &cinfo->args [i];
1760 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1762 * The stack offset can only be determined when the frame
1765 cfg->arch.omit_fp = FALSE;
1770 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1771 MonoInst *ins = cfg->varinfo [i];
1774 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1779 * Set var information according to the calling convention. arm version.
1780 * The locals var stuff should most likely be split in another method.
1783 mono_arch_allocate_vars (MonoCompile *cfg)
1785 MonoMethodSignature *sig;
1786 MonoMethodHeader *header;
1789 int i, offset, size, align, curinst;
1794 sig = mono_method_signature (cfg->method);
1796 if (!cfg->arch.cinfo)
1797 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1798 cinfo = cfg->arch.cinfo;
1799 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1801 mono_arch_compute_omit_fp (cfg);
1803 if (cfg->arch.omit_fp)
1804 cfg->frame_reg = ARMREG_SP;
1806 cfg->frame_reg = ARMREG_FP;
1808 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1810 /* allow room for the vararg method args: void* and long/double */
1811 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1812 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1814 header = cfg->header;
1816 /* See mono_arch_get_global_int_regs () */
1817 if (cfg->flags & MONO_CFG_HAS_CALLS)
1818 cfg->uses_rgctx_reg = TRUE;
1820 if (cfg->frame_reg != ARMREG_SP)
1821 cfg->used_int_regs |= 1 << cfg->frame_reg;
1823 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1824 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1825 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1829 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1830 if (sig_ret->type != MONO_TYPE_VOID) {
1831 cfg->ret->opcode = OP_REGVAR;
1832 cfg->ret->inst_c0 = ARMREG_R0;
1835 /* local vars are at a positive offset from the stack pointer */
1837 * also note that if the function uses alloca, we use FP
1838 * to point at the local variables.
1840 offset = 0; /* linkage area */
1841 /* align the offset to 16 bytes: not sure this is needed here */
1843 //offset &= ~(8 - 1);
1845 /* add parameter area size for called functions */
1846 offset += cfg->param_area;
1849 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1852 /* allow room to save the return value */
1853 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1856 switch (cinfo->ret.storage) {
1857 case RegTypeStructByVal:
1858 cfg->ret->opcode = OP_REGOFFSET;
1859 cfg->ret->inst_basereg = cfg->frame_reg;
1860 offset += sizeof (gpointer) - 1;
1861 offset &= ~(sizeof (gpointer) - 1);
1862 cfg->ret->inst_offset = - offset;
1863 offset += sizeof(gpointer);
1866 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1867 offset = ALIGN_TO (offset, 8);
1868 cfg->ret->opcode = OP_REGOFFSET;
1869 cfg->ret->inst_basereg = cfg->frame_reg;
1870 cfg->ret->inst_offset = offset;
1874 case RegTypeStructByAddr:
1875 ins = cfg->vret_addr;
1876 offset += sizeof(gpointer) - 1;
1877 offset &= ~(sizeof(gpointer) - 1);
1878 ins->inst_offset = offset;
1879 ins->opcode = OP_REGOFFSET;
1880 ins->inst_basereg = cfg->frame_reg;
1881 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1882 printf ("vret_addr =");
1883 mono_print_ins (cfg->vret_addr);
1885 offset += sizeof(gpointer);
1891 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1892 if (cfg->arch.seq_point_info_var) {
1895 ins = cfg->arch.seq_point_info_var;
1899 offset += align - 1;
1900 offset &= ~(align - 1);
1901 ins->opcode = OP_REGOFFSET;
1902 ins->inst_basereg = cfg->frame_reg;
1903 ins->inst_offset = offset;
1906 ins = cfg->arch.ss_trigger_page_var;
1909 offset += align - 1;
1910 offset &= ~(align - 1);
1911 ins->opcode = OP_REGOFFSET;
1912 ins->inst_basereg = cfg->frame_reg;
1913 ins->inst_offset = offset;
1917 if (cfg->arch.seq_point_read_var) {
1920 ins = cfg->arch.seq_point_read_var;
1924 offset += align - 1;
1925 offset &= ~(align - 1);
1926 ins->opcode = OP_REGOFFSET;
1927 ins->inst_basereg = cfg->frame_reg;
1928 ins->inst_offset = offset;
1931 ins = cfg->arch.seq_point_ss_method_var;
1934 offset += align - 1;
1935 offset &= ~(align - 1);
1936 ins->opcode = OP_REGOFFSET;
1937 ins->inst_basereg = cfg->frame_reg;
1938 ins->inst_offset = offset;
1941 ins = cfg->arch.seq_point_bp_method_var;
1944 offset += align - 1;
1945 offset &= ~(align - 1);
1946 ins->opcode = OP_REGOFFSET;
1947 ins->inst_basereg = cfg->frame_reg;
1948 ins->inst_offset = offset;
1952 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1953 /* Allocate a temporary used by the atomic ops */
1957 /* Allocate a local slot to hold the sig cookie address */
1958 offset += align - 1;
1959 offset &= ~(align - 1);
1960 cfg->arch.atomic_tmp_offset = offset;
1963 cfg->arch.atomic_tmp_offset = -1;
1966 cfg->locals_min_stack_offset = offset;
1968 curinst = cfg->locals_start;
1969 for (i = curinst; i < cfg->num_varinfo; ++i) {
1972 ins = cfg->varinfo [i];
1973 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1976 t = ins->inst_vtype;
1977 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (cfg, t))
1980 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1981 * pinvoke wrappers when they call functions returning structure */
1982 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1983 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1987 size = mono_type_size (t, &align);
1989 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1990 * since it loads/stores misaligned words, which don't do the right thing.
1992 if (align < 4 && size >= 4)
1994 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1995 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1996 offset += align - 1;
1997 offset &= ~(align - 1);
1998 ins->opcode = OP_REGOFFSET;
1999 ins->inst_offset = offset;
2000 ins->inst_basereg = cfg->frame_reg;
2002 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2005 cfg->locals_max_stack_offset = offset;
2009 ins = cfg->args [curinst];
2010 if (ins->opcode != OP_REGVAR) {
2011 ins->opcode = OP_REGOFFSET;
2012 ins->inst_basereg = cfg->frame_reg;
2013 offset += sizeof (gpointer) - 1;
2014 offset &= ~(sizeof (gpointer) - 1);
2015 ins->inst_offset = offset;
2016 offset += sizeof (gpointer);
2021 if (sig->call_convention == MONO_CALL_VARARG) {
2025 /* Allocate a local slot to hold the sig cookie address */
2026 offset += align - 1;
2027 offset &= ~(align - 1);
2028 cfg->sig_cookie = offset;
2032 for (i = 0; i < sig->param_count; ++i) {
2033 ainfo = cinfo->args + i;
2035 ins = cfg->args [curinst];
2037 switch (ainfo->storage) {
2039 offset = ALIGN_TO (offset, 8);
2040 ins->opcode = OP_REGOFFSET;
2041 ins->inst_basereg = cfg->frame_reg;
2042 /* These arguments are saved to the stack in the prolog */
2043 ins->inst_offset = offset;
2044 if (cfg->verbose_level >= 2)
2045 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2053 if (ins->opcode != OP_REGVAR) {
2054 ins->opcode = OP_REGOFFSET;
2055 ins->inst_basereg = cfg->frame_reg;
2056 size = mini_type_stack_size_full (cfg->generic_sharing_context, sig->params [i], &ualign, sig->pinvoke);
2058 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2059 * since it loads/stores misaligned words, which don't do the right thing.
2061 if (align < 4 && size >= 4)
2063 /* The code in the prolog () stores words when storing vtypes received in a register */
2064 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2066 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2067 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2068 offset += align - 1;
2069 offset &= ~(align - 1);
2070 ins->inst_offset = offset;
2076 /* align the offset to 8 bytes */
2077 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2078 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2083 cfg->stack_offset = offset;
2087 mono_arch_create_vars (MonoCompile *cfg)
2089 MonoMethodSignature *sig;
2093 sig = mono_method_signature (cfg->method);
2095 if (!cfg->arch.cinfo)
2096 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2097 cinfo = cfg->arch.cinfo;
2099 if (IS_HARD_FLOAT) {
2100 for (i = 0; i < 2; i++) {
2101 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2102 inst->flags |= MONO_INST_VOLATILE;
2104 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2108 if (cinfo->ret.storage == RegTypeStructByVal)
2109 cfg->ret_var_is_local = TRUE;
2111 if (cinfo->ret.storage == RegTypeStructByAddr) {
2112 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2113 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2114 printf ("vret_addr = ");
2115 mono_print_ins (cfg->vret_addr);
2119 if (cfg->gen_sdb_seq_points) {
2120 if (cfg->soft_breakpoints) {
2121 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2122 ins->flags |= MONO_INST_VOLATILE;
2123 cfg->arch.seq_point_read_var = ins;
2125 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2126 ins->flags |= MONO_INST_VOLATILE;
2127 cfg->arch.seq_point_ss_method_var = ins;
2129 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2130 ins->flags |= MONO_INST_VOLATILE;
2131 cfg->arch.seq_point_bp_method_var = ins;
2133 g_assert (!cfg->compile_aot);
2134 } else if (cfg->compile_aot) {
2135 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2136 ins->flags |= MONO_INST_VOLATILE;
2137 cfg->arch.seq_point_info_var = ins;
2139 /* Allocate a separate variable for this to save 1 load per seq point */
2140 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2141 ins->flags |= MONO_INST_VOLATILE;
2142 cfg->arch.ss_trigger_page_var = ins;
2148 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2150 MonoMethodSignature *tmp_sig;
2153 if (call->tail_call)
2156 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2159 * mono_ArgIterator_Setup assumes the signature cookie is
2160 * passed first and all the arguments which were before it are
2161 * passed on the stack after the signature. So compensate by
2162 * passing a different signature.
2164 tmp_sig = mono_metadata_signature_dup (call->signature);
2165 tmp_sig->param_count -= call->signature->sentinelpos;
2166 tmp_sig->sentinelpos = 0;
2167 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2169 sig_reg = mono_alloc_ireg (cfg);
2170 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2172 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2177 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2182 LLVMCallInfo *linfo;
2184 n = sig->param_count + sig->hasthis;
2186 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2188 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2191 * LLVM always uses the native ABI while we use our own ABI, the
2192 * only difference is the handling of vtypes:
2193 * - we only pass/receive them in registers in some cases, and only
2194 * in 1 or 2 integer registers.
2196 if (cinfo->ret.storage == RegTypeStructByAddr) {
2197 /* Vtype returned using a hidden argument */
2198 linfo->ret.storage = LLVMArgVtypeRetAddr;
2199 linfo->vret_arg_index = cinfo->vret_arg_index;
2200 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
2201 cfg->exception_message = g_strdup ("unknown ret conv");
2202 cfg->disable_llvm = TRUE;
2206 for (i = 0; i < n; ++i) {
2207 ainfo = cinfo->args + i;
2209 linfo->args [i].storage = LLVMArgNone;
2211 switch (ainfo->storage) {
2212 case RegTypeGeneral:
2213 case RegTypeIRegPair:
2215 linfo->args [i].storage = LLVMArgInIReg;
2217 case RegTypeStructByVal:
2218 linfo->args [i].storage = LLVMArgAsIArgs;
2219 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2222 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2223 cfg->disable_llvm = TRUE;
2233 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2236 MonoMethodSignature *sig;
2240 sig = call->signature;
2241 n = sig->param_count + sig->hasthis;
2243 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2245 switch (cinfo->ret.storage) {
2246 case RegTypeStructByVal:
2247 /* The JIT will transform this into a normal call */
2248 call->vret_in_reg = TRUE;
2252 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2253 * the location pointed to by it after call in emit_move_return_value ().
2255 if (!cfg->arch.vret_addr_loc) {
2256 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2257 /* Prevent it from being register allocated or optimized away */
2258 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2261 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2263 case RegTypeStructByAddr: {
2265 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2266 vtarg->sreg1 = call->vret_var->dreg;
2267 vtarg->dreg = mono_alloc_preg (cfg);
2268 MONO_ADD_INS (cfg->cbb, vtarg);
2270 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2277 for (i = 0; i < n; ++i) {
2278 ArgInfo *ainfo = cinfo->args + i;
2281 if (i >= sig->hasthis)
2282 t = sig->params [i - sig->hasthis];
2284 t = &mono_defaults.int_class->byval_arg;
2285 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
2287 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2288 /* Emit the signature cookie just before the implicit arguments */
2289 emit_sig_cookie (cfg, call, cinfo);
2292 in = call->args [i];
2294 switch (ainfo->storage) {
2295 case RegTypeGeneral:
2296 case RegTypeIRegPair:
2297 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2298 MONO_INST_NEW (cfg, ins, OP_MOVE);
2299 ins->dreg = mono_alloc_ireg (cfg);
2300 ins->sreg1 = in->dreg + 1;
2301 MONO_ADD_INS (cfg->cbb, ins);
2302 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2304 MONO_INST_NEW (cfg, ins, OP_MOVE);
2305 ins->dreg = mono_alloc_ireg (cfg);
2306 ins->sreg1 = in->dreg + 2;
2307 MONO_ADD_INS (cfg->cbb, ins);
2308 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2309 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2310 if (ainfo->size == 4) {
2311 if (IS_SOFT_FLOAT) {
2312 /* mono_emit_call_args () have already done the r8->r4 conversion */
2313 /* The converted value is in an int vreg */
2314 MONO_INST_NEW (cfg, ins, OP_MOVE);
2315 ins->dreg = mono_alloc_ireg (cfg);
2316 ins->sreg1 = in->dreg;
2317 MONO_ADD_INS (cfg->cbb, ins);
2318 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2322 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2323 creg = mono_alloc_ireg (cfg);
2324 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2325 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2328 if (IS_SOFT_FLOAT) {
2329 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2330 ins->dreg = mono_alloc_ireg (cfg);
2331 ins->sreg1 = in->dreg;
2332 MONO_ADD_INS (cfg->cbb, ins);
2333 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2335 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2336 ins->dreg = mono_alloc_ireg (cfg);
2337 ins->sreg1 = in->dreg;
2338 MONO_ADD_INS (cfg->cbb, ins);
2339 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2343 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2344 creg = mono_alloc_ireg (cfg);
2345 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2346 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2347 creg = mono_alloc_ireg (cfg);
2348 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2349 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2352 cfg->flags |= MONO_CFG_HAS_FPOUT;
2354 MONO_INST_NEW (cfg, ins, OP_MOVE);
2355 ins->dreg = mono_alloc_ireg (cfg);
2356 ins->sreg1 = in->dreg;
2357 MONO_ADD_INS (cfg->cbb, ins);
2359 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2362 case RegTypeStructByAddr:
2365 /* FIXME: where si the data allocated? */
2366 arg->backend.reg3 = ainfo->reg;
2367 call->used_iregs |= 1 << ainfo->reg;
2368 g_assert_not_reached ();
2371 case RegTypeStructByVal:
2372 case RegTypeGSharedVtInReg:
2373 case RegTypeGSharedVtOnStack:
2375 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2376 ins->opcode = OP_OUTARG_VT;
2377 ins->sreg1 = in->dreg;
2378 ins->klass = in->klass;
2379 ins->inst_p0 = call;
2380 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2381 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2382 mono_call_inst_add_outarg_vt (cfg, call, ins);
2383 MONO_ADD_INS (cfg->cbb, ins);
2386 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2387 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2388 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2389 if (t->type == MONO_TYPE_R8) {
2390 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2393 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2395 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2398 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2401 case RegTypeBaseGen:
2402 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2403 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
2404 MONO_INST_NEW (cfg, ins, OP_MOVE);
2405 ins->dreg = mono_alloc_ireg (cfg);
2406 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
2407 MONO_ADD_INS (cfg->cbb, ins);
2408 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2409 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2412 /* This should work for soft-float as well */
2414 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2415 creg = mono_alloc_ireg (cfg);
2416 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2417 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2418 creg = mono_alloc_ireg (cfg);
2419 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2420 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2421 cfg->flags |= MONO_CFG_HAS_FPOUT;
2423 g_assert_not_reached ();
2427 int fdreg = mono_alloc_freg (cfg);
2429 if (ainfo->size == 8) {
2430 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2431 ins->sreg1 = in->dreg;
2433 MONO_ADD_INS (cfg->cbb, ins);
2435 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2440 * Mono's register allocator doesn't speak single-precision registers that
2441 * overlap double-precision registers (i.e. armhf). So we have to work around
2442 * the register allocator and load the value from memory manually.
2444 * So we create a variable for the float argument and an instruction to store
2445 * the argument into the variable. We then store the list of these arguments
2446 * in cfg->float_args. This list is then used by emit_float_args later to
2447 * pass the arguments in the various call opcodes.
2449 * This is not very nice, and we should really try to fix the allocator.
2452 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2454 /* Make sure the instruction isn't seen as pointless and removed.
2456 float_arg->flags |= MONO_INST_VOLATILE;
2458 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2460 /* We use the dreg to look up the instruction later. The hreg is used to
2461 * emit the instruction that loads the value into the FP reg.
2463 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2464 fad->vreg = float_arg->dreg;
2465 fad->hreg = ainfo->reg;
2467 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2470 call->used_iregs |= 1 << ainfo->reg;
2471 cfg->flags |= MONO_CFG_HAS_FPOUT;
2475 g_assert_not_reached ();
2479 /* Handle the case where there are no implicit arguments */
2480 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2481 emit_sig_cookie (cfg, call, cinfo);
2483 call->call_info = cinfo;
2484 call->stack_usage = cinfo->stack_usage;
2488 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2494 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2495 ins->dreg = mono_alloc_freg (cfg);
2496 ins->sreg1 = arg->dreg;
2497 MONO_ADD_INS (cfg->cbb, ins);
2498 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2501 g_assert_not_reached ();
2507 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2509 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2511 ArgInfo *ainfo = ins->inst_p1;
2512 int ovf_size = ainfo->vtsize;
2513 int doffset = ainfo->offset;
2514 int struct_size = ainfo->struct_size;
2515 int i, soffset, dreg, tmpreg;
2517 switch (ainfo->storage) {
2518 case RegTypeGSharedVtInReg:
2520 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2522 case RegTypeGSharedVtOnStack:
2523 /* Pass by addr on stack */
2524 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2527 for (i = 0; i < ainfo->nregs; ++i) {
2528 if (ainfo->esize == 4)
2529 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2531 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2532 load->dreg = mono_alloc_freg (cfg);
2533 load->inst_basereg = src->dreg;
2534 load->inst_offset = i * ainfo->esize;
2535 MONO_ADD_INS (cfg->cbb, load);
2537 if (ainfo->esize == 4) {
2540 /* See RegTypeFP in mono_arch_emit_call () */
2541 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2542 float_arg->flags |= MONO_INST_VOLATILE;
2543 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2545 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2546 fad->vreg = float_arg->dreg;
2547 fad->hreg = ainfo->reg + i;
2549 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2551 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + i, load);
2557 for (i = 0; i < ainfo->size; ++i) {
2558 dreg = mono_alloc_ireg (cfg);
2559 switch (struct_size) {
2561 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2564 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2567 tmpreg = mono_alloc_ireg (cfg);
2568 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2569 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2570 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2571 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2572 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2573 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2574 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2577 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2580 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2581 soffset += sizeof (gpointer);
2582 struct_size -= sizeof (gpointer);
2584 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2586 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2592 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2594 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2597 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2600 if (COMPILE_LLVM (cfg)) {
2601 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2603 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2604 ins->sreg1 = val->dreg + 1;
2605 ins->sreg2 = val->dreg + 2;
2606 MONO_ADD_INS (cfg->cbb, ins);
2611 case MONO_ARM_FPU_NONE:
2612 if (ret->type == MONO_TYPE_R8) {
2615 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2616 ins->dreg = cfg->ret->dreg;
2617 ins->sreg1 = val->dreg;
2618 MONO_ADD_INS (cfg->cbb, ins);
2621 if (ret->type == MONO_TYPE_R4) {
2622 /* Already converted to an int in method_to_ir () */
2623 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2627 case MONO_ARM_FPU_VFP:
2628 case MONO_ARM_FPU_VFP_HARD:
2629 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2632 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2633 ins->dreg = cfg->ret->dreg;
2634 ins->sreg1 = val->dreg;
2635 MONO_ADD_INS (cfg->cbb, ins);
2640 g_assert_not_reached ();
2644 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2647 #endif /* #ifndef DISABLE_JIT */
2650 mono_arch_is_inst_imm (gint64 imm)
2656 MonoMethodSignature *sig;
2659 MonoType **param_types;
2663 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2667 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2670 switch (cinfo->ret.storage) {
2672 case RegTypeGeneral:
2673 case RegTypeIRegPair:
2674 case RegTypeStructByAddr:
2685 for (i = 0; i < cinfo->nargs; ++i) {
2686 ArgInfo *ainfo = &cinfo->args [i];
2689 switch (ainfo->storage) {
2690 case RegTypeGeneral:
2692 case RegTypeIRegPair:
2695 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2698 case RegTypeStructByVal:
2699 if (ainfo->size == 0)
2700 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2702 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2703 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2711 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2712 for (i = 0; i < sig->param_count; ++i) {
2713 MonoType *t = sig->params [i];
2718 t = mini_replace_type (t);
2741 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2743 ArchDynCallInfo *info;
2747 cinfo = get_call_info (NULL, NULL, sig);
2749 if (!dyn_call_supported (cinfo, sig)) {
2754 info = g_new0 (ArchDynCallInfo, 1);
2755 // FIXME: Preprocess the info to speed up start_dyn_call ()
2757 info->cinfo = cinfo;
2758 info->rtype = mini_type_get_underlying_type (NULL, sig->ret);
2759 info->param_types = g_new0 (MonoType*, sig->param_count);
2760 for (i = 0; i < sig->param_count; ++i)
2761 info->param_types [i] = mini_type_get_underlying_type (NULL, sig->params [i]);
2763 return (MonoDynCallInfo*)info;
2767 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2769 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2771 g_free (ainfo->cinfo);
2776 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2778 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2779 DynCallArgs *p = (DynCallArgs*)buf;
2780 int arg_index, greg, i, j, pindex;
2781 MonoMethodSignature *sig = dinfo->sig;
2783 g_assert (buf_len >= sizeof (DynCallArgs));
2792 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2793 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2798 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2799 p->regs [greg ++] = (mgreg_t)ret;
2801 for (i = pindex; i < sig->param_count; i++) {
2802 MonoType *t = dinfo->param_types [i];
2803 gpointer *arg = args [arg_index ++];
2804 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2807 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2809 else if (ainfo->storage == RegTypeBase)
2810 slot = PARAM_REGS + (ainfo->offset / 4);
2812 g_assert_not_reached ();
2815 p->regs [slot] = (mgreg_t)*arg;
2820 case MONO_TYPE_STRING:
2821 case MONO_TYPE_CLASS:
2822 case MONO_TYPE_ARRAY:
2823 case MONO_TYPE_SZARRAY:
2824 case MONO_TYPE_OBJECT:
2828 p->regs [slot] = (mgreg_t)*arg;
2831 p->regs [slot] = *(guint8*)arg;
2834 p->regs [slot] = *(gint8*)arg;
2837 p->regs [slot] = *(gint16*)arg;
2840 p->regs [slot] = *(guint16*)arg;
2843 p->regs [slot] = *(gint32*)arg;
2846 p->regs [slot] = *(guint32*)arg;
2850 p->regs [slot ++] = (mgreg_t)arg [0];
2851 p->regs [slot] = (mgreg_t)arg [1];
2854 p->regs [slot] = *(mgreg_t*)arg;
2857 p->regs [slot ++] = (mgreg_t)arg [0];
2858 p->regs [slot] = (mgreg_t)arg [1];
2860 case MONO_TYPE_GENERICINST:
2861 if (MONO_TYPE_IS_REFERENCE (t)) {
2862 p->regs [slot] = (mgreg_t)*arg;
2867 case MONO_TYPE_VALUETYPE:
2868 g_assert (ainfo->storage == RegTypeStructByVal);
2870 if (ainfo->size == 0)
2871 slot = PARAM_REGS + (ainfo->offset / 4);
2875 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2876 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2879 g_assert_not_reached ();
2885 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2887 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2888 MonoType *ptype = ainfo->rtype;
2889 guint8 *ret = ((DynCallArgs*)buf)->ret;
2890 mgreg_t res = ((DynCallArgs*)buf)->res;
2891 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2893 switch (ptype->type) {
2894 case MONO_TYPE_VOID:
2895 *(gpointer*)ret = NULL;
2897 case MONO_TYPE_STRING:
2898 case MONO_TYPE_CLASS:
2899 case MONO_TYPE_ARRAY:
2900 case MONO_TYPE_SZARRAY:
2901 case MONO_TYPE_OBJECT:
2905 *(gpointer*)ret = (gpointer)res;
2911 *(guint8*)ret = res;
2914 *(gint16*)ret = res;
2917 *(guint16*)ret = res;
2920 *(gint32*)ret = res;
2923 *(guint32*)ret = res;
2927 /* This handles endianness as well */
2928 ((gint32*)ret) [0] = res;
2929 ((gint32*)ret) [1] = res2;
2931 case MONO_TYPE_GENERICINST:
2932 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2933 *(gpointer*)ret = (gpointer)res;
2938 case MONO_TYPE_VALUETYPE:
2939 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2944 *(float*)ret = *(float*)&res;
2946 case MONO_TYPE_R8: {
2953 *(double*)ret = *(double*)®s;
2957 g_assert_not_reached ();
2964 * Allow tracing to work with this interface (with an optional argument)
2968 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2972 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2973 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2974 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2975 code = emit_call_reg (code, ARMREG_R2);
2989 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2992 int save_mode = SAVE_NONE;
2994 MonoMethod *method = cfg->method;
2995 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2996 int rtype = ret_type->type;
2997 int save_offset = cfg->param_area;
3001 offset = code - cfg->native_code;
3002 /* we need about 16 instructions */
3003 if (offset > (cfg->code_size - 16 * 4)) {
3004 cfg->code_size *= 2;
3005 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3006 code = cfg->native_code + offset;
3009 case MONO_TYPE_VOID:
3010 /* special case string .ctor icall */
3011 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3012 save_mode = SAVE_ONE;
3014 save_mode = SAVE_NONE;
3018 save_mode = SAVE_TWO;
3022 save_mode = SAVE_ONE_FP;
3024 save_mode = SAVE_ONE;
3028 save_mode = SAVE_TWO_FP;
3030 save_mode = SAVE_TWO;
3032 case MONO_TYPE_GENERICINST:
3033 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3034 save_mode = SAVE_ONE;
3038 case MONO_TYPE_VALUETYPE:
3039 save_mode = SAVE_STRUCT;
3042 save_mode = SAVE_ONE;
3046 switch (save_mode) {
3048 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3049 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3050 if (enable_arguments) {
3051 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3052 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3056 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3057 if (enable_arguments) {
3058 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3062 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3063 if (enable_arguments) {
3064 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3068 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3069 if (enable_arguments) {
3070 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3074 if (enable_arguments) {
3075 /* FIXME: get the actual address */
3076 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3084 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3085 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3086 code = emit_call_reg (code, ARMREG_IP);
3088 switch (save_mode) {
3090 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3091 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3094 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3097 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3100 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3111 * The immediate field for cond branches is big enough for all reasonable methods
3113 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3114 if (0 && ins->inst_true_bb->native_offset) { \
3115 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3117 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3118 ARM_B_COND (code, (condcode), 0); \
3121 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3123 /* emit an exception if condition is fail
3125 * We assign the extra code used to throw the implicit exceptions
3126 * to cfg->bb_exit as far as the big branch handling is concerned
3128 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3130 mono_add_patch_info (cfg, code - cfg->native_code, \
3131 MONO_PATCH_INFO_EXC, exc_name); \
3132 ARM_BL_COND (code, (condcode), 0); \
3135 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3138 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3143 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3147 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3148 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3150 switch (ins->opcode) {
3153 /* Already done by an arch-independent pass */
3155 case OP_LOAD_MEMBASE:
3156 case OP_LOADI4_MEMBASE:
3158 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3159 * OP_LOAD_MEMBASE offset(basereg), reg
3161 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3162 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3163 ins->inst_basereg == last_ins->inst_destbasereg &&
3164 ins->inst_offset == last_ins->inst_offset) {
3165 if (ins->dreg == last_ins->sreg1) {
3166 MONO_DELETE_INS (bb, ins);
3169 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3170 ins->opcode = OP_MOVE;
3171 ins->sreg1 = last_ins->sreg1;
3175 * Note: reg1 must be different from the basereg in the second load
3176 * OP_LOAD_MEMBASE offset(basereg), reg1
3177 * OP_LOAD_MEMBASE offset(basereg), reg2
3179 * OP_LOAD_MEMBASE offset(basereg), reg1
3180 * OP_MOVE reg1, reg2
3182 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3183 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3184 ins->inst_basereg != last_ins->dreg &&
3185 ins->inst_basereg == last_ins->inst_basereg &&
3186 ins->inst_offset == last_ins->inst_offset) {
3188 if (ins->dreg == last_ins->dreg) {
3189 MONO_DELETE_INS (bb, ins);
3192 ins->opcode = OP_MOVE;
3193 ins->sreg1 = last_ins->dreg;
3196 //g_assert_not_reached ();
3200 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3201 * OP_LOAD_MEMBASE offset(basereg), reg
3203 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3204 * OP_ICONST reg, imm
3206 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3207 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3208 ins->inst_basereg == last_ins->inst_destbasereg &&
3209 ins->inst_offset == last_ins->inst_offset) {
3210 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3211 ins->opcode = OP_ICONST;
3212 ins->inst_c0 = last_ins->inst_imm;
3213 g_assert_not_reached (); // check this rule
3217 case OP_LOADU1_MEMBASE:
3218 case OP_LOADI1_MEMBASE:
3219 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3220 ins->inst_basereg == last_ins->inst_destbasereg &&
3221 ins->inst_offset == last_ins->inst_offset) {
3222 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3223 ins->sreg1 = last_ins->sreg1;
3226 case OP_LOADU2_MEMBASE:
3227 case OP_LOADI2_MEMBASE:
3228 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3229 ins->inst_basereg == last_ins->inst_destbasereg &&
3230 ins->inst_offset == last_ins->inst_offset) {
3231 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3232 ins->sreg1 = last_ins->sreg1;
3236 ins->opcode = OP_MOVE;
3240 if (ins->dreg == ins->sreg1) {
3241 MONO_DELETE_INS (bb, ins);
3245 * OP_MOVE sreg, dreg
3246 * OP_MOVE dreg, sreg
3248 if (last_ins && last_ins->opcode == OP_MOVE &&
3249 ins->sreg1 == last_ins->dreg &&
3250 ins->dreg == last_ins->sreg1) {
3251 MONO_DELETE_INS (bb, ins);
3260 * the branch_cc_table should maintain the order of these
3274 branch_cc_table [] = {
3288 #define ADD_NEW_INS(cfg,dest,op) do { \
3289 MONO_INST_NEW ((cfg), (dest), (op)); \
3290 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3294 map_to_reg_reg_op (int op)
3303 case OP_COMPARE_IMM:
3305 case OP_ICOMPARE_IMM:
3319 case OP_LOAD_MEMBASE:
3320 return OP_LOAD_MEMINDEX;
3321 case OP_LOADI4_MEMBASE:
3322 return OP_LOADI4_MEMINDEX;
3323 case OP_LOADU4_MEMBASE:
3324 return OP_LOADU4_MEMINDEX;
3325 case OP_LOADU1_MEMBASE:
3326 return OP_LOADU1_MEMINDEX;
3327 case OP_LOADI2_MEMBASE:
3328 return OP_LOADI2_MEMINDEX;
3329 case OP_LOADU2_MEMBASE:
3330 return OP_LOADU2_MEMINDEX;
3331 case OP_LOADI1_MEMBASE:
3332 return OP_LOADI1_MEMINDEX;
3333 case OP_STOREI1_MEMBASE_REG:
3334 return OP_STOREI1_MEMINDEX;
3335 case OP_STOREI2_MEMBASE_REG:
3336 return OP_STOREI2_MEMINDEX;
3337 case OP_STOREI4_MEMBASE_REG:
3338 return OP_STOREI4_MEMINDEX;
3339 case OP_STORE_MEMBASE_REG:
3340 return OP_STORE_MEMINDEX;
3341 case OP_STORER4_MEMBASE_REG:
3342 return OP_STORER4_MEMINDEX;
3343 case OP_STORER8_MEMBASE_REG:
3344 return OP_STORER8_MEMINDEX;
3345 case OP_STORE_MEMBASE_IMM:
3346 return OP_STORE_MEMBASE_REG;
3347 case OP_STOREI1_MEMBASE_IMM:
3348 return OP_STOREI1_MEMBASE_REG;
3349 case OP_STOREI2_MEMBASE_IMM:
3350 return OP_STOREI2_MEMBASE_REG;
3351 case OP_STOREI4_MEMBASE_IMM:
3352 return OP_STOREI4_MEMBASE_REG;
3354 g_assert_not_reached ();
3358 * Remove from the instruction list the instructions that can't be
3359 * represented with very simple instructions with no register
3363 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3365 MonoInst *ins, *temp, *last_ins = NULL;
3366 int rot_amount, imm8, low_imm;
3368 MONO_BB_FOR_EACH_INS (bb, ins) {
3370 switch (ins->opcode) {
3374 case OP_COMPARE_IMM:
3375 case OP_ICOMPARE_IMM:
3389 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3390 ADD_NEW_INS (cfg, temp, OP_ICONST);
3391 temp->inst_c0 = ins->inst_imm;
3392 temp->dreg = mono_alloc_ireg (cfg);
3393 ins->sreg2 = temp->dreg;
3394 ins->opcode = mono_op_imm_to_op (ins->opcode);
3396 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3402 if (ins->inst_imm == 1) {
3403 ins->opcode = OP_MOVE;
3406 if (ins->inst_imm == 0) {
3407 ins->opcode = OP_ICONST;
3411 imm8 = mono_is_power_of_two (ins->inst_imm);
3413 ins->opcode = OP_SHL_IMM;
3414 ins->inst_imm = imm8;
3417 ADD_NEW_INS (cfg, temp, OP_ICONST);
3418 temp->inst_c0 = ins->inst_imm;
3419 temp->dreg = mono_alloc_ireg (cfg);
3420 ins->sreg2 = temp->dreg;
3421 ins->opcode = OP_IMUL;
3427 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3428 /* ARM sets the C flag to 1 if there was _no_ overflow */
3429 ins->next->opcode = OP_COND_EXC_NC;
3432 case OP_IDIV_UN_IMM:
3434 case OP_IREM_UN_IMM:
3435 ADD_NEW_INS (cfg, temp, OP_ICONST);
3436 temp->inst_c0 = ins->inst_imm;
3437 temp->dreg = mono_alloc_ireg (cfg);
3438 ins->sreg2 = temp->dreg;
3439 ins->opcode = mono_op_imm_to_op (ins->opcode);
3441 case OP_LOCALLOC_IMM:
3442 ADD_NEW_INS (cfg, temp, OP_ICONST);
3443 temp->inst_c0 = ins->inst_imm;
3444 temp->dreg = mono_alloc_ireg (cfg);
3445 ins->sreg1 = temp->dreg;
3446 ins->opcode = OP_LOCALLOC;
3448 case OP_LOAD_MEMBASE:
3449 case OP_LOADI4_MEMBASE:
3450 case OP_LOADU4_MEMBASE:
3451 case OP_LOADU1_MEMBASE:
3452 /* we can do two things: load the immed in a register
3453 * and use an indexed load, or see if the immed can be
3454 * represented as an ad_imm + a load with a smaller offset
3455 * that fits. We just do the first for now, optimize later.
3457 if (arm_is_imm12 (ins->inst_offset))
3459 ADD_NEW_INS (cfg, temp, OP_ICONST);
3460 temp->inst_c0 = ins->inst_offset;
3461 temp->dreg = mono_alloc_ireg (cfg);
3462 ins->sreg2 = temp->dreg;
3463 ins->opcode = map_to_reg_reg_op (ins->opcode);
3465 case OP_LOADI2_MEMBASE:
3466 case OP_LOADU2_MEMBASE:
3467 case OP_LOADI1_MEMBASE:
3468 if (arm_is_imm8 (ins->inst_offset))
3470 ADD_NEW_INS (cfg, temp, OP_ICONST);
3471 temp->inst_c0 = ins->inst_offset;
3472 temp->dreg = mono_alloc_ireg (cfg);
3473 ins->sreg2 = temp->dreg;
3474 ins->opcode = map_to_reg_reg_op (ins->opcode);
3476 case OP_LOADR4_MEMBASE:
3477 case OP_LOADR8_MEMBASE:
3478 if (arm_is_fpimm8 (ins->inst_offset))
3480 low_imm = ins->inst_offset & 0x1ff;
3481 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3482 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3483 temp->inst_imm = ins->inst_offset & ~0x1ff;
3484 temp->sreg1 = ins->inst_basereg;
3485 temp->dreg = mono_alloc_ireg (cfg);
3486 ins->inst_basereg = temp->dreg;
3487 ins->inst_offset = low_imm;
3491 ADD_NEW_INS (cfg, temp, OP_ICONST);
3492 temp->inst_c0 = ins->inst_offset;
3493 temp->dreg = mono_alloc_ireg (cfg);
3495 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3496 add_ins->sreg1 = ins->inst_basereg;
3497 add_ins->sreg2 = temp->dreg;
3498 add_ins->dreg = mono_alloc_ireg (cfg);
3500 ins->inst_basereg = add_ins->dreg;
3501 ins->inst_offset = 0;
3504 case OP_STORE_MEMBASE_REG:
3505 case OP_STOREI4_MEMBASE_REG:
3506 case OP_STOREI1_MEMBASE_REG:
3507 if (arm_is_imm12 (ins->inst_offset))
3509 ADD_NEW_INS (cfg, temp, OP_ICONST);
3510 temp->inst_c0 = ins->inst_offset;
3511 temp->dreg = mono_alloc_ireg (cfg);
3512 ins->sreg2 = temp->dreg;
3513 ins->opcode = map_to_reg_reg_op (ins->opcode);
3515 case OP_STOREI2_MEMBASE_REG:
3516 if (arm_is_imm8 (ins->inst_offset))
3518 ADD_NEW_INS (cfg, temp, OP_ICONST);
3519 temp->inst_c0 = ins->inst_offset;
3520 temp->dreg = mono_alloc_ireg (cfg);
3521 ins->sreg2 = temp->dreg;
3522 ins->opcode = map_to_reg_reg_op (ins->opcode);
3524 case OP_STORER4_MEMBASE_REG:
3525 case OP_STORER8_MEMBASE_REG:
3526 if (arm_is_fpimm8 (ins->inst_offset))
3528 low_imm = ins->inst_offset & 0x1ff;
3529 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3530 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3531 temp->inst_imm = ins->inst_offset & ~0x1ff;
3532 temp->sreg1 = ins->inst_destbasereg;
3533 temp->dreg = mono_alloc_ireg (cfg);
3534 ins->inst_destbasereg = temp->dreg;
3535 ins->inst_offset = low_imm;
3539 ADD_NEW_INS (cfg, temp, OP_ICONST);
3540 temp->inst_c0 = ins->inst_offset;
3541 temp->dreg = mono_alloc_ireg (cfg);
3543 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3544 add_ins->sreg1 = ins->inst_destbasereg;
3545 add_ins->sreg2 = temp->dreg;
3546 add_ins->dreg = mono_alloc_ireg (cfg);
3548 ins->inst_destbasereg = add_ins->dreg;
3549 ins->inst_offset = 0;
3552 case OP_STORE_MEMBASE_IMM:
3553 case OP_STOREI1_MEMBASE_IMM:
3554 case OP_STOREI2_MEMBASE_IMM:
3555 case OP_STOREI4_MEMBASE_IMM:
3556 ADD_NEW_INS (cfg, temp, OP_ICONST);
3557 temp->inst_c0 = ins->inst_imm;
3558 temp->dreg = mono_alloc_ireg (cfg);
3559 ins->sreg1 = temp->dreg;
3560 ins->opcode = map_to_reg_reg_op (ins->opcode);
3562 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3565 gboolean swap = FALSE;
3569 /* Optimized away */
3574 /* Some fp compares require swapped operands */
3575 switch (ins->next->opcode) {
3577 ins->next->opcode = OP_FBLT;
3581 ins->next->opcode = OP_FBLT_UN;
3585 ins->next->opcode = OP_FBGE;
3589 ins->next->opcode = OP_FBGE_UN;
3597 ins->sreg1 = ins->sreg2;
3606 bb->last_ins = last_ins;
3607 bb->max_vreg = cfg->next_vreg;
3611 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3615 if (long_ins->opcode == OP_LNEG) {
3617 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3618 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3624 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3626 /* sreg is a float, dreg is an integer reg */
3628 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3630 ARM_TOSIZD (code, vfp_scratch1, sreg);
3632 ARM_TOUIZD (code, vfp_scratch1, sreg);
3633 ARM_FMRS (code, dreg, vfp_scratch1);
3634 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3638 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3639 else if (size == 2) {
3640 ARM_SHL_IMM (code, dreg, dreg, 16);
3641 ARM_SHR_IMM (code, dreg, dreg, 16);
3645 ARM_SHL_IMM (code, dreg, dreg, 24);
3646 ARM_SAR_IMM (code, dreg, dreg, 24);
3647 } else if (size == 2) {
3648 ARM_SHL_IMM (code, dreg, dreg, 16);
3649 ARM_SAR_IMM (code, dreg, dreg, 16);
3656 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3658 /* sreg is a float, dreg is an integer reg */
3660 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3662 ARM_TOSIZS (code, vfp_scratch1, sreg);
3664 ARM_TOUIZS (code, vfp_scratch1, sreg);
3665 ARM_FMRS (code, dreg, vfp_scratch1);
3666 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3670 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3671 else if (size == 2) {
3672 ARM_SHL_IMM (code, dreg, dreg, 16);
3673 ARM_SHR_IMM (code, dreg, dreg, 16);
3677 ARM_SHL_IMM (code, dreg, dreg, 24);
3678 ARM_SAR_IMM (code, dreg, dreg, 24);
3679 } else if (size == 2) {
3680 ARM_SHL_IMM (code, dreg, dreg, 16);
3681 ARM_SAR_IMM (code, dreg, dreg, 16);
3687 #endif /* #ifndef DISABLE_JIT */
3689 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3692 emit_thunk (guint8 *code, gconstpointer target)
3696 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3697 if (thumb_supported)
3698 ARM_BX (code, ARMREG_IP);
3700 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3701 *(guint32*)code = (guint32)target;
3703 mono_arch_flush_icache (p, code - p);
3707 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3709 MonoJitInfo *ji = NULL;
3710 MonoThunkJitInfo *info;
3713 guint8 *orig_target;
3714 guint8 *target_thunk;
3717 domain = mono_domain_get ();
3721 * This can be called multiple times during JITting,
3722 * save the current position in cfg->arch to avoid
3723 * doing a O(n^2) search.
3725 if (!cfg->arch.thunks) {
3726 cfg->arch.thunks = cfg->thunks;
3727 cfg->arch.thunks_size = cfg->thunk_area;
3729 thunks = cfg->arch.thunks;
3730 thunks_size = cfg->arch.thunks_size;
3732 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3733 g_assert_not_reached ();
3736 g_assert (*(guint32*)thunks == 0);
3737 emit_thunk (thunks, target);
3738 arm_patch (code, thunks);
3740 cfg->arch.thunks += THUNK_SIZE;
3741 cfg->arch.thunks_size -= THUNK_SIZE;
3743 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3745 info = mono_jit_info_get_thunk_info (ji);
3748 thunks = (guint8*)ji->code_start + info->thunks_offset;
3749 thunks_size = info->thunks_size;
3751 orig_target = mono_arch_get_call_target (code + 4);
3753 mono_mini_arch_lock ();
3755 target_thunk = NULL;
3756 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3757 /* The call already points to a thunk, because of trampolines etc. */
3758 target_thunk = orig_target;
3760 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3761 if (((guint32*)p) [0] == 0) {
3769 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
3771 if (!target_thunk) {
3772 mono_mini_arch_unlock ();
3773 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3774 g_assert_not_reached ();
3777 emit_thunk (target_thunk, target);
3778 arm_patch (code, target_thunk);
3779 mono_arch_flush_icache (code, 4);
3781 mono_mini_arch_unlock ();
3786 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3788 guint32 *code32 = (void*)code;
3789 guint32 ins = *code32;
3790 guint32 prim = (ins >> 25) & 7;
3791 guint32 tval = GPOINTER_TO_UINT (target);
3793 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3794 if (prim == 5) { /* 101b */
3795 /* the diff starts 8 bytes from the branch opcode */
3796 gint diff = target - code - 8;
3798 gint tmask = 0xffffffff;
3799 if (tval & 1) { /* entering thumb mode */
3800 diff = target - 1 - code - 8;
3801 g_assert (thumb_supported);
3802 tbits = 0xf << 28; /* bl->blx bit pattern */
3803 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3804 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3808 tmask = ~(1 << 24); /* clear the link bit */
3809 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3814 if (diff <= 33554431) {
3816 ins = (ins & 0xff000000) | diff;
3818 *code32 = ins | tbits;
3822 /* diff between 0 and -33554432 */
3823 if (diff >= -33554432) {
3825 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3827 *code32 = ins | tbits;
3832 handle_thunk (cfg, domain, code, target);
3836 #ifdef USE_JUMP_TABLES
3838 gpointer *jte = mono_jumptable_get_entry (code);
3840 jte [0] = (gpointer) target;
3844 * The alternative call sequences looks like this:
3846 * ldr ip, [pc] // loads the address constant
3847 * b 1f // jumps around the constant
3848 * address constant embedded in the code
3853 * There are two cases for patching:
3854 * a) at the end of method emission: in this case code points to the start
3855 * of the call sequence
3856 * b) during runtime patching of the call site: in this case code points
3857 * to the mov pc, ip instruction
3859 * We have to handle also the thunk jump code sequence:
3863 * address constant // execution never reaches here
3865 if ((ins & 0x0ffffff0) == 0x12fff10) {
3866 /* Branch and exchange: the address is constructed in a reg
3867 * We can patch BX when the code sequence is the following:
3868 * ldr ip, [pc, #0] ; 0x8
3875 guint8 *emit = (guint8*)ccode;
3876 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3878 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3879 ARM_BX (emit, ARMREG_IP);
3881 /*patching from magic trampoline*/
3882 if (ins == ccode [3]) {
3883 g_assert (code32 [-4] == ccode [0]);
3884 g_assert (code32 [-3] == ccode [1]);
3885 g_assert (code32 [-1] == ccode [2]);
3886 code32 [-2] = (guint32)target;
3889 /*patching from JIT*/
3890 if (ins == ccode [0]) {
3891 g_assert (code32 [1] == ccode [1]);
3892 g_assert (code32 [3] == ccode [2]);
3893 g_assert (code32 [4] == ccode [3]);
3894 code32 [2] = (guint32)target;
3897 g_assert_not_reached ();
3898 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3906 guint8 *emit = (guint8*)ccode;
3907 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3909 ARM_BLX_REG (emit, ARMREG_IP);
3911 g_assert (code32 [-3] == ccode [0]);
3912 g_assert (code32 [-2] == ccode [1]);
3913 g_assert (code32 [0] == ccode [2]);
3915 code32 [-1] = (guint32)target;
3918 guint32 *tmp = ccode;
3919 guint8 *emit = (guint8*)tmp;
3920 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3921 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3922 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3923 ARM_BX (emit, ARMREG_IP);
3924 if (ins == ccode [2]) {
3925 g_assert_not_reached (); // should be -2 ...
3926 code32 [-1] = (guint32)target;
3929 if (ins == ccode [0]) {
3930 /* handles both thunk jump code and the far call sequence */
3931 code32 [2] = (guint32)target;
3934 g_assert_not_reached ();
3936 // g_print ("patched with 0x%08x\n", ins);
3941 arm_patch (guchar *code, const guchar *target)
3943 arm_patch_general (NULL, NULL, code, target);
3947 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3948 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3949 * to be used with the emit macros.
3950 * Return -1 otherwise.
3953 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3956 for (i = 0; i < 31; i+= 2) {
3957 res = (val << (32 - i)) | (val >> i);
3960 *rot_amount = i? 32 - i: 0;
3967 * Emits in code a sequence of instructions that load the value 'val'
3968 * into the dreg register. Uses at most 4 instructions.
3971 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3973 int imm8, rot_amount;
3975 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3976 /* skip the constant pool */
3982 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3983 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3984 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3985 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3988 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3990 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3994 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3996 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3998 if (val & 0xFF0000) {
3999 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4001 if (val & 0xFF000000) {
4002 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4004 } else if (val & 0xFF00) {
4005 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4006 if (val & 0xFF0000) {
4007 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4009 if (val & 0xFF000000) {
4010 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4012 } else if (val & 0xFF0000) {
4013 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4014 if (val & 0xFF000000) {
4015 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4018 //g_assert_not_reached ();
4024 mono_arm_thumb_supported (void)
4026 return thumb_supported;
4032 * emit_load_volatile_arguments:
4034 * Load volatile arguments from the stack to the original input registers.
4035 * Required before a tail call.
4038 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
4040 MonoMethod *method = cfg->method;
4041 MonoMethodSignature *sig;
4046 /* FIXME: Generate intermediate code instead */
4048 sig = mono_method_signature (method);
4050 /* This is the opposite of the code in emit_prolog */
4054 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
4056 if (cinfo->ret.storage == RegTypeStructByAddr) {
4057 ArgInfo *ainfo = &cinfo->ret;
4058 inst = cfg->vret_addr;
4059 g_assert (arm_is_imm12 (inst->inst_offset));
4060 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4062 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4063 ArgInfo *ainfo = cinfo->args + i;
4064 inst = cfg->args [pos];
4066 if (cfg->verbose_level > 2)
4067 g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
4068 if (inst->opcode == OP_REGVAR) {
4069 if (ainfo->storage == RegTypeGeneral)
4070 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
4071 else if (ainfo->storage == RegTypeFP) {
4072 g_assert_not_reached ();
4073 } else if (ainfo->storage == RegTypeBase) {
4077 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
4078 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4080 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4081 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
4085 g_assert_not_reached ();
4087 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
4088 switch (ainfo->size) {
4095 g_assert (arm_is_imm12 (inst->inst_offset));
4096 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4097 g_assert (arm_is_imm12 (inst->inst_offset + 4));
4098 ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
4101 if (arm_is_imm12 (inst->inst_offset)) {
4102 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4104 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4105 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4109 } else if (ainfo->storage == RegTypeBaseGen) {
4112 } else if (ainfo->storage == RegTypeBase) {
4114 } else if (ainfo->storage == RegTypeFP) {
4115 g_assert_not_reached ();
4116 } else if (ainfo->storage == RegTypeStructByVal) {
4117 int doffset = inst->inst_offset;
4121 if (mono_class_from_mono_type (inst->inst_vtype))
4122 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
4123 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
4124 if (arm_is_imm12 (doffset)) {
4125 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
4127 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
4128 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
4130 soffset += sizeof (gpointer);
4131 doffset += sizeof (gpointer);
4136 } else if (ainfo->storage == RegTypeStructByAddr) {
4151 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4156 call = (MonoCallInst*)ins;
4157 cinfo = call->call_info;
4159 switch (cinfo->ret.storage) {
4161 MonoInst *loc = cfg->arch.vret_addr_loc;
4164 /* Load the destination address */
4165 g_assert (loc && loc->opcode == OP_REGOFFSET);
4167 if (arm_is_imm12 (loc->inst_offset)) {
4168 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4170 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4171 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4173 for (i = 0; i < cinfo->ret.nregs; ++i) {
4174 if (cinfo->ret.esize == 4)
4175 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4177 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4185 switch (ins->opcode) {
4188 case OP_FCALL_MEMBASE:
4190 MonoType *sig_ret = mini_type_get_underlying_type (NULL, ((MonoCallInst*)ins)->signature->ret);
4191 if (sig_ret->type == MONO_TYPE_R4) {
4192 if (IS_HARD_FLOAT) {
4193 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4195 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4196 ARM_CVTS (code, ins->dreg, ins->dreg);
4199 if (IS_HARD_FLOAT) {
4200 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4202 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4209 case OP_RCALL_MEMBASE: {
4214 sig_ret = mini_type_get_underlying_type (NULL, ((MonoCallInst*)ins)->signature->ret);
4215 g_assert (sig_ret->type == MONO_TYPE_R4);
4216 if (IS_HARD_FLOAT) {
4217 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4219 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4220 ARM_CPYS (code, ins->dreg, ins->dreg);
4232 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4237 guint8 *code = cfg->native_code + cfg->code_len;
4238 MonoInst *last_ins = NULL;
4239 guint last_offset = 0;
4241 int imm8, rot_amount;
4243 /* we don't align basic blocks of loops on arm */
4245 if (cfg->verbose_level > 2)
4246 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4248 cpos = bb->max_offset;
4250 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4251 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4252 //g_assert (!mono_compile_aot);
4255 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4256 /* this is not thread save, but good enough */
4257 /* fixme: howto handle overflows? */
4258 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4261 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4262 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4263 (gpointer)"mono_break");
4264 code = emit_call_seq (cfg, code);
4267 MONO_BB_FOR_EACH_INS (bb, ins) {
4268 offset = code - cfg->native_code;
4270 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4272 if (offset > (cfg->code_size - max_len - 16)) {
4273 cfg->code_size *= 2;
4274 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4275 code = cfg->native_code + offset;
4277 // if (ins->cil_code)
4278 // g_print ("cil code\n");
4279 mono_debug_record_line_number (cfg, ins, offset);
4281 switch (ins->opcode) {
4282 case OP_MEMORY_BARRIER:
4284 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4285 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4289 #ifdef HAVE_AEABI_READ_TP
4290 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4291 (gpointer)"__aeabi_read_tp");
4292 code = emit_call_seq (cfg, code);
4294 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
4296 g_assert_not_reached ();
4299 case OP_ATOMIC_EXCHANGE_I4:
4300 case OP_ATOMIC_CAS_I4:
4301 case OP_ATOMIC_ADD_I4: {
4305 g_assert (v7_supported);
4308 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4310 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4312 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4316 g_assert (cfg->arch.atomic_tmp_offset != -1);
4317 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4319 switch (ins->opcode) {
4320 case OP_ATOMIC_EXCHANGE_I4:
4322 ARM_DMB (code, ARM_DMB_SY);
4323 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4324 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4325 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4327 ARM_B_COND (code, ARMCOND_NE, 0);
4328 arm_patch (buf [1], buf [0]);
4330 case OP_ATOMIC_CAS_I4:
4331 ARM_DMB (code, ARM_DMB_SY);
4333 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4334 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4336 ARM_B_COND (code, ARMCOND_NE, 0);
4337 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4338 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4340 ARM_B_COND (code, ARMCOND_NE, 0);
4341 arm_patch (buf [2], buf [0]);
4342 arm_patch (buf [1], code);
4344 case OP_ATOMIC_ADD_I4:
4346 ARM_DMB (code, ARM_DMB_SY);
4347 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4348 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4349 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4350 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4352 ARM_B_COND (code, ARMCOND_NE, 0);
4353 arm_patch (buf [1], buf [0]);
4356 g_assert_not_reached ();
4359 ARM_DMB (code, ARM_DMB_SY);
4360 if (tmpreg != ins->dreg)
4361 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4362 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4365 case OP_ATOMIC_LOAD_I1:
4366 case OP_ATOMIC_LOAD_U1:
4367 case OP_ATOMIC_LOAD_I2:
4368 case OP_ATOMIC_LOAD_U2:
4369 case OP_ATOMIC_LOAD_I4:
4370 case OP_ATOMIC_LOAD_U4:
4371 case OP_ATOMIC_LOAD_R4:
4372 case OP_ATOMIC_LOAD_R8: {
4373 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4374 ARM_DMB (code, ARM_DMB_SY);
4376 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4378 switch (ins->opcode) {
4379 case OP_ATOMIC_LOAD_I1:
4380 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4382 case OP_ATOMIC_LOAD_U1:
4383 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4385 case OP_ATOMIC_LOAD_I2:
4386 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4388 case OP_ATOMIC_LOAD_U2:
4389 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4391 case OP_ATOMIC_LOAD_I4:
4392 case OP_ATOMIC_LOAD_U4:
4393 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4395 case OP_ATOMIC_LOAD_R4:
4396 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4397 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4398 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4399 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4400 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4402 case OP_ATOMIC_LOAD_R8:
4403 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4404 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4408 ARM_DMB (code, ARM_DMB_SY);
4411 case OP_ATOMIC_STORE_I1:
4412 case OP_ATOMIC_STORE_U1:
4413 case OP_ATOMIC_STORE_I2:
4414 case OP_ATOMIC_STORE_U2:
4415 case OP_ATOMIC_STORE_I4:
4416 case OP_ATOMIC_STORE_U4:
4417 case OP_ATOMIC_STORE_R4:
4418 case OP_ATOMIC_STORE_R8: {
4419 ARM_DMB (code, ARM_DMB_SY);
4421 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4423 switch (ins->opcode) {
4424 case OP_ATOMIC_STORE_I1:
4425 case OP_ATOMIC_STORE_U1:
4426 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4428 case OP_ATOMIC_STORE_I2:
4429 case OP_ATOMIC_STORE_U2:
4430 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4432 case OP_ATOMIC_STORE_I4:
4433 case OP_ATOMIC_STORE_U4:
4434 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4436 case OP_ATOMIC_STORE_R4:
4437 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4438 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4439 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4440 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4441 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4443 case OP_ATOMIC_STORE_R8:
4444 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4445 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4449 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4450 ARM_DMB (code, ARM_DMB_SY);
4454 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4455 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4458 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4459 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4461 case OP_STOREI1_MEMBASE_IMM:
4462 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4463 g_assert (arm_is_imm12 (ins->inst_offset));
4464 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4466 case OP_STOREI2_MEMBASE_IMM:
4467 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4468 g_assert (arm_is_imm8 (ins->inst_offset));
4469 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4471 case OP_STORE_MEMBASE_IMM:
4472 case OP_STOREI4_MEMBASE_IMM:
4473 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4474 g_assert (arm_is_imm12 (ins->inst_offset));
4475 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4477 case OP_STOREI1_MEMBASE_REG:
4478 g_assert (arm_is_imm12 (ins->inst_offset));
4479 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4481 case OP_STOREI2_MEMBASE_REG:
4482 g_assert (arm_is_imm8 (ins->inst_offset));
4483 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4485 case OP_STORE_MEMBASE_REG:
4486 case OP_STOREI4_MEMBASE_REG:
4487 /* this case is special, since it happens for spill code after lowering has been called */
4488 if (arm_is_imm12 (ins->inst_offset)) {
4489 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4491 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4492 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4495 case OP_STOREI1_MEMINDEX:
4496 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4498 case OP_STOREI2_MEMINDEX:
4499 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4501 case OP_STORE_MEMINDEX:
4502 case OP_STOREI4_MEMINDEX:
4503 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4506 g_assert_not_reached ();
4508 case OP_LOAD_MEMINDEX:
4509 case OP_LOADI4_MEMINDEX:
4510 case OP_LOADU4_MEMINDEX:
4511 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4513 case OP_LOADI1_MEMINDEX:
4514 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4516 case OP_LOADU1_MEMINDEX:
4517 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4519 case OP_LOADI2_MEMINDEX:
4520 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4522 case OP_LOADU2_MEMINDEX:
4523 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4525 case OP_LOAD_MEMBASE:
4526 case OP_LOADI4_MEMBASE:
4527 case OP_LOADU4_MEMBASE:
4528 /* this case is special, since it happens for spill code after lowering has been called */
4529 if (arm_is_imm12 (ins->inst_offset)) {
4530 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4532 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4533 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4536 case OP_LOADI1_MEMBASE:
4537 g_assert (arm_is_imm8 (ins->inst_offset));
4538 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4540 case OP_LOADU1_MEMBASE:
4541 g_assert (arm_is_imm12 (ins->inst_offset));
4542 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4544 case OP_LOADU2_MEMBASE:
4545 g_assert (arm_is_imm8 (ins->inst_offset));
4546 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4548 case OP_LOADI2_MEMBASE:
4549 g_assert (arm_is_imm8 (ins->inst_offset));
4550 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4552 case OP_ICONV_TO_I1:
4553 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4554 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4556 case OP_ICONV_TO_I2:
4557 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4558 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4560 case OP_ICONV_TO_U1:
4561 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4563 case OP_ICONV_TO_U2:
4564 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4565 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4569 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4571 case OP_COMPARE_IMM:
4572 case OP_ICOMPARE_IMM:
4573 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4574 g_assert (imm8 >= 0);
4575 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4579 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4580 * So instead of emitting a trap, we emit a call a C function and place a
4583 //*(int*)code = 0xef9f0001;
4586 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4587 (gpointer)"mono_break");
4588 code = emit_call_seq (cfg, code);
4590 case OP_RELAXED_NOP:
4595 case OP_DUMMY_STORE:
4596 case OP_DUMMY_ICONST:
4597 case OP_DUMMY_R8CONST:
4598 case OP_NOT_REACHED:
4601 case OP_IL_SEQ_POINT:
4602 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4604 case OP_SEQ_POINT: {
4606 MonoInst *info_var = cfg->arch.seq_point_info_var;
4607 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4608 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
4609 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4610 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4612 int dreg = ARMREG_LR;
4614 if (cfg->soft_breakpoints) {
4615 g_assert (!cfg->compile_aot);
4619 * For AOT, we use one got slot per method, which will point to a
4620 * SeqPointInfo structure, containing all the information required
4621 * by the code below.
4623 if (cfg->compile_aot) {
4624 g_assert (info_var);
4625 g_assert (info_var->opcode == OP_REGOFFSET);
4626 g_assert (arm_is_imm12 (info_var->inst_offset));
4629 if (!cfg->soft_breakpoints) {
4631 * Read from the single stepping trigger page. This will cause a
4632 * SIGSEGV when single stepping is enabled.
4633 * We do this _before_ the breakpoint, so single stepping after
4634 * a breakpoint is hit will step to the next IL offset.
4636 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4639 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4640 if (cfg->soft_breakpoints) {
4641 /* Load the address of the sequence point trigger variable. */
4644 g_assert (var->opcode == OP_REGOFFSET);
4645 g_assert (arm_is_imm12 (var->inst_offset));
4646 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4648 /* Read the value and check whether it is non-zero. */
4649 ARM_LDR_IMM (code, dreg, dreg, 0);
4650 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4652 /* Load the address of the sequence point method. */
4653 var = ss_method_var;
4655 g_assert (var->opcode == OP_REGOFFSET);
4656 g_assert (arm_is_imm12 (var->inst_offset));
4657 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4659 /* Call it conditionally. */
4660 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4662 if (cfg->compile_aot) {
4663 /* Load the trigger page addr from the variable initialized in the prolog */
4664 var = ss_trigger_page_var;
4666 g_assert (var->opcode == OP_REGOFFSET);
4667 g_assert (arm_is_imm12 (var->inst_offset));
4668 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4670 #ifdef USE_JUMP_TABLES
4671 gpointer *jte = mono_jumptable_add_entry ();
4672 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4673 jte [0] = ss_trigger_page;
4675 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4677 *(int*)code = (int)ss_trigger_page;
4681 ARM_LDR_IMM (code, dreg, dreg, 0);
4685 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4687 if (cfg->soft_breakpoints) {
4688 /* Load the address of the breakpoint method into ip. */
4689 var = bp_method_var;
4691 g_assert (var->opcode == OP_REGOFFSET);
4692 g_assert (arm_is_imm12 (var->inst_offset));
4693 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4696 * A placeholder for a possible breakpoint inserted by
4697 * mono_arch_set_breakpoint ().
4700 } else if (cfg->compile_aot) {
4701 guint32 offset = code - cfg->native_code;
4704 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4705 /* Add the offset */
4706 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4707 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4708 if (arm_is_imm12 ((int)val)) {
4709 ARM_LDR_IMM (code, dreg, dreg, val);
4711 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4713 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4715 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4716 g_assert (!(val & 0xFF000000));
4718 ARM_LDR_IMM (code, dreg, dreg, 0);
4720 /* What is faster, a branch or a load ? */
4721 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4722 /* The breakpoint instruction */
4723 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4726 * A placeholder for a possible breakpoint inserted by
4727 * mono_arch_set_breakpoint ().
4729 for (i = 0; i < 4; ++i)
4736 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4739 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4743 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4746 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4747 g_assert (imm8 >= 0);
4748 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4752 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4753 g_assert (imm8 >= 0);
4754 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4758 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4759 g_assert (imm8 >= 0);
4760 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4763 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4764 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4766 case OP_IADD_OVF_UN:
4767 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4768 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4771 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4772 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4774 case OP_ISUB_OVF_UN:
4775 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4776 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4778 case OP_ADD_OVF_CARRY:
4779 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4780 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4782 case OP_ADD_OVF_UN_CARRY:
4783 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4784 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4786 case OP_SUB_OVF_CARRY:
4787 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4788 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4790 case OP_SUB_OVF_UN_CARRY:
4791 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4792 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4796 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4799 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4800 g_assert (imm8 >= 0);
4801 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4804 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4808 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4812 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4813 g_assert (imm8 >= 0);
4814 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4818 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4819 g_assert (imm8 >= 0);
4820 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4822 case OP_ARM_RSBS_IMM:
4823 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4824 g_assert (imm8 >= 0);
4825 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4827 case OP_ARM_RSC_IMM:
4828 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4829 g_assert (imm8 >= 0);
4830 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4833 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4837 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4838 g_assert (imm8 >= 0);
4839 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4842 g_assert (v7s_supported);
4843 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4846 g_assert (v7s_supported);
4847 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4850 g_assert (v7s_supported);
4851 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4852 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4855 g_assert (v7s_supported);
4856 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4857 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4861 g_assert_not_reached ();
4863 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4867 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4868 g_assert (imm8 >= 0);
4869 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4872 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4876 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4877 g_assert (imm8 >= 0);
4878 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4881 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4886 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4887 else if (ins->dreg != ins->sreg1)
4888 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4891 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4896 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4897 else if (ins->dreg != ins->sreg1)
4898 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4901 case OP_ISHR_UN_IMM:
4903 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4904 else if (ins->dreg != ins->sreg1)
4905 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4908 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4911 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4914 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4917 if (ins->dreg == ins->sreg2)
4918 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4920 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4923 g_assert_not_reached ();
4926 /* FIXME: handle ovf/ sreg2 != dreg */
4927 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4928 /* FIXME: MUL doesn't set the C/O flags on ARM */
4930 case OP_IMUL_OVF_UN:
4931 /* FIXME: handle ovf/ sreg2 != dreg */
4932 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4933 /* FIXME: MUL doesn't set the C/O flags on ARM */
4936 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4939 /* Load the GOT offset */
4940 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4941 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4943 *(gpointer*)code = NULL;
4945 /* Load the value from the GOT */
4946 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4948 case OP_OBJC_GET_SELECTOR:
4949 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4950 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4952 *(gpointer*)code = NULL;
4954 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4956 case OP_ICONV_TO_I4:
4957 case OP_ICONV_TO_U4:
4959 if (ins->dreg != ins->sreg1)
4960 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4963 int saved = ins->sreg2;
4964 if (ins->sreg2 == ARM_LSW_REG) {
4965 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4968 if (ins->sreg1 != ARM_LSW_REG)
4969 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4970 if (saved != ARM_MSW_REG)
4971 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4975 if (IS_VFP && ins->dreg != ins->sreg1)
4976 ARM_CPYD (code, ins->dreg, ins->sreg1);
4978 case OP_MOVE_F_TO_I4:
4979 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4980 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4981 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4982 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4984 case OP_MOVE_I4_TO_F:
4985 ARM_FMSR (code, ins->dreg, ins->sreg1);
4986 ARM_CVTS (code, ins->dreg, ins->dreg);
4988 case OP_FCONV_TO_R4:
4991 ARM_CVTD (code, ins->dreg, ins->sreg1);
4993 ARM_CVTD (code, ins->dreg, ins->sreg1);
4994 ARM_CVTS (code, ins->dreg, ins->dreg);
5000 * Keep in sync with mono_arch_emit_epilog
5002 g_assert (!cfg->method->save_lmf);
5004 code = emit_load_volatile_arguments (cfg, code);
5006 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5008 if (cfg->used_int_regs)
5009 ARM_POP (code, cfg->used_int_regs);
5010 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5012 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5014 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
5015 if (cfg->compile_aot) {
5016 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5018 *(gpointer*)code = NULL;
5020 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5022 code = mono_arm_patchable_b (code, ARMCOND_AL);
5026 MonoCallInst *call = (MonoCallInst*)ins;
5029 * The stack looks like the following:
5030 * <caller argument area>
5033 * <callee argument area>
5034 * Need to copy the arguments from the callee argument area to
5035 * the caller argument area, and pop the frame.
5037 if (call->stack_usage) {
5038 int i, prev_sp_offset = 0;
5040 /* Compute size of saved registers restored below */
5042 prev_sp_offset = 2 * 4;
5044 prev_sp_offset = 1 * 4;
5045 for (i = 0; i < 16; ++i) {
5046 if (cfg->used_int_regs & (1 << i))
5047 prev_sp_offset += 4;
5050 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5052 /* Copy arguments on the stack to our argument area */
5053 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5054 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5055 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5060 * Keep in sync with mono_arch_emit_epilog
5062 g_assert (!cfg->method->save_lmf);
5064 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5066 if (cfg->used_int_regs)
5067 ARM_POP (code, cfg->used_int_regs);
5068 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5070 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5073 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5074 if (cfg->compile_aot) {
5075 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5077 *(gpointer*)code = NULL;
5079 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5081 code = mono_arm_patchable_b (code, ARMCOND_AL);
5086 /* ensure ins->sreg1 is not NULL */
5087 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5090 g_assert (cfg->sig_cookie < 128);
5091 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5092 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5102 call = (MonoCallInst*)ins;
5105 code = emit_float_args (cfg, call, code, &max_len, &offset);
5107 if (ins->flags & MONO_INST_HAS_METHOD)
5108 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5110 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5111 code = emit_call_seq (cfg, code);
5112 ins->flags |= MONO_INST_GC_CALLSITE;
5113 ins->backend.pc_offset = code - cfg->native_code;
5114 code = emit_move_return_value (cfg, ins, code);
5121 case OP_VOIDCALL_REG:
5124 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5126 code = emit_call_reg (code, ins->sreg1);
5127 ins->flags |= MONO_INST_GC_CALLSITE;
5128 ins->backend.pc_offset = code - cfg->native_code;
5129 code = emit_move_return_value (cfg, ins, code);
5131 case OP_FCALL_MEMBASE:
5132 case OP_RCALL_MEMBASE:
5133 case OP_LCALL_MEMBASE:
5134 case OP_VCALL_MEMBASE:
5135 case OP_VCALL2_MEMBASE:
5136 case OP_VOIDCALL_MEMBASE:
5137 case OP_CALL_MEMBASE: {
5138 g_assert (ins->sreg1 != ARMREG_LR);
5139 call = (MonoCallInst*)ins;
5142 code = emit_float_args (cfg, call, code, &max_len, &offset);
5143 if (!arm_is_imm12 (ins->inst_offset))
5144 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5145 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5146 if (!arm_is_imm12 (ins->inst_offset))
5147 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5149 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5150 ins->flags |= MONO_INST_GC_CALLSITE;
5151 ins->backend.pc_offset = code - cfg->native_code;
5152 code = emit_move_return_value (cfg, ins, code);
5156 /* round the size to 8 bytes */
5157 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
5158 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
5159 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5160 /* memzero the area: dreg holds the size, sp is the pointer */
5161 if (ins->flags & MONO_INST_INIT) {
5162 guint8 *start_loop, *branch_to_cond;
5163 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5164 branch_to_cond = code;
5167 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5168 arm_patch (branch_to_cond, code);
5169 /* decrement by 4 and set flags */
5170 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5171 ARM_B_COND (code, ARMCOND_GE, 0);
5172 arm_patch (code - 4, start_loop);
5174 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5175 if (cfg->param_area)
5176 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5181 MonoInst *var = cfg->dyn_call_var;
5183 g_assert (var->opcode == OP_REGOFFSET);
5184 g_assert (arm_is_imm12 (var->inst_offset));
5186 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5187 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5189 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5191 /* Save args buffer */
5192 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5194 /* Set stack slots using R0 as scratch reg */
5195 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5196 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5197 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5198 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5201 /* Set argument registers */
5202 for (i = 0; i < PARAM_REGS; ++i)
5203 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5206 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5207 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5210 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5211 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5212 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5216 if (ins->sreg1 != ARMREG_R0)
5217 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5218 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5219 (gpointer)"mono_arch_throw_exception");
5220 code = emit_call_seq (cfg, code);
5224 if (ins->sreg1 != ARMREG_R0)
5225 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5226 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5227 (gpointer)"mono_arch_rethrow_exception");
5228 code = emit_call_seq (cfg, code);
5231 case OP_START_HANDLER: {
5232 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5235 /* Reserve a param area, see filter-stack.exe */
5236 if (cfg->param_area) {
5237 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5238 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5240 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5241 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5245 if (arm_is_imm12 (spvar->inst_offset)) {
5246 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5248 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5249 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5253 case OP_ENDFILTER: {
5254 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5257 /* Free the param area */
5258 if (cfg->param_area) {
5259 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5260 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5262 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5263 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5267 if (ins->sreg1 != ARMREG_R0)
5268 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5269 if (arm_is_imm12 (spvar->inst_offset)) {
5270 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5272 g_assert (ARMREG_IP != spvar->inst_basereg);
5273 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5274 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5276 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5279 case OP_ENDFINALLY: {
5280 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5283 /* Free the param area */
5284 if (cfg->param_area) {
5285 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5286 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5288 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5289 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5293 if (arm_is_imm12 (spvar->inst_offset)) {
5294 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5296 g_assert (ARMREG_IP != spvar->inst_basereg);
5297 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5298 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5300 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5303 case OP_CALL_HANDLER:
5304 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5305 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5306 cfg->thunk_area += THUNK_SIZE;
5307 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5310 if (ins->dreg != ARMREG_R0)
5311 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5315 ins->inst_c0 = code - cfg->native_code;
5318 /*if (ins->inst_target_bb->native_offset) {
5320 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5322 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5323 code = mono_arm_patchable_b (code, ARMCOND_AL);
5327 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5331 * In the normal case we have:
5332 * ldr pc, [pc, ins->sreg1 << 2]
5335 * ldr lr, [pc, ins->sreg1 << 2]
5337 * After follows the data.
5338 * FIXME: add aot support.
5340 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5341 #ifdef USE_JUMP_TABLES
5343 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5344 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5345 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5349 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5350 if (offset + max_len > (cfg->code_size - 16)) {
5351 cfg->code_size += max_len;
5352 cfg->code_size *= 2;
5353 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5354 code = cfg->native_code + offset;
5356 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5358 code += 4 * GPOINTER_TO_INT (ins->klass);
5363 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5364 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5368 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5369 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5373 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5374 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5378 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5379 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5383 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5384 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5387 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5388 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5391 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5392 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5395 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5396 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5399 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5400 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5403 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5404 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5406 case OP_COND_EXC_EQ:
5407 case OP_COND_EXC_NE_UN:
5408 case OP_COND_EXC_LT:
5409 case OP_COND_EXC_LT_UN:
5410 case OP_COND_EXC_GT:
5411 case OP_COND_EXC_GT_UN:
5412 case OP_COND_EXC_GE:
5413 case OP_COND_EXC_GE_UN:
5414 case OP_COND_EXC_LE:
5415 case OP_COND_EXC_LE_UN:
5416 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5418 case OP_COND_EXC_IEQ:
5419 case OP_COND_EXC_INE_UN:
5420 case OP_COND_EXC_ILT:
5421 case OP_COND_EXC_ILT_UN:
5422 case OP_COND_EXC_IGT:
5423 case OP_COND_EXC_IGT_UN:
5424 case OP_COND_EXC_IGE:
5425 case OP_COND_EXC_IGE_UN:
5426 case OP_COND_EXC_ILE:
5427 case OP_COND_EXC_ILE_UN:
5428 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5431 case OP_COND_EXC_IC:
5432 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5434 case OP_COND_EXC_OV:
5435 case OP_COND_EXC_IOV:
5436 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5438 case OP_COND_EXC_NC:
5439 case OP_COND_EXC_INC:
5440 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5442 case OP_COND_EXC_NO:
5443 case OP_COND_EXC_INO:
5444 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5456 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5459 /* floating point opcodes */
5461 if (cfg->compile_aot) {
5462 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5464 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5466 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5469 /* FIXME: we can optimize the imm load by dealing with part of
5470 * the displacement in LDFD (aligning to 512).
5472 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5473 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5477 if (cfg->compile_aot) {
5478 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5480 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5483 ARM_CVTS (code, ins->dreg, ins->dreg);
5485 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5486 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5488 ARM_CVTS (code, ins->dreg, ins->dreg);
5491 case OP_STORER8_MEMBASE_REG:
5492 /* This is generated by the local regalloc pass which runs after the lowering pass */
5493 if (!arm_is_fpimm8 (ins->inst_offset)) {
5494 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5495 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5496 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5498 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5501 case OP_LOADR8_MEMBASE:
5502 /* This is generated by the local regalloc pass which runs after the lowering pass */
5503 if (!arm_is_fpimm8 (ins->inst_offset)) {
5504 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5505 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5506 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5508 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5511 case OP_STORER4_MEMBASE_REG:
5512 g_assert (arm_is_fpimm8 (ins->inst_offset));
5514 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5516 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5517 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5518 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5519 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5522 case OP_LOADR4_MEMBASE:
5524 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5526 g_assert (arm_is_fpimm8 (ins->inst_offset));
5527 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5528 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5529 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5530 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5533 case OP_ICONV_TO_R_UN: {
5534 g_assert_not_reached ();
5537 case OP_ICONV_TO_R4:
5539 ARM_FMSR (code, ins->dreg, ins->sreg1);
5540 ARM_FSITOS (code, ins->dreg, ins->dreg);
5542 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5543 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5544 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5545 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5546 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5549 case OP_ICONV_TO_R8:
5550 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5551 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5552 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5553 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5557 MonoType *sig_ret = mini_type_get_underlying_type (NULL, mono_method_signature (cfg->method)->ret);
5558 if (sig_ret->type == MONO_TYPE_R4) {
5560 g_assert (!IS_HARD_FLOAT);
5561 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5563 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5566 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5570 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5572 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5576 case OP_FCONV_TO_I1:
5577 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5579 case OP_FCONV_TO_U1:
5580 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5582 case OP_FCONV_TO_I2:
5583 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5585 case OP_FCONV_TO_U2:
5586 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5588 case OP_FCONV_TO_I4:
5590 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5592 case OP_FCONV_TO_U4:
5594 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5596 case OP_FCONV_TO_I8:
5597 case OP_FCONV_TO_U8:
5598 g_assert_not_reached ();
5599 /* Implemented as helper calls */
5601 case OP_LCONV_TO_R_UN:
5602 g_assert_not_reached ();
5603 /* Implemented as helper calls */
5605 case OP_LCONV_TO_OVF_I4_2: {
5606 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5608 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5611 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5612 high_bit_not_set = code;
5613 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5615 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5616 valid_negative = code;
5617 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5618 invalid_negative = code;
5619 ARM_B_COND (code, ARMCOND_AL, 0);
5621 arm_patch (high_bit_not_set, code);
5623 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5624 valid_positive = code;
5625 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5627 arm_patch (invalid_negative, code);
5628 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5630 arm_patch (valid_negative, code);
5631 arm_patch (valid_positive, code);
5633 if (ins->dreg != ins->sreg1)
5634 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5638 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5641 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5644 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5647 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5650 ARM_NEGD (code, ins->dreg, ins->sreg1);
5654 g_assert_not_reached ();
5658 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5664 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5669 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5672 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5673 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5677 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5680 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5681 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5685 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5688 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5689 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5690 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5694 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5697 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5698 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5702 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5705 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5706 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5707 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5711 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5714 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5715 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5719 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5722 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5723 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5727 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5730 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5731 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5734 /* ARM FPA flags table:
5735 * N Less than ARMCOND_MI
5736 * Z Equal ARMCOND_EQ
5737 * C Greater Than or Equal ARMCOND_CS
5738 * V Unordered ARMCOND_VS
5741 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5744 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5747 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5750 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5751 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5757 g_assert_not_reached ();
5761 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5763 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5764 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5765 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5769 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5770 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5775 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5776 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5778 #ifdef USE_JUMP_TABLES
5780 gpointer *jte = mono_jumptable_add_entries (2);
5781 jte [0] = GUINT_TO_POINTER (0xffffffff);
5782 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5783 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5784 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5787 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5788 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5790 *(guint32*)code = 0xffffffff;
5792 *(guint32*)code = 0x7fefffff;
5795 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5797 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5798 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5800 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5801 ARM_CPYD (code, ins->dreg, ins->sreg1);
5803 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5804 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5809 case OP_RCONV_TO_I1:
5810 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5812 case OP_RCONV_TO_U1:
5813 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5815 case OP_RCONV_TO_I2:
5816 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5818 case OP_RCONV_TO_U2:
5819 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5821 case OP_RCONV_TO_I4:
5822 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5824 case OP_RCONV_TO_U4:
5825 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5827 case OP_RCONV_TO_R4:
5829 if (ins->dreg != ins->sreg1)
5830 ARM_CPYS (code, ins->dreg, ins->sreg1);
5832 case OP_RCONV_TO_R8:
5834 ARM_CVTS (code, ins->dreg, ins->sreg1);
5837 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5840 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5843 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5846 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5849 ARM_NEGS (code, ins->dreg, ins->sreg1);
5853 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5856 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5857 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5861 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5864 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5865 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5869 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5872 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5873 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5874 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5878 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5881 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5882 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5886 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5889 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5890 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5891 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5895 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5898 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5899 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5903 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5906 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5907 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5911 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5914 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5915 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5918 case OP_GC_LIVENESS_DEF:
5919 case OP_GC_LIVENESS_USE:
5920 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5921 ins->backend.pc_offset = code - cfg->native_code;
5923 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5924 ins->backend.pc_offset = code - cfg->native_code;
5925 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5929 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5930 g_assert_not_reached ();
5933 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5934 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5935 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5936 g_assert_not_reached ();
5942 last_offset = offset;
5945 cfg->code_len = code - cfg->native_code;
5948 #endif /* DISABLE_JIT */
5950 #ifdef HAVE_AEABI_READ_TP
5951 void __aeabi_read_tp (void);
5955 mono_arch_register_lowlevel_calls (void)
5957 /* The signature doesn't matter */
5958 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5959 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5961 #ifndef MONO_CROSS_COMPILE
5962 #ifdef HAVE_AEABI_READ_TP
5963 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
5968 #define patch_lis_ori(ip,val) do {\
5969 guint16 *__lis_ori = (guint16*)(ip); \
5970 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5971 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5975 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5977 unsigned char *ip = ji->ip.i + code;
5979 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5980 #ifdef USE_JUMP_TABLES
5981 gpointer *jt = mono_jumptable_get_entry (ip);
5983 gpointer *jt = (gpointer*)(ip + 8);
5986 /* jt is the inlined jump table, 2 instructions after ip
5987 * In the normal case we store the absolute addresses,
5988 * otherwise the displacements.
5990 for (i = 0; i < ji->data.table->table_size; i++)
5991 jt [i] = code + (int)ji->data.table->table [i];
5996 case MONO_PATCH_INFO_IP:
5997 g_assert_not_reached ();
5998 patch_lis_ori (ip, ip);
6000 case MONO_PATCH_INFO_METHOD_REL:
6001 g_assert_not_reached ();
6002 *((gpointer *)(ip)) = target;
6004 case MONO_PATCH_INFO_METHODCONST:
6005 case MONO_PATCH_INFO_CLASS:
6006 case MONO_PATCH_INFO_IMAGE:
6007 case MONO_PATCH_INFO_FIELD:
6008 case MONO_PATCH_INFO_VTABLE:
6009 case MONO_PATCH_INFO_IID:
6010 case MONO_PATCH_INFO_SFLDA:
6011 case MONO_PATCH_INFO_LDSTR:
6012 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6013 case MONO_PATCH_INFO_LDTOKEN:
6014 g_assert_not_reached ();
6015 /* from OP_AOTCONST : lis + ori */
6016 patch_lis_ori (ip, target);
6018 case MONO_PATCH_INFO_R4:
6019 case MONO_PATCH_INFO_R8:
6020 g_assert_not_reached ();
6021 *((gconstpointer *)(ip + 2)) = target;
6023 case MONO_PATCH_INFO_EXC_NAME:
6024 g_assert_not_reached ();
6025 *((gconstpointer *)(ip + 1)) = target;
6027 case MONO_PATCH_INFO_NONE:
6028 case MONO_PATCH_INFO_BB_OVF:
6029 case MONO_PATCH_INFO_EXC_OVF:
6030 /* everything is dealt with at epilog output time */
6035 arm_patch_general (cfg, domain, ip, target);
6041 * Stack frame layout:
6043 * ------------------- fp
6044 * MonoLMF structure or saved registers
6045 * -------------------
6047 * -------------------
6049 * -------------------
6050 * optional 8 bytes for tracing
6051 * -------------------
6052 * param area size is cfg->param_area
6053 * ------------------- sp
6056 mono_arch_emit_prolog (MonoCompile *cfg)
6058 MonoMethod *method = cfg->method;
6060 MonoMethodSignature *sig;
6062 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6067 int prev_sp_offset, reg_offset;
6069 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6072 sig = mono_method_signature (method);
6073 cfg->code_size = 256 + sig->param_count * 64;
6074 code = cfg->native_code = g_malloc (cfg->code_size);
6076 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6078 alloc_size = cfg->stack_offset;
6084 * The iphone uses R7 as the frame pointer, and it points at the saved
6089 * We can't use r7 as a frame pointer since it points into the middle of
6090 * the frame, so we keep using our own frame pointer.
6091 * FIXME: Optimize this.
6093 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6094 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6095 prev_sp_offset += 8; /* r7 and lr */
6096 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6097 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6100 if (!method->save_lmf) {
6102 /* No need to push LR again */
6103 if (cfg->used_int_regs)
6104 ARM_PUSH (code, cfg->used_int_regs);
6106 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6107 prev_sp_offset += 4;
6109 for (i = 0; i < 16; ++i) {
6110 if (cfg->used_int_regs & (1 << i))
6111 prev_sp_offset += 4;
6113 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6115 for (i = 0; i < 16; ++i) {
6116 if ((cfg->used_int_regs & (1 << i))) {
6117 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6118 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6123 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6124 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6126 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6127 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6130 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6131 ARM_PUSH (code, 0x5ff0);
6132 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6133 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6135 for (i = 0; i < 16; ++i) {
6136 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6137 /* The original r7 is saved at the start */
6138 if (!(iphone_abi && i == ARMREG_R7))
6139 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6143 g_assert (reg_offset == 4 * 10);
6144 pos += sizeof (MonoLMF) - (4 * 10);
6148 orig_alloc_size = alloc_size;
6149 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6150 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6151 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6152 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6155 /* the stack used in the pushed regs */
6156 if (prev_sp_offset & 4)
6158 cfg->stack_usage = alloc_size;
6160 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6161 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6163 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6164 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6166 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6168 if (cfg->frame_reg != ARMREG_SP) {
6169 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6170 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6172 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6173 prev_sp_offset += alloc_size;
6175 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6176 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6178 /* compute max_offset in order to use short forward jumps
6179 * we could skip do it on arm because the immediate displacement
6180 * for jumps is large enough, it may be useful later for constant pools
6183 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6184 MonoInst *ins = bb->code;
6185 bb->max_offset = max_offset;
6187 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6190 MONO_BB_FOR_EACH_INS (bb, ins)
6191 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6194 /* store runtime generic context */
6195 if (cfg->rgctx_var) {
6196 MonoInst *ins = cfg->rgctx_var;
6198 g_assert (ins->opcode == OP_REGOFFSET);
6200 if (arm_is_imm12 (ins->inst_offset)) {
6201 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6203 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6204 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6208 /* load arguments allocated to register from the stack */
6211 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
6213 if (cinfo->ret.storage == RegTypeStructByAddr) {
6214 ArgInfo *ainfo = &cinfo->ret;
6215 inst = cfg->vret_addr;
6216 g_assert (arm_is_imm12 (inst->inst_offset));
6217 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6220 if (sig->call_convention == MONO_CALL_VARARG) {
6221 ArgInfo *cookie = &cinfo->sig_cookie;
6223 /* Save the sig cookie address */
6224 g_assert (cookie->storage == RegTypeBase);
6226 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6227 g_assert (arm_is_imm12 (cfg->sig_cookie));
6228 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6229 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6232 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6233 ArgInfo *ainfo = cinfo->args + i;
6234 inst = cfg->args [pos];
6236 if (cfg->verbose_level > 2)
6237 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6239 if (inst->opcode == OP_REGVAR) {
6240 if (ainfo->storage == RegTypeGeneral)
6241 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6242 else if (ainfo->storage == RegTypeFP) {
6243 g_assert_not_reached ();
6244 } else if (ainfo->storage == RegTypeBase) {
6245 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6246 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6248 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6249 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6252 g_assert_not_reached ();
6254 if (cfg->verbose_level > 2)
6255 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6257 switch (ainfo->storage) {
6259 for (part = 0; part < ainfo->nregs; part ++) {
6260 if (ainfo->esize == 4)
6261 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6263 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6266 case RegTypeGeneral:
6267 case RegTypeIRegPair:
6268 case RegTypeGSharedVtInReg:
6269 switch (ainfo->size) {
6271 if (arm_is_imm12 (inst->inst_offset))
6272 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6274 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6275 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6279 if (arm_is_imm8 (inst->inst_offset)) {
6280 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6282 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6283 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6287 if (arm_is_imm12 (inst->inst_offset)) {
6288 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6290 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6291 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6293 if (arm_is_imm12 (inst->inst_offset + 4)) {
6294 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6296 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6297 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6301 if (arm_is_imm12 (inst->inst_offset)) {
6302 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6304 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6305 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6310 case RegTypeBaseGen:
6311 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6312 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6314 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6315 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6317 if (arm_is_imm12 (inst->inst_offset + 4)) {
6318 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6319 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6321 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6322 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6323 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6324 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6328 case RegTypeGSharedVtOnStack:
6329 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6330 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6332 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6333 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6336 switch (ainfo->size) {
6338 if (arm_is_imm8 (inst->inst_offset)) {
6339 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6341 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6342 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6346 if (arm_is_imm8 (inst->inst_offset)) {
6347 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6349 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6350 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6354 if (arm_is_imm12 (inst->inst_offset)) {
6355 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6357 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6358 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6360 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6361 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6363 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6364 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6366 if (arm_is_imm12 (inst->inst_offset + 4)) {
6367 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6369 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6370 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6374 if (arm_is_imm12 (inst->inst_offset)) {
6375 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6377 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6378 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6384 int imm8, rot_amount;
6386 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6387 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6388 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6390 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6392 if (ainfo->size == 8)
6393 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6395 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6398 case RegTypeStructByVal: {
6399 int doffset = inst->inst_offset;
6403 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
6404 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6405 if (arm_is_imm12 (doffset)) {
6406 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6408 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6409 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6411 soffset += sizeof (gpointer);
6412 doffset += sizeof (gpointer);
6414 if (ainfo->vtsize) {
6415 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6416 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6417 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6421 case RegTypeStructByAddr:
6422 g_assert_not_reached ();
6423 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6424 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6426 g_assert_not_reached ();
6433 if (method->save_lmf)
6434 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6437 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6439 if (cfg->arch.seq_point_info_var) {
6440 MonoInst *ins = cfg->arch.seq_point_info_var;
6442 /* Initialize the variable from a GOT slot */
6443 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6444 #ifdef USE_JUMP_TABLES
6446 gpointer *jte = mono_jumptable_add_entry ();
6447 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6448 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6450 /** XXX: is it correct? */
6452 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6454 *(gpointer*)code = NULL;
6457 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6459 g_assert (ins->opcode == OP_REGOFFSET);
6461 if (arm_is_imm12 (ins->inst_offset)) {
6462 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6464 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6465 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6469 /* Initialize ss_trigger_page_var */
6470 if (!cfg->soft_breakpoints) {
6471 MonoInst *info_var = cfg->arch.seq_point_info_var;
6472 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6473 int dreg = ARMREG_LR;
6476 g_assert (info_var->opcode == OP_REGOFFSET);
6477 g_assert (arm_is_imm12 (info_var->inst_offset));
6479 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6480 /* Load the trigger page addr */
6481 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6482 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6486 if (cfg->arch.seq_point_read_var) {
6487 MonoInst *read_ins = cfg->arch.seq_point_read_var;
6488 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6489 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6490 #ifdef USE_JUMP_TABLES
6493 g_assert (read_ins->opcode == OP_REGOFFSET);
6494 g_assert (arm_is_imm12 (read_ins->inst_offset));
6495 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6496 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6497 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6498 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6500 #ifdef USE_JUMP_TABLES
6501 jte = mono_jumptable_add_entries (3);
6502 jte [0] = (gpointer)&ss_trigger_var;
6503 jte [1] = single_step_tramp;
6504 jte [2] = breakpoint_tramp;
6505 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6507 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6509 *(volatile int **)code = &ss_trigger_var;
6511 *(gpointer*)code = single_step_tramp;
6513 *(gpointer*)code = breakpoint_tramp;
6517 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6518 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
6519 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6520 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6521 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
6522 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6525 cfg->code_len = code - cfg->native_code;
6526 g_assert (cfg->code_len < cfg->code_size);
6533 mono_arch_emit_epilog (MonoCompile *cfg)
6535 MonoMethod *method = cfg->method;
6536 int pos, i, rot_amount;
6537 int max_epilog_size = 16 + 20*4;
6541 if (cfg->method->save_lmf)
6542 max_epilog_size += 128;
6544 if (mono_jit_trace_calls != NULL)
6545 max_epilog_size += 50;
6547 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6548 max_epilog_size += 50;
6550 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6551 cfg->code_size *= 2;
6552 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6553 cfg->stat_code_reallocs++;
6557 * Keep in sync with OP_JMP
6559 code = cfg->native_code + cfg->code_len;
6561 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6562 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6566 /* Load returned vtypes into registers if needed */
6567 cinfo = cfg->arch.cinfo;
6568 switch (cinfo->ret.storage) {
6569 case RegTypeStructByVal: {
6570 MonoInst *ins = cfg->ret;
6572 if (arm_is_imm12 (ins->inst_offset)) {
6573 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6575 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6576 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6581 MonoInst *ins = cfg->ret;
6583 for (i = 0; i < cinfo->ret.nregs; ++i) {
6584 if (cinfo->ret.esize == 4)
6585 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6587 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6595 if (method->save_lmf) {
6596 int lmf_offset, reg, sp_adj, regmask;
6597 /* all but r0-r3, sp and pc */
6598 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6601 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6603 /* This points to r4 inside MonoLMF->iregs */
6604 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6606 regmask = 0x9ff0; /* restore lr to pc */
6607 /* Skip caller saved registers not used by the method */
6608 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6609 regmask &= ~(1 << reg);
6614 /* Restored later */
6615 regmask &= ~(1 << ARMREG_PC);
6616 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6617 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6619 ARM_POP (code, regmask);
6621 /* Restore saved r7, restore LR to PC */
6622 /* Skip lr from the lmf */
6623 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6624 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6627 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6628 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6630 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6631 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6635 /* Restore saved gregs */
6636 if (cfg->used_int_regs)
6637 ARM_POP (code, cfg->used_int_regs);
6638 /* Restore saved r7, restore LR to PC */
6639 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6641 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6645 cfg->code_len = code - cfg->native_code;
6647 g_assert (cfg->code_len < cfg->code_size);
6652 mono_arch_emit_exceptions (MonoCompile *cfg)
6654 MonoJumpInfo *patch_info;
6657 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6658 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6659 int max_epilog_size = 50;
6661 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6662 exc_throw_pos [i] = NULL;
6663 exc_throw_found [i] = 0;
6666 /* count the number of exception infos */
6669 * make sure we have enough space for exceptions
6671 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6672 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6673 i = mini_exception_id_by_name (patch_info->data.target);
6674 if (!exc_throw_found [i]) {
6675 max_epilog_size += 32;
6676 exc_throw_found [i] = TRUE;
6681 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6682 cfg->code_size *= 2;
6683 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6684 cfg->stat_code_reallocs++;
6687 code = cfg->native_code + cfg->code_len;
6689 /* add code to raise exceptions */
6690 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6691 switch (patch_info->type) {
6692 case MONO_PATCH_INFO_EXC: {
6693 MonoClass *exc_class;
6694 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6696 i = mini_exception_id_by_name (patch_info->data.target);
6697 if (exc_throw_pos [i]) {
6698 arm_patch (ip, exc_throw_pos [i]);
6699 patch_info->type = MONO_PATCH_INFO_NONE;
6702 exc_throw_pos [i] = code;
6704 arm_patch (ip, code);
6706 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6707 g_assert (exc_class);
6709 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6710 #ifdef USE_JUMP_TABLES
6712 gpointer *jte = mono_jumptable_add_entries (2);
6713 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6714 patch_info->data.name = "mono_arch_throw_corlib_exception";
6715 patch_info->ip.i = code - cfg->native_code;
6716 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6717 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6718 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6719 ARM_BLX_REG (code, ARMREG_IP);
6720 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6723 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6724 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6725 patch_info->data.name = "mono_arch_throw_corlib_exception";
6726 patch_info->ip.i = code - cfg->native_code;
6728 cfg->thunk_area += THUNK_SIZE;
6729 *(guint32*)(gpointer)code = exc_class->type_token;
6740 cfg->code_len = code - cfg->native_code;
6742 g_assert (cfg->code_len < cfg->code_size);
6746 #endif /* #ifndef DISABLE_JIT */
6749 mono_arch_finish_init (void)
6754 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6759 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6766 mono_arch_print_tree (MonoInst *tree, int arity)
6776 mono_arch_get_patch_offset (guint8 *code)
6783 mono_arch_flush_register_windows (void)
6788 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6790 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6794 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6796 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6799 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6800 #define BASE_SIZE (6 * 4)
6801 #define BSEARCH_ENTRY_SIZE (4 * 4)
6802 #define CMP_SIZE (3 * 4)
6803 #define BRANCH_SIZE (1 * 4)
6804 #define CALL_SIZE (2 * 4)
6805 #define WMC_SIZE (8 * 4)
6806 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6808 #ifdef USE_JUMP_TABLES
6810 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6812 g_assert (base [index] == NULL);
6813 base [index] = value;
6816 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6818 if (arm_is_imm12 (jti * 4)) {
6819 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6821 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6822 if ((jti * 4) >> 16)
6823 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6824 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6830 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6832 guint32 delta = DISTANCE (target, code);
6834 g_assert (delta >= 0 && delta <= 0xFFF);
6835 *target = *target | delta;
6841 #ifdef ENABLE_WRONG_METHOD_CHECK
6843 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6845 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6851 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6852 gpointer fail_tramp)
6855 arminstr_t *code, *start;
6856 #ifdef USE_JUMP_TABLES
6859 gboolean large_offsets = FALSE;
6860 guint32 **constant_pool_starts;
6861 arminstr_t *vtable_target = NULL;
6862 int extra_space = 0;
6864 #ifdef ENABLE_WRONG_METHOD_CHECK
6869 #ifdef USE_JUMP_TABLES
6870 for (i = 0; i < count; ++i) {
6871 MonoIMTCheckItem *item = imt_entries [i];
6872 item->chunk_size += 4 * 16;
6873 if (!item->is_equals)
6874 imt_entries [item->check_target_idx]->compare_done = TRUE;
6875 size += item->chunk_size;
6878 constant_pool_starts = g_new0 (guint32*, count);
6880 for (i = 0; i < count; ++i) {
6881 MonoIMTCheckItem *item = imt_entries [i];
6882 if (item->is_equals) {
6883 gboolean fail_case = !item->check_target_idx && fail_tramp;
6885 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6886 item->chunk_size += 32;
6887 large_offsets = TRUE;
6890 if (item->check_target_idx || fail_case) {
6891 if (!item->compare_done || fail_case)
6892 item->chunk_size += CMP_SIZE;
6893 item->chunk_size += BRANCH_SIZE;
6895 #ifdef ENABLE_WRONG_METHOD_CHECK
6896 item->chunk_size += WMC_SIZE;
6900 item->chunk_size += 16;
6901 large_offsets = TRUE;
6903 item->chunk_size += CALL_SIZE;
6905 item->chunk_size += BSEARCH_ENTRY_SIZE;
6906 imt_entries [item->check_target_idx]->compare_done = TRUE;
6908 size += item->chunk_size;
6912 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6916 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6918 code = mono_domain_code_reserve (domain, size);
6922 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6923 for (i = 0; i < count; ++i) {
6924 MonoIMTCheckItem *item = imt_entries [i];
6925 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6929 #ifdef USE_JUMP_TABLES
6930 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6931 #define VTABLE_JTI 0
6932 #define IMT_METHOD_OFFSET 0
6933 #define TARGET_CODE_OFFSET 1
6934 #define JUMP_CODE_OFFSET 2
6935 #define RECORDS_PER_ENTRY 3
6936 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
6937 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
6938 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
6940 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
6941 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
6942 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
6943 set_jumptable_element (jte, VTABLE_JTI, vtable);
6946 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6948 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6949 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6950 vtable_target = code;
6951 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6953 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6955 for (i = 0; i < count; ++i) {
6956 MonoIMTCheckItem *item = imt_entries [i];
6957 #ifdef USE_JUMP_TABLES
6958 guint32 imt_method_jti = 0, target_code_jti = 0;
6960 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6962 gint32 vtable_offset;
6964 item->code_target = (guint8*)code;
6966 if (item->is_equals) {
6967 gboolean fail_case = !item->check_target_idx && fail_tramp;
6969 if (item->check_target_idx || fail_case) {
6970 if (!item->compare_done || fail_case) {
6971 #ifdef USE_JUMP_TABLES
6972 imt_method_jti = IMT_METHOD_JTI (i);
6973 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
6976 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6978 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6980 #ifdef USE_JUMP_TABLES
6981 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
6982 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
6983 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
6985 item->jmp_code = (guint8*)code;
6986 ARM_B_COND (code, ARMCOND_NE, 0);
6989 /*Enable the commented code to assert on wrong method*/
6990 #ifdef ENABLE_WRONG_METHOD_CHECK
6991 #ifdef USE_JUMP_TABLES
6992 imt_method_jti = IMT_METHOD_JTI (i);
6993 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
6996 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6998 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7000 ARM_B_COND (code, ARMCOND_EQ, 0);
7002 /* Define this if your system is so bad that gdb is failing. */
7003 #ifdef BROKEN_DEV_ENV
7004 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7006 arm_patch (code - 1, mini_dump_bad_imt);
7010 arm_patch (cond, code);
7014 if (item->has_target_code) {
7015 /* Load target address */
7016 #ifdef USE_JUMP_TABLES
7017 target_code_jti = TARGET_CODE_JTI (i);
7018 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7019 /* Restore registers */
7020 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7022 ARM_BX (code, ARMREG_R1);
7023 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7025 target_code_ins = code;
7026 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7027 /* Save it to the fourth slot */
7028 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7029 /* Restore registers and branch */
7030 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7032 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7035 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7036 if (!arm_is_imm12 (vtable_offset)) {
7038 * We need to branch to a computed address but we don't have
7039 * a free register to store it, since IP must contain the
7040 * vtable address. So we push the two values to the stack, and
7041 * load them both using LDM.
7043 /* Compute target address */
7044 #ifdef USE_JUMP_TABLES
7045 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7046 if (vtable_offset >> 16)
7047 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7048 /* IP had vtable base. */
7049 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7050 /* Restore registers and branch */
7051 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7052 ARM_BX (code, ARMREG_IP);
7054 vtable_offset_ins = code;
7055 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7056 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7057 /* Save it to the fourth slot */
7058 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7059 /* Restore registers and branch */
7060 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7062 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7065 #ifdef USE_JUMP_TABLES
7066 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7067 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7068 ARM_BX (code, ARMREG_IP);
7070 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7072 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7073 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7079 #ifdef USE_JUMP_TABLES
7080 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7081 target_code_jti = TARGET_CODE_JTI (i);
7082 /* Load target address */
7083 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7084 /* Restore registers */
7085 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7087 ARM_BX (code, ARMREG_R1);
7088 set_jumptable_element (jte, target_code_jti, fail_tramp);
7090 arm_patch (item->jmp_code, (guchar*)code);
7092 target_code_ins = code;
7093 /* Load target address */
7094 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7095 /* Save it to the fourth slot */
7096 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7097 /* Restore registers and branch */
7098 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7100 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7102 item->jmp_code = NULL;
7105 #ifdef USE_JUMP_TABLES
7107 set_jumptable_element (jte, imt_method_jti, item->key);
7110 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7112 /*must emit after unconditional branch*/
7113 if (vtable_target) {
7114 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7115 item->chunk_size += 4;
7116 vtable_target = NULL;
7119 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7120 constant_pool_starts [i] = code;
7122 code += extra_space;
7127 #ifdef USE_JUMP_TABLES
7128 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7129 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7130 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7131 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7132 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7134 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7135 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7137 item->jmp_code = (guint8*)code;
7138 ARM_B_COND (code, ARMCOND_HS, 0);
7144 for (i = 0; i < count; ++i) {
7145 MonoIMTCheckItem *item = imt_entries [i];
7146 if (item->jmp_code) {
7147 if (item->check_target_idx)
7148 #ifdef USE_JUMP_TABLES
7149 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7151 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7154 if (i > 0 && item->is_equals) {
7156 #ifdef USE_JUMP_TABLES
7157 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7158 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7160 arminstr_t *space_start = constant_pool_starts [i];
7161 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7162 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7170 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7171 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7176 #ifndef USE_JUMP_TABLES
7177 g_free (constant_pool_starts);
7180 mono_arch_flush_icache ((guint8*)start, size);
7181 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7182 mono_stats.imt_thunks_size += code - start;
7184 g_assert (DISTANCE (start, code) <= size);
7189 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7191 return ctx->regs [reg];
7195 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7197 ctx->regs [reg] = val;
7201 * mono_arch_get_trampolines:
7203 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7207 mono_arch_get_trampolines (gboolean aot)
7209 return mono_arm_get_exception_trampolines (aot);
7213 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7220 bp = MONO_CONTEXT_GET_BP (ctx);
7221 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7223 old_value = *lr_loc;
7224 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7227 *lr_loc = new_value;
7232 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7234 * mono_arch_set_breakpoint:
7236 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7237 * The location should contain code emitted by OP_SEQ_POINT.
7240 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7243 guint32 native_offset = ip - (guint8*)ji->code_start;
7244 MonoDebugOptions *opt = mini_get_debug_options ();
7246 if (opt->soft_breakpoints) {
7247 g_assert (!ji->from_aot);
7249 ARM_BLX_REG (code, ARMREG_LR);
7250 mono_arch_flush_icache (code - 4, 4);
7251 } else if (ji->from_aot) {
7252 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7254 g_assert (native_offset % 4 == 0);
7255 g_assert (info->bp_addrs [native_offset / 4] == 0);
7256 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7258 int dreg = ARMREG_LR;
7260 /* Read from another trigger page */
7261 #ifdef USE_JUMP_TABLES
7262 gpointer *jte = mono_jumptable_add_entry ();
7263 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7264 jte [0] = bp_trigger_page;
7266 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7268 *(int*)code = (int)bp_trigger_page;
7271 ARM_LDR_IMM (code, dreg, dreg, 0);
7273 mono_arch_flush_icache (code - 16, 16);
7276 /* This is currently implemented by emitting an SWI instruction, which
7277 * qemu/linux seems to convert to a SIGILL.
7279 *(int*)code = (0xef << 24) | 8;
7281 mono_arch_flush_icache (code - 4, 4);
7287 * mono_arch_clear_breakpoint:
7289 * Clear the breakpoint at IP.
7292 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7294 MonoDebugOptions *opt = mini_get_debug_options ();
7298 if (opt->soft_breakpoints) {
7299 g_assert (!ji->from_aot);
7302 mono_arch_flush_icache (code - 4, 4);
7303 } else if (ji->from_aot) {
7304 guint32 native_offset = ip - (guint8*)ji->code_start;
7305 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7307 g_assert (native_offset % 4 == 0);
7308 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7309 info->bp_addrs [native_offset / 4] = 0;
7311 for (i = 0; i < 4; ++i)
7314 mono_arch_flush_icache (ip, code - ip);
7319 * mono_arch_start_single_stepping:
7321 * Start single stepping.
7324 mono_arch_start_single_stepping (void)
7326 if (ss_trigger_page)
7327 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7333 * mono_arch_stop_single_stepping:
7335 * Stop single stepping.
7338 mono_arch_stop_single_stepping (void)
7340 if (ss_trigger_page)
7341 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7347 #define DBG_SIGNAL SIGBUS
7349 #define DBG_SIGNAL SIGSEGV
7353 * mono_arch_is_single_step_event:
7355 * Return whenever the machine state in SIGCTX corresponds to a single
7359 mono_arch_is_single_step_event (void *info, void *sigctx)
7361 siginfo_t *sinfo = info;
7363 if (!ss_trigger_page)
7366 /* Sometimes the address is off by 4 */
7367 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7374 * mono_arch_is_breakpoint_event:
7376 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7379 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7381 siginfo_t *sinfo = info;
7383 if (!ss_trigger_page)
7386 if (sinfo->si_signo == DBG_SIGNAL) {
7387 /* Sometimes the address is off by 4 */
7388 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7398 * mono_arch_skip_breakpoint:
7400 * See mini-amd64.c for docs.
7403 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7405 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7409 * mono_arch_skip_single_step:
7411 * See mini-amd64.c for docs.
7414 mono_arch_skip_single_step (MonoContext *ctx)
7416 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7419 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7422 * mono_arch_get_seq_point_info:
7424 * See mini-amd64.c for docs.
7427 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7432 // FIXME: Add a free function
7434 mono_domain_lock (domain);
7435 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7437 mono_domain_unlock (domain);
7440 ji = mono_jit_info_table_find (domain, (char*)code);
7443 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7445 info->ss_trigger_page = ss_trigger_page;
7446 info->bp_trigger_page = bp_trigger_page;
7448 mono_domain_lock (domain);
7449 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7451 mono_domain_unlock (domain);
7458 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7460 ext->lmf.previous_lmf = prev_lmf;
7461 /* Mark that this is a MonoLMFExt */
7462 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7463 ext->lmf.sp = (gssize)ext;
7467 * mono_arch_set_target:
7469 * Set the target architecture the JIT backend should generate code for, in the form
7470 * of a GNU target triplet. Only used in AOT mode.
7473 mono_arch_set_target (char *mtriple)
7475 /* The GNU target triple format is not very well documented */
7476 if (strstr (mtriple, "armv7")) {
7477 v5_supported = TRUE;
7478 v6_supported = TRUE;
7479 v7_supported = TRUE;
7481 if (strstr (mtriple, "armv6")) {
7482 v5_supported = TRUE;
7483 v6_supported = TRUE;
7485 if (strstr (mtriple, "armv7s")) {
7486 v7s_supported = TRUE;
7488 if (strstr (mtriple, "thumbv7s")) {
7489 v5_supported = TRUE;
7490 v6_supported = TRUE;
7491 v7_supported = TRUE;
7492 v7s_supported = TRUE;
7493 thumb_supported = TRUE;
7494 thumb2_supported = TRUE;
7496 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7497 v5_supported = TRUE;
7498 v6_supported = TRUE;
7499 thumb_supported = TRUE;
7502 if (strstr (mtriple, "gnueabi"))
7503 eabi_supported = TRUE;
7507 mono_arch_opcode_supported (int opcode)
7510 case OP_ATOMIC_ADD_I4:
7511 case OP_ATOMIC_EXCHANGE_I4:
7512 case OP_ATOMIC_CAS_I4:
7513 case OP_ATOMIC_LOAD_I1:
7514 case OP_ATOMIC_LOAD_I2:
7515 case OP_ATOMIC_LOAD_I4:
7516 case OP_ATOMIC_LOAD_U1:
7517 case OP_ATOMIC_LOAD_U2:
7518 case OP_ATOMIC_LOAD_U4:
7519 case OP_ATOMIC_STORE_I1:
7520 case OP_ATOMIC_STORE_I2:
7521 case OP_ATOMIC_STORE_I4:
7522 case OP_ATOMIC_STORE_U1:
7523 case OP_ATOMIC_STORE_U2:
7524 case OP_ATOMIC_STORE_U4:
7525 return v7_supported;
7526 case OP_ATOMIC_LOAD_R4:
7527 case OP_ATOMIC_LOAD_R8:
7528 case OP_ATOMIC_STORE_R4:
7529 case OP_ATOMIC_STORE_R8:
7530 return v7_supported && IS_VFP;
7536 #if defined(ENABLE_GSHAREDVT)
7538 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7540 #endif /* !MONOTOUCH */