2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
16 #include <mono/metadata/abi-details.h>
17 #include <mono/metadata/appdomain.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/utils/mono-mmap.h>
21 #include <mono/utils/mono-hwcap.h>
22 #include <mono/utils/mono-memory-model.h>
23 #include <mono/utils/mono-threads-coop.h>
26 #include "mini-arm-tls.h"
30 #include "debugger-agent.h"
32 #include "mono/arch/arm/arm-vfp-codegen.h"
34 #if (defined(HAVE_KW_THREAD) && defined(__linux__) && defined(__ARM_EABI__)) \
35 || defined(TARGET_ANDROID) \
36 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
40 /* Sanity check: This makes no sense */
41 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
42 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
46 * IS_SOFT_FLOAT: Is full software floating point used?
47 * IS_HARD_FLOAT: Is full hardware floating point used?
48 * IS_VFP: Is hardware floating point with software ABI used?
50 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
51 * IS_VFP may delegate to mono_arch_is_soft_float ().
54 #if defined(ARM_FPU_VFP_HARD)
55 #define IS_SOFT_FLOAT (FALSE)
56 #define IS_HARD_FLOAT (TRUE)
58 #elif defined(ARM_FPU_NONE)
59 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
60 #define IS_HARD_FLOAT (FALSE)
61 #define IS_VFP (!mono_arch_is_soft_float ())
63 #define IS_SOFT_FLOAT (FALSE)
64 #define IS_HARD_FLOAT (FALSE)
68 #define THUNK_SIZE (3 * 4)
70 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
73 void sys_icache_invalidate (void *start, size_t len);
76 /* This mutex protects architecture specific caches */
77 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
78 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
79 static mono_mutex_t mini_arch_mutex;
81 static gboolean v5_supported = FALSE;
82 static gboolean v6_supported = FALSE;
83 static gboolean v7_supported = FALSE;
84 static gboolean v7s_supported = FALSE;
85 static gboolean v7k_supported = FALSE;
86 static gboolean thumb_supported = FALSE;
87 static gboolean thumb2_supported = FALSE;
89 * Whenever to use the ARM EABI
91 static gboolean eabi_supported = FALSE;
94 * Whenever to use the iphone ABI extensions:
95 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
96 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
97 * This is required for debugging/profiling tools to work, but it has some overhead so it should
98 * only be turned on in debug builds.
100 static gboolean iphone_abi = FALSE;
103 * The FPU we are generating code for. This is NOT runtime configurable right now,
104 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
106 static MonoArmFPU arm_fpu;
108 #if defined(ARM_FPU_VFP_HARD)
110 * On armhf, d0-d7 are used for argument passing and d8-d15
111 * must be preserved across calls, which leaves us no room
112 * for scratch registers. So we use d14-d15 but back up their
113 * previous contents to a stack slot before using them - see
114 * mono_arm_emit_vfp_scratch_save/_restore ().
116 static int vfp_scratch1 = ARM_VFP_D14;
117 static int vfp_scratch2 = ARM_VFP_D15;
120 * On armel, d0-d7 do not need to be preserved, so we can
121 * freely make use of them as scratch registers.
123 static int vfp_scratch1 = ARM_VFP_D0;
124 static int vfp_scratch2 = ARM_VFP_D1;
129 static gpointer single_step_tramp, breakpoint_tramp;
130 static gpointer get_tls_tramp;
133 * The code generated for sequence points reads from this location, which is
134 * made read-only when single stepping is enabled.
136 static gpointer ss_trigger_page;
138 /* Enabled breakpoints read from this trigger page */
139 static gpointer bp_trigger_page;
143 * floating point support: on ARM it is a mess, there are at least 3
144 * different setups, each of which binary incompat with the other.
145 * 1) FPA: old and ugly, but unfortunately what current distros use
146 * the double binary format has the two words swapped. 8 double registers.
147 * Implemented usually by kernel emulation.
148 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
149 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
150 * 3) VFP: the new and actually sensible and useful FP support. Implemented
151 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
153 * We do not care about FPA. We will support soft float and VFP.
155 int mono_exc_esp_offset = 0;
157 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
158 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
159 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
161 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
162 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
163 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
165 //#define DEBUG_IMT 0
168 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
172 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data);
175 mono_arch_regname (int reg)
177 static const char * rnames[] = {
178 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
179 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
180 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
183 if (reg >= 0 && reg < 16)
189 mono_arch_fregname (int reg)
191 static const char * rnames[] = {
192 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
193 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
194 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
195 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
196 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
197 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
200 if (reg >= 0 && reg < 32)
208 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
210 int imm8, rot_amount;
211 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
212 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
216 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
217 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
219 code = mono_arm_emit_load_imm (code, dreg, imm);
220 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
225 /* If dreg == sreg, this clobbers IP */
227 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
229 int imm8, rot_amount;
230 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
231 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
235 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
236 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
238 code = mono_arm_emit_load_imm (code, dreg, imm);
239 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
245 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
247 /* we can use r0-r3, since this is called only for incoming args on the stack */
248 if (size > sizeof (gpointer) * 4) {
250 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
251 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
252 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
253 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
254 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
255 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
256 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
257 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
258 ARM_B_COND (code, ARMCOND_NE, 0);
259 arm_patch (code - 4, start_loop);
262 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
263 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
265 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
266 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
272 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
273 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
274 doffset = soffset = 0;
276 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
277 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
283 g_assert (size == 0);
288 emit_call_reg (guint8 *code, int reg)
291 ARM_BLX_REG (code, reg);
293 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
297 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
303 emit_call_seq (MonoCompile *cfg, guint8 *code)
305 if (cfg->method->dynamic) {
306 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
308 *(gpointer*)code = NULL;
310 code = emit_call_reg (code, ARMREG_IP);
314 cfg->thunk_area += THUNK_SIZE;
319 mono_arm_patchable_b (guint8 *code, int cond)
321 ARM_B_COND (code, cond, 0);
326 mono_arm_patchable_bl (guint8 *code, int cond)
328 ARM_BL_COND (code, cond, 0);
333 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
336 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
337 if (cfg->compile_aot) {
339 * This opcode is generated by CEE_MONO_JIT_ATTACH, so it can execute on
340 * threads which are not yet attached to the runtime. This means we can't
341 * call it directly, since the call would go through the trampoline code
342 * which assumes the thread is attached. So use a separate patch info type
343 * for it, and load it from a preinitialized GOT slot.
345 code = emit_aotconst (cfg, code, ARMREG_R1, MONO_PATCH_INFO_GET_TLS_TRAMP, NULL);
346 code = emit_call_reg (code, ARMREG_R1);
348 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
350 code = emit_call_seq (cfg, code);
352 if (dreg != ARMREG_R0)
353 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
355 g_assert_not_reached ();
361 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
364 if (tls_offset_reg != ARMREG_R0)
365 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
366 if (cfg->compile_aot) {
367 code = emit_aotconst (cfg, code, ARMREG_R1, MONO_PATCH_INFO_GET_TLS_TRAMP, NULL);
368 code = emit_call_reg (code, ARMREG_R1);
370 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
372 code = emit_call_seq (cfg, code);
374 if (dreg != ARMREG_R0)
375 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
377 g_assert_not_reached ();
383 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
386 if (sreg != ARMREG_R1)
387 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
388 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
389 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
391 code = emit_call_seq (cfg, code);
393 g_assert_not_reached ();
399 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
402 /* Get sreg in R1 and tls_offset_reg in R0 */
403 if (tls_offset_reg == ARMREG_R1) {
404 if (sreg == ARMREG_R0) {
405 /* swap sreg and tls_offset_reg */
406 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
407 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
408 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
410 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
411 if (sreg != ARMREG_R1)
412 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
415 if (sreg != ARMREG_R1)
416 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
417 if (tls_offset_reg != ARMREG_R0)
418 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
420 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
422 code = emit_call_seq (cfg, code);
424 g_assert_not_reached ();
432 * Emit code to push an LMF structure on the LMF stack.
433 * On arm, this is intermixed with the initialization of other fields of the structure.
436 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
438 gboolean get_lmf_fast = FALSE;
441 if (mono_arm_have_tls_get ()) {
443 if (cfg->compile_aot) {
445 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
446 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
448 *(gpointer*)code = NULL;
450 /* Load the value from the GOT */
451 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
452 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
454 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
455 g_assert (lmf_addr_tls_offset != -1);
456 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
461 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
462 (gpointer)"mono_get_lmf_addr");
463 code = emit_call_seq (cfg, code);
465 /* we build the MonoLMF structure on the stack - see mini-arm.h */
466 /* lmf_offset is the offset from the previous stack pointer,
467 * alloc_size is the total stack space allocated, so the offset
468 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
469 * The pointer to the struct is put in r1 (new_lmf).
470 * ip is used as scratch
471 * The callee-saved registers are already in the MonoLMF structure
473 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
474 /* r0 is the result from mono_get_lmf_addr () */
475 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
476 /* new_lmf->previous_lmf = *lmf_addr */
477 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
478 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
479 /* *(lmf_addr) = r1 */
480 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
481 /* Skip method (only needed for trampoline LMF frames) */
482 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
483 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
484 /* save the current IP */
485 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
486 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
488 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
489 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
500 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
504 for (list = inst->float_args; list; list = list->next) {
505 FloatArgData *fad = list->data;
506 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
507 gboolean imm = arm_is_fpimm8 (var->inst_offset);
509 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
515 if (*offset + *max_len > cfg->code_size) {
516 cfg->code_size += *max_len;
517 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
519 code = cfg->native_code + *offset;
523 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
524 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
526 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
528 *offset = code - cfg->native_code;
535 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
539 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
541 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
544 if (!arm_is_fpimm8 (inst->inst_offset)) {
545 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
546 ARM_FSTD (code, reg, ARMREG_LR, 0);
548 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
555 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
559 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
561 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
564 if (!arm_is_fpimm8 (inst->inst_offset)) {
565 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
566 ARM_FLDD (code, reg, ARMREG_LR, 0);
568 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
577 * Emit code to pop an LMF structure from the LMF stack.
580 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
584 if (lmf_offset < 32) {
585 basereg = cfg->frame_reg;
590 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
593 /* ip = previous_lmf */
594 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
596 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
597 /* *(lmf_addr) = previous_lmf */
598 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
603 #endif /* #ifndef DISABLE_JIT */
606 * mono_arm_have_tls_get:
608 * Returns whether we have tls access implemented on the current
612 mono_arm_have_tls_get (void)
622 * mono_arch_get_argument_info:
623 * @csig: a method signature
624 * @param_count: the number of parameters to consider
625 * @arg_info: an array to store the result infos
627 * Gathers information on parameters such as size, alignment and
628 * padding. arg_info should be large enought to hold param_count + 1 entries.
630 * Returns the size of the activation frame.
633 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
635 int k, frame_size = 0;
636 guint32 size, align, pad;
640 t = mini_get_underlying_type (csig->ret);
641 if (MONO_TYPE_ISSTRUCT (t)) {
642 frame_size += sizeof (gpointer);
646 arg_info [0].offset = offset;
649 frame_size += sizeof (gpointer);
653 arg_info [0].size = frame_size;
655 for (k = 0; k < param_count; k++) {
656 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
658 /* ignore alignment for now */
661 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
662 arg_info [k].pad = pad;
664 arg_info [k + 1].pad = 0;
665 arg_info [k + 1].size = size;
667 arg_info [k + 1].offset = offset;
671 align = MONO_ARCH_FRAME_ALIGNMENT;
672 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
673 arg_info [k].pad = pad;
678 #define MAX_ARCH_DELEGATE_PARAMS 3
681 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
683 guint8 *code, *start;
684 GSList *unwind_ops = mono_arch_get_cie_program ();
687 start = code = mono_global_codeman_reserve (12);
689 /* Replace the this argument with the target */
690 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
691 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
692 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
694 g_assert ((code - start) <= 12);
696 mono_arch_flush_icache (start, 12);
700 size = 8 + param_count * 4;
701 start = code = mono_global_codeman_reserve (size);
703 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
704 /* slide down the arguments */
705 for (i = 0; i < param_count; ++i) {
706 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
708 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
710 g_assert ((code - start) <= size);
712 mono_arch_flush_icache (start, size);
716 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
718 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
719 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
723 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
729 * mono_arch_get_delegate_invoke_impls:
731 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
735 mono_arch_get_delegate_invoke_impls (void)
741 get_delegate_invoke_impl (&info, TRUE, 0);
742 res = g_slist_prepend (res, info);
744 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
745 get_delegate_invoke_impl (&info, FALSE, i);
746 res = g_slist_prepend (res, info);
753 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
755 guint8 *code, *start;
758 /* FIXME: Support more cases */
759 sig_ret = mini_get_underlying_type (sig->ret);
760 if (MONO_TYPE_ISSTRUCT (sig_ret))
764 static guint8* cached = NULL;
765 mono_mini_arch_lock ();
767 mono_mini_arch_unlock ();
772 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
775 start = get_delegate_invoke_impl (&info, TRUE, 0);
776 mono_tramp_info_register (info, NULL);
779 mono_mini_arch_unlock ();
782 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
785 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
787 for (i = 0; i < sig->param_count; ++i)
788 if (!mono_is_regsize_var (sig->params [i]))
791 mono_mini_arch_lock ();
792 code = cache [sig->param_count];
794 mono_mini_arch_unlock ();
799 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
800 start = mono_aot_get_trampoline (name);
804 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
805 mono_tramp_info_register (info, NULL);
807 cache [sig->param_count] = start;
808 mono_mini_arch_unlock ();
816 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
822 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
824 return (gpointer)regs [ARMREG_R0];
828 * Initialize the cpu to execute managed code.
831 mono_arch_cpu_init (void)
833 i8_align = MONO_ABI_ALIGNOF (gint64);
834 #ifdef MONO_CROSS_COMPILE
835 /* Need to set the alignment of i8 since it can different on the target */
836 #ifdef TARGET_ANDROID
838 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
844 * Initialize architecture specific code.
847 mono_arch_init (void)
849 const char *cpu_arch;
851 #ifdef TARGET_WATCHOS
852 mini_get_debug_options ()->soft_breakpoints = TRUE;
855 mono_os_mutex_init_recursive (&mini_arch_mutex);
856 if (mini_get_debug_options ()->soft_breakpoints) {
858 breakpoint_tramp = mini_get_breakpoint_trampoline ();
860 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
861 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
862 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
865 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
866 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
867 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
868 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
869 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
871 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
873 #if defined(__ARM_EABI__)
874 eabi_supported = TRUE;
877 #if defined(ARM_FPU_VFP_HARD)
878 arm_fpu = MONO_ARM_FPU_VFP_HARD;
880 arm_fpu = MONO_ARM_FPU_VFP;
882 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
884 * If we're compiling with a soft float fallback and it
885 * turns out that no VFP unit is available, we need to
886 * switch to soft float. We don't do this for iOS, since
887 * iOS devices always have a VFP unit.
889 if (!mono_hwcap_arm_has_vfp)
890 arm_fpu = MONO_ARM_FPU_NONE;
893 * This environment variable can be useful in testing
894 * environments to make sure the soft float fallback
895 * works. Most ARM devices have VFP units these days, so
896 * normally soft float code would not be exercised much.
898 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
900 if (soft && !strncmp (soft, "1", 1))
901 arm_fpu = MONO_ARM_FPU_NONE;
905 v5_supported = mono_hwcap_arm_is_v5;
906 v6_supported = mono_hwcap_arm_is_v6;
907 v7_supported = mono_hwcap_arm_is_v7;
910 * On weird devices, the hwcap code may fail to detect
911 * the ARM version. In that case, we can at least safely
912 * assume the version the runtime was compiled for.
924 #if defined(__APPLE__)
925 /* iOS is special-cased here because we don't yet
926 have a way to properly detect CPU features on it. */
927 thumb_supported = TRUE;
930 thumb_supported = mono_hwcap_arm_has_thumb;
931 thumb2_supported = mono_hwcap_arm_has_thumb2;
934 /* Format: armv(5|6|7[s])[-thumb[2]] */
935 cpu_arch = g_getenv ("MONO_CPU_ARCH");
937 /* Do this here so it overrides any detection. */
939 if (strncmp (cpu_arch, "armv", 4) == 0) {
940 v5_supported = cpu_arch [4] >= '5';
941 v6_supported = cpu_arch [4] >= '6';
942 v7_supported = cpu_arch [4] >= '7';
943 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
944 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
947 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
948 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
953 * Cleanup architecture specific code.
956 mono_arch_cleanup (void)
961 * This function returns the optimizations supported on this cpu.
964 mono_arch_cpu_optimizations (guint32 *exclude_mask)
966 /* no arm-specific optimizations yet */
972 * This function test for all SIMD functions supported.
974 * Returns a bitmask corresponding to all supported versions.
978 mono_arch_cpu_enumerate_simd_versions (void)
980 /* SIMD is currently unimplemented */
985 mono_arm_is_hard_float (void)
987 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
993 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
995 if (v7s_supported || v7k_supported) {
1009 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1011 mono_arch_is_soft_float (void)
1013 return arm_fpu == MONO_ARM_FPU_NONE;
1018 is_regsize_var (MonoType *t)
1022 t = mini_get_underlying_type (t);
1029 case MONO_TYPE_FNPTR:
1031 case MONO_TYPE_OBJECT:
1032 case MONO_TYPE_STRING:
1033 case MONO_TYPE_CLASS:
1034 case MONO_TYPE_SZARRAY:
1035 case MONO_TYPE_ARRAY:
1037 case MONO_TYPE_GENERICINST:
1038 if (!mono_type_generic_inst_is_valuetype (t))
1041 case MONO_TYPE_VALUETYPE:
1048 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1053 for (i = 0; i < cfg->num_varinfo; i++) {
1054 MonoInst *ins = cfg->varinfo [i];
1055 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1058 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1061 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1064 /* we can only allocate 32 bit values */
1065 if (is_regsize_var (ins->inst_vtype)) {
1066 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1067 g_assert (i == vmv->idx);
1068 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1076 mono_arch_get_global_int_regs (MonoCompile *cfg)
1080 mono_arch_compute_omit_fp (cfg);
1083 * FIXME: Interface calls might go through a static rgctx trampoline which
1084 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1087 if (cfg->flags & MONO_CFG_HAS_CALLS)
1088 cfg->uses_rgctx_reg = TRUE;
1090 if (cfg->arch.omit_fp)
1091 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1092 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1093 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1094 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1096 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1097 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1099 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1100 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1101 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1102 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1103 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1104 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1110 * mono_arch_regalloc_cost:
1112 * Return the cost, in number of memory references, of the action of
1113 * allocating the variable VMV into a register during global register
1117 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1123 #endif /* #ifndef DISABLE_JIT */
1126 mono_arch_flush_icache (guint8 *code, gint size)
1128 #if defined(MONO_CROSS_COMPILE)
1130 sys_icache_invalidate (code, size);
1132 __builtin___clear_cache (code, code + size);
1139 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1142 if (*gr > ARMREG_R3) {
1144 ainfo->offset = *stack_size;
1145 ainfo->reg = ARMREG_SP; /* in the caller */
1146 ainfo->storage = RegTypeBase;
1149 ainfo->storage = RegTypeGeneral;
1156 split = i8_align == 4;
1161 if (*gr == ARMREG_R3 && split) {
1162 /* first word in r3 and the second on the stack */
1163 ainfo->offset = *stack_size;
1164 ainfo->reg = ARMREG_SP; /* in the caller */
1165 ainfo->storage = RegTypeBaseGen;
1167 } else if (*gr >= ARMREG_R3) {
1168 if (eabi_supported) {
1169 /* darwin aligns longs to 4 byte only */
1170 if (i8_align == 8) {
1175 ainfo->offset = *stack_size;
1176 ainfo->reg = ARMREG_SP; /* in the caller */
1177 ainfo->storage = RegTypeBase;
1180 if (eabi_supported) {
1181 if (i8_align == 8 && ((*gr) & 1))
1184 ainfo->storage = RegTypeIRegPair;
1193 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1196 * If we're calling a function like this:
1198 * void foo(float a, double b, float c)
1200 * We pass a in s0 and b in d1. That leaves us
1201 * with s1 being unused. The armhf ABI recognizes
1202 * this and requires register assignment to then
1203 * use that for the next single-precision arg,
1204 * i.e. c in this example. So float_spare either
1205 * tells us which reg to use for the next single-
1206 * precision arg, or it's -1, meaning use *fpr.
1208 * Note that even though most of the JIT speaks
1209 * double-precision, fpr represents single-
1210 * precision registers.
1212 * See parts 5.5 and 6.1.2 of the AAPCS for how
1216 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1217 ainfo->storage = RegTypeFP;
1221 * If we're passing a double-precision value
1222 * and *fpr is odd (e.g. it's s1, s3, ...)
1223 * we need to use the next even register. So
1224 * we mark the current *fpr as a spare that
1225 * can be used for the next single-precision
1229 *float_spare = *fpr;
1234 * At this point, we have an even register
1235 * so we assign that and move along.
1239 } else if (*float_spare >= 0) {
1241 * We're passing a single-precision value
1242 * and it looks like a spare single-
1243 * precision register is available. Let's
1247 ainfo->reg = *float_spare;
1251 * If we hit this branch, we're passing a
1252 * single-precision value and we can simply
1253 * use the next available register.
1261 * We've exhausted available floating point
1262 * regs, so pass the rest on the stack.
1270 ainfo->offset = *stack_size;
1271 ainfo->reg = ARMREG_SP;
1272 ainfo->storage = RegTypeBase;
1279 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1283 MonoClassField *field;
1284 MonoType *ftype, *prev_ftype = NULL;
1287 klass = mono_class_from_mono_type (t);
1289 while ((field = mono_class_get_fields (klass, &iter))) {
1290 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1292 ftype = mono_field_get_type (field);
1293 ftype = mini_get_underlying_type (ftype);
1295 if (MONO_TYPE_ISSTRUCT (ftype)) {
1296 int nested_nfields, nested_esize;
1298 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1300 if (nested_esize == 4)
1301 ftype = &mono_defaults.single_class->byval_arg;
1303 ftype = &mono_defaults.double_class->byval_arg;
1304 if (prev_ftype && prev_ftype->type != ftype->type)
1307 nfields += nested_nfields;
1309 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1311 if (prev_ftype && prev_ftype->type != ftype->type)
1317 if (nfields == 0 || nfields > 4)
1319 *out_nfields = nfields;
1320 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1325 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1327 guint i, gr, fpr, pstart;
1329 int n = sig->hasthis + sig->param_count;
1333 guint32 stack_size = 0;
1335 gboolean is_pinvoke = sig->pinvoke;
1336 gboolean vtype_retaddr = FALSE;
1339 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1341 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1348 t = mini_get_underlying_type (sig->ret);
1359 case MONO_TYPE_FNPTR:
1360 case MONO_TYPE_CLASS:
1361 case MONO_TYPE_OBJECT:
1362 case MONO_TYPE_SZARRAY:
1363 case MONO_TYPE_ARRAY:
1364 case MONO_TYPE_STRING:
1365 cinfo->ret.storage = RegTypeGeneral;
1366 cinfo->ret.reg = ARMREG_R0;
1370 cinfo->ret.storage = RegTypeIRegPair;
1371 cinfo->ret.reg = ARMREG_R0;
1375 cinfo->ret.storage = RegTypeFP;
1377 if (t->type == MONO_TYPE_R4)
1378 cinfo->ret.size = 4;
1380 cinfo->ret.size = 8;
1382 if (IS_HARD_FLOAT) {
1383 cinfo->ret.reg = ARM_VFP_F0;
1385 cinfo->ret.reg = ARMREG_R0;
1388 case MONO_TYPE_GENERICINST:
1389 if (!mono_type_generic_inst_is_valuetype (t)) {
1390 cinfo->ret.storage = RegTypeGeneral;
1391 cinfo->ret.reg = ARMREG_R0;
1394 if (mini_is_gsharedvt_variable_type (t)) {
1395 cinfo->ret.storage = RegTypeStructByAddr;
1399 case MONO_TYPE_VALUETYPE:
1400 case MONO_TYPE_TYPEDBYREF:
1401 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1402 cinfo->ret.storage = RegTypeHFA;
1404 cinfo->ret.nregs = nfields;
1405 cinfo->ret.esize = esize;
1408 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1411 #ifdef TARGET_WATCHOS
1416 if (native_size <= max_size) {
1417 cinfo->ret.storage = RegTypeStructByVal;
1418 cinfo->ret.struct_size = native_size;
1419 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1421 cinfo->ret.storage = RegTypeStructByAddr;
1424 cinfo->ret.storage = RegTypeStructByAddr;
1429 case MONO_TYPE_MVAR:
1430 g_assert (mini_is_gsharedvt_type (t));
1431 cinfo->ret.storage = RegTypeStructByAddr;
1433 case MONO_TYPE_VOID:
1436 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1439 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1444 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1445 * the first argument, allowing 'this' to be always passed in the first arg reg.
1446 * Also do this if the first argument is a reference type, since virtual calls
1447 * are sometimes made using calli without sig->hasthis set, like in the delegate
1450 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1452 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1454 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1458 cinfo->ret.reg = gr;
1460 cinfo->vret_arg_index = 1;
1464 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1467 if (vtype_retaddr) {
1468 cinfo->ret.reg = gr;
1473 DEBUG(g_print("params: %d\n", sig->param_count));
1474 for (i = pstart; i < sig->param_count; ++i) {
1475 ArgInfo *ainfo = &cinfo->args [n];
1477 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1478 /* Prevent implicit arguments and sig_cookie from
1479 being passed in registers */
1482 /* Emit the signature cookie just before the implicit arguments */
1483 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1485 DEBUG(g_print("param %d: ", i));
1486 if (sig->params [i]->byref) {
1487 DEBUG(g_print("byref\n"));
1488 add_general (&gr, &stack_size, ainfo, TRUE);
1492 t = mini_get_underlying_type (sig->params [i]);
1496 cinfo->args [n].size = 1;
1497 add_general (&gr, &stack_size, ainfo, TRUE);
1501 cinfo->args [n].size = 2;
1502 add_general (&gr, &stack_size, ainfo, TRUE);
1506 cinfo->args [n].size = 4;
1507 add_general (&gr, &stack_size, ainfo, TRUE);
1512 case MONO_TYPE_FNPTR:
1513 case MONO_TYPE_CLASS:
1514 case MONO_TYPE_OBJECT:
1515 case MONO_TYPE_STRING:
1516 case MONO_TYPE_SZARRAY:
1517 case MONO_TYPE_ARRAY:
1518 cinfo->args [n].size = sizeof (gpointer);
1519 add_general (&gr, &stack_size, ainfo, TRUE);
1521 case MONO_TYPE_GENERICINST:
1522 if (!mono_type_generic_inst_is_valuetype (t)) {
1523 cinfo->args [n].size = sizeof (gpointer);
1524 add_general (&gr, &stack_size, ainfo, TRUE);
1527 if (mini_is_gsharedvt_variable_type (t)) {
1528 /* gsharedvt arguments are passed by ref */
1529 g_assert (mini_is_gsharedvt_type (t));
1530 add_general (&gr, &stack_size, ainfo, TRUE);
1531 switch (ainfo->storage) {
1532 case RegTypeGeneral:
1533 ainfo->storage = RegTypeGSharedVtInReg;
1536 ainfo->storage = RegTypeGSharedVtOnStack;
1539 g_assert_not_reached ();
1544 case MONO_TYPE_TYPEDBYREF:
1545 case MONO_TYPE_VALUETYPE: {
1548 int nwords, nfields, esize;
1551 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1552 if (fpr + nfields < ARM_VFP_F16) {
1553 ainfo->storage = RegTypeHFA;
1555 ainfo->nregs = nfields;
1556 ainfo->esize = esize;
1567 if (t->type == MONO_TYPE_TYPEDBYREF) {
1568 size = sizeof (MonoTypedRef);
1569 align = sizeof (gpointer);
1571 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1573 size = mono_class_native_size (klass, &align);
1575 size = mini_type_stack_size_full (t, &align, FALSE);
1577 DEBUG(g_print ("load %d bytes struct\n", size));
1579 #ifdef TARGET_WATCHOS
1580 /* Watchos pass large structures by ref */
1581 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1582 if (sig->pinvoke && size > 16) {
1583 add_general (&gr, &stack_size, ainfo, TRUE);
1584 switch (ainfo->storage) {
1585 case RegTypeGeneral:
1586 ainfo->storage = RegTypeStructByAddr;
1589 ainfo->storage = RegTypeStructByAddrOnStack;
1592 g_assert_not_reached ();
1601 align_size += (sizeof (gpointer) - 1);
1602 align_size &= ~(sizeof (gpointer) - 1);
1603 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1604 ainfo->storage = RegTypeStructByVal;
1605 ainfo->struct_size = size;
1606 /* FIXME: align stack_size if needed */
1607 if (eabi_supported) {
1608 if (align >= 8 && (gr & 1))
1611 if (gr > ARMREG_R3) {
1613 ainfo->vtsize = nwords;
1615 int rest = ARMREG_R3 - gr + 1;
1616 int n_in_regs = rest >= nwords? nwords: rest;
1618 ainfo->size = n_in_regs;
1619 ainfo->vtsize = nwords - n_in_regs;
1622 nwords -= n_in_regs;
1624 if (sig->call_convention == MONO_CALL_VARARG)
1625 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1626 stack_size = ALIGN_TO (stack_size, align);
1627 ainfo->offset = stack_size;
1628 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1629 stack_size += nwords * sizeof (gpointer);
1635 add_general (&gr, &stack_size, ainfo, FALSE);
1641 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1643 add_general (&gr, &stack_size, ainfo, TRUE);
1649 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1651 add_general (&gr, &stack_size, ainfo, FALSE);
1654 case MONO_TYPE_MVAR:
1655 /* gsharedvt arguments are passed by ref */
1656 g_assert (mini_is_gsharedvt_type (t));
1657 add_general (&gr, &stack_size, ainfo, TRUE);
1658 switch (ainfo->storage) {
1659 case RegTypeGeneral:
1660 ainfo->storage = RegTypeGSharedVtInReg;
1663 ainfo->storage = RegTypeGSharedVtOnStack;
1666 g_assert_not_reached ();
1670 g_error ("Can't handle 0x%x", sig->params [i]->type);
1675 /* Handle the case where there are no implicit arguments */
1676 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1677 /* Prevent implicit arguments and sig_cookie from
1678 being passed in registers */
1681 /* Emit the signature cookie just before the implicit arguments */
1682 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1685 /* align stack size to 8 */
1686 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1687 stack_size = (stack_size + 7) & ~7;
1689 cinfo->stack_usage = stack_size;
1695 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1697 MonoType *callee_ret;
1701 c1 = get_call_info (NULL, caller_sig);
1702 c2 = get_call_info (NULL, callee_sig);
1705 * Tail calls with more callee stack usage than the caller cannot be supported, since
1706 * the extra stack space would be left on the stack after the tail call.
1708 res = c1->stack_usage >= c2->stack_usage;
1709 callee_ret = mini_get_underlying_type (callee_sig->ret);
1710 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1711 /* An address on the callee's stack is passed as the first argument */
1714 if (c2->stack_usage > 16 * 4)
1726 debug_omit_fp (void)
1729 return mono_debug_count ();
1736 * mono_arch_compute_omit_fp:
1738 * Determine whenever the frame pointer can be eliminated.
1741 mono_arch_compute_omit_fp (MonoCompile *cfg)
1743 MonoMethodSignature *sig;
1744 MonoMethodHeader *header;
1748 if (cfg->arch.omit_fp_computed)
1751 header = cfg->header;
1753 sig = mono_method_signature (cfg->method);
1755 if (!cfg->arch.cinfo)
1756 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1757 cinfo = cfg->arch.cinfo;
1760 * FIXME: Remove some of the restrictions.
1762 cfg->arch.omit_fp = TRUE;
1763 cfg->arch.omit_fp_computed = TRUE;
1765 if (cfg->disable_omit_fp)
1766 cfg->arch.omit_fp = FALSE;
1767 if (!debug_omit_fp ())
1768 cfg->arch.omit_fp = FALSE;
1770 if (cfg->method->save_lmf)
1771 cfg->arch.omit_fp = FALSE;
1773 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1774 cfg->arch.omit_fp = FALSE;
1775 if (header->num_clauses)
1776 cfg->arch.omit_fp = FALSE;
1777 if (cfg->param_area)
1778 cfg->arch.omit_fp = FALSE;
1779 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1780 cfg->arch.omit_fp = FALSE;
1781 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1782 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1783 cfg->arch.omit_fp = FALSE;
1784 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1785 ArgInfo *ainfo = &cinfo->args [i];
1787 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1789 * The stack offset can only be determined when the frame
1792 cfg->arch.omit_fp = FALSE;
1797 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1798 MonoInst *ins = cfg->varinfo [i];
1801 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1806 * Set var information according to the calling convention. arm version.
1807 * The locals var stuff should most likely be split in another method.
1810 mono_arch_allocate_vars (MonoCompile *cfg)
1812 MonoMethodSignature *sig;
1813 MonoMethodHeader *header;
1816 int i, offset, size, align, curinst;
1821 sig = mono_method_signature (cfg->method);
1823 if (!cfg->arch.cinfo)
1824 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1825 cinfo = cfg->arch.cinfo;
1826 sig_ret = mini_get_underlying_type (sig->ret);
1828 mono_arch_compute_omit_fp (cfg);
1830 if (cfg->arch.omit_fp)
1831 cfg->frame_reg = ARMREG_SP;
1833 cfg->frame_reg = ARMREG_FP;
1835 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1837 /* allow room for the vararg method args: void* and long/double */
1838 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1839 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1841 header = cfg->header;
1843 /* See mono_arch_get_global_int_regs () */
1844 if (cfg->flags & MONO_CFG_HAS_CALLS)
1845 cfg->uses_rgctx_reg = TRUE;
1847 if (cfg->frame_reg != ARMREG_SP)
1848 cfg->used_int_regs |= 1 << cfg->frame_reg;
1850 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1851 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1852 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1856 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1857 if (sig_ret->type != MONO_TYPE_VOID) {
1858 cfg->ret->opcode = OP_REGVAR;
1859 cfg->ret->inst_c0 = ARMREG_R0;
1862 /* local vars are at a positive offset from the stack pointer */
1864 * also note that if the function uses alloca, we use FP
1865 * to point at the local variables.
1867 offset = 0; /* linkage area */
1868 /* align the offset to 16 bytes: not sure this is needed here */
1870 //offset &= ~(8 - 1);
1872 /* add parameter area size for called functions */
1873 offset += cfg->param_area;
1876 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1879 /* allow room to save the return value */
1880 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1883 switch (cinfo->ret.storage) {
1884 case RegTypeStructByVal:
1886 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1887 offset = ALIGN_TO (offset, 8);
1888 cfg->ret->opcode = OP_REGOFFSET;
1889 cfg->ret->inst_basereg = cfg->frame_reg;
1890 cfg->ret->inst_offset = offset;
1891 if (cinfo->ret.storage == RegTypeStructByVal)
1892 offset += cinfo->ret.nregs * sizeof (gpointer);
1896 case RegTypeStructByAddr:
1897 ins = cfg->vret_addr;
1898 offset += sizeof(gpointer) - 1;
1899 offset &= ~(sizeof(gpointer) - 1);
1900 ins->inst_offset = offset;
1901 ins->opcode = OP_REGOFFSET;
1902 ins->inst_basereg = cfg->frame_reg;
1903 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1904 g_print ("vret_addr =");
1905 mono_print_ins (cfg->vret_addr);
1907 offset += sizeof(gpointer);
1913 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1914 if (cfg->arch.seq_point_info_var) {
1917 ins = cfg->arch.seq_point_info_var;
1921 offset += align - 1;
1922 offset &= ~(align - 1);
1923 ins->opcode = OP_REGOFFSET;
1924 ins->inst_basereg = cfg->frame_reg;
1925 ins->inst_offset = offset;
1928 if (cfg->arch.ss_trigger_page_var) {
1931 ins = cfg->arch.ss_trigger_page_var;
1934 offset += align - 1;
1935 offset &= ~(align - 1);
1936 ins->opcode = OP_REGOFFSET;
1937 ins->inst_basereg = cfg->frame_reg;
1938 ins->inst_offset = offset;
1942 if (cfg->arch.seq_point_ss_method_var) {
1945 ins = cfg->arch.seq_point_ss_method_var;
1948 offset += align - 1;
1949 offset &= ~(align - 1);
1950 ins->opcode = OP_REGOFFSET;
1951 ins->inst_basereg = cfg->frame_reg;
1952 ins->inst_offset = offset;
1955 if (cfg->arch.seq_point_bp_method_var) {
1958 ins = cfg->arch.seq_point_bp_method_var;
1961 offset += align - 1;
1962 offset &= ~(align - 1);
1963 ins->opcode = OP_REGOFFSET;
1964 ins->inst_basereg = cfg->frame_reg;
1965 ins->inst_offset = offset;
1969 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1970 /* Allocate a temporary used by the atomic ops */
1974 /* Allocate a local slot to hold the sig cookie address */
1975 offset += align - 1;
1976 offset &= ~(align - 1);
1977 cfg->arch.atomic_tmp_offset = offset;
1980 cfg->arch.atomic_tmp_offset = -1;
1983 cfg->locals_min_stack_offset = offset;
1985 curinst = cfg->locals_start;
1986 for (i = curinst; i < cfg->num_varinfo; ++i) {
1989 ins = cfg->varinfo [i];
1990 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1993 t = ins->inst_vtype;
1994 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1997 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1998 * pinvoke wrappers when they call functions returning structure */
1999 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2000 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
2004 size = mono_type_size (t, &align);
2006 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2007 * since it loads/stores misaligned words, which don't do the right thing.
2009 if (align < 4 && size >= 4)
2011 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2012 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2013 offset += align - 1;
2014 offset &= ~(align - 1);
2015 ins->opcode = OP_REGOFFSET;
2016 ins->inst_offset = offset;
2017 ins->inst_basereg = cfg->frame_reg;
2019 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2022 cfg->locals_max_stack_offset = offset;
2026 ins = cfg->args [curinst];
2027 if (ins->opcode != OP_REGVAR) {
2028 ins->opcode = OP_REGOFFSET;
2029 ins->inst_basereg = cfg->frame_reg;
2030 offset += sizeof (gpointer) - 1;
2031 offset &= ~(sizeof (gpointer) - 1);
2032 ins->inst_offset = offset;
2033 offset += sizeof (gpointer);
2038 if (sig->call_convention == MONO_CALL_VARARG) {
2042 /* Allocate a local slot to hold the sig cookie address */
2043 offset += align - 1;
2044 offset &= ~(align - 1);
2045 cfg->sig_cookie = offset;
2049 for (i = 0; i < sig->param_count; ++i) {
2050 ainfo = cinfo->args + i;
2052 ins = cfg->args [curinst];
2054 switch (ainfo->storage) {
2056 offset = ALIGN_TO (offset, 8);
2057 ins->opcode = OP_REGOFFSET;
2058 ins->inst_basereg = cfg->frame_reg;
2059 /* These arguments are saved to the stack in the prolog */
2060 ins->inst_offset = offset;
2061 if (cfg->verbose_level >= 2)
2062 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2070 if (ins->opcode != OP_REGVAR) {
2071 ins->opcode = OP_REGOFFSET;
2072 ins->inst_basereg = cfg->frame_reg;
2073 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2075 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2076 * since it loads/stores misaligned words, which don't do the right thing.
2078 if (align < 4 && size >= 4)
2080 /* The code in the prolog () stores words when storing vtypes received in a register */
2081 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2083 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2084 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2085 offset += align - 1;
2086 offset &= ~(align - 1);
2087 ins->inst_offset = offset;
2093 /* align the offset to 8 bytes */
2094 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2095 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2100 cfg->stack_offset = offset;
2104 mono_arch_create_vars (MonoCompile *cfg)
2106 MonoMethodSignature *sig;
2110 sig = mono_method_signature (cfg->method);
2112 if (!cfg->arch.cinfo)
2113 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2114 cinfo = cfg->arch.cinfo;
2116 if (IS_HARD_FLOAT) {
2117 for (i = 0; i < 2; i++) {
2118 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2119 inst->flags |= MONO_INST_VOLATILE;
2121 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2125 if (cinfo->ret.storage == RegTypeStructByVal)
2126 cfg->ret_var_is_local = TRUE;
2128 if (cinfo->ret.storage == RegTypeStructByAddr) {
2129 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2130 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2131 g_print ("vret_addr = ");
2132 mono_print_ins (cfg->vret_addr);
2136 if (cfg->gen_sdb_seq_points) {
2137 if (cfg->compile_aot) {
2138 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2139 ins->flags |= MONO_INST_VOLATILE;
2140 cfg->arch.seq_point_info_var = ins;
2142 if (!cfg->soft_breakpoints) {
2143 /* Allocate a separate variable for this to save 1 load per seq point */
2144 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2145 ins->flags |= MONO_INST_VOLATILE;
2146 cfg->arch.ss_trigger_page_var = ins;
2149 if (cfg->soft_breakpoints) {
2152 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2153 ins->flags |= MONO_INST_VOLATILE;
2154 cfg->arch.seq_point_ss_method_var = ins;
2156 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2157 ins->flags |= MONO_INST_VOLATILE;
2158 cfg->arch.seq_point_bp_method_var = ins;
2164 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2166 MonoMethodSignature *tmp_sig;
2169 if (call->tail_call)
2172 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2175 * mono_ArgIterator_Setup assumes the signature cookie is
2176 * passed first and all the arguments which were before it are
2177 * passed on the stack after the signature. So compensate by
2178 * passing a different signature.
2180 tmp_sig = mono_metadata_signature_dup (call->signature);
2181 tmp_sig->param_count -= call->signature->sentinelpos;
2182 tmp_sig->sentinelpos = 0;
2183 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2185 sig_reg = mono_alloc_ireg (cfg);
2186 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2188 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2193 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2198 LLVMCallInfo *linfo;
2200 n = sig->param_count + sig->hasthis;
2202 cinfo = get_call_info (cfg->mempool, sig);
2204 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2207 * LLVM always uses the native ABI while we use our own ABI, the
2208 * only difference is the handling of vtypes:
2209 * - we only pass/receive them in registers in some cases, and only
2210 * in 1 or 2 integer registers.
2212 switch (cinfo->ret.storage) {
2213 case RegTypeGeneral:
2216 case RegTypeIRegPair:
2218 case RegTypeStructByAddr:
2219 /* Vtype returned using a hidden argument */
2220 linfo->ret.storage = LLVMArgVtypeRetAddr;
2221 linfo->vret_arg_index = cinfo->vret_arg_index;
2224 case RegTypeStructByVal:
2225 /* LLVM models this by returning an int array */
2226 linfo->ret.storage = LLVMArgAsIArgs;
2227 linfo->ret.nslots = cinfo->ret.nregs;
2231 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2232 cfg->disable_llvm = TRUE;
2236 for (i = 0; i < n; ++i) {
2237 LLVMArgInfo *lainfo = &linfo->args [i];
2238 ainfo = cinfo->args + i;
2240 lainfo->storage = LLVMArgNone;
2242 switch (ainfo->storage) {
2243 case RegTypeGeneral:
2244 case RegTypeIRegPair:
2246 case RegTypeBaseGen:
2248 lainfo->storage = LLVMArgNormal;
2250 case RegTypeStructByVal:
2251 lainfo->storage = LLVMArgAsIArgs;
2252 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2254 case RegTypeStructByAddr:
2255 case RegTypeStructByAddrOnStack:
2256 lainfo->storage = LLVMArgVtypeByRef;
2259 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2260 cfg->disable_llvm = TRUE;
2270 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2273 MonoMethodSignature *sig;
2277 sig = call->signature;
2278 n = sig->param_count + sig->hasthis;
2280 cinfo = get_call_info (cfg->mempool, sig);
2282 switch (cinfo->ret.storage) {
2283 case RegTypeStructByVal:
2285 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2286 /* The JIT will transform this into a normal call */
2287 call->vret_in_reg = TRUE;
2290 if (call->inst.opcode == OP_TAILCALL)
2293 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2294 * the location pointed to by it after call in emit_move_return_value ().
2296 if (!cfg->arch.vret_addr_loc) {
2297 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2298 /* Prevent it from being register allocated or optimized away */
2299 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2302 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2304 case RegTypeStructByAddr: {
2306 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2307 vtarg->sreg1 = call->vret_var->dreg;
2308 vtarg->dreg = mono_alloc_preg (cfg);
2309 MONO_ADD_INS (cfg->cbb, vtarg);
2311 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2318 for (i = 0; i < n; ++i) {
2319 ArgInfo *ainfo = cinfo->args + i;
2322 if (i >= sig->hasthis)
2323 t = sig->params [i - sig->hasthis];
2325 t = &mono_defaults.int_class->byval_arg;
2326 t = mini_get_underlying_type (t);
2328 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2329 /* Emit the signature cookie just before the implicit arguments */
2330 emit_sig_cookie (cfg, call, cinfo);
2333 in = call->args [i];
2335 switch (ainfo->storage) {
2336 case RegTypeGeneral:
2337 case RegTypeIRegPair:
2338 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2339 MONO_INST_NEW (cfg, ins, OP_MOVE);
2340 ins->dreg = mono_alloc_ireg (cfg);
2341 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2342 MONO_ADD_INS (cfg->cbb, ins);
2343 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2345 MONO_INST_NEW (cfg, ins, OP_MOVE);
2346 ins->dreg = mono_alloc_ireg (cfg);
2347 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2348 MONO_ADD_INS (cfg->cbb, ins);
2349 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2350 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2351 if (ainfo->size == 4) {
2352 if (IS_SOFT_FLOAT) {
2353 /* mono_emit_call_args () have already done the r8->r4 conversion */
2354 /* The converted value is in an int vreg */
2355 MONO_INST_NEW (cfg, ins, OP_MOVE);
2356 ins->dreg = mono_alloc_ireg (cfg);
2357 ins->sreg1 = in->dreg;
2358 MONO_ADD_INS (cfg->cbb, ins);
2359 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2363 cfg->param_area = MAX (cfg->param_area, 8);
2364 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2365 creg = mono_alloc_ireg (cfg);
2366 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2367 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2370 if (IS_SOFT_FLOAT) {
2371 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2372 ins->dreg = mono_alloc_ireg (cfg);
2373 ins->sreg1 = in->dreg;
2374 MONO_ADD_INS (cfg->cbb, ins);
2375 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2377 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2378 ins->dreg = mono_alloc_ireg (cfg);
2379 ins->sreg1 = in->dreg;
2380 MONO_ADD_INS (cfg->cbb, ins);
2381 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2385 cfg->param_area = MAX (cfg->param_area, 8);
2386 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2387 creg = mono_alloc_ireg (cfg);
2388 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2389 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2390 creg = mono_alloc_ireg (cfg);
2391 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2392 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2395 cfg->flags |= MONO_CFG_HAS_FPOUT;
2397 MONO_INST_NEW (cfg, ins, OP_MOVE);
2398 ins->dreg = mono_alloc_ireg (cfg);
2399 ins->sreg1 = in->dreg;
2400 MONO_ADD_INS (cfg->cbb, ins);
2402 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2405 case RegTypeStructByVal:
2406 case RegTypeGSharedVtInReg:
2407 case RegTypeGSharedVtOnStack:
2409 case RegTypeStructByAddr:
2410 case RegTypeStructByAddrOnStack:
2411 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2412 ins->opcode = OP_OUTARG_VT;
2413 ins->sreg1 = in->dreg;
2414 ins->klass = in->klass;
2415 ins->inst_p0 = call;
2416 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2417 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2418 mono_call_inst_add_outarg_vt (cfg, call, ins);
2419 MONO_ADD_INS (cfg->cbb, ins);
2422 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2423 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2424 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2425 if (t->type == MONO_TYPE_R8) {
2426 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2429 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2431 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2434 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2437 case RegTypeBaseGen:
2438 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2439 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2440 MONO_INST_NEW (cfg, ins, OP_MOVE);
2441 ins->dreg = mono_alloc_ireg (cfg);
2442 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2443 MONO_ADD_INS (cfg->cbb, ins);
2444 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2445 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2448 /* This should work for soft-float as well */
2450 cfg->param_area = MAX (cfg->param_area, 8);
2451 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2452 creg = mono_alloc_ireg (cfg);
2453 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2454 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2455 creg = mono_alloc_ireg (cfg);
2456 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2457 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2458 cfg->flags |= MONO_CFG_HAS_FPOUT;
2460 g_assert_not_reached ();
2464 int fdreg = mono_alloc_freg (cfg);
2466 if (ainfo->size == 8) {
2467 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2468 ins->sreg1 = in->dreg;
2470 MONO_ADD_INS (cfg->cbb, ins);
2472 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2477 * Mono's register allocator doesn't speak single-precision registers that
2478 * overlap double-precision registers (i.e. armhf). So we have to work around
2479 * the register allocator and load the value from memory manually.
2481 * So we create a variable for the float argument and an instruction to store
2482 * the argument into the variable. We then store the list of these arguments
2483 * in call->float_args. This list is then used by emit_float_args later to
2484 * pass the arguments in the various call opcodes.
2486 * This is not very nice, and we should really try to fix the allocator.
2489 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2491 /* Make sure the instruction isn't seen as pointless and removed.
2493 float_arg->flags |= MONO_INST_VOLATILE;
2495 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2497 /* We use the dreg to look up the instruction later. The hreg is used to
2498 * emit the instruction that loads the value into the FP reg.
2500 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2501 fad->vreg = float_arg->dreg;
2502 fad->hreg = ainfo->reg;
2504 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2507 call->used_iregs |= 1 << ainfo->reg;
2508 cfg->flags |= MONO_CFG_HAS_FPOUT;
2512 g_assert_not_reached ();
2516 /* Handle the case where there are no implicit arguments */
2517 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2518 emit_sig_cookie (cfg, call, cinfo);
2520 call->call_info = cinfo;
2521 call->stack_usage = cinfo->stack_usage;
2525 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2531 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2532 ins->dreg = mono_alloc_freg (cfg);
2533 ins->sreg1 = arg->dreg;
2534 MONO_ADD_INS (cfg->cbb, ins);
2535 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2538 g_assert_not_reached ();
2544 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2546 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2548 ArgInfo *ainfo = ins->inst_p1;
2549 int ovf_size = ainfo->vtsize;
2550 int doffset = ainfo->offset;
2551 int struct_size = ainfo->struct_size;
2552 int i, soffset, dreg, tmpreg;
2554 switch (ainfo->storage) {
2555 case RegTypeGSharedVtInReg:
2556 case RegTypeStructByAddr:
2558 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2560 case RegTypeGSharedVtOnStack:
2561 case RegTypeStructByAddrOnStack:
2562 /* Pass by addr on stack */
2563 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2566 for (i = 0; i < ainfo->nregs; ++i) {
2567 if (ainfo->esize == 4)
2568 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2570 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2571 load->dreg = mono_alloc_freg (cfg);
2572 load->inst_basereg = src->dreg;
2573 load->inst_offset = i * ainfo->esize;
2574 MONO_ADD_INS (cfg->cbb, load);
2576 if (ainfo->esize == 4) {
2579 /* See RegTypeFP in mono_arch_emit_call () */
2580 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2581 float_arg->flags |= MONO_INST_VOLATILE;
2582 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2584 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2585 fad->vreg = float_arg->dreg;
2586 fad->hreg = ainfo->reg + i;
2588 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2590 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2596 for (i = 0; i < ainfo->size; ++i) {
2597 dreg = mono_alloc_ireg (cfg);
2598 switch (struct_size) {
2600 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2603 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2606 tmpreg = mono_alloc_ireg (cfg);
2607 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2608 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2609 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2610 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2611 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2612 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2613 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2616 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2619 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2620 soffset += sizeof (gpointer);
2621 struct_size -= sizeof (gpointer);
2623 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2625 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2631 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2633 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2636 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2639 if (COMPILE_LLVM (cfg)) {
2640 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2642 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2643 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2644 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2645 MONO_ADD_INS (cfg->cbb, ins);
2650 case MONO_ARM_FPU_NONE:
2651 if (ret->type == MONO_TYPE_R8) {
2654 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2655 ins->dreg = cfg->ret->dreg;
2656 ins->sreg1 = val->dreg;
2657 MONO_ADD_INS (cfg->cbb, ins);
2660 if (ret->type == MONO_TYPE_R4) {
2661 /* Already converted to an int in method_to_ir () */
2662 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2666 case MONO_ARM_FPU_VFP:
2667 case MONO_ARM_FPU_VFP_HARD:
2668 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2671 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2672 ins->dreg = cfg->ret->dreg;
2673 ins->sreg1 = val->dreg;
2674 MONO_ADD_INS (cfg->cbb, ins);
2679 g_assert_not_reached ();
2683 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2686 #endif /* #ifndef DISABLE_JIT */
2689 mono_arch_is_inst_imm (gint64 imm)
2695 MonoMethodSignature *sig;
2698 MonoType **param_types;
2702 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2706 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2709 switch (cinfo->ret.storage) {
2711 case RegTypeGeneral:
2712 case RegTypeIRegPair:
2713 case RegTypeStructByAddr:
2724 for (i = 0; i < cinfo->nargs; ++i) {
2725 ArgInfo *ainfo = &cinfo->args [i];
2728 switch (ainfo->storage) {
2729 case RegTypeGeneral:
2730 case RegTypeIRegPair:
2731 case RegTypeBaseGen:
2735 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2738 case RegTypeStructByVal:
2739 if (ainfo->size == 0)
2740 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2742 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2743 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2751 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2752 for (i = 0; i < sig->param_count; ++i) {
2753 MonoType *t = sig->params [i];
2758 t = mini_get_underlying_type (t);
2781 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2783 ArchDynCallInfo *info;
2787 cinfo = get_call_info (NULL, sig);
2789 if (!dyn_call_supported (cinfo, sig)) {
2794 info = g_new0 (ArchDynCallInfo, 1);
2795 // FIXME: Preprocess the info to speed up start_dyn_call ()
2797 info->cinfo = cinfo;
2798 info->rtype = mini_get_underlying_type (sig->ret);
2799 info->param_types = g_new0 (MonoType*, sig->param_count);
2800 for (i = 0; i < sig->param_count; ++i)
2801 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2803 return (MonoDynCallInfo*)info;
2807 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2809 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2811 g_free (ainfo->cinfo);
2816 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2818 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2819 DynCallArgs *p = (DynCallArgs*)buf;
2820 int arg_index, greg, i, j, pindex;
2821 MonoMethodSignature *sig = dinfo->sig;
2823 g_assert (buf_len >= sizeof (DynCallArgs));
2833 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2834 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2839 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2840 p->regs [greg ++] = (mgreg_t)ret;
2842 for (i = pindex; i < sig->param_count; i++) {
2843 MonoType *t = dinfo->param_types [i];
2844 gpointer *arg = args [arg_index ++];
2845 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2848 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2850 } else if (ainfo->storage == RegTypeFP) {
2851 } else if (ainfo->storage == RegTypeBase) {
2852 slot = PARAM_REGS + (ainfo->offset / 4);
2853 } else if (ainfo->storage == RegTypeBaseGen) {
2854 /* slot + 1 is the first stack slot, so the code below will work */
2857 g_assert_not_reached ();
2861 p->regs [slot] = (mgreg_t)*arg;
2866 case MONO_TYPE_STRING:
2867 case MONO_TYPE_CLASS:
2868 case MONO_TYPE_ARRAY:
2869 case MONO_TYPE_SZARRAY:
2870 case MONO_TYPE_OBJECT:
2874 p->regs [slot] = (mgreg_t)*arg;
2877 p->regs [slot] = *(guint8*)arg;
2880 p->regs [slot] = *(gint8*)arg;
2883 p->regs [slot] = *(gint16*)arg;
2886 p->regs [slot] = *(guint16*)arg;
2889 p->regs [slot] = *(gint32*)arg;
2892 p->regs [slot] = *(guint32*)arg;
2896 p->regs [slot ++] = (mgreg_t)arg [0];
2897 p->regs [slot] = (mgreg_t)arg [1];
2900 if (ainfo->storage == RegTypeFP) {
2901 float f = *(float*)arg;
2902 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2905 p->regs [slot] = *(mgreg_t*)arg;
2909 if (ainfo->storage == RegTypeFP) {
2910 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2913 p->regs [slot ++] = (mgreg_t)arg [0];
2914 p->regs [slot] = (mgreg_t)arg [1];
2917 case MONO_TYPE_GENERICINST:
2918 if (MONO_TYPE_IS_REFERENCE (t)) {
2919 p->regs [slot] = (mgreg_t)*arg;
2922 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2923 MonoClass *klass = mono_class_from_mono_type (t);
2924 guint8 *nullable_buf;
2927 size = mono_class_value_size (klass, NULL);
2928 nullable_buf = g_alloca (size);
2929 g_assert (nullable_buf);
2931 /* The argument pointed to by arg is either a boxed vtype or null */
2932 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2934 arg = (gpointer*)nullable_buf;
2940 case MONO_TYPE_VALUETYPE:
2941 g_assert (ainfo->storage == RegTypeStructByVal);
2943 if (ainfo->size == 0)
2944 slot = PARAM_REGS + (ainfo->offset / 4);
2948 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2949 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2952 g_assert_not_reached ();
2958 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2960 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2961 DynCallArgs *p = (DynCallArgs*)buf;
2962 MonoType *ptype = ainfo->rtype;
2963 guint8 *ret = p->ret;
2964 mgreg_t res = p->res;
2965 mgreg_t res2 = p->res2;
2967 switch (ptype->type) {
2968 case MONO_TYPE_VOID:
2969 *(gpointer*)ret = NULL;
2971 case MONO_TYPE_STRING:
2972 case MONO_TYPE_CLASS:
2973 case MONO_TYPE_ARRAY:
2974 case MONO_TYPE_SZARRAY:
2975 case MONO_TYPE_OBJECT:
2979 *(gpointer*)ret = (gpointer)res;
2985 *(guint8*)ret = res;
2988 *(gint16*)ret = res;
2991 *(guint16*)ret = res;
2994 *(gint32*)ret = res;
2997 *(guint32*)ret = res;
3001 /* This handles endianness as well */
3002 ((gint32*)ret) [0] = res;
3003 ((gint32*)ret) [1] = res2;
3005 case MONO_TYPE_GENERICINST:
3006 if (MONO_TYPE_IS_REFERENCE (ptype)) {
3007 *(gpointer*)ret = (gpointer)res;
3012 case MONO_TYPE_VALUETYPE:
3013 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
3019 *(float*)ret = *(float*)&p->fpregs [0];
3021 *(float*)ret = *(float*)&res;
3023 case MONO_TYPE_R8: {
3027 if (IS_HARD_FLOAT) {
3028 *(double*)ret = p->fpregs [0];
3033 *(double*)ret = *(double*)®s;
3038 g_assert_not_reached ();
3045 * Allow tracing to work with this interface (with an optional argument)
3049 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3053 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3054 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3055 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3056 code = emit_call_reg (code, ARMREG_R2);
3070 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3073 int save_mode = SAVE_NONE;
3075 MonoMethod *method = cfg->method;
3076 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3077 int rtype = ret_type->type;
3078 int save_offset = cfg->param_area;
3082 offset = code - cfg->native_code;
3083 /* we need about 16 instructions */
3084 if (offset > (cfg->code_size - 16 * 4)) {
3085 cfg->code_size *= 2;
3086 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3087 code = cfg->native_code + offset;
3090 case MONO_TYPE_VOID:
3091 /* special case string .ctor icall */
3092 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3093 save_mode = SAVE_ONE;
3095 save_mode = SAVE_NONE;
3099 save_mode = SAVE_TWO;
3103 save_mode = SAVE_ONE_FP;
3105 save_mode = SAVE_ONE;
3109 save_mode = SAVE_TWO_FP;
3111 save_mode = SAVE_TWO;
3113 case MONO_TYPE_GENERICINST:
3114 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3115 save_mode = SAVE_ONE;
3119 case MONO_TYPE_VALUETYPE:
3120 save_mode = SAVE_STRUCT;
3123 save_mode = SAVE_ONE;
3127 switch (save_mode) {
3129 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3130 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3131 if (enable_arguments) {
3132 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3133 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3137 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3138 if (enable_arguments) {
3139 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3143 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3144 if (enable_arguments) {
3145 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3149 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3150 if (enable_arguments) {
3151 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3155 if (enable_arguments) {
3156 /* FIXME: get the actual address */
3157 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3165 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3166 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3167 code = emit_call_reg (code, ARMREG_IP);
3169 switch (save_mode) {
3171 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3172 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3175 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3178 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3181 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3192 * The immediate field for cond branches is big enough for all reasonable methods
3194 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3195 if (0 && ins->inst_true_bb->native_offset) { \
3196 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3198 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3199 ARM_B_COND (code, (condcode), 0); \
3202 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3204 /* emit an exception if condition is fail
3206 * We assign the extra code used to throw the implicit exceptions
3207 * to cfg->bb_exit as far as the big branch handling is concerned
3209 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3211 mono_add_patch_info (cfg, code - cfg->native_code, \
3212 MONO_PATCH_INFO_EXC, exc_name); \
3213 ARM_BL_COND (code, (condcode), 0); \
3216 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3219 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3224 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3228 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3229 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3231 switch (ins->opcode) {
3234 /* Already done by an arch-independent pass */
3236 case OP_LOAD_MEMBASE:
3237 case OP_LOADI4_MEMBASE:
3239 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3240 * OP_LOAD_MEMBASE offset(basereg), reg
3242 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3243 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3244 ins->inst_basereg == last_ins->inst_destbasereg &&
3245 ins->inst_offset == last_ins->inst_offset) {
3246 if (ins->dreg == last_ins->sreg1) {
3247 MONO_DELETE_INS (bb, ins);
3250 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3251 ins->opcode = OP_MOVE;
3252 ins->sreg1 = last_ins->sreg1;
3256 * Note: reg1 must be different from the basereg in the second load
3257 * OP_LOAD_MEMBASE offset(basereg), reg1
3258 * OP_LOAD_MEMBASE offset(basereg), reg2
3260 * OP_LOAD_MEMBASE offset(basereg), reg1
3261 * OP_MOVE reg1, reg2
3263 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3264 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3265 ins->inst_basereg != last_ins->dreg &&
3266 ins->inst_basereg == last_ins->inst_basereg &&
3267 ins->inst_offset == last_ins->inst_offset) {
3269 if (ins->dreg == last_ins->dreg) {
3270 MONO_DELETE_INS (bb, ins);
3273 ins->opcode = OP_MOVE;
3274 ins->sreg1 = last_ins->dreg;
3277 //g_assert_not_reached ();
3281 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3282 * OP_LOAD_MEMBASE offset(basereg), reg
3284 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3285 * OP_ICONST reg, imm
3287 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3288 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3289 ins->inst_basereg == last_ins->inst_destbasereg &&
3290 ins->inst_offset == last_ins->inst_offset) {
3291 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3292 ins->opcode = OP_ICONST;
3293 ins->inst_c0 = last_ins->inst_imm;
3294 g_assert_not_reached (); // check this rule
3298 case OP_LOADU1_MEMBASE:
3299 case OP_LOADI1_MEMBASE:
3300 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3301 ins->inst_basereg == last_ins->inst_destbasereg &&
3302 ins->inst_offset == last_ins->inst_offset) {
3303 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3304 ins->sreg1 = last_ins->sreg1;
3307 case OP_LOADU2_MEMBASE:
3308 case OP_LOADI2_MEMBASE:
3309 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3310 ins->inst_basereg == last_ins->inst_destbasereg &&
3311 ins->inst_offset == last_ins->inst_offset) {
3312 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3313 ins->sreg1 = last_ins->sreg1;
3317 ins->opcode = OP_MOVE;
3321 if (ins->dreg == ins->sreg1) {
3322 MONO_DELETE_INS (bb, ins);
3326 * OP_MOVE sreg, dreg
3327 * OP_MOVE dreg, sreg
3329 if (last_ins && last_ins->opcode == OP_MOVE &&
3330 ins->sreg1 == last_ins->dreg &&
3331 ins->dreg == last_ins->sreg1) {
3332 MONO_DELETE_INS (bb, ins);
3341 * the branch_cc_table should maintain the order of these
3355 branch_cc_table [] = {
3369 #define ADD_NEW_INS(cfg,dest,op) do { \
3370 MONO_INST_NEW ((cfg), (dest), (op)); \
3371 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3375 map_to_reg_reg_op (int op)
3384 case OP_COMPARE_IMM:
3386 case OP_ICOMPARE_IMM:
3400 case OP_LOAD_MEMBASE:
3401 return OP_LOAD_MEMINDEX;
3402 case OP_LOADI4_MEMBASE:
3403 return OP_LOADI4_MEMINDEX;
3404 case OP_LOADU4_MEMBASE:
3405 return OP_LOADU4_MEMINDEX;
3406 case OP_LOADU1_MEMBASE:
3407 return OP_LOADU1_MEMINDEX;
3408 case OP_LOADI2_MEMBASE:
3409 return OP_LOADI2_MEMINDEX;
3410 case OP_LOADU2_MEMBASE:
3411 return OP_LOADU2_MEMINDEX;
3412 case OP_LOADI1_MEMBASE:
3413 return OP_LOADI1_MEMINDEX;
3414 case OP_STOREI1_MEMBASE_REG:
3415 return OP_STOREI1_MEMINDEX;
3416 case OP_STOREI2_MEMBASE_REG:
3417 return OP_STOREI2_MEMINDEX;
3418 case OP_STOREI4_MEMBASE_REG:
3419 return OP_STOREI4_MEMINDEX;
3420 case OP_STORE_MEMBASE_REG:
3421 return OP_STORE_MEMINDEX;
3422 case OP_STORER4_MEMBASE_REG:
3423 return OP_STORER4_MEMINDEX;
3424 case OP_STORER8_MEMBASE_REG:
3425 return OP_STORER8_MEMINDEX;
3426 case OP_STORE_MEMBASE_IMM:
3427 return OP_STORE_MEMBASE_REG;
3428 case OP_STOREI1_MEMBASE_IMM:
3429 return OP_STOREI1_MEMBASE_REG;
3430 case OP_STOREI2_MEMBASE_IMM:
3431 return OP_STOREI2_MEMBASE_REG;
3432 case OP_STOREI4_MEMBASE_IMM:
3433 return OP_STOREI4_MEMBASE_REG;
3435 g_assert_not_reached ();
3439 * Remove from the instruction list the instructions that can't be
3440 * represented with very simple instructions with no register
3444 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3446 MonoInst *ins, *temp, *last_ins = NULL;
3447 int rot_amount, imm8, low_imm;
3449 MONO_BB_FOR_EACH_INS (bb, ins) {
3451 switch (ins->opcode) {
3455 case OP_COMPARE_IMM:
3456 case OP_ICOMPARE_IMM:
3470 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3471 int opcode2 = mono_op_imm_to_op (ins->opcode);
3472 ADD_NEW_INS (cfg, temp, OP_ICONST);
3473 temp->inst_c0 = ins->inst_imm;
3474 temp->dreg = mono_alloc_ireg (cfg);
3475 ins->sreg2 = temp->dreg;
3477 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3478 ins->opcode = opcode2;
3480 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3486 if (ins->inst_imm == 1) {
3487 ins->opcode = OP_MOVE;
3490 if (ins->inst_imm == 0) {
3491 ins->opcode = OP_ICONST;
3495 imm8 = mono_is_power_of_two (ins->inst_imm);
3497 ins->opcode = OP_SHL_IMM;
3498 ins->inst_imm = imm8;
3501 ADD_NEW_INS (cfg, temp, OP_ICONST);
3502 temp->inst_c0 = ins->inst_imm;
3503 temp->dreg = mono_alloc_ireg (cfg);
3504 ins->sreg2 = temp->dreg;
3505 ins->opcode = OP_IMUL;
3511 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3512 /* ARM sets the C flag to 1 if there was _no_ overflow */
3513 ins->next->opcode = OP_COND_EXC_NC;
3516 case OP_IDIV_UN_IMM:
3518 case OP_IREM_UN_IMM: {
3519 int opcode2 = mono_op_imm_to_op (ins->opcode);
3520 ADD_NEW_INS (cfg, temp, OP_ICONST);
3521 temp->inst_c0 = ins->inst_imm;
3522 temp->dreg = mono_alloc_ireg (cfg);
3523 ins->sreg2 = temp->dreg;
3525 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3526 ins->opcode = opcode2;
3529 case OP_LOCALLOC_IMM:
3530 ADD_NEW_INS (cfg, temp, OP_ICONST);
3531 temp->inst_c0 = ins->inst_imm;
3532 temp->dreg = mono_alloc_ireg (cfg);
3533 ins->sreg1 = temp->dreg;
3534 ins->opcode = OP_LOCALLOC;
3536 case OP_LOAD_MEMBASE:
3537 case OP_LOADI4_MEMBASE:
3538 case OP_LOADU4_MEMBASE:
3539 case OP_LOADU1_MEMBASE:
3540 /* we can do two things: load the immed in a register
3541 * and use an indexed load, or see if the immed can be
3542 * represented as an ad_imm + a load with a smaller offset
3543 * that fits. We just do the first for now, optimize later.
3545 if (arm_is_imm12 (ins->inst_offset))
3547 ADD_NEW_INS (cfg, temp, OP_ICONST);
3548 temp->inst_c0 = ins->inst_offset;
3549 temp->dreg = mono_alloc_ireg (cfg);
3550 ins->sreg2 = temp->dreg;
3551 ins->opcode = map_to_reg_reg_op (ins->opcode);
3553 case OP_LOADI2_MEMBASE:
3554 case OP_LOADU2_MEMBASE:
3555 case OP_LOADI1_MEMBASE:
3556 if (arm_is_imm8 (ins->inst_offset))
3558 ADD_NEW_INS (cfg, temp, OP_ICONST);
3559 temp->inst_c0 = ins->inst_offset;
3560 temp->dreg = mono_alloc_ireg (cfg);
3561 ins->sreg2 = temp->dreg;
3562 ins->opcode = map_to_reg_reg_op (ins->opcode);
3564 case OP_LOADR4_MEMBASE:
3565 case OP_LOADR8_MEMBASE:
3566 if (arm_is_fpimm8 (ins->inst_offset))
3568 low_imm = ins->inst_offset & 0x1ff;
3569 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3570 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3571 temp->inst_imm = ins->inst_offset & ~0x1ff;
3572 temp->sreg1 = ins->inst_basereg;
3573 temp->dreg = mono_alloc_ireg (cfg);
3574 ins->inst_basereg = temp->dreg;
3575 ins->inst_offset = low_imm;
3579 ADD_NEW_INS (cfg, temp, OP_ICONST);
3580 temp->inst_c0 = ins->inst_offset;
3581 temp->dreg = mono_alloc_ireg (cfg);
3583 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3584 add_ins->sreg1 = ins->inst_basereg;
3585 add_ins->sreg2 = temp->dreg;
3586 add_ins->dreg = mono_alloc_ireg (cfg);
3588 ins->inst_basereg = add_ins->dreg;
3589 ins->inst_offset = 0;
3592 case OP_STORE_MEMBASE_REG:
3593 case OP_STOREI4_MEMBASE_REG:
3594 case OP_STOREI1_MEMBASE_REG:
3595 if (arm_is_imm12 (ins->inst_offset))
3597 ADD_NEW_INS (cfg, temp, OP_ICONST);
3598 temp->inst_c0 = ins->inst_offset;
3599 temp->dreg = mono_alloc_ireg (cfg);
3600 ins->sreg2 = temp->dreg;
3601 ins->opcode = map_to_reg_reg_op (ins->opcode);
3603 case OP_STOREI2_MEMBASE_REG:
3604 if (arm_is_imm8 (ins->inst_offset))
3606 ADD_NEW_INS (cfg, temp, OP_ICONST);
3607 temp->inst_c0 = ins->inst_offset;
3608 temp->dreg = mono_alloc_ireg (cfg);
3609 ins->sreg2 = temp->dreg;
3610 ins->opcode = map_to_reg_reg_op (ins->opcode);
3612 case OP_STORER4_MEMBASE_REG:
3613 case OP_STORER8_MEMBASE_REG:
3614 if (arm_is_fpimm8 (ins->inst_offset))
3616 low_imm = ins->inst_offset & 0x1ff;
3617 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3618 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3619 temp->inst_imm = ins->inst_offset & ~0x1ff;
3620 temp->sreg1 = ins->inst_destbasereg;
3621 temp->dreg = mono_alloc_ireg (cfg);
3622 ins->inst_destbasereg = temp->dreg;
3623 ins->inst_offset = low_imm;
3627 ADD_NEW_INS (cfg, temp, OP_ICONST);
3628 temp->inst_c0 = ins->inst_offset;
3629 temp->dreg = mono_alloc_ireg (cfg);
3631 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3632 add_ins->sreg1 = ins->inst_destbasereg;
3633 add_ins->sreg2 = temp->dreg;
3634 add_ins->dreg = mono_alloc_ireg (cfg);
3636 ins->inst_destbasereg = add_ins->dreg;
3637 ins->inst_offset = 0;
3640 case OP_STORE_MEMBASE_IMM:
3641 case OP_STOREI1_MEMBASE_IMM:
3642 case OP_STOREI2_MEMBASE_IMM:
3643 case OP_STOREI4_MEMBASE_IMM:
3644 ADD_NEW_INS (cfg, temp, OP_ICONST);
3645 temp->inst_c0 = ins->inst_imm;
3646 temp->dreg = mono_alloc_ireg (cfg);
3647 ins->sreg1 = temp->dreg;
3648 ins->opcode = map_to_reg_reg_op (ins->opcode);
3650 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3653 gboolean swap = FALSE;
3657 /* Optimized away */
3662 /* Some fp compares require swapped operands */
3663 switch (ins->next->opcode) {
3665 ins->next->opcode = OP_FBLT;
3669 ins->next->opcode = OP_FBLT_UN;
3673 ins->next->opcode = OP_FBGE;
3677 ins->next->opcode = OP_FBGE_UN;
3685 ins->sreg1 = ins->sreg2;
3694 bb->last_ins = last_ins;
3695 bb->max_vreg = cfg->next_vreg;
3699 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3703 if (long_ins->opcode == OP_LNEG) {
3705 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3706 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3712 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3714 /* sreg is a float, dreg is an integer reg */
3716 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3718 ARM_TOSIZD (code, vfp_scratch1, sreg);
3720 ARM_TOUIZD (code, vfp_scratch1, sreg);
3721 ARM_FMRS (code, dreg, vfp_scratch1);
3722 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3726 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3727 else if (size == 2) {
3728 ARM_SHL_IMM (code, dreg, dreg, 16);
3729 ARM_SHR_IMM (code, dreg, dreg, 16);
3733 ARM_SHL_IMM (code, dreg, dreg, 24);
3734 ARM_SAR_IMM (code, dreg, dreg, 24);
3735 } else if (size == 2) {
3736 ARM_SHL_IMM (code, dreg, dreg, 16);
3737 ARM_SAR_IMM (code, dreg, dreg, 16);
3744 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3746 /* sreg is a float, dreg is an integer reg */
3748 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3750 ARM_TOSIZS (code, vfp_scratch1, sreg);
3752 ARM_TOUIZS (code, vfp_scratch1, sreg);
3753 ARM_FMRS (code, dreg, vfp_scratch1);
3754 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3758 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3759 else if (size == 2) {
3760 ARM_SHL_IMM (code, dreg, dreg, 16);
3761 ARM_SHR_IMM (code, dreg, dreg, 16);
3765 ARM_SHL_IMM (code, dreg, dreg, 24);
3766 ARM_SAR_IMM (code, dreg, dreg, 24);
3767 } else if (size == 2) {
3768 ARM_SHL_IMM (code, dreg, dreg, 16);
3769 ARM_SAR_IMM (code, dreg, dreg, 16);
3775 #endif /* #ifndef DISABLE_JIT */
3777 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3780 emit_thunk (guint8 *code, gconstpointer target)
3784 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3785 if (thumb_supported)
3786 ARM_BX (code, ARMREG_IP);
3788 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3789 *(guint32*)code = (guint32)target;
3791 mono_arch_flush_icache (p, code - p);
3795 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3797 MonoJitInfo *ji = NULL;
3798 MonoThunkJitInfo *info;
3801 guint8 *orig_target;
3802 guint8 *target_thunk;
3805 domain = mono_domain_get ();
3809 * This can be called multiple times during JITting,
3810 * save the current position in cfg->arch to avoid
3811 * doing a O(n^2) search.
3813 if (!cfg->arch.thunks) {
3814 cfg->arch.thunks = cfg->thunks;
3815 cfg->arch.thunks_size = cfg->thunk_area;
3817 thunks = cfg->arch.thunks;
3818 thunks_size = cfg->arch.thunks_size;
3820 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3821 g_assert_not_reached ();
3824 g_assert (*(guint32*)thunks == 0);
3825 emit_thunk (thunks, target);
3826 arm_patch (code, thunks);
3828 cfg->arch.thunks += THUNK_SIZE;
3829 cfg->arch.thunks_size -= THUNK_SIZE;
3831 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3833 info = mono_jit_info_get_thunk_info (ji);
3836 thunks = (guint8*)ji->code_start + info->thunks_offset;
3837 thunks_size = info->thunks_size;
3839 orig_target = mono_arch_get_call_target (code + 4);
3841 mono_mini_arch_lock ();
3843 target_thunk = NULL;
3844 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3845 /* The call already points to a thunk, because of trampolines etc. */
3846 target_thunk = orig_target;
3848 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3849 if (((guint32*)p) [0] == 0) {
3853 } else if (((guint32*)p) [2] == (guint32)target) {
3854 /* Thunk already points to target */
3861 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3863 if (!target_thunk) {
3864 mono_mini_arch_unlock ();
3865 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3866 g_assert_not_reached ();
3869 emit_thunk (target_thunk, target);
3870 arm_patch (code, target_thunk);
3871 mono_arch_flush_icache (code, 4);
3873 mono_mini_arch_unlock ();
3878 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3880 guint32 *code32 = (void*)code;
3881 guint32 ins = *code32;
3882 guint32 prim = (ins >> 25) & 7;
3883 guint32 tval = GPOINTER_TO_UINT (target);
3885 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3886 if (prim == 5) { /* 101b */
3887 /* the diff starts 8 bytes from the branch opcode */
3888 gint diff = target - code - 8;
3890 gint tmask = 0xffffffff;
3891 if (tval & 1) { /* entering thumb mode */
3892 diff = target - 1 - code - 8;
3893 g_assert (thumb_supported);
3894 tbits = 0xf << 28; /* bl->blx bit pattern */
3895 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3896 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3900 tmask = ~(1 << 24); /* clear the link bit */
3901 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3906 if (diff <= 33554431) {
3908 ins = (ins & 0xff000000) | diff;
3910 *code32 = ins | tbits;
3914 /* diff between 0 and -33554432 */
3915 if (diff >= -33554432) {
3917 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3919 *code32 = ins | tbits;
3924 handle_thunk (cfg, domain, code, target);
3929 * The alternative call sequences looks like this:
3931 * ldr ip, [pc] // loads the address constant
3932 * b 1f // jumps around the constant
3933 * address constant embedded in the code
3938 * There are two cases for patching:
3939 * a) at the end of method emission: in this case code points to the start
3940 * of the call sequence
3941 * b) during runtime patching of the call site: in this case code points
3942 * to the mov pc, ip instruction
3944 * We have to handle also the thunk jump code sequence:
3948 * address constant // execution never reaches here
3950 if ((ins & 0x0ffffff0) == 0x12fff10) {
3951 /* Branch and exchange: the address is constructed in a reg
3952 * We can patch BX when the code sequence is the following:
3953 * ldr ip, [pc, #0] ; 0x8
3960 guint8 *emit = (guint8*)ccode;
3961 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3963 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3964 ARM_BX (emit, ARMREG_IP);
3966 /*patching from magic trampoline*/
3967 if (ins == ccode [3]) {
3968 g_assert (code32 [-4] == ccode [0]);
3969 g_assert (code32 [-3] == ccode [1]);
3970 g_assert (code32 [-1] == ccode [2]);
3971 code32 [-2] = (guint32)target;
3974 /*patching from JIT*/
3975 if (ins == ccode [0]) {
3976 g_assert (code32 [1] == ccode [1]);
3977 g_assert (code32 [3] == ccode [2]);
3978 g_assert (code32 [4] == ccode [3]);
3979 code32 [2] = (guint32)target;
3982 g_assert_not_reached ();
3983 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3991 guint8 *emit = (guint8*)ccode;
3992 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3994 ARM_BLX_REG (emit, ARMREG_IP);
3996 g_assert (code32 [-3] == ccode [0]);
3997 g_assert (code32 [-2] == ccode [1]);
3998 g_assert (code32 [0] == ccode [2]);
4000 code32 [-1] = (guint32)target;
4003 guint32 *tmp = ccode;
4004 guint8 *emit = (guint8*)tmp;
4005 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4006 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4007 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
4008 ARM_BX (emit, ARMREG_IP);
4009 if (ins == ccode [2]) {
4010 g_assert_not_reached (); // should be -2 ...
4011 code32 [-1] = (guint32)target;
4014 if (ins == ccode [0]) {
4015 /* handles both thunk jump code and the far call sequence */
4016 code32 [2] = (guint32)target;
4019 g_assert_not_reached ();
4021 // g_print ("patched with 0x%08x\n", ins);
4025 arm_patch (guchar *code, const guchar *target)
4027 arm_patch_general (NULL, NULL, code, target);
4031 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4032 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4033 * to be used with the emit macros.
4034 * Return -1 otherwise.
4037 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4040 for (i = 0; i < 31; i+= 2) {
4041 res = (val << (32 - i)) | (val >> i);
4044 *rot_amount = i? 32 - i: 0;
4051 * Emits in code a sequence of instructions that load the value 'val'
4052 * into the dreg register. Uses at most 4 instructions.
4055 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4057 int imm8, rot_amount;
4059 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4060 /* skip the constant pool */
4066 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4067 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4068 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4072 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4073 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4074 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4075 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4078 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4080 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4084 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4086 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4088 if (val & 0xFF0000) {
4089 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4091 if (val & 0xFF000000) {
4092 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4094 } else if (val & 0xFF00) {
4095 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4096 if (val & 0xFF0000) {
4097 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4099 if (val & 0xFF000000) {
4100 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4102 } else if (val & 0xFF0000) {
4103 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4104 if (val & 0xFF000000) {
4105 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4108 //g_assert_not_reached ();
4114 mono_arm_thumb_supported (void)
4116 return thumb_supported;
4122 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4127 call = (MonoCallInst*)ins;
4128 cinfo = call->call_info;
4130 switch (cinfo->ret.storage) {
4131 case RegTypeStructByVal:
4133 MonoInst *loc = cfg->arch.vret_addr_loc;
4136 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4137 /* The JIT treats this as a normal call */
4141 /* Load the destination address */
4142 g_assert (loc && loc->opcode == OP_REGOFFSET);
4144 if (arm_is_imm12 (loc->inst_offset)) {
4145 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4147 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4148 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4151 if (cinfo->ret.storage == RegTypeStructByVal) {
4152 int rsize = cinfo->ret.struct_size;
4154 for (i = 0; i < cinfo->ret.nregs; ++i) {
4155 g_assert (rsize >= 0);
4160 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4163 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4166 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4172 for (i = 0; i < cinfo->ret.nregs; ++i) {
4173 if (cinfo->ret.esize == 4)
4174 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4176 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4185 switch (ins->opcode) {
4188 case OP_FCALL_MEMBASE:
4190 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4191 if (sig_ret->type == MONO_TYPE_R4) {
4192 if (IS_HARD_FLOAT) {
4193 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4195 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4196 ARM_CVTS (code, ins->dreg, ins->dreg);
4199 if (IS_HARD_FLOAT) {
4200 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4202 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4209 case OP_RCALL_MEMBASE: {
4214 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4215 g_assert (sig_ret->type == MONO_TYPE_R4);
4216 if (IS_HARD_FLOAT) {
4217 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4219 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4220 ARM_CPYS (code, ins->dreg, ins->dreg);
4232 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4237 guint8 *code = cfg->native_code + cfg->code_len;
4238 MonoInst *last_ins = NULL;
4239 guint last_offset = 0;
4241 int imm8, rot_amount;
4243 /* we don't align basic blocks of loops on arm */
4245 if (cfg->verbose_level > 2)
4246 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4248 cpos = bb->max_offset;
4250 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4251 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4252 //g_assert (!mono_compile_aot);
4255 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4256 /* this is not thread save, but good enough */
4257 /* fixme: howto handle overflows? */
4258 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4261 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4262 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4263 (gpointer)"mono_break");
4264 code = emit_call_seq (cfg, code);
4267 MONO_BB_FOR_EACH_INS (bb, ins) {
4268 offset = code - cfg->native_code;
4270 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4272 if (offset > (cfg->code_size - max_len - 16)) {
4273 cfg->code_size *= 2;
4274 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4275 code = cfg->native_code + offset;
4277 // if (ins->cil_code)
4278 // g_print ("cil code\n");
4279 mono_debug_record_line_number (cfg, ins, offset);
4281 switch (ins->opcode) {
4282 case OP_MEMORY_BARRIER:
4284 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4285 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4289 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4291 case OP_TLS_GET_REG:
4292 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4295 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4297 case OP_TLS_SET_REG:
4298 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4300 case OP_ATOMIC_EXCHANGE_I4:
4301 case OP_ATOMIC_CAS_I4:
4302 case OP_ATOMIC_ADD_I4: {
4306 g_assert (v7_supported);
4309 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4311 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4313 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4317 g_assert (cfg->arch.atomic_tmp_offset != -1);
4318 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4320 switch (ins->opcode) {
4321 case OP_ATOMIC_EXCHANGE_I4:
4323 ARM_DMB (code, ARM_DMB_SY);
4324 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4325 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4326 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4328 ARM_B_COND (code, ARMCOND_NE, 0);
4329 arm_patch (buf [1], buf [0]);
4331 case OP_ATOMIC_CAS_I4:
4332 ARM_DMB (code, ARM_DMB_SY);
4334 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4335 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4337 ARM_B_COND (code, ARMCOND_NE, 0);
4338 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4339 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4341 ARM_B_COND (code, ARMCOND_NE, 0);
4342 arm_patch (buf [2], buf [0]);
4343 arm_patch (buf [1], code);
4345 case OP_ATOMIC_ADD_I4:
4347 ARM_DMB (code, ARM_DMB_SY);
4348 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4349 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4350 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4351 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4353 ARM_B_COND (code, ARMCOND_NE, 0);
4354 arm_patch (buf [1], buf [0]);
4357 g_assert_not_reached ();
4360 ARM_DMB (code, ARM_DMB_SY);
4361 if (tmpreg != ins->dreg)
4362 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4363 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4366 case OP_ATOMIC_LOAD_I1:
4367 case OP_ATOMIC_LOAD_U1:
4368 case OP_ATOMIC_LOAD_I2:
4369 case OP_ATOMIC_LOAD_U2:
4370 case OP_ATOMIC_LOAD_I4:
4371 case OP_ATOMIC_LOAD_U4:
4372 case OP_ATOMIC_LOAD_R4:
4373 case OP_ATOMIC_LOAD_R8: {
4374 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4375 ARM_DMB (code, ARM_DMB_SY);
4377 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4379 switch (ins->opcode) {
4380 case OP_ATOMIC_LOAD_I1:
4381 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4383 case OP_ATOMIC_LOAD_U1:
4384 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4386 case OP_ATOMIC_LOAD_I2:
4387 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4389 case OP_ATOMIC_LOAD_U2:
4390 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4392 case OP_ATOMIC_LOAD_I4:
4393 case OP_ATOMIC_LOAD_U4:
4394 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4396 case OP_ATOMIC_LOAD_R4:
4398 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4399 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4401 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4402 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4403 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4404 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4405 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4408 case OP_ATOMIC_LOAD_R8:
4409 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4410 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4414 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4415 ARM_DMB (code, ARM_DMB_SY);
4418 case OP_ATOMIC_STORE_I1:
4419 case OP_ATOMIC_STORE_U1:
4420 case OP_ATOMIC_STORE_I2:
4421 case OP_ATOMIC_STORE_U2:
4422 case OP_ATOMIC_STORE_I4:
4423 case OP_ATOMIC_STORE_U4:
4424 case OP_ATOMIC_STORE_R4:
4425 case OP_ATOMIC_STORE_R8: {
4426 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4427 ARM_DMB (code, ARM_DMB_SY);
4429 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4431 switch (ins->opcode) {
4432 case OP_ATOMIC_STORE_I1:
4433 case OP_ATOMIC_STORE_U1:
4434 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4436 case OP_ATOMIC_STORE_I2:
4437 case OP_ATOMIC_STORE_U2:
4438 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4440 case OP_ATOMIC_STORE_I4:
4441 case OP_ATOMIC_STORE_U4:
4442 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4444 case OP_ATOMIC_STORE_R4:
4446 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4447 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4449 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4450 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4451 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4452 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4453 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4456 case OP_ATOMIC_STORE_R8:
4457 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4458 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4462 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4463 ARM_DMB (code, ARM_DMB_SY);
4467 ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4470 ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4472 case OP_STOREI1_MEMBASE_IMM:
4473 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4474 g_assert (arm_is_imm12 (ins->inst_offset));
4475 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4477 case OP_STOREI2_MEMBASE_IMM:
4478 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4479 g_assert (arm_is_imm8 (ins->inst_offset));
4480 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4482 case OP_STORE_MEMBASE_IMM:
4483 case OP_STOREI4_MEMBASE_IMM:
4484 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4485 g_assert (arm_is_imm12 (ins->inst_offset));
4486 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4488 case OP_STOREI1_MEMBASE_REG:
4489 g_assert (arm_is_imm12 (ins->inst_offset));
4490 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4492 case OP_STOREI2_MEMBASE_REG:
4493 g_assert (arm_is_imm8 (ins->inst_offset));
4494 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4496 case OP_STORE_MEMBASE_REG:
4497 case OP_STOREI4_MEMBASE_REG:
4498 /* this case is special, since it happens for spill code after lowering has been called */
4499 if (arm_is_imm12 (ins->inst_offset)) {
4500 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4502 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4503 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4506 case OP_STOREI1_MEMINDEX:
4507 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4509 case OP_STOREI2_MEMINDEX:
4510 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4512 case OP_STORE_MEMINDEX:
4513 case OP_STOREI4_MEMINDEX:
4514 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4517 g_assert_not_reached ();
4519 case OP_LOAD_MEMINDEX:
4520 case OP_LOADI4_MEMINDEX:
4521 case OP_LOADU4_MEMINDEX:
4522 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4524 case OP_LOADI1_MEMINDEX:
4525 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4527 case OP_LOADU1_MEMINDEX:
4528 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4530 case OP_LOADI2_MEMINDEX:
4531 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4533 case OP_LOADU2_MEMINDEX:
4534 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4536 case OP_LOAD_MEMBASE:
4537 case OP_LOADI4_MEMBASE:
4538 case OP_LOADU4_MEMBASE:
4539 /* this case is special, since it happens for spill code after lowering has been called */
4540 if (arm_is_imm12 (ins->inst_offset)) {
4541 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4543 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4544 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4547 case OP_LOADI1_MEMBASE:
4548 g_assert (arm_is_imm8 (ins->inst_offset));
4549 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4551 case OP_LOADU1_MEMBASE:
4552 g_assert (arm_is_imm12 (ins->inst_offset));
4553 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4555 case OP_LOADU2_MEMBASE:
4556 g_assert (arm_is_imm8 (ins->inst_offset));
4557 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4559 case OP_LOADI2_MEMBASE:
4560 g_assert (arm_is_imm8 (ins->inst_offset));
4561 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4563 case OP_ICONV_TO_I1:
4564 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4565 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4567 case OP_ICONV_TO_I2:
4568 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4569 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4571 case OP_ICONV_TO_U1:
4572 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4574 case OP_ICONV_TO_U2:
4575 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4576 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4580 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4582 case OP_COMPARE_IMM:
4583 case OP_ICOMPARE_IMM:
4584 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4585 g_assert (imm8 >= 0);
4586 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4590 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4591 * So instead of emitting a trap, we emit a call a C function and place a
4594 //*(int*)code = 0xef9f0001;
4597 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4598 (gpointer)"mono_break");
4599 code = emit_call_seq (cfg, code);
4601 case OP_RELAXED_NOP:
4606 case OP_DUMMY_STORE:
4607 case OP_DUMMY_ICONST:
4608 case OP_DUMMY_R8CONST:
4609 case OP_NOT_REACHED:
4612 case OP_IL_SEQ_POINT:
4613 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4615 case OP_SEQ_POINT: {
4617 MonoInst *info_var = cfg->arch.seq_point_info_var;
4618 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4619 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4620 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4622 int dreg = ARMREG_LR;
4625 if (cfg->soft_breakpoints) {
4626 g_assert (!cfg->compile_aot);
4631 * For AOT, we use one got slot per method, which will point to a
4632 * SeqPointInfo structure, containing all the information required
4633 * by the code below.
4635 if (cfg->compile_aot) {
4636 g_assert (info_var);
4637 g_assert (info_var->opcode == OP_REGOFFSET);
4638 g_assert (arm_is_imm12 (info_var->inst_offset));
4641 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4643 * Read from the single stepping trigger page. This will cause a
4644 * SIGSEGV when single stepping is enabled.
4645 * We do this _before_ the breakpoint, so single stepping after
4646 * a breakpoint is hit will step to the next IL offset.
4648 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4651 /* Single step check */
4652 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4653 if (cfg->soft_breakpoints) {
4654 /* Load the address of the sequence point method variable. */
4655 var = ss_method_var;
4657 g_assert (var->opcode == OP_REGOFFSET);
4658 g_assert (arm_is_imm12 (var->inst_offset));
4659 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4661 /* Read the value and check whether it is non-zero. */
4662 ARM_LDR_IMM (code, dreg, dreg, 0);
4663 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4664 /* Call it conditionally. */
4665 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4667 if (cfg->compile_aot) {
4668 /* Load the trigger page addr from the variable initialized in the prolog */
4669 var = ss_trigger_page_var;
4671 g_assert (var->opcode == OP_REGOFFSET);
4672 g_assert (arm_is_imm12 (var->inst_offset));
4673 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4675 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4677 *(int*)code = (int)ss_trigger_page;
4680 ARM_LDR_IMM (code, dreg, dreg, 0);
4684 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4686 /* Breakpoint check */
4687 if (cfg->compile_aot) {
4688 guint32 offset = code - cfg->native_code;
4691 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4692 /* Add the offset */
4693 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4694 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4695 if (arm_is_imm12 ((int)val)) {
4696 ARM_LDR_IMM (code, dreg, dreg, val);
4698 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4700 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4702 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4703 g_assert (!(val & 0xFF000000));
4705 ARM_LDR_IMM (code, dreg, dreg, 0);
4707 /* What is faster, a branch or a load ? */
4708 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4709 /* The breakpoint instruction */
4710 if (cfg->soft_breakpoints)
4711 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4713 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4714 } else if (cfg->soft_breakpoints) {
4715 /* Load the address of the breakpoint method into ip. */
4716 var = bp_method_var;
4718 g_assert (var->opcode == OP_REGOFFSET);
4719 g_assert (arm_is_imm12 (var->inst_offset));
4720 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4723 * A placeholder for a possible breakpoint inserted by
4724 * mono_arch_set_breakpoint ().
4729 * A placeholder for a possible breakpoint inserted by
4730 * mono_arch_set_breakpoint ().
4732 for (i = 0; i < 4; ++i)
4737 * Add an additional nop so skipping the bp doesn't cause the ip to point
4738 * to another IL offset.
4746 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4749 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4753 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4756 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4757 g_assert (imm8 >= 0);
4758 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4762 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4763 g_assert (imm8 >= 0);
4764 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4768 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4769 g_assert (imm8 >= 0);
4770 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4773 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4774 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4776 case OP_IADD_OVF_UN:
4777 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4778 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4781 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4782 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4784 case OP_ISUB_OVF_UN:
4785 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4786 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4788 case OP_ADD_OVF_CARRY:
4789 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4790 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4792 case OP_ADD_OVF_UN_CARRY:
4793 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4794 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4796 case OP_SUB_OVF_CARRY:
4797 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4798 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4800 case OP_SUB_OVF_UN_CARRY:
4801 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4802 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4806 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4809 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4810 g_assert (imm8 >= 0);
4811 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4814 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4818 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4822 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4823 g_assert (imm8 >= 0);
4824 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4828 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4829 g_assert (imm8 >= 0);
4830 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4832 case OP_ARM_RSBS_IMM:
4833 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4834 g_assert (imm8 >= 0);
4835 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4837 case OP_ARM_RSC_IMM:
4838 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4839 g_assert (imm8 >= 0);
4840 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4843 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4847 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4848 g_assert (imm8 >= 0);
4849 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4852 g_assert (v7s_supported || v7k_supported);
4853 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4856 g_assert (v7s_supported || v7k_supported);
4857 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4860 g_assert (v7s_supported || v7k_supported);
4861 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4862 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4865 g_assert (v7s_supported || v7k_supported);
4866 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4867 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4871 g_assert_not_reached ();
4873 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4877 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4878 g_assert (imm8 >= 0);
4879 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4882 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4886 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4887 g_assert (imm8 >= 0);
4888 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4891 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4896 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4897 else if (ins->dreg != ins->sreg1)
4898 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4901 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4906 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4907 else if (ins->dreg != ins->sreg1)
4908 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4911 case OP_ISHR_UN_IMM:
4913 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4914 else if (ins->dreg != ins->sreg1)
4915 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4918 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4921 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4924 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4927 if (ins->dreg == ins->sreg2)
4928 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4930 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4933 g_assert_not_reached ();
4936 /* FIXME: handle ovf/ sreg2 != dreg */
4937 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4938 /* FIXME: MUL doesn't set the C/O flags on ARM */
4940 case OP_IMUL_OVF_UN:
4941 /* FIXME: handle ovf/ sreg2 != dreg */
4942 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4943 /* FIXME: MUL doesn't set the C/O flags on ARM */
4946 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4949 /* Load the GOT offset */
4950 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4951 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4953 *(gpointer*)code = NULL;
4955 /* Load the value from the GOT */
4956 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4958 case OP_OBJC_GET_SELECTOR:
4959 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4960 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4962 *(gpointer*)code = NULL;
4964 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4966 case OP_ICONV_TO_I4:
4967 case OP_ICONV_TO_U4:
4969 if (ins->dreg != ins->sreg1)
4970 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4973 int saved = ins->sreg2;
4974 if (ins->sreg2 == ARM_LSW_REG) {
4975 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4978 if (ins->sreg1 != ARM_LSW_REG)
4979 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4980 if (saved != ARM_MSW_REG)
4981 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4985 if (IS_VFP && ins->dreg != ins->sreg1)
4986 ARM_CPYD (code, ins->dreg, ins->sreg1);
4989 if (IS_VFP && ins->dreg != ins->sreg1)
4990 ARM_CPYS (code, ins->dreg, ins->sreg1);
4992 case OP_MOVE_F_TO_I4:
4994 ARM_FMRS (code, ins->dreg, ins->sreg1);
4996 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4997 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4998 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4999 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5002 case OP_MOVE_I4_TO_F:
5004 ARM_FMSR (code, ins->dreg, ins->sreg1);
5006 ARM_FMSR (code, ins->dreg, ins->sreg1);
5007 ARM_CVTS (code, ins->dreg, ins->dreg);
5010 case OP_FCONV_TO_R4:
5013 ARM_CVTD (code, ins->dreg, ins->sreg1);
5015 ARM_CVTD (code, ins->dreg, ins->sreg1);
5016 ARM_CVTS (code, ins->dreg, ins->dreg);
5021 MonoCallInst *call = (MonoCallInst*)ins;
5024 * The stack looks like the following:
5025 * <caller argument area>
5028 * <callee argument area>
5029 * Need to copy the arguments from the callee argument area to
5030 * the caller argument area, and pop the frame.
5032 if (call->stack_usage) {
5033 int i, prev_sp_offset = 0;
5035 /* Compute size of saved registers restored below */
5037 prev_sp_offset = 2 * 4;
5039 prev_sp_offset = 1 * 4;
5040 for (i = 0; i < 16; ++i) {
5041 if (cfg->used_int_regs & (1 << i))
5042 prev_sp_offset += 4;
5045 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5047 /* Copy arguments on the stack to our argument area */
5048 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5049 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5050 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5055 * Keep in sync with mono_arch_emit_epilog
5057 g_assert (!cfg->method->save_lmf);
5059 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5061 if (cfg->used_int_regs)
5062 ARM_POP (code, cfg->used_int_regs);
5063 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5065 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5068 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5069 if (cfg->compile_aot) {
5070 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5072 *(gpointer*)code = NULL;
5074 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5076 code = mono_arm_patchable_b (code, ARMCOND_AL);
5077 cfg->thunk_area += THUNK_SIZE;
5082 /* ensure ins->sreg1 is not NULL */
5083 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5086 g_assert (cfg->sig_cookie < 128);
5087 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5088 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5098 call = (MonoCallInst*)ins;
5101 code = emit_float_args (cfg, call, code, &max_len, &offset);
5103 if (ins->flags & MONO_INST_HAS_METHOD)
5104 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5106 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5107 code = emit_call_seq (cfg, code);
5108 ins->flags |= MONO_INST_GC_CALLSITE;
5109 ins->backend.pc_offset = code - cfg->native_code;
5110 code = emit_move_return_value (cfg, ins, code);
5117 case OP_VOIDCALL_REG:
5120 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5122 code = emit_call_reg (code, ins->sreg1);
5123 ins->flags |= MONO_INST_GC_CALLSITE;
5124 ins->backend.pc_offset = code - cfg->native_code;
5125 code = emit_move_return_value (cfg, ins, code);
5127 case OP_FCALL_MEMBASE:
5128 case OP_RCALL_MEMBASE:
5129 case OP_LCALL_MEMBASE:
5130 case OP_VCALL_MEMBASE:
5131 case OP_VCALL2_MEMBASE:
5132 case OP_VOIDCALL_MEMBASE:
5133 case OP_CALL_MEMBASE: {
5134 g_assert (ins->sreg1 != ARMREG_LR);
5135 call = (MonoCallInst*)ins;
5138 code = emit_float_args (cfg, call, code, &max_len, &offset);
5139 if (!arm_is_imm12 (ins->inst_offset)) {
5140 /* sreg1 might be IP */
5141 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5142 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5143 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5144 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5145 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5147 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5148 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5150 ins->flags |= MONO_INST_GC_CALLSITE;
5151 ins->backend.pc_offset = code - cfg->native_code;
5152 code = emit_move_return_value (cfg, ins, code);
5155 case OP_GENERIC_CLASS_INIT: {
5156 static int byte_offset = -1;
5157 static guint8 bitmask;
5161 if (byte_offset < 0)
5162 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5164 g_assert (arm_is_imm8 (byte_offset));
5165 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5166 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5167 g_assert (imm8 >= 0);
5168 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5169 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5171 ARM_B_COND (code, ARMCOND_NE, 0);
5173 /* Uninitialized case */
5174 g_assert (ins->sreg1 == ARMREG_R0);
5176 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5177 (gpointer)"mono_generic_class_init");
5178 code = emit_call_seq (cfg, code);
5180 /* Initialized case */
5181 arm_patch (jump, code);
5185 /* round the size to 8 bytes */
5186 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5187 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5188 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5189 /* memzero the area: dreg holds the size, sp is the pointer */
5190 if (ins->flags & MONO_INST_INIT) {
5191 guint8 *start_loop, *branch_to_cond;
5192 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5193 branch_to_cond = code;
5196 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5197 arm_patch (branch_to_cond, code);
5198 /* decrement by 4 and set flags */
5199 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5200 ARM_B_COND (code, ARMCOND_GE, 0);
5201 arm_patch (code - 4, start_loop);
5203 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5204 if (cfg->param_area)
5205 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5210 MonoInst *var = cfg->dyn_call_var;
5213 g_assert (var->opcode == OP_REGOFFSET);
5214 g_assert (arm_is_imm12 (var->inst_offset));
5216 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5217 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5219 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5221 /* Save args buffer */
5222 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5224 /* Set stack slots using R0 as scratch reg */
5225 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5226 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5227 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5228 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5231 /* Set fp argument registers */
5232 if (IS_HARD_FLOAT) {
5233 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5234 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5236 ARM_B_COND (code, ARMCOND_EQ, 0);
5237 for (i = 0; i < FP_PARAM_REGS; ++i) {
5238 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5239 g_assert (arm_is_fpimm8 (offset));
5240 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5242 arm_patch (buf [0], code);
5245 /* Set argument registers */
5246 for (i = 0; i < PARAM_REGS; ++i)
5247 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5250 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5251 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5254 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5255 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5256 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5258 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5262 if (ins->sreg1 != ARMREG_R0)
5263 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5264 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5265 (gpointer)"mono_arch_throw_exception");
5266 code = emit_call_seq (cfg, code);
5270 if (ins->sreg1 != ARMREG_R0)
5271 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5272 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5273 (gpointer)"mono_arch_rethrow_exception");
5274 code = emit_call_seq (cfg, code);
5277 case OP_START_HANDLER: {
5278 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5279 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5282 /* Reserve a param area, see filter-stack.exe */
5284 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5285 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5287 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5288 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5292 if (arm_is_imm12 (spvar->inst_offset)) {
5293 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5295 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5296 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5300 case OP_ENDFILTER: {
5301 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5302 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5305 /* Free the param area */
5307 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5308 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5310 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5311 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5315 if (ins->sreg1 != ARMREG_R0)
5316 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5317 if (arm_is_imm12 (spvar->inst_offset)) {
5318 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5320 g_assert (ARMREG_IP != spvar->inst_basereg);
5321 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5322 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5324 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5327 case OP_ENDFINALLY: {
5328 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5329 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5332 /* Free the param area */
5334 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5335 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5337 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5338 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5342 if (arm_is_imm12 (spvar->inst_offset)) {
5343 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5345 g_assert (ARMREG_IP != spvar->inst_basereg);
5346 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5347 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5349 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5352 case OP_CALL_HANDLER:
5353 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5354 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5355 cfg->thunk_area += THUNK_SIZE;
5356 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5359 if (ins->dreg != ARMREG_R0)
5360 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5364 ins->inst_c0 = code - cfg->native_code;
5367 /*if (ins->inst_target_bb->native_offset) {
5369 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5371 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5372 code = mono_arm_patchable_b (code, ARMCOND_AL);
5376 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5380 * In the normal case we have:
5381 * ldr pc, [pc, ins->sreg1 << 2]
5384 * ldr lr, [pc, ins->sreg1 << 2]
5386 * After follows the data.
5387 * FIXME: add aot support.
5389 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5390 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5391 if (offset + max_len > (cfg->code_size - 16)) {
5392 cfg->code_size += max_len;
5393 cfg->code_size *= 2;
5394 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5395 code = cfg->native_code + offset;
5397 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5399 code += 4 * GPOINTER_TO_INT (ins->klass);
5403 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5404 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5408 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5409 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5413 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5414 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5418 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5419 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5423 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5424 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5427 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5428 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5431 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5432 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5435 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5436 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5439 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5440 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5443 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5444 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5446 case OP_COND_EXC_EQ:
5447 case OP_COND_EXC_NE_UN:
5448 case OP_COND_EXC_LT:
5449 case OP_COND_EXC_LT_UN:
5450 case OP_COND_EXC_GT:
5451 case OP_COND_EXC_GT_UN:
5452 case OP_COND_EXC_GE:
5453 case OP_COND_EXC_GE_UN:
5454 case OP_COND_EXC_LE:
5455 case OP_COND_EXC_LE_UN:
5456 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5458 case OP_COND_EXC_IEQ:
5459 case OP_COND_EXC_INE_UN:
5460 case OP_COND_EXC_ILT:
5461 case OP_COND_EXC_ILT_UN:
5462 case OP_COND_EXC_IGT:
5463 case OP_COND_EXC_IGT_UN:
5464 case OP_COND_EXC_IGE:
5465 case OP_COND_EXC_IGE_UN:
5466 case OP_COND_EXC_ILE:
5467 case OP_COND_EXC_ILE_UN:
5468 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5471 case OP_COND_EXC_IC:
5472 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5474 case OP_COND_EXC_OV:
5475 case OP_COND_EXC_IOV:
5476 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5478 case OP_COND_EXC_NC:
5479 case OP_COND_EXC_INC:
5480 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5482 case OP_COND_EXC_NO:
5483 case OP_COND_EXC_INO:
5484 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5496 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5499 /* floating point opcodes */
5501 if (cfg->compile_aot) {
5502 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5504 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5506 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5509 /* FIXME: we can optimize the imm load by dealing with part of
5510 * the displacement in LDFD (aligning to 512).
5512 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5513 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5517 if (cfg->compile_aot) {
5518 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5520 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5523 ARM_CVTS (code, ins->dreg, ins->dreg);
5525 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5526 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5528 ARM_CVTS (code, ins->dreg, ins->dreg);
5531 case OP_STORER8_MEMBASE_REG:
5532 /* This is generated by the local regalloc pass which runs after the lowering pass */
5533 if (!arm_is_fpimm8 (ins->inst_offset)) {
5534 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5535 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5536 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5538 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5541 case OP_LOADR8_MEMBASE:
5542 /* This is generated by the local regalloc pass which runs after the lowering pass */
5543 if (!arm_is_fpimm8 (ins->inst_offset)) {
5544 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5545 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5546 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5548 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5551 case OP_STORER4_MEMBASE_REG:
5552 g_assert (arm_is_fpimm8 (ins->inst_offset));
5554 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5556 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5557 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5558 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5559 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5562 case OP_LOADR4_MEMBASE:
5564 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5566 g_assert (arm_is_fpimm8 (ins->inst_offset));
5567 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5568 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5569 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5570 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5573 case OP_ICONV_TO_R_UN: {
5574 g_assert_not_reached ();
5577 case OP_ICONV_TO_R4:
5579 ARM_FMSR (code, ins->dreg, ins->sreg1);
5580 ARM_FSITOS (code, ins->dreg, ins->dreg);
5582 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5583 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5584 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5585 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5586 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5589 case OP_ICONV_TO_R8:
5590 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5591 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5592 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5593 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5597 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5598 if (sig_ret->type == MONO_TYPE_R4) {
5600 if (IS_HARD_FLOAT) {
5601 if (ins->sreg1 != ARM_VFP_D0)
5602 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5604 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5607 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5610 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5614 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5616 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5620 case OP_FCONV_TO_I1:
5621 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5623 case OP_FCONV_TO_U1:
5624 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5626 case OP_FCONV_TO_I2:
5627 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5629 case OP_FCONV_TO_U2:
5630 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5632 case OP_FCONV_TO_I4:
5634 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5636 case OP_FCONV_TO_U4:
5638 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5640 case OP_FCONV_TO_I8:
5641 case OP_FCONV_TO_U8:
5642 g_assert_not_reached ();
5643 /* Implemented as helper calls */
5645 case OP_LCONV_TO_R_UN:
5646 g_assert_not_reached ();
5647 /* Implemented as helper calls */
5649 case OP_LCONV_TO_OVF_I4_2: {
5650 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5652 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5655 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5656 high_bit_not_set = code;
5657 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5659 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5660 valid_negative = code;
5661 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5662 invalid_negative = code;
5663 ARM_B_COND (code, ARMCOND_AL, 0);
5665 arm_patch (high_bit_not_set, code);
5667 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5668 valid_positive = code;
5669 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5671 arm_patch (invalid_negative, code);
5672 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5674 arm_patch (valid_negative, code);
5675 arm_patch (valid_positive, code);
5677 if (ins->dreg != ins->sreg1)
5678 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5682 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5685 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5688 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5691 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5694 ARM_NEGD (code, ins->dreg, ins->sreg1);
5698 g_assert_not_reached ();
5702 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5708 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5713 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5716 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5717 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5721 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5724 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5725 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5729 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5732 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5733 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5734 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5738 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5741 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5742 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5746 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5749 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5750 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5751 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5755 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5758 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5759 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5763 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5766 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5767 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5771 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5774 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5775 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5778 /* ARM FPA flags table:
5779 * N Less than ARMCOND_MI
5780 * Z Equal ARMCOND_EQ
5781 * C Greater Than or Equal ARMCOND_CS
5782 * V Unordered ARMCOND_VS
5785 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5788 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5791 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5794 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5795 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5801 g_assert_not_reached ();
5805 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5807 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5808 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5809 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5813 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5814 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5819 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5820 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5822 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5823 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5825 *(guint32*)code = 0xffffffff;
5827 *(guint32*)code = 0x7fefffff;
5829 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5831 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5832 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5834 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5835 ARM_CPYD (code, ins->dreg, ins->sreg1);
5837 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5838 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5843 case OP_RCONV_TO_I1:
5844 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5846 case OP_RCONV_TO_U1:
5847 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5849 case OP_RCONV_TO_I2:
5850 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5852 case OP_RCONV_TO_U2:
5853 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5855 case OP_RCONV_TO_I4:
5856 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5858 case OP_RCONV_TO_U4:
5859 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5861 case OP_RCONV_TO_R4:
5863 if (ins->dreg != ins->sreg1)
5864 ARM_CPYS (code, ins->dreg, ins->sreg1);
5866 case OP_RCONV_TO_R8:
5868 ARM_CVTS (code, ins->dreg, ins->sreg1);
5871 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5874 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5877 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5880 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5883 ARM_NEGS (code, ins->dreg, ins->sreg1);
5887 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5890 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5891 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5895 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5898 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5899 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5903 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5906 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5907 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5908 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5912 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5915 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5916 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5920 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5923 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5924 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5925 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5929 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5932 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5933 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5937 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5940 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5941 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5945 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5948 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5949 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5952 case OP_GC_LIVENESS_DEF:
5953 case OP_GC_LIVENESS_USE:
5954 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5955 ins->backend.pc_offset = code - cfg->native_code;
5957 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5958 ins->backend.pc_offset = code - cfg->native_code;
5959 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5961 case OP_GC_SAFE_POINT: {
5964 g_assert (mono_threads_is_coop_enabled ());
5966 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5967 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5969 ARM_B_COND (code, ARMCOND_EQ, 0);
5970 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5971 code = emit_call_seq (cfg, code);
5972 arm_patch (buf [0], code);
5977 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5978 g_assert_not_reached ();
5981 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5982 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5983 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5984 g_assert_not_reached ();
5990 last_offset = offset;
5993 cfg->code_len = code - cfg->native_code;
5996 #endif /* DISABLE_JIT */
5999 mono_arch_register_lowlevel_calls (void)
6001 /* The signature doesn't matter */
6002 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
6003 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
6004 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
6006 #ifndef MONO_CROSS_COMPILE
6007 if (mono_arm_have_tls_get ()) {
6008 MonoTlsImplementation tls_imp = mono_arm_get_tls_implementation ();
6010 mono_register_jit_icall (tls_imp.get_tls_thunk, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
6011 mono_register_jit_icall (tls_imp.set_tls_thunk, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
6013 get_tls_tramp = tls_imp.get_tls_thunk;
6015 if (tls_imp.get_tls_thunk_end) {
6016 mono_tramp_info_register (
6017 mono_tramp_info_create (
6019 (guint8*)tls_imp.get_tls_thunk,
6020 (guint8*)tls_imp.get_tls_thunk_end - (guint8*)tls_imp.get_tls_thunk,
6022 mono_arch_get_cie_program ()
6026 mono_tramp_info_register (
6027 mono_tramp_info_create (
6029 (guint8*)tls_imp.set_tls_thunk,
6030 (guint8*)tls_imp.set_tls_thunk_end - (guint8*)tls_imp.set_tls_thunk,
6032 mono_arch_get_cie_program ()
6041 #define patch_lis_ori(ip,val) do {\
6042 guint16 *__lis_ori = (guint16*)(ip); \
6043 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
6044 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
6048 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6050 unsigned char *ip = ji->ip.i + code;
6052 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6056 case MONO_PATCH_INFO_SWITCH: {
6057 gpointer *jt = (gpointer*)(ip + 8);
6059 /* jt is the inlined jump table, 2 instructions after ip
6060 * In the normal case we store the absolute addresses,
6061 * otherwise the displacements.
6063 for (i = 0; i < ji->data.table->table_size; i++)
6064 jt [i] = code + (int)ji->data.table->table [i];
6067 case MONO_PATCH_INFO_IP:
6068 g_assert_not_reached ();
6069 patch_lis_ori (ip, ip);
6071 case MONO_PATCH_INFO_METHOD_REL:
6072 g_assert_not_reached ();
6073 *((gpointer *)(ip)) = target;
6075 case MONO_PATCH_INFO_METHODCONST:
6076 case MONO_PATCH_INFO_CLASS:
6077 case MONO_PATCH_INFO_IMAGE:
6078 case MONO_PATCH_INFO_FIELD:
6079 case MONO_PATCH_INFO_VTABLE:
6080 case MONO_PATCH_INFO_IID:
6081 case MONO_PATCH_INFO_SFLDA:
6082 case MONO_PATCH_INFO_LDSTR:
6083 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6084 case MONO_PATCH_INFO_LDTOKEN:
6085 g_assert_not_reached ();
6086 /* from OP_AOTCONST : lis + ori */
6087 patch_lis_ori (ip, target);
6089 case MONO_PATCH_INFO_R4:
6090 case MONO_PATCH_INFO_R8:
6091 g_assert_not_reached ();
6092 *((gconstpointer *)(ip + 2)) = target;
6094 case MONO_PATCH_INFO_EXC_NAME:
6095 g_assert_not_reached ();
6096 *((gconstpointer *)(ip + 1)) = target;
6098 case MONO_PATCH_INFO_NONE:
6099 case MONO_PATCH_INFO_BB_OVF:
6100 case MONO_PATCH_INFO_EXC_OVF:
6101 /* everything is dealt with at epilog output time */
6104 arm_patch_general (cfg, domain, ip, target);
6110 mono_arm_unaligned_stack (MonoMethod *method)
6112 g_assert_not_reached ();
6118 * Stack frame layout:
6120 * ------------------- fp
6121 * MonoLMF structure or saved registers
6122 * -------------------
6124 * -------------------
6126 * -------------------
6127 * optional 8 bytes for tracing
6128 * -------------------
6129 * param area size is cfg->param_area
6130 * ------------------- sp
6133 mono_arch_emit_prolog (MonoCompile *cfg)
6135 MonoMethod *method = cfg->method;
6137 MonoMethodSignature *sig;
6139 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6144 int prev_sp_offset, reg_offset;
6146 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6149 sig = mono_method_signature (method);
6150 cfg->code_size = 256 + sig->param_count * 64;
6151 code = cfg->native_code = g_malloc (cfg->code_size);
6153 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6155 alloc_size = cfg->stack_offset;
6161 * The iphone uses R7 as the frame pointer, and it points at the saved
6166 * We can't use r7 as a frame pointer since it points into the middle of
6167 * the frame, so we keep using our own frame pointer.
6168 * FIXME: Optimize this.
6170 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6171 prev_sp_offset += 8; /* r7 and lr */
6172 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6173 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6174 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6177 if (!method->save_lmf) {
6179 /* No need to push LR again */
6180 if (cfg->used_int_regs)
6181 ARM_PUSH (code, cfg->used_int_regs);
6183 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6184 prev_sp_offset += 4;
6186 for (i = 0; i < 16; ++i) {
6187 if (cfg->used_int_regs & (1 << i))
6188 prev_sp_offset += 4;
6190 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6192 for (i = 0; i < 16; ++i) {
6193 if ((cfg->used_int_regs & (1 << i))) {
6194 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6195 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6199 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6200 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6202 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6203 ARM_PUSH (code, 0x5ff0);
6204 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6205 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6207 for (i = 0; i < 16; ++i) {
6208 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6209 /* The original r7 is saved at the start */
6210 if (!(iphone_abi && i == ARMREG_R7))
6211 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6215 g_assert (reg_offset == 4 * 10);
6216 pos += sizeof (MonoLMF) - (4 * 10);
6220 orig_alloc_size = alloc_size;
6221 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6222 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6223 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6224 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6227 /* the stack used in the pushed regs */
6228 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6229 cfg->stack_usage = alloc_size;
6231 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6232 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6234 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6235 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6237 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6239 if (cfg->frame_reg != ARMREG_SP) {
6240 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6241 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6243 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6244 prev_sp_offset += alloc_size;
6246 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6247 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6249 /* compute max_offset in order to use short forward jumps
6250 * we could skip do it on arm because the immediate displacement
6251 * for jumps is large enough, it may be useful later for constant pools
6254 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6255 MonoInst *ins = bb->code;
6256 bb->max_offset = max_offset;
6258 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6261 MONO_BB_FOR_EACH_INS (bb, ins)
6262 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6265 /* stack alignment check */
6269 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6270 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6271 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6272 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6274 ARM_B_COND (code, ARMCOND_EQ, 0);
6275 if (cfg->compile_aot)
6276 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6278 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6279 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6280 code = emit_call_seq (cfg, code);
6281 arm_patch (buf [0], code);
6285 /* store runtime generic context */
6286 if (cfg->rgctx_var) {
6287 MonoInst *ins = cfg->rgctx_var;
6289 g_assert (ins->opcode == OP_REGOFFSET);
6291 if (arm_is_imm12 (ins->inst_offset)) {
6292 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6294 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6295 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6299 /* load arguments allocated to register from the stack */
6302 cinfo = get_call_info (NULL, sig);
6304 if (cinfo->ret.storage == RegTypeStructByAddr) {
6305 ArgInfo *ainfo = &cinfo->ret;
6306 inst = cfg->vret_addr;
6307 g_assert (arm_is_imm12 (inst->inst_offset));
6308 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6311 if (sig->call_convention == MONO_CALL_VARARG) {
6312 ArgInfo *cookie = &cinfo->sig_cookie;
6314 /* Save the sig cookie address */
6315 g_assert (cookie->storage == RegTypeBase);
6317 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6318 g_assert (arm_is_imm12 (cfg->sig_cookie));
6319 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6320 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6323 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6324 ArgInfo *ainfo = cinfo->args + i;
6325 inst = cfg->args [pos];
6327 if (cfg->verbose_level > 2)
6328 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6330 if (inst->opcode == OP_REGVAR) {
6331 if (ainfo->storage == RegTypeGeneral)
6332 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6333 else if (ainfo->storage == RegTypeFP) {
6334 g_assert_not_reached ();
6335 } else if (ainfo->storage == RegTypeBase) {
6336 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6337 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6339 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6340 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6343 g_assert_not_reached ();
6345 if (cfg->verbose_level > 2)
6346 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6348 switch (ainfo->storage) {
6350 for (part = 0; part < ainfo->nregs; part ++) {
6351 if (ainfo->esize == 4)
6352 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6354 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6357 case RegTypeGeneral:
6358 case RegTypeIRegPair:
6359 case RegTypeGSharedVtInReg:
6360 case RegTypeStructByAddr:
6361 switch (ainfo->size) {
6363 if (arm_is_imm12 (inst->inst_offset))
6364 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6366 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6367 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6371 if (arm_is_imm8 (inst->inst_offset)) {
6372 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6374 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6375 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6379 if (arm_is_imm12 (inst->inst_offset)) {
6380 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6382 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6383 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6385 if (arm_is_imm12 (inst->inst_offset + 4)) {
6386 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6388 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6389 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6393 if (arm_is_imm12 (inst->inst_offset)) {
6394 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6396 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6397 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6402 case RegTypeBaseGen:
6403 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6404 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6406 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6407 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6409 if (arm_is_imm12 (inst->inst_offset + 4)) {
6410 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6411 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6413 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6414 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6415 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6416 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6420 case RegTypeGSharedVtOnStack:
6421 case RegTypeStructByAddrOnStack:
6422 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6423 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6425 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6426 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6429 switch (ainfo->size) {
6431 if (arm_is_imm8 (inst->inst_offset)) {
6432 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6434 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6435 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6439 if (arm_is_imm8 (inst->inst_offset)) {
6440 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6442 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6443 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6447 if (arm_is_imm12 (inst->inst_offset)) {
6448 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6450 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6451 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6453 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6454 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6456 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6457 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6459 if (arm_is_imm12 (inst->inst_offset + 4)) {
6460 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6462 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6463 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6467 if (arm_is_imm12 (inst->inst_offset)) {
6468 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6470 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6471 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6477 int imm8, rot_amount;
6479 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6480 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6481 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6483 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6485 if (ainfo->size == 8)
6486 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6488 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6491 case RegTypeStructByVal: {
6492 int doffset = inst->inst_offset;
6496 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6497 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6498 if (arm_is_imm12 (doffset)) {
6499 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6501 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6502 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6504 soffset += sizeof (gpointer);
6505 doffset += sizeof (gpointer);
6507 if (ainfo->vtsize) {
6508 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6509 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6510 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6515 g_assert_not_reached ();
6522 if (method->save_lmf)
6523 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6526 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6528 if (cfg->arch.seq_point_info_var) {
6529 MonoInst *ins = cfg->arch.seq_point_info_var;
6531 /* Initialize the variable from a GOT slot */
6532 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6533 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6535 *(gpointer*)code = NULL;
6537 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6539 g_assert (ins->opcode == OP_REGOFFSET);
6541 if (arm_is_imm12 (ins->inst_offset)) {
6542 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6544 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6545 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6549 /* Initialize ss_trigger_page_var */
6550 if (!cfg->soft_breakpoints) {
6551 MonoInst *info_var = cfg->arch.seq_point_info_var;
6552 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6553 int dreg = ARMREG_LR;
6556 g_assert (info_var->opcode == OP_REGOFFSET);
6557 g_assert (arm_is_imm12 (info_var->inst_offset));
6559 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6560 /* Load the trigger page addr */
6561 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6562 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6566 if (cfg->arch.seq_point_ss_method_var) {
6567 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6568 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6570 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6571 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6573 if (cfg->compile_aot) {
6574 MonoInst *info_var = cfg->arch.seq_point_info_var;
6575 int dreg = ARMREG_LR;
6577 g_assert (info_var->opcode == OP_REGOFFSET);
6578 g_assert (arm_is_imm12 (info_var->inst_offset));
6580 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6581 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
6582 ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6584 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6585 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6587 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6589 *(gpointer*)code = &single_step_tramp;
6591 *(gpointer*)code = breakpoint_tramp;
6594 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6595 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6596 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6597 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6601 cfg->code_len = code - cfg->native_code;
6602 g_assert (cfg->code_len < cfg->code_size);
6609 mono_arch_emit_epilog (MonoCompile *cfg)
6611 MonoMethod *method = cfg->method;
6612 int pos, i, rot_amount;
6613 int max_epilog_size = 16 + 20*4;
6617 if (cfg->method->save_lmf)
6618 max_epilog_size += 128;
6620 if (mono_jit_trace_calls != NULL)
6621 max_epilog_size += 50;
6623 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6624 max_epilog_size += 50;
6626 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6627 cfg->code_size *= 2;
6628 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6629 cfg->stat_code_reallocs++;
6633 * Keep in sync with OP_JMP
6635 code = cfg->native_code + cfg->code_len;
6637 /* Save the uwind state which is needed by the out-of-line code */
6638 mono_emit_unwind_op_remember_state (cfg, code);
6640 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6641 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6645 /* Load returned vtypes into registers if needed */
6646 cinfo = cfg->arch.cinfo;
6647 switch (cinfo->ret.storage) {
6648 case RegTypeStructByVal: {
6649 MonoInst *ins = cfg->ret;
6651 if (cinfo->ret.nregs == 1) {
6652 if (arm_is_imm12 (ins->inst_offset)) {
6653 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6655 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6656 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6659 for (i = 0; i < cinfo->ret.nregs; ++i) {
6660 int offset = ins->inst_offset + (i * 4);
6661 if (arm_is_imm12 (offset)) {
6662 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6664 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6665 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6672 MonoInst *ins = cfg->ret;
6674 for (i = 0; i < cinfo->ret.nregs; ++i) {
6675 if (cinfo->ret.esize == 4)
6676 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6678 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6686 if (method->save_lmf) {
6687 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6688 /* all but r0-r3, sp and pc */
6689 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6692 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6694 /* This points to r4 inside MonoLMF->iregs */
6695 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6697 regmask = 0x9ff0; /* restore lr to pc */
6698 /* Skip caller saved registers not used by the method */
6699 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6700 regmask &= ~(1 << reg);
6705 /* Restored later */
6706 regmask &= ~(1 << ARMREG_PC);
6707 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6708 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6709 for (i = 0; i < 16; i++) {
6710 if (regmask & (1 << i))
6713 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6715 ARM_POP (code, regmask);
6717 for (i = 0; i < 16; i++) {
6718 if (regmask & (1 << i))
6719 mono_emit_unwind_op_same_value (cfg, code, i);
6721 /* Restore saved r7, restore LR to PC */
6722 /* Skip lr from the lmf */
6723 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6724 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6725 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6726 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6729 int i, nused_int_regs = 0;
6731 for (i = 0; i < 16; i++) {
6732 if (cfg->used_int_regs & (1 << i))
6736 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6737 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6739 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6740 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6743 if (cfg->frame_reg != ARMREG_SP) {
6744 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6748 /* Restore saved gregs */
6749 if (cfg->used_int_regs) {
6750 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6751 ARM_POP (code, cfg->used_int_regs);
6752 for (i = 0; i < 16; i++) {
6753 if (cfg->used_int_regs & (1 << i))
6754 mono_emit_unwind_op_same_value (cfg, code, i);
6757 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6758 /* Restore saved r7, restore LR to PC */
6759 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6761 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6762 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6766 /* Restore the unwind state to be the same as before the epilog */
6767 mono_emit_unwind_op_restore_state (cfg, code);
6769 cfg->code_len = code - cfg->native_code;
6771 g_assert (cfg->code_len < cfg->code_size);
6776 mono_arch_emit_exceptions (MonoCompile *cfg)
6778 MonoJumpInfo *patch_info;
6781 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6782 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6783 int max_epilog_size = 50;
6785 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6786 exc_throw_pos [i] = NULL;
6787 exc_throw_found [i] = 0;
6790 /* count the number of exception infos */
6793 * make sure we have enough space for exceptions
6795 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6796 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6797 i = mini_exception_id_by_name (patch_info->data.target);
6798 if (!exc_throw_found [i]) {
6799 max_epilog_size += 32;
6800 exc_throw_found [i] = TRUE;
6805 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6806 cfg->code_size *= 2;
6807 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6808 cfg->stat_code_reallocs++;
6811 code = cfg->native_code + cfg->code_len;
6813 /* add code to raise exceptions */
6814 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6815 switch (patch_info->type) {
6816 case MONO_PATCH_INFO_EXC: {
6817 MonoClass *exc_class;
6818 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6820 i = mini_exception_id_by_name (patch_info->data.target);
6821 if (exc_throw_pos [i]) {
6822 arm_patch (ip, exc_throw_pos [i]);
6823 patch_info->type = MONO_PATCH_INFO_NONE;
6826 exc_throw_pos [i] = code;
6828 arm_patch (ip, code);
6830 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6832 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6833 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6834 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6835 patch_info->data.name = "mono_arch_throw_corlib_exception";
6836 patch_info->ip.i = code - cfg->native_code;
6838 cfg->thunk_area += THUNK_SIZE;
6839 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6849 cfg->code_len = code - cfg->native_code;
6851 g_assert (cfg->code_len < cfg->code_size);
6855 #endif /* #ifndef DISABLE_JIT */
6858 mono_arch_finish_init (void)
6863 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6868 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6875 mono_arch_print_tree (MonoInst *tree, int arity)
6885 mono_arch_get_patch_offset (guint8 *code)
6892 mono_arch_flush_register_windows (void)
6897 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6899 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6903 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6905 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6909 mono_arch_get_cie_program (void)
6913 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6918 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6919 #define BASE_SIZE (6 * 4)
6920 #define BSEARCH_ENTRY_SIZE (4 * 4)
6921 #define CMP_SIZE (3 * 4)
6922 #define BRANCH_SIZE (1 * 4)
6923 #define CALL_SIZE (2 * 4)
6924 #define WMC_SIZE (8 * 4)
6925 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6928 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6930 guint32 delta = DISTANCE (target, code);
6932 g_assert (delta >= 0 && delta <= 0xFFF);
6933 *target = *target | delta;
6938 #ifdef ENABLE_WRONG_METHOD_CHECK
6940 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6942 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6948 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6949 gpointer fail_tramp)
6952 arminstr_t *code, *start;
6953 gboolean large_offsets = FALSE;
6954 guint32 **constant_pool_starts;
6955 arminstr_t *vtable_target = NULL;
6956 int extra_space = 0;
6957 #ifdef ENABLE_WRONG_METHOD_CHECK
6963 constant_pool_starts = g_new0 (guint32*, count);
6965 for (i = 0; i < count; ++i) {
6966 MonoIMTCheckItem *item = imt_entries [i];
6967 if (item->is_equals) {
6968 gboolean fail_case = !item->check_target_idx && fail_tramp;
6970 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6971 item->chunk_size += 32;
6972 large_offsets = TRUE;
6975 if (item->check_target_idx || fail_case) {
6976 if (!item->compare_done || fail_case)
6977 item->chunk_size += CMP_SIZE;
6978 item->chunk_size += BRANCH_SIZE;
6980 #ifdef ENABLE_WRONG_METHOD_CHECK
6981 item->chunk_size += WMC_SIZE;
6985 item->chunk_size += 16;
6986 large_offsets = TRUE;
6988 item->chunk_size += CALL_SIZE;
6990 item->chunk_size += BSEARCH_ENTRY_SIZE;
6991 imt_entries [item->check_target_idx]->compare_done = TRUE;
6993 size += item->chunk_size;
6997 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
7000 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
7002 code = mono_domain_code_reserve (domain, size);
7005 unwind_ops = mono_arch_get_cie_program ();
7008 g_print ("Building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
7009 for (i = 0; i < count; ++i) {
7010 MonoIMTCheckItem *item = imt_entries [i];
7011 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
7015 if (large_offsets) {
7016 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7017 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
7019 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7020 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7022 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7023 vtable_target = code;
7024 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7025 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7027 for (i = 0; i < count; ++i) {
7028 MonoIMTCheckItem *item = imt_entries [i];
7029 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7030 gint32 vtable_offset;
7032 item->code_target = (guint8*)code;
7034 if (item->is_equals) {
7035 gboolean fail_case = !item->check_target_idx && fail_tramp;
7037 if (item->check_target_idx || fail_case) {
7038 if (!item->compare_done || fail_case) {
7040 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7041 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7043 item->jmp_code = (guint8*)code;
7044 ARM_B_COND (code, ARMCOND_NE, 0);
7046 /*Enable the commented code to assert on wrong method*/
7047 #ifdef ENABLE_WRONG_METHOD_CHECK
7049 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7050 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7052 ARM_B_COND (code, ARMCOND_EQ, 0);
7054 /* Define this if your system is so bad that gdb is failing. */
7055 #ifdef BROKEN_DEV_ENV
7056 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7058 arm_patch (code - 1, mini_dump_bad_imt);
7062 arm_patch (cond, code);
7066 if (item->has_target_code) {
7067 /* Load target address */
7068 target_code_ins = code;
7069 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7070 /* Save it to the fourth slot */
7071 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7072 /* Restore registers and branch */
7073 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7075 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7077 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7078 if (!arm_is_imm12 (vtable_offset)) {
7080 * We need to branch to a computed address but we don't have
7081 * a free register to store it, since IP must contain the
7082 * vtable address. So we push the two values to the stack, and
7083 * load them both using LDM.
7085 /* Compute target address */
7086 vtable_offset_ins = code;
7087 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7088 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7089 /* Save it to the fourth slot */
7090 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7091 /* Restore registers and branch */
7092 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7094 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7096 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7097 if (large_offsets) {
7098 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7099 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7101 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7102 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7107 arm_patch (item->jmp_code, (guchar*)code);
7109 target_code_ins = code;
7110 /* Load target address */
7111 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7112 /* Save it to the fourth slot */
7113 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7114 /* Restore registers and branch */
7115 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7117 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7118 item->jmp_code = NULL;
7122 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7124 /*must emit after unconditional branch*/
7125 if (vtable_target) {
7126 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7127 item->chunk_size += 4;
7128 vtable_target = NULL;
7131 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7132 constant_pool_starts [i] = code;
7134 code += extra_space;
7138 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7139 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7141 item->jmp_code = (guint8*)code;
7142 ARM_B_COND (code, ARMCOND_HS, 0);
7147 for (i = 0; i < count; ++i) {
7148 MonoIMTCheckItem *item = imt_entries [i];
7149 if (item->jmp_code) {
7150 if (item->check_target_idx)
7151 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7153 if (i > 0 && item->is_equals) {
7155 arminstr_t *space_start = constant_pool_starts [i];
7156 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7157 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7164 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7165 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7170 g_free (constant_pool_starts);
7172 mono_arch_flush_icache ((guint8*)start, size);
7173 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7174 mono_stats.imt_trampolines_size += code - start;
7176 g_assert (DISTANCE (start, code) <= size);
7178 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7184 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7186 return ctx->regs [reg];
7190 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7192 ctx->regs [reg] = val;
7196 * mono_arch_get_trampolines:
7198 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7202 mono_arch_get_trampolines (gboolean aot)
7204 return mono_arm_get_exception_trampolines (aot);
7208 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7215 bp = MONO_CONTEXT_GET_BP (ctx);
7216 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7218 old_value = *lr_loc;
7219 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7222 *lr_loc = new_value;
7227 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7229 * mono_arch_set_breakpoint:
7231 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7232 * The location should contain code emitted by OP_SEQ_POINT.
7235 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7238 guint32 native_offset = ip - (guint8*)ji->code_start;
7239 MonoDebugOptions *opt = mini_get_debug_options ();
7242 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7244 if (!breakpoint_tramp)
7245 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7247 g_assert (native_offset % 4 == 0);
7248 g_assert (info->bp_addrs [native_offset / 4] == 0);
7249 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7250 } else if (opt->soft_breakpoints) {
7252 ARM_BLX_REG (code, ARMREG_LR);
7253 mono_arch_flush_icache (code - 4, 4);
7255 int dreg = ARMREG_LR;
7257 /* Read from another trigger page */
7258 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7260 *(int*)code = (int)bp_trigger_page;
7262 ARM_LDR_IMM (code, dreg, dreg, 0);
7264 mono_arch_flush_icache (code - 16, 16);
7267 /* This is currently implemented by emitting an SWI instruction, which
7268 * qemu/linux seems to convert to a SIGILL.
7270 *(int*)code = (0xef << 24) | 8;
7272 mono_arch_flush_icache (code - 4, 4);
7278 * mono_arch_clear_breakpoint:
7280 * Clear the breakpoint at IP.
7283 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7285 MonoDebugOptions *opt = mini_get_debug_options ();
7290 guint32 native_offset = ip - (guint8*)ji->code_start;
7291 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7293 if (!breakpoint_tramp)
7294 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7296 g_assert (native_offset % 4 == 0);
7297 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7298 info->bp_addrs [native_offset / 4] = 0;
7299 } else if (opt->soft_breakpoints) {
7302 mono_arch_flush_icache (code - 4, 4);
7304 for (i = 0; i < 4; ++i)
7307 mono_arch_flush_icache (ip, code - ip);
7312 * mono_arch_start_single_stepping:
7314 * Start single stepping.
7317 mono_arch_start_single_stepping (void)
7319 if (ss_trigger_page)
7320 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7322 single_step_tramp = mini_get_single_step_trampoline ();
7326 * mono_arch_stop_single_stepping:
7328 * Stop single stepping.
7331 mono_arch_stop_single_stepping (void)
7333 if (ss_trigger_page)
7334 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7336 single_step_tramp = NULL;
7340 #define DBG_SIGNAL SIGBUS
7342 #define DBG_SIGNAL SIGSEGV
7346 * mono_arch_is_single_step_event:
7348 * Return whenever the machine state in SIGCTX corresponds to a single
7352 mono_arch_is_single_step_event (void *info, void *sigctx)
7354 siginfo_t *sinfo = info;
7356 if (!ss_trigger_page)
7359 /* Sometimes the address is off by 4 */
7360 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7367 * mono_arch_is_breakpoint_event:
7369 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7372 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7374 siginfo_t *sinfo = info;
7376 if (!ss_trigger_page)
7379 if (sinfo->si_signo == DBG_SIGNAL) {
7380 /* Sometimes the address is off by 4 */
7381 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7391 * mono_arch_skip_breakpoint:
7393 * See mini-amd64.c for docs.
7396 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7398 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7402 * mono_arch_skip_single_step:
7404 * See mini-amd64.c for docs.
7407 mono_arch_skip_single_step (MonoContext *ctx)
7409 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7412 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7415 * mono_arch_get_seq_point_info:
7417 * See mini-amd64.c for docs.
7420 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7425 // FIXME: Add a free function
7427 mono_domain_lock (domain);
7428 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7430 mono_domain_unlock (domain);
7433 ji = mono_jit_info_table_find (domain, (char*)code);
7436 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7438 info->ss_trigger_page = ss_trigger_page;
7439 info->bp_trigger_page = bp_trigger_page;
7440 info->ss_tramp_addr = &single_step_tramp;
7442 mono_domain_lock (domain);
7443 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7445 mono_domain_unlock (domain);
7452 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7454 ext->lmf.previous_lmf = prev_lmf;
7455 /* Mark that this is a MonoLMFExt */
7456 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7457 ext->lmf.sp = (gssize)ext;
7461 * mono_arch_set_target:
7463 * Set the target architecture the JIT backend should generate code for, in the form
7464 * of a GNU target triplet. Only used in AOT mode.
7467 mono_arch_set_target (char *mtriple)
7469 /* The GNU target triple format is not very well documented */
7470 if (strstr (mtriple, "armv7")) {
7471 v5_supported = TRUE;
7472 v6_supported = TRUE;
7473 v7_supported = TRUE;
7475 if (strstr (mtriple, "armv6")) {
7476 v5_supported = TRUE;
7477 v6_supported = TRUE;
7479 if (strstr (mtriple, "armv7s")) {
7480 v7s_supported = TRUE;
7482 if (strstr (mtriple, "armv7k")) {
7483 v7k_supported = TRUE;
7485 if (strstr (mtriple, "thumbv7s")) {
7486 v5_supported = TRUE;
7487 v6_supported = TRUE;
7488 v7_supported = TRUE;
7489 v7s_supported = TRUE;
7490 thumb_supported = TRUE;
7491 thumb2_supported = TRUE;
7493 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7494 v5_supported = TRUE;
7495 v6_supported = TRUE;
7496 thumb_supported = TRUE;
7499 if (strstr (mtriple, "gnueabi"))
7500 eabi_supported = TRUE;
7504 mono_arch_opcode_supported (int opcode)
7507 case OP_ATOMIC_ADD_I4:
7508 case OP_ATOMIC_EXCHANGE_I4:
7509 case OP_ATOMIC_CAS_I4:
7510 case OP_ATOMIC_LOAD_I1:
7511 case OP_ATOMIC_LOAD_I2:
7512 case OP_ATOMIC_LOAD_I4:
7513 case OP_ATOMIC_LOAD_U1:
7514 case OP_ATOMIC_LOAD_U2:
7515 case OP_ATOMIC_LOAD_U4:
7516 case OP_ATOMIC_STORE_I1:
7517 case OP_ATOMIC_STORE_I2:
7518 case OP_ATOMIC_STORE_I4:
7519 case OP_ATOMIC_STORE_U1:
7520 case OP_ATOMIC_STORE_U2:
7521 case OP_ATOMIC_STORE_U4:
7522 return v7_supported;
7523 case OP_ATOMIC_LOAD_R4:
7524 case OP_ATOMIC_LOAD_R8:
7525 case OP_ATOMIC_STORE_R4:
7526 case OP_ATOMIC_STORE_R8:
7527 return v7_supported && IS_VFP;
7534 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7536 return get_call_info (mp, sig);
7540 mono_arch_get_get_tls_tramp (void)
7542 return get_tls_tramp;
7546 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data)
7549 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
7550 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7552 *(gpointer*)code = NULL;
7554 /* Load the value from the GOT */
7555 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);