2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
27 #include "debugger-agent.h"
29 #include "mono/arch/arm/arm-vfp-codegen.h"
31 /* Sanity check: This makes no sense */
32 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
33 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
37 * IS_SOFT_FLOAT: Is full software floating point used?
38 * IS_HARD_FLOAT: Is full hardware floating point used?
39 * IS_VFP: Is hardware floating point with software ABI used?
41 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
42 * IS_VFP may delegate to mono_arch_is_soft_float ().
45 #if defined(ARM_FPU_VFP_HARD)
46 #define IS_SOFT_FLOAT (FALSE)
47 #define IS_HARD_FLOAT (TRUE)
49 #elif defined(ARM_FPU_NONE)
50 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
51 #define IS_HARD_FLOAT (FALSE)
52 #define IS_VFP (!mono_arch_is_soft_float ())
54 #define IS_SOFT_FLOAT (FALSE)
55 #define IS_HARD_FLOAT (FALSE)
59 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(__native_client__)
60 #define HAVE_AEABI_READ_TP 1
63 #define THUNK_SIZE (3 * 4)
65 #ifdef __native_client_codegen__
66 const guint kNaClAlignment = kNaClAlignmentARM;
67 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
68 gint8 nacl_align_byte = -1; /* 0xff */
71 mono_arch_nacl_pad (guint8 *code, int pad)
73 /* Not yet properly implemented. */
74 g_assert_not_reached ();
79 mono_arch_nacl_skip_nops (guint8 *code)
81 /* Not yet properly implemented. */
82 g_assert_not_reached ();
86 #endif /* __native_client_codegen__ */
88 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
91 void sys_icache_invalidate (void *start, size_t len);
94 /* This mutex protects architecture specific caches */
95 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
96 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
97 static mono_mutex_t mini_arch_mutex;
99 static gboolean v5_supported = FALSE;
100 static gboolean v6_supported = FALSE;
101 static gboolean v7_supported = FALSE;
102 static gboolean v7s_supported = FALSE;
103 static gboolean thumb_supported = FALSE;
104 static gboolean thumb2_supported = FALSE;
106 * Whenever to use the ARM EABI
108 static gboolean eabi_supported = FALSE;
111 * Whenever to use the iphone ABI extensions:
112 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
113 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
114 * This is required for debugging/profiling tools to work, but it has some overhead so it should
115 * only be turned on in debug builds.
117 static gboolean iphone_abi = FALSE;
120 * The FPU we are generating code for. This is NOT runtime configurable right now,
121 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
123 static MonoArmFPU arm_fpu;
125 #if defined(ARM_FPU_VFP_HARD)
127 * On armhf, d0-d7 are used for argument passing and d8-d15
128 * must be preserved across calls, which leaves us no room
129 * for scratch registers. So we use d14-d15 but back up their
130 * previous contents to a stack slot before using them - see
131 * mono_arm_emit_vfp_scratch_save/_restore ().
133 static int vfp_scratch1 = ARM_VFP_D14;
134 static int vfp_scratch2 = ARM_VFP_D15;
137 * On armel, d0-d7 do not need to be preserved, so we can
138 * freely make use of them as scratch registers.
140 static int vfp_scratch1 = ARM_VFP_D0;
141 static int vfp_scratch2 = ARM_VFP_D1;
146 static volatile int ss_trigger_var = 0;
148 static gpointer single_step_tramp, breakpoint_tramp;
151 * The code generated for sequence points reads from this location, which is
152 * made read-only when single stepping is enabled.
154 static gpointer ss_trigger_page;
156 /* Enabled breakpoints read from this trigger page */
157 static gpointer bp_trigger_page;
161 * floating point support: on ARM it is a mess, there are at least 3
162 * different setups, each of which binary incompat with the other.
163 * 1) FPA: old and ugly, but unfortunately what current distros use
164 * the double binary format has the two words swapped. 8 double registers.
165 * Implemented usually by kernel emulation.
166 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
167 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
168 * 3) VFP: the new and actually sensible and useful FP support. Implemented
169 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
171 * We do not care about FPA. We will support soft float and VFP.
173 int mono_exc_esp_offset = 0;
175 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
176 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
177 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
179 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
180 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
181 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
183 //#define DEBUG_IMT 0
186 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
190 mono_arch_regname (int reg)
192 static const char * rnames[] = {
193 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
194 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
195 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
198 if (reg >= 0 && reg < 16)
204 mono_arch_fregname (int reg)
206 static const char * rnames[] = {
207 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
208 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
209 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
210 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
211 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
212 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
215 if (reg >= 0 && reg < 32)
223 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
225 int imm8, rot_amount;
226 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
227 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
231 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
232 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
234 code = mono_arm_emit_load_imm (code, dreg, imm);
235 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
240 /* If dreg == sreg, this clobbers IP */
242 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
244 int imm8, rot_amount;
245 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
246 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
250 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
251 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
253 code = mono_arm_emit_load_imm (code, dreg, imm);
254 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
260 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
262 /* we can use r0-r3, since this is called only for incoming args on the stack */
263 if (size > sizeof (gpointer) * 4) {
265 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
266 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
267 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
268 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
269 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
270 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
271 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
272 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
273 ARM_B_COND (code, ARMCOND_NE, 0);
274 arm_patch (code - 4, start_loop);
277 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
278 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
280 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
281 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
287 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
288 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
289 doffset = soffset = 0;
291 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
292 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
298 g_assert (size == 0);
303 emit_call_reg (guint8 *code, int reg)
306 ARM_BLX_REG (code, reg);
308 #ifdef USE_JUMP_TABLES
309 g_assert_not_reached ();
311 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
315 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
321 emit_call_seq (MonoCompile *cfg, guint8 *code)
323 #ifdef USE_JUMP_TABLES
324 code = mono_arm_patchable_bl (code, ARMCOND_AL);
326 if (cfg->method->dynamic) {
327 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
329 *(gpointer*)code = NULL;
331 code = emit_call_reg (code, ARMREG_IP);
335 cfg->thunk_area += THUNK_SIZE;
341 mono_arm_patchable_b (guint8 *code, int cond)
343 #ifdef USE_JUMP_TABLES
346 jte = mono_jumptable_add_entry ();
347 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
348 ARM_BX_COND (code, cond, ARMREG_IP);
350 ARM_B_COND (code, cond, 0);
356 mono_arm_patchable_bl (guint8 *code, int cond)
358 #ifdef USE_JUMP_TABLES
361 jte = mono_jumptable_add_entry ();
362 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
363 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
365 ARM_BL_COND (code, cond, 0);
370 #ifdef USE_JUMP_TABLES
372 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
374 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
375 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
380 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
382 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
383 ARM_LDR_IMM (code, reg, reg, 0);
391 * Emit code to push an LMF structure on the LMF stack.
392 * On arm, this is intermixed with the initialization of other fields of the structure.
395 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
397 gboolean get_lmf_fast = FALSE;
400 #ifdef HAVE_AEABI_READ_TP
401 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
403 if (lmf_addr_tls_offset != -1) {
406 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
407 (gpointer)"__aeabi_read_tp");
408 code = emit_call_seq (cfg, code);
410 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
416 if (cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) {
419 /* Inline mono_get_lmf_addr () */
420 /* jit_tls = pthread_getspecific (mono_jit_tls_id); lmf_addr = &jit_tls->lmf; */
422 /* Load mono_jit_tls_id */
424 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_TLS_ID, NULL);
425 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
427 *(gpointer*)code = NULL;
429 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
430 /* call pthread_getspecific () */
431 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
432 (gpointer)"pthread_getspecific");
433 code = emit_call_seq (cfg, code);
434 /* lmf_addr = &jit_tls->lmf */
435 lmf_offset = MONO_STRUCT_OFFSET (MonoJitTlsData, lmf);
436 g_assert (arm_is_imm8 (lmf_offset));
437 ARM_ADD_REG_IMM (code, ARMREG_R0, ARMREG_R0, lmf_offset, 0);
444 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
445 (gpointer)"mono_get_lmf_addr");
446 code = emit_call_seq (cfg, code);
448 /* we build the MonoLMF structure on the stack - see mini-arm.h */
449 /* lmf_offset is the offset from the previous stack pointer,
450 * alloc_size is the total stack space allocated, so the offset
451 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
452 * The pointer to the struct is put in r1 (new_lmf).
453 * ip is used as scratch
454 * The callee-saved registers are already in the MonoLMF structure
456 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
457 /* r0 is the result from mono_get_lmf_addr () */
458 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
459 /* new_lmf->previous_lmf = *lmf_addr */
460 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
461 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
462 /* *(lmf_addr) = r1 */
463 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
464 /* Skip method (only needed for trampoline LMF frames) */
465 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
466 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
467 /* save the current IP */
468 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
469 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
471 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
472 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
483 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
487 g_assert (!cfg->r4fp);
489 for (list = inst->float_args; list; list = list->next) {
490 FloatArgData *fad = list->data;
491 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
492 gboolean imm = arm_is_fpimm8 (var->inst_offset);
494 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
500 if (*offset + *max_len > cfg->code_size) {
501 cfg->code_size += *max_len;
502 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
504 code = cfg->native_code + *offset;
508 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
509 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
511 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
513 *offset = code - cfg->native_code;
520 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
524 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
526 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
529 if (!arm_is_fpimm8 (inst->inst_offset)) {
530 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
531 ARM_FSTD (code, reg, ARMREG_LR, 0);
533 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
540 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
544 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
546 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
549 if (!arm_is_fpimm8 (inst->inst_offset)) {
550 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
551 ARM_FLDD (code, reg, ARMREG_LR, 0);
553 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
562 * Emit code to pop an LMF structure from the LMF stack.
565 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
569 if (lmf_offset < 32) {
570 basereg = cfg->frame_reg;
575 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
578 /* ip = previous_lmf */
579 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
581 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
582 /* *(lmf_addr) = previous_lmf */
583 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
588 #endif /* #ifndef DISABLE_JIT */
591 * mono_arch_get_argument_info:
592 * @csig: a method signature
593 * @param_count: the number of parameters to consider
594 * @arg_info: an array to store the result infos
596 * Gathers information on parameters such as size, alignment and
597 * padding. arg_info should be large enought to hold param_count + 1 entries.
599 * Returns the size of the activation frame.
602 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
604 int k, frame_size = 0;
605 guint32 size, align, pad;
609 t = mini_type_get_underlying_type (gsctx, csig->ret);
610 if (MONO_TYPE_ISSTRUCT (t)) {
611 frame_size += sizeof (gpointer);
615 arg_info [0].offset = offset;
618 frame_size += sizeof (gpointer);
622 arg_info [0].size = frame_size;
624 for (k = 0; k < param_count; k++) {
625 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
627 /* ignore alignment for now */
630 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
631 arg_info [k].pad = pad;
633 arg_info [k + 1].pad = 0;
634 arg_info [k + 1].size = size;
636 arg_info [k + 1].offset = offset;
640 align = MONO_ARCH_FRAME_ALIGNMENT;
641 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
642 arg_info [k].pad = pad;
647 #define MAX_ARCH_DELEGATE_PARAMS 3
650 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
652 guint8 *code, *start;
655 start = code = mono_global_codeman_reserve (12);
657 /* Replace the this argument with the target */
658 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
659 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
660 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
662 g_assert ((code - start) <= 12);
664 mono_arch_flush_icache (start, 12);
668 size = 8 + param_count * 4;
669 start = code = mono_global_codeman_reserve (size);
671 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
672 /* slide down the arguments */
673 for (i = 0; i < param_count; ++i) {
674 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
676 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
678 g_assert ((code - start) <= size);
680 mono_arch_flush_icache (start, size);
683 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
685 *code_size = code - start;
691 * mono_arch_get_delegate_invoke_impls:
693 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
697 mono_arch_get_delegate_invoke_impls (void)
705 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
706 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
708 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
709 code = get_delegate_invoke_impl (FALSE, i, &code_len);
710 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
711 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
719 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
721 guint8 *code, *start;
724 /* FIXME: Support more cases */
725 sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
726 if (MONO_TYPE_ISSTRUCT (sig_ret))
730 static guint8* cached = NULL;
731 mono_mini_arch_lock ();
733 mono_mini_arch_unlock ();
738 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
740 start = get_delegate_invoke_impl (TRUE, 0, NULL);
742 mono_mini_arch_unlock ();
745 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
748 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
750 for (i = 0; i < sig->param_count; ++i)
751 if (!mono_is_regsize_var (sig->params [i]))
754 mono_mini_arch_lock ();
755 code = cache [sig->param_count];
757 mono_mini_arch_unlock ();
762 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
763 start = mono_aot_get_trampoline (name);
766 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
768 cache [sig->param_count] = start;
769 mono_mini_arch_unlock ();
777 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
783 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
785 return (gpointer)regs [ARMREG_R0];
789 * Initialize the cpu to execute managed code.
792 mono_arch_cpu_init (void)
794 i8_align = MONO_ABI_ALIGNOF (gint64);
795 #ifdef MONO_CROSS_COMPILE
796 /* Need to set the alignment of i8 since it can different on the target */
797 #ifdef TARGET_ANDROID
799 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
805 * Initialize architecture specific code.
808 mono_arch_init (void)
810 const char *cpu_arch;
812 mono_mutex_init_recursive (&mini_arch_mutex);
813 if (mini_get_debug_options ()->soft_breakpoints) {
814 single_step_tramp = mini_get_single_step_trampoline ();
815 breakpoint_tramp = mini_get_breakpoint_trampoline ();
817 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
818 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
819 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
822 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
823 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
824 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
825 #if defined(ENABLE_GSHAREDVT)
826 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
829 #if defined(__ARM_EABI__)
830 eabi_supported = TRUE;
833 #if defined(ARM_FPU_VFP_HARD)
834 arm_fpu = MONO_ARM_FPU_VFP_HARD;
836 arm_fpu = MONO_ARM_FPU_VFP;
838 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
840 * If we're compiling with a soft float fallback and it
841 * turns out that no VFP unit is available, we need to
842 * switch to soft float. We don't do this for iOS, since
843 * iOS devices always have a VFP unit.
845 if (!mono_hwcap_arm_has_vfp)
846 arm_fpu = MONO_ARM_FPU_NONE;
849 * This environment variable can be useful in testing
850 * environments to make sure the soft float fallback
851 * works. Most ARM devices have VFP units these days, so
852 * normally soft float code would not be exercised much.
854 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
856 if (soft && !strncmp (soft, "1", 1))
857 arm_fpu = MONO_ARM_FPU_NONE;
861 v5_supported = mono_hwcap_arm_is_v5;
862 v6_supported = mono_hwcap_arm_is_v6;
863 v7_supported = mono_hwcap_arm_is_v7;
864 v7s_supported = mono_hwcap_arm_is_v7s;
866 #if defined(__APPLE__)
867 /* iOS is special-cased here because we don't yet
868 have a way to properly detect CPU features on it. */
869 thumb_supported = TRUE;
872 thumb_supported = mono_hwcap_arm_has_thumb;
873 thumb2_supported = mono_hwcap_arm_has_thumb2;
876 /* Format: armv(5|6|7[s])[-thumb[2]] */
877 cpu_arch = g_getenv ("MONO_CPU_ARCH");
879 /* Do this here so it overrides any detection. */
881 if (strncmp (cpu_arch, "armv", 4) == 0) {
882 v5_supported = cpu_arch [4] >= '5';
883 v6_supported = cpu_arch [4] >= '6';
884 v7_supported = cpu_arch [4] >= '7';
885 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
888 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
889 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
894 * Cleanup architecture specific code.
897 mono_arch_cleanup (void)
902 * This function returns the optimizations supported on this cpu.
905 mono_arch_cpu_optimizations (guint32 *exclude_mask)
907 /* no arm-specific optimizations yet */
913 * This function test for all SIMD functions supported.
915 * Returns a bitmask corresponding to all supported versions.
919 mono_arch_cpu_enumerate_simd_versions (void)
921 /* SIMD is currently unimplemented */
929 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
945 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
947 mono_arch_is_soft_float (void)
949 return arm_fpu == MONO_ARM_FPU_NONE;
954 mono_arm_is_hard_float (void)
956 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
960 is_regsize_var (MonoGenericSharingContext *gsctx, MonoType *t) {
963 t = mini_type_get_underlying_type (gsctx, t);
970 case MONO_TYPE_FNPTR:
972 case MONO_TYPE_OBJECT:
973 case MONO_TYPE_STRING:
974 case MONO_TYPE_CLASS:
975 case MONO_TYPE_SZARRAY:
976 case MONO_TYPE_ARRAY:
978 case MONO_TYPE_GENERICINST:
979 if (!mono_type_generic_inst_is_valuetype (t))
982 case MONO_TYPE_VALUETYPE:
989 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
994 for (i = 0; i < cfg->num_varinfo; i++) {
995 MonoInst *ins = cfg->varinfo [i];
996 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
999 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1002 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1005 /* we can only allocate 32 bit values */
1006 if (is_regsize_var (cfg->generic_sharing_context, ins->inst_vtype)) {
1007 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1008 g_assert (i == vmv->idx);
1009 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1017 mono_arch_get_global_int_regs (MonoCompile *cfg)
1021 mono_arch_compute_omit_fp (cfg);
1024 * FIXME: Interface calls might go through a static rgctx trampoline which
1025 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1028 if (cfg->flags & MONO_CFG_HAS_CALLS)
1029 cfg->uses_rgctx_reg = TRUE;
1031 if (cfg->arch.omit_fp)
1032 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1033 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1034 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1035 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1037 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1038 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1040 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1041 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1042 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1043 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1044 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1045 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1051 * mono_arch_regalloc_cost:
1053 * Return the cost, in number of memory references, of the action of
1054 * allocating the variable VMV into a register during global register
1058 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1064 #endif /* #ifndef DISABLE_JIT */
1066 #ifndef __GNUC_PREREQ
1067 #define __GNUC_PREREQ(maj, min) (0)
1071 mono_arch_flush_icache (guint8 *code, gint size)
1073 #if defined(__native_client__)
1074 // For Native Client we don't have to flush i-cache here,
1075 // as it's being done by dyncode interface.
1078 #ifdef MONO_CROSS_COMPILE
1080 sys_icache_invalidate (code, size);
1081 #elif __GNUC_PREREQ(4, 3)
1082 __builtin___clear_cache (code, code + size);
1083 #elif __GNUC_PREREQ(4, 1)
1084 __clear_cache (code, code + size);
1085 #elif defined(PLATFORM_ANDROID)
1086 const int syscall = 0xf0002;
1094 : "r" (code), "r" (code + size), "r" (syscall)
1095 : "r0", "r1", "r7", "r2"
1098 __asm __volatile ("mov r0, %0\n"
1101 "swi 0x9f0002 @ sys_cacheflush"
1103 : "r" (code), "r" (code + size), "r" (0)
1104 : "r0", "r1", "r3" );
1106 #endif /* !__native_client__ */
1117 RegTypeStructByAddr,
1118 /* gsharedvt argument passed by addr in greg */
1119 RegTypeGSharedVtInReg,
1120 /* gsharedvt argument passed by addr on stack */
1121 RegTypeGSharedVtOnStack,
1127 guint16 vtsize; /* in param area */
1135 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1140 guint32 stack_usage;
1141 /* The index of the vret arg in the argument list for RegTypeStructByAddr */
1151 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1154 if (*gr > ARMREG_R3) {
1156 ainfo->offset = *stack_size;
1157 ainfo->reg = ARMREG_SP; /* in the caller */
1158 ainfo->storage = RegTypeBase;
1161 ainfo->storage = RegTypeGeneral;
1168 split = i8_align == 4;
1173 if (*gr == ARMREG_R3 && split) {
1174 /* first word in r3 and the second on the stack */
1175 ainfo->offset = *stack_size;
1176 ainfo->reg = ARMREG_SP; /* in the caller */
1177 ainfo->storage = RegTypeBaseGen;
1179 } else if (*gr >= ARMREG_R3) {
1180 if (eabi_supported) {
1181 /* darwin aligns longs to 4 byte only */
1182 if (i8_align == 8) {
1187 ainfo->offset = *stack_size;
1188 ainfo->reg = ARMREG_SP; /* in the caller */
1189 ainfo->storage = RegTypeBase;
1192 if (eabi_supported) {
1193 if (i8_align == 8 && ((*gr) & 1))
1196 ainfo->storage = RegTypeIRegPair;
1205 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1208 * If we're calling a function like this:
1210 * void foo(float a, double b, float c)
1212 * We pass a in s0 and b in d1. That leaves us
1213 * with s1 being unused. The armhf ABI recognizes
1214 * this and requires register assignment to then
1215 * use that for the next single-precision arg,
1216 * i.e. c in this example. So float_spare either
1217 * tells us which reg to use for the next single-
1218 * precision arg, or it's -1, meaning use *fpr.
1220 * Note that even though most of the JIT speaks
1221 * double-precision, fpr represents single-
1222 * precision registers.
1224 * See parts 5.5 and 6.1.2 of the AAPCS for how
1228 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1229 ainfo->storage = RegTypeFP;
1233 * If we're passing a double-precision value
1234 * and *fpr is odd (e.g. it's s1, s3, ...)
1235 * we need to use the next even register. So
1236 * we mark the current *fpr as a spare that
1237 * can be used for the next single-precision
1241 *float_spare = *fpr;
1246 * At this point, we have an even register
1247 * so we assign that and move along.
1251 } else if (*float_spare >= 0) {
1253 * We're passing a single-precision value
1254 * and it looks like a spare single-
1255 * precision register is available. Let's
1259 ainfo->reg = *float_spare;
1263 * If we hit this branch, we're passing a
1264 * single-precision value and we can simply
1265 * use the next available register.
1273 * We've exhausted available floating point
1274 * regs, so pass the rest on the stack.
1282 ainfo->offset = *stack_size;
1283 ainfo->reg = ARMREG_SP;
1284 ainfo->storage = RegTypeBase;
1291 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1295 MonoClassField *field;
1296 MonoType *ftype, *prev_ftype = NULL;
1299 klass = mono_class_from_mono_type (t);
1301 while ((field = mono_class_get_fields (klass, &iter))) {
1302 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1304 ftype = mono_field_get_type (field);
1305 ftype = mini_type_get_underlying_type (NULL, ftype);
1307 if (MONO_TYPE_ISSTRUCT (ftype)) {
1308 int nested_nfields, nested_esize;
1310 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1312 if (nested_esize == 4)
1313 ftype = &mono_defaults.single_class->byval_arg;
1315 ftype = &mono_defaults.double_class->byval_arg;
1316 if (prev_ftype && prev_ftype->type != ftype->type)
1319 nfields += nested_nfields;
1321 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1323 if (prev_ftype && prev_ftype->type != ftype->type)
1329 if (nfields == 0 || nfields > 4)
1331 *out_nfields = nfields;
1332 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1337 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
1339 guint i, gr, fpr, pstart;
1341 int n = sig->hasthis + sig->param_count;
1345 guint32 stack_size = 0;
1347 gboolean is_pinvoke = sig->pinvoke;
1348 gboolean vtype_retaddr = FALSE;
1351 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1353 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1360 t = mini_type_get_underlying_type (gsctx, sig->ret);
1371 case MONO_TYPE_FNPTR:
1372 case MONO_TYPE_CLASS:
1373 case MONO_TYPE_OBJECT:
1374 case MONO_TYPE_SZARRAY:
1375 case MONO_TYPE_ARRAY:
1376 case MONO_TYPE_STRING:
1377 cinfo->ret.storage = RegTypeGeneral;
1378 cinfo->ret.reg = ARMREG_R0;
1382 cinfo->ret.storage = RegTypeIRegPair;
1383 cinfo->ret.reg = ARMREG_R0;
1387 cinfo->ret.storage = RegTypeFP;
1389 if (t->type == MONO_TYPE_R4)
1390 cinfo->ret.size = 4;
1392 cinfo->ret.size = 8;
1394 if (IS_HARD_FLOAT) {
1395 cinfo->ret.reg = ARM_VFP_F0;
1397 cinfo->ret.reg = ARMREG_R0;
1400 case MONO_TYPE_GENERICINST:
1401 if (!mono_type_generic_inst_is_valuetype (t)) {
1402 cinfo->ret.storage = RegTypeGeneral;
1403 cinfo->ret.reg = ARMREG_R0;
1406 // FIXME: Only for variable types
1407 if (mini_is_gsharedvt_type_gsctx (gsctx, t)) {
1408 cinfo->ret.storage = RegTypeStructByAddr;
1412 case MONO_TYPE_VALUETYPE:
1413 case MONO_TYPE_TYPEDBYREF:
1414 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1415 cinfo->ret.storage = RegTypeHFA;
1417 cinfo->ret.nregs = nfields;
1418 cinfo->ret.esize = esize;
1420 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1421 cinfo->ret.storage = RegTypeStructByVal;
1423 cinfo->ret.storage = RegTypeStructByAddr;
1427 case MONO_TYPE_MVAR:
1428 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, t));
1429 cinfo->ret.storage = RegTypeStructByAddr;
1431 case MONO_TYPE_VOID:
1434 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1437 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1442 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1443 * the first argument, allowing 'this' to be always passed in the first arg reg.
1444 * Also do this if the first argument is a reference type, since virtual calls
1445 * are sometimes made using calli without sig->hasthis set, like in the delegate
1448 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1450 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1452 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1456 cinfo->ret.reg = gr;
1458 cinfo->vret_arg_index = 1;
1462 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1465 if (vtype_retaddr) {
1466 cinfo->ret.reg = gr;
1471 DEBUG(printf("params: %d\n", sig->param_count));
1472 for (i = pstart; i < sig->param_count; ++i) {
1473 ArgInfo *ainfo = &cinfo->args [n];
1475 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1476 /* Prevent implicit arguments and sig_cookie from
1477 being passed in registers */
1480 /* Emit the signature cookie just before the implicit arguments */
1481 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1483 DEBUG(printf("param %d: ", i));
1484 if (sig->params [i]->byref) {
1485 DEBUG(printf("byref\n"));
1486 add_general (&gr, &stack_size, ainfo, TRUE);
1490 t = mini_type_get_underlying_type (gsctx, sig->params [i]);
1494 cinfo->args [n].size = 1;
1495 add_general (&gr, &stack_size, ainfo, TRUE);
1499 cinfo->args [n].size = 2;
1500 add_general (&gr, &stack_size, ainfo, TRUE);
1504 cinfo->args [n].size = 4;
1505 add_general (&gr, &stack_size, ainfo, TRUE);
1510 case MONO_TYPE_FNPTR:
1511 case MONO_TYPE_CLASS:
1512 case MONO_TYPE_OBJECT:
1513 case MONO_TYPE_STRING:
1514 case MONO_TYPE_SZARRAY:
1515 case MONO_TYPE_ARRAY:
1516 cinfo->args [n].size = sizeof (gpointer);
1517 add_general (&gr, &stack_size, ainfo, TRUE);
1519 case MONO_TYPE_GENERICINST:
1520 if (!mono_type_generic_inst_is_valuetype (t)) {
1521 cinfo->args [n].size = sizeof (gpointer);
1522 add_general (&gr, &stack_size, ainfo, TRUE);
1525 if (mini_is_gsharedvt_type_gsctx (gsctx, t)) {
1526 /* gsharedvt arguments are passed by ref */
1527 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, t));
1528 add_general (&gr, &stack_size, ainfo, TRUE);
1529 switch (ainfo->storage) {
1530 case RegTypeGeneral:
1531 ainfo->storage = RegTypeGSharedVtInReg;
1534 ainfo->storage = RegTypeGSharedVtOnStack;
1537 g_assert_not_reached ();
1542 case MONO_TYPE_TYPEDBYREF:
1543 case MONO_TYPE_VALUETYPE: {
1546 int nwords, nfields, esize;
1549 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1550 if (fpr + nfields < ARM_VFP_F16) {
1551 ainfo->storage = RegTypeHFA;
1553 ainfo->nregs = nfields;
1554 ainfo->esize = esize;
1562 if (t->type == MONO_TYPE_TYPEDBYREF) {
1563 size = sizeof (MonoTypedRef);
1564 align = sizeof (gpointer);
1566 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1568 size = mono_class_native_size (klass, &align);
1570 size = mini_type_stack_size_full (gsctx, t, &align, FALSE);
1572 DEBUG(printf ("load %d bytes struct\n", size));
1575 align_size += (sizeof (gpointer) - 1);
1576 align_size &= ~(sizeof (gpointer) - 1);
1577 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1578 ainfo->storage = RegTypeStructByVal;
1579 ainfo->struct_size = size;
1580 /* FIXME: align stack_size if needed */
1581 if (eabi_supported) {
1582 if (align >= 8 && (gr & 1))
1585 if (gr > ARMREG_R3) {
1587 ainfo->vtsize = nwords;
1589 int rest = ARMREG_R3 - gr + 1;
1590 int n_in_regs = rest >= nwords? nwords: rest;
1592 ainfo->size = n_in_regs;
1593 ainfo->vtsize = nwords - n_in_regs;
1596 nwords -= n_in_regs;
1598 if (sig->call_convention == MONO_CALL_VARARG)
1599 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1600 stack_size = ALIGN_TO (stack_size, align);
1601 ainfo->offset = stack_size;
1602 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1603 stack_size += nwords * sizeof (gpointer);
1609 add_general (&gr, &stack_size, ainfo, FALSE);
1615 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1617 add_general (&gr, &stack_size, ainfo, TRUE);
1623 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1625 add_general (&gr, &stack_size, ainfo, FALSE);
1628 case MONO_TYPE_MVAR:
1629 /* gsharedvt arguments are passed by ref */
1630 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, t));
1631 add_general (&gr, &stack_size, ainfo, TRUE);
1632 switch (ainfo->storage) {
1633 case RegTypeGeneral:
1634 ainfo->storage = RegTypeGSharedVtInReg;
1637 ainfo->storage = RegTypeGSharedVtOnStack;
1640 g_assert_not_reached ();
1644 g_error ("Can't handle 0x%x", sig->params [i]->type);
1649 /* Handle the case where there are no implicit arguments */
1650 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1651 /* Prevent implicit arguments and sig_cookie from
1652 being passed in registers */
1655 /* Emit the signature cookie just before the implicit arguments */
1656 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1659 /* align stack size to 8 */
1660 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1661 stack_size = (stack_size + 7) & ~7;
1663 cinfo->stack_usage = stack_size;
1669 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1671 MonoType *callee_ret;
1675 c1 = get_call_info (NULL, NULL, caller_sig);
1676 c2 = get_call_info (NULL, NULL, callee_sig);
1679 * Tail calls with more callee stack usage than the caller cannot be supported, since
1680 * the extra stack space would be left on the stack after the tail call.
1682 res = c1->stack_usage >= c2->stack_usage;
1683 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1684 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1685 /* An address on the callee's stack is passed as the first argument */
1688 if (c2->stack_usage > 16 * 4)
1700 debug_omit_fp (void)
1703 return mono_debug_count ();
1710 * mono_arch_compute_omit_fp:
1712 * Determine whenever the frame pointer can be eliminated.
1715 mono_arch_compute_omit_fp (MonoCompile *cfg)
1717 MonoMethodSignature *sig;
1718 MonoMethodHeader *header;
1722 if (cfg->arch.omit_fp_computed)
1725 header = cfg->header;
1727 sig = mono_method_signature (cfg->method);
1729 if (!cfg->arch.cinfo)
1730 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1731 cinfo = cfg->arch.cinfo;
1734 * FIXME: Remove some of the restrictions.
1736 cfg->arch.omit_fp = TRUE;
1737 cfg->arch.omit_fp_computed = TRUE;
1739 if (cfg->disable_omit_fp)
1740 cfg->arch.omit_fp = FALSE;
1741 if (!debug_omit_fp ())
1742 cfg->arch.omit_fp = FALSE;
1744 if (cfg->method->save_lmf)
1745 cfg->arch.omit_fp = FALSE;
1747 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1748 cfg->arch.omit_fp = FALSE;
1749 if (header->num_clauses)
1750 cfg->arch.omit_fp = FALSE;
1751 if (cfg->param_area)
1752 cfg->arch.omit_fp = FALSE;
1753 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1754 cfg->arch.omit_fp = FALSE;
1755 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1756 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1757 cfg->arch.omit_fp = FALSE;
1758 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1759 ArgInfo *ainfo = &cinfo->args [i];
1761 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1763 * The stack offset can only be determined when the frame
1766 cfg->arch.omit_fp = FALSE;
1771 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1772 MonoInst *ins = cfg->varinfo [i];
1775 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1780 * Set var information according to the calling convention. arm version.
1781 * The locals var stuff should most likely be split in another method.
1784 mono_arch_allocate_vars (MonoCompile *cfg)
1786 MonoMethodSignature *sig;
1787 MonoMethodHeader *header;
1790 int i, offset, size, align, curinst;
1795 sig = mono_method_signature (cfg->method);
1797 if (!cfg->arch.cinfo)
1798 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1799 cinfo = cfg->arch.cinfo;
1800 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1802 mono_arch_compute_omit_fp (cfg);
1804 if (cfg->arch.omit_fp)
1805 cfg->frame_reg = ARMREG_SP;
1807 cfg->frame_reg = ARMREG_FP;
1809 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1811 /* allow room for the vararg method args: void* and long/double */
1812 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1813 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1815 header = cfg->header;
1817 /* See mono_arch_get_global_int_regs () */
1818 if (cfg->flags & MONO_CFG_HAS_CALLS)
1819 cfg->uses_rgctx_reg = TRUE;
1821 if (cfg->frame_reg != ARMREG_SP)
1822 cfg->used_int_regs |= 1 << cfg->frame_reg;
1824 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1825 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1826 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1830 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1831 if (sig_ret->type != MONO_TYPE_VOID) {
1832 cfg->ret->opcode = OP_REGVAR;
1833 cfg->ret->inst_c0 = ARMREG_R0;
1836 /* local vars are at a positive offset from the stack pointer */
1838 * also note that if the function uses alloca, we use FP
1839 * to point at the local variables.
1841 offset = 0; /* linkage area */
1842 /* align the offset to 16 bytes: not sure this is needed here */
1844 //offset &= ~(8 - 1);
1846 /* add parameter area size for called functions */
1847 offset += cfg->param_area;
1850 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1853 /* allow room to save the return value */
1854 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1857 switch (cinfo->ret.storage) {
1858 case RegTypeStructByVal:
1859 cfg->ret->opcode = OP_REGOFFSET;
1860 cfg->ret->inst_basereg = cfg->frame_reg;
1861 offset += sizeof (gpointer) - 1;
1862 offset &= ~(sizeof (gpointer) - 1);
1863 cfg->ret->inst_offset = - offset;
1864 offset += sizeof(gpointer);
1867 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1868 offset = ALIGN_TO (offset, 8);
1869 cfg->ret->opcode = OP_REGOFFSET;
1870 cfg->ret->inst_basereg = cfg->frame_reg;
1871 cfg->ret->inst_offset = offset;
1875 case RegTypeStructByAddr:
1876 ins = cfg->vret_addr;
1877 offset += sizeof(gpointer) - 1;
1878 offset &= ~(sizeof(gpointer) - 1);
1879 ins->inst_offset = offset;
1880 ins->opcode = OP_REGOFFSET;
1881 ins->inst_basereg = cfg->frame_reg;
1882 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1883 printf ("vret_addr =");
1884 mono_print_ins (cfg->vret_addr);
1886 offset += sizeof(gpointer);
1892 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1893 if (cfg->arch.seq_point_info_var) {
1896 ins = cfg->arch.seq_point_info_var;
1900 offset += align - 1;
1901 offset &= ~(align - 1);
1902 ins->opcode = OP_REGOFFSET;
1903 ins->inst_basereg = cfg->frame_reg;
1904 ins->inst_offset = offset;
1907 ins = cfg->arch.ss_trigger_page_var;
1910 offset += align - 1;
1911 offset &= ~(align - 1);
1912 ins->opcode = OP_REGOFFSET;
1913 ins->inst_basereg = cfg->frame_reg;
1914 ins->inst_offset = offset;
1918 if (cfg->arch.seq_point_read_var) {
1921 ins = cfg->arch.seq_point_read_var;
1925 offset += align - 1;
1926 offset &= ~(align - 1);
1927 ins->opcode = OP_REGOFFSET;
1928 ins->inst_basereg = cfg->frame_reg;
1929 ins->inst_offset = offset;
1932 ins = cfg->arch.seq_point_ss_method_var;
1935 offset += align - 1;
1936 offset &= ~(align - 1);
1937 ins->opcode = OP_REGOFFSET;
1938 ins->inst_basereg = cfg->frame_reg;
1939 ins->inst_offset = offset;
1942 ins = cfg->arch.seq_point_bp_method_var;
1945 offset += align - 1;
1946 offset &= ~(align - 1);
1947 ins->opcode = OP_REGOFFSET;
1948 ins->inst_basereg = cfg->frame_reg;
1949 ins->inst_offset = offset;
1953 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1954 /* Allocate a temporary used by the atomic ops */
1958 /* Allocate a local slot to hold the sig cookie address */
1959 offset += align - 1;
1960 offset &= ~(align - 1);
1961 cfg->arch.atomic_tmp_offset = offset;
1964 cfg->arch.atomic_tmp_offset = -1;
1967 cfg->locals_min_stack_offset = offset;
1969 curinst = cfg->locals_start;
1970 for (i = curinst; i < cfg->num_varinfo; ++i) {
1973 ins = cfg->varinfo [i];
1974 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1977 t = ins->inst_vtype;
1978 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (cfg, t))
1981 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1982 * pinvoke wrappers when they call functions returning structure */
1983 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1984 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1988 size = mono_type_size (t, &align);
1990 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1991 * since it loads/stores misaligned words, which don't do the right thing.
1993 if (align < 4 && size >= 4)
1995 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1996 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1997 offset += align - 1;
1998 offset &= ~(align - 1);
1999 ins->opcode = OP_REGOFFSET;
2000 ins->inst_offset = offset;
2001 ins->inst_basereg = cfg->frame_reg;
2003 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2006 cfg->locals_max_stack_offset = offset;
2010 ins = cfg->args [curinst];
2011 if (ins->opcode != OP_REGVAR) {
2012 ins->opcode = OP_REGOFFSET;
2013 ins->inst_basereg = cfg->frame_reg;
2014 offset += sizeof (gpointer) - 1;
2015 offset &= ~(sizeof (gpointer) - 1);
2016 ins->inst_offset = offset;
2017 offset += sizeof (gpointer);
2022 if (sig->call_convention == MONO_CALL_VARARG) {
2026 /* Allocate a local slot to hold the sig cookie address */
2027 offset += align - 1;
2028 offset &= ~(align - 1);
2029 cfg->sig_cookie = offset;
2033 for (i = 0; i < sig->param_count; ++i) {
2034 ainfo = cinfo->args + i;
2036 ins = cfg->args [curinst];
2038 switch (ainfo->storage) {
2040 offset = ALIGN_TO (offset, 8);
2041 ins->opcode = OP_REGOFFSET;
2042 ins->inst_basereg = cfg->frame_reg;
2043 /* These arguments are saved to the stack in the prolog */
2044 ins->inst_offset = offset;
2045 if (cfg->verbose_level >= 2)
2046 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2054 if (ins->opcode != OP_REGVAR) {
2055 ins->opcode = OP_REGOFFSET;
2056 ins->inst_basereg = cfg->frame_reg;
2057 size = mini_type_stack_size_full (cfg->generic_sharing_context, sig->params [i], &ualign, sig->pinvoke);
2059 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2060 * since it loads/stores misaligned words, which don't do the right thing.
2062 if (align < 4 && size >= 4)
2064 /* The code in the prolog () stores words when storing vtypes received in a register */
2065 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2067 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2068 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2069 offset += align - 1;
2070 offset &= ~(align - 1);
2071 ins->inst_offset = offset;
2077 /* align the offset to 8 bytes */
2078 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2079 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2084 cfg->stack_offset = offset;
2088 mono_arch_create_vars (MonoCompile *cfg)
2090 MonoMethodSignature *sig;
2094 sig = mono_method_signature (cfg->method);
2096 if (!cfg->arch.cinfo)
2097 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2098 cinfo = cfg->arch.cinfo;
2100 if (IS_HARD_FLOAT) {
2101 for (i = 0; i < 2; i++) {
2102 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2103 inst->flags |= MONO_INST_VOLATILE;
2105 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2109 if (cinfo->ret.storage == RegTypeStructByVal)
2110 cfg->ret_var_is_local = TRUE;
2112 if (cinfo->ret.storage == RegTypeStructByAddr) {
2113 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2114 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2115 printf ("vret_addr = ");
2116 mono_print_ins (cfg->vret_addr);
2120 if (cfg->gen_sdb_seq_points) {
2121 if (cfg->soft_breakpoints) {
2122 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2123 ins->flags |= MONO_INST_VOLATILE;
2124 cfg->arch.seq_point_read_var = ins;
2126 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2127 ins->flags |= MONO_INST_VOLATILE;
2128 cfg->arch.seq_point_ss_method_var = ins;
2130 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2131 ins->flags |= MONO_INST_VOLATILE;
2132 cfg->arch.seq_point_bp_method_var = ins;
2134 g_assert (!cfg->compile_aot);
2135 } else if (cfg->compile_aot) {
2136 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2137 ins->flags |= MONO_INST_VOLATILE;
2138 cfg->arch.seq_point_info_var = ins;
2140 /* Allocate a separate variable for this to save 1 load per seq point */
2141 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2142 ins->flags |= MONO_INST_VOLATILE;
2143 cfg->arch.ss_trigger_page_var = ins;
2149 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2151 MonoMethodSignature *tmp_sig;
2154 if (call->tail_call)
2157 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2160 * mono_ArgIterator_Setup assumes the signature cookie is
2161 * passed first and all the arguments which were before it are
2162 * passed on the stack after the signature. So compensate by
2163 * passing a different signature.
2165 tmp_sig = mono_metadata_signature_dup (call->signature);
2166 tmp_sig->param_count -= call->signature->sentinelpos;
2167 tmp_sig->sentinelpos = 0;
2168 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2170 sig_reg = mono_alloc_ireg (cfg);
2171 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2173 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2178 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2183 LLVMCallInfo *linfo;
2185 n = sig->param_count + sig->hasthis;
2187 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2189 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2192 * LLVM always uses the native ABI while we use our own ABI, the
2193 * only difference is the handling of vtypes:
2194 * - we only pass/receive them in registers in some cases, and only
2195 * in 1 or 2 integer registers.
2197 if (cinfo->ret.storage == RegTypeStructByAddr) {
2198 /* Vtype returned using a hidden argument */
2199 linfo->ret.storage = LLVMArgVtypeRetAddr;
2200 linfo->vret_arg_index = cinfo->vret_arg_index;
2201 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
2202 cfg->exception_message = g_strdup ("unknown ret conv");
2203 cfg->disable_llvm = TRUE;
2207 for (i = 0; i < n; ++i) {
2208 ainfo = cinfo->args + i;
2210 linfo->args [i].storage = LLVMArgNone;
2212 switch (ainfo->storage) {
2213 case RegTypeGeneral:
2214 case RegTypeIRegPair:
2216 linfo->args [i].storage = LLVMArgInIReg;
2218 case RegTypeStructByVal:
2219 linfo->args [i].storage = LLVMArgAsIArgs;
2220 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2223 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2224 cfg->disable_llvm = TRUE;
2234 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2237 MonoMethodSignature *sig;
2241 sig = call->signature;
2242 n = sig->param_count + sig->hasthis;
2244 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2246 switch (cinfo->ret.storage) {
2247 case RegTypeStructByVal:
2248 /* The JIT will transform this into a normal call */
2249 call->vret_in_reg = TRUE;
2253 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2254 * the location pointed to by it after call in emit_move_return_value ().
2256 if (!cfg->arch.vret_addr_loc) {
2257 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2258 /* Prevent it from being register allocated or optimized away */
2259 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2262 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2264 case RegTypeStructByAddr: {
2266 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2267 vtarg->sreg1 = call->vret_var->dreg;
2268 vtarg->dreg = mono_alloc_preg (cfg);
2269 MONO_ADD_INS (cfg->cbb, vtarg);
2271 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2278 for (i = 0; i < n; ++i) {
2279 ArgInfo *ainfo = cinfo->args + i;
2282 if (i >= sig->hasthis)
2283 t = sig->params [i - sig->hasthis];
2285 t = &mono_defaults.int_class->byval_arg;
2286 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
2288 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2289 /* Emit the signature cookie just before the implicit arguments */
2290 emit_sig_cookie (cfg, call, cinfo);
2293 in = call->args [i];
2295 switch (ainfo->storage) {
2296 case RegTypeGeneral:
2297 case RegTypeIRegPair:
2298 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2299 MONO_INST_NEW (cfg, ins, OP_MOVE);
2300 ins->dreg = mono_alloc_ireg (cfg);
2301 ins->sreg1 = in->dreg + 1;
2302 MONO_ADD_INS (cfg->cbb, ins);
2303 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2305 MONO_INST_NEW (cfg, ins, OP_MOVE);
2306 ins->dreg = mono_alloc_ireg (cfg);
2307 ins->sreg1 = in->dreg + 2;
2308 MONO_ADD_INS (cfg->cbb, ins);
2309 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2310 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2311 if (ainfo->size == 4) {
2312 if (IS_SOFT_FLOAT) {
2313 /* mono_emit_call_args () have already done the r8->r4 conversion */
2314 /* The converted value is in an int vreg */
2315 MONO_INST_NEW (cfg, ins, OP_MOVE);
2316 ins->dreg = mono_alloc_ireg (cfg);
2317 ins->sreg1 = in->dreg;
2318 MONO_ADD_INS (cfg->cbb, ins);
2319 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2323 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2324 creg = mono_alloc_ireg (cfg);
2325 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2326 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2329 if (IS_SOFT_FLOAT) {
2330 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2331 ins->dreg = mono_alloc_ireg (cfg);
2332 ins->sreg1 = in->dreg;
2333 MONO_ADD_INS (cfg->cbb, ins);
2334 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2336 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2337 ins->dreg = mono_alloc_ireg (cfg);
2338 ins->sreg1 = in->dreg;
2339 MONO_ADD_INS (cfg->cbb, ins);
2340 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2344 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2345 creg = mono_alloc_ireg (cfg);
2346 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2347 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2348 creg = mono_alloc_ireg (cfg);
2349 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2350 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2353 cfg->flags |= MONO_CFG_HAS_FPOUT;
2355 MONO_INST_NEW (cfg, ins, OP_MOVE);
2356 ins->dreg = mono_alloc_ireg (cfg);
2357 ins->sreg1 = in->dreg;
2358 MONO_ADD_INS (cfg->cbb, ins);
2360 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2363 case RegTypeStructByAddr:
2366 /* FIXME: where si the data allocated? */
2367 arg->backend.reg3 = ainfo->reg;
2368 call->used_iregs |= 1 << ainfo->reg;
2369 g_assert_not_reached ();
2372 case RegTypeStructByVal:
2373 case RegTypeGSharedVtInReg:
2374 case RegTypeGSharedVtOnStack:
2376 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2377 ins->opcode = OP_OUTARG_VT;
2378 ins->sreg1 = in->dreg;
2379 ins->klass = in->klass;
2380 ins->inst_p0 = call;
2381 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2382 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2383 mono_call_inst_add_outarg_vt (cfg, call, ins);
2384 MONO_ADD_INS (cfg->cbb, ins);
2387 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2388 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2389 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2390 if (t->type == MONO_TYPE_R8) {
2391 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2394 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2396 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2399 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2402 case RegTypeBaseGen:
2403 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2404 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
2405 MONO_INST_NEW (cfg, ins, OP_MOVE);
2406 ins->dreg = mono_alloc_ireg (cfg);
2407 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
2408 MONO_ADD_INS (cfg->cbb, ins);
2409 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2410 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2413 /* This should work for soft-float as well */
2415 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2416 creg = mono_alloc_ireg (cfg);
2417 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2418 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2419 creg = mono_alloc_ireg (cfg);
2420 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2421 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2422 cfg->flags |= MONO_CFG_HAS_FPOUT;
2424 g_assert_not_reached ();
2428 int fdreg = mono_alloc_freg (cfg);
2430 if (ainfo->size == 8) {
2431 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2432 ins->sreg1 = in->dreg;
2434 MONO_ADD_INS (cfg->cbb, ins);
2436 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2441 * Mono's register allocator doesn't speak single-precision registers that
2442 * overlap double-precision registers (i.e. armhf). So we have to work around
2443 * the register allocator and load the value from memory manually.
2445 * So we create a variable for the float argument and an instruction to store
2446 * the argument into the variable. We then store the list of these arguments
2447 * in cfg->float_args. This list is then used by emit_float_args later to
2448 * pass the arguments in the various call opcodes.
2450 * This is not very nice, and we should really try to fix the allocator.
2453 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2455 /* Make sure the instruction isn't seen as pointless and removed.
2457 float_arg->flags |= MONO_INST_VOLATILE;
2459 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2461 /* We use the dreg to look up the instruction later. The hreg is used to
2462 * emit the instruction that loads the value into the FP reg.
2464 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2465 fad->vreg = float_arg->dreg;
2466 fad->hreg = ainfo->reg;
2468 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2471 call->used_iregs |= 1 << ainfo->reg;
2472 cfg->flags |= MONO_CFG_HAS_FPOUT;
2476 g_assert_not_reached ();
2480 /* Handle the case where there are no implicit arguments */
2481 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2482 emit_sig_cookie (cfg, call, cinfo);
2484 call->call_info = cinfo;
2485 call->stack_usage = cinfo->stack_usage;
2489 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2495 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2496 ins->dreg = mono_alloc_freg (cfg);
2497 ins->sreg1 = arg->dreg;
2498 MONO_ADD_INS (cfg->cbb, ins);
2499 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2502 g_assert_not_reached ();
2508 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2510 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2512 ArgInfo *ainfo = ins->inst_p1;
2513 int ovf_size = ainfo->vtsize;
2514 int doffset = ainfo->offset;
2515 int struct_size = ainfo->struct_size;
2516 int i, soffset, dreg, tmpreg;
2518 switch (ainfo->storage) {
2519 case RegTypeGSharedVtInReg:
2521 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2523 case RegTypeGSharedVtOnStack:
2524 /* Pass by addr on stack */
2525 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2528 for (i = 0; i < ainfo->nregs; ++i) {
2529 if (ainfo->esize == 4)
2530 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2532 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2533 load->dreg = mono_alloc_freg (cfg);
2534 load->inst_basereg = src->dreg;
2535 load->inst_offset = i * ainfo->esize;
2536 MONO_ADD_INS (cfg->cbb, load);
2538 if (ainfo->esize == 4) {
2541 /* See RegTypeFP in mono_arch_emit_call () */
2542 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2543 float_arg->flags |= MONO_INST_VOLATILE;
2544 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2546 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2547 fad->vreg = float_arg->dreg;
2548 fad->hreg = ainfo->reg + i;
2550 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2552 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + i, load);
2558 for (i = 0; i < ainfo->size; ++i) {
2559 dreg = mono_alloc_ireg (cfg);
2560 switch (struct_size) {
2562 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2565 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2568 tmpreg = mono_alloc_ireg (cfg);
2569 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2570 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2571 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2572 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2573 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2574 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2575 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2578 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2581 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2582 soffset += sizeof (gpointer);
2583 struct_size -= sizeof (gpointer);
2585 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2587 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2593 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2595 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2598 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2601 if (COMPILE_LLVM (cfg)) {
2602 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2604 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2605 ins->sreg1 = val->dreg + 1;
2606 ins->sreg2 = val->dreg + 2;
2607 MONO_ADD_INS (cfg->cbb, ins);
2612 case MONO_ARM_FPU_NONE:
2613 if (ret->type == MONO_TYPE_R8) {
2616 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2617 ins->dreg = cfg->ret->dreg;
2618 ins->sreg1 = val->dreg;
2619 MONO_ADD_INS (cfg->cbb, ins);
2622 if (ret->type == MONO_TYPE_R4) {
2623 /* Already converted to an int in method_to_ir () */
2624 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2628 case MONO_ARM_FPU_VFP:
2629 case MONO_ARM_FPU_VFP_HARD:
2630 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2633 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2634 ins->dreg = cfg->ret->dreg;
2635 ins->sreg1 = val->dreg;
2636 MONO_ADD_INS (cfg->cbb, ins);
2641 g_assert_not_reached ();
2645 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2648 #endif /* #ifndef DISABLE_JIT */
2651 mono_arch_is_inst_imm (gint64 imm)
2657 MonoMethodSignature *sig;
2660 MonoType **param_types;
2664 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2668 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2671 switch (cinfo->ret.storage) {
2673 case RegTypeGeneral:
2674 case RegTypeIRegPair:
2675 case RegTypeStructByAddr:
2686 for (i = 0; i < cinfo->nargs; ++i) {
2687 ArgInfo *ainfo = &cinfo->args [i];
2690 switch (ainfo->storage) {
2691 case RegTypeGeneral:
2693 case RegTypeIRegPair:
2696 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2699 case RegTypeStructByVal:
2700 if (ainfo->size == 0)
2701 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2703 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2704 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2712 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2713 for (i = 0; i < sig->param_count; ++i) {
2714 MonoType *t = sig->params [i];
2719 t = mini_replace_type (t);
2742 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2744 ArchDynCallInfo *info;
2748 cinfo = get_call_info (NULL, NULL, sig);
2750 if (!dyn_call_supported (cinfo, sig)) {
2755 info = g_new0 (ArchDynCallInfo, 1);
2756 // FIXME: Preprocess the info to speed up start_dyn_call ()
2758 info->cinfo = cinfo;
2759 info->rtype = mini_type_get_underlying_type (NULL, sig->ret);
2760 info->param_types = g_new0 (MonoType*, sig->param_count);
2761 for (i = 0; i < sig->param_count; ++i)
2762 info->param_types [i] = mini_type_get_underlying_type (NULL, sig->params [i]);
2764 return (MonoDynCallInfo*)info;
2768 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2770 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2772 g_free (ainfo->cinfo);
2777 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2779 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2780 DynCallArgs *p = (DynCallArgs*)buf;
2781 int arg_index, greg, i, j, pindex;
2782 MonoMethodSignature *sig = dinfo->sig;
2784 g_assert (buf_len >= sizeof (DynCallArgs));
2793 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2794 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2799 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2800 p->regs [greg ++] = (mgreg_t)ret;
2802 for (i = pindex; i < sig->param_count; i++) {
2803 MonoType *t = dinfo->param_types [i];
2804 gpointer *arg = args [arg_index ++];
2805 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2808 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2810 else if (ainfo->storage == RegTypeBase)
2811 slot = PARAM_REGS + (ainfo->offset / 4);
2813 g_assert_not_reached ();
2816 p->regs [slot] = (mgreg_t)*arg;
2821 case MONO_TYPE_STRING:
2822 case MONO_TYPE_CLASS:
2823 case MONO_TYPE_ARRAY:
2824 case MONO_TYPE_SZARRAY:
2825 case MONO_TYPE_OBJECT:
2829 p->regs [slot] = (mgreg_t)*arg;
2832 p->regs [slot] = *(guint8*)arg;
2835 p->regs [slot] = *(gint8*)arg;
2838 p->regs [slot] = *(gint16*)arg;
2841 p->regs [slot] = *(guint16*)arg;
2844 p->regs [slot] = *(gint32*)arg;
2847 p->regs [slot] = *(guint32*)arg;
2851 p->regs [slot ++] = (mgreg_t)arg [0];
2852 p->regs [slot] = (mgreg_t)arg [1];
2855 p->regs [slot] = *(mgreg_t*)arg;
2858 p->regs [slot ++] = (mgreg_t)arg [0];
2859 p->regs [slot] = (mgreg_t)arg [1];
2861 case MONO_TYPE_GENERICINST:
2862 if (MONO_TYPE_IS_REFERENCE (t)) {
2863 p->regs [slot] = (mgreg_t)*arg;
2866 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2867 MonoClass *klass = mono_class_from_mono_type (t);
2868 guint8 *nullable_buf;
2871 size = mono_class_value_size (klass, NULL);
2872 nullable_buf = g_alloca (size);
2873 g_assert (nullable_buf);
2875 /* The argument pointed to by arg is either a boxed vtype or null */
2876 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2878 arg = (gpointer*)nullable_buf;
2884 case MONO_TYPE_VALUETYPE:
2885 g_assert (ainfo->storage == RegTypeStructByVal);
2887 if (ainfo->size == 0)
2888 slot = PARAM_REGS + (ainfo->offset / 4);
2892 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2893 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2896 g_assert_not_reached ();
2902 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2904 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2905 MonoType *ptype = ainfo->rtype;
2906 guint8 *ret = ((DynCallArgs*)buf)->ret;
2907 mgreg_t res = ((DynCallArgs*)buf)->res;
2908 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2910 switch (ptype->type) {
2911 case MONO_TYPE_VOID:
2912 *(gpointer*)ret = NULL;
2914 case MONO_TYPE_STRING:
2915 case MONO_TYPE_CLASS:
2916 case MONO_TYPE_ARRAY:
2917 case MONO_TYPE_SZARRAY:
2918 case MONO_TYPE_OBJECT:
2922 *(gpointer*)ret = (gpointer)res;
2928 *(guint8*)ret = res;
2931 *(gint16*)ret = res;
2934 *(guint16*)ret = res;
2937 *(gint32*)ret = res;
2940 *(guint32*)ret = res;
2944 /* This handles endianness as well */
2945 ((gint32*)ret) [0] = res;
2946 ((gint32*)ret) [1] = res2;
2948 case MONO_TYPE_GENERICINST:
2949 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2950 *(gpointer*)ret = (gpointer)res;
2955 case MONO_TYPE_VALUETYPE:
2956 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2961 *(float*)ret = *(float*)&res;
2963 case MONO_TYPE_R8: {
2970 *(double*)ret = *(double*)®s;
2974 g_assert_not_reached ();
2981 * Allow tracing to work with this interface (with an optional argument)
2985 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2989 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2990 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2991 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2992 code = emit_call_reg (code, ARMREG_R2);
3006 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3009 int save_mode = SAVE_NONE;
3011 MonoMethod *method = cfg->method;
3012 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
3013 int rtype = ret_type->type;
3014 int save_offset = cfg->param_area;
3018 offset = code - cfg->native_code;
3019 /* we need about 16 instructions */
3020 if (offset > (cfg->code_size - 16 * 4)) {
3021 cfg->code_size *= 2;
3022 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3023 code = cfg->native_code + offset;
3026 case MONO_TYPE_VOID:
3027 /* special case string .ctor icall */
3028 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3029 save_mode = SAVE_ONE;
3031 save_mode = SAVE_NONE;
3035 save_mode = SAVE_TWO;
3039 save_mode = SAVE_ONE_FP;
3041 save_mode = SAVE_ONE;
3045 save_mode = SAVE_TWO_FP;
3047 save_mode = SAVE_TWO;
3049 case MONO_TYPE_GENERICINST:
3050 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3051 save_mode = SAVE_ONE;
3055 case MONO_TYPE_VALUETYPE:
3056 save_mode = SAVE_STRUCT;
3059 save_mode = SAVE_ONE;
3063 switch (save_mode) {
3065 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3066 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3067 if (enable_arguments) {
3068 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3069 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3073 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3074 if (enable_arguments) {
3075 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3079 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3080 if (enable_arguments) {
3081 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3085 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3086 if (enable_arguments) {
3087 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3091 if (enable_arguments) {
3092 /* FIXME: get the actual address */
3093 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3101 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3102 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3103 code = emit_call_reg (code, ARMREG_IP);
3105 switch (save_mode) {
3107 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3108 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3111 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3114 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3117 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3128 * The immediate field for cond branches is big enough for all reasonable methods
3130 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3131 if (0 && ins->inst_true_bb->native_offset) { \
3132 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3134 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3135 ARM_B_COND (code, (condcode), 0); \
3138 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3140 /* emit an exception if condition is fail
3142 * We assign the extra code used to throw the implicit exceptions
3143 * to cfg->bb_exit as far as the big branch handling is concerned
3145 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3147 mono_add_patch_info (cfg, code - cfg->native_code, \
3148 MONO_PATCH_INFO_EXC, exc_name); \
3149 ARM_BL_COND (code, (condcode), 0); \
3152 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3155 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3160 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3164 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3165 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3167 switch (ins->opcode) {
3170 /* Already done by an arch-independent pass */
3172 case OP_LOAD_MEMBASE:
3173 case OP_LOADI4_MEMBASE:
3175 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3176 * OP_LOAD_MEMBASE offset(basereg), reg
3178 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3179 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3180 ins->inst_basereg == last_ins->inst_destbasereg &&
3181 ins->inst_offset == last_ins->inst_offset) {
3182 if (ins->dreg == last_ins->sreg1) {
3183 MONO_DELETE_INS (bb, ins);
3186 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3187 ins->opcode = OP_MOVE;
3188 ins->sreg1 = last_ins->sreg1;
3192 * Note: reg1 must be different from the basereg in the second load
3193 * OP_LOAD_MEMBASE offset(basereg), reg1
3194 * OP_LOAD_MEMBASE offset(basereg), reg2
3196 * OP_LOAD_MEMBASE offset(basereg), reg1
3197 * OP_MOVE reg1, reg2
3199 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3200 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3201 ins->inst_basereg != last_ins->dreg &&
3202 ins->inst_basereg == last_ins->inst_basereg &&
3203 ins->inst_offset == last_ins->inst_offset) {
3205 if (ins->dreg == last_ins->dreg) {
3206 MONO_DELETE_INS (bb, ins);
3209 ins->opcode = OP_MOVE;
3210 ins->sreg1 = last_ins->dreg;
3213 //g_assert_not_reached ();
3217 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3218 * OP_LOAD_MEMBASE offset(basereg), reg
3220 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3221 * OP_ICONST reg, imm
3223 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3224 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3225 ins->inst_basereg == last_ins->inst_destbasereg &&
3226 ins->inst_offset == last_ins->inst_offset) {
3227 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
3228 ins->opcode = OP_ICONST;
3229 ins->inst_c0 = last_ins->inst_imm;
3230 g_assert_not_reached (); // check this rule
3234 case OP_LOADU1_MEMBASE:
3235 case OP_LOADI1_MEMBASE:
3236 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3237 ins->inst_basereg == last_ins->inst_destbasereg &&
3238 ins->inst_offset == last_ins->inst_offset) {
3239 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3240 ins->sreg1 = last_ins->sreg1;
3243 case OP_LOADU2_MEMBASE:
3244 case OP_LOADI2_MEMBASE:
3245 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3246 ins->inst_basereg == last_ins->inst_destbasereg &&
3247 ins->inst_offset == last_ins->inst_offset) {
3248 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3249 ins->sreg1 = last_ins->sreg1;
3253 ins->opcode = OP_MOVE;
3257 if (ins->dreg == ins->sreg1) {
3258 MONO_DELETE_INS (bb, ins);
3262 * OP_MOVE sreg, dreg
3263 * OP_MOVE dreg, sreg
3265 if (last_ins && last_ins->opcode == OP_MOVE &&
3266 ins->sreg1 == last_ins->dreg &&
3267 ins->dreg == last_ins->sreg1) {
3268 MONO_DELETE_INS (bb, ins);
3277 * the branch_cc_table should maintain the order of these
3291 branch_cc_table [] = {
3305 #define ADD_NEW_INS(cfg,dest,op) do { \
3306 MONO_INST_NEW ((cfg), (dest), (op)); \
3307 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3311 map_to_reg_reg_op (int op)
3320 case OP_COMPARE_IMM:
3322 case OP_ICOMPARE_IMM:
3336 case OP_LOAD_MEMBASE:
3337 return OP_LOAD_MEMINDEX;
3338 case OP_LOADI4_MEMBASE:
3339 return OP_LOADI4_MEMINDEX;
3340 case OP_LOADU4_MEMBASE:
3341 return OP_LOADU4_MEMINDEX;
3342 case OP_LOADU1_MEMBASE:
3343 return OP_LOADU1_MEMINDEX;
3344 case OP_LOADI2_MEMBASE:
3345 return OP_LOADI2_MEMINDEX;
3346 case OP_LOADU2_MEMBASE:
3347 return OP_LOADU2_MEMINDEX;
3348 case OP_LOADI1_MEMBASE:
3349 return OP_LOADI1_MEMINDEX;
3350 case OP_STOREI1_MEMBASE_REG:
3351 return OP_STOREI1_MEMINDEX;
3352 case OP_STOREI2_MEMBASE_REG:
3353 return OP_STOREI2_MEMINDEX;
3354 case OP_STOREI4_MEMBASE_REG:
3355 return OP_STOREI4_MEMINDEX;
3356 case OP_STORE_MEMBASE_REG:
3357 return OP_STORE_MEMINDEX;
3358 case OP_STORER4_MEMBASE_REG:
3359 return OP_STORER4_MEMINDEX;
3360 case OP_STORER8_MEMBASE_REG:
3361 return OP_STORER8_MEMINDEX;
3362 case OP_STORE_MEMBASE_IMM:
3363 return OP_STORE_MEMBASE_REG;
3364 case OP_STOREI1_MEMBASE_IMM:
3365 return OP_STOREI1_MEMBASE_REG;
3366 case OP_STOREI2_MEMBASE_IMM:
3367 return OP_STOREI2_MEMBASE_REG;
3368 case OP_STOREI4_MEMBASE_IMM:
3369 return OP_STOREI4_MEMBASE_REG;
3371 g_assert_not_reached ();
3375 * Remove from the instruction list the instructions that can't be
3376 * represented with very simple instructions with no register
3380 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3382 MonoInst *ins, *temp, *last_ins = NULL;
3383 int rot_amount, imm8, low_imm;
3385 MONO_BB_FOR_EACH_INS (bb, ins) {
3387 switch (ins->opcode) {
3391 case OP_COMPARE_IMM:
3392 case OP_ICOMPARE_IMM:
3406 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3407 ADD_NEW_INS (cfg, temp, OP_ICONST);
3408 temp->inst_c0 = ins->inst_imm;
3409 temp->dreg = mono_alloc_ireg (cfg);
3410 ins->sreg2 = temp->dreg;
3411 ins->opcode = mono_op_imm_to_op (ins->opcode);
3413 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3419 if (ins->inst_imm == 1) {
3420 ins->opcode = OP_MOVE;
3423 if (ins->inst_imm == 0) {
3424 ins->opcode = OP_ICONST;
3428 imm8 = mono_is_power_of_two (ins->inst_imm);
3430 ins->opcode = OP_SHL_IMM;
3431 ins->inst_imm = imm8;
3434 ADD_NEW_INS (cfg, temp, OP_ICONST);
3435 temp->inst_c0 = ins->inst_imm;
3436 temp->dreg = mono_alloc_ireg (cfg);
3437 ins->sreg2 = temp->dreg;
3438 ins->opcode = OP_IMUL;
3444 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3445 /* ARM sets the C flag to 1 if there was _no_ overflow */
3446 ins->next->opcode = OP_COND_EXC_NC;
3449 case OP_IDIV_UN_IMM:
3451 case OP_IREM_UN_IMM:
3452 ADD_NEW_INS (cfg, temp, OP_ICONST);
3453 temp->inst_c0 = ins->inst_imm;
3454 temp->dreg = mono_alloc_ireg (cfg);
3455 ins->sreg2 = temp->dreg;
3456 ins->opcode = mono_op_imm_to_op (ins->opcode);
3458 case OP_LOCALLOC_IMM:
3459 ADD_NEW_INS (cfg, temp, OP_ICONST);
3460 temp->inst_c0 = ins->inst_imm;
3461 temp->dreg = mono_alloc_ireg (cfg);
3462 ins->sreg1 = temp->dreg;
3463 ins->opcode = OP_LOCALLOC;
3465 case OP_LOAD_MEMBASE:
3466 case OP_LOADI4_MEMBASE:
3467 case OP_LOADU4_MEMBASE:
3468 case OP_LOADU1_MEMBASE:
3469 /* we can do two things: load the immed in a register
3470 * and use an indexed load, or see if the immed can be
3471 * represented as an ad_imm + a load with a smaller offset
3472 * that fits. We just do the first for now, optimize later.
3474 if (arm_is_imm12 (ins->inst_offset))
3476 ADD_NEW_INS (cfg, temp, OP_ICONST);
3477 temp->inst_c0 = ins->inst_offset;
3478 temp->dreg = mono_alloc_ireg (cfg);
3479 ins->sreg2 = temp->dreg;
3480 ins->opcode = map_to_reg_reg_op (ins->opcode);
3482 case OP_LOADI2_MEMBASE:
3483 case OP_LOADU2_MEMBASE:
3484 case OP_LOADI1_MEMBASE:
3485 if (arm_is_imm8 (ins->inst_offset))
3487 ADD_NEW_INS (cfg, temp, OP_ICONST);
3488 temp->inst_c0 = ins->inst_offset;
3489 temp->dreg = mono_alloc_ireg (cfg);
3490 ins->sreg2 = temp->dreg;
3491 ins->opcode = map_to_reg_reg_op (ins->opcode);
3493 case OP_LOADR4_MEMBASE:
3494 case OP_LOADR8_MEMBASE:
3495 if (arm_is_fpimm8 (ins->inst_offset))
3497 low_imm = ins->inst_offset & 0x1ff;
3498 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3499 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3500 temp->inst_imm = ins->inst_offset & ~0x1ff;
3501 temp->sreg1 = ins->inst_basereg;
3502 temp->dreg = mono_alloc_ireg (cfg);
3503 ins->inst_basereg = temp->dreg;
3504 ins->inst_offset = low_imm;
3508 ADD_NEW_INS (cfg, temp, OP_ICONST);
3509 temp->inst_c0 = ins->inst_offset;
3510 temp->dreg = mono_alloc_ireg (cfg);
3512 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3513 add_ins->sreg1 = ins->inst_basereg;
3514 add_ins->sreg2 = temp->dreg;
3515 add_ins->dreg = mono_alloc_ireg (cfg);
3517 ins->inst_basereg = add_ins->dreg;
3518 ins->inst_offset = 0;
3521 case OP_STORE_MEMBASE_REG:
3522 case OP_STOREI4_MEMBASE_REG:
3523 case OP_STOREI1_MEMBASE_REG:
3524 if (arm_is_imm12 (ins->inst_offset))
3526 ADD_NEW_INS (cfg, temp, OP_ICONST);
3527 temp->inst_c0 = ins->inst_offset;
3528 temp->dreg = mono_alloc_ireg (cfg);
3529 ins->sreg2 = temp->dreg;
3530 ins->opcode = map_to_reg_reg_op (ins->opcode);
3532 case OP_STOREI2_MEMBASE_REG:
3533 if (arm_is_imm8 (ins->inst_offset))
3535 ADD_NEW_INS (cfg, temp, OP_ICONST);
3536 temp->inst_c0 = ins->inst_offset;
3537 temp->dreg = mono_alloc_ireg (cfg);
3538 ins->sreg2 = temp->dreg;
3539 ins->opcode = map_to_reg_reg_op (ins->opcode);
3541 case OP_STORER4_MEMBASE_REG:
3542 case OP_STORER8_MEMBASE_REG:
3543 if (arm_is_fpimm8 (ins->inst_offset))
3545 low_imm = ins->inst_offset & 0x1ff;
3546 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3547 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3548 temp->inst_imm = ins->inst_offset & ~0x1ff;
3549 temp->sreg1 = ins->inst_destbasereg;
3550 temp->dreg = mono_alloc_ireg (cfg);
3551 ins->inst_destbasereg = temp->dreg;
3552 ins->inst_offset = low_imm;
3556 ADD_NEW_INS (cfg, temp, OP_ICONST);
3557 temp->inst_c0 = ins->inst_offset;
3558 temp->dreg = mono_alloc_ireg (cfg);
3560 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3561 add_ins->sreg1 = ins->inst_destbasereg;
3562 add_ins->sreg2 = temp->dreg;
3563 add_ins->dreg = mono_alloc_ireg (cfg);
3565 ins->inst_destbasereg = add_ins->dreg;
3566 ins->inst_offset = 0;
3569 case OP_STORE_MEMBASE_IMM:
3570 case OP_STOREI1_MEMBASE_IMM:
3571 case OP_STOREI2_MEMBASE_IMM:
3572 case OP_STOREI4_MEMBASE_IMM:
3573 ADD_NEW_INS (cfg, temp, OP_ICONST);
3574 temp->inst_c0 = ins->inst_imm;
3575 temp->dreg = mono_alloc_ireg (cfg);
3576 ins->sreg1 = temp->dreg;
3577 ins->opcode = map_to_reg_reg_op (ins->opcode);
3579 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3582 gboolean swap = FALSE;
3586 /* Optimized away */
3591 /* Some fp compares require swapped operands */
3592 switch (ins->next->opcode) {
3594 ins->next->opcode = OP_FBLT;
3598 ins->next->opcode = OP_FBLT_UN;
3602 ins->next->opcode = OP_FBGE;
3606 ins->next->opcode = OP_FBGE_UN;
3614 ins->sreg1 = ins->sreg2;
3623 bb->last_ins = last_ins;
3624 bb->max_vreg = cfg->next_vreg;
3628 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3632 if (long_ins->opcode == OP_LNEG) {
3634 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3635 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3641 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3643 /* sreg is a float, dreg is an integer reg */
3645 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3647 ARM_TOSIZD (code, vfp_scratch1, sreg);
3649 ARM_TOUIZD (code, vfp_scratch1, sreg);
3650 ARM_FMRS (code, dreg, vfp_scratch1);
3651 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3655 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3656 else if (size == 2) {
3657 ARM_SHL_IMM (code, dreg, dreg, 16);
3658 ARM_SHR_IMM (code, dreg, dreg, 16);
3662 ARM_SHL_IMM (code, dreg, dreg, 24);
3663 ARM_SAR_IMM (code, dreg, dreg, 24);
3664 } else if (size == 2) {
3665 ARM_SHL_IMM (code, dreg, dreg, 16);
3666 ARM_SAR_IMM (code, dreg, dreg, 16);
3673 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3675 /* sreg is a float, dreg is an integer reg */
3677 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3679 ARM_TOSIZS (code, vfp_scratch1, sreg);
3681 ARM_TOUIZS (code, vfp_scratch1, sreg);
3682 ARM_FMRS (code, dreg, vfp_scratch1);
3683 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3687 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3688 else if (size == 2) {
3689 ARM_SHL_IMM (code, dreg, dreg, 16);
3690 ARM_SHR_IMM (code, dreg, dreg, 16);
3694 ARM_SHL_IMM (code, dreg, dreg, 24);
3695 ARM_SAR_IMM (code, dreg, dreg, 24);
3696 } else if (size == 2) {
3697 ARM_SHL_IMM (code, dreg, dreg, 16);
3698 ARM_SAR_IMM (code, dreg, dreg, 16);
3704 #endif /* #ifndef DISABLE_JIT */
3706 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3709 emit_thunk (guint8 *code, gconstpointer target)
3713 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3714 if (thumb_supported)
3715 ARM_BX (code, ARMREG_IP);
3717 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3718 *(guint32*)code = (guint32)target;
3720 mono_arch_flush_icache (p, code - p);
3724 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3726 MonoJitInfo *ji = NULL;
3727 MonoThunkJitInfo *info;
3730 guint8 *orig_target;
3731 guint8 *target_thunk;
3734 domain = mono_domain_get ();
3738 * This can be called multiple times during JITting,
3739 * save the current position in cfg->arch to avoid
3740 * doing a O(n^2) search.
3742 if (!cfg->arch.thunks) {
3743 cfg->arch.thunks = cfg->thunks;
3744 cfg->arch.thunks_size = cfg->thunk_area;
3746 thunks = cfg->arch.thunks;
3747 thunks_size = cfg->arch.thunks_size;
3749 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3750 g_assert_not_reached ();
3753 g_assert (*(guint32*)thunks == 0);
3754 emit_thunk (thunks, target);
3755 arm_patch (code, thunks);
3757 cfg->arch.thunks += THUNK_SIZE;
3758 cfg->arch.thunks_size -= THUNK_SIZE;
3760 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3762 info = mono_jit_info_get_thunk_info (ji);
3765 thunks = (guint8*)ji->code_start + info->thunks_offset;
3766 thunks_size = info->thunks_size;
3768 orig_target = mono_arch_get_call_target (code + 4);
3770 mono_mini_arch_lock ();
3772 target_thunk = NULL;
3773 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3774 /* The call already points to a thunk, because of trampolines etc. */
3775 target_thunk = orig_target;
3777 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3778 if (((guint32*)p) [0] == 0) {
3786 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
3788 if (!target_thunk) {
3789 mono_mini_arch_unlock ();
3790 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3791 g_assert_not_reached ();
3794 emit_thunk (target_thunk, target);
3795 arm_patch (code, target_thunk);
3796 mono_arch_flush_icache (code, 4);
3798 mono_mini_arch_unlock ();
3803 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3805 guint32 *code32 = (void*)code;
3806 guint32 ins = *code32;
3807 guint32 prim = (ins >> 25) & 7;
3808 guint32 tval = GPOINTER_TO_UINT (target);
3810 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3811 if (prim == 5) { /* 101b */
3812 /* the diff starts 8 bytes from the branch opcode */
3813 gint diff = target - code - 8;
3815 gint tmask = 0xffffffff;
3816 if (tval & 1) { /* entering thumb mode */
3817 diff = target - 1 - code - 8;
3818 g_assert (thumb_supported);
3819 tbits = 0xf << 28; /* bl->blx bit pattern */
3820 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3821 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3825 tmask = ~(1 << 24); /* clear the link bit */
3826 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3831 if (diff <= 33554431) {
3833 ins = (ins & 0xff000000) | diff;
3835 *code32 = ins | tbits;
3839 /* diff between 0 and -33554432 */
3840 if (diff >= -33554432) {
3842 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3844 *code32 = ins | tbits;
3849 handle_thunk (cfg, domain, code, target);
3853 #ifdef USE_JUMP_TABLES
3855 gpointer *jte = mono_jumptable_get_entry (code);
3857 jte [0] = (gpointer) target;
3861 * The alternative call sequences looks like this:
3863 * ldr ip, [pc] // loads the address constant
3864 * b 1f // jumps around the constant
3865 * address constant embedded in the code
3870 * There are two cases for patching:
3871 * a) at the end of method emission: in this case code points to the start
3872 * of the call sequence
3873 * b) during runtime patching of the call site: in this case code points
3874 * to the mov pc, ip instruction
3876 * We have to handle also the thunk jump code sequence:
3880 * address constant // execution never reaches here
3882 if ((ins & 0x0ffffff0) == 0x12fff10) {
3883 /* Branch and exchange: the address is constructed in a reg
3884 * We can patch BX when the code sequence is the following:
3885 * ldr ip, [pc, #0] ; 0x8
3892 guint8 *emit = (guint8*)ccode;
3893 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3895 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3896 ARM_BX (emit, ARMREG_IP);
3898 /*patching from magic trampoline*/
3899 if (ins == ccode [3]) {
3900 g_assert (code32 [-4] == ccode [0]);
3901 g_assert (code32 [-3] == ccode [1]);
3902 g_assert (code32 [-1] == ccode [2]);
3903 code32 [-2] = (guint32)target;
3906 /*patching from JIT*/
3907 if (ins == ccode [0]) {
3908 g_assert (code32 [1] == ccode [1]);
3909 g_assert (code32 [3] == ccode [2]);
3910 g_assert (code32 [4] == ccode [3]);
3911 code32 [2] = (guint32)target;
3914 g_assert_not_reached ();
3915 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3923 guint8 *emit = (guint8*)ccode;
3924 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3926 ARM_BLX_REG (emit, ARMREG_IP);
3928 g_assert (code32 [-3] == ccode [0]);
3929 g_assert (code32 [-2] == ccode [1]);
3930 g_assert (code32 [0] == ccode [2]);
3932 code32 [-1] = (guint32)target;
3935 guint32 *tmp = ccode;
3936 guint8 *emit = (guint8*)tmp;
3937 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3938 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3939 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3940 ARM_BX (emit, ARMREG_IP);
3941 if (ins == ccode [2]) {
3942 g_assert_not_reached (); // should be -2 ...
3943 code32 [-1] = (guint32)target;
3946 if (ins == ccode [0]) {
3947 /* handles both thunk jump code and the far call sequence */
3948 code32 [2] = (guint32)target;
3951 g_assert_not_reached ();
3953 // g_print ("patched with 0x%08x\n", ins);
3958 arm_patch (guchar *code, const guchar *target)
3960 arm_patch_general (NULL, NULL, code, target);
3964 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3965 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3966 * to be used with the emit macros.
3967 * Return -1 otherwise.
3970 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3973 for (i = 0; i < 31; i+= 2) {
3974 res = (val << (32 - i)) | (val >> i);
3977 *rot_amount = i? 32 - i: 0;
3984 * Emits in code a sequence of instructions that load the value 'val'
3985 * into the dreg register. Uses at most 4 instructions.
3988 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3990 int imm8, rot_amount;
3992 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3993 /* skip the constant pool */
3999 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4000 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4001 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4002 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4005 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4007 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4011 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4013 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4015 if (val & 0xFF0000) {
4016 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4018 if (val & 0xFF000000) {
4019 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4021 } else if (val & 0xFF00) {
4022 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4023 if (val & 0xFF0000) {
4024 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4026 if (val & 0xFF000000) {
4027 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4029 } else if (val & 0xFF0000) {
4030 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4031 if (val & 0xFF000000) {
4032 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4035 //g_assert_not_reached ();
4041 mono_arm_thumb_supported (void)
4043 return thumb_supported;
4049 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4054 call = (MonoCallInst*)ins;
4055 cinfo = call->call_info;
4057 switch (cinfo->ret.storage) {
4059 MonoInst *loc = cfg->arch.vret_addr_loc;
4062 /* Load the destination address */
4063 g_assert (loc && loc->opcode == OP_REGOFFSET);
4065 if (arm_is_imm12 (loc->inst_offset)) {
4066 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4068 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4069 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4071 for (i = 0; i < cinfo->ret.nregs; ++i) {
4072 if (cinfo->ret.esize == 4)
4073 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4075 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4083 switch (ins->opcode) {
4086 case OP_FCALL_MEMBASE:
4088 MonoType *sig_ret = mini_type_get_underlying_type (NULL, ((MonoCallInst*)ins)->signature->ret);
4089 if (sig_ret->type == MONO_TYPE_R4) {
4090 if (IS_HARD_FLOAT) {
4091 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4093 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4094 ARM_CVTS (code, ins->dreg, ins->dreg);
4097 if (IS_HARD_FLOAT) {
4098 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4100 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4107 case OP_RCALL_MEMBASE: {
4112 sig_ret = mini_type_get_underlying_type (NULL, ((MonoCallInst*)ins)->signature->ret);
4113 g_assert (sig_ret->type == MONO_TYPE_R4);
4114 if (IS_HARD_FLOAT) {
4115 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4117 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4118 ARM_CPYS (code, ins->dreg, ins->dreg);
4130 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4135 guint8 *code = cfg->native_code + cfg->code_len;
4136 MonoInst *last_ins = NULL;
4137 guint last_offset = 0;
4139 int imm8, rot_amount;
4141 /* we don't align basic blocks of loops on arm */
4143 if (cfg->verbose_level > 2)
4144 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4146 cpos = bb->max_offset;
4148 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4149 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4150 //g_assert (!mono_compile_aot);
4153 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4154 /* this is not thread save, but good enough */
4155 /* fixme: howto handle overflows? */
4156 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4159 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4160 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4161 (gpointer)"mono_break");
4162 code = emit_call_seq (cfg, code);
4165 MONO_BB_FOR_EACH_INS (bb, ins) {
4166 offset = code - cfg->native_code;
4168 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4170 if (offset > (cfg->code_size - max_len - 16)) {
4171 cfg->code_size *= 2;
4172 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4173 code = cfg->native_code + offset;
4175 // if (ins->cil_code)
4176 // g_print ("cil code\n");
4177 mono_debug_record_line_number (cfg, ins, offset);
4179 switch (ins->opcode) {
4180 case OP_MEMORY_BARRIER:
4182 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4183 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4187 #ifdef HAVE_AEABI_READ_TP
4188 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4189 (gpointer)"__aeabi_read_tp");
4190 code = emit_call_seq (cfg, code);
4192 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
4194 g_assert_not_reached ();
4197 case OP_ATOMIC_EXCHANGE_I4:
4198 case OP_ATOMIC_CAS_I4:
4199 case OP_ATOMIC_ADD_I4: {
4203 g_assert (v7_supported);
4206 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4208 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4210 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4214 g_assert (cfg->arch.atomic_tmp_offset != -1);
4215 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4217 switch (ins->opcode) {
4218 case OP_ATOMIC_EXCHANGE_I4:
4220 ARM_DMB (code, ARM_DMB_SY);
4221 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4222 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4223 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4225 ARM_B_COND (code, ARMCOND_NE, 0);
4226 arm_patch (buf [1], buf [0]);
4228 case OP_ATOMIC_CAS_I4:
4229 ARM_DMB (code, ARM_DMB_SY);
4231 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4232 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4234 ARM_B_COND (code, ARMCOND_NE, 0);
4235 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4236 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4238 ARM_B_COND (code, ARMCOND_NE, 0);
4239 arm_patch (buf [2], buf [0]);
4240 arm_patch (buf [1], code);
4242 case OP_ATOMIC_ADD_I4:
4244 ARM_DMB (code, ARM_DMB_SY);
4245 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4246 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4247 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4248 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4250 ARM_B_COND (code, ARMCOND_NE, 0);
4251 arm_patch (buf [1], buf [0]);
4254 g_assert_not_reached ();
4257 ARM_DMB (code, ARM_DMB_SY);
4258 if (tmpreg != ins->dreg)
4259 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4260 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4263 case OP_ATOMIC_LOAD_I1:
4264 case OP_ATOMIC_LOAD_U1:
4265 case OP_ATOMIC_LOAD_I2:
4266 case OP_ATOMIC_LOAD_U2:
4267 case OP_ATOMIC_LOAD_I4:
4268 case OP_ATOMIC_LOAD_U4:
4269 case OP_ATOMIC_LOAD_R4:
4270 case OP_ATOMIC_LOAD_R8: {
4271 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4272 ARM_DMB (code, ARM_DMB_SY);
4274 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4276 switch (ins->opcode) {
4277 case OP_ATOMIC_LOAD_I1:
4278 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4280 case OP_ATOMIC_LOAD_U1:
4281 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4283 case OP_ATOMIC_LOAD_I2:
4284 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4286 case OP_ATOMIC_LOAD_U2:
4287 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4289 case OP_ATOMIC_LOAD_I4:
4290 case OP_ATOMIC_LOAD_U4:
4291 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4293 case OP_ATOMIC_LOAD_R4:
4294 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4295 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4296 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4297 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4298 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4300 case OP_ATOMIC_LOAD_R8:
4301 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4302 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4306 ARM_DMB (code, ARM_DMB_SY);
4309 case OP_ATOMIC_STORE_I1:
4310 case OP_ATOMIC_STORE_U1:
4311 case OP_ATOMIC_STORE_I2:
4312 case OP_ATOMIC_STORE_U2:
4313 case OP_ATOMIC_STORE_I4:
4314 case OP_ATOMIC_STORE_U4:
4315 case OP_ATOMIC_STORE_R4:
4316 case OP_ATOMIC_STORE_R8: {
4317 ARM_DMB (code, ARM_DMB_SY);
4319 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4321 switch (ins->opcode) {
4322 case OP_ATOMIC_STORE_I1:
4323 case OP_ATOMIC_STORE_U1:
4324 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4326 case OP_ATOMIC_STORE_I2:
4327 case OP_ATOMIC_STORE_U2:
4328 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4330 case OP_ATOMIC_STORE_I4:
4331 case OP_ATOMIC_STORE_U4:
4332 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4334 case OP_ATOMIC_STORE_R4:
4335 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4336 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4337 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4338 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4339 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4341 case OP_ATOMIC_STORE_R8:
4342 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4343 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4347 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4348 ARM_DMB (code, ARM_DMB_SY);
4352 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4353 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4356 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4357 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4359 case OP_STOREI1_MEMBASE_IMM:
4360 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4361 g_assert (arm_is_imm12 (ins->inst_offset));
4362 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4364 case OP_STOREI2_MEMBASE_IMM:
4365 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4366 g_assert (arm_is_imm8 (ins->inst_offset));
4367 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4369 case OP_STORE_MEMBASE_IMM:
4370 case OP_STOREI4_MEMBASE_IMM:
4371 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4372 g_assert (arm_is_imm12 (ins->inst_offset));
4373 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4375 case OP_STOREI1_MEMBASE_REG:
4376 g_assert (arm_is_imm12 (ins->inst_offset));
4377 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4379 case OP_STOREI2_MEMBASE_REG:
4380 g_assert (arm_is_imm8 (ins->inst_offset));
4381 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4383 case OP_STORE_MEMBASE_REG:
4384 case OP_STOREI4_MEMBASE_REG:
4385 /* this case is special, since it happens for spill code after lowering has been called */
4386 if (arm_is_imm12 (ins->inst_offset)) {
4387 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4389 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4390 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4393 case OP_STOREI1_MEMINDEX:
4394 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4396 case OP_STOREI2_MEMINDEX:
4397 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4399 case OP_STORE_MEMINDEX:
4400 case OP_STOREI4_MEMINDEX:
4401 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4404 g_assert_not_reached ();
4406 case OP_LOAD_MEMINDEX:
4407 case OP_LOADI4_MEMINDEX:
4408 case OP_LOADU4_MEMINDEX:
4409 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4411 case OP_LOADI1_MEMINDEX:
4412 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4414 case OP_LOADU1_MEMINDEX:
4415 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4417 case OP_LOADI2_MEMINDEX:
4418 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4420 case OP_LOADU2_MEMINDEX:
4421 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4423 case OP_LOAD_MEMBASE:
4424 case OP_LOADI4_MEMBASE:
4425 case OP_LOADU4_MEMBASE:
4426 /* this case is special, since it happens for spill code after lowering has been called */
4427 if (arm_is_imm12 (ins->inst_offset)) {
4428 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4430 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4431 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4434 case OP_LOADI1_MEMBASE:
4435 g_assert (arm_is_imm8 (ins->inst_offset));
4436 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4438 case OP_LOADU1_MEMBASE:
4439 g_assert (arm_is_imm12 (ins->inst_offset));
4440 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4442 case OP_LOADU2_MEMBASE:
4443 g_assert (arm_is_imm8 (ins->inst_offset));
4444 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4446 case OP_LOADI2_MEMBASE:
4447 g_assert (arm_is_imm8 (ins->inst_offset));
4448 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4450 case OP_ICONV_TO_I1:
4451 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4452 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4454 case OP_ICONV_TO_I2:
4455 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4456 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4458 case OP_ICONV_TO_U1:
4459 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4461 case OP_ICONV_TO_U2:
4462 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4463 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4467 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4469 case OP_COMPARE_IMM:
4470 case OP_ICOMPARE_IMM:
4471 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4472 g_assert (imm8 >= 0);
4473 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4477 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4478 * So instead of emitting a trap, we emit a call a C function and place a
4481 //*(int*)code = 0xef9f0001;
4484 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4485 (gpointer)"mono_break");
4486 code = emit_call_seq (cfg, code);
4488 case OP_RELAXED_NOP:
4493 case OP_DUMMY_STORE:
4494 case OP_DUMMY_ICONST:
4495 case OP_DUMMY_R8CONST:
4496 case OP_NOT_REACHED:
4499 case OP_IL_SEQ_POINT:
4500 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4502 case OP_SEQ_POINT: {
4504 MonoInst *info_var = cfg->arch.seq_point_info_var;
4505 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4506 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
4507 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4508 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4510 int dreg = ARMREG_LR;
4512 if (cfg->soft_breakpoints) {
4513 g_assert (!cfg->compile_aot);
4517 * For AOT, we use one got slot per method, which will point to a
4518 * SeqPointInfo structure, containing all the information required
4519 * by the code below.
4521 if (cfg->compile_aot) {
4522 g_assert (info_var);
4523 g_assert (info_var->opcode == OP_REGOFFSET);
4524 g_assert (arm_is_imm12 (info_var->inst_offset));
4527 if (!cfg->soft_breakpoints) {
4529 * Read from the single stepping trigger page. This will cause a
4530 * SIGSEGV when single stepping is enabled.
4531 * We do this _before_ the breakpoint, so single stepping after
4532 * a breakpoint is hit will step to the next IL offset.
4534 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4537 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4538 if (cfg->soft_breakpoints) {
4539 /* Load the address of the sequence point trigger variable. */
4542 g_assert (var->opcode == OP_REGOFFSET);
4543 g_assert (arm_is_imm12 (var->inst_offset));
4544 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4546 /* Read the value and check whether it is non-zero. */
4547 ARM_LDR_IMM (code, dreg, dreg, 0);
4548 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4550 /* Load the address of the sequence point method. */
4551 var = ss_method_var;
4553 g_assert (var->opcode == OP_REGOFFSET);
4554 g_assert (arm_is_imm12 (var->inst_offset));
4555 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4557 /* Call it conditionally. */
4558 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4560 if (cfg->compile_aot) {
4561 /* Load the trigger page addr from the variable initialized in the prolog */
4562 var = ss_trigger_page_var;
4564 g_assert (var->opcode == OP_REGOFFSET);
4565 g_assert (arm_is_imm12 (var->inst_offset));
4566 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4568 #ifdef USE_JUMP_TABLES
4569 gpointer *jte = mono_jumptable_add_entry ();
4570 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4571 jte [0] = ss_trigger_page;
4573 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4575 *(int*)code = (int)ss_trigger_page;
4579 ARM_LDR_IMM (code, dreg, dreg, 0);
4583 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4585 if (cfg->soft_breakpoints) {
4586 /* Load the address of the breakpoint method into ip. */
4587 var = bp_method_var;
4589 g_assert (var->opcode == OP_REGOFFSET);
4590 g_assert (arm_is_imm12 (var->inst_offset));
4591 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4594 * A placeholder for a possible breakpoint inserted by
4595 * mono_arch_set_breakpoint ().
4598 } else if (cfg->compile_aot) {
4599 guint32 offset = code - cfg->native_code;
4602 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4603 /* Add the offset */
4604 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4605 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4606 if (arm_is_imm12 ((int)val)) {
4607 ARM_LDR_IMM (code, dreg, dreg, val);
4609 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4611 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4613 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4614 g_assert (!(val & 0xFF000000));
4616 ARM_LDR_IMM (code, dreg, dreg, 0);
4618 /* What is faster, a branch or a load ? */
4619 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4620 /* The breakpoint instruction */
4621 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4624 * A placeholder for a possible breakpoint inserted by
4625 * mono_arch_set_breakpoint ().
4627 for (i = 0; i < 4; ++i)
4634 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4637 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4641 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4644 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4645 g_assert (imm8 >= 0);
4646 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4650 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4651 g_assert (imm8 >= 0);
4652 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4656 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4657 g_assert (imm8 >= 0);
4658 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4661 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4662 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4664 case OP_IADD_OVF_UN:
4665 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4666 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4669 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4670 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4672 case OP_ISUB_OVF_UN:
4673 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4674 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4676 case OP_ADD_OVF_CARRY:
4677 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4678 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4680 case OP_ADD_OVF_UN_CARRY:
4681 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4682 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4684 case OP_SUB_OVF_CARRY:
4685 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4686 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4688 case OP_SUB_OVF_UN_CARRY:
4689 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4690 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4694 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4697 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4698 g_assert (imm8 >= 0);
4699 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4702 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4706 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4710 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4711 g_assert (imm8 >= 0);
4712 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4716 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4717 g_assert (imm8 >= 0);
4718 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4720 case OP_ARM_RSBS_IMM:
4721 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4722 g_assert (imm8 >= 0);
4723 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4725 case OP_ARM_RSC_IMM:
4726 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4727 g_assert (imm8 >= 0);
4728 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4731 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4735 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4736 g_assert (imm8 >= 0);
4737 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4740 g_assert (v7s_supported);
4741 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4744 g_assert (v7s_supported);
4745 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4748 g_assert (v7s_supported);
4749 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4750 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4753 g_assert (v7s_supported);
4754 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4755 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4759 g_assert_not_reached ();
4761 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4765 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4766 g_assert (imm8 >= 0);
4767 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4770 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4774 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4775 g_assert (imm8 >= 0);
4776 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4779 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4784 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4785 else if (ins->dreg != ins->sreg1)
4786 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4789 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4794 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4795 else if (ins->dreg != ins->sreg1)
4796 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4799 case OP_ISHR_UN_IMM:
4801 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4802 else if (ins->dreg != ins->sreg1)
4803 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4806 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4809 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4812 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4815 if (ins->dreg == ins->sreg2)
4816 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4818 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4821 g_assert_not_reached ();
4824 /* FIXME: handle ovf/ sreg2 != dreg */
4825 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4826 /* FIXME: MUL doesn't set the C/O flags on ARM */
4828 case OP_IMUL_OVF_UN:
4829 /* FIXME: handle ovf/ sreg2 != dreg */
4830 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4831 /* FIXME: MUL doesn't set the C/O flags on ARM */
4834 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4837 /* Load the GOT offset */
4838 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4839 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4841 *(gpointer*)code = NULL;
4843 /* Load the value from the GOT */
4844 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4846 case OP_OBJC_GET_SELECTOR:
4847 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4848 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4850 *(gpointer*)code = NULL;
4852 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4854 case OP_ICONV_TO_I4:
4855 case OP_ICONV_TO_U4:
4857 if (ins->dreg != ins->sreg1)
4858 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4861 int saved = ins->sreg2;
4862 if (ins->sreg2 == ARM_LSW_REG) {
4863 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4866 if (ins->sreg1 != ARM_LSW_REG)
4867 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4868 if (saved != ARM_MSW_REG)
4869 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4873 if (IS_VFP && ins->dreg != ins->sreg1)
4874 ARM_CPYD (code, ins->dreg, ins->sreg1);
4876 case OP_MOVE_F_TO_I4:
4877 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4878 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4879 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4880 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4882 case OP_MOVE_I4_TO_F:
4883 ARM_FMSR (code, ins->dreg, ins->sreg1);
4884 ARM_CVTS (code, ins->dreg, ins->dreg);
4886 case OP_FCONV_TO_R4:
4889 ARM_CVTD (code, ins->dreg, ins->sreg1);
4891 ARM_CVTD (code, ins->dreg, ins->sreg1);
4892 ARM_CVTS (code, ins->dreg, ins->dreg);
4897 MonoCallInst *call = (MonoCallInst*)ins;
4900 * The stack looks like the following:
4901 * <caller argument area>
4904 * <callee argument area>
4905 * Need to copy the arguments from the callee argument area to
4906 * the caller argument area, and pop the frame.
4908 if (call->stack_usage) {
4909 int i, prev_sp_offset = 0;
4911 /* Compute size of saved registers restored below */
4913 prev_sp_offset = 2 * 4;
4915 prev_sp_offset = 1 * 4;
4916 for (i = 0; i < 16; ++i) {
4917 if (cfg->used_int_regs & (1 << i))
4918 prev_sp_offset += 4;
4921 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4923 /* Copy arguments on the stack to our argument area */
4924 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4925 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4926 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4931 * Keep in sync with mono_arch_emit_epilog
4933 g_assert (!cfg->method->save_lmf);
4935 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4937 if (cfg->used_int_regs)
4938 ARM_POP (code, cfg->used_int_regs);
4939 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4941 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4944 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4945 if (cfg->compile_aot) {
4946 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4948 *(gpointer*)code = NULL;
4950 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4952 code = mono_arm_patchable_b (code, ARMCOND_AL);
4957 /* ensure ins->sreg1 is not NULL */
4958 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4961 g_assert (cfg->sig_cookie < 128);
4962 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4963 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4973 call = (MonoCallInst*)ins;
4976 code = emit_float_args (cfg, call, code, &max_len, &offset);
4978 if (ins->flags & MONO_INST_HAS_METHOD)
4979 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4981 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4982 code = emit_call_seq (cfg, code);
4983 ins->flags |= MONO_INST_GC_CALLSITE;
4984 ins->backend.pc_offset = code - cfg->native_code;
4985 code = emit_move_return_value (cfg, ins, code);
4992 case OP_VOIDCALL_REG:
4995 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
4997 code = emit_call_reg (code, ins->sreg1);
4998 ins->flags |= MONO_INST_GC_CALLSITE;
4999 ins->backend.pc_offset = code - cfg->native_code;
5000 code = emit_move_return_value (cfg, ins, code);
5002 case OP_FCALL_MEMBASE:
5003 case OP_RCALL_MEMBASE:
5004 case OP_LCALL_MEMBASE:
5005 case OP_VCALL_MEMBASE:
5006 case OP_VCALL2_MEMBASE:
5007 case OP_VOIDCALL_MEMBASE:
5008 case OP_CALL_MEMBASE: {
5009 g_assert (ins->sreg1 != ARMREG_LR);
5010 call = (MonoCallInst*)ins;
5013 code = emit_float_args (cfg, call, code, &max_len, &offset);
5014 if (!arm_is_imm12 (ins->inst_offset))
5015 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5016 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5017 if (!arm_is_imm12 (ins->inst_offset))
5018 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5020 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5021 ins->flags |= MONO_INST_GC_CALLSITE;
5022 ins->backend.pc_offset = code - cfg->native_code;
5023 code = emit_move_return_value (cfg, ins, code);
5026 case OP_GENERIC_CLASS_INIT: {
5027 static int byte_offset = -1;
5028 static guint8 bitmask;
5032 if (byte_offset < 0)
5033 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5035 g_assert (arm_is_imm8 (byte_offset));
5036 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5037 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5038 g_assert (imm8 >= 0);
5039 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5040 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5042 ARM_B_COND (code, ARMCOND_NE, 0);
5044 /* Uninitialized case */
5045 g_assert (ins->sreg1 == ARMREG_R0);
5047 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5048 (gpointer)"specific_trampoline_generic_class_init");
5049 code = emit_call_seq (cfg, code);
5051 /* Initialized case */
5052 arm_patch (jump, code);
5056 /* round the size to 8 bytes */
5057 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
5058 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
5059 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5060 /* memzero the area: dreg holds the size, sp is the pointer */
5061 if (ins->flags & MONO_INST_INIT) {
5062 guint8 *start_loop, *branch_to_cond;
5063 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5064 branch_to_cond = code;
5067 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5068 arm_patch (branch_to_cond, code);
5069 /* decrement by 4 and set flags */
5070 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5071 ARM_B_COND (code, ARMCOND_GE, 0);
5072 arm_patch (code - 4, start_loop);
5074 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5075 if (cfg->param_area)
5076 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5081 MonoInst *var = cfg->dyn_call_var;
5083 g_assert (var->opcode == OP_REGOFFSET);
5084 g_assert (arm_is_imm12 (var->inst_offset));
5086 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5087 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5089 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5091 /* Save args buffer */
5092 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5094 /* Set stack slots using R0 as scratch reg */
5095 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5096 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5097 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5098 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5101 /* Set argument registers */
5102 for (i = 0; i < PARAM_REGS; ++i)
5103 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5106 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5107 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5110 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5111 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5112 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5116 if (ins->sreg1 != ARMREG_R0)
5117 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5118 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5119 (gpointer)"mono_arch_throw_exception");
5120 code = emit_call_seq (cfg, code);
5124 if (ins->sreg1 != ARMREG_R0)
5125 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5126 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5127 (gpointer)"mono_arch_rethrow_exception");
5128 code = emit_call_seq (cfg, code);
5131 case OP_START_HANDLER: {
5132 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5135 /* Reserve a param area, see filter-stack.exe */
5136 if (cfg->param_area) {
5137 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5138 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5140 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5141 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5145 if (arm_is_imm12 (spvar->inst_offset)) {
5146 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5148 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5149 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5153 case OP_ENDFILTER: {
5154 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5157 /* Free the param area */
5158 if (cfg->param_area) {
5159 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5160 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5162 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5163 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5167 if (ins->sreg1 != ARMREG_R0)
5168 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5169 if (arm_is_imm12 (spvar->inst_offset)) {
5170 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5172 g_assert (ARMREG_IP != spvar->inst_basereg);
5173 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5174 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5176 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5179 case OP_ENDFINALLY: {
5180 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5183 /* Free the param area */
5184 if (cfg->param_area) {
5185 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
5186 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5188 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
5189 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5193 if (arm_is_imm12 (spvar->inst_offset)) {
5194 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5196 g_assert (ARMREG_IP != spvar->inst_basereg);
5197 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5198 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5200 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5203 case OP_CALL_HANDLER:
5204 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5205 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5206 cfg->thunk_area += THUNK_SIZE;
5207 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5210 if (ins->dreg != ARMREG_R0)
5211 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5215 ins->inst_c0 = code - cfg->native_code;
5218 /*if (ins->inst_target_bb->native_offset) {
5220 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5222 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5223 code = mono_arm_patchable_b (code, ARMCOND_AL);
5227 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5231 * In the normal case we have:
5232 * ldr pc, [pc, ins->sreg1 << 2]
5235 * ldr lr, [pc, ins->sreg1 << 2]
5237 * After follows the data.
5238 * FIXME: add aot support.
5240 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5241 #ifdef USE_JUMP_TABLES
5243 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5244 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5245 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5249 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5250 if (offset + max_len > (cfg->code_size - 16)) {
5251 cfg->code_size += max_len;
5252 cfg->code_size *= 2;
5253 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5254 code = cfg->native_code + offset;
5256 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5258 code += 4 * GPOINTER_TO_INT (ins->klass);
5263 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5264 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5268 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5269 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5273 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5274 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5278 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5279 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5283 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5284 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5287 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5288 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5291 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5292 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5295 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5296 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5299 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5300 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5303 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5304 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5306 case OP_COND_EXC_EQ:
5307 case OP_COND_EXC_NE_UN:
5308 case OP_COND_EXC_LT:
5309 case OP_COND_EXC_LT_UN:
5310 case OP_COND_EXC_GT:
5311 case OP_COND_EXC_GT_UN:
5312 case OP_COND_EXC_GE:
5313 case OP_COND_EXC_GE_UN:
5314 case OP_COND_EXC_LE:
5315 case OP_COND_EXC_LE_UN:
5316 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5318 case OP_COND_EXC_IEQ:
5319 case OP_COND_EXC_INE_UN:
5320 case OP_COND_EXC_ILT:
5321 case OP_COND_EXC_ILT_UN:
5322 case OP_COND_EXC_IGT:
5323 case OP_COND_EXC_IGT_UN:
5324 case OP_COND_EXC_IGE:
5325 case OP_COND_EXC_IGE_UN:
5326 case OP_COND_EXC_ILE:
5327 case OP_COND_EXC_ILE_UN:
5328 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5331 case OP_COND_EXC_IC:
5332 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5334 case OP_COND_EXC_OV:
5335 case OP_COND_EXC_IOV:
5336 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5338 case OP_COND_EXC_NC:
5339 case OP_COND_EXC_INC:
5340 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5342 case OP_COND_EXC_NO:
5343 case OP_COND_EXC_INO:
5344 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5356 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5359 /* floating point opcodes */
5361 if (cfg->compile_aot) {
5362 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5364 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5366 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5369 /* FIXME: we can optimize the imm load by dealing with part of
5370 * the displacement in LDFD (aligning to 512).
5372 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5373 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5377 if (cfg->compile_aot) {
5378 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5380 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5383 ARM_CVTS (code, ins->dreg, ins->dreg);
5385 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5386 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5388 ARM_CVTS (code, ins->dreg, ins->dreg);
5391 case OP_STORER8_MEMBASE_REG:
5392 /* This is generated by the local regalloc pass which runs after the lowering pass */
5393 if (!arm_is_fpimm8 (ins->inst_offset)) {
5394 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5395 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5396 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5398 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5401 case OP_LOADR8_MEMBASE:
5402 /* This is generated by the local regalloc pass which runs after the lowering pass */
5403 if (!arm_is_fpimm8 (ins->inst_offset)) {
5404 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5405 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5406 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5408 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5411 case OP_STORER4_MEMBASE_REG:
5412 g_assert (arm_is_fpimm8 (ins->inst_offset));
5414 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5416 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5417 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5418 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5419 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5422 case OP_LOADR4_MEMBASE:
5424 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5426 g_assert (arm_is_fpimm8 (ins->inst_offset));
5427 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5428 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5429 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5430 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5433 case OP_ICONV_TO_R_UN: {
5434 g_assert_not_reached ();
5437 case OP_ICONV_TO_R4:
5439 ARM_FMSR (code, ins->dreg, ins->sreg1);
5440 ARM_FSITOS (code, ins->dreg, ins->dreg);
5442 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5443 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5444 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5445 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5446 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5449 case OP_ICONV_TO_R8:
5450 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5451 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5452 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5453 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5457 MonoType *sig_ret = mini_type_get_underlying_type (NULL, mono_method_signature (cfg->method)->ret);
5458 if (sig_ret->type == MONO_TYPE_R4) {
5460 g_assert (!IS_HARD_FLOAT);
5461 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5463 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5466 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5470 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5472 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5476 case OP_FCONV_TO_I1:
5477 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5479 case OP_FCONV_TO_U1:
5480 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5482 case OP_FCONV_TO_I2:
5483 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5485 case OP_FCONV_TO_U2:
5486 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5488 case OP_FCONV_TO_I4:
5490 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5492 case OP_FCONV_TO_U4:
5494 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5496 case OP_FCONV_TO_I8:
5497 case OP_FCONV_TO_U8:
5498 g_assert_not_reached ();
5499 /* Implemented as helper calls */
5501 case OP_LCONV_TO_R_UN:
5502 g_assert_not_reached ();
5503 /* Implemented as helper calls */
5505 case OP_LCONV_TO_OVF_I4_2: {
5506 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5508 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5511 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5512 high_bit_not_set = code;
5513 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5515 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5516 valid_negative = code;
5517 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5518 invalid_negative = code;
5519 ARM_B_COND (code, ARMCOND_AL, 0);
5521 arm_patch (high_bit_not_set, code);
5523 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5524 valid_positive = code;
5525 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5527 arm_patch (invalid_negative, code);
5528 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5530 arm_patch (valid_negative, code);
5531 arm_patch (valid_positive, code);
5533 if (ins->dreg != ins->sreg1)
5534 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5538 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5541 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5544 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5547 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5550 ARM_NEGD (code, ins->dreg, ins->sreg1);
5554 g_assert_not_reached ();
5558 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5564 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5569 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5572 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5573 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5577 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5580 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5581 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5585 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5588 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5589 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5590 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5594 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5597 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5598 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5602 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5605 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5606 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5607 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5611 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5614 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5615 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5619 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5622 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5623 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5627 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5630 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5631 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5634 /* ARM FPA flags table:
5635 * N Less than ARMCOND_MI
5636 * Z Equal ARMCOND_EQ
5637 * C Greater Than or Equal ARMCOND_CS
5638 * V Unordered ARMCOND_VS
5641 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5644 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5647 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5650 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5651 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5657 g_assert_not_reached ();
5661 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5663 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5664 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5665 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5669 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5670 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5675 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5676 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5678 #ifdef USE_JUMP_TABLES
5680 gpointer *jte = mono_jumptable_add_entries (2);
5681 jte [0] = GUINT_TO_POINTER (0xffffffff);
5682 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5683 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5684 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5687 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5688 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5690 *(guint32*)code = 0xffffffff;
5692 *(guint32*)code = 0x7fefffff;
5695 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5697 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5698 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5700 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5701 ARM_CPYD (code, ins->dreg, ins->sreg1);
5703 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5704 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5709 case OP_RCONV_TO_I1:
5710 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5712 case OP_RCONV_TO_U1:
5713 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5715 case OP_RCONV_TO_I2:
5716 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5718 case OP_RCONV_TO_U2:
5719 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5721 case OP_RCONV_TO_I4:
5722 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5724 case OP_RCONV_TO_U4:
5725 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5727 case OP_RCONV_TO_R4:
5729 if (ins->dreg != ins->sreg1)
5730 ARM_CPYS (code, ins->dreg, ins->sreg1);
5732 case OP_RCONV_TO_R8:
5734 ARM_CVTS (code, ins->dreg, ins->sreg1);
5737 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5740 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5743 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5746 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5749 ARM_NEGS (code, ins->dreg, ins->sreg1);
5753 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5756 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5757 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5761 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5764 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5765 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5769 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5772 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5773 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5774 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5778 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5781 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5782 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5786 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5789 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5790 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5791 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5795 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5798 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5799 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5803 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5806 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5807 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5811 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5814 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5815 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5818 case OP_GC_LIVENESS_DEF:
5819 case OP_GC_LIVENESS_USE:
5820 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5821 ins->backend.pc_offset = code - cfg->native_code;
5823 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5824 ins->backend.pc_offset = code - cfg->native_code;
5825 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5829 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5830 g_assert_not_reached ();
5833 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5834 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5835 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5836 g_assert_not_reached ();
5842 last_offset = offset;
5845 cfg->code_len = code - cfg->native_code;
5848 #endif /* DISABLE_JIT */
5850 #ifdef HAVE_AEABI_READ_TP
5851 void __aeabi_read_tp (void);
5855 mono_arch_register_lowlevel_calls (void)
5857 /* The signature doesn't matter */
5858 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5859 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5861 #ifndef MONO_CROSS_COMPILE
5862 #ifdef HAVE_AEABI_READ_TP
5863 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
5868 #define patch_lis_ori(ip,val) do {\
5869 guint16 *__lis_ori = (guint16*)(ip); \
5870 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5871 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5875 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5877 unsigned char *ip = ji->ip.i + code;
5879 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5883 case MONO_PATCH_INFO_SWITCH: {
5884 #ifdef USE_JUMP_TABLES
5885 gpointer *jt = mono_jumptable_get_entry (ip);
5887 gpointer *jt = (gpointer*)(ip + 8);
5890 /* jt is the inlined jump table, 2 instructions after ip
5891 * In the normal case we store the absolute addresses,
5892 * otherwise the displacements.
5894 for (i = 0; i < ji->data.table->table_size; i++)
5895 jt [i] = code + (int)ji->data.table->table [i];
5898 case MONO_PATCH_INFO_IP:
5899 g_assert_not_reached ();
5900 patch_lis_ori (ip, ip);
5902 case MONO_PATCH_INFO_METHOD_REL:
5903 g_assert_not_reached ();
5904 *((gpointer *)(ip)) = target;
5906 case MONO_PATCH_INFO_METHODCONST:
5907 case MONO_PATCH_INFO_CLASS:
5908 case MONO_PATCH_INFO_IMAGE:
5909 case MONO_PATCH_INFO_FIELD:
5910 case MONO_PATCH_INFO_VTABLE:
5911 case MONO_PATCH_INFO_IID:
5912 case MONO_PATCH_INFO_SFLDA:
5913 case MONO_PATCH_INFO_LDSTR:
5914 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5915 case MONO_PATCH_INFO_LDTOKEN:
5916 g_assert_not_reached ();
5917 /* from OP_AOTCONST : lis + ori */
5918 patch_lis_ori (ip, target);
5920 case MONO_PATCH_INFO_R4:
5921 case MONO_PATCH_INFO_R8:
5922 g_assert_not_reached ();
5923 *((gconstpointer *)(ip + 2)) = target;
5925 case MONO_PATCH_INFO_EXC_NAME:
5926 g_assert_not_reached ();
5927 *((gconstpointer *)(ip + 1)) = target;
5929 case MONO_PATCH_INFO_NONE:
5930 case MONO_PATCH_INFO_BB_OVF:
5931 case MONO_PATCH_INFO_EXC_OVF:
5932 /* everything is dealt with at epilog output time */
5935 arm_patch_general (cfg, domain, ip, target);
5943 * Stack frame layout:
5945 * ------------------- fp
5946 * MonoLMF structure or saved registers
5947 * -------------------
5949 * -------------------
5951 * -------------------
5952 * optional 8 bytes for tracing
5953 * -------------------
5954 * param area size is cfg->param_area
5955 * ------------------- sp
5958 mono_arch_emit_prolog (MonoCompile *cfg)
5960 MonoMethod *method = cfg->method;
5962 MonoMethodSignature *sig;
5964 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
5969 int prev_sp_offset, reg_offset;
5971 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5974 sig = mono_method_signature (method);
5975 cfg->code_size = 256 + sig->param_count * 64;
5976 code = cfg->native_code = g_malloc (cfg->code_size);
5978 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
5980 alloc_size = cfg->stack_offset;
5986 * The iphone uses R7 as the frame pointer, and it points at the saved
5991 * We can't use r7 as a frame pointer since it points into the middle of
5992 * the frame, so we keep using our own frame pointer.
5993 * FIXME: Optimize this.
5995 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5996 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
5997 prev_sp_offset += 8; /* r7 and lr */
5998 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5999 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6002 if (!method->save_lmf) {
6004 /* No need to push LR again */
6005 if (cfg->used_int_regs)
6006 ARM_PUSH (code, cfg->used_int_regs);
6008 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6009 prev_sp_offset += 4;
6011 for (i = 0; i < 16; ++i) {
6012 if (cfg->used_int_regs & (1 << i))
6013 prev_sp_offset += 4;
6015 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6017 for (i = 0; i < 16; ++i) {
6018 if ((cfg->used_int_regs & (1 << i))) {
6019 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6020 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6025 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6026 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6028 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6029 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6032 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6033 ARM_PUSH (code, 0x5ff0);
6034 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6035 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6037 for (i = 0; i < 16; ++i) {
6038 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6039 /* The original r7 is saved at the start */
6040 if (!(iphone_abi && i == ARMREG_R7))
6041 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6045 g_assert (reg_offset == 4 * 10);
6046 pos += sizeof (MonoLMF) - (4 * 10);
6050 orig_alloc_size = alloc_size;
6051 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6052 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6053 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6054 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6057 /* the stack used in the pushed regs */
6058 if (prev_sp_offset & 4)
6060 cfg->stack_usage = alloc_size;
6062 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6063 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6065 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6066 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6068 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6070 if (cfg->frame_reg != ARMREG_SP) {
6071 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6072 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6074 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6075 prev_sp_offset += alloc_size;
6077 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6078 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6080 /* compute max_offset in order to use short forward jumps
6081 * we could skip do it on arm because the immediate displacement
6082 * for jumps is large enough, it may be useful later for constant pools
6085 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6086 MonoInst *ins = bb->code;
6087 bb->max_offset = max_offset;
6089 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6092 MONO_BB_FOR_EACH_INS (bb, ins)
6093 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6096 /* store runtime generic context */
6097 if (cfg->rgctx_var) {
6098 MonoInst *ins = cfg->rgctx_var;
6100 g_assert (ins->opcode == OP_REGOFFSET);
6102 if (arm_is_imm12 (ins->inst_offset)) {
6103 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6105 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6106 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6110 /* load arguments allocated to register from the stack */
6113 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
6115 if (cinfo->ret.storage == RegTypeStructByAddr) {
6116 ArgInfo *ainfo = &cinfo->ret;
6117 inst = cfg->vret_addr;
6118 g_assert (arm_is_imm12 (inst->inst_offset));
6119 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6122 if (sig->call_convention == MONO_CALL_VARARG) {
6123 ArgInfo *cookie = &cinfo->sig_cookie;
6125 /* Save the sig cookie address */
6126 g_assert (cookie->storage == RegTypeBase);
6128 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6129 g_assert (arm_is_imm12 (cfg->sig_cookie));
6130 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6131 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6134 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6135 ArgInfo *ainfo = cinfo->args + i;
6136 inst = cfg->args [pos];
6138 if (cfg->verbose_level > 2)
6139 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6141 if (inst->opcode == OP_REGVAR) {
6142 if (ainfo->storage == RegTypeGeneral)
6143 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6144 else if (ainfo->storage == RegTypeFP) {
6145 g_assert_not_reached ();
6146 } else if (ainfo->storage == RegTypeBase) {
6147 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6148 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6150 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6151 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6154 g_assert_not_reached ();
6156 if (cfg->verbose_level > 2)
6157 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6159 switch (ainfo->storage) {
6161 for (part = 0; part < ainfo->nregs; part ++) {
6162 if (ainfo->esize == 4)
6163 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6165 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6168 case RegTypeGeneral:
6169 case RegTypeIRegPair:
6170 case RegTypeGSharedVtInReg:
6171 switch (ainfo->size) {
6173 if (arm_is_imm12 (inst->inst_offset))
6174 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6176 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6177 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6181 if (arm_is_imm8 (inst->inst_offset)) {
6182 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6184 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6185 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6189 if (arm_is_imm12 (inst->inst_offset)) {
6190 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6192 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6193 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6195 if (arm_is_imm12 (inst->inst_offset + 4)) {
6196 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6198 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6199 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6203 if (arm_is_imm12 (inst->inst_offset)) {
6204 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6206 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6207 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6212 case RegTypeBaseGen:
6213 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6214 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6216 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6217 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6219 if (arm_is_imm12 (inst->inst_offset + 4)) {
6220 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6221 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6223 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6224 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6225 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6226 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6230 case RegTypeGSharedVtOnStack:
6231 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6232 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6234 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6235 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6238 switch (ainfo->size) {
6240 if (arm_is_imm8 (inst->inst_offset)) {
6241 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6243 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6244 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6248 if (arm_is_imm8 (inst->inst_offset)) {
6249 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6251 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6252 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6256 if (arm_is_imm12 (inst->inst_offset)) {
6257 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6259 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6260 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6262 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6263 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6265 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6266 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6268 if (arm_is_imm12 (inst->inst_offset + 4)) {
6269 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6271 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6272 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6276 if (arm_is_imm12 (inst->inst_offset)) {
6277 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6279 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6280 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6286 int imm8, rot_amount;
6288 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6289 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6290 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6292 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6294 if (ainfo->size == 8)
6295 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6297 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6300 case RegTypeStructByVal: {
6301 int doffset = inst->inst_offset;
6305 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
6306 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6307 if (arm_is_imm12 (doffset)) {
6308 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6310 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6311 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6313 soffset += sizeof (gpointer);
6314 doffset += sizeof (gpointer);
6316 if (ainfo->vtsize) {
6317 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6318 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6319 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6323 case RegTypeStructByAddr:
6324 g_assert_not_reached ();
6325 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6326 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6328 g_assert_not_reached ();
6335 if (method->save_lmf)
6336 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6339 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6341 if (cfg->arch.seq_point_info_var) {
6342 MonoInst *ins = cfg->arch.seq_point_info_var;
6344 /* Initialize the variable from a GOT slot */
6345 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6346 #ifdef USE_JUMP_TABLES
6348 gpointer *jte = mono_jumptable_add_entry ();
6349 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6350 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6352 /** XXX: is it correct? */
6354 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6356 *(gpointer*)code = NULL;
6359 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6361 g_assert (ins->opcode == OP_REGOFFSET);
6363 if (arm_is_imm12 (ins->inst_offset)) {
6364 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6366 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6367 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6371 /* Initialize ss_trigger_page_var */
6372 if (!cfg->soft_breakpoints) {
6373 MonoInst *info_var = cfg->arch.seq_point_info_var;
6374 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6375 int dreg = ARMREG_LR;
6378 g_assert (info_var->opcode == OP_REGOFFSET);
6379 g_assert (arm_is_imm12 (info_var->inst_offset));
6381 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6382 /* Load the trigger page addr */
6383 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6384 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6388 if (cfg->arch.seq_point_read_var) {
6389 MonoInst *read_ins = cfg->arch.seq_point_read_var;
6390 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6391 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6392 #ifdef USE_JUMP_TABLES
6395 g_assert (read_ins->opcode == OP_REGOFFSET);
6396 g_assert (arm_is_imm12 (read_ins->inst_offset));
6397 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6398 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6399 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6400 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6402 #ifdef USE_JUMP_TABLES
6403 jte = mono_jumptable_add_entries (3);
6404 jte [0] = (gpointer)&ss_trigger_var;
6405 jte [1] = single_step_tramp;
6406 jte [2] = breakpoint_tramp;
6407 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6409 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6411 *(volatile int **)code = &ss_trigger_var;
6413 *(gpointer*)code = single_step_tramp;
6415 *(gpointer*)code = breakpoint_tramp;
6419 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6420 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
6421 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6422 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6423 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
6424 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6427 cfg->code_len = code - cfg->native_code;
6428 g_assert (cfg->code_len < cfg->code_size);
6435 mono_arch_emit_epilog (MonoCompile *cfg)
6437 MonoMethod *method = cfg->method;
6438 int pos, i, rot_amount;
6439 int max_epilog_size = 16 + 20*4;
6443 if (cfg->method->save_lmf)
6444 max_epilog_size += 128;
6446 if (mono_jit_trace_calls != NULL)
6447 max_epilog_size += 50;
6449 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6450 max_epilog_size += 50;
6452 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6453 cfg->code_size *= 2;
6454 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6455 cfg->stat_code_reallocs++;
6459 * Keep in sync with OP_JMP
6461 code = cfg->native_code + cfg->code_len;
6463 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6464 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6468 /* Load returned vtypes into registers if needed */
6469 cinfo = cfg->arch.cinfo;
6470 switch (cinfo->ret.storage) {
6471 case RegTypeStructByVal: {
6472 MonoInst *ins = cfg->ret;
6474 if (arm_is_imm12 (ins->inst_offset)) {
6475 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6477 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6478 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6483 MonoInst *ins = cfg->ret;
6485 for (i = 0; i < cinfo->ret.nregs; ++i) {
6486 if (cinfo->ret.esize == 4)
6487 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6489 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6497 if (method->save_lmf) {
6498 int lmf_offset, reg, sp_adj, regmask;
6499 /* all but r0-r3, sp and pc */
6500 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6503 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6505 /* This points to r4 inside MonoLMF->iregs */
6506 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6508 regmask = 0x9ff0; /* restore lr to pc */
6509 /* Skip caller saved registers not used by the method */
6510 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6511 regmask &= ~(1 << reg);
6516 /* Restored later */
6517 regmask &= ~(1 << ARMREG_PC);
6518 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6519 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6521 ARM_POP (code, regmask);
6523 /* Restore saved r7, restore LR to PC */
6524 /* Skip lr from the lmf */
6525 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6526 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6529 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6530 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6532 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6533 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6537 /* Restore saved gregs */
6538 if (cfg->used_int_regs)
6539 ARM_POP (code, cfg->used_int_regs);
6540 /* Restore saved r7, restore LR to PC */
6541 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6543 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6547 cfg->code_len = code - cfg->native_code;
6549 g_assert (cfg->code_len < cfg->code_size);
6554 mono_arch_emit_exceptions (MonoCompile *cfg)
6556 MonoJumpInfo *patch_info;
6559 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6560 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6561 int max_epilog_size = 50;
6563 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6564 exc_throw_pos [i] = NULL;
6565 exc_throw_found [i] = 0;
6568 /* count the number of exception infos */
6571 * make sure we have enough space for exceptions
6573 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6574 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6575 i = mini_exception_id_by_name (patch_info->data.target);
6576 if (!exc_throw_found [i]) {
6577 max_epilog_size += 32;
6578 exc_throw_found [i] = TRUE;
6583 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6584 cfg->code_size *= 2;
6585 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6586 cfg->stat_code_reallocs++;
6589 code = cfg->native_code + cfg->code_len;
6591 /* add code to raise exceptions */
6592 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6593 switch (patch_info->type) {
6594 case MONO_PATCH_INFO_EXC: {
6595 MonoClass *exc_class;
6596 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6598 i = mini_exception_id_by_name (patch_info->data.target);
6599 if (exc_throw_pos [i]) {
6600 arm_patch (ip, exc_throw_pos [i]);
6601 patch_info->type = MONO_PATCH_INFO_NONE;
6604 exc_throw_pos [i] = code;
6606 arm_patch (ip, code);
6608 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6609 g_assert (exc_class);
6611 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6612 #ifdef USE_JUMP_TABLES
6614 gpointer *jte = mono_jumptable_add_entries (2);
6615 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6616 patch_info->data.name = "mono_arch_throw_corlib_exception";
6617 patch_info->ip.i = code - cfg->native_code;
6618 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6619 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6620 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6621 ARM_BLX_REG (code, ARMREG_IP);
6622 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6625 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6626 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6627 patch_info->data.name = "mono_arch_throw_corlib_exception";
6628 patch_info->ip.i = code - cfg->native_code;
6630 cfg->thunk_area += THUNK_SIZE;
6631 *(guint32*)(gpointer)code = exc_class->type_token;
6642 cfg->code_len = code - cfg->native_code;
6644 g_assert (cfg->code_len < cfg->code_size);
6648 #endif /* #ifndef DISABLE_JIT */
6651 mono_arch_finish_init (void)
6656 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6661 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6668 mono_arch_print_tree (MonoInst *tree, int arity)
6678 mono_arch_get_patch_offset (guint8 *code)
6685 mono_arch_flush_register_windows (void)
6690 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6692 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6696 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6698 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6701 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6702 #define BASE_SIZE (6 * 4)
6703 #define BSEARCH_ENTRY_SIZE (4 * 4)
6704 #define CMP_SIZE (3 * 4)
6705 #define BRANCH_SIZE (1 * 4)
6706 #define CALL_SIZE (2 * 4)
6707 #define WMC_SIZE (8 * 4)
6708 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6710 #ifdef USE_JUMP_TABLES
6712 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6714 g_assert (base [index] == NULL);
6715 base [index] = value;
6718 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6720 if (arm_is_imm12 (jti * 4)) {
6721 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6723 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6724 if ((jti * 4) >> 16)
6725 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6726 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6732 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6734 guint32 delta = DISTANCE (target, code);
6736 g_assert (delta >= 0 && delta <= 0xFFF);
6737 *target = *target | delta;
6743 #ifdef ENABLE_WRONG_METHOD_CHECK
6745 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6747 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6753 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6754 gpointer fail_tramp)
6757 arminstr_t *code, *start;
6758 #ifdef USE_JUMP_TABLES
6761 gboolean large_offsets = FALSE;
6762 guint32 **constant_pool_starts;
6763 arminstr_t *vtable_target = NULL;
6764 int extra_space = 0;
6766 #ifdef ENABLE_WRONG_METHOD_CHECK
6771 #ifdef USE_JUMP_TABLES
6772 for (i = 0; i < count; ++i) {
6773 MonoIMTCheckItem *item = imt_entries [i];
6774 item->chunk_size += 4 * 16;
6775 if (!item->is_equals)
6776 imt_entries [item->check_target_idx]->compare_done = TRUE;
6777 size += item->chunk_size;
6780 constant_pool_starts = g_new0 (guint32*, count);
6782 for (i = 0; i < count; ++i) {
6783 MonoIMTCheckItem *item = imt_entries [i];
6784 if (item->is_equals) {
6785 gboolean fail_case = !item->check_target_idx && fail_tramp;
6787 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6788 item->chunk_size += 32;
6789 large_offsets = TRUE;
6792 if (item->check_target_idx || fail_case) {
6793 if (!item->compare_done || fail_case)
6794 item->chunk_size += CMP_SIZE;
6795 item->chunk_size += BRANCH_SIZE;
6797 #ifdef ENABLE_WRONG_METHOD_CHECK
6798 item->chunk_size += WMC_SIZE;
6802 item->chunk_size += 16;
6803 large_offsets = TRUE;
6805 item->chunk_size += CALL_SIZE;
6807 item->chunk_size += BSEARCH_ENTRY_SIZE;
6808 imt_entries [item->check_target_idx]->compare_done = TRUE;
6810 size += item->chunk_size;
6814 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6818 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6820 code = mono_domain_code_reserve (domain, size);
6824 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6825 for (i = 0; i < count; ++i) {
6826 MonoIMTCheckItem *item = imt_entries [i];
6827 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6831 #ifdef USE_JUMP_TABLES
6832 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6833 #define VTABLE_JTI 0
6834 #define IMT_METHOD_OFFSET 0
6835 #define TARGET_CODE_OFFSET 1
6836 #define JUMP_CODE_OFFSET 2
6837 #define RECORDS_PER_ENTRY 3
6838 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
6839 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
6840 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
6842 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
6843 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
6844 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
6845 set_jumptable_element (jte, VTABLE_JTI, vtable);
6848 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6850 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6851 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6852 vtable_target = code;
6853 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6855 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6857 for (i = 0; i < count; ++i) {
6858 MonoIMTCheckItem *item = imt_entries [i];
6859 #ifdef USE_JUMP_TABLES
6860 guint32 imt_method_jti = 0, target_code_jti = 0;
6862 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6864 gint32 vtable_offset;
6866 item->code_target = (guint8*)code;
6868 if (item->is_equals) {
6869 gboolean fail_case = !item->check_target_idx && fail_tramp;
6871 if (item->check_target_idx || fail_case) {
6872 if (!item->compare_done || fail_case) {
6873 #ifdef USE_JUMP_TABLES
6874 imt_method_jti = IMT_METHOD_JTI (i);
6875 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
6878 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6880 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6882 #ifdef USE_JUMP_TABLES
6883 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
6884 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
6885 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
6887 item->jmp_code = (guint8*)code;
6888 ARM_B_COND (code, ARMCOND_NE, 0);
6891 /*Enable the commented code to assert on wrong method*/
6892 #ifdef ENABLE_WRONG_METHOD_CHECK
6893 #ifdef USE_JUMP_TABLES
6894 imt_method_jti = IMT_METHOD_JTI (i);
6895 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
6898 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6900 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6902 ARM_B_COND (code, ARMCOND_EQ, 0);
6904 /* Define this if your system is so bad that gdb is failing. */
6905 #ifdef BROKEN_DEV_ENV
6906 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6908 arm_patch (code - 1, mini_dump_bad_imt);
6912 arm_patch (cond, code);
6916 if (item->has_target_code) {
6917 /* Load target address */
6918 #ifdef USE_JUMP_TABLES
6919 target_code_jti = TARGET_CODE_JTI (i);
6920 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
6921 /* Restore registers */
6922 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6924 ARM_BX (code, ARMREG_R1);
6925 set_jumptable_element (jte, target_code_jti, item->value.target_code);
6927 target_code_ins = code;
6928 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6929 /* Save it to the fourth slot */
6930 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6931 /* Restore registers and branch */
6932 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6934 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
6937 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
6938 if (!arm_is_imm12 (vtable_offset)) {
6940 * We need to branch to a computed address but we don't have
6941 * a free register to store it, since IP must contain the
6942 * vtable address. So we push the two values to the stack, and
6943 * load them both using LDM.
6945 /* Compute target address */
6946 #ifdef USE_JUMP_TABLES
6947 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
6948 if (vtable_offset >> 16)
6949 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
6950 /* IP had vtable base. */
6951 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
6952 /* Restore registers and branch */
6953 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6954 ARM_BX (code, ARMREG_IP);
6956 vtable_offset_ins = code;
6957 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6958 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
6959 /* Save it to the fourth slot */
6960 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6961 /* Restore registers and branch */
6962 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6964 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
6967 #ifdef USE_JUMP_TABLES
6968 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
6969 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6970 ARM_BX (code, ARMREG_IP);
6972 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
6974 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
6975 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
6981 #ifdef USE_JUMP_TABLES
6982 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
6983 target_code_jti = TARGET_CODE_JTI (i);
6984 /* Load target address */
6985 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
6986 /* Restore registers */
6987 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
6989 ARM_BX (code, ARMREG_R1);
6990 set_jumptable_element (jte, target_code_jti, fail_tramp);
6992 arm_patch (item->jmp_code, (guchar*)code);
6994 target_code_ins = code;
6995 /* Load target address */
6996 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6997 /* Save it to the fourth slot */
6998 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6999 /* Restore registers and branch */
7000 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7002 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7004 item->jmp_code = NULL;
7007 #ifdef USE_JUMP_TABLES
7009 set_jumptable_element (jte, imt_method_jti, item->key);
7012 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7014 /*must emit after unconditional branch*/
7015 if (vtable_target) {
7016 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7017 item->chunk_size += 4;
7018 vtable_target = NULL;
7021 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7022 constant_pool_starts [i] = code;
7024 code += extra_space;
7029 #ifdef USE_JUMP_TABLES
7030 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7031 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7032 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7033 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7034 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7036 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7037 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7039 item->jmp_code = (guint8*)code;
7040 ARM_B_COND (code, ARMCOND_HS, 0);
7046 for (i = 0; i < count; ++i) {
7047 MonoIMTCheckItem *item = imt_entries [i];
7048 if (item->jmp_code) {
7049 if (item->check_target_idx)
7050 #ifdef USE_JUMP_TABLES
7051 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7053 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7056 if (i > 0 && item->is_equals) {
7058 #ifdef USE_JUMP_TABLES
7059 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7060 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7062 arminstr_t *space_start = constant_pool_starts [i];
7063 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7064 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7072 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7073 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7078 #ifndef USE_JUMP_TABLES
7079 g_free (constant_pool_starts);
7082 mono_arch_flush_icache ((guint8*)start, size);
7083 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7084 mono_stats.imt_thunks_size += code - start;
7086 g_assert (DISTANCE (start, code) <= size);
7091 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7093 return ctx->regs [reg];
7097 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7099 ctx->regs [reg] = val;
7103 * mono_arch_get_trampolines:
7105 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7109 mono_arch_get_trampolines (gboolean aot)
7111 return mono_arm_get_exception_trampolines (aot);
7115 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7122 bp = MONO_CONTEXT_GET_BP (ctx);
7123 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7125 old_value = *lr_loc;
7126 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7129 *lr_loc = new_value;
7134 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7136 * mono_arch_set_breakpoint:
7138 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7139 * The location should contain code emitted by OP_SEQ_POINT.
7142 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7145 guint32 native_offset = ip - (guint8*)ji->code_start;
7146 MonoDebugOptions *opt = mini_get_debug_options ();
7148 if (opt->soft_breakpoints) {
7149 g_assert (!ji->from_aot);
7151 ARM_BLX_REG (code, ARMREG_LR);
7152 mono_arch_flush_icache (code - 4, 4);
7153 } else if (ji->from_aot) {
7154 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7156 g_assert (native_offset % 4 == 0);
7157 g_assert (info->bp_addrs [native_offset / 4] == 0);
7158 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7160 int dreg = ARMREG_LR;
7162 /* Read from another trigger page */
7163 #ifdef USE_JUMP_TABLES
7164 gpointer *jte = mono_jumptable_add_entry ();
7165 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7166 jte [0] = bp_trigger_page;
7168 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7170 *(int*)code = (int)bp_trigger_page;
7173 ARM_LDR_IMM (code, dreg, dreg, 0);
7175 mono_arch_flush_icache (code - 16, 16);
7178 /* This is currently implemented by emitting an SWI instruction, which
7179 * qemu/linux seems to convert to a SIGILL.
7181 *(int*)code = (0xef << 24) | 8;
7183 mono_arch_flush_icache (code - 4, 4);
7189 * mono_arch_clear_breakpoint:
7191 * Clear the breakpoint at IP.
7194 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7196 MonoDebugOptions *opt = mini_get_debug_options ();
7200 if (opt->soft_breakpoints) {
7201 g_assert (!ji->from_aot);
7204 mono_arch_flush_icache (code - 4, 4);
7205 } else if (ji->from_aot) {
7206 guint32 native_offset = ip - (guint8*)ji->code_start;
7207 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7209 g_assert (native_offset % 4 == 0);
7210 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7211 info->bp_addrs [native_offset / 4] = 0;
7213 for (i = 0; i < 4; ++i)
7216 mono_arch_flush_icache (ip, code - ip);
7221 * mono_arch_start_single_stepping:
7223 * Start single stepping.
7226 mono_arch_start_single_stepping (void)
7228 if (ss_trigger_page)
7229 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7235 * mono_arch_stop_single_stepping:
7237 * Stop single stepping.
7240 mono_arch_stop_single_stepping (void)
7242 if (ss_trigger_page)
7243 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7249 #define DBG_SIGNAL SIGBUS
7251 #define DBG_SIGNAL SIGSEGV
7255 * mono_arch_is_single_step_event:
7257 * Return whenever the machine state in SIGCTX corresponds to a single
7261 mono_arch_is_single_step_event (void *info, void *sigctx)
7263 siginfo_t *sinfo = info;
7265 if (!ss_trigger_page)
7268 /* Sometimes the address is off by 4 */
7269 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7276 * mono_arch_is_breakpoint_event:
7278 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7281 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7283 siginfo_t *sinfo = info;
7285 if (!ss_trigger_page)
7288 if (sinfo->si_signo == DBG_SIGNAL) {
7289 /* Sometimes the address is off by 4 */
7290 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7300 * mono_arch_skip_breakpoint:
7302 * See mini-amd64.c for docs.
7305 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7307 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7311 * mono_arch_skip_single_step:
7313 * See mini-amd64.c for docs.
7316 mono_arch_skip_single_step (MonoContext *ctx)
7318 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7321 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7324 * mono_arch_get_seq_point_info:
7326 * See mini-amd64.c for docs.
7329 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7334 // FIXME: Add a free function
7336 mono_domain_lock (domain);
7337 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7339 mono_domain_unlock (domain);
7342 ji = mono_jit_info_table_find (domain, (char*)code);
7345 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7347 info->ss_trigger_page = ss_trigger_page;
7348 info->bp_trigger_page = bp_trigger_page;
7350 mono_domain_lock (domain);
7351 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7353 mono_domain_unlock (domain);
7360 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7362 ext->lmf.previous_lmf = prev_lmf;
7363 /* Mark that this is a MonoLMFExt */
7364 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7365 ext->lmf.sp = (gssize)ext;
7369 * mono_arch_set_target:
7371 * Set the target architecture the JIT backend should generate code for, in the form
7372 * of a GNU target triplet. Only used in AOT mode.
7375 mono_arch_set_target (char *mtriple)
7377 /* The GNU target triple format is not very well documented */
7378 if (strstr (mtriple, "armv7")) {
7379 v5_supported = TRUE;
7380 v6_supported = TRUE;
7381 v7_supported = TRUE;
7383 if (strstr (mtriple, "armv6")) {
7384 v5_supported = TRUE;
7385 v6_supported = TRUE;
7387 if (strstr (mtriple, "armv7s")) {
7388 v7s_supported = TRUE;
7390 if (strstr (mtriple, "thumbv7s")) {
7391 v5_supported = TRUE;
7392 v6_supported = TRUE;
7393 v7_supported = TRUE;
7394 v7s_supported = TRUE;
7395 thumb_supported = TRUE;
7396 thumb2_supported = TRUE;
7398 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7399 v5_supported = TRUE;
7400 v6_supported = TRUE;
7401 thumb_supported = TRUE;
7404 if (strstr (mtriple, "gnueabi"))
7405 eabi_supported = TRUE;
7409 mono_arch_opcode_supported (int opcode)
7412 case OP_ATOMIC_ADD_I4:
7413 case OP_ATOMIC_EXCHANGE_I4:
7414 case OP_ATOMIC_CAS_I4:
7415 case OP_ATOMIC_LOAD_I1:
7416 case OP_ATOMIC_LOAD_I2:
7417 case OP_ATOMIC_LOAD_I4:
7418 case OP_ATOMIC_LOAD_U1:
7419 case OP_ATOMIC_LOAD_U2:
7420 case OP_ATOMIC_LOAD_U4:
7421 case OP_ATOMIC_STORE_I1:
7422 case OP_ATOMIC_STORE_I2:
7423 case OP_ATOMIC_STORE_I4:
7424 case OP_ATOMIC_STORE_U1:
7425 case OP_ATOMIC_STORE_U2:
7426 case OP_ATOMIC_STORE_U4:
7427 return v7_supported;
7428 case OP_ATOMIC_LOAD_R4:
7429 case OP_ATOMIC_LOAD_R8:
7430 case OP_ATOMIC_STORE_R4:
7431 case OP_ATOMIC_STORE_R8:
7432 return v7_supported && IS_VFP;
7438 #if defined(ENABLE_GSHAREDVT)
7440 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7442 #endif /* !MONOTOUCH */