2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
13 #include <mono/metadata/appdomain.h>
14 #include <mono/metadata/debug-helpers.h>
15 #include <mono/utils/mono-mmap.h>
21 #include "debugger-agent.h"
23 #include "mono/arch/arm/arm-fpa-codegen.h"
24 #elif defined(ARM_FPU_VFP)
25 #include "mono/arch/arm/arm-vfp-codegen.h"
28 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
29 #define HAVE_AEABI_READ_TP 1
32 static gint lmf_tls_offset = -1;
33 static gint lmf_addr_tls_offset = -1;
35 /* This mutex protects architecture specific caches */
36 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
37 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
38 static CRITICAL_SECTION mini_arch_mutex;
40 static int v5_supported = 0;
41 static int v6_supported = 0;
42 static int v7_supported = 0;
43 static int thumb_supported = 0;
45 * Whenever to use the ARM EABI
47 static int eabi_supported = 0;
50 * Whenever we are on arm/darwin aka the iphone.
52 static int darwin = 0;
54 * Whenever to use the iphone ABI extensions:
55 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
56 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
57 * This is required for debugging/profiling tools to work, but it has some overhead so it should
58 * only be turned on in debug builds.
60 static int iphone_abi = 0;
63 static volatile int ss_trigger_var = 0;
65 static gpointer single_step_func_wrapper;
66 static gpointer breakpoint_func_wrapper;
70 * The code generated for sequence points reads from this location, which is
71 * made read-only when single stepping is enabled.
73 static gpointer ss_trigger_page;
75 /* Enabled breakpoints read from this trigger page */
76 static gpointer bp_trigger_page;
78 /* Structure used by the sequence points in AOTed code */
80 gpointer ss_trigger_page;
81 gpointer bp_trigger_page;
82 guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
87 * floating point support: on ARM it is a mess, there are at least 3
88 * different setups, each of which binary incompat with the other.
89 * 1) FPA: old and ugly, but unfortunately what current distros use
90 * the double binary format has the two words swapped. 8 double registers.
91 * Implemented usually by kernel emulation.
92 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
93 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
94 * 3) VFP: the new and actually sensible and useful FP support. Implemented
95 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
97 * The plan is to write the FPA support first. softfloat can be tested in a chroot.
99 int mono_exc_esp_offset = 0;
101 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
102 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
103 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
105 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
106 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
107 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
109 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
110 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) | (ARMREG_LR << 12) | ARMREG_PC)
113 /* A variant of ARM_LDR_IMM which can handle large offsets */
114 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
115 if (arm_is_imm12 ((offset))) { \
116 ARM_LDR_IMM (code, (dreg), (basereg), (offset)); \
118 g_assert ((scratch_reg) != (basereg)); \
119 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
120 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
124 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
125 if (arm_is_imm12 ((offset))) { \
126 ARM_STR_IMM (code, (dreg), (basereg), (offset)); \
128 g_assert ((scratch_reg) != (basereg)); \
129 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
130 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
134 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
137 mono_arch_regname (int reg)
139 static const char * rnames[] = {
140 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
141 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
142 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
145 if (reg >= 0 && reg < 16)
151 mono_arch_fregname (int reg)
153 static const char * rnames[] = {
154 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
155 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
156 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
157 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
158 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
159 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
162 if (reg >= 0 && reg < 32)
170 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
172 int imm8, rot_amount;
173 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
174 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
177 g_assert (dreg != sreg);
178 code = mono_arm_emit_load_imm (code, dreg, imm);
179 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
184 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
186 /* we can use r0-r3, since this is called only for incoming args on the stack */
187 if (size > sizeof (gpointer) * 4) {
189 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
190 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
191 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
192 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
193 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
194 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
195 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
196 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
197 ARM_B_COND (code, ARMCOND_NE, 0);
198 arm_patch (code - 4, start_loop);
201 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
202 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
204 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
205 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
211 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
212 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
213 doffset = soffset = 0;
215 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
216 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
222 g_assert (size == 0);
227 emit_call_reg (guint8 *code, int reg)
230 ARM_BLX_REG (code, reg);
232 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
236 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
242 emit_call_seq (MonoCompile *cfg, guint8 *code)
244 if (cfg->method->dynamic) {
245 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
247 *(gpointer*)code = NULL;
249 code = emit_call_reg (code, ARMREG_IP);
257 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
259 switch (ins->opcode) {
262 case OP_FCALL_MEMBASE:
264 if (ins->dreg != ARM_FPA_F0)
265 ARM_MVFD (code, ins->dreg, ARM_FPA_F0);
266 #elif defined(ARM_FPU_VFP)
267 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
268 ARM_FMSR (code, ins->dreg, ARMREG_R0);
269 ARM_CVTS (code, ins->dreg, ins->dreg);
271 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
283 * Emit code to push an LMF structure on the LMF stack.
284 * On arm, this is intermixed with the initialization of other fields of the structure.
287 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
289 gboolean get_lmf_fast = FALSE;
291 #ifdef HAVE_AEABI_READ_TP
292 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
294 if (lmf_addr_tls_offset != -1) {
297 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
298 (gpointer)"__aeabi_read_tp");
299 code = emit_call_seq (cfg, code);
301 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
306 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
307 (gpointer)"mono_get_lmf_addr");
308 code = emit_call_seq (cfg, code);
310 /* we build the MonoLMF structure on the stack - see mini-arm.h */
311 /* lmf_offset is the offset from the previous stack pointer,
312 * alloc_size is the total stack space allocated, so the offset
313 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
314 * The pointer to the struct is put in r1 (new_lmf).
315 * ip is used as scratch
316 * The callee-saved registers are already in the MonoLMF structure
318 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
319 /* r0 is the result from mono_get_lmf_addr () */
320 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
321 /* new_lmf->previous_lmf = *lmf_addr */
322 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
323 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
324 /* *(lmf_addr) = r1 */
325 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
326 /* Skip method (only needed for trampoline LMF frames) */
327 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, esp));
328 /* save the current IP */
329 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
330 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, eip));
338 * Emit code to pop an LMF structure from the LMF stack.
341 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
345 if (lmf_offset < 32) {
346 basereg = cfg->frame_reg;
351 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
354 /* ip = previous_lmf */
355 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
357 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
358 /* *(lmf_addr) = previous_lmf */
359 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
364 #endif /* #ifndef DISABLE_JIT */
367 * mono_arch_get_argument_info:
368 * @csig: a method signature
369 * @param_count: the number of parameters to consider
370 * @arg_info: an array to store the result infos
372 * Gathers information on parameters such as size, alignment and
373 * padding. arg_info should be large enought to hold param_count + 1 entries.
375 * Returns the size of the activation frame.
378 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
380 int k, frame_size = 0;
381 guint32 size, align, pad;
384 if (MONO_TYPE_ISSTRUCT (csig->ret)) {
385 frame_size += sizeof (gpointer);
389 arg_info [0].offset = offset;
392 frame_size += sizeof (gpointer);
396 arg_info [0].size = frame_size;
398 for (k = 0; k < param_count; k++) {
399 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
401 /* ignore alignment for now */
404 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
405 arg_info [k].pad = pad;
407 arg_info [k + 1].pad = 0;
408 arg_info [k + 1].size = size;
410 arg_info [k + 1].offset = offset;
414 align = MONO_ARCH_FRAME_ALIGNMENT;
415 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
416 arg_info [k].pad = pad;
421 #define MAX_ARCH_DELEGATE_PARAMS 3
424 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
426 guint8 *code, *start;
429 start = code = mono_global_codeman_reserve (12);
431 /* Replace the this argument with the target */
432 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
433 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
434 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
436 g_assert ((code - start) <= 12);
438 mono_arch_flush_icache (start, 12);
442 size = 8 + param_count * 4;
443 start = code = mono_global_codeman_reserve (size);
445 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
446 /* slide down the arguments */
447 for (i = 0; i < param_count; ++i) {
448 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
450 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
452 g_assert ((code - start) <= size);
454 mono_arch_flush_icache (start, size);
458 *code_size = code - start;
464 * mono_arch_get_delegate_invoke_impls:
466 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
470 mono_arch_get_delegate_invoke_impls (void)
477 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
478 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
480 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
481 code = get_delegate_invoke_impl (FALSE, i, &code_len);
482 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
489 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
491 guint8 *code, *start;
493 /* FIXME: Support more cases */
494 if (MONO_TYPE_ISSTRUCT (sig->ret))
498 static guint8* cached = NULL;
499 mono_mini_arch_lock ();
501 mono_mini_arch_unlock ();
506 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
508 start = get_delegate_invoke_impl (TRUE, 0, NULL);
510 mono_mini_arch_unlock ();
513 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
516 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
518 for (i = 0; i < sig->param_count; ++i)
519 if (!mono_is_regsize_var (sig->params [i]))
522 mono_mini_arch_lock ();
523 code = cache [sig->param_count];
525 mono_mini_arch_unlock ();
530 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
531 start = mono_aot_get_trampoline (name);
534 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
536 cache [sig->param_count] = start;
537 mono_mini_arch_unlock ();
545 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
547 return (gpointer)regs [ARMREG_R0];
551 * Initialize the cpu to execute managed code.
554 mono_arch_cpu_init (void)
556 #if defined(__ARM_EABI__)
557 eabi_supported = TRUE;
559 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
562 i8_align = __alignof__ (gint64);
567 create_function_wrapper (gpointer function)
569 guint8 *start, *code;
571 start = code = mono_global_codeman_reserve (96);
574 * Construct the MonoContext structure on the stack.
577 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, sizeof (MonoContext));
579 /* save ip, lr and pc into their correspodings ctx.regs slots. */
580 ARM_STR_IMM (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_IP);
581 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
582 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
584 /* save r0..r10 and fp */
585 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs));
586 ARM_STM (code, ARMREG_IP, 0x0fff);
588 /* now we can update fp. */
589 ARM_MOV_REG_REG (code, ARMREG_FP, ARMREG_SP);
591 /* make ctx.esp hold the actual value of sp at the beginning of this method. */
592 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_FP, sizeof (MonoContext));
593 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, 4 * ARMREG_SP);
594 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, esp));
596 /* make ctx.eip hold the address of the call. */
597 ARM_SUB_REG_IMM8 (code, ARMREG_LR, ARMREG_LR, 4);
598 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, eip));
600 /* r0 now points to the MonoContext */
601 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_FP);
604 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
606 *(gpointer*)code = function;
608 ARM_BLX_REG (code, ARMREG_IP);
610 /* we're back; save ctx.eip and ctx.esp into the corresponding regs slots. */
611 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, eip));
612 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
613 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
614 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, esp));
615 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_SP);
617 /* make ip point to the regs array, then restore everything, including pc. */
618 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs));
619 ARM_LDM (code, ARMREG_IP, 0xffff);
621 mono_arch_flush_icache (start, code - start);
627 * Initialize architecture specific code.
630 mono_arch_init (void)
632 InitializeCriticalSection (&mini_arch_mutex);
634 if (mini_get_debug_options ()->soft_breakpoints) {
635 single_step_func_wrapper = create_function_wrapper (debugger_agent_single_step_from_context);
636 breakpoint_func_wrapper = create_function_wrapper (debugger_agent_breakpoint_from_context);
638 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
639 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
640 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
643 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
644 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
645 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
649 * Cleanup architecture specific code.
652 mono_arch_cleanup (void)
657 * This function returns the optimizations supported on this cpu.
660 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
663 const char *cpu_arch = getenv ("MONO_CPU_ARCH");
664 if (cpu_arch != NULL) {
665 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
666 if (strncmp (cpu_arch, "armv", 4) == 0) {
667 v5_supported = cpu_arch [4] >= '5';
668 v6_supported = cpu_arch [4] >= '6';
669 v7_supported = cpu_arch [4] >= '7';
673 thumb_supported = TRUE;
680 FILE *file = fopen ("/proc/cpuinfo", "r");
682 while ((line = fgets (buf, 512, file))) {
683 if (strncmp (line, "Processor", 9) == 0) {
684 char *ver = strstr (line, "(v");
685 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
687 if (ver && (ver [2] == '6' || ver [2] == '7'))
689 if (ver && (ver [2] == '7'))
693 if (strncmp (line, "Features", 8) == 0) {
694 char *th = strstr (line, "thumb");
696 thumb_supported = TRUE;
704 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
709 /* no arm-specific optimizations yet */
717 is_regsize_var (MonoType *t) {
720 t = mini_type_get_underlying_type (NULL, t);
727 case MONO_TYPE_FNPTR:
729 case MONO_TYPE_OBJECT:
730 case MONO_TYPE_STRING:
731 case MONO_TYPE_CLASS:
732 case MONO_TYPE_SZARRAY:
733 case MONO_TYPE_ARRAY:
735 case MONO_TYPE_GENERICINST:
736 if (!mono_type_generic_inst_is_valuetype (t))
739 case MONO_TYPE_VALUETYPE:
746 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
751 for (i = 0; i < cfg->num_varinfo; i++) {
752 MonoInst *ins = cfg->varinfo [i];
753 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
756 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
759 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
762 /* we can only allocate 32 bit values */
763 if (is_regsize_var (ins->inst_vtype)) {
764 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
765 g_assert (i == vmv->idx);
766 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
773 #define USE_EXTRA_TEMPS 0
776 mono_arch_get_global_int_regs (MonoCompile *cfg)
780 mono_arch_compute_omit_fp (cfg);
783 * FIXME: Interface calls might go through a static rgctx trampoline which
784 * sets V5, but it doesn't save it, so we need to save it ourselves, and
787 if (cfg->flags & MONO_CFG_HAS_CALLS)
788 cfg->uses_rgctx_reg = TRUE;
790 if (cfg->arch.omit_fp)
791 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
792 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
793 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
794 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
796 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
797 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
799 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
800 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
801 /* V5 is reserved for passing the vtable/rgctx/IMT method */
802 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
803 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
804 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
810 * mono_arch_regalloc_cost:
812 * Return the cost, in number of memory references, of the action of
813 * allocating the variable VMV into a register during global register
817 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
823 #endif /* #ifndef DISABLE_JIT */
825 #ifndef __GNUC_PREREQ
826 #define __GNUC_PREREQ(maj, min) (0)
830 mono_arch_flush_icache (guint8 *code, gint size)
833 sys_icache_invalidate (code, size);
834 #elif __GNUC_PREREQ(4, 1)
835 __clear_cache (code, code + size);
836 #elif defined(PLATFORM_ANDROID)
837 const int syscall = 0xf0002;
845 : "r" (code), "r" (code + size), "r" (syscall)
846 : "r0", "r1", "r7", "r2"
849 __asm __volatile ("mov r0, %0\n"
852 "swi 0x9f0002 @ sys_cacheflush"
854 : "r" (code), "r" (code + size), "r" (0)
855 : "r0", "r1", "r3" );
872 guint16 vtsize; /* in param area */
876 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
882 gboolean vtype_retaddr;
883 /* The index of the vret arg in the argument list */
893 /*#define __alignof__(a) sizeof(a)*/
894 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
900 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
903 if (*gr > ARMREG_R3) {
904 ainfo->offset = *stack_size;
905 ainfo->reg = ARMREG_SP; /* in the caller */
906 ainfo->storage = RegTypeBase;
909 ainfo->storage = RegTypeGeneral;
916 split = i8_align == 4;
920 if (*gr == ARMREG_R3 && split) {
921 /* first word in r3 and the second on the stack */
922 ainfo->offset = *stack_size;
923 ainfo->reg = ARMREG_SP; /* in the caller */
924 ainfo->storage = RegTypeBaseGen;
926 } else if (*gr >= ARMREG_R3) {
927 if (eabi_supported) {
928 /* darwin aligns longs to 4 byte only */
934 ainfo->offset = *stack_size;
935 ainfo->reg = ARMREG_SP; /* in the caller */
936 ainfo->storage = RegTypeBase;
939 if (eabi_supported) {
940 if (i8_align == 8 && ((*gr) & 1))
943 ainfo->storage = RegTypeIRegPair;
952 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
955 int n = sig->hasthis + sig->param_count;
956 MonoType *simpletype;
957 guint32 stack_size = 0;
959 gboolean is_pinvoke = sig->pinvoke;
962 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
964 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
969 /* FIXME: handle returning a struct */
970 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
973 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (sig->ret), &align) <= sizeof (gpointer)) {
974 cinfo->ret.storage = RegTypeStructByVal;
976 cinfo->vtype_retaddr = TRUE;
983 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
984 * the first argument, allowing 'this' to be always passed in the first arg reg.
985 * Also do this if the first argument is a reference type, since virtual calls
986 * are sometimes made using calli without sig->hasthis set, like in the delegate
989 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
991 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
993 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
997 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
998 cinfo->vret_arg_index = 1;
1002 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1006 if (cinfo->vtype_retaddr)
1007 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1010 DEBUG(printf("params: %d\n", sig->param_count));
1011 for (i = pstart; i < sig->param_count; ++i) {
1012 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1013 /* Prevent implicit arguments and sig_cookie from
1014 being passed in registers */
1016 /* Emit the signature cookie just before the implicit arguments */
1017 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1019 DEBUG(printf("param %d: ", i));
1020 if (sig->params [i]->byref) {
1021 DEBUG(printf("byref\n"));
1022 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1026 simpletype = mini_type_get_underlying_type (NULL, sig->params [i]);
1027 switch (simpletype->type) {
1028 case MONO_TYPE_BOOLEAN:
1031 cinfo->args [n].size = 1;
1032 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1035 case MONO_TYPE_CHAR:
1038 cinfo->args [n].size = 2;
1039 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1044 cinfo->args [n].size = 4;
1045 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1051 case MONO_TYPE_FNPTR:
1052 case MONO_TYPE_CLASS:
1053 case MONO_TYPE_OBJECT:
1054 case MONO_TYPE_STRING:
1055 case MONO_TYPE_SZARRAY:
1056 case MONO_TYPE_ARRAY:
1058 cinfo->args [n].size = sizeof (gpointer);
1059 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1062 case MONO_TYPE_GENERICINST:
1063 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1064 cinfo->args [n].size = sizeof (gpointer);
1065 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1070 case MONO_TYPE_TYPEDBYREF:
1071 case MONO_TYPE_VALUETYPE: {
1077 if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1078 size = sizeof (MonoTypedRef);
1079 align = sizeof (gpointer);
1081 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1083 size = mono_class_native_size (klass, &align);
1085 size = mono_class_value_size (klass, &align);
1087 DEBUG(printf ("load %d bytes struct\n",
1088 mono_class_native_size (sig->params [i]->data.klass, NULL)));
1091 align_size += (sizeof (gpointer) - 1);
1092 align_size &= ~(sizeof (gpointer) - 1);
1093 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1094 cinfo->args [n].storage = RegTypeStructByVal;
1095 cinfo->args [n].struct_size = size;
1096 /* FIXME: align stack_size if needed */
1097 if (eabi_supported) {
1098 if (align >= 8 && (gr & 1))
1101 if (gr > ARMREG_R3) {
1102 cinfo->args [n].size = 0;
1103 cinfo->args [n].vtsize = nwords;
1105 int rest = ARMREG_R3 - gr + 1;
1106 int n_in_regs = rest >= nwords? nwords: rest;
1108 cinfo->args [n].size = n_in_regs;
1109 cinfo->args [n].vtsize = nwords - n_in_regs;
1110 cinfo->args [n].reg = gr;
1112 nwords -= n_in_regs;
1114 cinfo->args [n].offset = stack_size;
1115 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1116 stack_size += nwords * sizeof (gpointer);
1123 cinfo->args [n].size = 8;
1124 add_general (&gr, &stack_size, cinfo->args + n, FALSE);
1128 g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1132 /* Handle the case where there are no implicit arguments */
1133 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1134 /* Prevent implicit arguments and sig_cookie from
1135 being passed in registers */
1137 /* Emit the signature cookie just before the implicit arguments */
1138 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1142 simpletype = mini_type_get_underlying_type (NULL, sig->ret);
1143 switch (simpletype->type) {
1144 case MONO_TYPE_BOOLEAN:
1149 case MONO_TYPE_CHAR:
1155 case MONO_TYPE_FNPTR:
1156 case MONO_TYPE_CLASS:
1157 case MONO_TYPE_OBJECT:
1158 case MONO_TYPE_SZARRAY:
1159 case MONO_TYPE_ARRAY:
1160 case MONO_TYPE_STRING:
1161 cinfo->ret.storage = RegTypeGeneral;
1162 cinfo->ret.reg = ARMREG_R0;
1166 cinfo->ret.storage = RegTypeIRegPair;
1167 cinfo->ret.reg = ARMREG_R0;
1171 cinfo->ret.storage = RegTypeFP;
1172 cinfo->ret.reg = ARMREG_R0;
1173 /* FIXME: cinfo->ret.reg = ???;
1174 cinfo->ret.storage = RegTypeFP;*/
1176 case MONO_TYPE_GENERICINST:
1177 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1178 cinfo->ret.storage = RegTypeGeneral;
1179 cinfo->ret.reg = ARMREG_R0;
1183 case MONO_TYPE_VALUETYPE:
1184 case MONO_TYPE_TYPEDBYREF:
1185 if (cinfo->ret.storage != RegTypeStructByVal)
1186 cinfo->ret.storage = RegTypeStructByAddr;
1188 case MONO_TYPE_VOID:
1191 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1195 /* align stack size to 8 */
1196 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1197 stack_size = (stack_size + 7) & ~7;
1199 cinfo->stack_usage = stack_size;
1205 G_GNUC_UNUSED static void
1210 G_GNUC_UNUSED static gboolean
1213 static int count = 0;
1216 if (!getenv ("COUNT"))
1219 if (count == atoi (getenv ("COUNT"))) {
1223 if (count > atoi (getenv ("COUNT"))) {
1231 debug_omit_fp (void)
1234 return debug_count ();
1241 * mono_arch_compute_omit_fp:
1243 * Determine whenever the frame pointer can be eliminated.
1246 mono_arch_compute_omit_fp (MonoCompile *cfg)
1248 MonoMethodSignature *sig;
1249 MonoMethodHeader *header;
1253 if (cfg->arch.omit_fp_computed)
1256 header = cfg->header;
1258 sig = mono_method_signature (cfg->method);
1260 if (!cfg->arch.cinfo)
1261 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1262 cinfo = cfg->arch.cinfo;
1265 * FIXME: Remove some of the restrictions.
1267 cfg->arch.omit_fp = TRUE;
1268 cfg->arch.omit_fp_computed = TRUE;
1270 if (cfg->disable_omit_fp)
1271 cfg->arch.omit_fp = FALSE;
1272 if (!debug_omit_fp ())
1273 cfg->arch.omit_fp = FALSE;
1275 if (cfg->method->save_lmf)
1276 cfg->arch.omit_fp = FALSE;
1278 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1279 cfg->arch.omit_fp = FALSE;
1280 if (header->num_clauses)
1281 cfg->arch.omit_fp = FALSE;
1282 if (cfg->param_area)
1283 cfg->arch.omit_fp = FALSE;
1284 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1285 cfg->arch.omit_fp = FALSE;
1286 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1287 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1288 cfg->arch.omit_fp = FALSE;
1289 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1290 ArgInfo *ainfo = &cinfo->args [i];
1292 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1294 * The stack offset can only be determined when the frame
1297 cfg->arch.omit_fp = FALSE;
1302 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1303 MonoInst *ins = cfg->varinfo [i];
1306 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1311 * Set var information according to the calling convention. arm version.
1312 * The locals var stuff should most likely be split in another method.
1315 mono_arch_allocate_vars (MonoCompile *cfg)
1317 MonoMethodSignature *sig;
1318 MonoMethodHeader *header;
1320 int i, offset, size, align, curinst;
1324 sig = mono_method_signature (cfg->method);
1326 if (!cfg->arch.cinfo)
1327 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1328 cinfo = cfg->arch.cinfo;
1330 mono_arch_compute_omit_fp (cfg);
1332 if (cfg->arch.omit_fp)
1333 cfg->frame_reg = ARMREG_SP;
1335 cfg->frame_reg = ARMREG_FP;
1337 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1339 /* allow room for the vararg method args: void* and long/double */
1340 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1341 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1343 header = cfg->header;
1345 /* See mono_arch_get_global_int_regs () */
1346 if (cfg->flags & MONO_CFG_HAS_CALLS)
1347 cfg->uses_rgctx_reg = TRUE;
1349 if (cfg->frame_reg != ARMREG_SP)
1350 cfg->used_int_regs |= 1 << cfg->frame_reg;
1352 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1353 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1354 cfg->used_int_regs |= (1 << ARMREG_V5);
1358 if (!MONO_TYPE_ISSTRUCT (sig->ret)) {
1359 switch (mini_type_get_underlying_type (NULL, sig->ret)->type) {
1360 case MONO_TYPE_VOID:
1363 cfg->ret->opcode = OP_REGVAR;
1364 cfg->ret->inst_c0 = ARMREG_R0;
1368 /* local vars are at a positive offset from the stack pointer */
1370 * also note that if the function uses alloca, we use FP
1371 * to point at the local variables.
1373 offset = 0; /* linkage area */
1374 /* align the offset to 16 bytes: not sure this is needed here */
1376 //offset &= ~(8 - 1);
1378 /* add parameter area size for called functions */
1379 offset += cfg->param_area;
1382 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1385 /* allow room to save the return value */
1386 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1389 /* the MonoLMF structure is stored just below the stack pointer */
1390 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1391 if (cinfo->ret.storage == RegTypeStructByVal) {
1392 cfg->ret->opcode = OP_REGOFFSET;
1393 cfg->ret->inst_basereg = cfg->frame_reg;
1394 offset += sizeof (gpointer) - 1;
1395 offset &= ~(sizeof (gpointer) - 1);
1396 cfg->ret->inst_offset = - offset;
1398 ins = cfg->vret_addr;
1399 offset += sizeof(gpointer) - 1;
1400 offset &= ~(sizeof(gpointer) - 1);
1401 ins->inst_offset = offset;
1402 ins->opcode = OP_REGOFFSET;
1403 ins->inst_basereg = cfg->frame_reg;
1404 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1405 printf ("vret_addr =");
1406 mono_print_ins (cfg->vret_addr);
1409 offset += sizeof(gpointer);
1412 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1413 if (cfg->arch.seq_point_info_var) {
1416 ins = cfg->arch.seq_point_info_var;
1420 offset += align - 1;
1421 offset &= ~(align - 1);
1422 ins->opcode = OP_REGOFFSET;
1423 ins->inst_basereg = cfg->frame_reg;
1424 ins->inst_offset = offset;
1427 ins = cfg->arch.ss_trigger_page_var;
1430 offset += align - 1;
1431 offset &= ~(align - 1);
1432 ins->opcode = OP_REGOFFSET;
1433 ins->inst_basereg = cfg->frame_reg;
1434 ins->inst_offset = offset;
1438 if (cfg->arch.seq_point_read_var) {
1441 ins = cfg->arch.seq_point_read_var;
1445 offset += align - 1;
1446 offset &= ~(align - 1);
1447 ins->opcode = OP_REGOFFSET;
1448 ins->inst_basereg = cfg->frame_reg;
1449 ins->inst_offset = offset;
1452 ins = cfg->arch.seq_point_ss_method_var;
1455 offset += align - 1;
1456 offset &= ~(align - 1);
1457 ins->opcode = OP_REGOFFSET;
1458 ins->inst_basereg = cfg->frame_reg;
1459 ins->inst_offset = offset;
1462 ins = cfg->arch.seq_point_bp_method_var;
1465 offset += align - 1;
1466 offset &= ~(align - 1);
1467 ins->opcode = OP_REGOFFSET;
1468 ins->inst_basereg = cfg->frame_reg;
1469 ins->inst_offset = offset;
1473 curinst = cfg->locals_start;
1474 for (i = curinst; i < cfg->num_varinfo; ++i) {
1475 ins = cfg->varinfo [i];
1476 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1479 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1480 * pinvoke wrappers when they call functions returning structure */
1481 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (ins->inst_vtype) && ins->inst_vtype->type != MONO_TYPE_TYPEDBYREF) {
1482 size = mono_class_native_size (mono_class_from_mono_type (ins->inst_vtype), &ualign);
1486 size = mono_type_size (ins->inst_vtype, &align);
1488 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1489 * since it loads/stores misaligned words, which don't do the right thing.
1491 if (align < 4 && size >= 4)
1493 offset += align - 1;
1494 offset &= ~(align - 1);
1495 ins->opcode = OP_REGOFFSET;
1496 ins->inst_offset = offset;
1497 ins->inst_basereg = cfg->frame_reg;
1499 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1504 ins = cfg->args [curinst];
1505 if (ins->opcode != OP_REGVAR) {
1506 ins->opcode = OP_REGOFFSET;
1507 ins->inst_basereg = cfg->frame_reg;
1508 offset += sizeof (gpointer) - 1;
1509 offset &= ~(sizeof (gpointer) - 1);
1510 ins->inst_offset = offset;
1511 offset += sizeof (gpointer);
1516 if (sig->call_convention == MONO_CALL_VARARG) {
1520 /* Allocate a local slot to hold the sig cookie address */
1521 offset += align - 1;
1522 offset &= ~(align - 1);
1523 cfg->sig_cookie = offset;
1527 for (i = 0; i < sig->param_count; ++i) {
1528 ins = cfg->args [curinst];
1530 if (ins->opcode != OP_REGVAR) {
1531 ins->opcode = OP_REGOFFSET;
1532 ins->inst_basereg = cfg->frame_reg;
1533 size = mini_type_stack_size_full (NULL, sig->params [i], &ualign, sig->pinvoke);
1535 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1536 * since it loads/stores misaligned words, which don't do the right thing.
1538 if (align < 4 && size >= 4)
1540 /* The code in the prolog () stores words when storing vtypes received in a register */
1541 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1543 offset += align - 1;
1544 offset &= ~(align - 1);
1545 ins->inst_offset = offset;
1551 /* align the offset to 8 bytes */
1556 cfg->stack_offset = offset;
1560 mono_arch_create_vars (MonoCompile *cfg)
1562 MonoMethodSignature *sig;
1565 sig = mono_method_signature (cfg->method);
1567 if (!cfg->arch.cinfo)
1568 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1569 cinfo = cfg->arch.cinfo;
1571 if (cinfo->ret.storage == RegTypeStructByVal)
1572 cfg->ret_var_is_local = TRUE;
1574 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
1575 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1576 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1577 printf ("vret_addr = ");
1578 mono_print_ins (cfg->vret_addr);
1582 if (cfg->gen_seq_points) {
1583 if (cfg->soft_breakpoints) {
1584 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1585 ins->flags |= MONO_INST_VOLATILE;
1586 cfg->arch.seq_point_read_var = ins;
1588 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1589 ins->flags |= MONO_INST_VOLATILE;
1590 cfg->arch.seq_point_ss_method_var = ins;
1592 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1593 ins->flags |= MONO_INST_VOLATILE;
1594 cfg->arch.seq_point_bp_method_var = ins;
1596 g_assert (!cfg->compile_aot);
1597 } else if (cfg->compile_aot) {
1598 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1599 ins->flags |= MONO_INST_VOLATILE;
1600 cfg->arch.seq_point_info_var = ins;
1602 /* Allocate a separate variable for this to save 1 load per seq point */
1603 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1604 ins->flags |= MONO_INST_VOLATILE;
1605 cfg->arch.ss_trigger_page_var = ins;
1611 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1613 MonoMethodSignature *tmp_sig;
1616 if (call->tail_call)
1619 /* FIXME: Add support for signature tokens to AOT */
1620 cfg->disable_aot = TRUE;
1622 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1625 * mono_ArgIterator_Setup assumes the signature cookie is
1626 * passed first and all the arguments which were before it are
1627 * passed on the stack after the signature. So compensate by
1628 * passing a different signature.
1630 tmp_sig = mono_metadata_signature_dup (call->signature);
1631 tmp_sig->param_count -= call->signature->sentinelpos;
1632 tmp_sig->sentinelpos = 0;
1633 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1635 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1636 sig_arg->dreg = mono_alloc_ireg (cfg);
1637 sig_arg->inst_p0 = tmp_sig;
1638 MONO_ADD_INS (cfg->cbb, sig_arg);
1640 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_arg->dreg);
1645 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1650 LLVMCallInfo *linfo;
1652 n = sig->param_count + sig->hasthis;
1654 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1656 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1659 * LLVM always uses the native ABI while we use our own ABI, the
1660 * only difference is the handling of vtypes:
1661 * - we only pass/receive them in registers in some cases, and only
1662 * in 1 or 2 integer registers.
1664 if (cinfo->vtype_retaddr) {
1665 /* Vtype returned using a hidden argument */
1666 linfo->ret.storage = LLVMArgVtypeRetAddr;
1667 linfo->vret_arg_index = cinfo->vret_arg_index;
1668 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1669 cfg->exception_message = g_strdup ("unknown ret conv");
1670 cfg->disable_llvm = TRUE;
1674 for (i = 0; i < n; ++i) {
1675 ainfo = cinfo->args + i;
1677 linfo->args [i].storage = LLVMArgNone;
1679 switch (ainfo->storage) {
1680 case RegTypeGeneral:
1681 case RegTypeIRegPair:
1683 linfo->args [i].storage = LLVMArgInIReg;
1685 case RegTypeStructByVal:
1686 // FIXME: Passing entirely on the stack or split reg/stack
1687 if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1688 linfo->args [i].storage = LLVMArgVtypeInReg;
1689 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1690 if (ainfo->size == 2)
1691 linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1693 linfo->args [i].pair_storage [1] = LLVMArgNone;
1695 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1696 cfg->disable_llvm = TRUE;
1700 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1701 cfg->disable_llvm = TRUE;
1711 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1714 MonoMethodSignature *sig;
1718 sig = call->signature;
1719 n = sig->param_count + sig->hasthis;
1721 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1723 for (i = 0; i < n; ++i) {
1724 ArgInfo *ainfo = cinfo->args + i;
1727 if (i >= sig->hasthis)
1728 t = sig->params [i - sig->hasthis];
1730 t = &mono_defaults.int_class->byval_arg;
1731 t = mini_type_get_underlying_type (NULL, t);
1733 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1734 /* Emit the signature cookie just before the implicit arguments */
1735 emit_sig_cookie (cfg, call, cinfo);
1738 in = call->args [i];
1740 switch (ainfo->storage) {
1741 case RegTypeGeneral:
1742 case RegTypeIRegPair:
1743 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1744 MONO_INST_NEW (cfg, ins, OP_MOVE);
1745 ins->dreg = mono_alloc_ireg (cfg);
1746 ins->sreg1 = in->dreg + 1;
1747 MONO_ADD_INS (cfg->cbb, ins);
1748 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1750 MONO_INST_NEW (cfg, ins, OP_MOVE);
1751 ins->dreg = mono_alloc_ireg (cfg);
1752 ins->sreg1 = in->dreg + 2;
1753 MONO_ADD_INS (cfg->cbb, ins);
1754 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1755 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1756 #ifndef MONO_ARCH_SOFT_FLOAT
1760 if (ainfo->size == 4) {
1761 #ifdef MONO_ARCH_SOFT_FLOAT
1762 /* mono_emit_call_args () have already done the r8->r4 conversion */
1763 /* The converted value is in an int vreg */
1764 MONO_INST_NEW (cfg, ins, OP_MOVE);
1765 ins->dreg = mono_alloc_ireg (cfg);
1766 ins->sreg1 = in->dreg;
1767 MONO_ADD_INS (cfg->cbb, ins);
1768 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1770 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1771 creg = mono_alloc_ireg (cfg);
1772 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1773 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1776 #ifdef MONO_ARCH_SOFT_FLOAT
1777 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1778 ins->dreg = mono_alloc_ireg (cfg);
1779 ins->sreg1 = in->dreg;
1780 MONO_ADD_INS (cfg->cbb, ins);
1781 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1783 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1784 ins->dreg = mono_alloc_ireg (cfg);
1785 ins->sreg1 = in->dreg;
1786 MONO_ADD_INS (cfg->cbb, ins);
1787 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1789 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1790 creg = mono_alloc_ireg (cfg);
1791 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1792 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1793 creg = mono_alloc_ireg (cfg);
1794 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1795 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1798 cfg->flags |= MONO_CFG_HAS_FPOUT;
1800 MONO_INST_NEW (cfg, ins, OP_MOVE);
1801 ins->dreg = mono_alloc_ireg (cfg);
1802 ins->sreg1 = in->dreg;
1803 MONO_ADD_INS (cfg->cbb, ins);
1805 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1808 case RegTypeStructByAddr:
1811 /* FIXME: where si the data allocated? */
1812 arg->backend.reg3 = ainfo->reg;
1813 call->used_iregs |= 1 << ainfo->reg;
1814 g_assert_not_reached ();
1817 case RegTypeStructByVal:
1818 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1819 ins->opcode = OP_OUTARG_VT;
1820 ins->sreg1 = in->dreg;
1821 ins->klass = in->klass;
1822 ins->inst_p0 = call;
1823 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1824 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1825 mono_call_inst_add_outarg_vt (cfg, call, ins);
1826 MONO_ADD_INS (cfg->cbb, ins);
1829 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1830 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1831 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1832 if (t->type == MONO_TYPE_R8) {
1833 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1835 #ifdef MONO_ARCH_SOFT_FLOAT
1836 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1838 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1842 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1845 case RegTypeBaseGen:
1846 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1847 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1848 MONO_INST_NEW (cfg, ins, OP_MOVE);
1849 ins->dreg = mono_alloc_ireg (cfg);
1850 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1851 MONO_ADD_INS (cfg->cbb, ins);
1852 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1853 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1856 /* This should work for soft-float as well */
1858 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1859 creg = mono_alloc_ireg (cfg);
1860 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1861 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1862 creg = mono_alloc_ireg (cfg);
1863 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1864 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1865 cfg->flags |= MONO_CFG_HAS_FPOUT;
1867 g_assert_not_reached ();
1874 arg->backend.reg3 = ainfo->reg;
1875 /* FP args are passed in int regs */
1876 call->used_iregs |= 1 << ainfo->reg;
1877 if (ainfo->size == 8) {
1878 arg->opcode = OP_OUTARG_R8;
1879 call->used_iregs |= 1 << (ainfo->reg + 1);
1881 arg->opcode = OP_OUTARG_R4;
1884 cfg->flags |= MONO_CFG_HAS_FPOUT;
1888 g_assert_not_reached ();
1892 /* Handle the case where there are no implicit arguments */
1893 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1894 emit_sig_cookie (cfg, call, cinfo);
1896 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1899 if (cinfo->ret.storage == RegTypeStructByVal) {
1900 /* The JIT will transform this into a normal call */
1901 call->vret_in_reg = TRUE;
1903 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1904 vtarg->sreg1 = call->vret_var->dreg;
1905 vtarg->dreg = mono_alloc_preg (cfg);
1906 MONO_ADD_INS (cfg->cbb, vtarg);
1908 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1912 call->stack_usage = cinfo->stack_usage;
1918 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1920 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1921 ArgInfo *ainfo = ins->inst_p1;
1922 int ovf_size = ainfo->vtsize;
1923 int doffset = ainfo->offset;
1924 int struct_size = ainfo->struct_size;
1925 int i, soffset, dreg, tmpreg;
1928 for (i = 0; i < ainfo->size; ++i) {
1929 dreg = mono_alloc_ireg (cfg);
1930 switch (struct_size) {
1932 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1935 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
1938 tmpreg = mono_alloc_ireg (cfg);
1939 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1940 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
1941 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
1942 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1943 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
1944 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
1945 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1948 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1951 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
1952 soffset += sizeof (gpointer);
1953 struct_size -= sizeof (gpointer);
1955 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
1957 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
1961 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1963 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1966 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1969 if (COMPILE_LLVM (cfg)) {
1970 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1972 MONO_INST_NEW (cfg, ins, OP_SETLRET);
1973 ins->sreg1 = val->dreg + 1;
1974 ins->sreg2 = val->dreg + 2;
1975 MONO_ADD_INS (cfg->cbb, ins);
1979 #ifdef MONO_ARCH_SOFT_FLOAT
1980 if (ret->type == MONO_TYPE_R8) {
1983 MONO_INST_NEW (cfg, ins, OP_SETFRET);
1984 ins->dreg = cfg->ret->dreg;
1985 ins->sreg1 = val->dreg;
1986 MONO_ADD_INS (cfg->cbb, ins);
1989 if (ret->type == MONO_TYPE_R4) {
1990 /* Already converted to an int in method_to_ir () */
1991 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1994 #elif defined(ARM_FPU_VFP)
1995 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
1998 MONO_INST_NEW (cfg, ins, OP_SETFRET);
1999 ins->dreg = cfg->ret->dreg;
2000 ins->sreg1 = val->dreg;
2001 MONO_ADD_INS (cfg->cbb, ins);
2005 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
2006 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2013 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2016 #endif /* #ifndef DISABLE_JIT */
2019 mono_arch_is_inst_imm (gint64 imm)
2024 #define DYN_CALL_STACK_ARGS 6
2027 MonoMethodSignature *sig;
2032 mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
2038 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2042 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2045 switch (cinfo->ret.storage) {
2047 case RegTypeGeneral:
2048 case RegTypeIRegPair:
2049 case RegTypeStructByAddr:
2054 #elif defined(ARM_FPU_VFP)
2063 for (i = 0; i < cinfo->nargs; ++i) {
2064 switch (cinfo->args [i].storage) {
2065 case RegTypeGeneral:
2067 case RegTypeIRegPair:
2070 if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2073 case RegTypeStructByVal:
2074 if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2082 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2083 for (i = 0; i < sig->param_count; ++i) {
2084 MonoType *t = sig->params [i];
2092 #ifdef MONO_ARCH_SOFT_FLOAT
2111 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2113 ArchDynCallInfo *info;
2116 cinfo = get_call_info (NULL, NULL, sig);
2118 if (!dyn_call_supported (cinfo, sig)) {
2123 info = g_new0 (ArchDynCallInfo, 1);
2124 // FIXME: Preprocess the info to speed up start_dyn_call ()
2126 info->cinfo = cinfo;
2128 return (MonoDynCallInfo*)info;
2132 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2134 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2136 g_free (ainfo->cinfo);
2141 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2143 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2144 DynCallArgs *p = (DynCallArgs*)buf;
2145 int arg_index, greg, i, j, pindex;
2146 MonoMethodSignature *sig = dinfo->sig;
2148 g_assert (buf_len >= sizeof (DynCallArgs));
2157 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2158 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2163 if (dinfo->cinfo->vtype_retaddr)
2164 p->regs [greg ++] = (mgreg_t)ret;
2166 for (i = pindex; i < sig->param_count; i++) {
2167 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2168 gpointer *arg = args [arg_index ++];
2169 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2172 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2174 else if (ainfo->storage == RegTypeBase)
2175 slot = PARAM_REGS + (ainfo->offset / 4);
2177 g_assert_not_reached ();
2180 p->regs [slot] = (mgreg_t)*arg;
2185 case MONO_TYPE_STRING:
2186 case MONO_TYPE_CLASS:
2187 case MONO_TYPE_ARRAY:
2188 case MONO_TYPE_SZARRAY:
2189 case MONO_TYPE_OBJECT:
2193 p->regs [slot] = (mgreg_t)*arg;
2195 case MONO_TYPE_BOOLEAN:
2197 p->regs [slot] = *(guint8*)arg;
2200 p->regs [slot] = *(gint8*)arg;
2203 p->regs [slot] = *(gint16*)arg;
2206 case MONO_TYPE_CHAR:
2207 p->regs [slot] = *(guint16*)arg;
2210 p->regs [slot] = *(gint32*)arg;
2213 p->regs [slot] = *(guint32*)arg;
2217 p->regs [slot ++] = (mgreg_t)arg [0];
2218 p->regs [slot] = (mgreg_t)arg [1];
2221 p->regs [slot] = *(mgreg_t*)arg;
2224 p->regs [slot ++] = (mgreg_t)arg [0];
2225 p->regs [slot] = (mgreg_t)arg [1];
2227 case MONO_TYPE_GENERICINST:
2228 if (MONO_TYPE_IS_REFERENCE (t)) {
2229 p->regs [slot] = (mgreg_t)*arg;
2234 case MONO_TYPE_VALUETYPE:
2235 g_assert (ainfo->storage == RegTypeStructByVal);
2237 if (ainfo->size == 0)
2238 slot = PARAM_REGS + (ainfo->offset / 4);
2242 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2243 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2246 g_assert_not_reached ();
2252 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2254 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2255 MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2256 guint8 *ret = ((DynCallArgs*)buf)->ret;
2257 mgreg_t res = ((DynCallArgs*)buf)->res;
2258 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2260 switch (mono_type_get_underlying_type (sig->ret)->type) {
2261 case MONO_TYPE_VOID:
2262 *(gpointer*)ret = NULL;
2264 case MONO_TYPE_STRING:
2265 case MONO_TYPE_CLASS:
2266 case MONO_TYPE_ARRAY:
2267 case MONO_TYPE_SZARRAY:
2268 case MONO_TYPE_OBJECT:
2272 *(gpointer*)ret = (gpointer)res;
2278 case MONO_TYPE_BOOLEAN:
2279 *(guint8*)ret = res;
2282 *(gint16*)ret = res;
2285 case MONO_TYPE_CHAR:
2286 *(guint16*)ret = res;
2289 *(gint32*)ret = res;
2292 *(guint32*)ret = res;
2296 /* This handles endianness as well */
2297 ((gint32*)ret) [0] = res;
2298 ((gint32*)ret) [1] = res2;
2300 case MONO_TYPE_GENERICINST:
2301 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2302 *(gpointer*)ret = (gpointer)res;
2307 case MONO_TYPE_VALUETYPE:
2308 g_assert (ainfo->cinfo->vtype_retaddr);
2311 #if defined(ARM_FPU_VFP)
2313 *(float*)ret = *(float*)&res;
2315 case MONO_TYPE_R8: {
2321 *(double*)ret = *(double*)®s;
2326 g_assert_not_reached ();
2333 * Allow tracing to work with this interface (with an optional argument)
2337 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2341 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2342 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2343 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2344 code = emit_call_reg (code, ARMREG_R2);
2357 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2360 int save_mode = SAVE_NONE;
2362 MonoMethod *method = cfg->method;
2363 int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2364 int save_offset = cfg->param_area;
2368 offset = code - cfg->native_code;
2369 /* we need about 16 instructions */
2370 if (offset > (cfg->code_size - 16 * 4)) {
2371 cfg->code_size *= 2;
2372 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2373 code = cfg->native_code + offset;
2376 case MONO_TYPE_VOID:
2377 /* special case string .ctor icall */
2378 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2379 save_mode = SAVE_ONE;
2381 save_mode = SAVE_NONE;
2385 save_mode = SAVE_TWO;
2389 save_mode = SAVE_FP;
2391 case MONO_TYPE_VALUETYPE:
2392 save_mode = SAVE_STRUCT;
2395 save_mode = SAVE_ONE;
2399 switch (save_mode) {
2401 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2402 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2403 if (enable_arguments) {
2404 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2405 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2409 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2410 if (enable_arguments) {
2411 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2415 /* FIXME: what reg? */
2416 if (enable_arguments) {
2417 /* FIXME: what reg? */
2421 if (enable_arguments) {
2422 /* FIXME: get the actual address */
2423 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2431 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2432 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2433 code = emit_call_reg (code, ARMREG_IP);
2435 switch (save_mode) {
2437 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2438 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2441 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2455 * The immediate field for cond branches is big enough for all reasonable methods
2457 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2458 if (0 && ins->inst_true_bb->native_offset) { \
2459 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2461 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2462 ARM_B_COND (code, (condcode), 0); \
2465 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2467 /* emit an exception if condition is fail
2469 * We assign the extra code used to throw the implicit exceptions
2470 * to cfg->bb_exit as far as the big branch handling is concerned
2472 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
2474 mono_add_patch_info (cfg, code - cfg->native_code, \
2475 MONO_PATCH_INFO_EXC, exc_name); \
2476 ARM_BL_COND (code, (condcode), 0); \
2479 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2482 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2487 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2489 MonoInst *ins, *n, *last_ins = NULL;
2491 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2492 switch (ins->opcode) {
2495 /* Already done by an arch-independent pass */
2497 case OP_LOAD_MEMBASE:
2498 case OP_LOADI4_MEMBASE:
2500 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2501 * OP_LOAD_MEMBASE offset(basereg), reg
2503 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2504 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2505 ins->inst_basereg == last_ins->inst_destbasereg &&
2506 ins->inst_offset == last_ins->inst_offset) {
2507 if (ins->dreg == last_ins->sreg1) {
2508 MONO_DELETE_INS (bb, ins);
2511 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2512 ins->opcode = OP_MOVE;
2513 ins->sreg1 = last_ins->sreg1;
2517 * Note: reg1 must be different from the basereg in the second load
2518 * OP_LOAD_MEMBASE offset(basereg), reg1
2519 * OP_LOAD_MEMBASE offset(basereg), reg2
2521 * OP_LOAD_MEMBASE offset(basereg), reg1
2522 * OP_MOVE reg1, reg2
2524 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2525 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2526 ins->inst_basereg != last_ins->dreg &&
2527 ins->inst_basereg == last_ins->inst_basereg &&
2528 ins->inst_offset == last_ins->inst_offset) {
2530 if (ins->dreg == last_ins->dreg) {
2531 MONO_DELETE_INS (bb, ins);
2534 ins->opcode = OP_MOVE;
2535 ins->sreg1 = last_ins->dreg;
2538 //g_assert_not_reached ();
2542 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2543 * OP_LOAD_MEMBASE offset(basereg), reg
2545 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2546 * OP_ICONST reg, imm
2548 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2549 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2550 ins->inst_basereg == last_ins->inst_destbasereg &&
2551 ins->inst_offset == last_ins->inst_offset) {
2552 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2553 ins->opcode = OP_ICONST;
2554 ins->inst_c0 = last_ins->inst_imm;
2555 g_assert_not_reached (); // check this rule
2559 case OP_LOADU1_MEMBASE:
2560 case OP_LOADI1_MEMBASE:
2561 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2562 ins->inst_basereg == last_ins->inst_destbasereg &&
2563 ins->inst_offset == last_ins->inst_offset) {
2564 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2565 ins->sreg1 = last_ins->sreg1;
2568 case OP_LOADU2_MEMBASE:
2569 case OP_LOADI2_MEMBASE:
2570 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2571 ins->inst_basereg == last_ins->inst_destbasereg &&
2572 ins->inst_offset == last_ins->inst_offset) {
2573 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2574 ins->sreg1 = last_ins->sreg1;
2578 ins->opcode = OP_MOVE;
2582 if (ins->dreg == ins->sreg1) {
2583 MONO_DELETE_INS (bb, ins);
2587 * OP_MOVE sreg, dreg
2588 * OP_MOVE dreg, sreg
2590 if (last_ins && last_ins->opcode == OP_MOVE &&
2591 ins->sreg1 == last_ins->dreg &&
2592 ins->dreg == last_ins->sreg1) {
2593 MONO_DELETE_INS (bb, ins);
2601 bb->last_ins = last_ins;
2605 * the branch_cc_table should maintain the order of these
2619 branch_cc_table [] = {
2633 #define NEW_INS(cfg,dest,op) do { \
2634 MONO_INST_NEW ((cfg), (dest), (op)); \
2635 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2639 map_to_reg_reg_op (int op)
2648 case OP_COMPARE_IMM:
2650 case OP_ICOMPARE_IMM:
2664 case OP_LOAD_MEMBASE:
2665 return OP_LOAD_MEMINDEX;
2666 case OP_LOADI4_MEMBASE:
2667 return OP_LOADI4_MEMINDEX;
2668 case OP_LOADU4_MEMBASE:
2669 return OP_LOADU4_MEMINDEX;
2670 case OP_LOADU1_MEMBASE:
2671 return OP_LOADU1_MEMINDEX;
2672 case OP_LOADI2_MEMBASE:
2673 return OP_LOADI2_MEMINDEX;
2674 case OP_LOADU2_MEMBASE:
2675 return OP_LOADU2_MEMINDEX;
2676 case OP_LOADI1_MEMBASE:
2677 return OP_LOADI1_MEMINDEX;
2678 case OP_STOREI1_MEMBASE_REG:
2679 return OP_STOREI1_MEMINDEX;
2680 case OP_STOREI2_MEMBASE_REG:
2681 return OP_STOREI2_MEMINDEX;
2682 case OP_STOREI4_MEMBASE_REG:
2683 return OP_STOREI4_MEMINDEX;
2684 case OP_STORE_MEMBASE_REG:
2685 return OP_STORE_MEMINDEX;
2686 case OP_STORER4_MEMBASE_REG:
2687 return OP_STORER4_MEMINDEX;
2688 case OP_STORER8_MEMBASE_REG:
2689 return OP_STORER8_MEMINDEX;
2690 case OP_STORE_MEMBASE_IMM:
2691 return OP_STORE_MEMBASE_REG;
2692 case OP_STOREI1_MEMBASE_IMM:
2693 return OP_STOREI1_MEMBASE_REG;
2694 case OP_STOREI2_MEMBASE_IMM:
2695 return OP_STOREI2_MEMBASE_REG;
2696 case OP_STOREI4_MEMBASE_IMM:
2697 return OP_STOREI4_MEMBASE_REG;
2699 g_assert_not_reached ();
2703 * Remove from the instruction list the instructions that can't be
2704 * represented with very simple instructions with no register
2708 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2710 MonoInst *ins, *temp, *last_ins = NULL;
2711 int rot_amount, imm8, low_imm;
2713 MONO_BB_FOR_EACH_INS (bb, ins) {
2715 switch (ins->opcode) {
2719 case OP_COMPARE_IMM:
2720 case OP_ICOMPARE_IMM:
2734 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2735 NEW_INS (cfg, temp, OP_ICONST);
2736 temp->inst_c0 = ins->inst_imm;
2737 temp->dreg = mono_alloc_ireg (cfg);
2738 ins->sreg2 = temp->dreg;
2739 ins->opcode = mono_op_imm_to_op (ins->opcode);
2741 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2747 if (ins->inst_imm == 1) {
2748 ins->opcode = OP_MOVE;
2751 if (ins->inst_imm == 0) {
2752 ins->opcode = OP_ICONST;
2756 imm8 = mono_is_power_of_two (ins->inst_imm);
2758 ins->opcode = OP_SHL_IMM;
2759 ins->inst_imm = imm8;
2762 NEW_INS (cfg, temp, OP_ICONST);
2763 temp->inst_c0 = ins->inst_imm;
2764 temp->dreg = mono_alloc_ireg (cfg);
2765 ins->sreg2 = temp->dreg;
2766 ins->opcode = OP_IMUL;
2772 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2773 /* ARM sets the C flag to 1 if there was _no_ overflow */
2774 ins->next->opcode = OP_COND_EXC_NC;
2776 case OP_LOCALLOC_IMM:
2777 NEW_INS (cfg, temp, OP_ICONST);
2778 temp->inst_c0 = ins->inst_imm;
2779 temp->dreg = mono_alloc_ireg (cfg);
2780 ins->sreg1 = temp->dreg;
2781 ins->opcode = OP_LOCALLOC;
2783 case OP_LOAD_MEMBASE:
2784 case OP_LOADI4_MEMBASE:
2785 case OP_LOADU4_MEMBASE:
2786 case OP_LOADU1_MEMBASE:
2787 /* we can do two things: load the immed in a register
2788 * and use an indexed load, or see if the immed can be
2789 * represented as an ad_imm + a load with a smaller offset
2790 * that fits. We just do the first for now, optimize later.
2792 if (arm_is_imm12 (ins->inst_offset))
2794 NEW_INS (cfg, temp, OP_ICONST);
2795 temp->inst_c0 = ins->inst_offset;
2796 temp->dreg = mono_alloc_ireg (cfg);
2797 ins->sreg2 = temp->dreg;
2798 ins->opcode = map_to_reg_reg_op (ins->opcode);
2800 case OP_LOADI2_MEMBASE:
2801 case OP_LOADU2_MEMBASE:
2802 case OP_LOADI1_MEMBASE:
2803 if (arm_is_imm8 (ins->inst_offset))
2805 NEW_INS (cfg, temp, OP_ICONST);
2806 temp->inst_c0 = ins->inst_offset;
2807 temp->dreg = mono_alloc_ireg (cfg);
2808 ins->sreg2 = temp->dreg;
2809 ins->opcode = map_to_reg_reg_op (ins->opcode);
2811 case OP_LOADR4_MEMBASE:
2812 case OP_LOADR8_MEMBASE:
2813 if (arm_is_fpimm8 (ins->inst_offset))
2815 low_imm = ins->inst_offset & 0x1ff;
2816 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2817 NEW_INS (cfg, temp, OP_ADD_IMM);
2818 temp->inst_imm = ins->inst_offset & ~0x1ff;
2819 temp->sreg1 = ins->inst_basereg;
2820 temp->dreg = mono_alloc_ireg (cfg);
2821 ins->inst_basereg = temp->dreg;
2822 ins->inst_offset = low_imm;
2825 /* VFP/FPA doesn't have indexed load instructions */
2826 g_assert_not_reached ();
2828 case OP_STORE_MEMBASE_REG:
2829 case OP_STOREI4_MEMBASE_REG:
2830 case OP_STOREI1_MEMBASE_REG:
2831 if (arm_is_imm12 (ins->inst_offset))
2833 NEW_INS (cfg, temp, OP_ICONST);
2834 temp->inst_c0 = ins->inst_offset;
2835 temp->dreg = mono_alloc_ireg (cfg);
2836 ins->sreg2 = temp->dreg;
2837 ins->opcode = map_to_reg_reg_op (ins->opcode);
2839 case OP_STOREI2_MEMBASE_REG:
2840 if (arm_is_imm8 (ins->inst_offset))
2842 NEW_INS (cfg, temp, OP_ICONST);
2843 temp->inst_c0 = ins->inst_offset;
2844 temp->dreg = mono_alloc_ireg (cfg);
2845 ins->sreg2 = temp->dreg;
2846 ins->opcode = map_to_reg_reg_op (ins->opcode);
2848 case OP_STORER4_MEMBASE_REG:
2849 case OP_STORER8_MEMBASE_REG:
2850 if (arm_is_fpimm8 (ins->inst_offset))
2852 low_imm = ins->inst_offset & 0x1ff;
2853 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2854 NEW_INS (cfg, temp, OP_ADD_IMM);
2855 temp->inst_imm = ins->inst_offset & ~0x1ff;
2856 temp->sreg1 = ins->inst_destbasereg;
2857 temp->dreg = mono_alloc_ireg (cfg);
2858 ins->inst_destbasereg = temp->dreg;
2859 ins->inst_offset = low_imm;
2862 /*g_print ("fail with: %d (%d, %d)\n", ins->inst_offset, ins->inst_offset & ~0x1ff, low_imm);*/
2863 /* VFP/FPA doesn't have indexed store instructions */
2864 g_assert_not_reached ();
2866 case OP_STORE_MEMBASE_IMM:
2867 case OP_STOREI1_MEMBASE_IMM:
2868 case OP_STOREI2_MEMBASE_IMM:
2869 case OP_STOREI4_MEMBASE_IMM:
2870 NEW_INS (cfg, temp, OP_ICONST);
2871 temp->inst_c0 = ins->inst_imm;
2872 temp->dreg = mono_alloc_ireg (cfg);
2873 ins->sreg1 = temp->dreg;
2874 ins->opcode = map_to_reg_reg_op (ins->opcode);
2876 goto loop_start; /* make it handle the possibly big ins->inst_offset */
2878 gboolean swap = FALSE;
2882 /* Optimized away */
2887 /* Some fp compares require swapped operands */
2888 switch (ins->next->opcode) {
2890 ins->next->opcode = OP_FBLT;
2894 ins->next->opcode = OP_FBLT_UN;
2898 ins->next->opcode = OP_FBGE;
2902 ins->next->opcode = OP_FBGE_UN;
2910 ins->sreg1 = ins->sreg2;
2919 bb->last_ins = last_ins;
2920 bb->max_vreg = cfg->next_vreg;
2924 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2928 if (long_ins->opcode == OP_LNEG) {
2930 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
2931 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
2937 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2939 /* sreg is a float, dreg is an integer reg */
2941 ARM_FIXZ (code, dreg, sreg);
2942 #elif defined(ARM_FPU_VFP)
2944 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
2946 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
2947 ARM_FMRS (code, dreg, ARM_VFP_F0);
2951 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
2952 else if (size == 2) {
2953 ARM_SHL_IMM (code, dreg, dreg, 16);
2954 ARM_SHR_IMM (code, dreg, dreg, 16);
2958 ARM_SHL_IMM (code, dreg, dreg, 24);
2959 ARM_SAR_IMM (code, dreg, dreg, 24);
2960 } else if (size == 2) {
2961 ARM_SHL_IMM (code, dreg, dreg, 16);
2962 ARM_SAR_IMM (code, dreg, dreg, 16);
2968 #endif /* #ifndef DISABLE_JIT */
2972 const guchar *target;
2977 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
2980 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
2981 PatchData *pdata = (PatchData*)user_data;
2982 guchar *code = data;
2983 guint32 *thunks = data;
2984 guint32 *endthunks = (guint32*)(code + bsize);
2986 int difflow, diffhigh;
2988 /* always ensure a call from pdata->code can reach to the thunks without further thunks */
2989 difflow = (char*)pdata->code - (char*)thunks;
2990 diffhigh = (char*)pdata->code - (char*)endthunks;
2991 if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
2995 * The thunk is composed of 3 words:
2996 * load constant from thunks [2] into ARM_IP
2999 * Note that the LR register is already setup
3001 //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
3002 if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
3003 while (thunks < endthunks) {
3004 //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
3005 if (thunks [2] == (guint32)pdata->target) {
3006 arm_patch (pdata->code, (guchar*)thunks);
3007 mono_arch_flush_icache (pdata->code, 4);
3010 } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
3011 /* found a free slot instead: emit thunk */
3012 /* ARMREG_IP is fine to use since this can't be an IMT call
3015 code = (guchar*)thunks;
3016 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3017 if (thumb_supported)
3018 ARM_BX (code, ARMREG_IP);
3020 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3021 thunks [2] = (guint32)pdata->target;
3022 mono_arch_flush_icache ((guchar*)thunks, 12);
3024 arm_patch (pdata->code, (guchar*)thunks);
3025 mono_arch_flush_icache (pdata->code, 4);
3029 /* skip 12 bytes, the size of the thunk */
3033 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
3039 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3044 domain = mono_domain_get ();
3047 pdata.target = target;
3048 pdata.absolute = absolute;
3052 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
3055 if (pdata.found != 1) {
3056 mono_domain_lock (domain);
3057 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3060 /* this uses the first available slot */
3062 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3064 mono_domain_unlock (domain);
3067 if (pdata.found != 1) {
3069 GHashTableIter iter;
3070 MonoJitDynamicMethodInfo *ji;
3073 * This might be a dynamic method, search its code manager. We can only
3074 * use the dynamic method containing CODE, since the others might be freed later.
3078 mono_domain_lock (domain);
3079 hash = domain_jit_info (domain)->dynamic_code_hash;
3081 /* FIXME: Speed this up */
3082 g_hash_table_iter_init (&iter, hash);
3083 while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
3084 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
3085 if (pdata.found == 1)
3089 mono_domain_unlock (domain);
3091 if (pdata.found != 1)
3092 g_print ("thunk failed for %p from %p\n", target, code);
3093 g_assert (pdata.found == 1);
3097 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3099 guint32 *code32 = (void*)code;
3100 guint32 ins = *code32;
3101 guint32 prim = (ins >> 25) & 7;
3102 guint32 tval = GPOINTER_TO_UINT (target);
3104 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3105 if (prim == 5) { /* 101b */
3106 /* the diff starts 8 bytes from the branch opcode */
3107 gint diff = target - code - 8;
3109 gint tmask = 0xffffffff;
3110 if (tval & 1) { /* entering thumb mode */
3111 diff = target - 1 - code - 8;
3112 g_assert (thumb_supported);
3113 tbits = 0xf << 28; /* bl->blx bit pattern */
3114 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3115 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3119 tmask = ~(1 << 24); /* clear the link bit */
3120 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3125 if (diff <= 33554431) {
3127 ins = (ins & 0xff000000) | diff;
3129 *code32 = ins | tbits;
3133 /* diff between 0 and -33554432 */
3134 if (diff >= -33554432) {
3136 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3138 *code32 = ins | tbits;
3143 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3148 * The alternative call sequences looks like this:
3150 * ldr ip, [pc] // loads the address constant
3151 * b 1f // jumps around the constant
3152 * address constant embedded in the code
3157 * There are two cases for patching:
3158 * a) at the end of method emission: in this case code points to the start
3159 * of the call sequence
3160 * b) during runtime patching of the call site: in this case code points
3161 * to the mov pc, ip instruction
3163 * We have to handle also the thunk jump code sequence:
3167 * address constant // execution never reaches here
3169 if ((ins & 0x0ffffff0) == 0x12fff10) {
3170 /* Branch and exchange: the address is constructed in a reg
3171 * We can patch BX when the code sequence is the following:
3172 * ldr ip, [pc, #0] ; 0x8
3179 guint8 *emit = (guint8*)ccode;
3180 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3182 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3183 ARM_BX (emit, ARMREG_IP);
3185 /*patching from magic trampoline*/
3186 if (ins == ccode [3]) {
3187 g_assert (code32 [-4] == ccode [0]);
3188 g_assert (code32 [-3] == ccode [1]);
3189 g_assert (code32 [-1] == ccode [2]);
3190 code32 [-2] = (guint32)target;
3193 /*patching from JIT*/
3194 if (ins == ccode [0]) {
3195 g_assert (code32 [1] == ccode [1]);
3196 g_assert (code32 [3] == ccode [2]);
3197 g_assert (code32 [4] == ccode [3]);
3198 code32 [2] = (guint32)target;
3201 g_assert_not_reached ();
3202 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3210 guint8 *emit = (guint8*)ccode;
3211 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3213 ARM_BLX_REG (emit, ARMREG_IP);
3215 g_assert (code32 [-3] == ccode [0]);
3216 g_assert (code32 [-2] == ccode [1]);
3217 g_assert (code32 [0] == ccode [2]);
3219 code32 [-1] = (guint32)target;
3222 guint32 *tmp = ccode;
3223 guint8 *emit = (guint8*)tmp;
3224 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3225 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3226 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3227 ARM_BX (emit, ARMREG_IP);
3228 if (ins == ccode [2]) {
3229 g_assert_not_reached (); // should be -2 ...
3230 code32 [-1] = (guint32)target;
3233 if (ins == ccode [0]) {
3234 /* handles both thunk jump code and the far call sequence */
3235 code32 [2] = (guint32)target;
3238 g_assert_not_reached ();
3240 // g_print ("patched with 0x%08x\n", ins);
3244 arm_patch (guchar *code, const guchar *target)
3246 arm_patch_general (NULL, code, target, NULL);
3250 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3251 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3252 * to be used with the emit macros.
3253 * Return -1 otherwise.
3256 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3259 for (i = 0; i < 31; i+= 2) {
3260 res = (val << (32 - i)) | (val >> i);
3263 *rot_amount = i? 32 - i: 0;
3270 * Emits in code a sequence of instructions that load the value 'val'
3271 * into the dreg register. Uses at most 4 instructions.
3274 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3276 int imm8, rot_amount;
3278 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3279 /* skip the constant pool */
3285 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3286 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3287 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3288 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3291 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3293 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3297 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3299 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3301 if (val & 0xFF0000) {
3302 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3304 if (val & 0xFF000000) {
3305 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3307 } else if (val & 0xFF00) {
3308 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3309 if (val & 0xFF0000) {
3310 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3312 if (val & 0xFF000000) {
3313 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3315 } else if (val & 0xFF0000) {
3316 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3317 if (val & 0xFF000000) {
3318 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3321 //g_assert_not_reached ();
3327 mono_arm_thumb_supported (void)
3329 return thumb_supported;
3335 * emit_load_volatile_arguments:
3337 * Load volatile arguments from the stack to the original input registers.
3338 * Required before a tail call.
3341 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3343 MonoMethod *method = cfg->method;
3344 MonoMethodSignature *sig;
3349 /* FIXME: Generate intermediate code instead */
3351 sig = mono_method_signature (method);
3353 /* This is the opposite of the code in emit_prolog */
3357 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3359 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
3360 ArgInfo *ainfo = &cinfo->ret;
3361 inst = cfg->vret_addr;
3362 g_assert (arm_is_imm12 (inst->inst_offset));
3363 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3365 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3366 ArgInfo *ainfo = cinfo->args + i;
3367 inst = cfg->args [pos];
3369 if (cfg->verbose_level > 2)
3370 g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3371 if (inst->opcode == OP_REGVAR) {
3372 if (ainfo->storage == RegTypeGeneral)
3373 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3374 else if (ainfo->storage == RegTypeFP) {
3375 g_assert_not_reached ();
3376 } else if (ainfo->storage == RegTypeBase) {
3380 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3381 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3383 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3384 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3388 g_assert_not_reached ();
3390 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3391 switch (ainfo->size) {
3398 g_assert (arm_is_imm12 (inst->inst_offset));
3399 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3400 g_assert (arm_is_imm12 (inst->inst_offset + 4));
3401 ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3404 if (arm_is_imm12 (inst->inst_offset)) {
3405 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3407 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3408 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3412 } else if (ainfo->storage == RegTypeBaseGen) {
3415 } else if (ainfo->storage == RegTypeBase) {
3417 } else if (ainfo->storage == RegTypeFP) {
3418 g_assert_not_reached ();
3419 } else if (ainfo->storage == RegTypeStructByVal) {
3420 int doffset = inst->inst_offset;
3424 if (mono_class_from_mono_type (inst->inst_vtype))
3425 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3426 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3427 if (arm_is_imm12 (doffset)) {
3428 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3430 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3431 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3433 soffset += sizeof (gpointer);
3434 doffset += sizeof (gpointer);
3439 } else if (ainfo->storage == RegTypeStructByAddr) {
3454 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3459 guint8 *code = cfg->native_code + cfg->code_len;
3460 MonoInst *last_ins = NULL;
3461 guint last_offset = 0;
3463 int imm8, rot_amount;
3465 /* we don't align basic blocks of loops on arm */
3467 if (cfg->verbose_level > 2)
3468 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3470 cpos = bb->max_offset;
3472 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3473 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3474 //g_assert (!mono_compile_aot);
3477 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3478 /* this is not thread save, but good enough */
3479 /* fixme: howto handle overflows? */
3480 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3483 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3484 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3485 (gpointer)"mono_break");
3486 code = emit_call_seq (cfg, code);
3489 MONO_BB_FOR_EACH_INS (bb, ins) {
3490 offset = code - cfg->native_code;
3492 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3494 if (offset > (cfg->code_size - max_len - 16)) {
3495 cfg->code_size *= 2;
3496 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3497 code = cfg->native_code + offset;
3499 // if (ins->cil_code)
3500 // g_print ("cil code\n");
3501 mono_debug_record_line_number (cfg, ins, offset);
3503 switch (ins->opcode) {
3504 case OP_MEMORY_BARRIER:
3506 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
3507 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
3511 #ifdef HAVE_AEABI_READ_TP
3512 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3513 (gpointer)"__aeabi_read_tp");
3514 code = emit_call_seq (cfg, code);
3516 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3518 g_assert_not_reached ();
3522 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3523 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3526 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3527 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3529 case OP_STOREI1_MEMBASE_IMM:
3530 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3531 g_assert (arm_is_imm12 (ins->inst_offset));
3532 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3534 case OP_STOREI2_MEMBASE_IMM:
3535 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3536 g_assert (arm_is_imm8 (ins->inst_offset));
3537 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3539 case OP_STORE_MEMBASE_IMM:
3540 case OP_STOREI4_MEMBASE_IMM:
3541 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3542 g_assert (arm_is_imm12 (ins->inst_offset));
3543 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3545 case OP_STOREI1_MEMBASE_REG:
3546 g_assert (arm_is_imm12 (ins->inst_offset));
3547 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3549 case OP_STOREI2_MEMBASE_REG:
3550 g_assert (arm_is_imm8 (ins->inst_offset));
3551 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3553 case OP_STORE_MEMBASE_REG:
3554 case OP_STOREI4_MEMBASE_REG:
3555 /* this case is special, since it happens for spill code after lowering has been called */
3556 if (arm_is_imm12 (ins->inst_offset)) {
3557 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3559 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3560 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3563 case OP_STOREI1_MEMINDEX:
3564 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3566 case OP_STOREI2_MEMINDEX:
3567 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3569 case OP_STORE_MEMINDEX:
3570 case OP_STOREI4_MEMINDEX:
3571 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3574 g_assert_not_reached ();
3576 case OP_LOAD_MEMINDEX:
3577 case OP_LOADI4_MEMINDEX:
3578 case OP_LOADU4_MEMINDEX:
3579 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3581 case OP_LOADI1_MEMINDEX:
3582 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3584 case OP_LOADU1_MEMINDEX:
3585 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3587 case OP_LOADI2_MEMINDEX:
3588 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3590 case OP_LOADU2_MEMINDEX:
3591 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3593 case OP_LOAD_MEMBASE:
3594 case OP_LOADI4_MEMBASE:
3595 case OP_LOADU4_MEMBASE:
3596 /* this case is special, since it happens for spill code after lowering has been called */
3597 if (arm_is_imm12 (ins->inst_offset)) {
3598 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3600 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3601 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3604 case OP_LOADI1_MEMBASE:
3605 g_assert (arm_is_imm8 (ins->inst_offset));
3606 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3608 case OP_LOADU1_MEMBASE:
3609 g_assert (arm_is_imm12 (ins->inst_offset));
3610 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3612 case OP_LOADU2_MEMBASE:
3613 g_assert (arm_is_imm8 (ins->inst_offset));
3614 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3616 case OP_LOADI2_MEMBASE:
3617 g_assert (arm_is_imm8 (ins->inst_offset));
3618 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3620 case OP_ICONV_TO_I1:
3621 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3622 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3624 case OP_ICONV_TO_I2:
3625 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3626 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3628 case OP_ICONV_TO_U1:
3629 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3631 case OP_ICONV_TO_U2:
3632 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3633 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3637 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3639 case OP_COMPARE_IMM:
3640 case OP_ICOMPARE_IMM:
3641 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3642 g_assert (imm8 >= 0);
3643 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3647 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3648 * So instead of emitting a trap, we emit a call a C function and place a
3651 //*(int*)code = 0xef9f0001;
3654 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3655 (gpointer)"mono_break");
3656 code = emit_call_seq (cfg, code);
3658 case OP_RELAXED_NOP:
3663 case OP_DUMMY_STORE:
3664 case OP_NOT_REACHED:
3667 case OP_SEQ_POINT: {
3669 MonoInst *info_var = cfg->arch.seq_point_info_var;
3670 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3671 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
3672 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
3673 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
3675 int dreg = ARMREG_LR;
3677 if (cfg->soft_breakpoints) {
3678 g_assert (!cfg->compile_aot);
3682 * For AOT, we use one got slot per method, which will point to a
3683 * SeqPointInfo structure, containing all the information required
3684 * by the code below.
3686 if (cfg->compile_aot) {
3687 g_assert (info_var);
3688 g_assert (info_var->opcode == OP_REGOFFSET);
3689 g_assert (arm_is_imm12 (info_var->inst_offset));
3692 if (!cfg->soft_breakpoints) {
3694 * Read from the single stepping trigger page. This will cause a
3695 * SIGSEGV when single stepping is enabled.
3696 * We do this _before_ the breakpoint, so single stepping after
3697 * a breakpoint is hit will step to the next IL offset.
3699 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3702 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3703 if (cfg->soft_breakpoints) {
3704 /* Load the address of the sequence point trigger variable. */
3707 g_assert (var->opcode == OP_REGOFFSET);
3708 g_assert (arm_is_imm12 (var->inst_offset));
3709 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3711 /* Read the value and check whether it is non-zero. */
3712 ARM_LDR_IMM (code, dreg, dreg, 0);
3713 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3715 /* Load the address of the sequence point method. */
3716 var = ss_method_var;
3718 g_assert (var->opcode == OP_REGOFFSET);
3719 g_assert (arm_is_imm12 (var->inst_offset));
3720 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3722 /* Call it conditionally. */
3723 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
3725 if (cfg->compile_aot) {
3726 /* Load the trigger page addr from the variable initialized in the prolog */
3727 var = ss_trigger_page_var;
3729 g_assert (var->opcode == OP_REGOFFSET);
3730 g_assert (arm_is_imm12 (var->inst_offset));
3731 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3733 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3735 *(int*)code = (int)ss_trigger_page;
3738 ARM_LDR_IMM (code, dreg, dreg, 0);
3742 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3744 if (cfg->soft_breakpoints) {
3745 /* Load the address of the breakpoint method into ip. */
3746 var = bp_method_var;
3748 g_assert (var->opcode == OP_REGOFFSET);
3749 g_assert (arm_is_imm12 (var->inst_offset));
3750 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3753 * A placeholder for a possible breakpoint inserted by
3754 * mono_arch_set_breakpoint ().
3757 } else if (cfg->compile_aot) {
3758 guint32 offset = code - cfg->native_code;
3761 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3762 /* Add the offset */
3763 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3764 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3766 * Have to emit nops to keep the difference between the offset
3767 * stored in seq_points and breakpoint instruction constant,
3768 * mono_arch_get_ip_for_breakpoint () depends on this.
3771 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3775 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3778 g_assert (!(val & 0xFF000000));
3779 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3780 ARM_LDR_IMM (code, dreg, dreg, 0);
3782 /* What is faster, a branch or a load ? */
3783 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3784 /* The breakpoint instruction */
3785 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3788 * A placeholder for a possible breakpoint inserted by
3789 * mono_arch_set_breakpoint ().
3791 for (i = 0; i < 4; ++i)
3798 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3801 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3805 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3808 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3809 g_assert (imm8 >= 0);
3810 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3814 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3815 g_assert (imm8 >= 0);
3816 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3820 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3821 g_assert (imm8 >= 0);
3822 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3825 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3826 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3828 case OP_IADD_OVF_UN:
3829 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3830 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3833 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3834 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3836 case OP_ISUB_OVF_UN:
3837 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3838 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3840 case OP_ADD_OVF_CARRY:
3841 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3842 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3844 case OP_ADD_OVF_UN_CARRY:
3845 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3846 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3848 case OP_SUB_OVF_CARRY:
3849 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3850 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3852 case OP_SUB_OVF_UN_CARRY:
3853 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3854 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3858 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3861 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3862 g_assert (imm8 >= 0);
3863 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3866 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3870 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3874 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3875 g_assert (imm8 >= 0);
3876 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3880 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3881 g_assert (imm8 >= 0);
3882 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3884 case OP_ARM_RSBS_IMM:
3885 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3886 g_assert (imm8 >= 0);
3887 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3889 case OP_ARM_RSC_IMM:
3890 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3891 g_assert (imm8 >= 0);
3892 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3895 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3899 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3900 g_assert (imm8 >= 0);
3901 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3909 /* crappy ARM arch doesn't have a DIV instruction */
3910 g_assert_not_reached ();
3912 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3916 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3917 g_assert (imm8 >= 0);
3918 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3921 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3925 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3926 g_assert (imm8 >= 0);
3927 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3930 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3935 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3936 else if (ins->dreg != ins->sreg1)
3937 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3940 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3945 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3946 else if (ins->dreg != ins->sreg1)
3947 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3950 case OP_ISHR_UN_IMM:
3952 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3953 else if (ins->dreg != ins->sreg1)
3954 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3957 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3960 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
3963 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
3966 if (ins->dreg == ins->sreg2)
3967 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3969 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
3972 g_assert_not_reached ();
3975 /* FIXME: handle ovf/ sreg2 != dreg */
3976 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3977 /* FIXME: MUL doesn't set the C/O flags on ARM */
3979 case OP_IMUL_OVF_UN:
3980 /* FIXME: handle ovf/ sreg2 != dreg */
3981 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3982 /* FIXME: MUL doesn't set the C/O flags on ARM */
3985 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
3988 /* Load the GOT offset */
3989 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3990 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
3992 *(gpointer*)code = NULL;
3994 /* Load the value from the GOT */
3995 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
3997 case OP_ICONV_TO_I4:
3998 case OP_ICONV_TO_U4:
4000 if (ins->dreg != ins->sreg1)
4001 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4004 int saved = ins->sreg2;
4005 if (ins->sreg2 == ARM_LSW_REG) {
4006 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4009 if (ins->sreg1 != ARM_LSW_REG)
4010 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4011 if (saved != ARM_MSW_REG)
4012 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4017 ARM_MVFD (code, ins->dreg, ins->sreg1);
4018 #elif defined(ARM_FPU_VFP)
4019 ARM_CPYD (code, ins->dreg, ins->sreg1);
4022 case OP_FCONV_TO_R4:
4024 ARM_MVFS (code, ins->dreg, ins->sreg1);
4025 #elif defined(ARM_FPU_VFP)
4026 ARM_CVTD (code, ins->dreg, ins->sreg1);
4027 ARM_CVTS (code, ins->dreg, ins->dreg);
4032 * Keep in sync with mono_arch_emit_epilog
4034 g_assert (!cfg->method->save_lmf);
4036 code = emit_load_volatile_arguments (cfg, code);
4038 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4040 if (cfg->used_int_regs)
4041 ARM_POP (code, cfg->used_int_regs);
4042 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4044 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4046 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4047 if (cfg->compile_aot) {
4048 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4050 *(gpointer*)code = NULL;
4052 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4058 /* ensure ins->sreg1 is not NULL */
4059 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4062 g_assert (cfg->sig_cookie < 128);
4063 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4064 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4073 call = (MonoCallInst*)ins;
4074 if (ins->flags & MONO_INST_HAS_METHOD)
4075 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4077 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4078 code = emit_call_seq (cfg, code);
4079 code = emit_move_return_value (cfg, ins, code);
4085 case OP_VOIDCALL_REG:
4087 code = emit_call_reg (code, ins->sreg1);
4088 code = emit_move_return_value (cfg, ins, code);
4090 case OP_FCALL_MEMBASE:
4091 case OP_LCALL_MEMBASE:
4092 case OP_VCALL_MEMBASE:
4093 case OP_VCALL2_MEMBASE:
4094 case OP_VOIDCALL_MEMBASE:
4095 case OP_CALL_MEMBASE:
4096 g_assert (arm_is_imm12 (ins->inst_offset));
4097 g_assert (ins->sreg1 != ARMREG_LR);
4098 call = (MonoCallInst*)ins;
4099 if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE) {
4100 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
4101 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4103 * We can't embed the method in the code stream in PIC code, or
4105 * Instead, we put it in V5 in code emitted by
4106 * mono_arch_emit_imt_argument (), and embed NULL here to
4107 * signal the IMT thunk that the value is in V5.
4109 if (call->dynamic_imt_arg)
4110 *((gpointer*)code) = NULL;
4112 *((gpointer*)code) = (gpointer)call->method;
4115 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4116 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4118 code = emit_move_return_value (cfg, ins, code);
4121 /* keep alignment */
4122 int alloca_waste = cfg->param_area;
4125 /* round the size to 8 bytes */
4126 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
4127 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
4129 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
4130 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
4131 /* memzero the area: dreg holds the size, sp is the pointer */
4132 if (ins->flags & MONO_INST_INIT) {
4133 guint8 *start_loop, *branch_to_cond;
4134 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
4135 branch_to_cond = code;
4138 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
4139 arm_patch (branch_to_cond, code);
4140 /* decrement by 4 and set flags */
4141 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
4142 ARM_B_COND (code, ARMCOND_GE, 0);
4143 arm_patch (code - 4, start_loop);
4145 ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
4150 MonoInst *var = cfg->dyn_call_var;
4152 g_assert (var->opcode == OP_REGOFFSET);
4153 g_assert (arm_is_imm12 (var->inst_offset));
4155 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
4156 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
4158 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
4160 /* Save args buffer */
4161 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4163 /* Set stack slots using R0 as scratch reg */
4164 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
4165 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4166 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
4167 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4170 /* Set argument registers */
4171 for (i = 0; i < PARAM_REGS; ++i)
4172 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
4175 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4176 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4179 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
4180 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
4181 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
4185 if (ins->sreg1 != ARMREG_R0)
4186 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4187 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4188 (gpointer)"mono_arch_throw_exception");
4189 code = emit_call_seq (cfg, code);
4193 if (ins->sreg1 != ARMREG_R0)
4194 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4195 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4196 (gpointer)"mono_arch_rethrow_exception");
4197 code = emit_call_seq (cfg, code);
4200 case OP_START_HANDLER: {
4201 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4203 if (arm_is_imm12 (spvar->inst_offset)) {
4204 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4206 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4207 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
4211 case OP_ENDFILTER: {
4212 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4214 if (ins->sreg1 != ARMREG_R0)
4215 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4216 if (arm_is_imm12 (spvar->inst_offset)) {
4217 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4219 g_assert (ARMREG_IP != spvar->inst_basereg);
4220 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4221 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4223 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4226 case OP_ENDFINALLY: {
4227 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4229 if (arm_is_imm12 (spvar->inst_offset)) {
4230 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4232 g_assert (ARMREG_IP != spvar->inst_basereg);
4233 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4234 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4236 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4239 case OP_CALL_HANDLER:
4240 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4242 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4245 ins->inst_c0 = code - cfg->native_code;
4248 /*if (ins->inst_target_bb->native_offset) {
4250 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4252 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4257 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
4261 * In the normal case we have:
4262 * ldr pc, [pc, ins->sreg1 << 2]
4265 * ldr lr, [pc, ins->sreg1 << 2]
4267 * After follows the data.
4268 * FIXME: add aot support.
4270 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
4271 max_len += 4 * GPOINTER_TO_INT (ins->klass);
4272 if (offset + max_len > (cfg->code_size - 16)) {
4273 cfg->code_size += max_len;
4274 cfg->code_size *= 2;
4275 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4276 code = cfg->native_code + offset;
4278 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
4280 code += 4 * GPOINTER_TO_INT (ins->klass);
4284 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4285 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4289 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4290 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
4294 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4295 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
4299 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4300 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
4304 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4305 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
4307 case OP_COND_EXC_EQ:
4308 case OP_COND_EXC_NE_UN:
4309 case OP_COND_EXC_LT:
4310 case OP_COND_EXC_LT_UN:
4311 case OP_COND_EXC_GT:
4312 case OP_COND_EXC_GT_UN:
4313 case OP_COND_EXC_GE:
4314 case OP_COND_EXC_GE_UN:
4315 case OP_COND_EXC_LE:
4316 case OP_COND_EXC_LE_UN:
4317 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
4319 case OP_COND_EXC_IEQ:
4320 case OP_COND_EXC_INE_UN:
4321 case OP_COND_EXC_ILT:
4322 case OP_COND_EXC_ILT_UN:
4323 case OP_COND_EXC_IGT:
4324 case OP_COND_EXC_IGT_UN:
4325 case OP_COND_EXC_IGE:
4326 case OP_COND_EXC_IGE_UN:
4327 case OP_COND_EXC_ILE:
4328 case OP_COND_EXC_ILE_UN:
4329 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4332 case OP_COND_EXC_IC:
4333 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4335 case OP_COND_EXC_OV:
4336 case OP_COND_EXC_IOV:
4337 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4339 case OP_COND_EXC_NC:
4340 case OP_COND_EXC_INC:
4341 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4343 case OP_COND_EXC_NO:
4344 case OP_COND_EXC_INO:
4345 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4357 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4360 /* floating point opcodes */
4363 if (cfg->compile_aot) {
4364 ARM_LDFD (code, ins->dreg, ARMREG_PC, 0);
4366 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4368 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4371 /* FIXME: we can optimize the imm load by dealing with part of
4372 * the displacement in LDFD (aligning to 512).
4374 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4375 ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
4379 if (cfg->compile_aot) {
4380 ARM_LDFS (code, ins->dreg, ARMREG_PC, 0);
4382 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4385 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4386 ARM_LDFS (code, ins->dreg, ARMREG_LR, 0);
4389 case OP_STORER8_MEMBASE_REG:
4390 /* This is generated by the local regalloc pass which runs after the lowering pass */
4391 if (!arm_is_fpimm8 (ins->inst_offset)) {
4392 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4393 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4394 ARM_STFD (code, ins->sreg1, ARMREG_LR, 0);
4396 ARM_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4399 case OP_LOADR8_MEMBASE:
4400 /* This is generated by the local regalloc pass which runs after the lowering pass */
4401 if (!arm_is_fpimm8 (ins->inst_offset)) {
4402 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4403 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4404 ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
4406 ARM_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4409 case OP_STORER4_MEMBASE_REG:
4410 g_assert (arm_is_fpimm8 (ins->inst_offset));
4411 ARM_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4413 case OP_LOADR4_MEMBASE:
4414 g_assert (arm_is_fpimm8 (ins->inst_offset));
4415 ARM_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4417 case OP_ICONV_TO_R_UN: {
4419 tmpreg = ins->dreg == 0? 1: 0;
4420 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4421 ARM_FLTD (code, ins->dreg, ins->sreg1);
4422 ARM_B_COND (code, ARMCOND_GE, 8);
4423 /* save the temp register */
4424 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4425 ARM_STFD (code, tmpreg, ARMREG_SP, 0);
4426 ARM_LDFD (code, tmpreg, ARMREG_PC, 12);
4427 ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4428 ARM_LDFD (code, tmpreg, ARMREG_SP, 0);
4429 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4430 /* skip the constant pool */
4433 *(int*)code = 0x41f00000;
4438 * ldfltd ftemp, [pc, #8] 0x41f00000 0x00000000
4439 * adfltd fdest, fdest, ftemp
4443 case OP_ICONV_TO_R4:
4444 ARM_FLTS (code, ins->dreg, ins->sreg1);
4446 case OP_ICONV_TO_R8:
4447 ARM_FLTD (code, ins->dreg, ins->sreg1);
4450 #elif defined(ARM_FPU_VFP)
4453 if (cfg->compile_aot) {
4454 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4456 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4458 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4461 /* FIXME: we can optimize the imm load by dealing with part of
4462 * the displacement in LDFD (aligning to 512).
4464 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4465 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4469 if (cfg->compile_aot) {
4470 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4472 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4474 ARM_CVTS (code, ins->dreg, ins->dreg);
4476 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4477 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4478 ARM_CVTS (code, ins->dreg, ins->dreg);
4481 case OP_STORER8_MEMBASE_REG:
4482 /* This is generated by the local regalloc pass which runs after the lowering pass */
4483 if (!arm_is_fpimm8 (ins->inst_offset)) {
4484 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4485 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4486 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4488 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4491 case OP_LOADR8_MEMBASE:
4492 /* This is generated by the local regalloc pass which runs after the lowering pass */
4493 if (!arm_is_fpimm8 (ins->inst_offset)) {
4494 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4495 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4496 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4498 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4501 case OP_STORER4_MEMBASE_REG:
4502 g_assert (arm_is_fpimm8 (ins->inst_offset));
4503 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4504 ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4506 case OP_LOADR4_MEMBASE:
4507 g_assert (arm_is_fpimm8 (ins->inst_offset));
4508 ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4509 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4511 case OP_ICONV_TO_R_UN: {
4512 g_assert_not_reached ();
4515 case OP_ICONV_TO_R4:
4516 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4517 ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4518 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4520 case OP_ICONV_TO_R8:
4521 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4522 ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4526 if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4527 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4528 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4530 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4536 case OP_FCONV_TO_I1:
4537 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4539 case OP_FCONV_TO_U1:
4540 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4542 case OP_FCONV_TO_I2:
4543 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4545 case OP_FCONV_TO_U2:
4546 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4548 case OP_FCONV_TO_I4:
4550 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4552 case OP_FCONV_TO_U4:
4554 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4556 case OP_FCONV_TO_I8:
4557 case OP_FCONV_TO_U8:
4558 g_assert_not_reached ();
4559 /* Implemented as helper calls */
4561 case OP_LCONV_TO_R_UN:
4562 g_assert_not_reached ();
4563 /* Implemented as helper calls */
4565 case OP_LCONV_TO_OVF_I4_2: {
4566 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4568 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4571 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4572 high_bit_not_set = code;
4573 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4575 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4576 valid_negative = code;
4577 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4578 invalid_negative = code;
4579 ARM_B_COND (code, ARMCOND_AL, 0);
4581 arm_patch (high_bit_not_set, code);
4583 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4584 valid_positive = code;
4585 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4587 arm_patch (invalid_negative, code);
4588 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4590 arm_patch (valid_negative, code);
4591 arm_patch (valid_positive, code);
4593 if (ins->dreg != ins->sreg1)
4594 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4599 ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4602 ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4605 ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4608 ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4611 ARM_MNFD (code, ins->dreg, ins->sreg1);
4613 #elif defined(ARM_FPU_VFP)
4615 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4618 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4621 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4624 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4627 ARM_NEGD (code, ins->dreg, ins->sreg1);
4632 g_assert_not_reached ();
4636 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4637 #elif defined(ARM_FPU_VFP)
4638 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4644 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4645 #elif defined(ARM_FPU_VFP)
4646 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4649 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4650 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4654 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4655 #elif defined(ARM_FPU_VFP)
4656 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4659 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4660 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4664 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4665 #elif defined(ARM_FPU_VFP)
4666 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4669 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4670 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4671 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4676 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4677 #elif defined(ARM_FPU_VFP)
4678 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4681 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4682 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4687 ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4688 #elif defined(ARM_FPU_VFP)
4689 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4692 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4693 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4694 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4696 /* ARM FPA flags table:
4697 * N Less than ARMCOND_MI
4698 * Z Equal ARMCOND_EQ
4699 * C Greater Than or Equal ARMCOND_CS
4700 * V Unordered ARMCOND_VS
4703 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4706 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4709 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4712 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4713 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4719 g_assert_not_reached ();
4723 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4725 /* FPA requires EQ even thou the docs suggests that just CS is enough */
4726 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4727 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4731 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4732 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4737 if (ins->dreg != ins->sreg1)
4738 ARM_MVFD (code, ins->dreg, ins->sreg1);
4739 #elif defined(ARM_FPU_VFP)
4740 ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4741 ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4743 *(guint32*)code = 0xffffffff;
4745 *(guint32*)code = 0x7fefffff;
4747 ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4749 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4750 ARM_CMPD (code, ins->sreg1, ins->sreg1);
4752 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4754 ARM_CPYD (code, ins->dreg, ins->sreg1);
4759 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4760 g_assert_not_reached ();
4763 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4764 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4765 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4766 g_assert_not_reached ();
4772 last_offset = offset;
4775 cfg->code_len = code - cfg->native_code;
4778 #endif /* DISABLE_JIT */
4780 #ifdef HAVE_AEABI_READ_TP
4781 void __aeabi_read_tp (void);
4785 mono_arch_register_lowlevel_calls (void)
4787 /* The signature doesn't matter */
4788 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4789 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4791 #ifndef MONO_CROSS_COMPILE
4792 #ifdef HAVE_AEABI_READ_TP
4793 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4798 #define patch_lis_ori(ip,val) do {\
4799 guint16 *__lis_ori = (guint16*)(ip); \
4800 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
4801 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
4805 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4807 MonoJumpInfo *patch_info;
4808 gboolean compile_aot = !run_cctors;
4810 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4811 unsigned char *ip = patch_info->ip.i + code;
4812 const unsigned char *target;
4814 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4815 gpointer *jt = (gpointer*)(ip + 8);
4817 /* jt is the inlined jump table, 2 instructions after ip
4818 * In the normal case we store the absolute addresses,
4819 * otherwise the displacements.
4821 for (i = 0; i < patch_info->data.table->table_size; i++)
4822 jt [i] = code + (int)patch_info->data.table->table [i];
4825 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4828 switch (patch_info->type) {
4829 case MONO_PATCH_INFO_BB:
4830 case MONO_PATCH_INFO_LABEL:
4833 /* No need to patch these */
4838 switch (patch_info->type) {
4839 case MONO_PATCH_INFO_IP:
4840 g_assert_not_reached ();
4841 patch_lis_ori (ip, ip);
4843 case MONO_PATCH_INFO_METHOD_REL:
4844 g_assert_not_reached ();
4845 *((gpointer *)(ip)) = code + patch_info->data.offset;
4847 case MONO_PATCH_INFO_METHODCONST:
4848 case MONO_PATCH_INFO_CLASS:
4849 case MONO_PATCH_INFO_IMAGE:
4850 case MONO_PATCH_INFO_FIELD:
4851 case MONO_PATCH_INFO_VTABLE:
4852 case MONO_PATCH_INFO_IID:
4853 case MONO_PATCH_INFO_SFLDA:
4854 case MONO_PATCH_INFO_LDSTR:
4855 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4856 case MONO_PATCH_INFO_LDTOKEN:
4857 g_assert_not_reached ();
4858 /* from OP_AOTCONST : lis + ori */
4859 patch_lis_ori (ip, target);
4861 case MONO_PATCH_INFO_R4:
4862 case MONO_PATCH_INFO_R8:
4863 g_assert_not_reached ();
4864 *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4866 case MONO_PATCH_INFO_EXC_NAME:
4867 g_assert_not_reached ();
4868 *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4870 case MONO_PATCH_INFO_NONE:
4871 case MONO_PATCH_INFO_BB_OVF:
4872 case MONO_PATCH_INFO_EXC_OVF:
4873 /* everything is dealt with at epilog output time */
4878 arm_patch_general (domain, ip, target, dyn_code_mp);
4885 * Stack frame layout:
4887 * ------------------- fp
4888 * MonoLMF structure or saved registers
4889 * -------------------
4891 * -------------------
4893 * -------------------
4894 * optional 8 bytes for tracing
4895 * -------------------
4896 * param area size is cfg->param_area
4897 * ------------------- sp
4900 mono_arch_emit_prolog (MonoCompile *cfg)
4902 MonoMethod *method = cfg->method;
4904 MonoMethodSignature *sig;
4906 int alloc_size, pos, max_offset, i, rot_amount;
4911 int prev_sp_offset, reg_offset;
4913 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4916 sig = mono_method_signature (method);
4917 cfg->code_size = 256 + sig->param_count * 64;
4918 code = cfg->native_code = g_malloc (cfg->code_size);
4920 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
4922 alloc_size = cfg->stack_offset;
4926 if (!method->save_lmf) {
4929 * The iphone uses R7 as the frame pointer, and it points at the saved
4934 * We can't use r7 as a frame pointer since it points into the middle of
4935 * the frame, so we keep using our own frame pointer.
4936 * FIXME: Optimize this.
4939 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4940 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
4941 prev_sp_offset += 8; /* r7 and lr */
4942 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4943 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
4945 /* No need to push LR again */
4946 if (cfg->used_int_regs)
4947 ARM_PUSH (code, cfg->used_int_regs);
4949 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
4950 prev_sp_offset += 4;
4952 for (i = 0; i < 16; ++i) {
4953 if (cfg->used_int_regs & (1 << i))
4954 prev_sp_offset += 4;
4956 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4958 for (i = 0; i < 16; ++i) {
4959 if ((cfg->used_int_regs & (1 << i))) {
4960 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
4965 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
4967 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
4970 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
4971 ARM_PUSH (code, 0x5ff0);
4972 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
4973 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4975 for (i = 0; i < 16; ++i) {
4976 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
4977 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
4981 pos += sizeof (MonoLMF) - prev_sp_offset;
4985 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
4986 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
4987 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
4988 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
4991 /* the stack used in the pushed regs */
4992 if (prev_sp_offset & 4)
4994 cfg->stack_usage = alloc_size;
4996 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
4997 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4999 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
5000 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5002 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
5004 if (cfg->frame_reg != ARMREG_SP) {
5005 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
5006 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
5008 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
5009 prev_sp_offset += alloc_size;
5011 /* compute max_offset in order to use short forward jumps
5012 * we could skip do it on arm because the immediate displacement
5013 * for jumps is large enough, it may be useful later for constant pools
5016 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5017 MonoInst *ins = bb->code;
5018 bb->max_offset = max_offset;
5020 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5023 MONO_BB_FOR_EACH_INS (bb, ins)
5024 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5027 /* store runtime generic context */
5028 if (cfg->rgctx_var) {
5029 MonoInst *ins = cfg->rgctx_var;
5031 g_assert (ins->opcode == OP_REGOFFSET);
5033 if (arm_is_imm12 (ins->inst_offset)) {
5034 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
5036 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5037 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
5041 /* load arguments allocated to register from the stack */
5044 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
5046 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
5047 ArgInfo *ainfo = &cinfo->ret;
5048 inst = cfg->vret_addr;
5049 g_assert (arm_is_imm12 (inst->inst_offset));
5050 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5053 if (sig->call_convention == MONO_CALL_VARARG) {
5054 ArgInfo *cookie = &cinfo->sig_cookie;
5056 /* Save the sig cookie address */
5057 g_assert (cookie->storage == RegTypeBase);
5059 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
5060 g_assert (arm_is_imm12 (cfg->sig_cookie));
5061 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
5062 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5065 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5066 ArgInfo *ainfo = cinfo->args + i;
5067 inst = cfg->args [pos];
5069 if (cfg->verbose_level > 2)
5070 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
5071 if (inst->opcode == OP_REGVAR) {
5072 if (ainfo->storage == RegTypeGeneral)
5073 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
5074 else if (ainfo->storage == RegTypeFP) {
5075 g_assert_not_reached ();
5076 } else if (ainfo->storage == RegTypeBase) {
5077 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5078 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5080 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5081 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
5084 g_assert_not_reached ();
5086 if (cfg->verbose_level > 2)
5087 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5089 /* the argument should be put on the stack: FIXME handle size != word */
5090 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
5091 switch (ainfo->size) {
5093 if (arm_is_imm12 (inst->inst_offset))
5094 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5096 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5097 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5101 if (arm_is_imm8 (inst->inst_offset)) {
5102 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5104 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5105 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5109 g_assert (arm_is_imm12 (inst->inst_offset));
5110 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5111 g_assert (arm_is_imm12 (inst->inst_offset + 4));
5112 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
5115 if (arm_is_imm12 (inst->inst_offset)) {
5116 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5118 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5119 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5123 } else if (ainfo->storage == RegTypeBaseGen) {
5124 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
5125 g_assert (arm_is_imm12 (inst->inst_offset));
5126 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5127 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5128 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
5129 } else if (ainfo->storage == RegTypeBase) {
5130 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5131 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5133 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
5134 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5137 switch (ainfo->size) {
5139 if (arm_is_imm8 (inst->inst_offset)) {
5140 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5142 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5143 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5147 if (arm_is_imm8 (inst->inst_offset)) {
5148 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5150 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5151 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5155 if (arm_is_imm12 (inst->inst_offset)) {
5156 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5158 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5159 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5161 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
5162 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
5164 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
5165 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5167 if (arm_is_imm12 (inst->inst_offset + 4)) {
5168 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5170 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5171 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5175 if (arm_is_imm12 (inst->inst_offset)) {
5176 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5178 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5179 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5183 } else if (ainfo->storage == RegTypeFP) {
5184 g_assert_not_reached ();
5185 } else if (ainfo->storage == RegTypeStructByVal) {
5186 int doffset = inst->inst_offset;
5190 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
5191 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
5192 if (arm_is_imm12 (doffset)) {
5193 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
5195 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
5196 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
5198 soffset += sizeof (gpointer);
5199 doffset += sizeof (gpointer);
5201 if (ainfo->vtsize) {
5202 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5203 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
5204 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
5206 } else if (ainfo->storage == RegTypeStructByAddr) {
5207 g_assert_not_reached ();
5208 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5209 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
5211 g_assert_not_reached ();
5216 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5217 if (cfg->compile_aot)
5218 /* AOT code is only used in the root domain */
5219 code = mono_arm_emit_load_imm (code, ARMREG_R0, 0);
5221 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->domain);
5222 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5223 (gpointer)"mono_jit_thread_attach");
5224 code = emit_call_seq (cfg, code);
5227 if (method->save_lmf)
5228 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
5231 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5233 if (cfg->arch.seq_point_info_var) {
5234 MonoInst *ins = cfg->arch.seq_point_info_var;
5236 /* Initialize the variable from a GOT slot */
5237 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
5238 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5240 *(gpointer*)code = NULL;
5242 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
5244 g_assert (ins->opcode == OP_REGOFFSET);
5246 if (arm_is_imm12 (ins->inst_offset)) {
5247 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5249 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5250 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5254 /* Initialize ss_trigger_page_var */
5255 if (!cfg->soft_breakpoints) {
5256 MonoInst *info_var = cfg->arch.seq_point_info_var;
5257 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
5258 int dreg = ARMREG_LR;
5261 g_assert (info_var->opcode == OP_REGOFFSET);
5262 g_assert (arm_is_imm12 (info_var->inst_offset));
5264 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
5265 /* Load the trigger page addr */
5266 ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
5267 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
5271 if (cfg->arch.seq_point_read_var) {
5272 MonoInst *read_ins = cfg->arch.seq_point_read_var;
5273 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
5274 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
5276 g_assert (read_ins->opcode == OP_REGOFFSET);
5277 g_assert (arm_is_imm12 (read_ins->inst_offset));
5278 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
5279 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
5280 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
5281 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
5283 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5285 *(volatile int **)code = &ss_trigger_var;
5287 *(gpointer*)code = single_step_func_wrapper;
5289 *(gpointer*)code = breakpoint_func_wrapper;
5292 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
5293 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
5294 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
5295 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
5296 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
5297 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
5300 cfg->code_len = code - cfg->native_code;
5301 g_assert (cfg->code_len < cfg->code_size);
5308 mono_arch_emit_epilog (MonoCompile *cfg)
5310 MonoMethod *method = cfg->method;
5311 int pos, i, rot_amount;
5312 int max_epilog_size = 16 + 20*4;
5316 if (cfg->method->save_lmf)
5317 max_epilog_size += 128;
5319 if (mono_jit_trace_calls != NULL)
5320 max_epilog_size += 50;
5322 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5323 max_epilog_size += 50;
5325 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5326 cfg->code_size *= 2;
5327 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5328 cfg->stat_code_reallocs++;
5332 * Keep in sync with OP_JMP
5334 code = cfg->native_code + cfg->code_len;
5336 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5337 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5341 /* Load returned vtypes into registers if needed */
5342 cinfo = cfg->arch.cinfo;
5343 if (cinfo->ret.storage == RegTypeStructByVal) {
5344 MonoInst *ins = cfg->ret;
5346 if (arm_is_imm12 (ins->inst_offset)) {
5347 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5349 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5350 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5354 if (method->save_lmf) {
5355 int lmf_offset, reg, sp_adj, regmask;
5356 /* all but r0-r3, sp and pc */
5357 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5360 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
5362 /* This points to r4 inside MonoLMF->iregs */
5363 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5365 regmask = 0x9ff0; /* restore lr to pc */
5366 /* Skip caller saved registers not used by the method */
5367 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5368 regmask &= ~(1 << reg);
5372 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5373 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
5375 ARM_POP (code, regmask);
5377 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5378 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5380 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5381 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5385 /* Restore saved gregs */
5386 if (cfg->used_int_regs)
5387 ARM_POP (code, cfg->used_int_regs);
5388 /* Restore saved r7, restore LR to PC */
5389 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5391 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5395 cfg->code_len = code - cfg->native_code;
5397 g_assert (cfg->code_len < cfg->code_size);
5401 /* remove once throw_exception_by_name is eliminated */
5403 exception_id_by_name (const char *name)
5405 if (strcmp (name, "IndexOutOfRangeException") == 0)
5406 return MONO_EXC_INDEX_OUT_OF_RANGE;
5407 if (strcmp (name, "OverflowException") == 0)
5408 return MONO_EXC_OVERFLOW;
5409 if (strcmp (name, "ArithmeticException") == 0)
5410 return MONO_EXC_ARITHMETIC;
5411 if (strcmp (name, "DivideByZeroException") == 0)
5412 return MONO_EXC_DIVIDE_BY_ZERO;
5413 if (strcmp (name, "InvalidCastException") == 0)
5414 return MONO_EXC_INVALID_CAST;
5415 if (strcmp (name, "NullReferenceException") == 0)
5416 return MONO_EXC_NULL_REF;
5417 if (strcmp (name, "ArrayTypeMismatchException") == 0)
5418 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5419 if (strcmp (name, "ArgumentException") == 0)
5420 return MONO_EXC_ARGUMENT;
5421 g_error ("Unknown intrinsic exception %s\n", name);
5426 mono_arch_emit_exceptions (MonoCompile *cfg)
5428 MonoJumpInfo *patch_info;
5431 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5432 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5433 int max_epilog_size = 50;
5435 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5436 exc_throw_pos [i] = NULL;
5437 exc_throw_found [i] = 0;
5440 /* count the number of exception infos */
5443 * make sure we have enough space for exceptions
5445 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5446 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5447 i = exception_id_by_name (patch_info->data.target);
5448 if (!exc_throw_found [i]) {
5449 max_epilog_size += 32;
5450 exc_throw_found [i] = TRUE;
5455 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5456 cfg->code_size *= 2;
5457 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5458 cfg->stat_code_reallocs++;
5461 code = cfg->native_code + cfg->code_len;
5463 /* add code to raise exceptions */
5464 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5465 switch (patch_info->type) {
5466 case MONO_PATCH_INFO_EXC: {
5467 MonoClass *exc_class;
5468 unsigned char *ip = patch_info->ip.i + cfg->native_code;
5470 i = exception_id_by_name (patch_info->data.target);
5471 if (exc_throw_pos [i]) {
5472 arm_patch (ip, exc_throw_pos [i]);
5473 patch_info->type = MONO_PATCH_INFO_NONE;
5476 exc_throw_pos [i] = code;
5478 arm_patch (ip, code);
5480 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5481 g_assert (exc_class);
5483 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5484 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5485 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5486 patch_info->data.name = "mono_arch_throw_corlib_exception";
5487 patch_info->ip.i = code - cfg->native_code;
5489 *(guint32*)(gpointer)code = exc_class->type_token;
5499 cfg->code_len = code - cfg->native_code;
5501 g_assert (cfg->code_len < cfg->code_size);
5505 #endif /* #ifndef DISABLE_JIT */
5507 static gboolean tls_offset_inited = FALSE;
5510 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5512 if (!tls_offset_inited) {
5513 tls_offset_inited = TRUE;
5515 lmf_tls_offset = mono_get_lmf_tls_offset ();
5516 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5521 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5526 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5533 mono_arch_print_tree (MonoInst *tree, int arity)
5539 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5541 return mono_get_domain_intrinsic (cfg);
5545 mono_arch_get_patch_offset (guint8 *code)
5552 mono_arch_flush_register_windows (void)
5556 #ifdef MONO_ARCH_HAVE_IMT
5561 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5563 if (cfg->compile_aot) {
5564 int method_reg = mono_alloc_ireg (cfg);
5567 call->dynamic_imt_arg = TRUE;
5570 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5572 MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5573 ins->dreg = method_reg;
5574 ins->inst_p0 = call->method;
5575 ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5576 MONO_ADD_INS (cfg->cbb, ins);
5578 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5580 } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5582 /* Always pass in a register for simplicity */
5583 call->dynamic_imt_arg = TRUE;
5585 cfg->uses_rgctx_reg = TRUE;
5588 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5591 int method_reg = mono_alloc_preg (cfg);
5593 MONO_INST_NEW (cfg, ins, OP_PCONST);
5594 ins->inst_p0 = call->method;
5595 ins->dreg = method_reg;
5596 MONO_ADD_INS (cfg->cbb, ins);
5598 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5603 #endif /* DISABLE_JIT */
5606 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5608 guint32 *code_ptr = (guint32*)code;
5613 return (MonoMethod*)regs [ARMREG_V5];
5615 /* The IMT value is stored in the code stream right after the LDC instruction. */
5616 if (!IS_LDR_PC (code_ptr [0])) {
5617 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5618 g_assert (IS_LDR_PC (code_ptr [0]));
5620 if (code_ptr [1] == 0)
5621 /* This is AOTed code, the IMT method is in V5 */
5622 return (MonoMethod*)regs [ARMREG_V5];
5624 return (MonoMethod*) code_ptr [1];
5628 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5630 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5633 #define ENABLE_WRONG_METHOD_CHECK 0
5634 #define BASE_SIZE (6 * 4)
5635 #define BSEARCH_ENTRY_SIZE (4 * 4)
5636 #define CMP_SIZE (3 * 4)
5637 #define BRANCH_SIZE (1 * 4)
5638 #define CALL_SIZE (2 * 4)
5639 #define WMC_SIZE (5 * 4)
5640 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5643 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5645 guint32 delta = DISTANCE (target, code);
5647 g_assert (delta >= 0 && delta <= 0xFFF);
5648 *target = *target | delta;
5654 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5655 gpointer fail_tramp)
5657 int size, i, extra_space = 0;
5658 arminstr_t *code, *start, *vtable_target = NULL;
5659 gboolean large_offsets = FALSE;
5660 guint32 **constant_pool_starts;
5663 constant_pool_starts = g_new0 (guint32*, count);
5665 for (i = 0; i < count; ++i) {
5666 MonoIMTCheckItem *item = imt_entries [i];
5667 if (item->is_equals) {
5668 gboolean fail_case = !item->check_target_idx && fail_tramp;
5670 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5671 item->chunk_size += 32;
5672 large_offsets = TRUE;
5675 if (item->check_target_idx || fail_case) {
5676 if (!item->compare_done || fail_case)
5677 item->chunk_size += CMP_SIZE;
5678 item->chunk_size += BRANCH_SIZE;
5680 #if ENABLE_WRONG_METHOD_CHECK
5681 item->chunk_size += WMC_SIZE;
5685 item->chunk_size += 16;
5686 large_offsets = TRUE;
5688 item->chunk_size += CALL_SIZE;
5690 item->chunk_size += BSEARCH_ENTRY_SIZE;
5691 imt_entries [item->check_target_idx]->compare_done = TRUE;
5693 size += item->chunk_size;
5697 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5700 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5702 code = mono_domain_code_reserve (domain, size);
5706 printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5707 for (i = 0; i < count; ++i) {
5708 MonoIMTCheckItem *item = imt_entries [i];
5709 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5714 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5716 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5717 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5718 vtable_target = code;
5719 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5721 if (mono_use_llvm) {
5722 /* LLVM always passes the IMT method in R5 */
5723 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5725 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5726 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5727 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5730 for (i = 0; i < count; ++i) {
5731 MonoIMTCheckItem *item = imt_entries [i];
5732 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5733 gint32 vtable_offset;
5735 item->code_target = (guint8*)code;
5737 if (item->is_equals) {
5738 gboolean fail_case = !item->check_target_idx && fail_tramp;
5740 if (item->check_target_idx || fail_case) {
5741 if (!item->compare_done || fail_case) {
5743 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5744 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5746 item->jmp_code = (guint8*)code;
5747 ARM_B_COND (code, ARMCOND_NE, 0);
5749 /*Enable the commented code to assert on wrong method*/
5750 #if ENABLE_WRONG_METHOD_CHECK
5752 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5753 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5754 ARM_B_COND (code, ARMCOND_NE, 1);
5760 if (item->has_target_code) {
5761 target_code_ins = code;
5762 /* Load target address */
5763 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5764 /* Save it to the fourth slot */
5765 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5766 /* Restore registers and branch */
5767 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5769 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5771 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5772 if (!arm_is_imm12 (vtable_offset)) {
5774 * We need to branch to a computed address but we don't have
5775 * a free register to store it, since IP must contain the
5776 * vtable address. So we push the two values to the stack, and
5777 * load them both using LDM.
5779 /* Compute target address */
5780 vtable_offset_ins = code;
5781 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5782 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5783 /* Save it to the fourth slot */
5784 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5785 /* Restore registers and branch */
5786 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5788 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5790 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5792 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5793 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5798 arm_patch (item->jmp_code, (guchar*)code);
5800 target_code_ins = code;
5801 /* Load target address */
5802 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5803 /* Save it to the fourth slot */
5804 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5805 /* Restore registers and branch */
5806 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5808 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5809 item->jmp_code = NULL;
5813 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5815 /*must emit after unconditional branch*/
5816 if (vtable_target) {
5817 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5818 item->chunk_size += 4;
5819 vtable_target = NULL;
5822 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5823 constant_pool_starts [i] = code;
5825 code += extra_space;
5829 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5830 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5832 item->jmp_code = (guint8*)code;
5833 ARM_B_COND (code, ARMCOND_GE, 0);
5838 for (i = 0; i < count; ++i) {
5839 MonoIMTCheckItem *item = imt_entries [i];
5840 if (item->jmp_code) {
5841 if (item->check_target_idx)
5842 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5844 if (i > 0 && item->is_equals) {
5846 arminstr_t *space_start = constant_pool_starts [i];
5847 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5848 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5855 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5856 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5861 g_free (constant_pool_starts);
5863 mono_arch_flush_icache ((guint8*)start, size);
5864 mono_stats.imt_thunks_size += code - start;
5866 g_assert (DISTANCE (start, code) <= size);
5873 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5875 if (reg == ARMREG_SP)
5878 return ctx->regs [reg];
5882 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
5884 if (reg == ARMREG_SP)
5887 ctx->regs [reg] = val;
5891 * mono_arch_get_trampolines:
5893 * Return a list of MonoTrampInfo structures describing arch specific trampolines
5897 mono_arch_get_trampolines (gboolean aot)
5899 return mono_arm_get_exception_trampolines (aot);
5903 * mono_arch_set_breakpoint:
5905 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
5906 * The location should contain code emitted by OP_SEQ_POINT.
5909 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5912 guint32 native_offset = ip - (guint8*)ji->code_start;
5913 MonoDebugOptions *opt = mini_get_debug_options ();
5915 if (opt->soft_breakpoints) {
5916 g_assert (!ji->from_aot);
5918 ARM_BLX_REG (code, ARMREG_LR);
5919 mono_arch_flush_icache (code - 4, 4);
5920 } else if (ji->from_aot) {
5921 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5923 g_assert (native_offset % 4 == 0);
5924 g_assert (info->bp_addrs [native_offset / 4] == 0);
5925 info->bp_addrs [native_offset / 4] = bp_trigger_page;
5927 int dreg = ARMREG_LR;
5929 /* Read from another trigger page */
5930 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
5932 *(int*)code = (int)bp_trigger_page;
5934 ARM_LDR_IMM (code, dreg, dreg, 0);
5936 mono_arch_flush_icache (code - 16, 16);
5939 /* This is currently implemented by emitting an SWI instruction, which
5940 * qemu/linux seems to convert to a SIGILL.
5942 *(int*)code = (0xef << 24) | 8;
5944 mono_arch_flush_icache (code - 4, 4);
5950 * mono_arch_clear_breakpoint:
5952 * Clear the breakpoint at IP.
5955 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5957 MonoDebugOptions *opt = mini_get_debug_options ();
5961 if (opt->soft_breakpoints) {
5962 g_assert (!ji->from_aot);
5965 mono_arch_flush_icache (code - 4, 4);
5966 } else if (ji->from_aot) {
5967 guint32 native_offset = ip - (guint8*)ji->code_start;
5968 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5970 g_assert (native_offset % 4 == 0);
5971 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
5972 info->bp_addrs [native_offset / 4] = 0;
5974 for (i = 0; i < 4; ++i)
5977 mono_arch_flush_icache (ip, code - ip);
5982 * mono_arch_start_single_stepping:
5984 * Start single stepping.
5987 mono_arch_start_single_stepping (void)
5989 if (ss_trigger_page)
5990 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
5996 * mono_arch_stop_single_stepping:
5998 * Stop single stepping.
6001 mono_arch_stop_single_stepping (void)
6003 if (ss_trigger_page)
6004 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6010 #define DBG_SIGNAL SIGBUS
6012 #define DBG_SIGNAL SIGSEGV
6016 * mono_arch_is_single_step_event:
6018 * Return whenever the machine state in SIGCTX corresponds to a single
6022 mono_arch_is_single_step_event (void *info, void *sigctx)
6024 siginfo_t *sinfo = info;
6026 if (!ss_trigger_page)
6029 /* Sometimes the address is off by 4 */
6030 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
6037 * mono_arch_is_breakpoint_event:
6039 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
6042 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6044 siginfo_t *sinfo = info;
6046 if (!ss_trigger_page)
6049 if (sinfo->si_signo == DBG_SIGNAL) {
6050 /* Sometimes the address is off by 4 */
6051 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
6061 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
6063 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
6067 else if (mini_get_debug_options ()->soft_breakpoints)
6076 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
6078 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
6086 * mono_arch_skip_breakpoint:
6088 * See mini-amd64.c for docs.
6091 mono_arch_skip_breakpoint (MonoContext *ctx)
6093 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6097 * mono_arch_skip_single_step:
6099 * See mini-amd64.c for docs.
6102 mono_arch_skip_single_step (MonoContext *ctx)
6104 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6108 * mono_arch_get_seq_point_info:
6110 * See mini-amd64.c for docs.
6113 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6118 // FIXME: Add a free function
6120 mono_domain_lock (domain);
6121 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
6123 mono_domain_unlock (domain);
6126 ji = mono_jit_info_table_find (domain, (char*)code);
6129 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
6131 info->ss_trigger_page = ss_trigger_page;
6132 info->bp_trigger_page = bp_trigger_page;
6134 mono_domain_lock (domain);
6135 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
6137 mono_domain_unlock (domain);
6144 * mono_arch_set_target:
6146 * Set the target architecture the JIT backend should generate code for, in the form
6147 * of a GNU target triplet. Only used in AOT mode.
6150 mono_arch_set_target (char *mtriple)
6152 /* The GNU target triple format is not very well documented */
6153 if (strstr (mtriple, "armv7")) {
6154 v6_supported = TRUE;
6155 v7_supported = TRUE;
6157 if (strstr (mtriple, "armv6")) {
6158 v6_supported = TRUE;
6160 if (strstr (mtriple, "darwin")) {
6161 v5_supported = TRUE;
6162 thumb_supported = TRUE;
6166 if (strstr (mtriple, "gnueabi"))
6167 eabi_supported = TRUE;