mono/mini/mini-amd64.c

   1 /**
   2  * \file
   3  * AMD64 backend for the Mono code generator
   4  *
   5  * Based on mini-x86.c.
   6  *
   7  * Authors:
   8  *   Paolo Molaro (lupus@ximian.com)
   9  *   Dietmar Maurer (dietmar@ximian.com)
  10  *   Patrik Torstensson
  11  *   Zoltan Varga (vargaz@gmail.com)
  12  *   Johan Lorensson (lateralusx.github@gmail.com)
  13  *
  14  * (C) 2003 Ximian, Inc.
  15  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  16  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  17  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  18  */
  19 #include "mini.h"
  20 #include <string.h>
  21 #include <math.h>
  22 #include <assert.h>
  23 #ifdef HAVE_UNISTD_H
  24 #include <unistd.h>
  25 #endif
  26
  27 #include <mono/metadata/abi-details.h>
  28 #include <mono/metadata/appdomain.h>
  29 #include <mono/metadata/debug-helpers.h>
  30 #include <mono/metadata/threads.h>
  31 #include <mono/metadata/profiler-private.h>
  32 #include <mono/metadata/mono-debug.h>
  33 #include <mono/metadata/gc-internals.h>
  34 #include <mono/utils/mono-math.h>
  35 #include <mono/utils/mono-mmap.h>
  36 #include <mono/utils/mono-memory-model.h>
  37 #include <mono/utils/mono-tls.h>
  38 #include <mono/utils/mono-hwcap.h>
  39 #include <mono/utils/mono-threads.h>
  40
  41 #include "trace.h"
  42 #include "ir-emit.h"
  43 #include "mini-amd64.h"
  44 #include "cpu-amd64.h"
  45 #include "debugger-agent.h"
  46 #include "mini-gc.h"
  47
  48 #ifdef MONO_XEN_OPT
  49 static gboolean optimize_for_xen = TRUE;
  50 #else
  51 #define optimize_for_xen 0
  52 #endif
  53
  54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  55
  56 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  57
  58 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  59
  60 #ifdef TARGET_WIN32
  61 /* Under windows, the calling convention is never stdcall */
  62 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  63 #else
  64 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  65 #endif
  66
  67 /* This mutex protects architecture specific caches */
  68 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  69 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  70 static mono_mutex_t mini_arch_mutex;
  71
  72 /* The single step trampoline */
  73 static gpointer ss_trampoline;
  74
  75 /* The breakpoint trampoline */
  76 static gpointer bp_trampoline;
  77
  78 /* Offset between fp and the first argument in the callee */
  79 #define ARGS_OFFSET 16
  80 #define GP_SCRATCH_REG AMD64_R11
  81
  82 /*
  83  * AMD64 register usage:
  84  * - callee saved registers are used for global register allocation
  85  * - %r11 is used for materializing 64 bit constants in opcodes
  86  * - the rest is used for local allocation
  87  */
  88
  89 /*
  90  * Floating point comparison results:
  91  *                  ZF PF CF
  92  * A > B            0  0  0
  93  * A < B            0  0  1
  94  * A = B            1  0  0
  95  * A > B            0  0  0
  96  * UNORDERED        1  1  1
  97  */
  98
  99 const char*
 100 mono_arch_regname (int reg)
 101 {
 102         switch (reg) {
 103         case AMD64_RAX: return "%rax";
 104         case AMD64_RBX: return "%rbx";
 105         case AMD64_RCX: return "%rcx";
 106         case AMD64_RDX: return "%rdx";
 107         case AMD64_RSP: return "%rsp";
 108         case AMD64_RBP: return "%rbp";
 109         case AMD64_RDI: return "%rdi";
 110         case AMD64_RSI: return "%rsi";
 111         case AMD64_R8: return "%r8";
 112         case AMD64_R9: return "%r9";
 113         case AMD64_R10: return "%r10";
 114         case AMD64_R11: return "%r11";
 115         case AMD64_R12: return "%r12";
 116         case AMD64_R13: return "%r13";
 117         case AMD64_R14: return "%r14";
 118         case AMD64_R15: return "%r15";
 119         }
 120         return "unknown";
 121 }
 122
 123 static const char * packed_xmmregs [] = {
 124         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 125         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 126 };
 127
 128 static const char * single_xmmregs [] = {
 129         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 130         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 131 };
 132
 133 const char*
 134 mono_arch_fregname (int reg)
 135 {
 136         if (reg < AMD64_XMM_NREG)
 137                 return single_xmmregs [reg];
 138         else
 139                 return "unknown";
 140 }
 141
 142 const char *
 143 mono_arch_xregname (int reg)
 144 {
 145         if (reg < AMD64_XMM_NREG)
 146                 return packed_xmmregs [reg];
 147         else
 148                 return "unknown";
 149 }
 150
 151 static gboolean
 152 debug_omit_fp (void)
 153 {
 154 #if 0
 155         return mono_debug_count ();
 156 #else
 157         return TRUE;
 158 #endif
 159 }
 160
 161 static inline gboolean
 162 amd64_is_near_call (guint8 *code)
 163 {
 164         /* Skip REX */
 165         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 166                 code += 1;
 167
 168         return code [0] == 0xe8;
 169 }
 170
 171 static inline gboolean
 172 amd64_use_imm32 (gint64 val)
 173 {
 174         if (mini_get_debug_options()->single_imm_size)
 175                 return FALSE;
 176
 177         return amd64_is_imm32 (val);
 178 }
 179
 180 static void
 181 amd64_patch (unsigned char* code, gpointer target)
 182 {
 183         guint8 rex = 0;
 184
 185         /* Skip REX */
 186         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 187                 rex = code [0];
 188                 code += 1;
 189         }
 190
 191         if ((code [0] & 0xf8) == 0xb8) {
 192                 /* amd64_set_reg_template */
 193                 *(guint64*)(code + 1) = (guint64)target;
 194         }
 195         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 196                 /* mov 0(%rip), %dreg */
 197                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 198         }
 199         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 200                 /* call *<OFFSET>(%rip) */
 201                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 202         }
 203         else if (code [0] == 0xe8) {
 204                 /* call <DISP> */
 205                 gint64 disp = (guint8*)target - (guint8*)code;
 206                 g_assert (amd64_is_imm32 (disp));
 207                 x86_patch (code, (unsigned char*)target);
 208         }
 209         else
 210                 x86_patch (code, (unsigned char*)target);
 211 }
 212
 213 void
 214 mono_amd64_patch (unsigned char* code, gpointer target)
 215 {
 216         amd64_patch (code, target);
 217 }
 218
 219 #define DEBUG(a) if (cfg->verbose_level > 1) a
 220
 221 static void inline
 222 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 223 {
 224     ainfo->offset = *stack_size;
 225
 226     if (*gr >= PARAM_REGS) {
 227                 ainfo->storage = ArgOnStack;
 228                 ainfo->arg_size = sizeof (mgreg_t);
 229                 /* Since the same stack slot size is used for all arg */
 230                 /*  types, it needs to be big enough to hold them all */
 231                 (*stack_size) += sizeof(mgreg_t);
 232     }
 233     else {
 234                 ainfo->storage = ArgInIReg;
 235                 ainfo->reg = param_regs [*gr];
 236                 (*gr) ++;
 237     }
 238 }
 239
 240 static void inline
 241 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 242 {
 243     ainfo->offset = *stack_size;
 244
 245     if (*gr >= FLOAT_PARAM_REGS) {
 246                 ainfo->storage = ArgOnStack;
 247                 ainfo->arg_size = sizeof (mgreg_t);
 248                 /* Since the same stack slot size is used for both float */
 249                 /*  types, it needs to be big enough to hold them both */
 250                 (*stack_size) += sizeof(mgreg_t);
 251     }
 252     else {
 253                 /* A double register */
 254                 if (is_double)
 255                         ainfo->storage = ArgInDoubleSSEReg;
 256                 else
 257                         ainfo->storage = ArgInFloatSSEReg;
 258                 ainfo->reg = *gr;
 259                 (*gr) += 1;
 260     }
 261 }
 262
 263 typedef enum ArgumentClass {
 264         ARG_CLASS_NO_CLASS,
 265         ARG_CLASS_MEMORY,
 266         ARG_CLASS_INTEGER,
 267         ARG_CLASS_SSE
 268 } ArgumentClass;
 269
 270 static ArgumentClass
 271 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 272 {
 273         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 274         MonoType *ptype;
 275
 276         ptype = mini_get_underlying_type (type);
 277         switch (ptype->type) {
 278         case MONO_TYPE_I1:
 279         case MONO_TYPE_U1:
 280         case MONO_TYPE_I2:
 281         case MONO_TYPE_U2:
 282         case MONO_TYPE_I4:
 283         case MONO_TYPE_U4:
 284         case MONO_TYPE_I:
 285         case MONO_TYPE_U:
 286         case MONO_TYPE_OBJECT:
 287         case MONO_TYPE_PTR:
 288         case MONO_TYPE_FNPTR:
 289         case MONO_TYPE_I8:
 290         case MONO_TYPE_U8:
 291                 class2 = ARG_CLASS_INTEGER;
 292                 break;
 293         case MONO_TYPE_R4:
 294         case MONO_TYPE_R8:
 295 #ifdef TARGET_WIN32
 296                 class2 = ARG_CLASS_INTEGER;
 297 #else
 298                 class2 = ARG_CLASS_SSE;
 299 #endif
 300                 break;
 301
 302         case MONO_TYPE_TYPEDBYREF:
 303                 g_assert_not_reached ();
 304
 305         case MONO_TYPE_GENERICINST:
 306                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 307                         class2 = ARG_CLASS_INTEGER;
 308                         break;
 309                 }
 310                 /* fall through */
 311         case MONO_TYPE_VALUETYPE: {
 312                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 313                 int i;
 314
 315                 for (i = 0; i < info->num_fields; ++i) {
 316                         class2 = class1;
 317                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 318                 }
 319                 break;
 320         }
 321         default:
 322                 g_assert_not_reached ();
 323         }
 324
 325         /* Merge */
 326         if (class1 == class2)
 327                 ;
 328         else if (class1 == ARG_CLASS_NO_CLASS)
 329                 class1 = class2;
 330         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 331                 class1 = ARG_CLASS_MEMORY;
 332         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 333                 class1 = ARG_CLASS_INTEGER;
 334         else
 335                 class1 = ARG_CLASS_SSE;
 336
 337         return class1;
 338 }
 339
 340 typedef struct {
 341         MonoType *type;
 342         int size, offset;
 343 } StructFieldInfo;
 344
 345 /*
 346  * collect_field_info_nested:
 347  *
 348  *   Collect field info from KLASS recursively into FIELDS.
 349  */
 350 static void
 351 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
 352 {
 353         MonoMarshalType *info;
 354         int i;
 355
 356         if (pinvoke) {
 357                 info = mono_marshal_load_type_info (klass);
 358                 g_assert(info);
 359                 for (i = 0; i < info->num_fields; ++i) {
 360                         if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 361                                 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
 362                         } else {
 363                                 guint32 align;
 364                                 StructFieldInfo f;
 365
 366                                 f.type = info->fields [i].field->type;
 367                                 f.size = mono_marshal_type_size (info->fields [i].field->type,
 368                                                                                                                            info->fields [i].mspec,
 369                                                                                                                            &align, TRUE, unicode);
 370                                 f.offset = offset + info->fields [i].offset;
 371                                 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
 372                                         /* This can happen with .pack directives eg. 'fixed' arrays */
 373                                         if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
 374                                                 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
 375                                                 g_array_append_val (fields_array, f);
 376                                                 while (f.size + f.offset < info->native_size) {
 377                                                         f.offset += f.size;
 378                                                         g_array_append_val (fields_array, f);
 379                                                 }
 380                                         } else {
 381                                                 f.size = info->native_size - f.offset;
 382                                                 g_array_append_val (fields_array, f);
 383                                         }
 384                                 } else {
 385                                         g_array_append_val (fields_array, f);
 386                                 }
 387                         }
 388                 }
 389         } else {
 390                 gpointer iter;
 391                 MonoClassField *field;
 392
 393                 iter = NULL;
 394                 while ((field = mono_class_get_fields (klass, &iter))) {
 395                         if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
 396                                 continue;
 397                         if (MONO_TYPE_ISSTRUCT (field->type)) {
 398                                 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
 399                         } else {
 400                                 int align;
 401                                 StructFieldInfo f;
 402
 403                                 f.type = field->type;
 404                                 f.size = mono_type_size (field->type, &align);
 405                                 f.offset = field->offset - sizeof (MonoObject) + offset;
 406
 407                                 g_array_append_val (fields_array, f);
 408                         }
 409                 }
 410         }
 411 }
 412
 413 #ifdef TARGET_WIN32
 414
 415 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
 416 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
 417
 418 static gboolean
 419 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
 420 {
 421         gboolean result = FALSE;
 422
 423         assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
 424         assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
 425
 426         arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 427         arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
 428         arg_info->pair_size [0] = 0;
 429         arg_info->pair_size [1] = 0;
 430         arg_info->nregs = 0;
 431
 432         if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
 433                 /* Pass parameter in integer register. */
 434                 arg_info->pair_storage [0] = ArgInIReg;
 435                 arg_info->pair_regs [0] = int_regs [*current_int_reg];
 436                 (*current_int_reg) ++;
 437                 result = TRUE;
 438         } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
 439                 /* Pass parameter in float register. */
 440                 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
 441                 arg_info->pair_regs [0] = float_regs [*current_float_reg];
 442                 (*current_float_reg) ++;
 443                 result = TRUE;
 444         }
 445
 446         if (result == TRUE) {
 447                 arg_info->pair_size [0] = arg_size;
 448                 arg_info->nregs = 1;
 449         }
 450
 451         return result;
 452 }
 453
 454 static inline gboolean
 455 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 456 {
 457         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
 458 }
 459
 460 static inline gboolean
 461 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 462 {
 463         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
 464 }
 465
 466 static void
 467 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
 468                                                                           guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 469 {
 470         /* Windows x64 value type ABI.
 471         *
 472         * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
 473         *
 474         * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
 475         *    Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
 476         * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 477         *    Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
 478         *
 479         * Return values:  https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
 480         *
 481         * Integers/Float types smaller than or equal to 8 bytes
 482         *    Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
 483         * Properly sized struct/unions (1,2,4,8)
 484         *    Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
 485         * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 486         *    Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
 487         */
 488
 489         assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 490
 491         if (!is_return) {
 492
 493                 /* Parameter cases. */
 494                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 495                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 496
 497                         /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
 498                         arg_info->storage = ArgValuetypeInReg;
 499                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 500                                 /* No more registers, fallback passing parameter on stack as value. */
 501                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 502
 503                                 /* Passing value directly on stack, so use size of value. */
 504                                 arg_info->storage = ArgOnStack;
 505                                 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 506                                 arg_info->offset = *stack_size;
 507                                 arg_info->arg_size = arg_size;
 508                                 *stack_size += arg_size;
 509                         }
 510                 } else {
 511                         /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
 512                         arg_info->storage = ArgValuetypeAddrInIReg;
 513                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 514                                 /* No more registers, fallback passing address to parameter on stack. */
 515                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 516
 517                                 /* Passing an address to value on stack, so use size of register as argument size. */
 518                                 arg_info->storage = ArgValuetypeAddrOnStack;
 519                                 arg_size = sizeof (mgreg_t);
 520                                 arg_info->offset = *stack_size;
 521                                 arg_info->arg_size = arg_size;
 522                                 *stack_size += arg_size;
 523                         }
 524                 }
 525         } else {
 526                 /* Return value cases. */
 527                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 528                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 529
 530                         /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
 531                         arg_info->storage = ArgValuetypeInReg;
 532                         allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 533
 534                         /* Only RAX/XMM0 should be used to return valuetype. */
 535                         assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
 536                 } else {
 537                         /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
 538                         arg_info->storage = ArgValuetypeAddrInIReg;
 539                         allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 540
 541                         /* Only RAX should be used to return valuetype address. */
 542                         assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
 543
 544                         arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 545                         arg_info->offset = *stack_size;
 546                         *stack_size += arg_size;
 547                 }
 548         }
 549 }
 550
 551 static void
 552 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
 553 {
 554         *arg_size = 0;
 555         *arg_class = ARG_CLASS_NO_CLASS;
 556
 557         assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
 558
 559         if (pinvoke) {
 560                 /* Calculate argument class type and size of marshalled type. */
 561                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 562                 *arg_size = info->native_size;
 563         } else {
 564                 /* Calculate argument class type and size of managed type. */
 565                 *arg_size = mono_class_value_size (klass, NULL);
 566         }
 567
 568         /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
 569         *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
 570
 571         if (*arg_class == ARG_CLASS_MEMORY) {
 572                 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
 573                 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
 574         }
 575
 576         /*
 577         * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
 578         * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
 579         * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
 580         * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
 581         * it must be represented in call and cannot be dropped.
 582         */
 583         if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
 584                 arg_info->pass_empty_struct = TRUE;
 585                 *arg_size = SIZEOF_REGISTER;
 586                 *arg_class = ARG_CLASS_INTEGER;
 587         }
 588
 589         assert (*arg_class != ARG_CLASS_NO_CLASS);
 590 }
 591
 592 static void
 593 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
 594                                                 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 595 {
 596         guint32 arg_size = SIZEOF_REGISTER;
 597         MonoClass *klass = NULL;
 598         ArgumentClass arg_class;
 599
 600         assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 601
 602         klass = mono_class_from_mono_type (type);
 603         get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
 604
 605         /* Only drop value type if its not an empty struct as input that must be represented in call */
 606         if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
 607                 arg_info->storage = ArgValuetypeInReg;
 608                 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 609         } else {
 610                 /* Alocate storage for value type. */
 611                 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
 612         }
 613 }
 614
 615 #endif /* TARGET_WIN32 */
 616
 617 static void
 618 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 619                            gboolean is_return,
 620                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 621 {
 622 #ifdef TARGET_WIN32
 623         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 624 #else
 625         guint32 size, quad, nquads, i, nfields;
 626         /* Keep track of the size used in each quad so we can */
 627         /* use the right size when copying args/return vars.  */
 628         guint32 quadsize [2] = {8, 8};
 629         ArgumentClass args [2];
 630         StructFieldInfo *fields = NULL;
 631         GArray *fields_array;
 632         MonoClass *klass;
 633         gboolean pass_on_stack = FALSE;
 634         int struct_size;
 635
 636         klass = mono_class_from_mono_type (type);
 637         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 638
 639         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 640                 /* We pass and return vtypes of size 8 in a register */
 641         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 642                 pass_on_stack = TRUE;
 643         }
 644
 645         /* If this struct can't be split up naturally into 8-byte */
 646         /* chunks (registers), pass it on the stack.              */
 647         if (sig->pinvoke) {
 648                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 649                 g_assert (info);
 650                 struct_size = info->native_size;
 651         } else {
 652                 struct_size = mono_class_value_size (klass, NULL);
 653         }
 654         /*
 655          * Collect field information recursively to be able to
 656          * handle nested structures.
 657          */
 658         fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
 659         collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
 660         fields = (StructFieldInfo*)fields_array->data;
 661         nfields = fields_array->len;
 662
 663         for (i = 0; i < nfields; ++i) {
 664                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 665                         pass_on_stack = TRUE;
 666                         break;
 667                 }
 668         }
 669
 670         if (size == 0) {
 671                 ainfo->storage = ArgValuetypeInReg;
 672                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 673                 return;
 674         }
 675
 676         if (pass_on_stack) {
 677                 /* Allways pass in memory */
 678                 ainfo->offset = *stack_size;
 679                 *stack_size += ALIGN_TO (size, 8);
 680                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 681                 if (!is_return)
 682                         ainfo->arg_size = ALIGN_TO (size, 8);
 683
 684                 g_array_free (fields_array, TRUE);
 685                 return;
 686         }
 687
 688         if (size > 8)
 689                 nquads = 2;
 690         else
 691                 nquads = 1;
 692
 693         if (!sig->pinvoke) {
 694                 int n = mono_class_value_size (klass, NULL);
 695
 696                 quadsize [0] = n >= 8 ? 8 : n;
 697                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 698
 699                 /* Always pass in 1 or 2 integer registers */
 700                 args [0] = ARG_CLASS_INTEGER;
 701                 args [1] = ARG_CLASS_INTEGER;
 702                 /* Only the simplest cases are supported */
 703                 if (is_return && nquads != 1) {
 704                         args [0] = ARG_CLASS_MEMORY;
 705                         args [1] = ARG_CLASS_MEMORY;
 706                 }
 707         } else {
 708                 /*
 709                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 710                  * The X87 and SSEUP stuff is left out since there are no such types in
 711                  * the CLR.
 712                  */
 713                 if (!nfields) {
 714                         ainfo->storage = ArgValuetypeInReg;
 715                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 716                         return;
 717                 }
 718
 719                 if (struct_size > 16) {
 720                         ainfo->offset = *stack_size;
 721                         *stack_size += ALIGN_TO (struct_size, 8);
 722                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 723                         if (!is_return)
 724                                 ainfo->arg_size = ALIGN_TO (struct_size, 8);
 725
 726                         g_array_free (fields_array, TRUE);
 727                         return;
 728                 }
 729
 730                 args [0] = ARG_CLASS_NO_CLASS;
 731                 args [1] = ARG_CLASS_NO_CLASS;
 732                 for (quad = 0; quad < nquads; ++quad) {
 733                         ArgumentClass class1;
 734
 735                         if (nfields == 0)
 736                                 class1 = ARG_CLASS_MEMORY;
 737                         else
 738                                 class1 = ARG_CLASS_NO_CLASS;
 739                         for (i = 0; i < nfields; ++i) {
 740                                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 741                                         /* Unaligned field */
 742                                         NOT_IMPLEMENTED;
 743                                 }
 744
 745                                 /* Skip fields in other quad */
 746                                 if ((quad == 0) && (fields [i].offset >= 8))
 747                                         continue;
 748                                 if ((quad == 1) && (fields [i].offset < 8))
 749                                         continue;
 750
 751                                 /* How far into this quad this data extends.*/
 752                                 /* (8 is size of quad) */
 753                                 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
 754
 755                                 class1 = merge_argument_class_from_type (fields [i].type, class1);
 756                         }
 757                         /* Empty structs have a nonzero size, causing this assert to be hit */
 758                         if (sig->pinvoke)
 759                                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 760                         args [quad] = class1;
 761                 }
 762         }
 763
 764         g_array_free (fields_array, TRUE);
 765
 766         /* Post merger cleanup */
 767         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 768                 args [0] = args [1] = ARG_CLASS_MEMORY;
 769
 770         /* Allocate registers */
 771         {
 772                 int orig_gr = *gr;
 773                 int orig_fr = *fr;
 774
 775                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 776                         quadsize [0] ++;
 777                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 778                         quadsize [1] ++;
 779
 780                 ainfo->storage = ArgValuetypeInReg;
 781                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 782                 g_assert (quadsize [0] <= 8);
 783                 g_assert (quadsize [1] <= 8);
 784                 ainfo->pair_size [0] = quadsize [0];
 785                 ainfo->pair_size [1] = quadsize [1];
 786                 ainfo->nregs = nquads;
 787                 for (quad = 0; quad < nquads; ++quad) {
 788                         switch (args [quad]) {
 789                         case ARG_CLASS_INTEGER:
 790                                 if (*gr >= PARAM_REGS)
 791                                         args [quad] = ARG_CLASS_MEMORY;
 792                                 else {
 793                                         ainfo->pair_storage [quad] = ArgInIReg;
 794                                         if (is_return)
 795                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 796                                         else
 797                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 798                                         (*gr) ++;
 799                                 }
 800                                 break;
 801                         case ARG_CLASS_SSE:
 802                                 if (*fr >= FLOAT_PARAM_REGS)
 803                                         args [quad] = ARG_CLASS_MEMORY;
 804                                 else {
 805                                         if (quadsize[quad] <= 4)
 806                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 807                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 808                                         ainfo->pair_regs [quad] = *fr;
 809                                         (*fr) ++;
 810                                 }
 811                                 break;
 812                         case ARG_CLASS_MEMORY:
 813                                 break;
 814                         case ARG_CLASS_NO_CLASS:
 815                                 break;
 816                         default:
 817                                 g_assert_not_reached ();
 818                         }
 819                 }
 820
 821                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 822                         int arg_size;
 823                         /* Revert possible register assignments */
 824                         *gr = orig_gr;
 825                         *fr = orig_fr;
 826
 827                         ainfo->offset = *stack_size;
 828                         if (sig->pinvoke)
 829                                 arg_size = ALIGN_TO (struct_size, 8);
 830                         else
 831                                 arg_size = nquads * sizeof(mgreg_t);
 832                         *stack_size += arg_size;
 833                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 834                         if (!is_return)
 835                                 ainfo->arg_size = arg_size;
 836                 }
 837         }
 838 #endif /* !TARGET_WIN32 */
 839 }
 840
 841 /*
 842  * get_call_info:
 843  *
 844  * Obtain information about a call according to the calling convention.
 845  * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
 846  * Draft Version 0.23" document for more information.
 847  * For AMD64 Windows, see "Overview of x64 Calling Conventions",
 848  * https://msdn.microsoft.com/en-us/library/ms235286.aspx
 849  */
 850 static CallInfo*
 851 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 852 {
 853         guint32 i, gr, fr, pstart;
 854         MonoType *ret_type;
 855         int n = sig->hasthis + sig->param_count;
 856         guint32 stack_size = 0;
 857         CallInfo *cinfo;
 858         gboolean is_pinvoke = sig->pinvoke;
 859
 860         if (mp)
 861                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 862         else
 863                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 864
 865         cinfo->nargs = n;
 866         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 867
 868         gr = 0;
 869         fr = 0;
 870
 871 #ifdef TARGET_WIN32
 872         /* Reserve space where the callee can save the argument registers */
 873         stack_size = 4 * sizeof (mgreg_t);
 874 #endif
 875
 876         /* return value */
 877         ret_type = mini_get_underlying_type (sig->ret);
 878         switch (ret_type->type) {
 879         case MONO_TYPE_I1:
 880         case MONO_TYPE_U1:
 881         case MONO_TYPE_I2:
 882         case MONO_TYPE_U2:
 883         case MONO_TYPE_I4:
 884         case MONO_TYPE_U4:
 885         case MONO_TYPE_I:
 886         case MONO_TYPE_U:
 887         case MONO_TYPE_PTR:
 888         case MONO_TYPE_FNPTR:
 889         case MONO_TYPE_OBJECT:
 890                 cinfo->ret.storage = ArgInIReg;
 891                 cinfo->ret.reg = AMD64_RAX;
 892                 break;
 893         case MONO_TYPE_U8:
 894         case MONO_TYPE_I8:
 895                 cinfo->ret.storage = ArgInIReg;
 896                 cinfo->ret.reg = AMD64_RAX;
 897                 break;
 898         case MONO_TYPE_R4:
 899                 cinfo->ret.storage = ArgInFloatSSEReg;
 900                 cinfo->ret.reg = AMD64_XMM0;
 901                 break;
 902         case MONO_TYPE_R8:
 903                 cinfo->ret.storage = ArgInDoubleSSEReg;
 904                 cinfo->ret.reg = AMD64_XMM0;
 905                 break;
 906         case MONO_TYPE_GENERICINST:
 907                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 908                         cinfo->ret.storage = ArgInIReg;
 909                         cinfo->ret.reg = AMD64_RAX;
 910                         break;
 911                 }
 912                 if (mini_is_gsharedvt_type (ret_type)) {
 913                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 914                         break;
 915                 }
 916                 /* fall through */
 917         case MONO_TYPE_VALUETYPE:
 918         case MONO_TYPE_TYPEDBYREF: {
 919                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 920
 921                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 922                 g_assert (cinfo->ret.storage != ArgInIReg);
 923                 break;
 924         }
 925         case MONO_TYPE_VAR:
 926         case MONO_TYPE_MVAR:
 927                 g_assert (mini_is_gsharedvt_type (ret_type));
 928                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 929                 break;
 930         case MONO_TYPE_VOID:
 931                 break;
 932         default:
 933                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 934         }
 935
 936         pstart = 0;
 937         /*
 938          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 939          * the first argument, allowing 'this' to be always passed in the first arg reg.
 940          * Also do this if the first argument is a reference type, since virtual calls
 941          * are sometimes made using calli without sig->hasthis set, like in the delegate
 942          * invoke wrappers.
 943          */
 944         ArgStorage ret_storage = cinfo->ret.storage;
 945         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 946                 if (sig->hasthis) {
 947                         add_general (&gr, &stack_size, cinfo->args + 0);
 948                 } else {
 949                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 950                         pstart = 1;
 951                 }
 952                 add_general (&gr, &stack_size, &cinfo->ret);
 953                 cinfo->ret.storage = ret_storage;
 954                 cinfo->vret_arg_index = 1;
 955         } else {
 956                 /* this */
 957                 if (sig->hasthis)
 958                         add_general (&gr, &stack_size, cinfo->args + 0);
 959
 960                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 961                         add_general (&gr, &stack_size, &cinfo->ret);
 962                         cinfo->ret.storage = ret_storage;
 963                 }
 964         }
 965
 966         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 967                 gr = PARAM_REGS;
 968                 fr = FLOAT_PARAM_REGS;
 969
 970                 /* Emit the signature cookie just before the implicit arguments */
 971                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 972         }
 973
 974         for (i = pstart; i < sig->param_count; ++i) {
 975                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 976                 MonoType *ptype;
 977
 978 #ifdef TARGET_WIN32
 979                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 980                 if (gr > fr)
 981                         fr = gr;
 982                 else if (fr > gr)
 983                         gr = fr;
 984 #endif
 985
 986                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 987                         /* We allways pass the sig cookie on the stack for simplicity */
 988                         /*
 989                          * Prevent implicit arguments + the sig cookie from being passed
 990                          * in registers.
 991                          */
 992                         gr = PARAM_REGS;
 993                         fr = FLOAT_PARAM_REGS;
 994
 995                         /* Emit the signature cookie just before the implicit arguments */
 996                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 997                 }
 998
 999                 ptype = mini_get_underlying_type (sig->params [i]);
1000                 switch (ptype->type) {
1001                 case MONO_TYPE_I1:
1002                 case MONO_TYPE_U1:
1003                         add_general (&gr, &stack_size, ainfo);
1004                         ainfo->byte_arg_size = 1;
1005                         break;
1006                 case MONO_TYPE_I2:
1007                 case MONO_TYPE_U2:
1008                         add_general (&gr, &stack_size, ainfo);
1009                         ainfo->byte_arg_size = 2;
1010                         break;
1011                 case MONO_TYPE_I4:
1012                 case MONO_TYPE_U4:
1013                         add_general (&gr, &stack_size, ainfo);
1014                         ainfo->byte_arg_size = 4;
1015                         break;
1016                 case MONO_TYPE_I:
1017                 case MONO_TYPE_U:
1018                 case MONO_TYPE_PTR:
1019                 case MONO_TYPE_FNPTR:
1020                 case MONO_TYPE_OBJECT:
1021                         add_general (&gr, &stack_size, ainfo);
1022                         break;
1023                 case MONO_TYPE_GENERICINST:
1024                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1025                                 add_general (&gr, &stack_size, ainfo);
1026                                 break;
1027                         }
1028                         if (mini_is_gsharedvt_variable_type (ptype)) {
1029                                 /* gsharedvt arguments are passed by ref */
1030                                 add_general (&gr, &stack_size, ainfo);
1031                                 if (ainfo->storage == ArgInIReg)
1032                                         ainfo->storage = ArgGSharedVtInReg;
1033                                 else
1034                                         ainfo->storage = ArgGSharedVtOnStack;
1035                                 break;
1036                         }
1037                         /* fall through */
1038                 case MONO_TYPE_VALUETYPE:
1039                 case MONO_TYPE_TYPEDBYREF:
1040                         add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1041                         break;
1042                 case MONO_TYPE_U8:
1043
1044                 case MONO_TYPE_I8:
1045                         add_general (&gr, &stack_size, ainfo);
1046                         break;
1047                 case MONO_TYPE_R4:
1048                         add_float (&fr, &stack_size, ainfo, FALSE);
1049                         break;
1050                 case MONO_TYPE_R8:
1051                         add_float (&fr, &stack_size, ainfo, TRUE);
1052                         break;
1053                 case MONO_TYPE_VAR:
1054                 case MONO_TYPE_MVAR:
1055                         /* gsharedvt arguments are passed by ref */
1056                         g_assert (mini_is_gsharedvt_type (ptype));
1057                         add_general (&gr, &stack_size, ainfo);
1058                         if (ainfo->storage == ArgInIReg)
1059                                 ainfo->storage = ArgGSharedVtInReg;
1060                         else
1061                                 ainfo->storage = ArgGSharedVtOnStack;
1062                         break;
1063                 default:
1064                         g_assert_not_reached ();
1065                 }
1066         }
1067
1068         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1069                 gr = PARAM_REGS;
1070                 fr = FLOAT_PARAM_REGS;
1071
1072                 /* Emit the signature cookie just before the implicit arguments */
1073                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1074         }
1075
1076         cinfo->stack_usage = stack_size;
1077         cinfo->reg_usage = gr;
1078         cinfo->freg_usage = fr;
1079         return cinfo;
1080 }
1081
1082 /*
1083  * mono_arch_get_argument_info:
1084  * @csig:  a method signature
1085  * @param_count: the number of parameters to consider
1086  * @arg_info: an array to store the result infos
1087  *
1088  * Gathers information on parameters such as size, alignment and
1089  * padding. arg_info should be large enought to hold param_count + 1 entries.
1090  *
1091  * Returns the size of the argument area on the stack.
1092  */
1093 int
1094 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1095 {
1096         int k;
1097         CallInfo *cinfo = get_call_info (NULL, csig);
1098         guint32 args_size = cinfo->stack_usage;
1099
1100         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1101         if (csig->hasthis) {
1102                 arg_info [0].offset = 0;
1103         }
1104
1105         for (k = 0; k < param_count; k++) {
1106                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1107                 /* FIXME: */
1108                 arg_info [k + 1].size = 0;
1109         }
1110
1111         g_free (cinfo);
1112
1113         return args_size;
1114 }
1115
1116 gboolean
1117 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1118 {
1119         CallInfo *c1, *c2;
1120         gboolean res;
1121         MonoType *callee_ret;
1122
1123         c1 = get_call_info (NULL, caller_sig);
1124         c2 = get_call_info (NULL, callee_sig);
1125         res = c1->stack_usage >= c2->stack_usage;
1126         callee_ret = mini_get_underlying_type (callee_sig->ret);
1127         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1128                 /* An address on the callee's stack is passed as the first argument */
1129                 res = FALSE;
1130
1131         g_free (c1);
1132         g_free (c2);
1133
1134         return res;
1135 }
1136
1137 /*
1138  * Initialize the cpu to execute managed code.
1139  */
1140 void
1141 mono_arch_cpu_init (void)
1142 {
1143 #ifndef _MSC_VER
1144         guint16 fpcw;
1145
1146         /* spec compliance requires running with double precision */
1147         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1148         fpcw &= ~X86_FPCW_PRECC_MASK;
1149         fpcw |= X86_FPCW_PREC_DOUBLE;
1150         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1151         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1152 #else
1153         /* TODO: This is crashing on Win64 right now.
1154         * _control87 (_PC_53, MCW_PC);
1155         */
1156 #endif
1157 }
1158
1159 /*
1160  * Initialize architecture specific code.
1161  */
1162 void
1163 mono_arch_init (void)
1164 {
1165         mono_os_mutex_init_recursive (&mini_arch_mutex);
1166
1167         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1168         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1169         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1170         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1171         mono_aot_register_jit_icall ("mono_amd64_handler_block_trampoline_helper", mono_amd64_handler_block_trampoline_helper);
1172
1173 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1174         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1175 #endif
1176
1177         if (!mono_aot_only)
1178                 bp_trampoline = mini_get_breakpoint_trampoline ();
1179 }
1180
1181 /*
1182  * Cleanup architecture specific code.
1183  */
1184 void
1185 mono_arch_cleanup (void)
1186 {
1187         mono_os_mutex_destroy (&mini_arch_mutex);
1188 }
1189
1190 /*
1191  * This function returns the optimizations supported on this cpu.
1192  */
1193 guint32
1194 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1195 {
1196         guint32 opts = 0;
1197
1198         *exclude_mask = 0;
1199
1200         if (mono_hwcap_x86_has_cmov) {
1201                 opts |= MONO_OPT_CMOV;
1202
1203                 if (mono_hwcap_x86_has_fcmov)
1204                         opts |= MONO_OPT_FCMOV;
1205                 else
1206                         *exclude_mask |= MONO_OPT_FCMOV;
1207         } else {
1208                 *exclude_mask |= MONO_OPT_CMOV;
1209         }
1210
1211 #ifdef TARGET_WIN32
1212         /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1213         /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1214         /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1215         /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1216         /* will now have a reference to an argument that won't be fully decomposed. */
1217         *exclude_mask |= MONO_OPT_SIMD;
1218 #endif
1219
1220         return opts;
1221 }
1222
1223 /*
1224  * This function test for all SSE functions supported.
1225  *
1226  * Returns a bitmask corresponding to all supported versions.
1227  *
1228  */
1229 guint32
1230 mono_arch_cpu_enumerate_simd_versions (void)
1231 {
1232         guint32 sse_opts = 0;
1233
1234         if (mono_hwcap_x86_has_sse1)
1235                 sse_opts |= SIMD_VERSION_SSE1;
1236
1237         if (mono_hwcap_x86_has_sse2)
1238                 sse_opts |= SIMD_VERSION_SSE2;
1239
1240         if (mono_hwcap_x86_has_sse3)
1241                 sse_opts |= SIMD_VERSION_SSE3;
1242
1243         if (mono_hwcap_x86_has_ssse3)
1244                 sse_opts |= SIMD_VERSION_SSSE3;
1245
1246         if (mono_hwcap_x86_has_sse41)
1247                 sse_opts |= SIMD_VERSION_SSE41;
1248
1249         if (mono_hwcap_x86_has_sse42)
1250                 sse_opts |= SIMD_VERSION_SSE42;
1251
1252         if (mono_hwcap_x86_has_sse4a)
1253                 sse_opts |= SIMD_VERSION_SSE4a;
1254
1255         return sse_opts;
1256 }
1257
1258 #ifndef DISABLE_JIT
1259
1260 GList *
1261 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1262 {
1263         GList *vars = NULL;
1264         int i;
1265
1266         for (i = 0; i < cfg->num_varinfo; i++) {
1267                 MonoInst *ins = cfg->varinfo [i];
1268                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1269
1270                 /* unused vars */
1271                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1272                         continue;
1273
1274                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1275                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1276                         continue;
1277
1278                 if (mono_is_regsize_var (ins->inst_vtype)) {
1279                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1280                         g_assert (i == vmv->idx);
1281                         vars = g_list_prepend (vars, vmv);
1282                 }
1283         }
1284
1285         vars = mono_varlist_sort (cfg, vars, 0);
1286
1287         return vars;
1288 }
1289
1290 /**
1291  * mono_arch_compute_omit_fp:
1292  * Determine whether the frame pointer can be eliminated.
1293  */
1294 static void
1295 mono_arch_compute_omit_fp (MonoCompile *cfg)
1296 {
1297         MonoMethodSignature *sig;
1298         MonoMethodHeader *header;
1299         int i, locals_size;
1300         CallInfo *cinfo;
1301
1302         if (cfg->arch.omit_fp_computed)
1303                 return;
1304
1305         header = cfg->header;
1306
1307         sig = mono_method_signature (cfg->method);
1308
1309         if (!cfg->arch.cinfo)
1310                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1311         cinfo = (CallInfo *)cfg->arch.cinfo;
1312
1313         /*
1314          * FIXME: Remove some of the restrictions.
1315          */
1316         cfg->arch.omit_fp = TRUE;
1317         cfg->arch.omit_fp_computed = TRUE;
1318
1319         if (cfg->disable_omit_fp)
1320                 cfg->arch.omit_fp = FALSE;
1321
1322         if (!debug_omit_fp ())
1323                 cfg->arch.omit_fp = FALSE;
1324         /*
1325         if (cfg->method->save_lmf)
1326                 cfg->arch.omit_fp = FALSE;
1327         */
1328         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1329                 cfg->arch.omit_fp = FALSE;
1330         if (header->num_clauses)
1331                 cfg->arch.omit_fp = FALSE;
1332         if (cfg->param_area)
1333                 cfg->arch.omit_fp = FALSE;
1334         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1335                 cfg->arch.omit_fp = FALSE;
1336         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1337                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1338                 cfg->arch.omit_fp = FALSE;
1339         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1340                 ArgInfo *ainfo = &cinfo->args [i];
1341
1342                 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1343                         /*
1344                          * The stack offset can only be determined when the frame
1345                          * size is known.
1346                          */
1347                         cfg->arch.omit_fp = FALSE;
1348                 }
1349         }
1350
1351         locals_size = 0;
1352         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1353                 MonoInst *ins = cfg->varinfo [i];
1354                 int ialign;
1355
1356                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1357         }
1358 }
1359
1360 GList *
1361 mono_arch_get_global_int_regs (MonoCompile *cfg)
1362 {
1363         GList *regs = NULL;
1364
1365         mono_arch_compute_omit_fp (cfg);
1366
1367         if (cfg->arch.omit_fp)
1368                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1369
1370         /* We use the callee saved registers for global allocation */
1371         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1372         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1373         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1374         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1375         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1376 #ifdef TARGET_WIN32
1377         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1378         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1379 #endif
1380
1381         return regs;
1382 }
1383
1384 GList*
1385 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1386 {
1387         GList *regs = NULL;
1388         int i;
1389
1390         /* All XMM registers */
1391         for (i = 0; i < 16; ++i)
1392                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1393
1394         return regs;
1395 }
1396
1397 GList*
1398 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1399 {
1400         static GList *r = NULL;
1401
1402         if (r == NULL) {
1403                 GList *regs = NULL;
1404
1405                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1406                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1407                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1408                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1409                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1410                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1411
1412                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1413                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1414                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1415                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1416                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1417                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1418                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1419                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1420
1421                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1422         }
1423
1424         return r;
1425 }
1426
1427 GList*
1428 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1429 {
1430         int i;
1431         static GList *r = NULL;
1432
1433         if (r == NULL) {
1434                 GList *regs = NULL;
1435
1436                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1437                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1438
1439                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1440         }
1441
1442         return r;
1443 }
1444
1445 /*
1446  * mono_arch_regalloc_cost:
1447  *
1448  *  Return the cost, in number of memory references, of the action of
1449  * allocating the variable VMV into a register during global register
1450  * allocation.
1451  */
1452 guint32
1453 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1454 {
1455         MonoInst *ins = cfg->varinfo [vmv->idx];
1456
1457         if (cfg->method->save_lmf)
1458                 /* The register is already saved */
1459                 /* substract 1 for the invisible store in the prolog */
1460                 return (ins->opcode == OP_ARG) ? 0 : 1;
1461         else
1462                 /* push+pop */
1463                 return (ins->opcode == OP_ARG) ? 1 : 2;
1464 }
1465
1466 /*
1467  * mono_arch_fill_argument_info:
1468  *
1469  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1470  * of the method.
1471  */
1472 void
1473 mono_arch_fill_argument_info (MonoCompile *cfg)
1474 {
1475         MonoType *sig_ret;
1476         MonoMethodSignature *sig;
1477         MonoInst *ins;
1478         int i;
1479         CallInfo *cinfo;
1480
1481         sig = mono_method_signature (cfg->method);
1482
1483         cinfo = (CallInfo *)cfg->arch.cinfo;
1484         sig_ret = mini_get_underlying_type (sig->ret);
1485
1486         /*
1487          * Contrary to mono_arch_allocate_vars (), the information should describe
1488          * where the arguments are at the beginning of the method, not where they can be
1489          * accessed during the execution of the method. The later makes no sense for the
1490          * global register allocator, since a variable can be in more than one location.
1491          */
1492         switch (cinfo->ret.storage) {
1493         case ArgInIReg:
1494         case ArgInFloatSSEReg:
1495         case ArgInDoubleSSEReg:
1496                 cfg->ret->opcode = OP_REGVAR;
1497                 cfg->ret->inst_c0 = cinfo->ret.reg;
1498                 break;
1499         case ArgValuetypeInReg:
1500                 cfg->ret->opcode = OP_REGOFFSET;
1501                 cfg->ret->inst_basereg = -1;
1502                 cfg->ret->inst_offset = -1;
1503                 break;
1504         case ArgNone:
1505                 break;
1506         default:
1507                 g_assert_not_reached ();
1508         }
1509
1510         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1511                 ArgInfo *ainfo = &cinfo->args [i];
1512
1513                 ins = cfg->args [i];
1514
1515                 switch (ainfo->storage) {
1516                 case ArgInIReg:
1517                 case ArgInFloatSSEReg:
1518                 case ArgInDoubleSSEReg:
1519                         ins->opcode = OP_REGVAR;
1520                         ins->inst_c0 = ainfo->reg;
1521                         break;
1522                 case ArgOnStack:
1523                         ins->opcode = OP_REGOFFSET;
1524                         ins->inst_basereg = -1;
1525                         ins->inst_offset = -1;
1526                         break;
1527                 case ArgValuetypeInReg:
1528                         /* Dummy */
1529                         ins->opcode = OP_NOP;
1530                         break;
1531                 default:
1532                         g_assert_not_reached ();
1533                 }
1534         }
1535 }
1536
1537 void
1538 mono_arch_allocate_vars (MonoCompile *cfg)
1539 {
1540         MonoType *sig_ret;
1541         MonoMethodSignature *sig;
1542         MonoInst *ins;
1543         int i, offset;
1544         guint32 locals_stack_size, locals_stack_align;
1545         gint32 *offsets;
1546         CallInfo *cinfo;
1547
1548         sig = mono_method_signature (cfg->method);
1549
1550         cinfo = (CallInfo *)cfg->arch.cinfo;
1551         sig_ret = mini_get_underlying_type (sig->ret);
1552
1553         mono_arch_compute_omit_fp (cfg);
1554
1555         /*
1556          * We use the ABI calling conventions for managed code as well.
1557          * Exception: valuetypes are only sometimes passed or returned in registers.
1558          */
1559
1560         /*
1561          * The stack looks like this:
1562          * <incoming arguments passed on the stack>
1563          * <return value>
1564          * <lmf/caller saved registers>
1565          * <locals>
1566          * <spill area>
1567          * <localloc area>  -> grows dynamically
1568          * <params area>
1569          */
1570
1571         if (cfg->arch.omit_fp) {
1572                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1573                 cfg->frame_reg = AMD64_RSP;
1574                 offset = 0;
1575         } else {
1576                 /* Locals are allocated backwards from %fp */
1577                 cfg->frame_reg = AMD64_RBP;
1578                 offset = 0;
1579         }
1580
1581         cfg->arch.saved_iregs = cfg->used_int_regs;
1582         if (cfg->method->save_lmf) {
1583                 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1584                 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1585                 cfg->arch.saved_iregs |= iregs_to_save;
1586         }
1587
1588         if (cfg->arch.omit_fp)
1589                 cfg->arch.reg_save_area_offset = offset;
1590         /* Reserve space for callee saved registers */
1591         for (i = 0; i < AMD64_NREG; ++i)
1592                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1593                         offset += sizeof(mgreg_t);
1594                 }
1595         if (!cfg->arch.omit_fp)
1596                 cfg->arch.reg_save_area_offset = -offset;
1597
1598         if (sig_ret->type != MONO_TYPE_VOID) {
1599                 switch (cinfo->ret.storage) {
1600                 case ArgInIReg:
1601                 case ArgInFloatSSEReg:
1602                 case ArgInDoubleSSEReg:
1603                         cfg->ret->opcode = OP_REGVAR;
1604                         cfg->ret->inst_c0 = cinfo->ret.reg;
1605                         cfg->ret->dreg = cinfo->ret.reg;
1606                         break;
1607                 case ArgValuetypeAddrInIReg:
1608                 case ArgGsharedvtVariableInReg:
1609                         /* The register is volatile */
1610                         cfg->vret_addr->opcode = OP_REGOFFSET;
1611                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1612                         if (cfg->arch.omit_fp) {
1613                                 cfg->vret_addr->inst_offset = offset;
1614                                 offset += 8;
1615                         } else {
1616                                 offset += 8;
1617                                 cfg->vret_addr->inst_offset = -offset;
1618                         }
1619                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1620                                 printf ("vret_addr =");
1621                                 mono_print_ins (cfg->vret_addr);
1622                         }
1623                         break;
1624                 case ArgValuetypeInReg:
1625                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1626                         cfg->ret->opcode = OP_REGOFFSET;
1627                         cfg->ret->inst_basereg = cfg->frame_reg;
1628                         if (cfg->arch.omit_fp) {
1629                                 cfg->ret->inst_offset = offset;
1630                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1631                         } else {
1632                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1633                                 cfg->ret->inst_offset = - offset;
1634                         }
1635                         break;
1636                 default:
1637                         g_assert_not_reached ();
1638                 }
1639         }
1640
1641         /* Allocate locals */
1642         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1643         if (locals_stack_align) {
1644                 offset += (locals_stack_align - 1);
1645                 offset &= ~(locals_stack_align - 1);
1646         }
1647         if (cfg->arch.omit_fp) {
1648                 cfg->locals_min_stack_offset = offset;
1649                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1650         } else {
1651                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1652                 cfg->locals_max_stack_offset = - offset;
1653         }
1654
1655         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1656                 if (offsets [i] != -1) {
1657                         MonoInst *ins = cfg->varinfo [i];
1658                         ins->opcode = OP_REGOFFSET;
1659                         ins->inst_basereg = cfg->frame_reg;
1660                         if (cfg->arch.omit_fp)
1661                                 ins->inst_offset = (offset + offsets [i]);
1662                         else
1663                                 ins->inst_offset = - (offset + offsets [i]);
1664                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1665                 }
1666         }
1667         offset += locals_stack_size;
1668
1669         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1670                 g_assert (!cfg->arch.omit_fp);
1671                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1672                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1673         }
1674
1675         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1676                 ins = cfg->args [i];
1677                 if (ins->opcode != OP_REGVAR) {
1678                         ArgInfo *ainfo = &cinfo->args [i];
1679                         gboolean inreg = TRUE;
1680
1681                         /* FIXME: Allocate volatile arguments to registers */
1682                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1683                                 inreg = FALSE;
1684
1685                         /*
1686                          * Under AMD64, all registers used to pass arguments to functions
1687                          * are volatile across calls.
1688                          * FIXME: Optimize this.
1689                          */
1690                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1691                                 inreg = FALSE;
1692
1693                         ins->opcode = OP_REGOFFSET;
1694
1695                         switch (ainfo->storage) {
1696                         case ArgInIReg:
1697                         case ArgInFloatSSEReg:
1698                         case ArgInDoubleSSEReg:
1699                         case ArgGSharedVtInReg:
1700                                 if (inreg) {
1701                                         ins->opcode = OP_REGVAR;
1702                                         ins->dreg = ainfo->reg;
1703                                 }
1704                                 break;
1705                         case ArgOnStack:
1706                         case ArgGSharedVtOnStack:
1707                                 g_assert (!cfg->arch.omit_fp);
1708                                 ins->opcode = OP_REGOFFSET;
1709                                 ins->inst_basereg = cfg->frame_reg;
1710                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1711                                 break;
1712                         case ArgValuetypeInReg:
1713                                 break;
1714                         case ArgValuetypeAddrInIReg:
1715                         case ArgValuetypeAddrOnStack: {
1716                                 MonoInst *indir;
1717                                 g_assert (!cfg->arch.omit_fp);
1718                                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1719                                 MONO_INST_NEW (cfg, indir, 0);
1720
1721                                 indir->opcode = OP_REGOFFSET;
1722                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1723                                         indir->inst_basereg = cfg->frame_reg;
1724                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1725                                         offset += (sizeof (gpointer));
1726                                         indir->inst_offset = - offset;
1727                                 }
1728                                 else {
1729                                         indir->inst_basereg = cfg->frame_reg;
1730                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1731                                 }
1732
1733                                 ins->opcode = OP_VTARG_ADDR;
1734                                 ins->inst_left = indir;
1735
1736                                 break;
1737                         }
1738                         default:
1739                                 NOT_IMPLEMENTED;
1740                         }
1741
1742                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1743                                 ins->opcode = OP_REGOFFSET;
1744                                 ins->inst_basereg = cfg->frame_reg;
1745                                 /* These arguments are saved to the stack in the prolog */
1746                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1747                                 if (cfg->arch.omit_fp) {
1748                                         ins->inst_offset = offset;
1749                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1750                                         // Arguments are yet supported by the stack map creation code
1751                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1752                                 } else {
1753                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1754                                         ins->inst_offset = - offset;
1755                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1756                                 }
1757                         }
1758                 }
1759         }
1760
1761         cfg->stack_offset = offset;
1762 }
1763
1764 void
1765 mono_arch_create_vars (MonoCompile *cfg)
1766 {
1767         MonoMethodSignature *sig;
1768         CallInfo *cinfo;
1769         MonoType *sig_ret;
1770
1771         sig = mono_method_signature (cfg->method);
1772
1773         if (!cfg->arch.cinfo)
1774                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1775         cinfo = (CallInfo *)cfg->arch.cinfo;
1776
1777         if (cinfo->ret.storage == ArgValuetypeInReg)
1778                 cfg->ret_var_is_local = TRUE;
1779
1780         sig_ret = mini_get_underlying_type (sig->ret);
1781         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1782                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1783                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1784                         printf ("vret_addr = ");
1785                         mono_print_ins (cfg->vret_addr);
1786                 }
1787         }
1788
1789         if (cfg->gen_sdb_seq_points) {
1790                 MonoInst *ins;
1791
1792                 if (cfg->compile_aot) {
1793                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1794                         ins->flags |= MONO_INST_VOLATILE;
1795                         cfg->arch.seq_point_info_var = ins;
1796                 }
1797                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1798                 ins->flags |= MONO_INST_VOLATILE;
1799                 cfg->arch.ss_tramp_var = ins;
1800
1801                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1802                 ins->flags |= MONO_INST_VOLATILE;
1803                 cfg->arch.bp_tramp_var = ins;
1804         }
1805
1806         if (cfg->method->save_lmf)
1807                 cfg->create_lmf_var = TRUE;
1808
1809         if (cfg->method->save_lmf) {
1810                 cfg->lmf_ir = TRUE;
1811         }
1812 }
1813
1814 static void
1815 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1816 {
1817         MonoInst *ins;
1818
1819         switch (storage) {
1820         case ArgInIReg:
1821                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1822                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1823                 ins->sreg1 = tree->dreg;
1824                 MONO_ADD_INS (cfg->cbb, ins);
1825                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1826                 break;
1827         case ArgInFloatSSEReg:
1828                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1829                 ins->dreg = mono_alloc_freg (cfg);
1830                 ins->sreg1 = tree->dreg;
1831                 MONO_ADD_INS (cfg->cbb, ins);
1832
1833                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1834                 break;
1835         case ArgInDoubleSSEReg:
1836                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1837                 ins->dreg = mono_alloc_freg (cfg);
1838                 ins->sreg1 = tree->dreg;
1839                 MONO_ADD_INS (cfg->cbb, ins);
1840
1841                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1842
1843                 break;
1844         default:
1845                 g_assert_not_reached ();
1846         }
1847 }
1848
1849 static int
1850 arg_storage_to_load_membase (ArgStorage storage)
1851 {
1852         switch (storage) {
1853         case ArgInIReg:
1854 #if defined(__mono_ilp32__)
1855                 return OP_LOADI8_MEMBASE;
1856 #else
1857                 return OP_LOAD_MEMBASE;
1858 #endif
1859         case ArgInDoubleSSEReg:
1860                 return OP_LOADR8_MEMBASE;
1861         case ArgInFloatSSEReg:
1862                 return OP_LOADR4_MEMBASE;
1863         default:
1864                 g_assert_not_reached ();
1865         }
1866
1867         return -1;
1868 }
1869
1870 static void
1871 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1872 {
1873         MonoMethodSignature *tmp_sig;
1874         int sig_reg;
1875
1876         if (call->tail_call)
1877                 NOT_IMPLEMENTED;
1878
1879         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1880
1881         /*
1882          * mono_ArgIterator_Setup assumes the signature cookie is
1883          * passed first and all the arguments which were before it are
1884          * passed on the stack after the signature. So compensate by
1885          * passing a different signature.
1886          */
1887         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1888         tmp_sig->param_count -= call->signature->sentinelpos;
1889         tmp_sig->sentinelpos = 0;
1890         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1891
1892         sig_reg = mono_alloc_ireg (cfg);
1893         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1894
1895         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1896 }
1897
1898 #ifdef ENABLE_LLVM
1899 static inline LLVMArgStorage
1900 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1901 {
1902         switch (storage) {
1903         case ArgInIReg:
1904                 return LLVMArgInIReg;
1905         case ArgNone:
1906                 return LLVMArgNone;
1907         case ArgGSharedVtInReg:
1908         case ArgGSharedVtOnStack:
1909                 return LLVMArgGSharedVt;
1910         default:
1911                 g_assert_not_reached ();
1912                 return LLVMArgNone;
1913         }
1914 }
1915
1916 LLVMCallInfo*
1917 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1918 {
1919         int i, n;
1920         CallInfo *cinfo;
1921         ArgInfo *ainfo;
1922         int j;
1923         LLVMCallInfo *linfo;
1924         MonoType *t, *sig_ret;
1925
1926         n = sig->param_count + sig->hasthis;
1927         sig_ret = mini_get_underlying_type (sig->ret);
1928
1929         cinfo = get_call_info (cfg->mempool, sig);
1930
1931         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1932
1933         /*
1934          * LLVM always uses the native ABI while we use our own ABI, the
1935          * only difference is the handling of vtypes:
1936          * - we only pass/receive them in registers in some cases, and only
1937          *   in 1 or 2 integer registers.
1938          */
1939         switch (cinfo->ret.storage) {
1940         case ArgNone:
1941                 linfo->ret.storage = LLVMArgNone;
1942                 break;
1943         case ArgInIReg:
1944         case ArgInFloatSSEReg:
1945         case ArgInDoubleSSEReg:
1946                 linfo->ret.storage = LLVMArgNormal;
1947                 break;
1948         case ArgValuetypeInReg: {
1949                 ainfo = &cinfo->ret;
1950
1951                 if (sig->pinvoke &&
1952                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1953                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1954                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1955                         cfg->disable_llvm = TRUE;
1956                         return linfo;
1957                 }
1958
1959                 linfo->ret.storage = LLVMArgVtypeInReg;
1960                 for (j = 0; j < 2; ++j)
1961                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1962                 break;
1963         }
1964         case ArgValuetypeAddrInIReg:
1965         case ArgGsharedvtVariableInReg:
1966                 /* Vtype returned using a hidden argument */
1967                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1968                 linfo->vret_arg_index = cinfo->vret_arg_index;
1969                 break;
1970         default:
1971                 g_assert_not_reached ();
1972                 break;
1973         }
1974
1975         for (i = 0; i < n; ++i) {
1976                 ainfo = cinfo->args + i;
1977
1978                 if (i >= sig->hasthis)
1979                         t = sig->params [i - sig->hasthis];
1980                 else
1981                         t = &mono_defaults.int_class->byval_arg;
1982                 t = mini_type_get_underlying_type (t);
1983
1984                 linfo->args [i].storage = LLVMArgNone;
1985
1986                 switch (ainfo->storage) {
1987                 case ArgInIReg:
1988                         linfo->args [i].storage = LLVMArgNormal;
1989                         break;
1990                 case ArgInDoubleSSEReg:
1991                 case ArgInFloatSSEReg:
1992                         linfo->args [i].storage = LLVMArgNormal;
1993                         break;
1994                 case ArgOnStack:
1995                         if (MONO_TYPE_ISSTRUCT (t))
1996                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1997                         else
1998                                 linfo->args [i].storage = LLVMArgNormal;
1999                         break;
2000                 case ArgValuetypeInReg:
2001                         if (sig->pinvoke &&
2002                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2003                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2004                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2005                                 cfg->disable_llvm = TRUE;
2006                                 return linfo;
2007                         }
2008
2009                         linfo->args [i].storage = LLVMArgVtypeInReg;
2010                         for (j = 0; j < 2; ++j)
2011                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2012                         break;
2013                 case ArgGSharedVtInReg:
2014                 case ArgGSharedVtOnStack:
2015                         linfo->args [i].storage = LLVMArgGSharedVt;
2016                         break;
2017                 default:
2018                         cfg->exception_message = g_strdup ("ainfo->storage");
2019                         cfg->disable_llvm = TRUE;
2020                         break;
2021                 }
2022         }
2023
2024         return linfo;
2025 }
2026 #endif
2027
2028 void
2029 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2030 {
2031         MonoInst *arg, *in;
2032         MonoMethodSignature *sig;
2033         MonoType *sig_ret;
2034         int i, n;
2035         CallInfo *cinfo;
2036         ArgInfo *ainfo;
2037
2038         sig = call->signature;
2039         n = sig->param_count + sig->hasthis;
2040
2041         cinfo = get_call_info (cfg->mempool, sig);
2042
2043         sig_ret = sig->ret;
2044
2045         if (COMPILE_LLVM (cfg)) {
2046                 /* We shouldn't be called in the llvm case */
2047                 cfg->disable_llvm = TRUE;
2048                 return;
2049         }
2050
2051         /*
2052          * Emit all arguments which are passed on the stack to prevent register
2053          * allocation problems.
2054          */
2055         for (i = 0; i < n; ++i) {
2056                 MonoType *t;
2057                 ainfo = cinfo->args + i;
2058
2059                 in = call->args [i];
2060
2061                 if (sig->hasthis && i == 0)
2062                         t = &mono_defaults.object_class->byval_arg;
2063                 else
2064                         t = sig->params [i - sig->hasthis];
2065
2066                 t = mini_get_underlying_type (t);
2067                 //XXX what about ArgGSharedVtOnStack here?
2068                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2069                         if (!t->byref) {
2070                                 if (t->type == MONO_TYPE_R4)
2071                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2072                                 else if (t->type == MONO_TYPE_R8)
2073                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2074                                 else
2075                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2076                         } else {
2077                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2078                         }
2079                         if (cfg->compute_gc_maps) {
2080                                 MonoInst *def;
2081
2082                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2083                         }
2084                 }
2085         }
2086
2087         /*
2088          * Emit all parameters passed in registers in non-reverse order for better readability
2089          * and to help the optimization in emit_prolog ().
2090          */
2091         for (i = 0; i < n; ++i) {
2092                 ainfo = cinfo->args + i;
2093
2094                 in = call->args [i];
2095
2096                 if (ainfo->storage == ArgInIReg)
2097                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2098         }
2099
2100         for (i = n - 1; i >= 0; --i) {
2101                 MonoType *t;
2102
2103                 ainfo = cinfo->args + i;
2104
2105                 in = call->args [i];
2106
2107                 if (sig->hasthis && i == 0)
2108                         t = &mono_defaults.object_class->byval_arg;
2109                 else
2110                         t = sig->params [i - sig->hasthis];
2111                 t = mini_get_underlying_type (t);
2112
2113                 switch (ainfo->storage) {
2114                 case ArgInIReg:
2115                         /* Already done */
2116                         break;
2117                 case ArgInFloatSSEReg:
2118                 case ArgInDoubleSSEReg:
2119                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2120                         break;
2121                 case ArgOnStack:
2122                 case ArgValuetypeInReg:
2123                 case ArgValuetypeAddrInIReg:
2124                 case ArgValuetypeAddrOnStack:
2125                 case ArgGSharedVtInReg:
2126                 case ArgGSharedVtOnStack: {
2127                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2128                                 /* Already emitted above */
2129                                 break;
2130                         //FIXME what about ArgGSharedVtOnStack ?
2131                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2132                                 MonoInst *call_inst = (MonoInst*)call;
2133                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2134                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2135                                 break;
2136                         }
2137
2138                         guint32 align;
2139                         guint32 size;
2140
2141                         if (sig->pinvoke)
2142                                 size = mono_type_native_stack_size (t, &align);
2143                         else {
2144                                 /*
2145                                  * Other backends use mono_type_stack_size (), but that
2146                                  * aligns the size to 8, which is larger than the size of
2147                                  * the source, leading to reads of invalid memory if the
2148                                  * source is at the end of address space.
2149                                  */
2150                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2151                         }
2152
2153                         if (size >= 10000) {
2154                                 /* Avoid asserts in emit_memcpy () */
2155                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2156                                 /* Continue normally */
2157                         }
2158
2159                         if (size > 0 || ainfo->pass_empty_struct) {
2160                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2161                                 arg->sreg1 = in->dreg;
2162                                 arg->klass = mono_class_from_mono_type (t);
2163                                 arg->backend.size = size;
2164                                 arg->inst_p0 = call;
2165                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2166                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2167
2168                                 MONO_ADD_INS (cfg->cbb, arg);
2169                         }
2170                         break;
2171                 }
2172                 default:
2173                         g_assert_not_reached ();
2174                 }
2175
2176                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2177                         /* Emit the signature cookie just before the implicit arguments */
2178                         emit_sig_cookie (cfg, call, cinfo);
2179         }
2180
2181         /* Handle the case where there are no implicit arguments */
2182         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2183                 emit_sig_cookie (cfg, call, cinfo);
2184
2185         switch (cinfo->ret.storage) {
2186         case ArgValuetypeInReg:
2187                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2188                         /*
2189                          * Tell the JIT to use a more efficient calling convention: call using
2190                          * OP_CALL, compute the result location after the call, and save the
2191                          * result there.
2192                          */
2193                         call->vret_in_reg = TRUE;
2194                         /*
2195                          * Nullify the instruction computing the vret addr to enable
2196                          * future optimizations.
2197                          */
2198                         if (call->vret_var)
2199                                 NULLIFY_INS (call->vret_var);
2200                 } else {
2201                         if (call->tail_call)
2202                                 NOT_IMPLEMENTED;
2203                         /*
2204                          * The valuetype is in RAX:RDX after the call, need to be copied to
2205                          * the stack. Push the address here, so the call instruction can
2206                          * access it.
2207                          */
2208                         if (!cfg->arch.vret_addr_loc) {
2209                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2210                                 /* Prevent it from being register allocated or optimized away */
2211                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2212                         }
2213
2214                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2215                 }
2216                 break;
2217         case ArgValuetypeAddrInIReg:
2218         case ArgGsharedvtVariableInReg: {
2219                 MonoInst *vtarg;
2220                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2221                 vtarg->sreg1 = call->vret_var->dreg;
2222                 vtarg->dreg = mono_alloc_preg (cfg);
2223                 MONO_ADD_INS (cfg->cbb, vtarg);
2224
2225                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2226                 break;
2227         }
2228         default:
2229                 break;
2230         }
2231
2232         if (cfg->method->save_lmf) {
2233                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2234                 MONO_ADD_INS (cfg->cbb, arg);
2235         }
2236
2237         call->stack_usage = cinfo->stack_usage;
2238 }
2239
2240 void
2241 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2242 {
2243         MonoInst *arg;
2244         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2245         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2246         int size = ins->backend.size;
2247
2248         switch (ainfo->storage) {
2249         case ArgValuetypeInReg: {
2250                 MonoInst *load;
2251                 int part;
2252
2253                 for (part = 0; part < 2; ++part) {
2254                         if (ainfo->pair_storage [part] == ArgNone)
2255                                 continue;
2256
2257                         if (ainfo->pass_empty_struct) {
2258                                 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2259                                 NEW_ICONST (cfg, load, 0);
2260                         }
2261                         else {
2262                                 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2263                                 load->inst_basereg = src->dreg;
2264                                 load->inst_offset = part * sizeof(mgreg_t);
2265
2266                                 switch (ainfo->pair_storage [part]) {
2267                                 case ArgInIReg:
2268                                         load->dreg = mono_alloc_ireg (cfg);
2269                                         break;
2270                                 case ArgInDoubleSSEReg:
2271                                 case ArgInFloatSSEReg:
2272                                         load->dreg = mono_alloc_freg (cfg);
2273                                         break;
2274                                 default:
2275                                         g_assert_not_reached ();
2276                                 }
2277                         }
2278
2279                         MONO_ADD_INS (cfg->cbb, load);
2280
2281                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2282                 }
2283                 break;
2284         }
2285         case ArgValuetypeAddrInIReg:
2286         case ArgValuetypeAddrOnStack: {
2287                 MonoInst *vtaddr, *load;
2288
2289                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2290
2291                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2292
2293                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2294                 cfg->has_indirection = TRUE;
2295                 load->inst_p0 = vtaddr;
2296                 vtaddr->flags |= MONO_INST_INDIRECT;
2297                 load->type = STACK_MP;
2298                 load->klass = vtaddr->klass;
2299                 load->dreg = mono_alloc_ireg (cfg);
2300                 MONO_ADD_INS (cfg->cbb, load);
2301                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, SIZEOF_VOID_P);
2302
2303                 if (ainfo->pair_storage [0] == ArgInIReg) {
2304                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2305                         arg->dreg = mono_alloc_ireg (cfg);
2306                         arg->sreg1 = load->dreg;
2307                         arg->inst_imm = 0;
2308                         MONO_ADD_INS (cfg->cbb, arg);
2309                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2310                 } else {
2311                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2312                 }
2313                 break;
2314         }
2315         case ArgGSharedVtInReg:
2316                 /* Pass by addr */
2317                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2318                 break;
2319         case ArgGSharedVtOnStack:
2320                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2321                 break;
2322         default:
2323                 if (size == 8) {
2324                         int dreg = mono_alloc_ireg (cfg);
2325
2326                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2327                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2328                 } else if (size <= 40) {
2329                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2330                 } else {
2331                         // FIXME: Code growth
2332                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2333                 }
2334
2335                 if (cfg->compute_gc_maps) {
2336                         MonoInst *def;
2337                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2338                 }
2339         }
2340 }
2341
2342 void
2343 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2344 {
2345         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2346
2347         if (ret->type == MONO_TYPE_R4) {
2348                 if (COMPILE_LLVM (cfg))
2349                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2350                 else
2351                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2352                 return;
2353         } else if (ret->type == MONO_TYPE_R8) {
2354                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2355                 return;
2356         }
2357
2358         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2359 }
2360
2361 #endif /* DISABLE_JIT */
2362
2363 #define EMIT_COND_BRANCH(ins,cond,sign) \
2364         if (ins->inst_true_bb->native_offset) { \
2365                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2366         } else { \
2367                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2368                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2369             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2370                         x86_branch8 (code, cond, 0, sign); \
2371                 else \
2372                         x86_branch32 (code, cond, 0, sign); \
2373 }
2374
2375 typedef struct {
2376         MonoMethodSignature *sig;
2377         CallInfo *cinfo;
2378 } ArchDynCallInfo;
2379
2380 static gboolean
2381 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2382 {
2383         int i;
2384
2385         switch (cinfo->ret.storage) {
2386         case ArgNone:
2387         case ArgInIReg:
2388         case ArgInFloatSSEReg:
2389         case ArgInDoubleSSEReg:
2390         case ArgValuetypeAddrInIReg:
2391         case ArgValuetypeInReg:
2392                 break;
2393         default:
2394                 return FALSE;
2395         }
2396
2397         for (i = 0; i < cinfo->nargs; ++i) {
2398                 ArgInfo *ainfo = &cinfo->args [i];
2399                 switch (ainfo->storage) {
2400                 case ArgInIReg:
2401                 case ArgInFloatSSEReg:
2402                 case ArgInDoubleSSEReg:
2403                 case ArgValuetypeInReg:
2404                         break;
2405                 case ArgOnStack:
2406                         if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2407                                 return FALSE;
2408                         break;
2409                 default:
2410                         return FALSE;
2411                 }
2412         }
2413
2414         return TRUE;
2415 }
2416
2417 /*
2418  * mono_arch_dyn_call_prepare:
2419  *
2420  *   Return a pointer to an arch-specific structure which contains information
2421  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2422  * supported for SIG.
2423  * This function is equivalent to ffi_prep_cif in libffi.
2424  */
2425 MonoDynCallInfo*
2426 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2427 {
2428         ArchDynCallInfo *info;
2429         CallInfo *cinfo;
2430
2431         cinfo = get_call_info (NULL, sig);
2432
2433         if (!dyn_call_supported (sig, cinfo)) {
2434                 g_free (cinfo);
2435                 return NULL;
2436         }
2437
2438         info = g_new0 (ArchDynCallInfo, 1);
2439         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2440         info->sig = sig;
2441         info->cinfo = cinfo;
2442
2443         return (MonoDynCallInfo*)info;
2444 }
2445
2446 /*
2447  * mono_arch_dyn_call_free:
2448  *
2449  *   Free a MonoDynCallInfo structure.
2450  */
2451 void
2452 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2453 {
2454         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2455
2456         g_free (ainfo->cinfo);
2457         g_free (ainfo);
2458 }
2459
2460 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2461 #define GREG_TO_PTR(greg) (gpointer)(greg)
2462
2463 /*
2464  * mono_arch_get_start_dyn_call:
2465  *
2466  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2467  * store the result into BUF.
2468  * ARGS should be an array of pointers pointing to the arguments.
2469  * RET should point to a memory buffer large enought to hold the result of the
2470  * call.
2471  * This function should be as fast as possible, any work which does not depend
2472  * on the actual values of the arguments should be done in
2473  * mono_arch_dyn_call_prepare ().
2474  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2475  * libffi.
2476  */
2477 void
2478 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2479 {
2480         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2481         DynCallArgs *p = (DynCallArgs*)buf;
2482         int arg_index, greg, freg, i, pindex;
2483         MonoMethodSignature *sig = dinfo->sig;
2484         int buffer_offset = 0;
2485         static int param_reg_to_index [16];
2486         static gboolean param_reg_to_index_inited;
2487
2488         if (!param_reg_to_index_inited) {
2489                 for (i = 0; i < PARAM_REGS; ++i)
2490                         param_reg_to_index [param_regs [i]] = i;
2491                 mono_memory_barrier ();
2492                 param_reg_to_index_inited = 1;
2493         }
2494
2495         g_assert (buf_len >= sizeof (DynCallArgs));
2496
2497         p->res = 0;
2498         p->ret = ret;
2499
2500         arg_index = 0;
2501         greg = 0;
2502         freg = 0;
2503         pindex = 0;
2504
2505         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2506                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2507                 if (!sig->hasthis)
2508                         pindex = 1;
2509         }
2510
2511         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2512                 p->regs [greg ++] = PTR_TO_GREG(ret);
2513
2514         for (; pindex < sig->param_count; pindex++) {
2515                 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2516                 gpointer *arg = args [arg_index ++];
2517                 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2518                 int slot;
2519
2520                 if (ainfo->storage == ArgOnStack) {
2521                         slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2522                 } else {
2523                         slot = param_reg_to_index [ainfo->reg];
2524                 }
2525
2526                 if (t->byref) {
2527                         p->regs [slot] = PTR_TO_GREG(*(arg));
2528                         greg ++;
2529                         continue;
2530                 }
2531
2532                 switch (t->type) {
2533                 case MONO_TYPE_OBJECT:
2534                 case MONO_TYPE_PTR:
2535                 case MONO_TYPE_I:
2536                 case MONO_TYPE_U:
2537 #if !defined(__mono_ilp32__)
2538                 case MONO_TYPE_I8:
2539                 case MONO_TYPE_U8:
2540 #endif
2541                         p->regs [slot] = PTR_TO_GREG(*(arg));
2542                         break;
2543 #if defined(__mono_ilp32__)
2544                 case MONO_TYPE_I8:
2545                 case MONO_TYPE_U8:
2546                         p->regs [slot] = *(guint64*)(arg);
2547                         break;
2548 #endif
2549                 case MONO_TYPE_U1:
2550                         p->regs [slot] = *(guint8*)(arg);
2551                         break;
2552                 case MONO_TYPE_I1:
2553                         p->regs [slot] = *(gint8*)(arg);
2554                         break;
2555                 case MONO_TYPE_I2:
2556                         p->regs [slot] = *(gint16*)(arg);
2557                         break;
2558                 case MONO_TYPE_U2:
2559                         p->regs [slot] = *(guint16*)(arg);
2560                         break;
2561                 case MONO_TYPE_I4:
2562                         p->regs [slot] = *(gint32*)(arg);
2563                         break;
2564                 case MONO_TYPE_U4:
2565                         p->regs [slot] = *(guint32*)(arg);
2566                         break;
2567                 case MONO_TYPE_R4: {
2568                         double d;
2569
2570                         *(float*)&d = *(float*)(arg);
2571                         p->has_fp = 1;
2572                         p->fregs [freg ++] = d;
2573                         break;
2574                 }
2575                 case MONO_TYPE_R8:
2576                         p->has_fp = 1;
2577                         p->fregs [freg ++] = *(double*)(arg);
2578                         break;
2579                 case MONO_TYPE_GENERICINST:
2580                     if (MONO_TYPE_IS_REFERENCE (t)) {
2581                                 p->regs [slot] = PTR_TO_GREG(*(arg));
2582                                 break;
2583                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2584                                         MonoClass *klass = mono_class_from_mono_type (t);
2585                                         guint8 *nullable_buf;
2586                                         int size;
2587
2588                                         size = mono_class_value_size (klass, NULL);
2589                                         nullable_buf = p->buffer + buffer_offset;
2590                                         buffer_offset += size;
2591                                         g_assert (buffer_offset <= 256);
2592
2593                                         /* The argument pointed to by arg is either a boxed vtype or null */
2594                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2595
2596                                         arg = (gpointer*)nullable_buf;
2597                                         /* Fall though */
2598
2599                         } else {
2600                                 /* Fall through */
2601                         }
2602                 case MONO_TYPE_VALUETYPE: {
2603                         switch (ainfo->storage) {
2604                         case ArgValuetypeInReg:
2605                                 for (i = 0; i < 2; ++i) {
2606                                         switch (ainfo->pair_storage [i]) {
2607                                         case ArgNone:
2608                                                 break;
2609                                         case ArgInIReg:
2610                                                 slot = param_reg_to_index [ainfo->pair_regs [i]];
2611                                                 p->regs [slot] = ((mgreg_t*)(arg))[i];
2612                                                 break;
2613                                         case ArgInDoubleSSEReg:
2614                                                 p->has_fp = 1;
2615                                                 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2616                                                 break;
2617                                         default:
2618                                                 g_assert_not_reached ();
2619                                                 break;
2620                                         }
2621                                 }
2622                                 break;
2623                         case ArgOnStack:
2624                                 for (i = 0; i < ainfo->arg_size / 8; ++i)
2625                                         p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2626                                 break;
2627                         default:
2628                                 g_assert_not_reached ();
2629                                 break;
2630                         }
2631                         break;
2632                 }
2633                 default:
2634                         g_assert_not_reached ();
2635                 }
2636         }
2637 }
2638
2639 /*
2640  * mono_arch_finish_dyn_call:
2641  *
2642  *   Store the result of a dyn call into the return value buffer passed to
2643  * start_dyn_call ().
2644  * This function should be as fast as possible, any work which does not depend
2645  * on the actual values of the arguments should be done in
2646  * mono_arch_dyn_call_prepare ().
2647  */
2648 void
2649 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2650 {
2651         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2652         MonoMethodSignature *sig = dinfo->sig;
2653         DynCallArgs *dargs = (DynCallArgs*)buf;
2654         guint8 *ret = dargs->ret;
2655         mgreg_t res = dargs->res;
2656         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2657         int i;
2658
2659         switch (sig_ret->type) {
2660         case MONO_TYPE_VOID:
2661                 *(gpointer*)ret = NULL;
2662                 break;
2663         case MONO_TYPE_OBJECT:
2664         case MONO_TYPE_I:
2665         case MONO_TYPE_U:
2666         case MONO_TYPE_PTR:
2667                 *(gpointer*)ret = GREG_TO_PTR(res);
2668                 break;
2669         case MONO_TYPE_I1:
2670                 *(gint8*)ret = res;
2671                 break;
2672         case MONO_TYPE_U1:
2673                 *(guint8*)ret = res;
2674                 break;
2675         case MONO_TYPE_I2:
2676                 *(gint16*)ret = res;
2677                 break;
2678         case MONO_TYPE_U2:
2679                 *(guint16*)ret = res;
2680                 break;
2681         case MONO_TYPE_I4:
2682                 *(gint32*)ret = res;
2683                 break;
2684         case MONO_TYPE_U4:
2685                 *(guint32*)ret = res;
2686                 break;
2687         case MONO_TYPE_I8:
2688                 *(gint64*)ret = res;
2689                 break;
2690         case MONO_TYPE_U8:
2691                 *(guint64*)ret = res;
2692                 break;
2693         case MONO_TYPE_R4:
2694                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2695                 break;
2696         case MONO_TYPE_R8:
2697                 *(double*)ret = dargs->fregs [0];
2698                 break;
2699         case MONO_TYPE_GENERICINST:
2700                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2701                         *(gpointer*)ret = GREG_TO_PTR(res);
2702                         break;
2703                 } else {
2704                         /* Fall through */
2705                 }
2706         case MONO_TYPE_VALUETYPE:
2707                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2708                         /* Nothing to do */
2709                 } else {
2710                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2711
2712                         g_assert (ainfo->storage == ArgValuetypeInReg);
2713
2714                         for (i = 0; i < 2; ++i) {
2715                                 switch (ainfo->pair_storage [0]) {
2716                                 case ArgInIReg:
2717                                         ((mgreg_t*)ret)[i] = res;
2718                                         break;
2719                                 case ArgInDoubleSSEReg:
2720                                         ((double*)ret)[i] = dargs->fregs [i];
2721                                         break;
2722                                 case ArgNone:
2723                                         break;
2724                                 default:
2725                                         g_assert_not_reached ();
2726                                         break;
2727                                 }
2728                         }
2729                 }
2730                 break;
2731         default:
2732                 g_assert_not_reached ();
2733         }
2734 }
2735
2736 /* emit an exception if condition is fail */
2737 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2738         do {                                                        \
2739                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2740                 if (tins == NULL) {                                                                             \
2741                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2742                                         MONO_PATCH_INFO_EXC, exc_name);  \
2743                         x86_branch32 (code, cond, 0, signed);               \
2744                 } else {        \
2745                         EMIT_COND_BRANCH (tins, cond, signed);  \
2746                 }                       \
2747         } while (0);
2748
2749 #define EMIT_FPCOMPARE(code) do { \
2750         amd64_fcompp (code); \
2751         amd64_fnstsw (code); \
2752 } while (0);
2753
2754 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2755     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2756         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2757         amd64_ ##op (code); \
2758         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2759         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2760 } while (0);
2761
2762 static guint8*
2763 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2764 {
2765         gboolean no_patch = FALSE;
2766
2767         /*
2768          * FIXME: Add support for thunks
2769          */
2770         {
2771                 gboolean near_call = FALSE;
2772
2773                 /*
2774                  * Indirect calls are expensive so try to make a near call if possible.
2775                  * The caller memory is allocated by the code manager so it is
2776                  * guaranteed to be at a 32 bit offset.
2777                  */
2778
2779                 if (patch_type != MONO_PATCH_INFO_ABS) {
2780                         /* The target is in memory allocated using the code manager */
2781                         near_call = TRUE;
2782
2783                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2784                                 if (((MonoMethod*)data)->klass->image->aot_module)
2785                                         /* The callee might be an AOT method */
2786                                         near_call = FALSE;
2787                                 if (((MonoMethod*)data)->dynamic)
2788                                         /* The target is in malloc-ed memory */
2789                                         near_call = FALSE;
2790                         }
2791
2792                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2793                                 /*
2794                                  * The call might go directly to a native function without
2795                                  * the wrapper.
2796                                  */
2797                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2798                                 if (mi) {
2799                                         gconstpointer target = mono_icall_get_wrapper (mi);
2800                                         if ((((guint64)target) >> 32) != 0)
2801                                                 near_call = FALSE;
2802                                 }
2803                         }
2804                 }
2805                 else {
2806                         MonoJumpInfo *jinfo = NULL;
2807
2808                         if (cfg->abs_patches)
2809                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2810                         if (jinfo) {
2811                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2812                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2813                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2814                                                 near_call = TRUE;
2815                                         no_patch = TRUE;
2816                                 } else {
2817                                         /*
2818                                          * This is not really an optimization, but required because the
2819                                          * generic class init trampolines use R11 to pass the vtable.
2820                                          */
2821                                         near_call = TRUE;
2822                                 }
2823                         } else {
2824                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2825                                 if (info) {
2826                                         if (info->func == info->wrapper) {
2827                                                 /* No wrapper */
2828                                                 if ((((guint64)info->func) >> 32) == 0)
2829                                                         near_call = TRUE;
2830                                         }
2831                                         else {
2832                                                 /* See the comment in mono_codegen () */
2833                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2834                                                         near_call = TRUE;
2835                                         }
2836                                 }
2837                                 else if ((((guint64)data) >> 32) == 0) {
2838                                         near_call = TRUE;
2839                                         no_patch = TRUE;
2840                                 }
2841                         }
2842                 }
2843
2844                 if (cfg->method->dynamic)
2845                         /* These methods are allocated using malloc */
2846                         near_call = FALSE;
2847
2848 #ifdef MONO_ARCH_NOMAP32BIT
2849                 near_call = FALSE;
2850 #endif
2851                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2852                 if (optimize_for_xen)
2853                         near_call = FALSE;
2854
2855                 if (cfg->compile_aot) {
2856                         near_call = TRUE;
2857                         no_patch = TRUE;
2858                 }
2859
2860                 if (near_call) {
2861                         /*
2862                          * Align the call displacement to an address divisible by 4 so it does
2863                          * not span cache lines. This is required for code patching to work on SMP
2864                          * systems.
2865                          */
2866                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2867                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2868                                 amd64_padding (code, pad_size);
2869                         }
2870                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2871                         amd64_call_code (code, 0);
2872                 }
2873                 else {
2874                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2875                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2876                         amd64_call_reg (code, GP_SCRATCH_REG);
2877                 }
2878         }
2879
2880         return code;
2881 }
2882
2883 static inline guint8*
2884 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2885 {
2886 #ifdef TARGET_WIN32
2887         if (win64_adjust_stack)
2888                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2889 #endif
2890         code = emit_call_body (cfg, code, patch_type, data);
2891 #ifdef TARGET_WIN32
2892         if (win64_adjust_stack)
2893                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2894 #endif
2895
2896         return code;
2897 }
2898
2899 static inline int
2900 store_membase_imm_to_store_membase_reg (int opcode)
2901 {
2902         switch (opcode) {
2903         case OP_STORE_MEMBASE_IMM:
2904                 return OP_STORE_MEMBASE_REG;
2905         case OP_STOREI4_MEMBASE_IMM:
2906                 return OP_STOREI4_MEMBASE_REG;
2907         case OP_STOREI8_MEMBASE_IMM:
2908                 return OP_STOREI8_MEMBASE_REG;
2909         }
2910
2911         return -1;
2912 }
2913
2914 #ifndef DISABLE_JIT
2915
2916 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2917
2918 /*
2919  * mono_arch_peephole_pass_1:
2920  *
2921  *   Perform peephole opts which should/can be performed before local regalloc
2922  */
2923 void
2924 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2925 {
2926         MonoInst *ins, *n;
2927
2928         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2929                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2930
2931                 switch (ins->opcode) {
2932                 case OP_ADD_IMM:
2933                 case OP_IADD_IMM:
2934                 case OP_LADD_IMM:
2935                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2936                                 /*
2937                                  * X86_LEA is like ADD, but doesn't have the
2938                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2939                                  * its operand to 64 bit.
2940                                  */
2941                                 ins->opcode = OP_X86_LEA_MEMBASE;
2942                                 ins->inst_basereg = ins->sreg1;
2943                         }
2944                         break;
2945                 case OP_LXOR:
2946                 case OP_IXOR:
2947                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2948                                 MonoInst *ins2;
2949
2950                                 /*
2951                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2952                                  * the latter has length 2-3 instead of 6 (reverse constant
2953                                  * propagation). These instruction sequences are very common
2954                                  * in the initlocals bblock.
2955                                  */
2956                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2957                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2958                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2959                                                 ins2->sreg1 = ins->dreg;
2960                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2961                                                 /* Continue */
2962                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2963                                                 NULLIFY_INS (ins2);
2964                                                 /* Continue */
2965                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2966                                                 /* Continue */
2967                                         } else {
2968                                                 break;
2969                                         }
2970                                 }
2971                         }
2972                         break;
2973                 case OP_COMPARE_IMM:
2974                 case OP_LCOMPARE_IMM:
2975                         /* OP_COMPARE_IMM (reg, 0)
2976                          * -->
2977                          * OP_AMD64_TEST_NULL (reg)
2978                          */
2979                         if (!ins->inst_imm)
2980                                 ins->opcode = OP_AMD64_TEST_NULL;
2981                         break;
2982                 case OP_ICOMPARE_IMM:
2983                         if (!ins->inst_imm)
2984                                 ins->opcode = OP_X86_TEST_NULL;
2985                         break;
2986                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2987                         /*
2988                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2989                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2990                          * -->
2991                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2992                          * OP_COMPARE_IMM reg, imm
2993                          *
2994                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2995                          */
2996                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2997                             ins->inst_basereg == last_ins->inst_destbasereg &&
2998                             ins->inst_offset == last_ins->inst_offset) {
2999                                         ins->opcode = OP_ICOMPARE_IMM;
3000                                         ins->sreg1 = last_ins->sreg1;
3001
3002                                         /* check if we can remove cmp reg,0 with test null */
3003                                         if (!ins->inst_imm)
3004                                                 ins->opcode = OP_X86_TEST_NULL;
3005                                 }
3006
3007                         break;
3008                 }
3009
3010                 mono_peephole_ins (bb, ins);
3011         }
3012 }
3013
3014 void
3015 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3016 {
3017         MonoInst *ins, *n;
3018
3019         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3020                 switch (ins->opcode) {
3021                 case OP_ICONST:
3022                 case OP_I8CONST: {
3023                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3024                         /* reg = 0 -> XOR (reg, reg) */
3025                         /* XOR sets cflags on x86, so we cant do it always */
3026                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3027                                 ins->opcode = OP_LXOR;
3028                                 ins->sreg1 = ins->dreg;
3029                                 ins->sreg2 = ins->dreg;
3030                                 /* Fall through */
3031                         } else {
3032                                 break;
3033                         }
3034                 }
3035                 case OP_LXOR:
3036                         /*
3037                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3038                          * 0 result into 64 bits.
3039                          */
3040                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3041                                 ins->opcode = OP_IXOR;
3042                         }
3043                         /* Fall through */
3044                 case OP_IXOR:
3045                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3046                                 MonoInst *ins2;
3047
3048                                 /*
3049                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3050                                  * the latter has length 2-3 instead of 6 (reverse constant
3051                                  * propagation). These instruction sequences are very common
3052                                  * in the initlocals bblock.
3053                                  */
3054                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3055                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3056                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3057                                                 ins2->sreg1 = ins->dreg;
3058                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3059                                                 /* Continue */
3060                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3061                                                 NULLIFY_INS (ins2);
3062                                                 /* Continue */
3063                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3064                                                 /* Continue */
3065                                         } else {
3066                                                 break;
3067                                         }
3068                                 }
3069                         }
3070                         break;
3071                 case OP_IADD_IMM:
3072                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3073                                 ins->opcode = OP_X86_INC_REG;
3074                         break;
3075                 case OP_ISUB_IMM:
3076                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3077                                 ins->opcode = OP_X86_DEC_REG;
3078                         break;
3079                 }
3080
3081                 mono_peephole_ins (bb, ins);
3082         }
3083 }
3084
3085 #define NEW_INS(cfg,ins,dest,op) do {   \
3086                 MONO_INST_NEW ((cfg), (dest), (op)); \
3087         (dest)->cil_code = (ins)->cil_code; \
3088         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3089         } while (0)
3090
3091 /*
3092  * mono_arch_lowering_pass:
3093  *
3094  *  Converts complex opcodes into simpler ones so that each IR instruction
3095  * corresponds to one machine instruction.
3096  */
3097 void
3098 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3099 {
3100         MonoInst *ins, *n, *temp;
3101
3102         /*
3103          * FIXME: Need to add more instructions, but the current machine
3104          * description can't model some parts of the composite instructions like
3105          * cdq.
3106          */
3107         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3108                 switch (ins->opcode) {
3109                 case OP_DIV_IMM:
3110                 case OP_REM_IMM:
3111                 case OP_IDIV_IMM:
3112                 case OP_IDIV_UN_IMM:
3113                 case OP_IREM_UN_IMM:
3114                 case OP_LREM_IMM:
3115                 case OP_IREM_IMM:
3116                         mono_decompose_op_imm (cfg, bb, ins);
3117                         break;
3118                 case OP_COMPARE_IMM:
3119                 case OP_LCOMPARE_IMM:
3120                         if (!amd64_use_imm32 (ins->inst_imm)) {
3121                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3122                                 temp->inst_c0 = ins->inst_imm;
3123                                 temp->dreg = mono_alloc_ireg (cfg);
3124                                 ins->opcode = OP_COMPARE;
3125                                 ins->sreg2 = temp->dreg;
3126                         }
3127                         break;
3128 #ifndef __mono_ilp32__
3129                 case OP_LOAD_MEMBASE:
3130 #endif
3131                 case OP_LOADI8_MEMBASE:
3132                 /*  Don't generate memindex opcodes (to simplify */
3133                 /*  read sandboxing) */
3134                         if (!amd64_use_imm32 (ins->inst_offset)) {
3135                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3136                                 temp->inst_c0 = ins->inst_offset;
3137                                 temp->dreg = mono_alloc_ireg (cfg);
3138                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3139                                 ins->inst_indexreg = temp->dreg;
3140                         }
3141                         break;
3142 #ifndef __mono_ilp32__
3143                 case OP_STORE_MEMBASE_IMM:
3144 #endif
3145                 case OP_STOREI8_MEMBASE_IMM:
3146                         if (!amd64_use_imm32 (ins->inst_imm)) {
3147                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3148                                 temp->inst_c0 = ins->inst_imm;
3149                                 temp->dreg = mono_alloc_ireg (cfg);
3150                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3151                                 ins->sreg1 = temp->dreg;
3152                         }
3153                         break;
3154 #ifdef MONO_ARCH_SIMD_INTRINSICS
3155                 case OP_EXPAND_I1: {
3156                                 int temp_reg1 = mono_alloc_ireg (cfg);
3157                                 int temp_reg2 = mono_alloc_ireg (cfg);
3158                                 int original_reg = ins->sreg1;
3159
3160                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3161                                 temp->sreg1 = original_reg;
3162                                 temp->dreg = temp_reg1;
3163
3164                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3165                                 temp->sreg1 = temp_reg1;
3166                                 temp->dreg = temp_reg2;
3167                                 temp->inst_imm = 8;
3168
3169                                 NEW_INS (cfg, ins, temp, OP_LOR);
3170                                 temp->sreg1 = temp->dreg = temp_reg2;
3171                                 temp->sreg2 = temp_reg1;
3172
3173                                 ins->opcode = OP_EXPAND_I2;
3174                                 ins->sreg1 = temp_reg2;
3175                         }
3176                         break;
3177 #endif
3178                 default:
3179                         break;
3180                 }
3181         }
3182
3183         bb->max_vreg = cfg->next_vreg;
3184 }
3185
3186 static const int
3187 branch_cc_table [] = {
3188         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3189         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3190         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3191 };
3192
3193 /* Maps CMP_... constants to X86_CC_... constants */
3194 static const int
3195 cc_table [] = {
3196         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3197         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3198 };
3199
3200 static const int
3201 cc_signed_table [] = {
3202         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3203         FALSE, FALSE, FALSE, FALSE
3204 };
3205
3206 /*#include "cprop.c"*/
3207
3208 static unsigned char*
3209 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3210 {
3211         if (size == 8)
3212                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3213         else
3214                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3215
3216         if (size == 1)
3217                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3218         else if (size == 2)
3219                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3220         return code;
3221 }
3222
3223 static unsigned char*
3224 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3225 {
3226         int sreg = tree->sreg1;
3227         int need_touch = FALSE;
3228
3229 #if defined(TARGET_WIN32)
3230         need_touch = TRUE;
3231 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3232         if (!(tree->flags & MONO_INST_INIT))
3233                 need_touch = TRUE;
3234 #endif
3235
3236         if (need_touch) {
3237                 guint8* br[5];
3238
3239                 /*
3240                  * Under Windows:
3241                  * If requested stack size is larger than one page,
3242                  * perform stack-touch operation
3243                  */
3244                 /*
3245                  * Generate stack probe code.
3246                  * Under Windows, it is necessary to allocate one page at a time,
3247                  * "touching" stack after each successful sub-allocation. This is
3248                  * because of the way stack growth is implemented - there is a
3249                  * guard page before the lowest stack page that is currently commited.
3250                  * Stack normally grows sequentially so OS traps access to the
3251                  * guard page and commits more pages when needed.
3252                  */
3253                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3254                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3255
3256                 br[2] = code; /* loop */
3257                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3258                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3259                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3260                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3261                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3262                 amd64_patch (br[3], br[2]);
3263                 amd64_test_reg_reg (code, sreg, sreg);
3264                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3265                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3266
3267                 br[1] = code; x86_jump8 (code, 0);
3268
3269                 amd64_patch (br[0], code);
3270                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3271                 amd64_patch (br[1], code);
3272                 amd64_patch (br[4], code);
3273         }
3274         else
3275                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3276
3277         if (tree->flags & MONO_INST_INIT) {
3278                 int offset = 0;
3279                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3280                         amd64_push_reg (code, AMD64_RAX);
3281                         offset += 8;
3282                 }
3283                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3284                         amd64_push_reg (code, AMD64_RCX);
3285                         offset += 8;
3286                 }
3287                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3288                         amd64_push_reg (code, AMD64_RDI);
3289                         offset += 8;
3290                 }
3291
3292                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3293                 if (sreg != AMD64_RCX)
3294                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3295                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3296
3297                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3298                 if (cfg->param_area)
3299                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3300                 amd64_cld (code);
3301                 amd64_prefix (code, X86_REP_PREFIX);
3302                 amd64_stosl (code);
3303
3304                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3305                         amd64_pop_reg (code, AMD64_RDI);
3306                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3307                         amd64_pop_reg (code, AMD64_RCX);
3308                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3309                         amd64_pop_reg (code, AMD64_RAX);
3310         }
3311         return code;
3312 }
3313
3314 static guint8*
3315 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3316 {
3317         CallInfo *cinfo;
3318         guint32 quad;
3319
3320         /* Move return value to the target register */
3321         /* FIXME: do this in the local reg allocator */
3322         switch (ins->opcode) {
3323         case OP_CALL:
3324         case OP_CALL_REG:
3325         case OP_CALL_MEMBASE:
3326         case OP_LCALL:
3327         case OP_LCALL_REG:
3328         case OP_LCALL_MEMBASE:
3329                 g_assert (ins->dreg == AMD64_RAX);
3330                 break;
3331         case OP_FCALL:
3332         case OP_FCALL_REG:
3333         case OP_FCALL_MEMBASE: {
3334                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3335                 if (rtype->type == MONO_TYPE_R4) {
3336                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3337                 }
3338                 else {
3339                         if (ins->dreg != AMD64_XMM0)
3340                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3341                 }
3342                 break;
3343         }
3344         case OP_RCALL:
3345         case OP_RCALL_REG:
3346         case OP_RCALL_MEMBASE:
3347                 if (ins->dreg != AMD64_XMM0)
3348                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3349                 break;
3350         case OP_VCALL:
3351         case OP_VCALL_REG:
3352         case OP_VCALL_MEMBASE:
3353         case OP_VCALL2:
3354         case OP_VCALL2_REG:
3355         case OP_VCALL2_MEMBASE:
3356                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3357                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3358                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3359
3360                         /* Load the destination address */
3361                         g_assert (loc->opcode == OP_REGOFFSET);
3362                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3363
3364                         for (quad = 0; quad < 2; quad ++) {
3365                                 switch (cinfo->ret.pair_storage [quad]) {
3366                                 case ArgInIReg:
3367                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3368                                         break;
3369                                 case ArgInFloatSSEReg:
3370                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3371                                         break;
3372                                 case ArgInDoubleSSEReg:
3373                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3374                                         break;
3375                                 case ArgNone:
3376                                         break;
3377                                 default:
3378                                         NOT_IMPLEMENTED;
3379                                 }
3380                         }
3381                 }
3382                 break;
3383         }
3384
3385         return code;
3386 }
3387
3388 #endif /* DISABLE_JIT */
3389
3390 #ifdef TARGET_MACH
3391 static int tls_gs_offset;
3392 #endif
3393
3394 gboolean
3395 mono_arch_have_fast_tls (void)
3396 {
3397 #ifdef TARGET_MACH
3398         static gboolean have_fast_tls = FALSE;
3399         static gboolean inited = FALSE;
3400         guint8 *ins;
3401
3402         if (mini_get_debug_options ()->use_fallback_tls)
3403                 return FALSE;
3404
3405         if (inited)
3406                 return have_fast_tls;
3407
3408         ins = (guint8*)pthread_getspecific;
3409
3410         /*
3411          * We're looking for these two instructions:
3412          *
3413          * mov    %gs:[offset](,%rdi,8),%rax
3414          * retq
3415          */
3416         have_fast_tls = ins [0] == 0x65 &&
3417                        ins [1] == 0x48 &&
3418                        ins [2] == 0x8b &&
3419                        ins [3] == 0x04 &&
3420                        ins [4] == 0xfd &&
3421                        ins [6] == 0x00 &&
3422                        ins [7] == 0x00 &&
3423                        ins [8] == 0x00 &&
3424                        ins [9] == 0xc3;
3425
3426         tls_gs_offset = ins[5];
3427
3428         /*
3429          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3430          * For that version we're looking for these instructions:
3431          *
3432          * pushq  %rbp
3433          * movq   %rsp, %rbp
3434          * mov    %gs:[offset](,%rdi,8),%rax
3435          * popq   %rbp
3436          * retq
3437          */
3438         if (!have_fast_tls) {
3439                 have_fast_tls = ins [0] == 0x55 &&
3440                                ins [1] == 0x48 &&
3441                                ins [2] == 0x89 &&
3442                                ins [3] == 0xe5 &&
3443                                ins [4] == 0x65 &&
3444                                ins [5] == 0x48 &&
3445                                ins [6] == 0x8b &&
3446                                ins [7] == 0x04 &&
3447                                ins [8] == 0xfd &&
3448                                ins [10] == 0x00 &&
3449                                ins [11] == 0x00 &&
3450                                ins [12] == 0x00 &&
3451                                ins [13] == 0x5d &&
3452                                ins [14] == 0xc3;
3453
3454                 tls_gs_offset = ins[9];
3455         }
3456         inited = TRUE;
3457
3458         return have_fast_tls;
3459 #elif defined(TARGET_ANDROID)
3460         return FALSE;
3461 #else
3462         if (mini_get_debug_options ()->use_fallback_tls)
3463                 return FALSE;
3464         return TRUE;
3465 #endif
3466 }
3467
3468 int
3469 mono_amd64_get_tls_gs_offset (void)
3470 {
3471 #ifdef TARGET_OSX
3472         return tls_gs_offset;
3473 #else
3474         g_assert_not_reached ();
3475         return -1;
3476 #endif
3477 }
3478
3479 /*
3480  * \param code buffer to store code to
3481  * \param dreg hard register where to place the result
3482  * \param tls_offset offset info
3483  * \return a pointer to the end of the stored code
3484  *
3485  * mono_amd64_emit_tls_get emits in \p code the native code that puts in
3486  * the dreg register the item in the thread local storage identified
3487  * by tls_offset.
3488  */
3489 static guint8*
3490 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3491 {
3492 #ifdef TARGET_WIN32
3493         if (tls_offset < 64) {
3494                 x86_prefix (code, X86_GS_PREFIX);
3495                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3496         } else {
3497                 guint8 *buf [16];
3498
3499                 g_assert (tls_offset < 0x440);
3500                 /* Load TEB->TlsExpansionSlots */
3501                 x86_prefix (code, X86_GS_PREFIX);
3502                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3503                 amd64_test_reg_reg (code, dreg, dreg);
3504                 buf [0] = code;
3505                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3506                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3507                 amd64_patch (buf [0], code);
3508         }
3509 #elif defined(TARGET_MACH)
3510         x86_prefix (code, X86_GS_PREFIX);
3511         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3512 #else
3513         if (optimize_for_xen) {
3514                 x86_prefix (code, X86_FS_PREFIX);
3515                 amd64_mov_reg_mem (code, dreg, 0, 8);
3516                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3517         } else {
3518                 x86_prefix (code, X86_FS_PREFIX);
3519                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3520         }
3521 #endif
3522         return code;
3523 }
3524
3525 static guint8*
3526 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3527 {
3528 #ifdef TARGET_WIN32
3529         g_assert_not_reached ();
3530 #elif defined(TARGET_MACH)
3531         x86_prefix (code, X86_GS_PREFIX);
3532         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3533 #else
3534         g_assert (!optimize_for_xen);
3535         x86_prefix (code, X86_FS_PREFIX);
3536         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3537 #endif
3538         return code;
3539 }
3540
3541 /*
3542  * emit_setup_lmf:
3543  *
3544  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3545  */
3546 static guint8*
3547 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3548 {
3549         /*
3550          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3551          */
3552         /*
3553          * sp is saved right before calls but we need to save it here too so
3554          * async stack walks would work.
3555          */
3556         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3557         /* Save rbp */
3558         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3559         if (cfg->arch.omit_fp && cfa_offset != -1)
3560                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3561
3562         /* These can't contain refs */
3563         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3564         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3565         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3566         /* These are handled automatically by the stack marking code */
3567         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3568
3569         return code;
3570 }
3571
3572 #ifdef TARGET_WIN32
3573
3574 #define TEB_LAST_ERROR_OFFSET 0x068
3575
3576 static guint8*
3577 emit_get_last_error (guint8* code, int dreg)
3578 {
3579         /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3580         x86_prefix (code, X86_GS_PREFIX);
3581         amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3582
3583         return code;
3584 }
3585
3586 #else
3587
3588 static guint8*
3589 emit_get_last_error (guint8* code, int dreg)
3590 {
3591         g_assert_not_reached ();
3592 }
3593
3594 #endif
3595
3596 /* benchmark and set based on cpu */
3597 #define LOOP_ALIGNMENT 8
3598 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3599
3600 #ifndef DISABLE_JIT
3601 void
3602 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3603 {
3604         MonoInst *ins;
3605         MonoCallInst *call;
3606         guint offset;
3607         guint8 *code = cfg->native_code + cfg->code_len;
3608         int max_len;
3609
3610         /* Fix max_offset estimate for each successor bb */
3611         if (cfg->opt & MONO_OPT_BRANCH) {
3612                 int current_offset = cfg->code_len;
3613                 MonoBasicBlock *current_bb;
3614                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3615                         current_bb->max_offset = current_offset;
3616                         current_offset += current_bb->max_length;
3617                 }
3618         }
3619
3620         if (cfg->opt & MONO_OPT_LOOP) {
3621                 int pad, align = LOOP_ALIGNMENT;
3622                 /* set alignment depending on cpu */
3623                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3624                         pad = align - pad;
3625                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3626                         amd64_padding (code, pad);
3627                         cfg->code_len += pad;
3628                         bb->native_offset = cfg->code_len;
3629                 }
3630         }
3631
3632         if (cfg->verbose_level > 2)
3633                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3634
3635         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3636                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3637                 g_assert (!cfg->compile_aot);
3638
3639                 cov->data [bb->dfn].cil_code = bb->cil_code;
3640                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3641                 /* this is not thread save, but good enough */
3642                 amd64_inc_membase (code, AMD64_R11, 0);
3643         }
3644
3645         offset = code - cfg->native_code;
3646
3647         mono_debug_open_block (cfg, bb, offset);
3648
3649     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3650                 x86_breakpoint (code);
3651
3652         MONO_BB_FOR_EACH_INS (bb, ins) {
3653                 offset = code - cfg->native_code;
3654
3655                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3656
3657 #define EXTRA_CODE_SPACE (16)
3658
3659                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3660                         cfg->code_size *= 2;
3661                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3662                         code = cfg->native_code + offset;
3663                         cfg->stat_code_reallocs++;
3664                 }
3665
3666                 if (cfg->debug_info)
3667                         mono_debug_record_line_number (cfg, ins, offset);
3668
3669                 switch (ins->opcode) {
3670                 case OP_BIGMUL:
3671                         amd64_mul_reg (code, ins->sreg2, TRUE);
3672                         break;
3673                 case OP_BIGMUL_UN:
3674                         amd64_mul_reg (code, ins->sreg2, FALSE);
3675                         break;
3676                 case OP_X86_SETEQ_MEMBASE:
3677                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3678                         break;
3679                 case OP_STOREI1_MEMBASE_IMM:
3680                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3681                         break;
3682                 case OP_STOREI2_MEMBASE_IMM:
3683                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3684                         break;
3685                 case OP_STOREI4_MEMBASE_IMM:
3686                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3687                         break;
3688                 case OP_STOREI1_MEMBASE_REG:
3689                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3690                         break;
3691                 case OP_STOREI2_MEMBASE_REG:
3692                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3693                         break;
3694                 /* In AMD64 NaCl, pointers are 4 bytes, */
3695                 /*  so STORE_* != STOREI8_*. Likewise below. */
3696                 case OP_STORE_MEMBASE_REG:
3697                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3698                         break;
3699                 case OP_STOREI8_MEMBASE_REG:
3700                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3701                         break;
3702                 case OP_STOREI4_MEMBASE_REG:
3703                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3704                         break;
3705                 case OP_STORE_MEMBASE_IMM:
3706                         /* In NaCl, this could be a PCONST type, which could */
3707                         /* mean a pointer type was copied directly into the  */
3708                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3709                         /* the value would be 0x00000000FFFFFFFF which is    */
3710                         /* not proper for an imm32 unless you cast it.       */
3711                         g_assert (amd64_is_imm32 (ins->inst_imm));
3712                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3713                         break;
3714                 case OP_STOREI8_MEMBASE_IMM:
3715                         g_assert (amd64_is_imm32 (ins->inst_imm));
3716                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3717                         break;
3718                 case OP_LOAD_MEM:
3719 #ifdef __mono_ilp32__
3720                         /* In ILP32, pointers are 4 bytes, so separate these */
3721                         /* cases, use literal 8 below where we really want 8 */
3722                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3723                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3724                         break;
3725 #endif
3726                 case OP_LOADI8_MEM:
3727                         // FIXME: Decompose this earlier
3728                         if (amd64_use_imm32 (ins->inst_imm))
3729                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3730                         else {
3731                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3732                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3733                         }
3734                         break;
3735                 case OP_LOADI4_MEM:
3736                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3737                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3738                         break;
3739                 case OP_LOADU4_MEM:
3740                         // FIXME: Decompose this earlier
3741                         if (amd64_use_imm32 (ins->inst_imm))
3742                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3743                         else {
3744                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3745                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3746                         }
3747                         break;
3748                 case OP_LOADU1_MEM:
3749                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3750                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3751                         break;
3752                 case OP_LOADU2_MEM:
3753                         /* For NaCl, pointers are 4 bytes, so separate these */
3754                         /* cases, use literal 8 below where we really want 8 */
3755                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3756                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3757                         break;
3758                 case OP_LOAD_MEMBASE:
3759                         g_assert (amd64_is_imm32 (ins->inst_offset));
3760                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3761                         break;
3762                 case OP_LOADI8_MEMBASE:
3763                         /* Use literal 8 instead of sizeof pointer or */
3764                         /* register, we really want 8 for this opcode */
3765                         g_assert (amd64_is_imm32 (ins->inst_offset));
3766                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3767                         break;
3768                 case OP_LOADI4_MEMBASE:
3769                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3770                         break;
3771                 case OP_LOADU4_MEMBASE:
3772                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3773                         break;
3774                 case OP_LOADU1_MEMBASE:
3775                         /* The cpu zero extends the result into 64 bits */
3776                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3777                         break;
3778                 case OP_LOADI1_MEMBASE:
3779                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3780                         break;
3781                 case OP_LOADU2_MEMBASE:
3782                         /* The cpu zero extends the result into 64 bits */
3783                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3784                         break;
3785                 case OP_LOADI2_MEMBASE:
3786                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3787                         break;
3788                 case OP_AMD64_LOADI8_MEMINDEX:
3789                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3790                         break;
3791                 case OP_LCONV_TO_I1:
3792                 case OP_ICONV_TO_I1:
3793                 case OP_SEXT_I1:
3794                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3795                         break;
3796                 case OP_LCONV_TO_I2:
3797                 case OP_ICONV_TO_I2:
3798                 case OP_SEXT_I2:
3799                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3800                         break;
3801                 case OP_LCONV_TO_U1:
3802                 case OP_ICONV_TO_U1:
3803                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3804                         break;
3805                 case OP_LCONV_TO_U2:
3806                 case OP_ICONV_TO_U2:
3807                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3808                         break;
3809                 case OP_ZEXT_I4:
3810                         /* Clean out the upper word */
3811                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3812                         break;
3813                 case OP_SEXT_I4:
3814                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3815                         break;
3816                 case OP_COMPARE:
3817                 case OP_LCOMPARE:
3818                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3819                         break;
3820                 case OP_COMPARE_IMM:
3821 #if defined(__mono_ilp32__)
3822                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3823                         g_assert (amd64_is_imm32 (ins->inst_imm));
3824                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3825                         break;
3826 #endif
3827                 case OP_LCOMPARE_IMM:
3828                         g_assert (amd64_is_imm32 (ins->inst_imm));
3829                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3830                         break;
3831                 case OP_X86_COMPARE_REG_MEMBASE:
3832                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3833                         break;
3834                 case OP_X86_TEST_NULL:
3835                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3836                         break;
3837                 case OP_AMD64_TEST_NULL:
3838                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3839                         break;
3840
3841                 case OP_X86_ADD_REG_MEMBASE:
3842                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3843                         break;
3844                 case OP_X86_SUB_REG_MEMBASE:
3845                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3846                         break;
3847                 case OP_X86_AND_REG_MEMBASE:
3848                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3849                         break;
3850                 case OP_X86_OR_REG_MEMBASE:
3851                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3852                         break;
3853                 case OP_X86_XOR_REG_MEMBASE:
3854                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3855                         break;
3856
3857                 case OP_X86_ADD_MEMBASE_IMM:
3858                         /* FIXME: Make a 64 version too */
3859                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3860                         break;
3861                 case OP_X86_SUB_MEMBASE_IMM:
3862                         g_assert (amd64_is_imm32 (ins->inst_imm));
3863                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3864                         break;
3865                 case OP_X86_AND_MEMBASE_IMM:
3866                         g_assert (amd64_is_imm32 (ins->inst_imm));
3867                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3868                         break;
3869                 case OP_X86_OR_MEMBASE_IMM:
3870                         g_assert (amd64_is_imm32 (ins->inst_imm));
3871                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3872                         break;
3873                 case OP_X86_XOR_MEMBASE_IMM:
3874                         g_assert (amd64_is_imm32 (ins->inst_imm));
3875                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3876                         break;
3877                 case OP_X86_ADD_MEMBASE_REG:
3878                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3879                         break;
3880                 case OP_X86_SUB_MEMBASE_REG:
3881                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3882                         break;
3883                 case OP_X86_AND_MEMBASE_REG:
3884                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3885                         break;
3886                 case OP_X86_OR_MEMBASE_REG:
3887                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3888                         break;
3889                 case OP_X86_XOR_MEMBASE_REG:
3890                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3891                         break;
3892                 case OP_X86_INC_MEMBASE:
3893                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3894                         break;
3895                 case OP_X86_INC_REG:
3896                         amd64_inc_reg_size (code, ins->dreg, 4);
3897                         break;
3898                 case OP_X86_DEC_MEMBASE:
3899                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3900                         break;
3901                 case OP_X86_DEC_REG:
3902                         amd64_dec_reg_size (code, ins->dreg, 4);
3903                         break;
3904                 case OP_X86_MUL_REG_MEMBASE:
3905                 case OP_X86_MUL_MEMBASE_REG:
3906                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3907                         break;
3908                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3909                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3910                         break;
3911                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3912                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3913                         break;
3914                 case OP_AMD64_COMPARE_MEMBASE_REG:
3915                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3916                         break;
3917                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3918                         g_assert (amd64_is_imm32 (ins->inst_imm));
3919                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3920                         break;
3921                 case OP_X86_COMPARE_MEMBASE8_IMM:
3922                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3923                         break;
3924                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3925                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3926                         break;
3927                 case OP_AMD64_COMPARE_REG_MEMBASE:
3928                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3929                         break;
3930
3931                 case OP_AMD64_ADD_REG_MEMBASE:
3932                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3933                         break;
3934                 case OP_AMD64_SUB_REG_MEMBASE:
3935                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3936                         break;
3937                 case OP_AMD64_AND_REG_MEMBASE:
3938                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3939                         break;
3940                 case OP_AMD64_OR_REG_MEMBASE:
3941                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3942                         break;
3943                 case OP_AMD64_XOR_REG_MEMBASE:
3944                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3945                         break;
3946
3947                 case OP_AMD64_ADD_MEMBASE_REG:
3948                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3949                         break;
3950                 case OP_AMD64_SUB_MEMBASE_REG:
3951                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3952                         break;
3953                 case OP_AMD64_AND_MEMBASE_REG:
3954                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3955                         break;
3956                 case OP_AMD64_OR_MEMBASE_REG:
3957                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3958                         break;
3959                 case OP_AMD64_XOR_MEMBASE_REG:
3960                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3961                         break;
3962
3963                 case OP_AMD64_ADD_MEMBASE_IMM:
3964                         g_assert (amd64_is_imm32 (ins->inst_imm));
3965                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3966                         break;
3967                 case OP_AMD64_SUB_MEMBASE_IMM:
3968                         g_assert (amd64_is_imm32 (ins->inst_imm));
3969                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3970                         break;
3971                 case OP_AMD64_AND_MEMBASE_IMM:
3972                         g_assert (amd64_is_imm32 (ins->inst_imm));
3973                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3974                         break;
3975                 case OP_AMD64_OR_MEMBASE_IMM:
3976                         g_assert (amd64_is_imm32 (ins->inst_imm));
3977                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3978                         break;
3979                 case OP_AMD64_XOR_MEMBASE_IMM:
3980                         g_assert (amd64_is_imm32 (ins->inst_imm));
3981                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3982                         break;
3983
3984                 case OP_BREAK:
3985                         amd64_breakpoint (code);
3986                         break;
3987                 case OP_RELAXED_NOP:
3988                         x86_prefix (code, X86_REP_PREFIX);
3989                         x86_nop (code);
3990                         break;
3991                 case OP_HARD_NOP:
3992                         x86_nop (code);
3993                         break;
3994                 case OP_NOP:
3995                 case OP_DUMMY_USE:
3996                 case OP_DUMMY_STORE:
3997                 case OP_DUMMY_ICONST:
3998                 case OP_DUMMY_R8CONST:
3999                 case OP_NOT_REACHED:
4000                 case OP_NOT_NULL:
4001                         break;
4002                 case OP_IL_SEQ_POINT:
4003                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4004                         break;
4005                 case OP_SEQ_POINT: {
4006                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4007                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4008                                 guint8 *label;
4009
4010                                 /* Load ss_tramp_var */
4011                                 /* This is equal to &ss_trampoline */
4012                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4013                                 /* Load the trampoline address */
4014                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4015                                 /* Call it if it is non-null */
4016                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4017                                 label = code;
4018                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4019                                 amd64_call_reg (code, AMD64_R11);
4020                                 amd64_patch (label, code);
4021                         }
4022
4023                         /*
4024                          * This is the address which is saved in seq points,
4025                          */
4026                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4027
4028                         if (cfg->compile_aot) {
4029                                 guint32 offset = code - cfg->native_code;
4030                                 guint32 val;
4031                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4032                                 guint8 *label;
4033
4034                                 /* Load info var */
4035                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4036                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4037                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4038                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4039                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4040                                 label = code;
4041                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4042                                 /* Call the trampoline */
4043                                 amd64_call_reg (code, AMD64_R11);
4044                                 amd64_patch (label, code);
4045                         } else {
4046                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4047                                 guint8 *label;
4048
4049                                 /*
4050                                  * Emit a test+branch against a constant, the constant will be overwritten
4051                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4052                                  */
4053                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4054                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4055                                 label = code;
4056                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4057
4058                                 g_assert (var);
4059                                 g_assert (var->opcode == OP_REGOFFSET);
4060                                 /* Load bp_tramp_var */
4061                                 /* This is equal to &bp_trampoline */
4062                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4063                                 /* Call the trampoline */
4064                                 amd64_call_membase (code, AMD64_R11, 0);
4065                                 amd64_patch (label, code);
4066                         }
4067                         /*
4068                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4069                          * to another IL offset.
4070                          */
4071                         x86_nop (code);
4072                         break;
4073                 }
4074                 case OP_ADDCC:
4075                 case OP_LADDCC:
4076                 case OP_LADD:
4077                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4078                         break;
4079                 case OP_ADC:
4080                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4081                         break;
4082                 case OP_ADD_IMM:
4083                 case OP_LADD_IMM:
4084                         g_assert (amd64_is_imm32 (ins->inst_imm));
4085                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4086                         break;
4087                 case OP_ADC_IMM:
4088                         g_assert (amd64_is_imm32 (ins->inst_imm));
4089                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4090                         break;
4091                 case OP_SUBCC:
4092                 case OP_LSUBCC:
4093                 case OP_LSUB:
4094                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4095                         break;
4096                 case OP_SBB:
4097                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4098                         break;
4099                 case OP_SUB_IMM:
4100                 case OP_LSUB_IMM:
4101                         g_assert (amd64_is_imm32 (ins->inst_imm));
4102                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4103                         break;
4104                 case OP_SBB_IMM:
4105                         g_assert (amd64_is_imm32 (ins->inst_imm));
4106                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4107                         break;
4108                 case OP_LAND:
4109                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4110                         break;
4111                 case OP_AND_IMM:
4112                 case OP_LAND_IMM:
4113                         g_assert (amd64_is_imm32 (ins->inst_imm));
4114                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4115                         break;
4116                 case OP_LMUL:
4117                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4118                         break;
4119                 case OP_MUL_IMM:
4120                 case OP_LMUL_IMM:
4121                 case OP_IMUL_IMM: {
4122                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4123
4124                         switch (ins->inst_imm) {
4125                         case 2:
4126                                 /* MOV r1, r2 */
4127                                 /* ADD r1, r1 */
4128                                 if (ins->dreg != ins->sreg1)
4129                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4130                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4131                                 break;
4132                         case 3:
4133                                 /* LEA r1, [r2 + r2*2] */
4134                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4135                                 break;
4136                         case 5:
4137                                 /* LEA r1, [r2 + r2*4] */
4138                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4139                                 break;
4140                         case 6:
4141                                 /* LEA r1, [r2 + r2*2] */
4142                                 /* ADD r1, r1          */
4143                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4144                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4145                                 break;
4146                         case 9:
4147                                 /* LEA r1, [r2 + r2*8] */
4148                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4149                                 break;
4150                         case 10:
4151                                 /* LEA r1, [r2 + r2*4] */
4152                                 /* ADD r1, r1          */
4153                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4154                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4155                                 break;
4156                         case 12:
4157                                 /* LEA r1, [r2 + r2*2] */
4158                                 /* SHL r1, 2           */
4159                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4160                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4161                                 break;
4162                         case 25:
4163                                 /* LEA r1, [r2 + r2*4] */
4164                                 /* LEA r1, [r1 + r1*4] */
4165                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4166                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4167                                 break;
4168                         case 100:
4169                                 /* LEA r1, [r2 + r2*4] */
4170                                 /* SHL r1, 2           */
4171                                 /* LEA r1, [r1 + r1*4] */
4172                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4173                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4174                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4175                                 break;
4176                         default:
4177                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4178                                 break;
4179                         }
4180                         break;
4181                 }
4182                 case OP_LDIV:
4183                 case OP_LREM:
4184                         /* Regalloc magic makes the div/rem cases the same */
4185                         if (ins->sreg2 == AMD64_RDX) {
4186                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4187                                 amd64_cdq (code);
4188                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4189                         } else {
4190                                 amd64_cdq (code);
4191                                 amd64_div_reg (code, ins->sreg2, TRUE);
4192                         }
4193                         break;
4194                 case OP_LDIV_UN:
4195                 case OP_LREM_UN:
4196                         if (ins->sreg2 == AMD64_RDX) {
4197                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4198                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4199                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4200                         } else {
4201                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4202                                 amd64_div_reg (code, ins->sreg2, FALSE);
4203                         }
4204                         break;
4205                 case OP_IDIV:
4206                 case OP_IREM:
4207                         if (ins->sreg2 == AMD64_RDX) {
4208                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4209                                 amd64_cdq_size (code, 4);
4210                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4211                         } else {
4212                                 amd64_cdq_size (code, 4);
4213                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4214                         }
4215                         break;
4216                 case OP_IDIV_UN:
4217                 case OP_IREM_UN:
4218                         if (ins->sreg2 == AMD64_RDX) {
4219                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4220                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4221                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4222                         } else {
4223                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4224                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4225                         }
4226                         break;
4227                 case OP_LMUL_OVF:
4228                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4229                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4230                         break;
4231                 case OP_LOR:
4232                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4233                         break;
4234                 case OP_OR_IMM:
4235                 case OP_LOR_IMM:
4236                         g_assert (amd64_is_imm32 (ins->inst_imm));
4237                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4238                         break;
4239                 case OP_LXOR:
4240                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4241                         break;
4242                 case OP_XOR_IMM:
4243                 case OP_LXOR_IMM:
4244                         g_assert (amd64_is_imm32 (ins->inst_imm));
4245                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4246                         break;
4247                 case OP_LSHL:
4248                         g_assert (ins->sreg2 == AMD64_RCX);
4249                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4250                         break;
4251                 case OP_LSHR:
4252                         g_assert (ins->sreg2 == AMD64_RCX);
4253                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4254                         break;
4255                 case OP_SHR_IMM:
4256                 case OP_LSHR_IMM:
4257                         g_assert (amd64_is_imm32 (ins->inst_imm));
4258                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4259                         break;
4260                 case OP_SHR_UN_IMM:
4261                         g_assert (amd64_is_imm32 (ins->inst_imm));
4262                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4263                         break;
4264                 case OP_LSHR_UN_IMM:
4265                         g_assert (amd64_is_imm32 (ins->inst_imm));
4266                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4267                         break;
4268                 case OP_LSHR_UN:
4269                         g_assert (ins->sreg2 == AMD64_RCX);
4270                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4271                         break;
4272                 case OP_SHL_IMM:
4273                 case OP_LSHL_IMM:
4274                         g_assert (amd64_is_imm32 (ins->inst_imm));
4275                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4276                         break;
4277
4278                 case OP_IADDCC:
4279                 case OP_IADD:
4280                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4281                         break;
4282                 case OP_IADC:
4283                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4284                         break;
4285                 case OP_IADD_IMM:
4286                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4287                         break;
4288                 case OP_IADC_IMM:
4289                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4290                         break;
4291                 case OP_ISUBCC:
4292                 case OP_ISUB:
4293                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4294                         break;
4295                 case OP_ISBB:
4296                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4297                         break;
4298                 case OP_ISUB_IMM:
4299                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4300                         break;
4301                 case OP_ISBB_IMM:
4302                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4303                         break;
4304                 case OP_IAND:
4305                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4306                         break;
4307                 case OP_IAND_IMM:
4308                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4309                         break;
4310                 case OP_IOR:
4311                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4312                         break;
4313                 case OP_IOR_IMM:
4314                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4315                         break;
4316                 case OP_IXOR:
4317                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4318                         break;
4319                 case OP_IXOR_IMM:
4320                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4321                         break;
4322                 case OP_INEG:
4323                         amd64_neg_reg_size (code, ins->sreg1, 4);
4324                         break;
4325                 case OP_INOT:
4326                         amd64_not_reg_size (code, ins->sreg1, 4);
4327                         break;
4328                 case OP_ISHL:
4329                         g_assert (ins->sreg2 == AMD64_RCX);
4330                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4331                         break;
4332                 case OP_ISHR:
4333                         g_assert (ins->sreg2 == AMD64_RCX);
4334                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4335                         break;
4336                 case OP_ISHR_IMM:
4337                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4338                         break;
4339                 case OP_ISHR_UN_IMM:
4340                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4341                         break;
4342                 case OP_ISHR_UN:
4343                         g_assert (ins->sreg2 == AMD64_RCX);
4344                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4345                         break;
4346                 case OP_ISHL_IMM:
4347                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4348                         break;
4349                 case OP_IMUL:
4350                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4351                         break;
4352                 case OP_IMUL_OVF:
4353                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4354                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4355                         break;
4356                 case OP_IMUL_OVF_UN:
4357                 case OP_LMUL_OVF_UN: {
4358                         /* the mul operation and the exception check should most likely be split */
4359                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4360                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4361                         /*g_assert (ins->sreg2 == X86_EAX);
4362                         g_assert (ins->dreg == X86_EAX);*/
4363                         if (ins->sreg2 == X86_EAX) {
4364                                 non_eax_reg = ins->sreg1;
4365                         } else if (ins->sreg1 == X86_EAX) {
4366                                 non_eax_reg = ins->sreg2;
4367                         } else {
4368                                 /* no need to save since we're going to store to it anyway */
4369                                 if (ins->dreg != X86_EAX) {
4370                                         saved_eax = TRUE;
4371                                         amd64_push_reg (code, X86_EAX);
4372                                 }
4373                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4374                                 non_eax_reg = ins->sreg2;
4375                         }
4376                         if (ins->dreg == X86_EDX) {
4377                                 if (!saved_eax) {
4378                                         saved_eax = TRUE;
4379                                         amd64_push_reg (code, X86_EAX);
4380                                 }
4381                         } else {
4382                                 saved_edx = TRUE;
4383                                 amd64_push_reg (code, X86_EDX);
4384                         }
4385                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4386                         /* save before the check since pop and mov don't change the flags */
4387                         if (ins->dreg != X86_EAX)
4388                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4389                         if (saved_edx)
4390                                 amd64_pop_reg (code, X86_EDX);
4391                         if (saved_eax)
4392                                 amd64_pop_reg (code, X86_EAX);
4393                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4394                         break;
4395                 }
4396                 case OP_ICOMPARE:
4397                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4398                         break;
4399                 case OP_ICOMPARE_IMM:
4400                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4401                         break;
4402                 case OP_IBEQ:
4403                 case OP_IBLT:
4404                 case OP_IBGT:
4405                 case OP_IBGE:
4406                 case OP_IBLE:
4407                 case OP_LBEQ:
4408                 case OP_LBLT:
4409                 case OP_LBGT:
4410                 case OP_LBGE:
4411                 case OP_LBLE:
4412                 case OP_IBNE_UN:
4413                 case OP_IBLT_UN:
4414                 case OP_IBGT_UN:
4415                 case OP_IBGE_UN:
4416                 case OP_IBLE_UN:
4417                 case OP_LBNE_UN:
4418                 case OP_LBLT_UN:
4419                 case OP_LBGT_UN:
4420                 case OP_LBGE_UN:
4421                 case OP_LBLE_UN:
4422                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4423                         break;
4424
4425                 case OP_CMOV_IEQ:
4426                 case OP_CMOV_IGE:
4427                 case OP_CMOV_IGT:
4428                 case OP_CMOV_ILE:
4429                 case OP_CMOV_ILT:
4430                 case OP_CMOV_INE_UN:
4431                 case OP_CMOV_IGE_UN:
4432                 case OP_CMOV_IGT_UN:
4433                 case OP_CMOV_ILE_UN:
4434                 case OP_CMOV_ILT_UN:
4435                 case OP_CMOV_LEQ:
4436                 case OP_CMOV_LGE:
4437                 case OP_CMOV_LGT:
4438                 case OP_CMOV_LLE:
4439                 case OP_CMOV_LLT:
4440                 case OP_CMOV_LNE_UN:
4441                 case OP_CMOV_LGE_UN:
4442                 case OP_CMOV_LGT_UN:
4443                 case OP_CMOV_LLE_UN:
4444                 case OP_CMOV_LLT_UN:
4445                         g_assert (ins->dreg == ins->sreg1);
4446                         /* This needs to operate on 64 bit values */
4447                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4448                         break;
4449
4450                 case OP_LNOT:
4451                         amd64_not_reg (code, ins->sreg1);
4452                         break;
4453                 case OP_LNEG:
4454                         amd64_neg_reg (code, ins->sreg1);
4455                         break;
4456
4457                 case OP_ICONST:
4458                 case OP_I8CONST:
4459                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4460                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4461                         else
4462                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4463                         break;
4464                 case OP_AOTCONST:
4465                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4466                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4467                         break;
4468                 case OP_JUMP_TABLE:
4469                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4470                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4471                         break;
4472                 case OP_MOVE:
4473                         if (ins->dreg != ins->sreg1)
4474                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4475                         break;
4476                 case OP_AMD64_SET_XMMREG_R4: {
4477                         if (cfg->r4fp) {
4478                                 if (ins->dreg != ins->sreg1)
4479                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4480                         } else {
4481                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4482                         }
4483                         break;
4484                 }
4485                 case OP_AMD64_SET_XMMREG_R8: {
4486                         if (ins->dreg != ins->sreg1)
4487                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4488                         break;
4489                 }
4490                 case OP_TAILCALL: {
4491                         MonoCallInst *call = (MonoCallInst*)ins;
4492                         int i, save_area_offset;
4493
4494                         g_assert (!cfg->method->save_lmf);
4495
4496                         /* Restore callee saved registers */
4497                         save_area_offset = cfg->arch.reg_save_area_offset;
4498                         for (i = 0; i < AMD64_NREG; ++i)
4499                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4500                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4501                                         save_area_offset += 8;
4502                                 }
4503
4504                         if (cfg->arch.omit_fp) {
4505                                 if (cfg->arch.stack_alloc_size)
4506                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4507                                 // FIXME:
4508                                 if (call->stack_usage)
4509                                         NOT_IMPLEMENTED;
4510                         } else {
4511                                 /* Copy arguments on the stack to our argument area */
4512                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4513                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4514                                         amd64_mov_membase_reg (code, AMD64_RBP, ARGS_OFFSET + i, AMD64_RAX, sizeof(mgreg_t));
4515                                 }
4516
4517 #ifdef TARGET_WIN32
4518                                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
4519                                 amd64_pop_reg (code, AMD64_RBP);
4520                                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
4521 #else
4522                                 amd64_leave (code);
4523 #endif
4524                         }
4525
4526                         offset = code - cfg->native_code;
4527                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4528                         if (cfg->compile_aot)
4529                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4530                         else
4531                                 amd64_set_reg_template (code, AMD64_R11);
4532                         amd64_jump_reg (code, AMD64_R11);
4533                         ins->flags |= MONO_INST_GC_CALLSITE;
4534                         ins->backend.pc_offset = code - cfg->native_code;
4535                         break;
4536                 }
4537                 case OP_CHECK_THIS:
4538                         /* ensure ins->sreg1 is not NULL */
4539                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4540                         break;
4541                 case OP_ARGLIST: {
4542                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4543                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4544                         break;
4545                 }
4546                 case OP_CALL:
4547                 case OP_FCALL:
4548                 case OP_RCALL:
4549                 case OP_LCALL:
4550                 case OP_VCALL:
4551                 case OP_VCALL2:
4552                 case OP_VOIDCALL:
4553                         call = (MonoCallInst*)ins;
4554                         /*
4555                          * The AMD64 ABI forces callers to know about varargs.
4556                          */
4557                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4558                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4559                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4560                                 /*
4561                                  * Since the unmanaged calling convention doesn't contain a
4562                                  * 'vararg' entry, we have to treat every pinvoke call as a
4563                                  * potential vararg call.
4564                                  */
4565                                 guint32 nregs, i;
4566                                 nregs = 0;
4567                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4568                                         if (call->used_fregs & (1 << i))
4569                                                 nregs ++;
4570                                 if (!nregs)
4571                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4572                                 else
4573                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4574                         }
4575
4576                         if (ins->flags & MONO_INST_HAS_METHOD)
4577                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4578                         else
4579                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4580                         ins->flags |= MONO_INST_GC_CALLSITE;
4581                         ins->backend.pc_offset = code - cfg->native_code;
4582                         code = emit_move_return_value (cfg, ins, code);
4583                         break;
4584                 case OP_FCALL_REG:
4585                 case OP_RCALL_REG:
4586                 case OP_LCALL_REG:
4587                 case OP_VCALL_REG:
4588                 case OP_VCALL2_REG:
4589                 case OP_VOIDCALL_REG:
4590                 case OP_CALL_REG:
4591                         call = (MonoCallInst*)ins;
4592
4593                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4594                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4595                                 ins->sreg1 = AMD64_R11;
4596                         }
4597
4598                         /*
4599                          * The AMD64 ABI forces callers to know about varargs.
4600                          */
4601                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4602                                 if (ins->sreg1 == AMD64_RAX) {
4603                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4604                                         ins->sreg1 = AMD64_R11;
4605                                 }
4606                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4607                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4608                                 /*
4609                                  * Since the unmanaged calling convention doesn't contain a
4610                                  * 'vararg' entry, we have to treat every pinvoke call as a
4611                                  * potential vararg call.
4612                                  */
4613                                 guint32 nregs, i;
4614                                 nregs = 0;
4615                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4616                                         if (call->used_fregs & (1 << i))
4617                                                 nregs ++;
4618                                 if (ins->sreg1 == AMD64_RAX) {
4619                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4620                                         ins->sreg1 = AMD64_R11;
4621                                 }
4622                                 if (!nregs)
4623                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4624                                 else
4625                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4626                         }
4627
4628                         amd64_call_reg (code, ins->sreg1);
4629                         ins->flags |= MONO_INST_GC_CALLSITE;
4630                         ins->backend.pc_offset = code - cfg->native_code;
4631                         code = emit_move_return_value (cfg, ins, code);
4632                         break;
4633                 case OP_FCALL_MEMBASE:
4634                 case OP_RCALL_MEMBASE:
4635                 case OP_LCALL_MEMBASE:
4636                 case OP_VCALL_MEMBASE:
4637                 case OP_VCALL2_MEMBASE:
4638                 case OP_VOIDCALL_MEMBASE:
4639                 case OP_CALL_MEMBASE:
4640                         call = (MonoCallInst*)ins;
4641
4642                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4643                         ins->flags |= MONO_INST_GC_CALLSITE;
4644                         ins->backend.pc_offset = code - cfg->native_code;
4645                         code = emit_move_return_value (cfg, ins, code);
4646                         break;
4647                 case OP_DYN_CALL: {
4648                         int i;
4649                         MonoInst *var = cfg->dyn_call_var;
4650                         guint8 *label;
4651
4652                         g_assert (var->opcode == OP_REGOFFSET);
4653
4654                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4655                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4656                         /* r10 = ftn */
4657                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4658
4659                         /* Save args buffer */
4660                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4661
4662                         /* Set fp arg regs */
4663                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4664                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4665                         label = code;
4666                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4667                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4668                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4669                         amd64_patch (label, code);
4670
4671                         /* Set stack args */
4672                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4673                                 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4674                                 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4675                         }
4676
4677                         /* Set argument registers */
4678                         for (i = 0; i < PARAM_REGS; ++i)
4679                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4680
4681                         /* Make the call */
4682                         amd64_call_reg (code, AMD64_R10);
4683
4684                         ins->flags |= MONO_INST_GC_CALLSITE;
4685                         ins->backend.pc_offset = code - cfg->native_code;
4686
4687                         /* Save result */
4688                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4689                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4690                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4691                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4692                         break;
4693                 }
4694                 case OP_AMD64_SAVE_SP_TO_LMF: {
4695                         MonoInst *lmf_var = cfg->lmf_var;
4696                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4697                         break;
4698                 }
4699                 case OP_X86_PUSH:
4700                         g_assert_not_reached ();
4701                         amd64_push_reg (code, ins->sreg1);
4702                         break;
4703                 case OP_X86_PUSH_IMM:
4704                         g_assert_not_reached ();
4705                         g_assert (amd64_is_imm32 (ins->inst_imm));
4706                         amd64_push_imm (code, ins->inst_imm);
4707                         break;
4708                 case OP_X86_PUSH_MEMBASE:
4709                         g_assert_not_reached ();
4710                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4711                         break;
4712                 case OP_X86_PUSH_OBJ: {
4713                         int size = ALIGN_TO (ins->inst_imm, 8);
4714
4715                         g_assert_not_reached ();
4716
4717                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4718                         amd64_push_reg (code, AMD64_RDI);
4719                         amd64_push_reg (code, AMD64_RSI);
4720                         amd64_push_reg (code, AMD64_RCX);
4721                         if (ins->inst_offset)
4722                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4723                         else
4724                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4725                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4726                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4727                         amd64_cld (code);
4728                         amd64_prefix (code, X86_REP_PREFIX);
4729                         amd64_movsd (code);
4730                         amd64_pop_reg (code, AMD64_RCX);
4731                         amd64_pop_reg (code, AMD64_RSI);
4732                         amd64_pop_reg (code, AMD64_RDI);
4733                         break;
4734                 }
4735                 case OP_GENERIC_CLASS_INIT: {
4736                         guint8 *jump;
4737
4738                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4739
4740                         amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4741                         jump = code;
4742                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4743
4744                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4745                         ins->flags |= MONO_INST_GC_CALLSITE;
4746                         ins->backend.pc_offset = code - cfg->native_code;
4747
4748                         x86_patch (jump, code);
4749                         break;
4750                 }
4751
4752                 case OP_X86_LEA:
4753                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4754                         break;
4755                 case OP_X86_LEA_MEMBASE:
4756                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4757                         break;
4758                 case OP_X86_XCHG:
4759                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4760                         break;
4761                 case OP_LOCALLOC:
4762                         /* keep alignment */
4763                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4764                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4765                         code = mono_emit_stack_alloc (cfg, code, ins);
4766                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4767                         if (cfg->param_area)
4768                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4769                         break;
4770                 case OP_LOCALLOC_IMM: {
4771                         guint32 size = ins->inst_imm;
4772                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4773
4774                         if (ins->flags & MONO_INST_INIT) {
4775                                 if (size < 64) {
4776                                         int i;
4777
4778                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4779                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4780
4781                                         for (i = 0; i < size; i += 8)
4782                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4783                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4784                                 } else {
4785                                         amd64_mov_reg_imm (code, ins->dreg, size);
4786                                         ins->sreg1 = ins->dreg;
4787
4788                                         code = mono_emit_stack_alloc (cfg, code, ins);
4789                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4790                                 }
4791                         } else {
4792                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4793                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4794                         }
4795                         if (cfg->param_area)
4796                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4797                         break;
4798                 }
4799                 case OP_THROW: {
4800                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4801                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4802                                              (gpointer)"mono_arch_throw_exception", FALSE);
4803                         ins->flags |= MONO_INST_GC_CALLSITE;
4804                         ins->backend.pc_offset = code - cfg->native_code;
4805                         break;
4806                 }
4807                 case OP_RETHROW: {
4808                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4809                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4810                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4811                         ins->flags |= MONO_INST_GC_CALLSITE;
4812                         ins->backend.pc_offset = code - cfg->native_code;
4813                         break;
4814                 }
4815                 case OP_CALL_HANDLER:
4816                         /* Align stack */
4817                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4818                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4819                         amd64_call_imm (code, 0);
4820                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4821                         /* Restore stack alignment */
4822                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4823                         break;
4824                 case OP_START_HANDLER: {
4825                         /* Even though we're saving RSP, use sizeof */
4826                         /* gpointer because spvar is of type IntPtr */
4827                         /* see: mono_create_spvar_for_region */
4828                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4829                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4830
4831                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4832                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FILTER)) &&
4833                                 cfg->param_area) {
4834                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4835                         }
4836                         break;
4837                 }
4838                 case OP_ENDFINALLY: {
4839                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4840                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4841                         amd64_ret (code);
4842                         break;
4843                 }
4844                 case OP_ENDFILTER: {
4845                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4846                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4847                         /* The local allocator will put the result into RAX */
4848                         amd64_ret (code);
4849                         break;
4850                 }
4851                 case OP_GET_EX_OBJ:
4852                         if (ins->dreg != AMD64_RAX)
4853                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4854                         break;
4855                 case OP_LABEL:
4856                         ins->inst_c0 = code - cfg->native_code;
4857                         break;
4858                 case OP_BR:
4859                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4860                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4861                         //break;
4862                                 if (ins->inst_target_bb->native_offset) {
4863                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4864                                 } else {
4865                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4866                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4867                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4868                                                 x86_jump8 (code, 0);
4869                                         else
4870                                                 x86_jump32 (code, 0);
4871                         }
4872                         break;
4873                 case OP_BR_REG:
4874                         amd64_jump_reg (code, ins->sreg1);
4875                         break;
4876                 case OP_ICNEQ:
4877                 case OP_ICGE:
4878                 case OP_ICLE:
4879                 case OP_ICGE_UN:
4880                 case OP_ICLE_UN:
4881
4882                 case OP_CEQ:
4883                 case OP_LCEQ:
4884                 case OP_ICEQ:
4885                 case OP_CLT:
4886                 case OP_LCLT:
4887                 case OP_ICLT:
4888                 case OP_CGT:
4889                 case OP_ICGT:
4890                 case OP_LCGT:
4891                 case OP_CLT_UN:
4892                 case OP_LCLT_UN:
4893                 case OP_ICLT_UN:
4894                 case OP_CGT_UN:
4895                 case OP_LCGT_UN:
4896                 case OP_ICGT_UN:
4897                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4898                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4899                         break;
4900                 case OP_COND_EXC_EQ:
4901                 case OP_COND_EXC_NE_UN:
4902                 case OP_COND_EXC_LT:
4903                 case OP_COND_EXC_LT_UN:
4904                 case OP_COND_EXC_GT:
4905                 case OP_COND_EXC_GT_UN:
4906                 case OP_COND_EXC_GE:
4907                 case OP_COND_EXC_GE_UN:
4908                 case OP_COND_EXC_LE:
4909                 case OP_COND_EXC_LE_UN:
4910                 case OP_COND_EXC_IEQ:
4911                 case OP_COND_EXC_INE_UN:
4912                 case OP_COND_EXC_ILT:
4913                 case OP_COND_EXC_ILT_UN:
4914                 case OP_COND_EXC_IGT:
4915                 case OP_COND_EXC_IGT_UN:
4916                 case OP_COND_EXC_IGE:
4917                 case OP_COND_EXC_IGE_UN:
4918                 case OP_COND_EXC_ILE:
4919                 case OP_COND_EXC_ILE_UN:
4920                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4921                         break;
4922                 case OP_COND_EXC_OV:
4923                 case OP_COND_EXC_NO:
4924                 case OP_COND_EXC_C:
4925                 case OP_COND_EXC_NC:
4926                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4927                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4928                         break;
4929                 case OP_COND_EXC_IOV:
4930                 case OP_COND_EXC_INO:
4931                 case OP_COND_EXC_IC:
4932                 case OP_COND_EXC_INC:
4933                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4934                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4935                         break;
4936
4937                 /* floating point opcodes */
4938                 case OP_R8CONST: {
4939                         double d = *(double *)ins->inst_p0;
4940
4941                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4942                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4943                         }
4944                         else {
4945                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4946                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4947                         }
4948                         break;
4949                 }
4950                 case OP_R4CONST: {
4951                         float f = *(float *)ins->inst_p0;
4952
4953                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4954                                 if (cfg->r4fp)
4955                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4956                                 else
4957                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4958                         }
4959                         else {
4960                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4961                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4962                                 if (!cfg->r4fp)
4963                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4964                         }
4965                         break;
4966                 }
4967                 case OP_STORER8_MEMBASE_REG:
4968                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4969                         break;
4970                 case OP_LOADR8_MEMBASE:
4971                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4972                         break;
4973                 case OP_STORER4_MEMBASE_REG:
4974                         if (cfg->r4fp) {
4975                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4976                         } else {
4977                                 /* This requires a double->single conversion */
4978                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
4979                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
4980                         }
4981                         break;
4982                 case OP_LOADR4_MEMBASE:
4983                         if (cfg->r4fp) {
4984                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4985                         } else {
4986                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4987                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4988                         }
4989                         break;
4990                 case OP_ICONV_TO_R4:
4991                         if (cfg->r4fp) {
4992                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4993                         } else {
4994                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4995                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4996                         }
4997                         break;
4998                 case OP_ICONV_TO_R8:
4999                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5000                         break;
5001                 case OP_LCONV_TO_R4:
5002                         if (cfg->r4fp) {
5003                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5004                         } else {
5005                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5006                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5007                         }
5008                         break;
5009                 case OP_LCONV_TO_R8:
5010                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5011                         break;
5012                 case OP_FCONV_TO_R4:
5013                         if (cfg->r4fp) {
5014                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5015                         } else {
5016                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5017                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5018                         }
5019                         break;
5020                 case OP_FCONV_TO_I1:
5021                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5022                         break;
5023                 case OP_FCONV_TO_U1:
5024                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5025                         break;
5026                 case OP_FCONV_TO_I2:
5027                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5028                         break;
5029                 case OP_FCONV_TO_U2:
5030                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5031                         break;
5032                 case OP_FCONV_TO_U4:
5033                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5034                         break;
5035                 case OP_FCONV_TO_I4:
5036                 case OP_FCONV_TO_I:
5037                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5038                         break;
5039                 case OP_FCONV_TO_I8:
5040                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5041                         break;
5042
5043                 case OP_RCONV_TO_I1:
5044                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5045                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5046                         break;
5047                 case OP_RCONV_TO_U1:
5048                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5049                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5050                         break;
5051                 case OP_RCONV_TO_I2:
5052                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5053                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5054                         break;
5055                 case OP_RCONV_TO_U2:
5056                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5057                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5058                         break;
5059                 case OP_RCONV_TO_I4:
5060                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5061                         break;
5062                 case OP_RCONV_TO_U4:
5063                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5064                         break;
5065                 case OP_RCONV_TO_I8:
5066                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5067                         break;
5068                 case OP_RCONV_TO_R8:
5069                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5070                         break;
5071                 case OP_RCONV_TO_R4:
5072                         if (ins->dreg != ins->sreg1)
5073                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5074                         break;
5075
5076                 case OP_LCONV_TO_R_UN: {
5077                         guint8 *br [2];
5078
5079                         /* Based on gcc code */
5080                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5081                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5082
5083                         /* Positive case */
5084                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5085                         br [1] = code; x86_jump8 (code, 0);
5086                         amd64_patch (br [0], code);
5087
5088                         /* Negative case */
5089                         /* Save to the red zone */
5090                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5091                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5092                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5093                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5094                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5095                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5096                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5097                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5098                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5099                         /* Restore */
5100                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5101                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5102                         amd64_patch (br [1], code);
5103                         break;
5104                 }
5105                 case OP_LCONV_TO_OVF_U4:
5106                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5107                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5108                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5109                         break;
5110                 case OP_LCONV_TO_OVF_I4_UN:
5111                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5112                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5113                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5114                         break;
5115                 case OP_FMOVE:
5116                         if (ins->dreg != ins->sreg1)
5117                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5118                         break;
5119                 case OP_RMOVE:
5120                         if (ins->dreg != ins->sreg1)
5121                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5122                         break;
5123                 case OP_MOVE_F_TO_I4:
5124                         if (cfg->r4fp) {
5125                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5126                         } else {
5127                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5128                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5129                         }
5130                         break;
5131                 case OP_MOVE_I4_TO_F:
5132                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5133                         if (!cfg->r4fp)
5134                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5135                         break;
5136                 case OP_MOVE_F_TO_I8:
5137                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5138                         break;
5139                 case OP_MOVE_I8_TO_F:
5140                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5141                         break;
5142                 case OP_FADD:
5143                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5144                         break;
5145                 case OP_FSUB:
5146                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5147                         break;
5148                 case OP_FMUL:
5149                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5150                         break;
5151                 case OP_FDIV:
5152                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5153                         break;
5154                 case OP_FNEG: {
5155                         static double r8_0 = -0.0;
5156
5157                         g_assert (ins->sreg1 == ins->dreg);
5158
5159                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5160                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5161                         break;
5162                 }
5163                 case OP_SIN:
5164                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5165                         break;
5166                 case OP_COS:
5167                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5168                         break;
5169                 case OP_ABS: {
5170                         static guint64 d = 0x7fffffffffffffffUL;
5171
5172                         g_assert (ins->sreg1 == ins->dreg);
5173
5174                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5175                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5176                         break;
5177                 }
5178                 case OP_SQRT:
5179                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5180                         break;
5181
5182                 case OP_RADD:
5183                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5184                         break;
5185                 case OP_RSUB:
5186                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5187                         break;
5188                 case OP_RMUL:
5189                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5190                         break;
5191                 case OP_RDIV:
5192                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5193                         break;
5194                 case OP_RNEG: {
5195                         static float r4_0 = -0.0;
5196
5197                         g_assert (ins->sreg1 == ins->dreg);
5198
5199                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5200                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5201                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5202                         break;
5203                 }
5204
5205                 case OP_IMIN:
5206                         g_assert (cfg->opt & MONO_OPT_CMOV);
5207                         g_assert (ins->dreg == ins->sreg1);
5208                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5209                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5210                         break;
5211                 case OP_IMIN_UN:
5212                         g_assert (cfg->opt & MONO_OPT_CMOV);
5213                         g_assert (ins->dreg == ins->sreg1);
5214                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5215                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5216                         break;
5217                 case OP_IMAX:
5218                         g_assert (cfg->opt & MONO_OPT_CMOV);
5219                         g_assert (ins->dreg == ins->sreg1);
5220                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5221                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5222                         break;
5223                 case OP_IMAX_UN:
5224                         g_assert (cfg->opt & MONO_OPT_CMOV);
5225                         g_assert (ins->dreg == ins->sreg1);
5226                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5227                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5228                         break;
5229                 case OP_LMIN:
5230                         g_assert (cfg->opt & MONO_OPT_CMOV);
5231                         g_assert (ins->dreg == ins->sreg1);
5232                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5233                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5234                         break;
5235                 case OP_LMIN_UN:
5236                         g_assert (cfg->opt & MONO_OPT_CMOV);
5237                         g_assert (ins->dreg == ins->sreg1);
5238                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5239                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5240                         break;
5241                 case OP_LMAX:
5242                         g_assert (cfg->opt & MONO_OPT_CMOV);
5243                         g_assert (ins->dreg == ins->sreg1);
5244                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5245                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5246                         break;
5247                 case OP_LMAX_UN:
5248                         g_assert (cfg->opt & MONO_OPT_CMOV);
5249                         g_assert (ins->dreg == ins->sreg1);
5250                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5251                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5252                         break;
5253                 case OP_X86_FPOP:
5254                         break;
5255                 case OP_FCOMPARE:
5256                         /*
5257                          * The two arguments are swapped because the fbranch instructions
5258                          * depend on this for the non-sse case to work.
5259                          */
5260                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5261                         break;
5262                 case OP_RCOMPARE:
5263                         /*
5264                          * FIXME: Get rid of this.
5265                          * The two arguments are swapped because the fbranch instructions
5266                          * depend on this for the non-sse case to work.
5267                          */
5268                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5269                         break;
5270                 case OP_FCNEQ:
5271                 case OP_FCEQ: {
5272                         /* zeroing the register at the start results in
5273                          * shorter and faster code (we can also remove the widening op)
5274                          */
5275                         guchar *unordered_check;
5276
5277                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5278                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5279                         unordered_check = code;
5280                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5281
5282                         if (ins->opcode == OP_FCEQ) {
5283                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5284                                 amd64_patch (unordered_check, code);
5285                         } else {
5286                                 guchar *jump_to_end;
5287                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5288                                 jump_to_end = code;
5289                                 x86_jump8 (code, 0);
5290                                 amd64_patch (unordered_check, code);
5291                                 amd64_inc_reg (code, ins->dreg);
5292                                 amd64_patch (jump_to_end, code);
5293                         }
5294                         break;
5295                 }
5296                 case OP_FCLT:
5297                 case OP_FCLT_UN: {
5298                         /* zeroing the register at the start results in
5299                          * shorter and faster code (we can also remove the widening op)
5300                          */
5301                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5302                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5303                         if (ins->opcode == OP_FCLT_UN) {
5304                                 guchar *unordered_check = code;
5305                                 guchar *jump_to_end;
5306                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5307                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5308                                 jump_to_end = code;
5309                                 x86_jump8 (code, 0);
5310                                 amd64_patch (unordered_check, code);
5311                                 amd64_inc_reg (code, ins->dreg);
5312                                 amd64_patch (jump_to_end, code);
5313                         } else {
5314                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5315                         }
5316                         break;
5317                 }
5318                 case OP_FCLE: {
5319                         guchar *unordered_check;
5320                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5321                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5322                         unordered_check = code;
5323                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5324                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5325                         amd64_patch (unordered_check, code);
5326                         break;
5327                 }
5328                 case OP_FCGT:
5329                 case OP_FCGT_UN: {
5330                         /* zeroing the register at the start results in
5331                          * shorter and faster code (we can also remove the widening op)
5332                          */
5333                         guchar *unordered_check;
5334
5335                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5336                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5337                         if (ins->opcode == OP_FCGT) {
5338                                 unordered_check = code;
5339                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5340                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5341                                 amd64_patch (unordered_check, code);
5342                         } else {
5343                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5344                         }
5345                         break;
5346                 }
5347                 case OP_FCGE: {
5348                         guchar *unordered_check;
5349                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5350                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5351                         unordered_check = code;
5352                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5353                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5354                         amd64_patch (unordered_check, code);
5355                         break;
5356                 }
5357
5358                 case OP_RCEQ:
5359                 case OP_RCGT:
5360                 case OP_RCLT:
5361                 case OP_RCLT_UN:
5362                 case OP_RCGT_UN: {
5363                         int x86_cond;
5364                         gboolean unordered = FALSE;
5365
5366                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5367                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5368
5369                         switch (ins->opcode) {
5370                         case OP_RCEQ:
5371                                 x86_cond = X86_CC_EQ;
5372                                 break;
5373                         case OP_RCGT:
5374                                 x86_cond = X86_CC_LT;
5375                                 break;
5376                         case OP_RCLT:
5377                                 x86_cond = X86_CC_GT;
5378                                 break;
5379                         case OP_RCLT_UN:
5380                                 x86_cond = X86_CC_GT;
5381                                 unordered = TRUE;
5382                                 break;
5383                         case OP_RCGT_UN:
5384                                 x86_cond = X86_CC_LT;
5385                                 unordered = TRUE;
5386                                 break;
5387                         default:
5388                                 g_assert_not_reached ();
5389                                 break;
5390                         }
5391
5392                         if (unordered) {
5393                                 guchar *unordered_check;
5394                                 guchar *jump_to_end;
5395
5396                                 unordered_check = code;
5397                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5398                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5399                                 jump_to_end = code;
5400                                 x86_jump8 (code, 0);
5401                                 amd64_patch (unordered_check, code);
5402                                 amd64_inc_reg (code, ins->dreg);
5403                                 amd64_patch (jump_to_end, code);
5404                         } else {
5405                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5406                         }
5407                         break;
5408                 }
5409                 case OP_FCLT_MEMBASE:
5410                 case OP_FCGT_MEMBASE:
5411                 case OP_FCLT_UN_MEMBASE:
5412                 case OP_FCGT_UN_MEMBASE:
5413                 case OP_FCEQ_MEMBASE: {
5414                         guchar *unordered_check, *jump_to_end;
5415                         int x86_cond;
5416
5417                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5418                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5419
5420                         switch (ins->opcode) {
5421                         case OP_FCEQ_MEMBASE:
5422                                 x86_cond = X86_CC_EQ;
5423                                 break;
5424                         case OP_FCLT_MEMBASE:
5425                         case OP_FCLT_UN_MEMBASE:
5426                                 x86_cond = X86_CC_LT;
5427                                 break;
5428                         case OP_FCGT_MEMBASE:
5429                         case OP_FCGT_UN_MEMBASE:
5430                                 x86_cond = X86_CC_GT;
5431                                 break;
5432                         default:
5433                                 g_assert_not_reached ();
5434                         }
5435
5436                         unordered_check = code;
5437                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5438                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5439
5440                         switch (ins->opcode) {
5441                         case OP_FCEQ_MEMBASE:
5442                         case OP_FCLT_MEMBASE:
5443                         case OP_FCGT_MEMBASE:
5444                                 amd64_patch (unordered_check, code);
5445                                 break;
5446                         case OP_FCLT_UN_MEMBASE:
5447                         case OP_FCGT_UN_MEMBASE:
5448                                 jump_to_end = code;
5449                                 x86_jump8 (code, 0);
5450                                 amd64_patch (unordered_check, code);
5451                                 amd64_inc_reg (code, ins->dreg);
5452                                 amd64_patch (jump_to_end, code);
5453                                 break;
5454                         default:
5455                                 break;
5456                         }
5457                         break;
5458                 }
5459                 case OP_FBEQ: {
5460                         guchar *jump = code;
5461                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5462                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5463                         amd64_patch (jump, code);
5464                         break;
5465                 }
5466                 case OP_FBNE_UN:
5467                         /* Branch if C013 != 100 */
5468                         /* branch if !ZF or (PF|CF) */
5469                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5470                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5471                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5472                         break;
5473                 case OP_FBLT:
5474                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5475                         break;
5476                 case OP_FBLT_UN:
5477                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5478                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5479                         break;
5480                 case OP_FBGT:
5481                 case OP_FBGT_UN:
5482                         if (ins->opcode == OP_FBGT) {
5483                                 guchar *br1;
5484
5485                                 /* skip branch if C1=1 */
5486                                 br1 = code;
5487                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5488                                 /* branch if (C0 | C3) = 1 */
5489                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5490                                 amd64_patch (br1, code);
5491                                 break;
5492                         } else {
5493                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5494                         }
5495                         break;
5496                 case OP_FBGE: {
5497                         /* Branch if C013 == 100 or 001 */
5498                         guchar *br1;
5499
5500                         /* skip branch if C1=1 */
5501                         br1 = code;
5502                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5503                         /* branch if (C0 | C3) = 1 */
5504                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5505                         amd64_patch (br1, code);
5506                         break;
5507                 }
5508                 case OP_FBGE_UN:
5509                         /* Branch if C013 == 000 */
5510                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5511                         break;
5512                 case OP_FBLE: {
5513                         /* Branch if C013=000 or 100 */
5514                         guchar *br1;
5515
5516                         /* skip branch if C1=1 */
5517                         br1 = code;
5518                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5519                         /* branch if C0=0 */
5520                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5521                         amd64_patch (br1, code);
5522                         break;
5523                 }
5524                 case OP_FBLE_UN:
5525                         /* Branch if C013 != 001 */
5526                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5527                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5528                         break;
5529                 case OP_CKFINITE:
5530                         /* Transfer value to the fp stack */
5531                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5532                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5533                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5534
5535                         amd64_push_reg (code, AMD64_RAX);
5536                         amd64_fxam (code);
5537                         amd64_fnstsw (code);
5538                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5539                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5540                         amd64_pop_reg (code, AMD64_RAX);
5541                         amd64_fstp (code, 0);
5542                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5543                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5544                         break;
5545                 case OP_TLS_GET: {
5546                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5547                         break;
5548                 }
5549                 case OP_TLS_SET: {
5550                         code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5551                         break;
5552                 }
5553                 case OP_MEMORY_BARRIER: {
5554                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5555                                 x86_mfence (code);
5556                         break;
5557                 }
5558                 case OP_ATOMIC_ADD_I4:
5559                 case OP_ATOMIC_ADD_I8: {
5560                         int dreg = ins->dreg;
5561                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5562
5563                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5564                                 dreg = AMD64_R11;
5565
5566                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5567                         amd64_prefix (code, X86_LOCK_PREFIX);
5568                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5569                         /* dreg contains the old value, add with sreg2 value */
5570                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5571
5572                         if (ins->dreg != dreg)
5573                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5574
5575                         break;
5576                 }
5577                 case OP_ATOMIC_EXCHANGE_I4:
5578                 case OP_ATOMIC_EXCHANGE_I8: {
5579                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5580
5581                         /* LOCK prefix is implied. */
5582                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5583                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5584                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5585                         break;
5586                 }
5587                 case OP_ATOMIC_CAS_I4:
5588                 case OP_ATOMIC_CAS_I8: {
5589                         guint32 size;
5590
5591                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5592                                 size = 8;
5593                         else
5594                                 size = 4;
5595
5596                         /*
5597                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5598                          * an explanation of how this works.
5599                          */
5600                         g_assert (ins->sreg3 == AMD64_RAX);
5601                         g_assert (ins->sreg1 != AMD64_RAX);
5602                         g_assert (ins->sreg1 != ins->sreg2);
5603
5604                         amd64_prefix (code, X86_LOCK_PREFIX);
5605                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5606
5607                         if (ins->dreg != AMD64_RAX)
5608                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5609                         break;
5610                 }
5611                 case OP_ATOMIC_LOAD_I1: {
5612                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5613                         break;
5614                 }
5615                 case OP_ATOMIC_LOAD_U1: {
5616                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5617                         break;
5618                 }
5619                 case OP_ATOMIC_LOAD_I2: {
5620                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5621                         break;
5622                 }
5623                 case OP_ATOMIC_LOAD_U2: {
5624                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5625                         break;
5626                 }
5627                 case OP_ATOMIC_LOAD_I4: {
5628                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5629                         break;
5630                 }
5631                 case OP_ATOMIC_LOAD_U4:
5632                 case OP_ATOMIC_LOAD_I8:
5633                 case OP_ATOMIC_LOAD_U8: {
5634                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5635                         break;
5636                 }
5637                 case OP_ATOMIC_LOAD_R4: {
5638                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5639                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5640                         break;
5641                 }
5642                 case OP_ATOMIC_LOAD_R8: {
5643                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5644                         break;
5645                 }
5646                 case OP_ATOMIC_STORE_I1:
5647                 case OP_ATOMIC_STORE_U1:
5648                 case OP_ATOMIC_STORE_I2:
5649                 case OP_ATOMIC_STORE_U2:
5650                 case OP_ATOMIC_STORE_I4:
5651                 case OP_ATOMIC_STORE_U4:
5652                 case OP_ATOMIC_STORE_I8:
5653                 case OP_ATOMIC_STORE_U8: {
5654                         int size;
5655
5656                         switch (ins->opcode) {
5657                         case OP_ATOMIC_STORE_I1:
5658                         case OP_ATOMIC_STORE_U1:
5659                                 size = 1;
5660                                 break;
5661                         case OP_ATOMIC_STORE_I2:
5662                         case OP_ATOMIC_STORE_U2:
5663                                 size = 2;
5664                                 break;
5665                         case OP_ATOMIC_STORE_I4:
5666                         case OP_ATOMIC_STORE_U4:
5667                                 size = 4;
5668                                 break;
5669                         case OP_ATOMIC_STORE_I8:
5670                         case OP_ATOMIC_STORE_U8:
5671                                 size = 8;
5672                                 break;
5673                         }
5674
5675                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5676
5677                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5678                                 x86_mfence (code);
5679                         break;
5680                 }
5681                 case OP_ATOMIC_STORE_R4: {
5682                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5683                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5684
5685                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5686                                 x86_mfence (code);
5687                         break;
5688                 }
5689                 case OP_ATOMIC_STORE_R8: {
5690                         x86_nop (code);
5691                         x86_nop (code);
5692                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5693                         x86_nop (code);
5694                         x86_nop (code);
5695
5696                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5697                                 x86_mfence (code);
5698                         break;
5699                 }
5700                 case OP_CARD_TABLE_WBARRIER: {
5701                         int ptr = ins->sreg1;
5702                         int value = ins->sreg2;
5703                         guchar *br = 0;
5704                         int nursery_shift, card_table_shift;
5705                         gpointer card_table_mask;
5706                         size_t nursery_size;
5707
5708                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5709                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5710                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5711
5712                         /*If either point to the stack we can simply avoid the WB. This happens due to
5713                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5714                          */
5715                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5716                                 continue;
5717
5718                         /*
5719                          * We need one register we can clobber, we choose EDX and make sreg1
5720                          * fixed EAX to work around limitations in the local register allocator.
5721                          * sreg2 might get allocated to EDX, but that is not a problem since
5722                          * we use it before clobbering EDX.
5723                          */
5724                         g_assert (ins->sreg1 == AMD64_RAX);
5725
5726                         /*
5727                          * This is the code we produce:
5728                          *
5729                          *   edx = value
5730                          *   edx >>= nursery_shift
5731                          *   cmp edx, (nursery_start >> nursery_shift)
5732                          *   jne done
5733                          *   edx = ptr
5734                          *   edx >>= card_table_shift
5735                          *   edx += cardtable
5736                          *   [edx] = 1
5737                          * done:
5738                          */
5739
5740                         if (mono_gc_card_table_nursery_check ()) {
5741                                 if (value != AMD64_RDX)
5742                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5743                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5744                                 if (shifted_nursery_start >> 31) {
5745                                         /*
5746                                          * The value we need to compare against is 64 bits, so we need
5747                                          * another spare register.  We use RBX, which we save and
5748                                          * restore.
5749                                          */
5750                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5751                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5752                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5753                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5754                                 } else {
5755                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5756                                 }
5757                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5758                         }
5759                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5760                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5761                         if (card_table_mask)
5762                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5763
5764                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5765                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5766
5767                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5768
5769                         if (mono_gc_card_table_nursery_check ())
5770                                 x86_patch (br, code);
5771                         break;
5772                 }
5773 #ifdef MONO_ARCH_SIMD_INTRINSICS
5774                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5775                 case OP_ADDPS:
5776                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5777                         break;
5778                 case OP_DIVPS:
5779                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5780                         break;
5781                 case OP_MULPS:
5782                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5783                         break;
5784                 case OP_SUBPS:
5785                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5786                         break;
5787                 case OP_MAXPS:
5788                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5789                         break;
5790                 case OP_MINPS:
5791                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5792                         break;
5793                 case OP_COMPPS:
5794                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5795                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5796                         break;
5797                 case OP_ANDPS:
5798                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5799                         break;
5800                 case OP_ANDNPS:
5801                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5802                         break;
5803                 case OP_ORPS:
5804                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5805                         break;
5806                 case OP_XORPS:
5807                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5808                         break;
5809                 case OP_SQRTPS:
5810                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5811                         break;
5812                 case OP_RSQRTPS:
5813                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5814                         break;
5815                 case OP_RCPPS:
5816                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5817                         break;
5818                 case OP_ADDSUBPS:
5819                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5820                         break;
5821                 case OP_HADDPS:
5822                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5823                         break;
5824                 case OP_HSUBPS:
5825                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5826                         break;
5827                 case OP_DUPPS_HIGH:
5828                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5829                         break;
5830                 case OP_DUPPS_LOW:
5831                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5832                         break;
5833
5834                 case OP_PSHUFLEW_HIGH:
5835                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5836                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5837                         break;
5838                 case OP_PSHUFLEW_LOW:
5839                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5840                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5841                         break;
5842                 case OP_PSHUFLED:
5843                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5844                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5845                         break;
5846                 case OP_SHUFPS:
5847                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5848                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5849                         break;
5850                 case OP_SHUFPD:
5851                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5852                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5853                         break;
5854
5855                 case OP_ADDPD:
5856                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5857                         break;
5858                 case OP_DIVPD:
5859                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5860                         break;
5861                 case OP_MULPD:
5862                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5863                         break;
5864                 case OP_SUBPD:
5865                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5866                         break;
5867                 case OP_MAXPD:
5868                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5869                         break;
5870                 case OP_MINPD:
5871                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5872                         break;
5873                 case OP_COMPPD:
5874                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5875                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5876                         break;
5877                 case OP_ANDPD:
5878                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5879                         break;
5880                 case OP_ANDNPD:
5881                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5882                         break;
5883                 case OP_ORPD:
5884                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5885                         break;
5886                 case OP_XORPD:
5887                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5888                         break;
5889                 case OP_SQRTPD:
5890                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5891                         break;
5892                 case OP_ADDSUBPD:
5893                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5894                         break;
5895                 case OP_HADDPD:
5896                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5897                         break;
5898                 case OP_HSUBPD:
5899                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5900                         break;
5901                 case OP_DUPPD:
5902                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5903                         break;
5904
5905                 case OP_EXTRACT_MASK:
5906                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5907                         break;
5908
5909                 case OP_PAND:
5910                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5911                         break;
5912                 case OP_POR:
5913                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5914                         break;
5915                 case OP_PXOR:
5916                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5917                         break;
5918
5919                 case OP_PADDB:
5920                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5921                         break;
5922                 case OP_PADDW:
5923                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5924                         break;
5925                 case OP_PADDD:
5926                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5927                         break;
5928                 case OP_PADDQ:
5929                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5930                         break;
5931
5932                 case OP_PSUBB:
5933                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5934                         break;
5935                 case OP_PSUBW:
5936                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5937                         break;
5938                 case OP_PSUBD:
5939                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5940                         break;
5941                 case OP_PSUBQ:
5942                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5943                         break;
5944
5945                 case OP_PMAXB_UN:
5946                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948                 case OP_PMAXW_UN:
5949                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5950                         break;
5951                 case OP_PMAXD_UN:
5952                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5953                         break;
5954
5955                 case OP_PMAXB:
5956                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5957                         break;
5958                 case OP_PMAXW:
5959                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5960                         break;
5961                 case OP_PMAXD:
5962                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5963                         break;
5964
5965                 case OP_PAVGB_UN:
5966                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5967                         break;
5968                 case OP_PAVGW_UN:
5969                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5970                         break;
5971
5972                 case OP_PMINB_UN:
5973                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_PMINW_UN:
5976                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978                 case OP_PMIND_UN:
5979                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5980                         break;
5981
5982                 case OP_PMINB:
5983                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985                 case OP_PMINW:
5986                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5987                         break;
5988                 case OP_PMIND:
5989                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5990                         break;
5991
5992                 case OP_PCMPEQB:
5993                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995                 case OP_PCMPEQW:
5996                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5997                         break;
5998                 case OP_PCMPEQD:
5999                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6000                         break;
6001                 case OP_PCMPEQQ:
6002                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6003                         break;
6004
6005                 case OP_PCMPGTB:
6006                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6007                         break;
6008                 case OP_PCMPGTW:
6009                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6010                         break;
6011                 case OP_PCMPGTD:
6012                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6013                         break;
6014                 case OP_PCMPGTQ:
6015                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6016                         break;
6017
6018                 case OP_PSUM_ABS_DIFF:
6019                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6020                         break;
6021
6022                 case OP_UNPACK_LOWB:
6023                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6024                         break;
6025                 case OP_UNPACK_LOWW:
6026                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028                 case OP_UNPACK_LOWD:
6029                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6030                         break;
6031                 case OP_UNPACK_LOWQ:
6032                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034                 case OP_UNPACK_LOWPS:
6035                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_UNPACK_LOWPD:
6038                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040
6041                 case OP_UNPACK_HIGHB:
6042                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6043                         break;
6044                 case OP_UNPACK_HIGHW:
6045                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047                 case OP_UNPACK_HIGHD:
6048                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6049                         break;
6050                 case OP_UNPACK_HIGHQ:
6051                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6052                         break;
6053                 case OP_UNPACK_HIGHPS:
6054                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6055                         break;
6056                 case OP_UNPACK_HIGHPD:
6057                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6058                         break;
6059
6060                 case OP_PACKW:
6061                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6062                         break;
6063                 case OP_PACKD:
6064                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6065                         break;
6066                 case OP_PACKW_UN:
6067                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6068                         break;
6069                 case OP_PACKD_UN:
6070                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6071                         break;
6072
6073                 case OP_PADDB_SAT_UN:
6074                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076                 case OP_PSUBB_SAT_UN:
6077                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6078                         break;
6079                 case OP_PADDW_SAT_UN:
6080                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6081                         break;
6082                 case OP_PSUBW_SAT_UN:
6083                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6084                         break;
6085
6086                 case OP_PADDB_SAT:
6087                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089                 case OP_PSUBB_SAT:
6090                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092                 case OP_PADDW_SAT:
6093                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095                 case OP_PSUBW_SAT:
6096                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6097                         break;
6098
6099                 case OP_PMULW:
6100                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102                 case OP_PMULD:
6103                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105                 case OP_PMULQ:
6106                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108                 case OP_PMULW_HIGH_UN:
6109                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6110                         break;
6111                 case OP_PMULW_HIGH:
6112                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6113                         break;
6114
6115                 case OP_PSHRW:
6116                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6117                         break;
6118                 case OP_PSHRW_REG:
6119                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6120                         break;
6121
6122                 case OP_PSARW:
6123                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6124                         break;
6125                 case OP_PSARW_REG:
6126                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6127                         break;
6128
6129                 case OP_PSHLW:
6130                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6131                         break;
6132                 case OP_PSHLW_REG:
6133                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6134                         break;
6135
6136                 case OP_PSHRD:
6137                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6138                         break;
6139                 case OP_PSHRD_REG:
6140                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6141                         break;
6142
6143                 case OP_PSARD:
6144                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6145                         break;
6146                 case OP_PSARD_REG:
6147                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6148                         break;
6149
6150                 case OP_PSHLD:
6151                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6152                         break;
6153                 case OP_PSHLD_REG:
6154                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6155                         break;
6156
6157                 case OP_PSHRQ:
6158                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6159                         break;
6160                 case OP_PSHRQ_REG:
6161                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6162                         break;
6163
6164                 /*TODO: This is appart of the sse spec but not added
6165                 case OP_PSARQ:
6166                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6167                         break;
6168                 case OP_PSARQ_REG:
6169                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6170                         break;
6171                 */
6172
6173                 case OP_PSHLQ:
6174                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6175                         break;
6176                 case OP_PSHLQ_REG:
6177                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6178                         break;
6179                 case OP_CVTDQ2PD:
6180                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6181                         break;
6182                 case OP_CVTDQ2PS:
6183                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6184                         break;
6185                 case OP_CVTPD2DQ:
6186                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6187                         break;
6188                 case OP_CVTPD2PS:
6189                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6190                         break;
6191                 case OP_CVTPS2DQ:
6192                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6193                         break;
6194                 case OP_CVTPS2PD:
6195                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6196                         break;
6197                 case OP_CVTTPD2DQ:
6198                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6199                         break;
6200                 case OP_CVTTPS2DQ:
6201                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6202                         break;
6203
6204                 case OP_ICONV_TO_X:
6205                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6206                         break;
6207                 case OP_EXTRACT_I4:
6208                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6209                         break;
6210                 case OP_EXTRACT_I8:
6211                         if (ins->inst_c0) {
6212                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6213                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6214                         } else {
6215                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6216                         }
6217                         break;
6218                 case OP_EXTRACT_I1:
6219                 case OP_EXTRACT_U1:
6220                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6221                         if (ins->inst_c0)
6222                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6223                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6224                         break;
6225                 case OP_EXTRACT_I2:
6226                 case OP_EXTRACT_U2:
6227                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6228                         if (ins->inst_c0)
6229                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6230                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6231                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6232                         break;
6233                 case OP_EXTRACT_R8:
6234                         if (ins->inst_c0)
6235                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6236                         else
6237                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6238                         break;
6239                 case OP_INSERT_I2:
6240                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6241                         break;
6242                 case OP_EXTRACTX_U2:
6243                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6244                         break;
6245                 case OP_INSERTX_U1_SLOW:
6246                         /*sreg1 is the extracted ireg (scratch)
6247                         /sreg2 is the to be inserted ireg (scratch)
6248                         /dreg is the xreg to receive the value*/
6249
6250                         /*clear the bits from the extracted word*/
6251                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6252                         /*shift the value to insert if needed*/
6253                         if (ins->inst_c0 & 1)
6254                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6255                         /*join them together*/
6256                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6257                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6258                         break;
6259                 case OP_INSERTX_I4_SLOW:
6260                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6261                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6262                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6263                         break;
6264                 case OP_INSERTX_I8_SLOW:
6265                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6266                         if (ins->inst_c0)
6267                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6268                         else
6269                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6270                         break;
6271
6272                 case OP_INSERTX_R4_SLOW:
6273                         switch (ins->inst_c0) {
6274                         case 0:
6275                                 if (cfg->r4fp)
6276                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6277                                 else
6278                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6279                                 break;
6280                         case 1:
6281                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6282                                 if (cfg->r4fp)
6283                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6284                                 else
6285                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6286                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6287                                 break;
6288                         case 2:
6289                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6290                                 if (cfg->r4fp)
6291                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6292                                 else
6293                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6294                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6295                                 break;
6296                         case 3:
6297                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6298                                 if (cfg->r4fp)
6299                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6300                                 else
6301                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6302                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6303                                 break;
6304                         }
6305                         break;
6306                 case OP_INSERTX_R8_SLOW:
6307                         if (ins->inst_c0)
6308                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6309                         else
6310                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6311                         break;
6312                 case OP_STOREX_MEMBASE_REG:
6313                 case OP_STOREX_MEMBASE:
6314                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6315                         break;
6316                 case OP_LOADX_MEMBASE:
6317                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6318                         break;
6319                 case OP_LOADX_ALIGNED_MEMBASE:
6320                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6321                         break;
6322                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6323                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6324                         break;
6325                 case OP_STOREX_NTA_MEMBASE_REG:
6326                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6327                         break;
6328                 case OP_PREFETCH_MEMBASE:
6329                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6330                         break;
6331
6332                 case OP_XMOVE:
6333                         /*FIXME the peephole pass should have killed this*/
6334                         if (ins->dreg != ins->sreg1)
6335                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6336                         break;
6337                 case OP_XZERO:
6338                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6339                         break;
6340                 case OP_XONES:
6341                         amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6342                         break;
6343                 case OP_ICONV_TO_R4_RAW:
6344                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6345                         if (!cfg->r4fp)
6346                           amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6347                         break;
6348
6349                 case OP_FCONV_TO_R8_X:
6350                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6351                         break;
6352
6353                 case OP_XCONV_R8_TO_I4:
6354                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6355                         switch (ins->backend.source_opcode) {
6356                         case OP_FCONV_TO_I1:
6357                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6358                                 break;
6359                         case OP_FCONV_TO_U1:
6360                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6361                                 break;
6362                         case OP_FCONV_TO_I2:
6363                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6364                                 break;
6365                         case OP_FCONV_TO_U2:
6366                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6367                                 break;
6368                         }
6369                         break;
6370
6371                 case OP_EXPAND_I2:
6372                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6373                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6374                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6375                         break;
6376                 case OP_EXPAND_I4:
6377                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6378                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6379                         break;
6380                 case OP_EXPAND_I8:
6381                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6382                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6383                         break;
6384                 case OP_EXPAND_R4:
6385                         if (cfg->r4fp) {
6386                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6387                         } else {
6388                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6389                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6390                         }
6391                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6392                         break;
6393                 case OP_EXPAND_R8:
6394                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6395                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6396                         break;
6397 #endif
6398                 case OP_LIVERANGE_START: {
6399                         if (cfg->verbose_level > 1)
6400                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6401                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6402                         break;
6403                 }
6404                 case OP_LIVERANGE_END: {
6405                         if (cfg->verbose_level > 1)
6406                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6407                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6408                         break;
6409                 }
6410                 case OP_GC_SAFE_POINT: {
6411                         guint8 *br [1];
6412
6413                         g_assert (mono_threads_is_coop_enabled ());
6414
6415                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6416                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6417                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6418                         amd64_patch (br[0], code);
6419                         break;
6420                 }
6421
6422                 case OP_GC_LIVENESS_DEF:
6423                 case OP_GC_LIVENESS_USE:
6424                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6425                         ins->backend.pc_offset = code - cfg->native_code;
6426                         break;
6427                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6428                         ins->backend.pc_offset = code - cfg->native_code;
6429                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6430                         break;
6431                 case OP_GET_LAST_ERROR:
6432                         emit_get_last_error(code, ins->dreg);
6433                         break;
6434                 default:
6435                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6436                         g_assert_not_reached ();
6437                 }
6438
6439                 if ((code - cfg->native_code - offset) > max_len) {
6440                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6441                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6442                         g_assert_not_reached ();
6443                 }
6444         }
6445
6446         cfg->code_len = code - cfg->native_code;
6447 }
6448
6449 #endif /* DISABLE_JIT */
6450
6451 void
6452 mono_arch_register_lowlevel_calls (void)
6453 {
6454         /* The signature doesn't matter */
6455         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6456
6457 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6458 #if _MSC_VER
6459         extern void __chkstk (void);
6460         mono_register_jit_icall_full (__chkstk, "mono_chkstk_win64", NULL, TRUE, FALSE, "__chkstk");
6461 #else
6462         extern void ___chkstk_ms (void);
6463         mono_register_jit_icall_full (___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, FALSE, "___chkstk_ms");
6464 #endif
6465 #endif
6466 }
6467
6468 void
6469 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6470 {
6471         unsigned char *ip = ji->ip.i + code;
6472
6473         /*
6474          * Debug code to help track down problems where the target of a near call is
6475          * is not valid.
6476          */
6477         if (amd64_is_near_call (ip)) {
6478                 gint64 disp = (guint8*)target - (guint8*)ip;
6479
6480                 if (!amd64_is_imm32 (disp)) {
6481                         printf ("TYPE: %d\n", ji->type);
6482                         switch (ji->type) {
6483                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6484                                 printf ("V: %s\n", ji->data.name);
6485                                 break;
6486                         case MONO_PATCH_INFO_METHOD_JUMP:
6487                         case MONO_PATCH_INFO_METHOD:
6488                                 printf ("V: %s\n", ji->data.method->name);
6489                                 break;
6490                         default:
6491                                 break;
6492                         }
6493                 }
6494         }
6495
6496         amd64_patch (ip, (gpointer)target);
6497 }
6498
6499 #ifndef DISABLE_JIT
6500
6501 static int
6502 get_max_epilog_size (MonoCompile *cfg)
6503 {
6504         int max_epilog_size = 16;
6505
6506         if (cfg->method->save_lmf)
6507                 max_epilog_size += 256;
6508
6509         if (mono_jit_trace_calls != NULL)
6510                 max_epilog_size += 50;
6511
6512         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6513                 max_epilog_size += 50;
6514
6515         max_epilog_size += (AMD64_NREG * 2);
6516
6517         return max_epilog_size;
6518 }
6519
6520 /*
6521  * This macro is used for testing whenever the unwinder works correctly at every point
6522  * where an async exception can happen.
6523  */
6524 /* This will generate a SIGSEGV at the given point in the code */
6525 #define async_exc_point(code) do { \
6526     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6527          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6528              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6529          cfg->arch.async_point_count ++; \
6530     } \
6531 } while (0)
6532
6533 #ifdef TARGET_WIN32
6534 static guint8 *
6535 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6536 {
6537         int cfa_offset = *cfa_offset_input;
6538
6539         /* Allocate windows stack frame using stack probing method */
6540         if (alloc_size) {
6541
6542                 if (alloc_size >= 0x1000) {
6543                         amd64_mov_reg_imm (code, AMD64_RAX, alloc_size);
6544                         code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_chkstk_win64");
6545                 }
6546
6547                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6548                 if (cfg->arch.omit_fp) {
6549                         cfa_offset += alloc_size;
6550                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6551                         async_exc_point (code);
6552                 }
6553
6554                 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6555                 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6556                 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6557                 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6558                 // that will retrieve the expected results.
6559                 if (cfg->arch.omit_fp)
6560                         mono_emit_unwind_op_sp_alloc (cfg, code, alloc_size);
6561         }
6562
6563         *cfa_offset_input = cfa_offset;
6564         return code;
6565 }
6566 #endif /* TARGET_WIN32 */
6567
6568 guint8 *
6569 mono_arch_emit_prolog (MonoCompile *cfg)
6570 {
6571         MonoMethod *method = cfg->method;
6572         MonoBasicBlock *bb;
6573         MonoMethodSignature *sig;
6574         MonoInst *ins;
6575         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6576         guint8 *code;
6577         CallInfo *cinfo;
6578         MonoInst *lmf_var = cfg->lmf_var;
6579         gboolean args_clobbered = FALSE;
6580         gboolean trace = FALSE;
6581
6582         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6583
6584         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6585
6586         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6587                 trace = TRUE;
6588
6589         /* Amount of stack space allocated by register saving code */
6590         pos = 0;
6591
6592         /* Offset between RSP and the CFA */
6593         cfa_offset = 0;
6594
6595         /*
6596          * The prolog consists of the following parts:
6597          * FP present:
6598          * - push rbp
6599          * - mov rbp, rsp
6600          * - save callee saved regs using moves
6601          * - allocate frame
6602          * - save rgctx if needed
6603          * - save lmf if needed
6604          * FP not present:
6605          * - allocate frame
6606          * - save rgctx if needed
6607          * - save lmf if needed
6608          * - save callee saved regs using moves
6609          */
6610
6611         // CFA = sp + 8
6612         cfa_offset = 8;
6613         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6614         // IP saved at CFA - 8
6615         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6616         async_exc_point (code);
6617         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6618
6619         if (!cfg->arch.omit_fp) {
6620                 amd64_push_reg (code, AMD64_RBP);
6621                 cfa_offset += 8;
6622                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6623                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6624                 async_exc_point (code);
6625                 /* These are handled automatically by the stack marking code */
6626                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6627
6628                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6629                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6630                 mono_emit_unwind_op_fp_alloc (cfg, code, AMD64_RBP, 0);
6631                 async_exc_point (code);
6632         }
6633
6634         /* The param area is always at offset 0 from sp */
6635         /* This needs to be allocated here, since it has to come after the spill area */
6636         if (cfg->param_area) {
6637                 if (cfg->arch.omit_fp)
6638                         // FIXME:
6639                         g_assert_not_reached ();
6640                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6641         }
6642
6643         if (cfg->arch.omit_fp) {
6644                 /*
6645                  * On enter, the stack is misaligned by the pushing of the return
6646                  * address. It is either made aligned by the pushing of %rbp, or by
6647                  * this.
6648                  */
6649                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6650                 if ((alloc_size % 16) == 0) {
6651                         alloc_size += 8;
6652                         /* Mark the padding slot as NOREF */
6653                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6654                 }
6655         } else {
6656                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6657                 if (cfg->stack_offset != alloc_size) {
6658                         /* Mark the padding slot as NOREF */
6659                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6660                 }
6661                 cfg->arch.sp_fp_offset = alloc_size;
6662                 alloc_size -= pos;
6663         }
6664
6665         cfg->arch.stack_alloc_size = alloc_size;
6666
6667         /* Allocate stack frame */
6668 #ifdef TARGET_WIN32
6669         code = emit_prolog_setup_sp_win64 (cfg, code, alloc_size, &cfa_offset);
6670 #else
6671         if (alloc_size) {
6672                 /* See mono_emit_stack_alloc */
6673 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6674                 guint32 remaining_size = alloc_size;
6675
6676                 /* Use a loop for large sizes */
6677                 if (remaining_size > 10 * 0x1000) {
6678                         amd64_mov_reg_imm (code, X86_EAX, remaining_size / 0x1000);
6679                         guint8 *label = code;
6680                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6681                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6682                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RAX, 1);
6683                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6684                         guint8 *label2 = code;
6685                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
6686                         amd64_patch (label2, label);
6687                         if (cfg->arch.omit_fp) {
6688                                 cfa_offset += (remaining_size / 0x1000) * 0x1000;
6689                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6690                         }
6691
6692                         remaining_size = remaining_size % 0x1000;
6693                 }
6694
6695                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6696                 guint32 offset = code - cfg->native_code;
6697                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6698                         while (required_code_size >= (cfg->code_size - offset))
6699                                 cfg->code_size *= 2;
6700                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6701                         code = cfg->native_code + offset;
6702                         cfg->stat_code_reallocs++;
6703                 }
6704
6705                 while (remaining_size >= 0x1000) {
6706                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6707                         if (cfg->arch.omit_fp) {
6708                                 cfa_offset += 0x1000;
6709                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6710                         }
6711                         async_exc_point (code);
6712
6713                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6714                         remaining_size -= 0x1000;
6715                 }
6716                 if (remaining_size) {
6717                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6718                         if (cfg->arch.omit_fp) {
6719                                 cfa_offset += remaining_size;
6720                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6721                                 async_exc_point (code);
6722                         }
6723                 }
6724 #else
6725                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6726                 if (cfg->arch.omit_fp) {
6727                         cfa_offset += alloc_size;
6728                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6729                         async_exc_point (code);
6730                 }
6731 #endif
6732         }
6733 #endif
6734
6735         /* Stack alignment check */
6736 #if 0
6737         {
6738                 guint8 *buf;
6739
6740                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6741                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6742                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6743                 buf = code;
6744                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6745                 amd64_breakpoint (code);
6746                 amd64_patch (buf, code);
6747         }
6748 #endif
6749
6750         if (mini_get_debug_options ()->init_stacks) {
6751                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6752
6753                 /* Save registers to the red zone */
6754                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6755                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6756
6757                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6758                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6759                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6760
6761                 amd64_cld (code);
6762                 amd64_prefix (code, X86_REP_PREFIX);
6763                 amd64_stosl (code);
6764
6765                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6766                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6767         }
6768
6769         /* Save LMF */
6770         if (method->save_lmf)
6771                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6772
6773         /* Save callee saved registers */
6774         if (cfg->arch.omit_fp) {
6775                 save_area_offset = cfg->arch.reg_save_area_offset;
6776                 /* Save caller saved registers after sp is adjusted */
6777                 /* The registers are saved at the bottom of the frame */
6778                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6779         } else {
6780                 /* The registers are saved just below the saved rbp */
6781                 save_area_offset = cfg->arch.reg_save_area_offset;
6782         }
6783
6784         for (i = 0; i < AMD64_NREG; ++i) {
6785                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6786                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6787
6788                         if (cfg->arch.omit_fp) {
6789                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6790                                 /* These are handled automatically by the stack marking code */
6791                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6792                         } else {
6793                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6794                                 // FIXME: GC
6795                         }
6796
6797                         save_area_offset += 8;
6798                         async_exc_point (code);
6799                 }
6800         }
6801
6802         /* store runtime generic context */
6803         if (cfg->rgctx_var) {
6804                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6805                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6806
6807                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6808
6809                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6810                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6811         }
6812
6813         /* compute max_length in order to use short forward jumps */
6814         max_epilog_size = get_max_epilog_size (cfg);
6815         if (cfg->opt & MONO_OPT_BRANCH) {
6816                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6817                         MonoInst *ins;
6818                         int max_length = 0;
6819
6820                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6821                                 max_length += 6;
6822                         /* max alignment for loops */
6823                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6824                                 max_length += LOOP_ALIGNMENT;
6825
6826                         MONO_BB_FOR_EACH_INS (bb, ins) {
6827                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6828                         }
6829
6830                         /* Take prolog and epilog instrumentation into account */
6831                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6832                                 max_length += max_epilog_size;
6833
6834                         bb->max_length = max_length;
6835                 }
6836         }
6837
6838         sig = mono_method_signature (method);
6839         pos = 0;
6840
6841         cinfo = (CallInfo *)cfg->arch.cinfo;
6842
6843         if (sig->ret->type != MONO_TYPE_VOID) {
6844                 /* Save volatile arguments to the stack */
6845                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6846                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6847         }
6848
6849         /* Keep this in sync with emit_load_volatile_arguments */
6850         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6851                 ArgInfo *ainfo = cinfo->args + i;
6852
6853                 ins = cfg->args [i];
6854
6855                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6856                         /* Unused arguments */
6857                         continue;
6858
6859                 /* Save volatile arguments to the stack */
6860                 if (ins->opcode != OP_REGVAR) {
6861                         switch (ainfo->storage) {
6862                         case ArgInIReg: {
6863                                 guint32 size = 8;
6864
6865                                 /* FIXME: I1 etc */
6866                                 /*
6867                                 if (stack_offset & 0x1)
6868                                         size = 1;
6869                                 else if (stack_offset & 0x2)
6870                                         size = 2;
6871                                 else if (stack_offset & 0x4)
6872                                         size = 4;
6873                                 else
6874                                         size = 8;
6875                                 */
6876                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6877
6878                                 /*
6879                                  * Save the original location of 'this',
6880                                  * get_generic_info_from_stack_frame () needs this to properly look up
6881                                  * the argument value during the handling of async exceptions.
6882                                  */
6883                                 if (ins == cfg->args [0]) {
6884                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6885                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6886                                 }
6887                                 break;
6888                         }
6889                         case ArgInFloatSSEReg:
6890                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6891                                 break;
6892                         case ArgInDoubleSSEReg:
6893                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6894                                 break;
6895                         case ArgValuetypeInReg:
6896                                 for (quad = 0; quad < 2; quad ++) {
6897                                         switch (ainfo->pair_storage [quad]) {
6898                                         case ArgInIReg:
6899                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6900                                                 break;
6901                                         case ArgInFloatSSEReg:
6902                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6903                                                 break;
6904                                         case ArgInDoubleSSEReg:
6905                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6906                                                 break;
6907                                         case ArgNone:
6908                                                 break;
6909                                         default:
6910                                                 g_assert_not_reached ();
6911                                         }
6912                                 }
6913                                 break;
6914                         case ArgValuetypeAddrInIReg:
6915                                 if (ainfo->pair_storage [0] == ArgInIReg)
6916                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6917                                 break;
6918                         case ArgValuetypeAddrOnStack:
6919                                 break;
6920                         case ArgGSharedVtInReg:
6921                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6922                                 break;
6923                         default:
6924                                 break;
6925                         }
6926                 } else {
6927                         /* Argument allocated to (non-volatile) register */
6928                         switch (ainfo->storage) {
6929                         case ArgInIReg:
6930                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6931                                 break;
6932                         case ArgOnStack:
6933                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6934                                 break;
6935                         default:
6936                                 g_assert_not_reached ();
6937                         }
6938
6939                         if (ins == cfg->args [0]) {
6940                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6941                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6942                         }
6943                 }
6944         }
6945
6946         if (cfg->method->save_lmf)
6947                 args_clobbered = TRUE;
6948
6949         if (trace) {
6950                 args_clobbered = TRUE;
6951                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6952         }
6953
6954         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6955                 args_clobbered = TRUE;
6956
6957         /*
6958          * Optimize the common case of the first bblock making a call with the same
6959          * arguments as the method. This works because the arguments are still in their
6960          * original argument registers.
6961          * FIXME: Generalize this
6962          */
6963         if (!args_clobbered) {
6964                 MonoBasicBlock *first_bb = cfg->bb_entry;
6965                 MonoInst *next;
6966                 int filter = FILTER_IL_SEQ_POINT;
6967
6968                 next = mono_bb_first_inst (first_bb, filter);
6969                 if (!next && first_bb->next_bb) {
6970                         first_bb = first_bb->next_bb;
6971                         next = mono_bb_first_inst (first_bb, filter);
6972                 }
6973
6974                 if (first_bb->in_count > 1)
6975                         next = NULL;
6976
6977                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6978                         ArgInfo *ainfo = cinfo->args + i;
6979                         gboolean match = FALSE;
6980
6981                         ins = cfg->args [i];
6982                         if (ins->opcode != OP_REGVAR) {
6983                                 switch (ainfo->storage) {
6984                                 case ArgInIReg: {
6985                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6986                                                 if (next->dreg == ainfo->reg) {
6987                                                         NULLIFY_INS (next);
6988                                                         match = TRUE;
6989                                                 } else {
6990                                                         next->opcode = OP_MOVE;
6991                                                         next->sreg1 = ainfo->reg;
6992                                                         /* Only continue if the instruction doesn't change argument regs */
6993                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6994                                                                 match = TRUE;
6995                                                 }
6996                                         }
6997                                         break;
6998                                 }
6999                                 default:
7000                                         break;
7001                                 }
7002                         } else {
7003                                 /* Argument allocated to (non-volatile) register */
7004                                 switch (ainfo->storage) {
7005                                 case ArgInIReg:
7006                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7007                                                 NULLIFY_INS (next);
7008                                                 match = TRUE;
7009                                         }
7010                                         break;
7011                                 default:
7012                                         break;
7013                                 }
7014                         }
7015
7016                         if (match) {
7017                                 next = mono_inst_next (next, filter);
7018                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7019                                 if (!next)
7020                                         break;
7021                         }
7022                 }
7023         }
7024
7025         if (cfg->gen_sdb_seq_points) {
7026                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7027
7028                 /* Initialize seq_point_info_var */
7029                 if (cfg->compile_aot) {
7030                         /* Initialize the variable from a GOT slot */
7031                         /* Same as OP_AOTCONST */
7032                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7033                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7034                         g_assert (info_var->opcode == OP_REGOFFSET);
7035                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7036                 }
7037
7038                 if (cfg->compile_aot) {
7039                         /* Initialize ss_tramp_var */
7040                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7041                         g_assert (ins->opcode == OP_REGOFFSET);
7042
7043                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7044                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7045                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7046                 } else {
7047                         /* Initialize ss_tramp_var */
7048                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7049                         g_assert (ins->opcode == OP_REGOFFSET);
7050
7051                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7052                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7053
7054                         /* Initialize bp_tramp_var */
7055                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7056                         g_assert (ins->opcode == OP_REGOFFSET);
7057
7058                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7059                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7060                 }
7061         }
7062
7063         cfg->code_len = code - cfg->native_code;
7064
7065         g_assert (cfg->code_len < cfg->code_size);
7066
7067         return code;
7068 }
7069
7070 void
7071 mono_arch_emit_epilog (MonoCompile *cfg)
7072 {
7073         MonoMethod *method = cfg->method;
7074         int quad, i;
7075         guint8 *code;
7076         int max_epilog_size;
7077         CallInfo *cinfo;
7078         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7079         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7080
7081         max_epilog_size = get_max_epilog_size (cfg);
7082
7083         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7084                 cfg->code_size *= 2;
7085                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7086                 cfg->stat_code_reallocs++;
7087         }
7088         code = cfg->native_code + cfg->code_len;
7089
7090         cfg->has_unwind_info_for_epilog = TRUE;
7091
7092         /* Mark the start of the epilog */
7093         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7094
7095         /* Save the uwind state which is needed by the out-of-line code */
7096         mono_emit_unwind_op_remember_state (cfg, code);
7097
7098         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7099                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7100
7101         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7102
7103         if (method->save_lmf) {
7104                 /* check if we need to restore protection of the stack after a stack overflow */
7105                 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7106                         guint8 *patch;
7107                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7108                         /* we load the value in a separate instruction: this mechanism may be
7109                          * used later as a safer way to do thread interruption
7110                          */
7111                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7112                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7113                         patch = code;
7114                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7115                         /* note that the call trampoline will preserve eax/edx */
7116                         x86_call_reg (code, X86_ECX);
7117                         x86_patch (patch, code);
7118                 } else {
7119                         /* FIXME: maybe save the jit tls in the prolog */
7120                 }
7121                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7122                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7123                 }
7124         }
7125
7126         /* Restore callee saved regs */
7127         for (i = 0; i < AMD64_NREG; ++i) {
7128                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7129                         /* Restore only used_int_regs, not arch.saved_iregs */
7130 #if defined(MONO_SUPPORT_TASKLETS)
7131                         int restore_reg=1;
7132 #else
7133                         int restore_reg=(cfg->used_int_regs & (1 << i));
7134 #endif
7135                         if (restore_reg) {
7136                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7137                                 mono_emit_unwind_op_same_value (cfg, code, i);
7138                                 async_exc_point (code);
7139                         }
7140                         save_area_offset += 8;
7141                 }
7142         }
7143
7144         /* Load returned vtypes into registers if needed */
7145         cinfo = (CallInfo *)cfg->arch.cinfo;
7146         if (cinfo->ret.storage == ArgValuetypeInReg) {
7147                 ArgInfo *ainfo = &cinfo->ret;
7148                 MonoInst *inst = cfg->ret;
7149
7150                 for (quad = 0; quad < 2; quad ++) {
7151                         switch (ainfo->pair_storage [quad]) {
7152                         case ArgInIReg:
7153                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7154                                 break;
7155                         case ArgInFloatSSEReg:
7156                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7157                                 break;
7158                         case ArgInDoubleSSEReg:
7159                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7160                                 break;
7161                         case ArgNone:
7162                                 break;
7163                         default:
7164                                 g_assert_not_reached ();
7165                         }
7166                 }
7167         }
7168
7169         if (cfg->arch.omit_fp) {
7170                 if (cfg->arch.stack_alloc_size) {
7171                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7172                 }
7173         } else {
7174 #ifdef TARGET_WIN32
7175                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
7176                 amd64_pop_reg (code, AMD64_RBP);
7177                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7178 #else
7179                 amd64_leave (code);
7180                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7181 #endif
7182         }
7183         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7184         async_exc_point (code);
7185         amd64_ret (code);
7186
7187         /* Restore the unwind state to be the same as before the epilog */
7188         mono_emit_unwind_op_restore_state (cfg, code);
7189
7190         cfg->code_len = code - cfg->native_code;
7191
7192         g_assert (cfg->code_len < cfg->code_size);
7193 }
7194
7195 void
7196 mono_arch_emit_exceptions (MonoCompile *cfg)
7197 {
7198         MonoJumpInfo *patch_info;
7199         int nthrows, i;
7200         guint8 *code;
7201         MonoClass *exc_classes [16];
7202         guint8 *exc_throw_start [16], *exc_throw_end [16];
7203         guint32 code_size = 0;
7204
7205         /* Compute needed space */
7206         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7207                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7208                         code_size += 40;
7209                 if (patch_info->type == MONO_PATCH_INFO_R8)
7210                         code_size += 8 + 15; /* sizeof (double) + alignment */
7211                 if (patch_info->type == MONO_PATCH_INFO_R4)
7212                         code_size += 4 + 15; /* sizeof (float) + alignment */
7213                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7214                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7215         }
7216
7217         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7218                 cfg->code_size *= 2;
7219                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7220                 cfg->stat_code_reallocs++;
7221         }
7222
7223         code = cfg->native_code + cfg->code_len;
7224
7225         /* add code to raise exceptions */
7226         nthrows = 0;
7227         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7228                 switch (patch_info->type) {
7229                 case MONO_PATCH_INFO_EXC: {
7230                         MonoClass *exc_class;
7231                         guint8 *buf, *buf2;
7232                         guint32 throw_ip;
7233
7234                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7235
7236                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7237                         throw_ip = patch_info->ip.i;
7238
7239                         //x86_breakpoint (code);
7240                         /* Find a throw sequence for the same exception class */
7241                         for (i = 0; i < nthrows; ++i)
7242                                 if (exc_classes [i] == exc_class)
7243                                         break;
7244                         if (i < nthrows) {
7245                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7246                                 x86_jump_code (code, exc_throw_start [i]);
7247                                 patch_info->type = MONO_PATCH_INFO_NONE;
7248                         }
7249                         else {
7250                                 buf = code;
7251                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7252                                 buf2 = code;
7253
7254                                 if (nthrows < 16) {
7255                                         exc_classes [nthrows] = exc_class;
7256                                         exc_throw_start [nthrows] = code;
7257                                 }
7258                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7259
7260                                 patch_info->type = MONO_PATCH_INFO_NONE;
7261
7262                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7263
7264                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7265                                 while (buf < buf2)
7266                                         x86_nop (buf);
7267
7268                                 if (nthrows < 16) {
7269                                         exc_throw_end [nthrows] = code;
7270                                         nthrows ++;
7271                                 }
7272                         }
7273                         break;
7274                 }
7275                 default:
7276                         /* do nothing */
7277                         break;
7278                 }
7279                 g_assert(code < cfg->native_code + cfg->code_size);
7280         }
7281
7282         /* Handle relocations with RIP relative addressing */
7283         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7284                 gboolean remove = FALSE;
7285                 guint8 *orig_code = code;
7286
7287                 switch (patch_info->type) {
7288                 case MONO_PATCH_INFO_R8:
7289                 case MONO_PATCH_INFO_R4: {
7290                         guint8 *pos, *patch_pos;
7291                         guint32 target_pos;
7292
7293                         /* The SSE opcodes require a 16 byte alignment */
7294                         code = (guint8*)ALIGN_TO (code, 16);
7295
7296                         pos = cfg->native_code + patch_info->ip.i;
7297                         if (IS_REX (pos [1])) {
7298                                 patch_pos = pos + 5;
7299                                 target_pos = code - pos - 9;
7300                         }
7301                         else {
7302                                 patch_pos = pos + 4;
7303                                 target_pos = code - pos - 8;
7304                         }
7305
7306                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7307                                 *(double*)code = *(double*)patch_info->data.target;
7308                                 code += sizeof (double);
7309                         } else {
7310                                 *(float*)code = *(float*)patch_info->data.target;
7311                                 code += sizeof (float);
7312                         }
7313
7314                         *(guint32*)(patch_pos) = target_pos;
7315
7316                         remove = TRUE;
7317                         break;
7318                 }
7319                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7320                         guint8 *pos;
7321
7322                         if (cfg->compile_aot)
7323                                 continue;
7324
7325                         /*loading is faster against aligned addresses.*/
7326                         code = (guint8*)ALIGN_TO (code, 8);
7327                         memset (orig_code, 0, code - orig_code);
7328
7329                         pos = cfg->native_code + patch_info->ip.i;
7330
7331                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7332                         if (IS_REX (pos [1]))
7333                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7334                         else
7335                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7336
7337                         *(gpointer*)code = (gpointer)patch_info->data.target;
7338                         code += sizeof (gpointer);
7339
7340                         remove = TRUE;
7341                         break;
7342                 }
7343                 default:
7344                         break;
7345                 }
7346
7347                 if (remove) {
7348                         if (patch_info == cfg->patch_info)
7349                                 cfg->patch_info = patch_info->next;
7350                         else {
7351                                 MonoJumpInfo *tmp;
7352
7353                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7354                                         ;
7355                                 tmp->next = patch_info->next;
7356                         }
7357                 }
7358                 g_assert (code < cfg->native_code + cfg->code_size);
7359         }
7360
7361         cfg->code_len = code - cfg->native_code;
7362
7363         g_assert (cfg->code_len < cfg->code_size);
7364
7365 }
7366
7367 #endif /* DISABLE_JIT */
7368
7369 void*
7370 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7371 {
7372         guchar *code = (guchar *)p;
7373         MonoMethodSignature *sig;
7374         MonoInst *inst;
7375         int i, n, stack_area = 0;
7376
7377         /* Keep this in sync with mono_arch_get_argument_info */
7378
7379         if (enable_arguments) {
7380                 /* Allocate a new area on the stack and save arguments there */
7381                 sig = mono_method_signature (cfg->method);
7382
7383                 n = sig->param_count + sig->hasthis;
7384
7385                 stack_area = ALIGN_TO (n * 8, 16);
7386
7387                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7388
7389                 for (i = 0; i < n; ++i) {
7390                         inst = cfg->args [i];
7391
7392                         if (inst->opcode == OP_REGVAR)
7393                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7394                         else {
7395                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7396                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7397                         }
7398                 }
7399         }
7400
7401         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7402         amd64_set_reg_template (code, AMD64_ARG_REG1);
7403         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7404         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7405
7406         if (enable_arguments)
7407                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7408
7409         return code;
7410 }
7411
7412 enum {
7413         SAVE_NONE,
7414         SAVE_STRUCT,
7415         SAVE_EAX,
7416         SAVE_EAX_EDX,
7417         SAVE_XMM
7418 };
7419
7420 void*
7421 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7422 {
7423         guchar *code = (guchar *)p;
7424         int save_mode = SAVE_NONE;
7425         MonoMethod *method = cfg->method;
7426         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7427         int i;
7428
7429         switch (ret_type->type) {
7430         case MONO_TYPE_VOID:
7431                 /* special case string .ctor icall */
7432                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7433                         save_mode = SAVE_EAX;
7434                 else
7435                         save_mode = SAVE_NONE;
7436                 break;
7437         case MONO_TYPE_I8:
7438         case MONO_TYPE_U8:
7439                 save_mode = SAVE_EAX;
7440                 break;
7441         case MONO_TYPE_R4:
7442         case MONO_TYPE_R8:
7443                 save_mode = SAVE_XMM;
7444                 break;
7445         case MONO_TYPE_GENERICINST:
7446                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7447                         save_mode = SAVE_EAX;
7448                         break;
7449                 }
7450                 /* Fall through */
7451         case MONO_TYPE_VALUETYPE:
7452                 save_mode = SAVE_STRUCT;
7453                 break;
7454         default:
7455                 save_mode = SAVE_EAX;
7456                 break;
7457         }
7458
7459         /* Save the result and copy it into the proper argument register */
7460         switch (save_mode) {
7461         case SAVE_EAX:
7462                 amd64_push_reg (code, AMD64_RAX);
7463                 /* Align stack */
7464                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7465                 if (enable_arguments)
7466                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7467                 break;
7468         case SAVE_STRUCT:
7469                 /* FIXME: */
7470                 if (enable_arguments)
7471                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7472                 break;
7473         case SAVE_XMM:
7474                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7475                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7476                 /* Align stack */
7477                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7478                 /*
7479                  * The result is already in the proper argument register so no copying
7480                  * needed.
7481                  */
7482                 break;
7483         case SAVE_NONE:
7484                 break;
7485         default:
7486                 g_assert_not_reached ();
7487         }
7488
7489         /* Set %al since this is a varargs call */
7490         if (save_mode == SAVE_XMM)
7491                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7492         else
7493                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7494
7495         if (preserve_argument_registers) {
7496                 for (i = 0; i < PARAM_REGS; ++i)
7497                         amd64_push_reg (code, param_regs [i]);
7498         }
7499
7500         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7501         amd64_set_reg_template (code, AMD64_ARG_REG1);
7502         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7503
7504         if (preserve_argument_registers) {
7505                 for (i = PARAM_REGS - 1; i >= 0; --i)
7506                         amd64_pop_reg (code, param_regs [i]);
7507         }
7508
7509         /* Restore result */
7510         switch (save_mode) {
7511         case SAVE_EAX:
7512                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7513                 amd64_pop_reg (code, AMD64_RAX);
7514                 break;
7515         case SAVE_STRUCT:
7516                 /* FIXME: */
7517                 break;
7518         case SAVE_XMM:
7519                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7520                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7521                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7522                 break;
7523         case SAVE_NONE:
7524                 break;
7525         default:
7526                 g_assert_not_reached ();
7527         }
7528
7529         return code;
7530 }
7531
7532 void
7533 mono_arch_flush_icache (guint8 *code, gint size)
7534 {
7535         /* Not needed */
7536 }
7537
7538 void
7539 mono_arch_flush_register_windows (void)
7540 {
7541 }
7542
7543 gboolean
7544 mono_arch_is_inst_imm (gint64 imm)
7545 {
7546         return amd64_use_imm32 (imm);
7547 }
7548
7549 /*
7550  * Determine whenever the trap whose info is in SIGINFO is caused by
7551  * integer overflow.
7552  */
7553 gboolean
7554 mono_arch_is_int_overflow (void *sigctx, void *info)
7555 {
7556         MonoContext ctx;
7557         guint8* rip;
7558         int reg;
7559         gint64 value;
7560
7561         mono_sigctx_to_monoctx (sigctx, &ctx);
7562
7563         rip = (guint8*)ctx.gregs [AMD64_RIP];
7564
7565         if (IS_REX (rip [0])) {
7566                 reg = amd64_rex_b (rip [0]);
7567                 rip ++;
7568         }
7569         else
7570                 reg = 0;
7571
7572         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7573                 /* idiv REG */
7574                 reg += x86_modrm_rm (rip [1]);
7575
7576                 value = ctx.gregs [reg];
7577
7578                 if (value == -1)
7579                         return TRUE;
7580         }
7581
7582         return FALSE;
7583 }
7584
7585 guint32
7586 mono_arch_get_patch_offset (guint8 *code)
7587 {
7588         return 3;
7589 }
7590
7591 /**
7592  * \return TRUE if no sw breakpoint was present.
7593  *
7594  * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
7595  * breakpoints in the original code, they are removed in the copy.
7596  */
7597 gboolean
7598 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7599 {
7600         /*
7601          * If method_start is non-NULL we need to perform bound checks, since we access memory
7602          * at code - offset we could go before the start of the method and end up in a different
7603          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7604          * instead.
7605          */
7606         if (!method_start || code - offset >= method_start) {
7607                 memcpy (buf, code - offset, size);
7608         } else {
7609                 int diff = code - method_start;
7610                 memset (buf, 0, size);
7611                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7612         }
7613         return TRUE;
7614 }
7615
7616 int
7617 mono_arch_get_this_arg_reg (guint8 *code)
7618 {
7619         return AMD64_ARG_REG1;
7620 }
7621
7622 gpointer
7623 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7624 {
7625         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7626 }
7627
7628 #define MAX_ARCH_DELEGATE_PARAMS 10
7629
7630 static gpointer
7631 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7632 {
7633         guint8 *code, *start;
7634         GSList *unwind_ops = NULL;
7635         int i;
7636
7637         unwind_ops = mono_arch_get_cie_program ();
7638
7639         if (has_target) {
7640                 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7641
7642                 /* Replace the this argument with the target */
7643                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7644                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7645                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7646
7647                 g_assert ((code - start) < 64);
7648                 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7649         } else {
7650                 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7651
7652                 if (param_count == 0) {
7653                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7654                 } else {
7655                         /* We have to shift the arguments left */
7656                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7657                         for (i = 0; i < param_count; ++i) {
7658 #ifdef TARGET_WIN32
7659                                 if (i < 3)
7660                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7661                                 else
7662                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7663 #else
7664                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7665 #endif
7666                         }
7667
7668                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7669                 }
7670                 g_assert ((code - start) < 64);
7671                 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7672         }
7673
7674         mono_arch_flush_icache (start, code - start);
7675
7676         if (has_target) {
7677                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7678         } else {
7679                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7680                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7681                 g_free (name);
7682         }
7683
7684         if (mono_jit_map_is_enabled ()) {
7685                 char *buff;
7686                 if (has_target)
7687                         buff = (char*)"delegate_invoke_has_target";
7688                 else
7689                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7690                 mono_emit_jit_tramp (start, code - start, buff);
7691                 if (!has_target)
7692                         g_free (buff);
7693         }
7694         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7695
7696         return start;
7697 }
7698
7699 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7700
7701 static gpointer
7702 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7703 {
7704         guint8 *code, *start;
7705         int size = 20;
7706         char *tramp_name;
7707         GSList *unwind_ops;
7708
7709         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7710                 return NULL;
7711
7712         start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7713
7714         unwind_ops = mono_arch_get_cie_program ();
7715
7716         /* Replace the this argument with the target */
7717         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7718         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7719
7720         if (load_imt_reg) {
7721                 /* Load the IMT reg */
7722                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7723         }
7724
7725         /* Load the vtable */
7726         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7727         amd64_jump_membase (code, AMD64_RAX, offset);
7728         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7729
7730         tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7731         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7732         g_free (tramp_name);
7733
7734         return start;
7735 }
7736
7737 /*
7738  * mono_arch_get_delegate_invoke_impls:
7739  *
7740  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7741  * trampolines.
7742  */
7743 GSList*
7744 mono_arch_get_delegate_invoke_impls (void)
7745 {
7746         GSList *res = NULL;
7747         MonoTrampInfo *info;
7748         int i;
7749
7750         get_delegate_invoke_impl (&info, TRUE, 0);
7751         res = g_slist_prepend (res, info);
7752
7753         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7754                 get_delegate_invoke_impl (&info, FALSE, i);
7755                 res = g_slist_prepend (res, info);
7756         }
7757
7758         for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7759                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7760                 res = g_slist_prepend (res, info);
7761         }
7762
7763         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7764                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7765                 res = g_slist_prepend (res, info);
7766                 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7767                 res = g_slist_prepend (res, info);
7768         }
7769
7770         return res;
7771 }
7772
7773 gpointer
7774 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7775 {
7776         guint8 *code, *start;
7777         int i;
7778
7779         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7780                 return NULL;
7781
7782         /* FIXME: Support more cases */
7783         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7784                 return NULL;
7785
7786         if (has_target) {
7787                 static guint8* cached = NULL;
7788
7789                 if (cached)
7790                         return cached;
7791
7792                 if (mono_aot_only) {
7793                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7794                 } else {
7795                         MonoTrampInfo *info;
7796                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7797                         mono_tramp_info_register (info, NULL);
7798                 }
7799
7800                 mono_memory_barrier ();
7801
7802                 cached = start;
7803         } else {
7804                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7805                 for (i = 0; i < sig->param_count; ++i)
7806                         if (!mono_is_regsize_var (sig->params [i]))
7807                                 return NULL;
7808                 if (sig->param_count > 4)
7809                         return NULL;
7810
7811                 code = cache [sig->param_count];
7812                 if (code)
7813                         return code;
7814
7815                 if (mono_aot_only) {
7816                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7817                         start = (guint8 *)mono_aot_get_trampoline (name);
7818                         g_free (name);
7819                 } else {
7820                         MonoTrampInfo *info;
7821                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7822                         mono_tramp_info_register (info, NULL);
7823                 }
7824
7825                 mono_memory_barrier ();
7826
7827                 cache [sig->param_count] = start;
7828         }
7829
7830         return start;
7831 }
7832
7833 gpointer
7834 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7835 {
7836         MonoTrampInfo *info;
7837         gpointer code;
7838
7839         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7840         if (code)
7841                 mono_tramp_info_register (info, NULL);
7842         return code;
7843 }
7844
7845 void
7846 mono_arch_finish_init (void)
7847 {
7848 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7849         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7850 #endif
7851 }
7852
7853 void
7854 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7855 {
7856 }
7857
7858 #define CMP_SIZE (6 + 1)
7859 #define CMP_REG_REG_SIZE (4 + 1)
7860 #define BR_SMALL_SIZE 2
7861 #define BR_LARGE_SIZE 6
7862 #define MOV_REG_IMM_SIZE 10
7863 #define MOV_REG_IMM_32BIT_SIZE 6
7864 #define JUMP_REG_SIZE (2 + 1)
7865
7866 static int
7867 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7868 {
7869         int i, distance = 0;
7870         for (i = start; i < target; ++i)
7871                 distance += imt_entries [i]->chunk_size;
7872         return distance;
7873 }
7874
7875 /*
7876  * LOCKING: called with the domain lock held
7877  */
7878 gpointer
7879 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7880         gpointer fail_tramp)
7881 {
7882         int i;
7883         int size = 0;
7884         guint8 *code, *start;
7885         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7886         GSList *unwind_ops;
7887
7888         for (i = 0; i < count; ++i) {
7889                 MonoIMTCheckItem *item = imt_entries [i];
7890                 if (item->is_equals) {
7891                         if (item->check_target_idx) {
7892                                 if (!item->compare_done) {
7893                                         if (amd64_use_imm32 ((gint64)item->key))
7894                                                 item->chunk_size += CMP_SIZE;
7895                                         else
7896                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7897                                 }
7898                                 if (item->has_target_code) {
7899                                         item->chunk_size += MOV_REG_IMM_SIZE;
7900                                 } else {
7901                                         if (vtable_is_32bit)
7902                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7903                                         else
7904                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7905                                 }
7906                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7907                         } else {
7908                                 if (fail_tramp) {
7909                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7910                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7911                                 } else {
7912                                         if (vtable_is_32bit)
7913                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7914                                         else
7915                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7916                                         item->chunk_size += JUMP_REG_SIZE;
7917                                         /* with assert below:
7918                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7919                                          */
7920                                 }
7921                         }
7922                 } else {
7923                         if (amd64_use_imm32 ((gint64)item->key))
7924                                 item->chunk_size += CMP_SIZE;
7925                         else
7926                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7927                         item->chunk_size += BR_LARGE_SIZE;
7928                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7929                 }
7930                 size += item->chunk_size;
7931         }
7932         if (fail_tramp)
7933                 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7934         else
7935                 code = (guint8 *)mono_domain_code_reserve (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7936         start = code;
7937
7938         unwind_ops = mono_arch_get_cie_program ();
7939
7940         for (i = 0; i < count; ++i) {
7941                 MonoIMTCheckItem *item = imt_entries [i];
7942                 item->code_target = code;
7943                 if (item->is_equals) {
7944                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7945
7946                         if (item->check_target_idx || fail_case) {
7947                                 if (!item->compare_done || fail_case) {
7948                                         if (amd64_use_imm32 ((gint64)item->key))
7949                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7950                                         else {
7951                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7952                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7953                                         }
7954                                 }
7955                                 item->jmp_code = code;
7956                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7957                                 if (item->has_target_code) {
7958                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7959                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7960                                 } else {
7961                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7962                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7963                                 }
7964
7965                                 if (fail_case) {
7966                                         amd64_patch (item->jmp_code, code);
7967                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7968                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7969                                         item->jmp_code = NULL;
7970                                 }
7971                         } else {
7972                                 /* enable the commented code to assert on wrong method */
7973 #if 0
7974                                 if (amd64_is_imm32 (item->key))
7975                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7976                                 else {
7977                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7978                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7979                                 }
7980                                 item->jmp_code = code;
7981                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7982                                 /* See the comment below about R10 */
7983                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7984                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7985                                 amd64_patch (item->jmp_code, code);
7986                                 amd64_breakpoint (code);
7987                                 item->jmp_code = NULL;
7988 #else
7989                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7990                                    needs to be preserved.  R10 needs
7991                                    to be preserved for calls which
7992                                    require a runtime generic context,
7993                                    but interface calls don't. */
7994                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7995                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7996 #endif
7997                         }
7998                 } else {
7999                         if (amd64_use_imm32 ((gint64)item->key))
8000                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8001                         else {
8002                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8003                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8004                         }
8005                         item->jmp_code = code;
8006                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8007                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8008                         else
8009                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8010                 }
8011                 g_assert (code - item->code_target <= item->chunk_size);
8012         }
8013         /* patch the branches to get to the target items */
8014         for (i = 0; i < count; ++i) {
8015                 MonoIMTCheckItem *item = imt_entries [i];
8016                 if (item->jmp_code) {
8017                         if (item->check_target_idx) {
8018                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8019                         }
8020                 }
8021         }
8022
8023         if (!fail_tramp)
8024                 mono_stats.imt_trampolines_size += code - start;
8025         g_assert (code - start <= size);
8026         g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8027
8028         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8029
8030         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8031
8032         return start;
8033 }
8034
8035 MonoMethod*
8036 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8037 {
8038         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8039 }
8040
8041 MonoVTable*
8042 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8043 {
8044         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8045 }
8046
8047 GSList*
8048 mono_arch_get_cie_program (void)
8049 {
8050         GSList *l = NULL;
8051
8052         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8053         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8054
8055         return l;
8056 }
8057
8058 #ifndef DISABLE_JIT
8059
8060 MonoInst*
8061 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8062 {
8063         MonoInst *ins = NULL;
8064         int opcode = 0;
8065
8066         if (cmethod->klass == mono_defaults.math_class) {
8067                 if (strcmp (cmethod->name, "Sin") == 0) {
8068                         opcode = OP_SIN;
8069                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8070                         opcode = OP_COS;
8071                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8072                         opcode = OP_SQRT;
8073                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8074                         opcode = OP_ABS;
8075                 }
8076
8077                 if (opcode && fsig->param_count == 1) {
8078                         MONO_INST_NEW (cfg, ins, opcode);
8079                         ins->type = STACK_R8;
8080                         ins->dreg = mono_alloc_freg (cfg);
8081                         ins->sreg1 = args [0]->dreg;
8082                         MONO_ADD_INS (cfg->cbb, ins);
8083                 }
8084
8085                 opcode = 0;
8086                 if (cfg->opt & MONO_OPT_CMOV) {
8087                         if (strcmp (cmethod->name, "Min") == 0) {
8088                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8089                                         opcode = OP_IMIN;
8090                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8091                                         opcode = OP_IMIN_UN;
8092                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8093                                         opcode = OP_LMIN;
8094                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8095                                         opcode = OP_LMIN_UN;
8096                         } else if (strcmp (cmethod->name, "Max") == 0) {
8097                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8098                                         opcode = OP_IMAX;
8099                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8100                                         opcode = OP_IMAX_UN;
8101                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8102                                         opcode = OP_LMAX;
8103                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8104                                         opcode = OP_LMAX_UN;
8105                         }
8106                 }
8107
8108                 if (opcode && fsig->param_count == 2) {
8109                         MONO_INST_NEW (cfg, ins, opcode);
8110                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8111                         ins->dreg = mono_alloc_ireg (cfg);
8112                         ins->sreg1 = args [0]->dreg;
8113                         ins->sreg2 = args [1]->dreg;
8114                         MONO_ADD_INS (cfg->cbb, ins);
8115                 }
8116
8117 #if 0
8118                 /* OP_FREM is not IEEE compatible */
8119                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8120                         MONO_INST_NEW (cfg, ins, OP_FREM);
8121                         ins->inst_i0 = args [0];
8122                         ins->inst_i1 = args [1];
8123                 }
8124 #endif
8125         }
8126
8127         return ins;
8128 }
8129 #endif
8130
8131 gboolean
8132 mono_arch_print_tree (MonoInst *tree, int arity)
8133 {
8134         return 0;
8135 }
8136
8137 mgreg_t
8138 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8139 {
8140         return ctx->gregs [reg];
8141 }
8142
8143 void
8144 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8145 {
8146         ctx->gregs [reg] = val;
8147 }
8148
8149 gpointer
8150 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8151 {
8152         gpointer *sp, old_value;
8153         char *bp;
8154
8155         /*Load the spvar*/
8156         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8157         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8158
8159         old_value = *sp;
8160         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8161                 return old_value;
8162
8163         *sp = new_value;
8164
8165         return old_value;
8166 }
8167
8168 /*
8169  * mono_arch_emit_load_aotconst:
8170  *
8171  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8172  * TARGET from the mscorlib GOT in full-aot code.
8173  * On AMD64, the result is placed into R11.
8174  */
8175 guint8*
8176 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8177 {
8178         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8179         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8180
8181         return code;
8182 }
8183
8184 /*
8185  * mono_arch_get_trampolines:
8186  *
8187  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8188  * for AOT.
8189  */
8190 GSList *
8191 mono_arch_get_trampolines (gboolean aot)
8192 {
8193         return mono_amd64_get_exception_trampolines (aot);
8194 }
8195
8196 /* Soft Debug support */
8197 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8198
8199 /*
8200  * mono_arch_set_breakpoint:
8201  *
8202  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8203  * The location should contain code emitted by OP_SEQ_POINT.
8204  */
8205 void
8206 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8207 {
8208         guint8 *code = ip;
8209
8210         if (ji->from_aot) {
8211                 guint32 native_offset = ip - (guint8*)ji->code_start;
8212                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8213
8214                 g_assert (info->bp_addrs [native_offset] == 0);
8215                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8216         } else {
8217                 /* ip points to a mov r11, 0 */
8218                 g_assert (code [0] == 0x41);
8219                 g_assert (code [1] == 0xbb);
8220                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8221         }
8222 }
8223
8224 /*
8225  * mono_arch_clear_breakpoint:
8226  *
8227  *   Clear the breakpoint at IP.
8228  */
8229 void
8230 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8231 {
8232         guint8 *code = ip;
8233
8234         if (ji->from_aot) {
8235                 guint32 native_offset = ip - (guint8*)ji->code_start;
8236                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8237
8238                 info->bp_addrs [native_offset] = NULL;
8239         } else {
8240                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8241         }
8242 }
8243
8244 gboolean
8245 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8246 {
8247         /* We use soft breakpoints on amd64 */
8248         return FALSE;
8249 }
8250
8251 /*
8252  * mono_arch_skip_breakpoint:
8253  *
8254  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8255  * we resume, the instruction is not executed again.
8256  */
8257 void
8258 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8259 {
8260         g_assert_not_reached ();
8261 }
8262
8263 /*
8264  * mono_arch_start_single_stepping:
8265  *
8266  *   Start single stepping.
8267  */
8268 void
8269 mono_arch_start_single_stepping (void)
8270 {
8271         ss_trampoline = mini_get_single_step_trampoline ();
8272 }
8273
8274 /*
8275  * mono_arch_stop_single_stepping:
8276  *
8277  *   Stop single stepping.
8278  */
8279 void
8280 mono_arch_stop_single_stepping (void)
8281 {
8282         ss_trampoline = NULL;
8283 }
8284
8285 /*
8286  * mono_arch_is_single_step_event:
8287  *
8288  *   Return whenever the machine state in SIGCTX corresponds to a single
8289  * step event.
8290  */
8291 gboolean
8292 mono_arch_is_single_step_event (void *info, void *sigctx)
8293 {
8294         /* We use soft breakpoints on amd64 */
8295         return FALSE;
8296 }
8297
8298 /*
8299  * mono_arch_skip_single_step:
8300  *
8301  *   Modify CTX so the ip is placed after the single step trigger instruction,
8302  * we resume, the instruction is not executed again.
8303  */
8304 void
8305 mono_arch_skip_single_step (MonoContext *ctx)
8306 {
8307         g_assert_not_reached ();
8308 }
8309
8310 /*
8311  * mono_arch_create_seq_point_info:
8312  *
8313  *   Return a pointer to a data structure which is used by the sequence
8314  * point implementation in AOTed code.
8315  */
8316 gpointer
8317 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8318 {
8319         SeqPointInfo *info;
8320         MonoJitInfo *ji;
8321
8322         // FIXME: Add a free function
8323
8324         mono_domain_lock (domain);
8325         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8326                                                                 code);
8327         mono_domain_unlock (domain);
8328
8329         if (!info) {
8330                 ji = mono_jit_info_table_find (domain, (char*)code);
8331                 g_assert (ji);
8332
8333                 // FIXME: Optimize the size
8334                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8335
8336                 info->ss_tramp_addr = &ss_trampoline;
8337
8338                 mono_domain_lock (domain);
8339                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8340                                                          code, info);
8341                 mono_domain_unlock (domain);
8342         }
8343
8344         return info;
8345 }
8346
8347 void
8348 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8349 {
8350         ext->lmf.previous_lmf = prev_lmf;
8351         /* Mark that this is a MonoLMFExt */
8352         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8353         ext->lmf.rsp = (gssize)ext;
8354 }
8355
8356 #endif
8357
8358 gboolean
8359 mono_arch_opcode_supported (int opcode)
8360 {
8361         switch (opcode) {
8362         case OP_ATOMIC_ADD_I4:
8363         case OP_ATOMIC_ADD_I8:
8364         case OP_ATOMIC_EXCHANGE_I4:
8365         case OP_ATOMIC_EXCHANGE_I8:
8366         case OP_ATOMIC_CAS_I4:
8367         case OP_ATOMIC_CAS_I8:
8368         case OP_ATOMIC_LOAD_I1:
8369         case OP_ATOMIC_LOAD_I2:
8370         case OP_ATOMIC_LOAD_I4:
8371         case OP_ATOMIC_LOAD_I8:
8372         case OP_ATOMIC_LOAD_U1:
8373         case OP_ATOMIC_LOAD_U2:
8374         case OP_ATOMIC_LOAD_U4:
8375         case OP_ATOMIC_LOAD_U8:
8376         case OP_ATOMIC_LOAD_R4:
8377         case OP_ATOMIC_LOAD_R8:
8378         case OP_ATOMIC_STORE_I1:
8379         case OP_ATOMIC_STORE_I2:
8380         case OP_ATOMIC_STORE_I4:
8381         case OP_ATOMIC_STORE_I8:
8382         case OP_ATOMIC_STORE_U1:
8383         case OP_ATOMIC_STORE_U2:
8384         case OP_ATOMIC_STORE_U4:
8385         case OP_ATOMIC_STORE_U8:
8386         case OP_ATOMIC_STORE_R4:
8387         case OP_ATOMIC_STORE_R8:
8388                 return TRUE;
8389         default:
8390                 return FALSE;
8391         }
8392 }
8393
8394 CallInfo*
8395 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8396 {
8397         return get_call_info (mp, sig);
8398 }