mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "ir-emit.h"
  30 #include "mini-amd64.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * xmmregs [] = {
 121         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 122         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 123 };
 124
 125 const char*
 126 mono_arch_fregname (int reg)
 127 {
 128         if (reg < AMD64_XMM_NREG)
 129                 return xmmregs [reg];
 130         else
 131                 return "unknown";
 132 }
 133
 134 G_GNUC_UNUSED static void
 135 break_count (void)
 136 {
 137 }
 138
 139 G_GNUC_UNUSED static gboolean
 140 debug_count (void)
 141 {
 142         static int count = 0;
 143         count ++;
 144
 145         if (!getenv ("COUNT"))
 146                 return TRUE;
 147
 148         if (count == atoi (getenv ("COUNT"))) {
 149                 break_count ();
 150         }
 151
 152         if (count > atoi (getenv ("COUNT"))) {
 153                 return FALSE;
 154         }
 155
 156         return TRUE;
 157 }
 158
 159 static gboolean
 160 debug_omit_fp (void)
 161 {
 162 #if 0
 163         return debug_count ();
 164 #else
 165         return TRUE;
 166 #endif
 167 }
 168
 169 static inline gboolean
 170 amd64_is_near_call (guint8 *code)
 171 {
 172         /* Skip REX */
 173         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 174                 code += 1;
 175
 176         return code [0] == 0xe8;
 177 }
 178
 179 static inline void
 180 amd64_patch (unsigned char* code, gpointer target)
 181 {
 182         guint8 rex = 0;
 183
 184         /* Skip REX */
 185         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 186                 rex = code [0];
 187                 code += 1;
 188         }
 189
 190         if ((code [0] & 0xf8) == 0xb8) {
 191                 /* amd64_set_reg_template */
 192                 *(guint64*)(code + 1) = (guint64)target;
 193         }
 194         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 195                 /* mov 0(%rip), %dreg */
 196                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 197         }
 198         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 199                 /* call *<OFFSET>(%rip) */
 200                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 201         }
 202         else if ((code [0] == 0xe8)) {
 203                 /* call <DISP> */
 204                 gint64 disp = (guint8*)target - (guint8*)code;
 205                 g_assert (amd64_is_imm32 (disp));
 206                 x86_patch (code, (unsigned char*)target);
 207         }
 208         else
 209                 x86_patch (code, (unsigned char*)target);
 210 }
 211
 212 void
 213 mono_amd64_patch (unsigned char* code, gpointer target)
 214 {
 215         amd64_patch (code, target);
 216 }
 217
 218 typedef enum {
 219         ArgInIReg,
 220         ArgInFloatSSEReg,
 221         ArgInDoubleSSEReg,
 222         ArgOnStack,
 223         ArgValuetypeInReg,
 224         ArgValuetypeAddrInIReg,
 225         ArgNone /* only in pair_storage */
 226 } ArgStorage;
 227
 228 typedef struct {
 229         gint16 offset;
 230         gint8  reg;
 231         ArgStorage storage;
 232
 233         /* Only if storage == ArgValuetypeInReg */
 234         ArgStorage pair_storage [2];
 235         gint8 pair_regs [2];
 236 } ArgInfo;
 237
 238 typedef struct {
 239         int nargs;
 240         guint32 stack_usage;
 241         guint32 reg_usage;
 242         guint32 freg_usage;
 243         gboolean need_stack_align;
 244         ArgInfo ret;
 245         ArgInfo sig_cookie;
 246         ArgInfo args [1];
 247 } CallInfo;
 248
 249 #define DEBUG(a) if (cfg->verbose_level > 1) a
 250
 251 #ifdef PLATFORM_WIN32
 252 #define PARAM_REGS 4
 253
 254 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 255
 256 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 257 #else
 258 #define PARAM_REGS 6
 259
 260 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 261
 262  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 263 #endif
 264
 265 static void inline
 266 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 267 {
 268     ainfo->offset = *stack_size;
 269
 270     if (*gr >= PARAM_REGS) {
 271                 ainfo->storage = ArgOnStack;
 272                 (*stack_size) += sizeof (gpointer);
 273     }
 274     else {
 275                 ainfo->storage = ArgInIReg;
 276                 ainfo->reg = param_regs [*gr];
 277                 (*gr) ++;
 278     }
 279 }
 280
 281 #ifdef PLATFORM_WIN32
 282 #define FLOAT_PARAM_REGS 4
 283 #else
 284 #define FLOAT_PARAM_REGS 8
 285 #endif
 286
 287 static void inline
 288 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 289 {
 290     ainfo->offset = *stack_size;
 291
 292     if (*gr >= FLOAT_PARAM_REGS) {
 293                 ainfo->storage = ArgOnStack;
 294                 (*stack_size) += sizeof (gpointer);
 295     }
 296     else {
 297                 /* A double register */
 298                 if (is_double)
 299                         ainfo->storage = ArgInDoubleSSEReg;
 300                 else
 301                         ainfo->storage = ArgInFloatSSEReg;
 302                 ainfo->reg = *gr;
 303                 (*gr) += 1;
 304     }
 305 }
 306
 307 typedef enum ArgumentClass {
 308         ARG_CLASS_NO_CLASS,
 309         ARG_CLASS_MEMORY,
 310         ARG_CLASS_INTEGER,
 311         ARG_CLASS_SSE
 312 } ArgumentClass;
 313
 314 static ArgumentClass
 315 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 316 {
 317         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 318         MonoType *ptype;
 319
 320         ptype = mini_type_get_underlying_type (NULL, type);
 321         switch (ptype->type) {
 322         case MONO_TYPE_BOOLEAN:
 323         case MONO_TYPE_CHAR:
 324         case MONO_TYPE_I1:
 325         case MONO_TYPE_U1:
 326         case MONO_TYPE_I2:
 327         case MONO_TYPE_U2:
 328         case MONO_TYPE_I4:
 329         case MONO_TYPE_U4:
 330         case MONO_TYPE_I:
 331         case MONO_TYPE_U:
 332         case MONO_TYPE_STRING:
 333         case MONO_TYPE_OBJECT:
 334         case MONO_TYPE_CLASS:
 335         case MONO_TYPE_SZARRAY:
 336         case MONO_TYPE_PTR:
 337         case MONO_TYPE_FNPTR:
 338         case MONO_TYPE_ARRAY:
 339         case MONO_TYPE_I8:
 340         case MONO_TYPE_U8:
 341                 class2 = ARG_CLASS_INTEGER;
 342                 break;
 343         case MONO_TYPE_R4:
 344         case MONO_TYPE_R8:
 345 #ifdef PLATFORM_WIN32
 346                 class2 = ARG_CLASS_INTEGER;
 347 #else
 348                 class2 = ARG_CLASS_SSE;
 349 #endif
 350                 break;
 351
 352         case MONO_TYPE_TYPEDBYREF:
 353                 g_assert_not_reached ();
 354
 355         case MONO_TYPE_GENERICINST:
 356                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 357                         class2 = ARG_CLASS_INTEGER;
 358                         break;
 359                 }
 360                 /* fall through */
 361         case MONO_TYPE_VALUETYPE: {
 362                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 363                 int i;
 364
 365                 for (i = 0; i < info->num_fields; ++i) {
 366                         class2 = class1;
 367                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 368                 }
 369                 break;
 370         }
 371         default:
 372                 g_assert_not_reached ();
 373         }
 374
 375         /* Merge */
 376         if (class1 == class2)
 377                 ;
 378         else if (class1 == ARG_CLASS_NO_CLASS)
 379                 class1 = class2;
 380         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 381                 class1 = ARG_CLASS_MEMORY;
 382         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 383                 class1 = ARG_CLASS_INTEGER;
 384         else
 385                 class1 = ARG_CLASS_SSE;
 386
 387         return class1;
 388 }
 389
 390 static void
 391 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 392                gboolean is_return,
 393                guint32 *gr, guint32 *fr, guint32 *stack_size)
 394 {
 395         guint32 size, quad, nquads, i;
 396         ArgumentClass args [2];
 397         MonoMarshalType *info = NULL;
 398         MonoClass *klass;
 399         MonoGenericSharingContext tmp_gsctx;
 400
 401         /*
 402          * The gsctx currently contains no data, it is only used for checking whenever
 403          * open types are allowed, some callers like mono_arch_get_argument_info ()
 404          * don't pass it to us, so work around that.
 405          */
 406         if (!gsctx)
 407                 gsctx = &tmp_gsctx;
 408
 409         klass = mono_class_from_mono_type (type);
 410         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 411 #ifndef PLATFORM_WIN32
 412         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 413                 /* We pass and return vtypes of size 8 in a register */
 414         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 415 #else
 416         if (!sig->pinvoke) {
 417 #endif
 418                 /* Allways pass in memory */
 419                 ainfo->offset = *stack_size;
 420                 *stack_size += ALIGN_TO (size, 8);
 421                 ainfo->storage = ArgOnStack;
 422
 423                 return;
 424         }
 425
 426         /* FIXME: Handle structs smaller than 8 bytes */
 427         //if ((size % 8) != 0)
 428         //      NOT_IMPLEMENTED;
 429
 430         if (size > 8)
 431                 nquads = 2;
 432         else
 433                 nquads = 1;
 434
 435         if (!sig->pinvoke) {
 436                 /* Always pass in 1 or 2 integer registers */
 437                 args [0] = ARG_CLASS_INTEGER;
 438                 args [1] = ARG_CLASS_INTEGER;
 439                 /* Only the simplest cases are supported */
 440                 if (is_return && nquads != 1) {
 441                         args [0] = ARG_CLASS_MEMORY;
 442                         args [1] = ARG_CLASS_MEMORY;
 443                 }
 444         } else {
 445                 /*
 446                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 447                  * The X87 and SSEUP stuff is left out since there are no such types in
 448                  * the CLR.
 449                  */
 450                 info = mono_marshal_load_type_info (klass);
 451                 g_assert (info);
 452
 453 #ifndef PLATFORM_WIN32
 454                 if (info->native_size > 16) {
 455                         ainfo->offset = *stack_size;
 456                         *stack_size += ALIGN_TO (info->native_size, 8);
 457                         ainfo->storage = ArgOnStack;
 458
 459                         return;
 460                 }
 461 #else
 462                 switch (info->native_size) {
 463                 case 1: case 2: case 4: case 8:
 464                         break;
 465                 default:
 466                         if (is_return) {
 467                                 ainfo->storage = ArgOnStack;
 468                                 ainfo->offset = *stack_size;
 469                                 *stack_size += ALIGN_TO (info->native_size, 8);
 470                         }
 471                         else {
 472                                 ainfo->storage = ArgValuetypeAddrInIReg;
 473
 474                                 if (*gr < PARAM_REGS) {
 475                                         ainfo->pair_storage [0] = ArgInIReg;
 476                                         ainfo->pair_regs [0] = param_regs [*gr];
 477                                         (*gr) ++;
 478                                 }
 479                                 else {
 480                                         ainfo->pair_storage [0] = ArgOnStack;
 481                                         ainfo->offset = *stack_size;
 482                                         *stack_size += 8;
 483                                 }
 484                         }
 485
 486                         return;
 487                 }
 488 #endif
 489
 490                 args [0] = ARG_CLASS_NO_CLASS;
 491                 args [1] = ARG_CLASS_NO_CLASS;
 492                 for (quad = 0; quad < nquads; ++quad) {
 493                         int size;
 494                         guint32 align;
 495                         ArgumentClass class1;
 496
 497                         if (info->num_fields == 0)
 498                                 class1 = ARG_CLASS_MEMORY;
 499                         else
 500                                 class1 = ARG_CLASS_NO_CLASS;
 501                         for (i = 0; i < info->num_fields; ++i) {
 502                                 size = mono_marshal_type_size (info->fields [i].field->type,
 503                                                                                            info->fields [i].mspec,
 504                                                                                            &align, TRUE, klass->unicode);
 505                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 506                                         /* Unaligned field */
 507                                         NOT_IMPLEMENTED;
 508                                 }
 509
 510                                 /* Skip fields in other quad */
 511                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 512                                         continue;
 513                                 if ((quad == 1) && (info->fields [i].offset < 8))
 514                                         continue;
 515
 516                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 517                         }
 518                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 519                         args [quad] = class1;
 520                 }
 521         }
 522
 523         /* Post merger cleanup */
 524         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 525                 args [0] = args [1] = ARG_CLASS_MEMORY;
 526
 527         /* Allocate registers */
 528         {
 529                 int orig_gr = *gr;
 530                 int orig_fr = *fr;
 531
 532                 ainfo->storage = ArgValuetypeInReg;
 533                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 534                 for (quad = 0; quad < nquads; ++quad) {
 535                         switch (args [quad]) {
 536                         case ARG_CLASS_INTEGER:
 537                                 if (*gr >= PARAM_REGS)
 538                                         args [quad] = ARG_CLASS_MEMORY;
 539                                 else {
 540                                         ainfo->pair_storage [quad] = ArgInIReg;
 541                                         if (is_return)
 542                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 543                                         else
 544                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 545                                         (*gr) ++;
 546                                 }
 547                                 break;
 548                         case ARG_CLASS_SSE:
 549                                 if (*fr >= FLOAT_PARAM_REGS)
 550                                         args [quad] = ARG_CLASS_MEMORY;
 551                                 else {
 552                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 553                                         ainfo->pair_regs [quad] = *fr;
 554                                         (*fr) ++;
 555                                 }
 556                                 break;
 557                         case ARG_CLASS_MEMORY:
 558                                 break;
 559                         default:
 560                                 g_assert_not_reached ();
 561                         }
 562                 }
 563
 564                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 565                         /* Revert possible register assignments */
 566                         *gr = orig_gr;
 567                         *fr = orig_fr;
 568
 569                         ainfo->offset = *stack_size;
 570                         if (sig->pinvoke)
 571                                 *stack_size += ALIGN_TO (info->native_size, 8);
 572                         else
 573                                 *stack_size += nquads * sizeof (gpointer);
 574                         ainfo->storage = ArgOnStack;
 575                 }
 576         }
 577 }
 578
 579 /*
 580  * get_call_info:
 581  *
 582  *  Obtain information about a call according to the calling convention.
 583  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 584  * Draft Version 0.23" document for more information.
 585  */
 586 static CallInfo*
 587 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 588 {
 589         guint32 i, gr, fr;
 590         MonoType *ret_type;
 591         int n = sig->hasthis + sig->param_count;
 592         guint32 stack_size = 0;
 593         CallInfo *cinfo;
 594
 595         if (mp)
 596                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 597         else
 598                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 599
 600         gr = 0;
 601         fr = 0;
 602
 603         /* return value */
 604         {
 605                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 606                 switch (ret_type->type) {
 607                 case MONO_TYPE_BOOLEAN:
 608                 case MONO_TYPE_I1:
 609                 case MONO_TYPE_U1:
 610                 case MONO_TYPE_I2:
 611                 case MONO_TYPE_U2:
 612                 case MONO_TYPE_CHAR:
 613                 case MONO_TYPE_I4:
 614                 case MONO_TYPE_U4:
 615                 case MONO_TYPE_I:
 616                 case MONO_TYPE_U:
 617                 case MONO_TYPE_PTR:
 618                 case MONO_TYPE_FNPTR:
 619                 case MONO_TYPE_CLASS:
 620                 case MONO_TYPE_OBJECT:
 621                 case MONO_TYPE_SZARRAY:
 622                 case MONO_TYPE_ARRAY:
 623                 case MONO_TYPE_STRING:
 624                         cinfo->ret.storage = ArgInIReg;
 625                         cinfo->ret.reg = AMD64_RAX;
 626                         break;
 627                 case MONO_TYPE_U8:
 628                 case MONO_TYPE_I8:
 629                         cinfo->ret.storage = ArgInIReg;
 630                         cinfo->ret.reg = AMD64_RAX;
 631                         break;
 632                 case MONO_TYPE_R4:
 633                         cinfo->ret.storage = ArgInFloatSSEReg;
 634                         cinfo->ret.reg = AMD64_XMM0;
 635                         break;
 636                 case MONO_TYPE_R8:
 637                         cinfo->ret.storage = ArgInDoubleSSEReg;
 638                         cinfo->ret.reg = AMD64_XMM0;
 639                         break;
 640                 case MONO_TYPE_GENERICINST:
 641                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 642                                 cinfo->ret.storage = ArgInIReg;
 643                                 cinfo->ret.reg = AMD64_RAX;
 644                                 break;
 645                         }
 646                         /* fall through */
 647                 case MONO_TYPE_VALUETYPE: {
 648                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 649
 650                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 651                         if (cinfo->ret.storage == ArgOnStack)
 652                                 /* The caller passes the address where the value is stored */
 653                                 add_general (&gr, &stack_size, &cinfo->ret);
 654                         break;
 655                 }
 656                 case MONO_TYPE_TYPEDBYREF:
 657                         /* Same as a valuetype with size 24 */
 658                         add_general (&gr, &stack_size, &cinfo->ret);
 659                         ;
 660                         break;
 661                 case MONO_TYPE_VOID:
 662                         break;
 663                 default:
 664                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 665                 }
 666         }
 667
 668         /* this */
 669         if (sig->hasthis)
 670                 add_general (&gr, &stack_size, cinfo->args + 0);
 671
 672         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 673                 gr = PARAM_REGS;
 674                 fr = FLOAT_PARAM_REGS;
 675
 676                 /* Emit the signature cookie just before the implicit arguments */
 677                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 678         }
 679
 680         for (i = 0; i < sig->param_count; ++i) {
 681                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 682                 MonoType *ptype;
 683
 684 #ifdef PLATFORM_WIN32
 685                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 686                 if (gr > fr)
 687                         fr = gr;
 688                 else if (fr > gr)
 689                         gr = fr;
 690 #endif
 691
 692                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 693                         /* We allways pass the sig cookie on the stack for simplicity */
 694                         /*
 695                          * Prevent implicit arguments + the sig cookie from being passed
 696                          * in registers.
 697                          */
 698                         gr = PARAM_REGS;
 699                         fr = FLOAT_PARAM_REGS;
 700
 701                         /* Emit the signature cookie just before the implicit arguments */
 702                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 703                 }
 704
 705                 if (sig->params [i]->byref) {
 706                         add_general (&gr, &stack_size, ainfo);
 707                         continue;
 708                 }
 709                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 710                 switch (ptype->type) {
 711                 case MONO_TYPE_BOOLEAN:
 712                 case MONO_TYPE_I1:
 713                 case MONO_TYPE_U1:
 714                         add_general (&gr, &stack_size, ainfo);
 715                         break;
 716                 case MONO_TYPE_I2:
 717                 case MONO_TYPE_U2:
 718                 case MONO_TYPE_CHAR:
 719                         add_general (&gr, &stack_size, ainfo);
 720                         break;
 721                 case MONO_TYPE_I4:
 722                 case MONO_TYPE_U4:
 723                         add_general (&gr, &stack_size, ainfo);
 724                         break;
 725                 case MONO_TYPE_I:
 726                 case MONO_TYPE_U:
 727                 case MONO_TYPE_PTR:
 728                 case MONO_TYPE_FNPTR:
 729                 case MONO_TYPE_CLASS:
 730                 case MONO_TYPE_OBJECT:
 731                 case MONO_TYPE_STRING:
 732                 case MONO_TYPE_SZARRAY:
 733                 case MONO_TYPE_ARRAY:
 734                         add_general (&gr, &stack_size, ainfo);
 735                         break;
 736                 case MONO_TYPE_GENERICINST:
 737                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 738                                 add_general (&gr, &stack_size, ainfo);
 739                                 break;
 740                         }
 741                         /* fall through */
 742                 case MONO_TYPE_VALUETYPE:
 743                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 744                         break;
 745                 case MONO_TYPE_TYPEDBYREF:
 746 #ifdef PLATFORM_WIN32
 747                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 748 #else
 749                         stack_size += sizeof (MonoTypedRef);
 750                         ainfo->storage = ArgOnStack;
 751 #endif
 752                         break;
 753                 case MONO_TYPE_U8:
 754                 case MONO_TYPE_I8:
 755                         add_general (&gr, &stack_size, ainfo);
 756                         break;
 757                 case MONO_TYPE_R4:
 758                         add_float (&fr, &stack_size, ainfo, FALSE);
 759                         break;
 760                 case MONO_TYPE_R8:
 761                         add_float (&fr, &stack_size, ainfo, TRUE);
 762                         break;
 763                 default:
 764                         g_assert_not_reached ();
 765                 }
 766         }
 767
 768         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 769                 gr = PARAM_REGS;
 770                 fr = FLOAT_PARAM_REGS;
 771
 772                 /* Emit the signature cookie just before the implicit arguments */
 773                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 774         }
 775
 776 #ifdef PLATFORM_WIN32
 777         // There always is 32 bytes reserved on the stack when calling on Winx64
 778         stack_size += 0x20;
 779 #endif
 780
 781         if (stack_size & 0x8) {
 782                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 783                 cinfo->need_stack_align = TRUE;
 784                 stack_size += 8;
 785         }
 786
 787         cinfo->stack_usage = stack_size;
 788         cinfo->reg_usage = gr;
 789         cinfo->freg_usage = fr;
 790         return cinfo;
 791 }
 792
 793 /*
 794  * mono_arch_get_argument_info:
 795  * @csig:  a method signature
 796  * @param_count: the number of parameters to consider
 797  * @arg_info: an array to store the result infos
 798  *
 799  * Gathers information on parameters such as size, alignment and
 800  * padding. arg_info should be large enought to hold param_count + 1 entries.
 801  *
 802  * Returns the size of the argument area on the stack.
 803  */
 804 int
 805 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 806 {
 807         int k;
 808         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 809         guint32 args_size = cinfo->stack_usage;
 810
 811         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 812         if (csig->hasthis) {
 813                 arg_info [0].offset = 0;
 814         }
 815
 816         for (k = 0; k < param_count; k++) {
 817                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 818                 /* FIXME: */
 819                 arg_info [k + 1].size = 0;
 820         }
 821
 822         g_free (cinfo);
 823
 824         return args_size;
 825 }
 826
 827 static int
 828 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 829 {
 830 #ifndef _MSC_VER
 831         __asm__ __volatile__ ("cpuid"
 832                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 833                 : "a" (id));
 834 #else
 835         int info[4];
 836         __cpuid(info, id);
 837         *p_eax = info[0];
 838         *p_ebx = info[1];
 839         *p_ecx = info[2];
 840         *p_edx = info[3];
 841 #endif
 842         return 1;
 843 }
 844
 845 /*
 846  * Initialize the cpu to execute managed code.
 847  */
 848 void
 849 mono_arch_cpu_init (void)
 850 {
 851 #ifndef _MSC_VER
 852         guint16 fpcw;
 853
 854         /* spec compliance requires running with double precision */
 855         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 856         fpcw &= ~X86_FPCW_PRECC_MASK;
 857         fpcw |= X86_FPCW_PREC_DOUBLE;
 858         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 859         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 860 #else
 861         /* TODO: This is crashing on Win64 right now.
 862         * _control87 (_PC_53, MCW_PC);
 863         */
 864 #endif
 865 }
 866
 867 /*
 868  * Initialize architecture specific code.
 869  */
 870 void
 871 mono_arch_init (void)
 872 {
 873         InitializeCriticalSection (&mini_arch_mutex);
 874 }
 875
 876 /*
 877  * Cleanup architecture specific code.
 878  */
 879 void
 880 mono_arch_cleanup (void)
 881 {
 882         DeleteCriticalSection (&mini_arch_mutex);
 883 }
 884
 885 /*
 886  * This function returns the optimizations supported on this cpu.
 887  */
 888 guint32
 889 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 890 {
 891         int eax, ebx, ecx, edx;
 892         guint32 opts = 0;
 893
 894         /* FIXME: AMD64 */
 895
 896         *exclude_mask = 0;
 897         /* Feature Flags function, flags returned in EDX. */
 898         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 899                 if (edx & (1 << 15)) {
 900                         opts |= MONO_OPT_CMOV;
 901                         if (edx & 1)
 902                                 opts |= MONO_OPT_FCMOV;
 903                         else
 904                                 *exclude_mask |= MONO_OPT_FCMOV;
 905                 } else
 906                         *exclude_mask |= MONO_OPT_CMOV;
 907         }
 908
 909         return opts;
 910 }
 911
 912 GList *
 913 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 914 {
 915         GList *vars = NULL;
 916         int i;
 917
 918         for (i = 0; i < cfg->num_varinfo; i++) {
 919                 MonoInst *ins = cfg->varinfo [i];
 920                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 921
 922                 /* unused vars */
 923                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 924                         continue;
 925
 926                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 927                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 928                         continue;
 929
 930                 if (mono_is_regsize_var (ins->inst_vtype)) {
 931                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 932                         g_assert (i == vmv->idx);
 933                         vars = g_list_prepend (vars, vmv);
 934                 }
 935         }
 936
 937         vars = mono_varlist_sort (cfg, vars, 0);
 938
 939         return vars;
 940 }
 941
 942 /**
 943  * mono_arch_compute_omit_fp:
 944  *
 945  *   Determine whenever the frame pointer can be eliminated.
 946  */
 947 static void
 948 mono_arch_compute_omit_fp (MonoCompile *cfg)
 949 {
 950         MonoMethodSignature *sig;
 951         MonoMethodHeader *header;
 952         int i, locals_size;
 953         CallInfo *cinfo;
 954
 955         if (cfg->arch.omit_fp_computed)
 956                 return;
 957
 958         header = mono_method_get_header (cfg->method);
 959
 960         sig = mono_method_signature (cfg->method);
 961
 962         if (!cfg->arch.cinfo)
 963                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 964         cinfo = cfg->arch.cinfo;
 965
 966         /*
 967          * FIXME: Remove some of the restrictions.
 968          */
 969         cfg->arch.omit_fp = TRUE;
 970         cfg->arch.omit_fp_computed = TRUE;
 971
 972         if (cfg->disable_omit_fp)
 973                 cfg->arch.omit_fp = FALSE;
 974
 975         if (!debug_omit_fp ())
 976                 cfg->arch.omit_fp = FALSE;
 977         /*
 978         if (cfg->method->save_lmf)
 979                 cfg->arch.omit_fp = FALSE;
 980         */
 981         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 982                 cfg->arch.omit_fp = FALSE;
 983         if (header->num_clauses)
 984                 cfg->arch.omit_fp = FALSE;
 985         if (cfg->param_area)
 986                 cfg->arch.omit_fp = FALSE;
 987         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 988                 cfg->arch.omit_fp = FALSE;
 989         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 990                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 991                 cfg->arch.omit_fp = FALSE;
 992         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 993                 ArgInfo *ainfo = &cinfo->args [i];
 994
 995                 if (ainfo->storage == ArgOnStack) {
 996                         /*
 997                          * The stack offset can only be determined when the frame
 998                          * size is known.
 999                          */
1000                         cfg->arch.omit_fp = FALSE;
1001                 }
1002         }
1003
1004         locals_size = 0;
1005         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1006                 MonoInst *ins = cfg->varinfo [i];
1007                 int ialign;
1008
1009                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1010         }
1011
1012         if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
1013                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1014                 cfg->arch.omit_fp = FALSE;
1015         }
1016 }
1017
1018 GList *
1019 mono_arch_get_global_int_regs (MonoCompile *cfg)
1020 {
1021         GList *regs = NULL;
1022
1023         mono_arch_compute_omit_fp (cfg);
1024
1025         if (cfg->globalra) {
1026                 if (cfg->arch.omit_fp)
1027                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1028
1029                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1030                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1031                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1032                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1033                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1034
1035                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1036                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1037                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1038                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1039                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1040                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1041                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1042                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1043         } else {
1044                 if (cfg->arch.omit_fp)
1045                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1046
1047                 /* We use the callee saved registers for global allocation */
1048                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1050                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1051                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1052                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1053         }
1054
1055         return regs;
1056 }
1057
1058 GList*
1059 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1060 {
1061         GList *regs = NULL;
1062         int i;
1063
1064         /* All XMM registers */
1065         for (i = 0; i < 16; ++i)
1066                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1067
1068         return regs;
1069 }
1070
1071 GList*
1072 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1073 {
1074         static GList *r = NULL;
1075
1076         if (r == NULL) {
1077                 GList *regs = NULL;
1078
1079                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1080                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1081                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1082                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1083                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1084                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1085
1086                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1087                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1089                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1093                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1094
1095                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1096         }
1097
1098         return r;
1099 }
1100
1101 GList*
1102 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1103 {
1104         int i;
1105         static GList *r = NULL;
1106
1107         if (r == NULL) {
1108                 GList *regs = NULL;
1109
1110                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1111                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1112
1113                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1114         }
1115
1116         return r;
1117 }
1118
1119 /*
1120  * mono_arch_regalloc_cost:
1121  *
1122  *  Return the cost, in number of memory references, of the action of
1123  * allocating the variable VMV into a register during global register
1124  * allocation.
1125  */
1126 guint32
1127 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1128 {
1129         MonoInst *ins = cfg->varinfo [vmv->idx];
1130
1131         if (cfg->method->save_lmf)
1132                 /* The register is already saved */
1133                 /* substract 1 for the invisible store in the prolog */
1134                 return (ins->opcode == OP_ARG) ? 0 : 1;
1135         else
1136                 /* push+pop */
1137                 return (ins->opcode == OP_ARG) ? 1 : 2;
1138 }
1139
1140 /*
1141  * mono_arch_fill_argument_info:
1142  *
1143  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1144  * of the method.
1145  */
1146 void
1147 mono_arch_fill_argument_info (MonoCompile *cfg)
1148 {
1149         MonoMethodSignature *sig;
1150         MonoMethodHeader *header;
1151         MonoInst *ins;
1152         int i;
1153         CallInfo *cinfo;
1154
1155         header = mono_method_get_header (cfg->method);
1156
1157         sig = mono_method_signature (cfg->method);
1158
1159         cinfo = cfg->arch.cinfo;
1160
1161         /*
1162          * Contrary to mono_arch_allocate_vars (), the information should describe
1163          * where the arguments are at the beginning of the method, not where they can be
1164          * accessed during the execution of the method. The later makes no sense for the
1165          * global register allocator, since a variable can be in more than one location.
1166          */
1167         if (sig->ret->type != MONO_TYPE_VOID) {
1168                 switch (cinfo->ret.storage) {
1169                 case ArgInIReg:
1170                 case ArgInFloatSSEReg:
1171                 case ArgInDoubleSSEReg:
1172                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1173                                 cfg->vret_addr->opcode = OP_REGVAR;
1174                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1175                         }
1176                         else {
1177                                 cfg->ret->opcode = OP_REGVAR;
1178                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1179                         }
1180                         break;
1181                 case ArgValuetypeInReg:
1182                         cfg->ret->opcode = OP_REGOFFSET;
1183                         cfg->ret->inst_basereg = -1;
1184                         cfg->ret->inst_offset = -1;
1185                         break;
1186                 default:
1187                         g_assert_not_reached ();
1188                 }
1189         }
1190
1191         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1192                 ArgInfo *ainfo = &cinfo->args [i];
1193                 MonoType *arg_type;
1194
1195                 ins = cfg->args [i];
1196
1197                 if (sig->hasthis && (i == 0))
1198                         arg_type = &mono_defaults.object_class->byval_arg;
1199                 else
1200                         arg_type = sig->params [i - sig->hasthis];
1201
1202                 switch (ainfo->storage) {
1203                 case ArgInIReg:
1204                 case ArgInFloatSSEReg:
1205                 case ArgInDoubleSSEReg:
1206                         ins->opcode = OP_REGVAR;
1207                         ins->inst_c0 = ainfo->reg;
1208                         break;
1209                 case ArgOnStack:
1210                         ins->opcode = OP_REGOFFSET;
1211                         ins->inst_basereg = -1;
1212                         ins->inst_offset = -1;
1213                         break;
1214                 case ArgValuetypeInReg:
1215                         /* Dummy */
1216                         ins->opcode = OP_NOP;
1217                         break;
1218                 default:
1219                         g_assert_not_reached ();
1220                 }
1221         }
1222 }
1223
1224 void
1225 mono_arch_allocate_vars (MonoCompile *cfg)
1226 {
1227         MonoMethodSignature *sig;
1228         MonoMethodHeader *header;
1229         MonoInst *ins;
1230         int i, offset;
1231         guint32 locals_stack_size, locals_stack_align;
1232         gint32 *offsets;
1233         CallInfo *cinfo;
1234
1235         header = mono_method_get_header (cfg->method);
1236
1237         sig = mono_method_signature (cfg->method);
1238
1239         cinfo = cfg->arch.cinfo;
1240
1241         mono_arch_compute_omit_fp (cfg);
1242
1243         /*
1244          * We use the ABI calling conventions for managed code as well.
1245          * Exception: valuetypes are never passed or returned in registers.
1246          */
1247
1248         if (cfg->arch.omit_fp) {
1249                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1250                 cfg->frame_reg = AMD64_RSP;
1251                 offset = 0;
1252         } else {
1253                 /* Locals are allocated backwards from %fp */
1254                 cfg->frame_reg = AMD64_RBP;
1255                 offset = 0;
1256         }
1257
1258         if (cfg->method->save_lmf) {
1259                 /* Reserve stack space for saving LMF */
1260                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1261                 g_assert (offset == 0);
1262                 if (cfg->arch.omit_fp) {
1263                         cfg->arch.lmf_offset = offset;
1264                         offset += sizeof (MonoLMF);
1265                 }
1266                 else {
1267                         offset += sizeof (MonoLMF);
1268                         cfg->arch.lmf_offset = -offset;
1269                 }
1270         } else {
1271                 if (cfg->arch.omit_fp)
1272                         cfg->arch.reg_save_area_offset = offset;
1273                 /* Reserve space for caller saved registers */
1274                 for (i = 0; i < AMD64_NREG; ++i)
1275                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1276                                 offset += sizeof (gpointer);
1277                         }
1278         }
1279
1280         if (sig->ret->type != MONO_TYPE_VOID) {
1281                 switch (cinfo->ret.storage) {
1282                 case ArgInIReg:
1283                 case ArgInFloatSSEReg:
1284                 case ArgInDoubleSSEReg:
1285                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1286                                 if (cfg->globalra) {
1287                                         cfg->vret_addr->opcode = OP_REGVAR;
1288                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1289                                 } else {
1290                                         /* The register is volatile */
1291                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1292                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1293                                         if (cfg->arch.omit_fp) {
1294                                                 cfg->vret_addr->inst_offset = offset;
1295                                                 offset += 8;
1296                                         } else {
1297                                                 offset += 8;
1298                                                 cfg->vret_addr->inst_offset = -offset;
1299                                         }
1300                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1301                                                 printf ("vret_addr =");
1302                                                 mono_print_ins (cfg->vret_addr);
1303                                         }
1304                                 }
1305                         }
1306                         else {
1307                                 cfg->ret->opcode = OP_REGVAR;
1308                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1309                         }
1310                         break;
1311                 case ArgValuetypeInReg:
1312                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1313                         cfg->ret->opcode = OP_REGOFFSET;
1314                         cfg->ret->inst_basereg = cfg->frame_reg;
1315                         if (cfg->arch.omit_fp) {
1316                                 cfg->ret->inst_offset = offset;
1317                                 offset += 16;
1318                         } else {
1319                                 offset += 16;
1320                                 cfg->ret->inst_offset = - offset;
1321                         }
1322                         break;
1323                 default:
1324                         g_assert_not_reached ();
1325                 }
1326                 if (!cfg->globalra)
1327                         cfg->ret->dreg = cfg->ret->inst_c0;
1328         }
1329
1330         /* Allocate locals */
1331         if (!cfg->globalra) {
1332                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1333                 if (locals_stack_align) {
1334                         offset += (locals_stack_align - 1);
1335                         offset &= ~(locals_stack_align - 1);
1336                 }
1337                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1338                         if (offsets [i] != -1) {
1339                                 MonoInst *ins = cfg->varinfo [i];
1340                                 ins->opcode = OP_REGOFFSET;
1341                                 ins->inst_basereg = cfg->frame_reg;
1342                                 if (cfg->arch.omit_fp)
1343                                         ins->inst_offset = (offset + offsets [i]);
1344                                 else
1345                                         ins->inst_offset = - (offset + offsets [i]);
1346                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1347                         }
1348                 }
1349                 offset += locals_stack_size;
1350         }
1351
1352         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1353                 g_assert (!cfg->arch.omit_fp);
1354                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1355                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1356         }
1357
1358         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1359                 ins = cfg->args [i];
1360                 if (ins->opcode != OP_REGVAR) {
1361                         ArgInfo *ainfo = &cinfo->args [i];
1362                         gboolean inreg = TRUE;
1363                         MonoType *arg_type;
1364
1365                         if (sig->hasthis && (i == 0))
1366                                 arg_type = &mono_defaults.object_class->byval_arg;
1367                         else
1368                                 arg_type = sig->params [i - sig->hasthis];
1369
1370                         if (cfg->globalra) {
1371                                 /* The new allocator needs info about the original locations of the arguments */
1372                                 switch (ainfo->storage) {
1373                                 case ArgInIReg:
1374                                 case ArgInFloatSSEReg:
1375                                 case ArgInDoubleSSEReg:
1376                                         ins->opcode = OP_REGVAR;
1377                                         ins->inst_c0 = ainfo->reg;
1378                                         break;
1379                                 case ArgOnStack:
1380                                         g_assert (!cfg->arch.omit_fp);
1381                                         ins->opcode = OP_REGOFFSET;
1382                                         ins->inst_basereg = cfg->frame_reg;
1383                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1384                                         break;
1385                                 case ArgValuetypeInReg:
1386                                         ins->opcode = OP_REGOFFSET;
1387                                         ins->inst_basereg = cfg->frame_reg;
1388                                         /* These arguments are saved to the stack in the prolog */
1389                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1390                                         if (cfg->arch.omit_fp) {
1391                                                 ins->inst_offset = offset;
1392                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1393                                         } else {
1394                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1395                                                 ins->inst_offset = - offset;
1396                                         }
1397                                         break;
1398                                 default:
1399                                         g_assert_not_reached ();
1400                                 }
1401
1402                                 continue;
1403                         }
1404
1405                         /* FIXME: Allocate volatile arguments to registers */
1406                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1407                                 inreg = FALSE;
1408
1409                         /*
1410                          * Under AMD64, all registers used to pass arguments to functions
1411                          * are volatile across calls.
1412                          * FIXME: Optimize this.
1413                          */
1414                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1415                                 inreg = FALSE;
1416
1417                         ins->opcode = OP_REGOFFSET;
1418
1419                         switch (ainfo->storage) {
1420                         case ArgInIReg:
1421                         case ArgInFloatSSEReg:
1422                         case ArgInDoubleSSEReg:
1423                                 if (inreg) {
1424                                         ins->opcode = OP_REGVAR;
1425                                         ins->dreg = ainfo->reg;
1426                                 }
1427                                 break;
1428                         case ArgOnStack:
1429                                 g_assert (!cfg->arch.omit_fp);
1430                                 ins->opcode = OP_REGOFFSET;
1431                                 ins->inst_basereg = cfg->frame_reg;
1432                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1433                                 break;
1434                         case ArgValuetypeInReg:
1435                                 break;
1436                         case ArgValuetypeAddrInIReg: {
1437                                 MonoInst *indir;
1438                                 g_assert (!cfg->arch.omit_fp);
1439
1440                                 MONO_INST_NEW (cfg, indir, 0);
1441                                 indir->opcode = OP_REGOFFSET;
1442                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1443                                         indir->inst_basereg = cfg->frame_reg;
1444                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1445                                         offset += (sizeof (gpointer));
1446                                         indir->inst_offset = - offset;
1447                                 }
1448                                 else {
1449                                         indir->inst_basereg = cfg->frame_reg;
1450                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1451                                 }
1452
1453                                 ins->opcode = OP_VTARG_ADDR;
1454                                 ins->inst_left = indir;
1455
1456                                 break;
1457                         }
1458                         default:
1459                                 NOT_IMPLEMENTED;
1460                         }
1461
1462                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1463                                 ins->opcode = OP_REGOFFSET;
1464                                 ins->inst_basereg = cfg->frame_reg;
1465                                 /* These arguments are saved to the stack in the prolog */
1466                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1467                                 if (cfg->arch.omit_fp) {
1468                                         ins->inst_offset = offset;
1469                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1470                                 } else {
1471                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1472                                         ins->inst_offset = - offset;
1473                                 }
1474                         }
1475                 }
1476         }
1477
1478         cfg->stack_offset = offset;
1479 }
1480
1481 void
1482 mono_arch_create_vars (MonoCompile *cfg)
1483 {
1484         MonoMethodSignature *sig;
1485         CallInfo *cinfo;
1486
1487         sig = mono_method_signature (cfg->method);
1488
1489         if (!cfg->arch.cinfo)
1490                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1491         cinfo = cfg->arch.cinfo;
1492
1493         if (cinfo->ret.storage == ArgValuetypeInReg)
1494                 cfg->ret_var_is_local = TRUE;
1495
1496         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1497                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1498                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1499                         printf ("vret_addr = ");
1500                         mono_print_ins (cfg->vret_addr);
1501                 }
1502         }
1503 }
1504
1505 static void
1506 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1507 {
1508         MonoInst *ins;
1509
1510         switch (storage) {
1511         case ArgInIReg:
1512                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1513                 ins->dreg = mono_alloc_ireg (cfg);
1514                 ins->sreg1 = tree->dreg;
1515                 MONO_ADD_INS (cfg->cbb, ins);
1516                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1517                 break;
1518         case ArgInFloatSSEReg:
1519                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1520                 ins->dreg = mono_alloc_freg (cfg);
1521                 ins->sreg1 = tree->dreg;
1522                 MONO_ADD_INS (cfg->cbb, ins);
1523
1524                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1525                 break;
1526         case ArgInDoubleSSEReg:
1527                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1528                 ins->dreg = mono_alloc_freg (cfg);
1529                 ins->sreg1 = tree->dreg;
1530                 MONO_ADD_INS (cfg->cbb, ins);
1531
1532                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1533
1534                 break;
1535         default:
1536                 g_assert_not_reached ();
1537         }
1538 }
1539
1540 static int
1541 arg_storage_to_load_membase (ArgStorage storage)
1542 {
1543         switch (storage) {
1544         case ArgInIReg:
1545                 return OP_LOAD_MEMBASE;
1546         case ArgInDoubleSSEReg:
1547                 return OP_LOADR8_MEMBASE;
1548         case ArgInFloatSSEReg:
1549                 return OP_LOADR4_MEMBASE;
1550         default:
1551                 g_assert_not_reached ();
1552         }
1553
1554         return -1;
1555 }
1556
1557 static void
1558 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1559 {
1560         MonoInst *arg;
1561         MonoMethodSignature *tmp_sig;
1562         MonoInst *sig_arg;
1563
1564         if (call->tail_call)
1565                 NOT_IMPLEMENTED;
1566
1567         /* FIXME: Add support for signature tokens to AOT */
1568         cfg->disable_aot = TRUE;
1569
1570         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1571
1572         /*
1573          * mono_ArgIterator_Setup assumes the signature cookie is
1574          * passed first and all the arguments which were before it are
1575          * passed on the stack after the signature. So compensate by
1576          * passing a different signature.
1577          */
1578         tmp_sig = mono_metadata_signature_dup (call->signature);
1579         tmp_sig->param_count -= call->signature->sentinelpos;
1580         tmp_sig->sentinelpos = 0;
1581         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1582
1583         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1584         sig_arg->dreg = mono_alloc_ireg (cfg);
1585         sig_arg->inst_p0 = tmp_sig;
1586         MONO_ADD_INS (cfg->cbb, sig_arg);
1587
1588         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1589         arg->sreg1 = sig_arg->dreg;
1590         MONO_ADD_INS (cfg->cbb, arg);
1591 }
1592
1593 #define NEW_VARSTORE(cfg,dest,var,vartype,inst) do {    \
1594         MONO_INST_NEW ((cfg), (dest), OP_MOVE); \
1595                 (dest)->opcode = mono_type_to_regmove ((cfg), (vartype));    \
1596                 (dest)->klass = (var)->klass;   \
1597         (dest)->sreg1 = (inst)->dreg; \
1598                 (dest)->dreg = (var)->dreg;   \
1599         if ((dest)->opcode == OP_VMOVE) (dest)->klass = mono_class_from_mono_type ((vartype)); \
1600         } while (0)
1601
1602 #define NEW_ARGSTORE(cfg,dest,num,inst) NEW_VARSTORE ((cfg), (dest), cfg->args [(num)], cfg->arg_types [(num)], (inst))
1603
1604 #define EMIT_NEW_ARGSTORE(cfg,dest,num,inst) do { NEW_ARGSTORE ((cfg), (dest), (num), (inst)); MONO_ADD_INS ((cfg)->cbb, (dest)); } while (0)
1605
1606 void
1607 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1608 {
1609         MonoInst *arg, *in;
1610         MonoMethodSignature *sig;
1611         int i, n, stack_size;
1612         CallInfo *cinfo;
1613         ArgInfo *ainfo;
1614
1615         stack_size = 0;
1616
1617         sig = call->signature;
1618         n = sig->param_count + sig->hasthis;
1619
1620         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1621
1622         if (cinfo->need_stack_align) {
1623                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1624         }
1625
1626         /*
1627          * Emit all parameters passed in registers in non-reverse order for better readability
1628          * and to help the optimization in emit_prolog ().
1629          */
1630         for (i = 0; i < n; ++i) {
1631                 ainfo = cinfo->args + i;
1632
1633                 in = call->args [i];
1634
1635                 if (ainfo->storage == ArgInIReg)
1636                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1637         }
1638
1639         for (i = n - 1; i >= 0; --i) {
1640                 ainfo = cinfo->args + i;
1641
1642                 in = call->args [i];
1643
1644                 switch (ainfo->storage) {
1645                 case ArgInIReg:
1646                         /* Already done */
1647                         break;
1648                 case ArgInFloatSSEReg:
1649                 case ArgInDoubleSSEReg:
1650                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1651                         break;
1652                 case ArgOnStack:
1653                 case ArgValuetypeInReg:
1654                 case ArgValuetypeAddrInIReg:
1655                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1656                                 MonoInst *call_inst = (MonoInst*)call;
1657                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1658                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1659                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1660                                 guint32 align;
1661                                 guint32 size;
1662
1663                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1664                                         size = sizeof (MonoTypedRef);
1665                                         align = sizeof (gpointer);
1666                                 }
1667                                 else {
1668                                         if (sig->pinvoke)
1669                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1670                                         else {
1671                                                 /*
1672                                                  * Other backends use mono_type_stack_size (), but that
1673                                                  * aligns the size to 8, which is larger than the size of
1674                                                  * the source, leading to reads of invalid memory if the
1675                                                  * source is at the end of address space.
1676                                                  */
1677                                                 size = mono_class_value_size (in->klass, &align);
1678                                         }
1679                                 }
1680                                 g_assert (in->klass);
1681
1682                                 if (size > 0) {
1683                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1684                                         arg->sreg1 = in->dreg;
1685                                         arg->klass = in->klass;
1686                                         arg->backend.size = size;
1687                                         arg->inst_p0 = call;
1688                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1689                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1690
1691                                         MONO_ADD_INS (cfg->cbb, arg);
1692                                 }
1693                         } else {
1694                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1695                                 arg->sreg1 = in->dreg;
1696                                 if (!sig->params [i - sig->hasthis]->byref) {
1697                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1698                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1699                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
1700                                                 arg->inst_destbasereg = X86_ESP;
1701                                                 arg->inst_offset = 0;
1702                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1703                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1704                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
1705                                                 arg->inst_destbasereg = X86_ESP;
1706                                                 arg->inst_offset = 0;
1707                                         }
1708                                 }
1709                                 MONO_ADD_INS (cfg->cbb, arg);
1710                         }
1711                         break;
1712                 default:
1713                         g_assert_not_reached ();
1714                 }
1715
1716                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1717                         /* Emit the signature cookie just before the implicit arguments */
1718                         emit_sig_cookie (cfg, call, cinfo);
1719         }
1720
1721         /* Handle the case where there are no implicit arguments */
1722         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1723                 emit_sig_cookie (cfg, call, cinfo);
1724
1725         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1726                 MonoInst *vtarg;
1727
1728                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1729                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1730                                 /*
1731                                  * Tell the JIT to use a more efficient calling convention: call using
1732                                  * OP_CALL, compute the result location after the call, and save the
1733                                  * result there.
1734                                  */
1735                                 call->vret_in_reg = TRUE;
1736                                 /*
1737                                  * Nullify the instruction computing the vret addr to enable
1738                                  * future optimizations.
1739                                  */
1740                                 if (call->vret_var)
1741                                         NULLIFY_INS (call->vret_var);
1742                         } else {
1743                                 if (call->tail_call)
1744                                         NOT_IMPLEMENTED;
1745                                 /*
1746                                  * The valuetype is in RAX:RDX after the call, need to be copied to
1747                                  * the stack. Push the address here, so the call instruction can
1748                                  * access it.
1749                                  */
1750                                 if (!cfg->arch.vret_addr_loc) {
1751                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1752                                         /* Prevent it from being register allocated or optimized away */
1753                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1754                                 }
1755
1756                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
1757                         }
1758                 }
1759                 else {
1760                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1761                         vtarg->sreg1 = call->vret_var->dreg;
1762                         vtarg->dreg = mono_alloc_preg (cfg);
1763                         MONO_ADD_INS (cfg->cbb, vtarg);
1764
1765                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1766                 }
1767         }
1768
1769 #ifdef PLATFORM_WIN32
1770         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
1771                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
1772         }
1773 #endif
1774
1775         if (cfg->method->save_lmf) {
1776                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1777                 MONO_ADD_INS (cfg->cbb, arg);
1778         }
1779
1780         call->stack_usage = cinfo->stack_usage;
1781 }
1782
1783 void
1784 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1785 {
1786         MonoInst *arg;
1787         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1788         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1789         int size = ins->backend.size;
1790
1791         if (ainfo->storage == ArgValuetypeInReg) {
1792                 MonoInst *load;
1793                 int part;
1794
1795                 for (part = 0; part < 2; ++part) {
1796                         if (ainfo->pair_storage [part] == ArgNone)
1797                                 continue;
1798
1799                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
1800                         load->inst_basereg = src->dreg;
1801                         load->inst_offset = part * sizeof (gpointer);
1802
1803                         switch (ainfo->pair_storage [part]) {
1804                         case ArgInIReg:
1805                                 load->dreg = mono_alloc_ireg (cfg);
1806                                 break;
1807                         case ArgInDoubleSSEReg:
1808                         case ArgInFloatSSEReg:
1809                                 load->dreg = mono_alloc_freg (cfg);
1810                                 break;
1811                         default:
1812                                 g_assert_not_reached ();
1813                         }
1814                         MONO_ADD_INS (cfg->cbb, load);
1815
1816                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
1817                 }
1818         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
1819                 MonoInst *vtaddr, *load;
1820                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
1821
1822                 MONO_INST_NEW (cfg, load, OP_LDADDR);
1823                 load->inst_p0 = vtaddr;
1824                 vtaddr->flags |= MONO_INST_INDIRECT;
1825                 load->type = STACK_MP;
1826                 load->klass = vtaddr->klass;
1827                 load->dreg = mono_alloc_ireg (cfg);
1828                 MONO_ADD_INS (cfg->cbb, load);
1829                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
1830
1831                 if (ainfo->pair_storage [0] == ArgInIReg) {
1832                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
1833                         arg->dreg = mono_alloc_ireg (cfg);
1834                         arg->sreg1 = load->dreg;
1835                         arg->inst_imm = 0;
1836                         MONO_ADD_INS (cfg->cbb, arg);
1837                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
1838                 } else {
1839                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1840                         arg->sreg1 = load->dreg;
1841                         MONO_ADD_INS (cfg->cbb, arg);
1842                 }
1843         } else {
1844                 if (size == 8) {
1845                         /* Can't use this for < 8 since it does an 8 byte memory load */
1846                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1847                         arg->inst_basereg = src->dreg;
1848                         arg->inst_offset = 0;
1849                         MONO_ADD_INS (cfg->cbb, arg);
1850                 } else if (size <= 40) {
1851                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
1852                         mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1853                 } else {
1854                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1855                         arg->inst_basereg = src->dreg;
1856                         arg->inst_offset = 0;
1857                         arg->inst_imm = size;
1858                         MONO_ADD_INS (cfg->cbb, arg);
1859                 }
1860         }
1861 }
1862
1863 void
1864 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1865 {
1866         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
1867
1868         if (!ret->byref) {
1869                 if (ret->type == MONO_TYPE_R4) {
1870                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
1871                         return;
1872                 } else if (ret->type == MONO_TYPE_R8) {
1873                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1874                         return;
1875                 }
1876         }
1877
1878         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1879 }
1880
1881 #define EMIT_COND_BRANCH(ins,cond,sign) \
1882 if (ins->flags & MONO_INST_BRLABEL) { \
1883         if (ins->inst_i0->inst_c0) { \
1884                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1885         } else { \
1886                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1887                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1888                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1889                         x86_branch8 (code, cond, 0, sign); \
1890                 else \
1891                         x86_branch32 (code, cond, 0, sign); \
1892         } \
1893 } else { \
1894         if (ins->inst_true_bb->native_offset) { \
1895                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1896         } else { \
1897                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1898                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1899                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1900                         x86_branch8 (code, cond, 0, sign); \
1901                 else \
1902                         x86_branch32 (code, cond, 0, sign); \
1903         } \
1904 }
1905
1906 /* emit an exception if condition is fail */
1907 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1908         do {                                                        \
1909                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1910                 if (tins == NULL) {                                                                             \
1911                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1912                                         MONO_PATCH_INFO_EXC, exc_name);  \
1913                         x86_branch32 (code, cond, 0, signed);               \
1914                 } else {        \
1915                         EMIT_COND_BRANCH (tins, cond, signed);  \
1916                 }                       \
1917         } while (0);
1918
1919 #define EMIT_FPCOMPARE(code) do { \
1920         amd64_fcompp (code); \
1921         amd64_fnstsw (code); \
1922 } while (0);
1923
1924 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1925     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1926         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1927         amd64_ ##op (code); \
1928         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1929         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1930 } while (0);
1931
1932 static guint8*
1933 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1934 {
1935         gboolean no_patch = FALSE;
1936
1937         /*
1938          * FIXME: Add support for thunks
1939          */
1940         {
1941                 gboolean near_call = FALSE;
1942
1943                 /*
1944                  * Indirect calls are expensive so try to make a near call if possible.
1945                  * The caller memory is allocated by the code manager so it is
1946                  * guaranteed to be at a 32 bit offset.
1947                  */
1948
1949                 if (patch_type != MONO_PATCH_INFO_ABS) {
1950                         /* The target is in memory allocated using the code manager */
1951                         near_call = TRUE;
1952
1953                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1954                                 if (((MonoMethod*)data)->klass->image->aot_module)
1955                                         /* The callee might be an AOT method */
1956                                         near_call = FALSE;
1957                                 if (((MonoMethod*)data)->dynamic)
1958                                         /* The target is in malloc-ed memory */
1959                                         near_call = FALSE;
1960                         }
1961
1962                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1963                                 /*
1964                                  * The call might go directly to a native function without
1965                                  * the wrapper.
1966                                  */
1967                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1968                                 if (mi) {
1969                                         gconstpointer target = mono_icall_get_wrapper (mi);
1970                                         if ((((guint64)target) >> 32) != 0)
1971                                                 near_call = FALSE;
1972                                 }
1973                         }
1974                 }
1975                 else {
1976                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
1977                                 /*
1978                                  * This is not really an optimization, but required because the
1979                                  * generic class init trampolines use R11 to pass the vtable.
1980                                  */
1981                                 near_call = TRUE;
1982                         } else {
1983                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1984                                 if (info) {
1985                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1986                                                 strstr (cfg->method->name, info->name)) {
1987                                                 /* A call to the wrapped function */
1988                                                 if ((((guint64)data) >> 32) == 0)
1989                                                         near_call = TRUE;
1990                                                 no_patch = TRUE;
1991                                         }
1992                                         else if (info->func == info->wrapper) {
1993                                                 /* No wrapper */
1994                                                 if ((((guint64)info->func) >> 32) == 0)
1995                                                         near_call = TRUE;
1996                                         }
1997                                         else {
1998                                                 /* See the comment in mono_codegen () */
1999                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2000                                                         near_call = TRUE;
2001                                         }
2002                                 }
2003                                 else if ((((guint64)data) >> 32) == 0) {
2004                                         near_call = TRUE;
2005                                         no_patch = TRUE;
2006                                 }
2007                         }
2008                 }
2009
2010                 if (cfg->method->dynamic)
2011                         /* These methods are allocated using malloc */
2012                         near_call = FALSE;
2013
2014                 if (cfg->compile_aot) {
2015                         near_call = TRUE;
2016                         no_patch = TRUE;
2017                 }
2018
2019 #ifdef MONO_ARCH_NOMAP32BIT
2020                 near_call = FALSE;
2021 #endif
2022
2023                 if (near_call) {
2024                         /*
2025                          * Align the call displacement to an address divisible by 4 so it does
2026                          * not span cache lines. This is required for code patching to work on SMP
2027                          * systems.
2028                          */
2029                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2030                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2031                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2032                         amd64_call_code (code, 0);
2033                 }
2034                 else {
2035                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2036                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2037                         amd64_call_reg (code, GP_SCRATCH_REG);
2038                 }
2039         }
2040
2041         return code;
2042 }
2043
2044 static inline guint8*
2045 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2046 {
2047 #ifdef PLATFORM_WIN32
2048         if (win64_adjust_stack)
2049                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2050 #endif
2051         code = emit_call_body (cfg, code, patch_type, data);
2052 #ifdef PLATFORM_WIN32
2053         if (win64_adjust_stack)
2054                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2055 #endif
2056
2057         return code;
2058 }
2059
2060 static inline int
2061 store_membase_imm_to_store_membase_reg (int opcode)
2062 {
2063         switch (opcode) {
2064         case OP_STORE_MEMBASE_IMM:
2065                 return OP_STORE_MEMBASE_REG;
2066         case OP_STOREI4_MEMBASE_IMM:
2067                 return OP_STOREI4_MEMBASE_REG;
2068         case OP_STOREI8_MEMBASE_IMM:
2069                 return OP_STOREI8_MEMBASE_REG;
2070         }
2071
2072         return -1;
2073 }
2074
2075 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2076
2077 /*
2078  * mono_arch_peephole_pass_1:
2079  *
2080  *   Perform peephole opts which should/can be performed before local regalloc
2081  */
2082 void
2083 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2084 {
2085         MonoInst *ins, *n;
2086
2087         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2088                 MonoInst *last_ins = ins->prev;
2089
2090                 switch (ins->opcode) {
2091                 case OP_ADD_IMM:
2092                 case OP_IADD_IMM:
2093                 case OP_LADD_IMM:
2094                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2095                                 /*
2096                                  * X86_LEA is like ADD, but doesn't have the
2097                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2098                                  * its operand to 64 bit.
2099                                  */
2100                                 ins->opcode = OP_X86_LEA_MEMBASE;
2101                                 ins->inst_basereg = ins->sreg1;
2102                         }
2103                         break;
2104                 case OP_LXOR:
2105                 case OP_IXOR:
2106                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2107                                 MonoInst *ins2;
2108
2109                                 /*
2110                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2111                                  * the latter has length 2-3 instead of 6 (reverse constant
2112                                  * propagation). These instruction sequences are very common
2113                                  * in the initlocals bblock.
2114                                  */
2115                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2116                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2117                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2118                                                 ins2->sreg1 = ins->dreg;
2119                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2120                                                 /* Continue */
2121                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2122                                                 NULLIFY_INS (ins2);
2123                                                 /* Continue */
2124                                         } else {
2125                                                 break;
2126                                         }
2127                                 }
2128                         }
2129                         break;
2130                 case OP_COMPARE_IMM:
2131                 case OP_LCOMPARE_IMM:
2132                         /* OP_COMPARE_IMM (reg, 0)
2133                          * -->
2134                          * OP_AMD64_TEST_NULL (reg)
2135                          */
2136                         if (!ins->inst_imm)
2137                                 ins->opcode = OP_AMD64_TEST_NULL;
2138                         break;
2139                 case OP_ICOMPARE_IMM:
2140                         if (!ins->inst_imm)
2141                                 ins->opcode = OP_X86_TEST_NULL;
2142                         break;
2143                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2144                         /*
2145                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2146                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2147                          * -->
2148                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2149                          * OP_COMPARE_IMM reg, imm
2150                          *
2151                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2152                          */
2153                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2154                             ins->inst_basereg == last_ins->inst_destbasereg &&
2155                             ins->inst_offset == last_ins->inst_offset) {
2156                                         ins->opcode = OP_ICOMPARE_IMM;
2157                                         ins->sreg1 = last_ins->sreg1;
2158
2159                                         /* check if we can remove cmp reg,0 with test null */
2160                                         if (!ins->inst_imm)
2161                                                 ins->opcode = OP_X86_TEST_NULL;
2162                                 }
2163
2164                         break;
2165                 }
2166
2167                 mono_peephole_ins (bb, ins);
2168         }
2169 }
2170
2171 void
2172 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2173 {
2174         MonoInst *ins, *n;
2175
2176         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2177                 switch (ins->opcode) {
2178                 case OP_ICONST:
2179                 case OP_I8CONST: {
2180                         /* reg = 0 -> XOR (reg, reg) */
2181                         /* XOR sets cflags on x86, so we cant do it always */
2182                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2183                                 ins->opcode = OP_LXOR;
2184                                 ins->sreg1 = ins->dreg;
2185                                 ins->sreg2 = ins->dreg;
2186                                 /* Fall through */
2187                         } else {
2188                                 break;
2189                         }
2190                 }
2191                 case OP_LXOR:
2192                         /*
2193                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2194                          * 0 result into 64 bits.
2195                          */
2196                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2197                                 ins->opcode = OP_IXOR;
2198                         }
2199                         /* Fall through */
2200                 case OP_IXOR:
2201                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2202                                 MonoInst *ins2;
2203
2204                                 /*
2205                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2206                                  * the latter has length 2-3 instead of 6 (reverse constant
2207                                  * propagation). These instruction sequences are very common
2208                                  * in the initlocals bblock.
2209                                  */
2210                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2211                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2212                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2213                                                 ins2->sreg1 = ins->dreg;
2214                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2215                                                 /* Continue */
2216                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2217                                                 NULLIFY_INS (ins2);
2218                                                 /* Continue */
2219                                         } else {
2220                                                 break;
2221                                         }
2222                                 }
2223                         }
2224                         break;
2225                 case OP_IADD_IMM:
2226                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2227                                 ins->opcode = OP_X86_INC_REG;
2228                         break;
2229                 case OP_ISUB_IMM:
2230                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2231                                 ins->opcode = OP_X86_DEC_REG;
2232                         break;
2233                 }
2234
2235                 mono_peephole_ins (bb, ins);
2236         }
2237 }
2238
2239 #define NEW_INS(cfg,ins,dest,op) do {   \
2240                 MONO_INST_NEW ((cfg), (dest), (op)); \
2241         (dest)->cil_code = (ins)->cil_code; \
2242         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2243         } while (0)
2244
2245 /*
2246  * mono_arch_lowering_pass:
2247  *
2248  *  Converts complex opcodes into simpler ones so that each IR instruction
2249  * corresponds to one machine instruction.
2250  */
2251 void
2252 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2253 {
2254         MonoInst *ins, *n, *temp;
2255
2256         if (bb->max_vreg > cfg->rs->next_vreg)
2257                 cfg->rs->next_vreg = bb->max_vreg;
2258
2259         /*
2260          * FIXME: Need to add more instructions, but the current machine
2261          * description can't model some parts of the composite instructions like
2262          * cdq.
2263          */
2264         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2265                 switch (ins->opcode) {
2266                 case OP_DIV_IMM:
2267                 case OP_REM_IMM:
2268                 case OP_IDIV_IMM:
2269                 case OP_IDIV_UN_IMM:
2270                 case OP_IREM_UN_IMM:
2271                         mono_decompose_op_imm (cfg, bb, ins);
2272                         break;
2273                 case OP_IREM_IMM:
2274                         /* Keep the opcode if we can implement it efficiently */
2275                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2276                                 mono_decompose_op_imm (cfg, bb, ins);
2277                         break;
2278                 case OP_COMPARE_IMM:
2279                 case OP_LCOMPARE_IMM:
2280                         if (!amd64_is_imm32 (ins->inst_imm)) {
2281                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2282                                 temp->inst_c0 = ins->inst_imm;
2283                                 if (cfg->globalra)
2284                                         temp->dreg = mono_alloc_ireg (cfg);
2285                                 else
2286                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2287                                 ins->opcode = OP_COMPARE;
2288                                 ins->sreg2 = temp->dreg;
2289                         }
2290                         break;
2291                 case OP_LOAD_MEMBASE:
2292                 case OP_LOADI8_MEMBASE:
2293                         if (!amd64_is_imm32 (ins->inst_offset)) {
2294                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2295                                 temp->inst_c0 = ins->inst_offset;
2296                                 if (cfg->globalra)
2297                                         temp->dreg = mono_alloc_ireg (cfg);
2298                                 else
2299                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2300                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2301                                 ins->inst_indexreg = temp->dreg;
2302                         }
2303                         break;
2304                 case OP_STORE_MEMBASE_IMM:
2305                 case OP_STOREI8_MEMBASE_IMM:
2306                         if (!amd64_is_imm32 (ins->inst_imm)) {
2307                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2308                                 temp->inst_c0 = ins->inst_imm;
2309                                 if (cfg->globalra)
2310                                         temp->dreg = mono_alloc_ireg (cfg);
2311                                 else
2312                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2313                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2314                                 ins->sreg1 = temp->dreg;
2315                         }
2316                         break;
2317                 default:
2318                         break;
2319                 }
2320         }
2321
2322         bb->max_vreg = cfg->rs->next_vreg;
2323 }
2324
2325 static const int
2326 branch_cc_table [] = {
2327         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2328         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2329         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2330 };
2331
2332 /* Maps CMP_... constants to X86_CC_... constants */
2333 static const int
2334 cc_table [] = {
2335         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2336         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2337 };
2338
2339 static const int
2340 cc_signed_table [] = {
2341         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2342         FALSE, FALSE, FALSE, FALSE
2343 };
2344
2345 /*#include "cprop.c"*/
2346
2347 static unsigned char*
2348 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2349 {
2350         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2351
2352         if (size == 1)
2353                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2354         else if (size == 2)
2355                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2356         return code;
2357 }
2358
2359 static unsigned char*
2360 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2361 {
2362         int sreg = tree->sreg1;
2363         int need_touch = FALSE;
2364
2365 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2366         if (!tree->flags & MONO_INST_INIT)
2367                 need_touch = TRUE;
2368 #endif
2369
2370         if (need_touch) {
2371                 guint8* br[5];
2372
2373                 /*
2374                  * Under Windows:
2375                  * If requested stack size is larger than one page,
2376                  * perform stack-touch operation
2377                  */
2378                 /*
2379                  * Generate stack probe code.
2380                  * Under Windows, it is necessary to allocate one page at a time,
2381                  * "touching" stack after each successful sub-allocation. This is
2382                  * because of the way stack growth is implemented - there is a
2383                  * guard page before the lowest stack page that is currently commited.
2384                  * Stack normally grows sequentially so OS traps access to the
2385                  * guard page and commits more pages when needed.
2386                  */
2387                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2388                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2389
2390                 br[2] = code; /* loop */
2391                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2392                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2393                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2394                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2395                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2396                 amd64_patch (br[3], br[2]);
2397                 amd64_test_reg_reg (code, sreg, sreg);
2398                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2399                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2400
2401                 br[1] = code; x86_jump8 (code, 0);
2402
2403                 amd64_patch (br[0], code);
2404                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2405                 amd64_patch (br[1], code);
2406                 amd64_patch (br[4], code);
2407         }
2408         else
2409                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2410
2411         if (tree->flags & MONO_INST_INIT) {
2412                 int offset = 0;
2413                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2414                         amd64_push_reg (code, AMD64_RAX);
2415                         offset += 8;
2416                 }
2417                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2418                         amd64_push_reg (code, AMD64_RCX);
2419                         offset += 8;
2420                 }
2421                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2422                         amd64_push_reg (code, AMD64_RDI);
2423                         offset += 8;
2424                 }
2425
2426                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2427                 if (sreg != AMD64_RCX)
2428                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2429                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2430
2431                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2432                 amd64_cld (code);
2433                 amd64_prefix (code, X86_REP_PREFIX);
2434                 amd64_stosl (code);
2435
2436                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2437                         amd64_pop_reg (code, AMD64_RDI);
2438                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2439                         amd64_pop_reg (code, AMD64_RCX);
2440                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2441                         amd64_pop_reg (code, AMD64_RAX);
2442         }
2443         return code;
2444 }
2445
2446 static guint8*
2447 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2448 {
2449         CallInfo *cinfo;
2450         guint32 quad;
2451
2452         /* Move return value to the target register */
2453         /* FIXME: do this in the local reg allocator */
2454         switch (ins->opcode) {
2455         case OP_CALL:
2456         case OP_CALL_REG:
2457         case OP_CALL_MEMBASE:
2458         case OP_LCALL:
2459         case OP_LCALL_REG:
2460         case OP_LCALL_MEMBASE:
2461                 g_assert (ins->dreg == AMD64_RAX);
2462                 break;
2463         case OP_FCALL:
2464         case OP_FCALL_REG:
2465         case OP_FCALL_MEMBASE:
2466                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2467                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2468                 }
2469                 else {
2470                         if (ins->dreg != AMD64_XMM0)
2471                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2472                 }
2473                 break;
2474         case OP_VCALL:
2475         case OP_VCALL_REG:
2476         case OP_VCALL_MEMBASE:
2477         case OP_VCALL2:
2478         case OP_VCALL2_REG:
2479         case OP_VCALL2_MEMBASE:
2480                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2481                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2482                         MonoInst *loc = cfg->arch.vret_addr_loc;
2483
2484                         /* Load the destination address */
2485                         g_assert (loc->opcode == OP_REGOFFSET);
2486                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2487
2488                         for (quad = 0; quad < 2; quad ++) {
2489                                 switch (cinfo->ret.pair_storage [quad]) {
2490                                 case ArgInIReg:
2491                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2492                                         break;
2493                                 case ArgInFloatSSEReg:
2494                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2495                                         break;
2496                                 case ArgInDoubleSSEReg:
2497                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2498                                         break;
2499                                 case ArgNone:
2500                                         break;
2501                                 default:
2502                                         NOT_IMPLEMENTED;
2503                                 }
2504                         }
2505                 }
2506                 break;
2507         }
2508
2509         return code;
2510 }
2511
2512 /*
2513  * mono_amd64_emit_tls_get:
2514  * @code: buffer to store code to
2515  * @dreg: hard register where to place the result
2516  * @tls_offset: offset info
2517  *
2518  * mono_amd64_emit_tls_get emits in @code the native code that puts in
2519  * the dreg register the item in the thread local storage identified
2520  * by tls_offset.
2521  *
2522  * Returns: a pointer to the end of the stored code
2523  */
2524 guint8*
2525 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
2526 {
2527 #ifdef PLATFORM_WIN32
2528         g_assert (tls_offset < 64);
2529         x86_prefix (code, X86_GS_PREFIX);
2530         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2531 #else
2532         if (optimize_for_xen) {
2533                 x86_prefix (code, X86_FS_PREFIX);
2534                 amd64_mov_reg_mem (code, dreg, 0, 8);
2535                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2536         } else {
2537                 x86_prefix (code, X86_FS_PREFIX);
2538                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2539         }
2540 #endif
2541         return code;
2542 }
2543
2544 #define REAL_PRINT_REG(text,reg) \
2545 mono_assert (reg >= 0); \
2546 amd64_push_reg (code, AMD64_RAX); \
2547 amd64_push_reg (code, AMD64_RDX); \
2548 amd64_push_reg (code, AMD64_RCX); \
2549 amd64_push_reg (code, reg); \
2550 amd64_push_imm (code, reg); \
2551 amd64_push_imm (code, text " %d %p\n"); \
2552 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2553 amd64_call_reg (code, AMD64_RAX); \
2554 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2555 amd64_pop_reg (code, AMD64_RCX); \
2556 amd64_pop_reg (code, AMD64_RDX); \
2557 amd64_pop_reg (code, AMD64_RAX);
2558
2559 /* benchmark and set based on cpu */
2560 #define LOOP_ALIGNMENT 8
2561 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2562
2563 #ifndef DISABLE_JIT
2564
2565 void
2566 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2567 {
2568         MonoInst *ins;
2569         MonoCallInst *call;
2570         guint offset;
2571         guint8 *code = cfg->native_code + cfg->code_len;
2572         MonoInst *last_ins = NULL;
2573         guint last_offset = 0;
2574         int max_len, cpos;
2575
2576         if (cfg->opt & MONO_OPT_LOOP) {
2577                 int pad, align = LOOP_ALIGNMENT;
2578                 /* set alignment depending on cpu */
2579                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2580                         pad = align - pad;
2581                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2582                         amd64_padding (code, pad);
2583                         cfg->code_len += pad;
2584                         bb->native_offset = cfg->code_len;
2585                 }
2586         }
2587
2588         if (cfg->verbose_level > 2)
2589                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2590
2591         cpos = bb->max_offset;
2592
2593         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2594                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2595                 g_assert (!cfg->compile_aot);
2596                 cpos += 6;
2597
2598                 cov->data [bb->dfn].cil_code = bb->cil_code;
2599                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2600                 /* this is not thread save, but good enough */
2601                 amd64_inc_membase (code, AMD64_R11, 0);
2602         }
2603
2604         offset = code - cfg->native_code;
2605
2606         mono_debug_open_block (cfg, bb, offset);
2607
2608     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2609                 x86_breakpoint (code);
2610
2611         MONO_BB_FOR_EACH_INS (bb, ins) {
2612                 offset = code - cfg->native_code;
2613
2614                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2615
2616                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2617                         cfg->code_size *= 2;
2618                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2619                         code = cfg->native_code + offset;
2620                         mono_jit_stats.code_reallocs++;
2621                 }
2622
2623                 if (cfg->debug_info)
2624                         mono_debug_record_line_number (cfg, ins, offset);
2625
2626                 switch (ins->opcode) {
2627                 case OP_BIGMUL:
2628                         amd64_mul_reg (code, ins->sreg2, TRUE);
2629                         break;
2630                 case OP_BIGMUL_UN:
2631                         amd64_mul_reg (code, ins->sreg2, FALSE);
2632                         break;
2633                 case OP_X86_SETEQ_MEMBASE:
2634                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2635                         break;
2636                 case OP_STOREI1_MEMBASE_IMM:
2637                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2638                         break;
2639                 case OP_STOREI2_MEMBASE_IMM:
2640                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2641                         break;
2642                 case OP_STOREI4_MEMBASE_IMM:
2643                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2644                         break;
2645                 case OP_STOREI1_MEMBASE_REG:
2646                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2647                         break;
2648                 case OP_STOREI2_MEMBASE_REG:
2649                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2650                         break;
2651                 case OP_STORE_MEMBASE_REG:
2652                 case OP_STOREI8_MEMBASE_REG:
2653                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2654                         break;
2655                 case OP_STOREI4_MEMBASE_REG:
2656                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2657                         break;
2658                 case OP_STORE_MEMBASE_IMM:
2659                 case OP_STOREI8_MEMBASE_IMM:
2660                         g_assert (amd64_is_imm32 (ins->inst_imm));
2661                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2662                         break;
2663                 case OP_LOAD_MEM:
2664                 case OP_LOADI8_MEM:
2665                         // FIXME: Decompose this earlier
2666                         if (amd64_is_imm32 (ins->inst_imm))
2667                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2668                         else {
2669                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2670                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2671                         }
2672                         break;
2673                 case OP_LOADI4_MEM:
2674                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2675                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2676                         break;
2677                 case OP_LOADU4_MEM:
2678                         // FIXME: Decompose this earlier
2679                         if (amd64_is_imm32 (ins->inst_imm))
2680                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2681                         else {
2682                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2683                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2684                         }
2685                         break;
2686                 case OP_LOADU1_MEM:
2687                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2688                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2689                         break;
2690                 case OP_LOADU2_MEM:
2691                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2692                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2693                         break;
2694                 case OP_LOAD_MEMBASE:
2695                 case OP_LOADI8_MEMBASE:
2696                         g_assert (amd64_is_imm32 (ins->inst_offset));
2697                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2698                         break;
2699                 case OP_LOADI4_MEMBASE:
2700                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2701                         break;
2702                 case OP_LOADU4_MEMBASE:
2703                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2704                         break;
2705                 case OP_LOADU1_MEMBASE:
2706                         /* The cpu zero extends the result into 64 bits */
2707                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
2708                         break;
2709                 case OP_LOADI1_MEMBASE:
2710                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2711                         break;
2712                 case OP_LOADU2_MEMBASE:
2713                         /* The cpu zero extends the result into 64 bits */
2714                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
2715                         break;
2716                 case OP_LOADI2_MEMBASE:
2717                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2718                         break;
2719                 case OP_AMD64_LOADI8_MEMINDEX:
2720                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2721                         break;
2722                 case OP_LCONV_TO_I1:
2723                 case OP_ICONV_TO_I1:
2724                 case OP_SEXT_I1:
2725                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2726                         break;
2727                 case OP_LCONV_TO_I2:
2728                 case OP_ICONV_TO_I2:
2729                 case OP_SEXT_I2:
2730                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2731                         break;
2732                 case OP_LCONV_TO_U1:
2733                 case OP_ICONV_TO_U1:
2734                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2735                         break;
2736                 case OP_LCONV_TO_U2:
2737                 case OP_ICONV_TO_U2:
2738                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2739                         break;
2740                 case OP_ZEXT_I4:
2741                         /* Clean out the upper word */
2742                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2743                         break;
2744                 case OP_SEXT_I4:
2745                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2746                         break;
2747                 case OP_COMPARE:
2748                 case OP_LCOMPARE:
2749                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2750                         break;
2751                 case OP_COMPARE_IMM:
2752                 case OP_LCOMPARE_IMM:
2753                         g_assert (amd64_is_imm32 (ins->inst_imm));
2754                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2755                         break;
2756                 case OP_X86_COMPARE_REG_MEMBASE:
2757                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2758                         break;
2759                 case OP_X86_TEST_NULL:
2760                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2761                         break;
2762                 case OP_AMD64_TEST_NULL:
2763                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2764                         break;
2765
2766                 case OP_X86_ADD_REG_MEMBASE:
2767                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2768                         break;
2769                 case OP_X86_SUB_REG_MEMBASE:
2770                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2771                         break;
2772                 case OP_X86_AND_REG_MEMBASE:
2773                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2774                         break;
2775                 case OP_X86_OR_REG_MEMBASE:
2776                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2777                         break;
2778                 case OP_X86_XOR_REG_MEMBASE:
2779                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2780                         break;
2781
2782                 case OP_X86_ADD_MEMBASE_IMM:
2783                         /* FIXME: Make a 64 version too */
2784                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2785                         break;
2786                 case OP_X86_SUB_MEMBASE_IMM:
2787                         g_assert (amd64_is_imm32 (ins->inst_imm));
2788                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2789                         break;
2790                 case OP_X86_AND_MEMBASE_IMM:
2791                         g_assert (amd64_is_imm32 (ins->inst_imm));
2792                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2793                         break;
2794                 case OP_X86_OR_MEMBASE_IMM:
2795                         g_assert (amd64_is_imm32 (ins->inst_imm));
2796                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2797                         break;
2798                 case OP_X86_XOR_MEMBASE_IMM:
2799                         g_assert (amd64_is_imm32 (ins->inst_imm));
2800                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2801                         break;
2802                 case OP_X86_ADD_MEMBASE_REG:
2803                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2804                         break;
2805                 case OP_X86_SUB_MEMBASE_REG:
2806                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2807                         break;
2808                 case OP_X86_AND_MEMBASE_REG:
2809                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2810                         break;
2811                 case OP_X86_OR_MEMBASE_REG:
2812                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2813                         break;
2814                 case OP_X86_XOR_MEMBASE_REG:
2815                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2816                         break;
2817                 case OP_X86_INC_MEMBASE:
2818                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2819                         break;
2820                 case OP_X86_INC_REG:
2821                         amd64_inc_reg_size (code, ins->dreg, 4);
2822                         break;
2823                 case OP_X86_DEC_MEMBASE:
2824                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2825                         break;
2826                 case OP_X86_DEC_REG:
2827                         amd64_dec_reg_size (code, ins->dreg, 4);
2828                         break;
2829                 case OP_X86_MUL_REG_MEMBASE:
2830                 case OP_X86_MUL_MEMBASE_REG:
2831                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2832                         break;
2833                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2834                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2835                         break;
2836                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2837                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2838                         break;
2839                 case OP_AMD64_COMPARE_MEMBASE_REG:
2840                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2841                         break;
2842                 case OP_AMD64_COMPARE_MEMBASE_IMM:
2843                         g_assert (amd64_is_imm32 (ins->inst_imm));
2844                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2845                         break;
2846                 case OP_X86_COMPARE_MEMBASE8_IMM:
2847                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2848                         break;
2849                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2850                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2851                         break;
2852                 case OP_AMD64_COMPARE_REG_MEMBASE:
2853                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2854                         break;
2855
2856                 case OP_AMD64_ADD_REG_MEMBASE:
2857                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2858                         break;
2859                 case OP_AMD64_SUB_REG_MEMBASE:
2860                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2861                         break;
2862                 case OP_AMD64_AND_REG_MEMBASE:
2863                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2864                         break;
2865                 case OP_AMD64_OR_REG_MEMBASE:
2866                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2867                         break;
2868                 case OP_AMD64_XOR_REG_MEMBASE:
2869                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2870                         break;
2871
2872                 case OP_AMD64_ADD_MEMBASE_REG:
2873                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2874                         break;
2875                 case OP_AMD64_SUB_MEMBASE_REG:
2876                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2877                         break;
2878                 case OP_AMD64_AND_MEMBASE_REG:
2879                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2880                         break;
2881                 case OP_AMD64_OR_MEMBASE_REG:
2882                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2883                         break;
2884                 case OP_AMD64_XOR_MEMBASE_REG:
2885                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2886                         break;
2887
2888                 case OP_AMD64_ADD_MEMBASE_IMM:
2889                         g_assert (amd64_is_imm32 (ins->inst_imm));
2890                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2891                         break;
2892                 case OP_AMD64_SUB_MEMBASE_IMM:
2893                         g_assert (amd64_is_imm32 (ins->inst_imm));
2894                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2895                         break;
2896                 case OP_AMD64_AND_MEMBASE_IMM:
2897                         g_assert (amd64_is_imm32 (ins->inst_imm));
2898                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2899                         break;
2900                 case OP_AMD64_OR_MEMBASE_IMM:
2901                         g_assert (amd64_is_imm32 (ins->inst_imm));
2902                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2903                         break;
2904                 case OP_AMD64_XOR_MEMBASE_IMM:
2905                         g_assert (amd64_is_imm32 (ins->inst_imm));
2906                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2907                         break;
2908
2909                 case OP_BREAK:
2910                         amd64_breakpoint (code);
2911                         break;
2912                 case OP_RELAXED_NOP:
2913                         x86_prefix (code, X86_REP_PREFIX);
2914                         x86_nop (code);
2915                         break;
2916                 case OP_HARD_NOP:
2917                         x86_nop (code);
2918                         break;
2919                 case OP_NOP:
2920                 case OP_DUMMY_USE:
2921                 case OP_DUMMY_STORE:
2922                 case OP_NOT_REACHED:
2923                 case OP_NOT_NULL:
2924                         break;
2925                 case OP_ADDCC:
2926                 case OP_LADD:
2927                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2928                         break;
2929                 case OP_ADC:
2930                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2931                         break;
2932                 case OP_ADD_IMM:
2933                 case OP_LADD_IMM:
2934                         g_assert (amd64_is_imm32 (ins->inst_imm));
2935                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2936                         break;
2937                 case OP_ADC_IMM:
2938                         g_assert (amd64_is_imm32 (ins->inst_imm));
2939                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2940                         break;
2941                 case OP_SUBCC:
2942                 case OP_LSUB:
2943                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2944                         break;
2945                 case OP_SBB:
2946                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2947                         break;
2948                 case OP_SUB_IMM:
2949                 case OP_LSUB_IMM:
2950                         g_assert (amd64_is_imm32 (ins->inst_imm));
2951                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2952                         break;
2953                 case OP_SBB_IMM:
2954                         g_assert (amd64_is_imm32 (ins->inst_imm));
2955                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2956                         break;
2957                 case OP_LAND:
2958                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2959                         break;
2960                 case OP_AND_IMM:
2961                 case OP_LAND_IMM:
2962                         g_assert (amd64_is_imm32 (ins->inst_imm));
2963                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2964                         break;
2965                 case OP_LMUL:
2966                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2967                         break;
2968                 case OP_MUL_IMM:
2969                 case OP_LMUL_IMM:
2970                 case OP_IMUL_IMM: {
2971                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2972
2973                         switch (ins->inst_imm) {
2974                         case 2:
2975                                 /* MOV r1, r2 */
2976                                 /* ADD r1, r1 */
2977                                 if (ins->dreg != ins->sreg1)
2978                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2979                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2980                                 break;
2981                         case 3:
2982                                 /* LEA r1, [r2 + r2*2] */
2983                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2984                                 break;
2985                         case 5:
2986                                 /* LEA r1, [r2 + r2*4] */
2987                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2988                                 break;
2989                         case 6:
2990                                 /* LEA r1, [r2 + r2*2] */
2991                                 /* ADD r1, r1          */
2992                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2993                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2994                                 break;
2995                         case 9:
2996                                 /* LEA r1, [r2 + r2*8] */
2997                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2998                                 break;
2999                         case 10:
3000                                 /* LEA r1, [r2 + r2*4] */
3001                                 /* ADD r1, r1          */
3002                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3003                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3004                                 break;
3005                         case 12:
3006                                 /* LEA r1, [r2 + r2*2] */
3007                                 /* SHL r1, 2           */
3008                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3009                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3010                                 break;
3011                         case 25:
3012                                 /* LEA r1, [r2 + r2*4] */
3013                                 /* LEA r1, [r1 + r1*4] */
3014                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3015                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3016                                 break;
3017                         case 100:
3018                                 /* LEA r1, [r2 + r2*4] */
3019                                 /* SHL r1, 2           */
3020                                 /* LEA r1, [r1 + r1*4] */
3021                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3022                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3023                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3024                                 break;
3025                         default:
3026                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3027                                 break;
3028                         }
3029                         break;
3030                 }
3031                 case OP_LDIV:
3032                 case OP_LREM:
3033                         /* Regalloc magic makes the div/rem cases the same */
3034                         if (ins->sreg2 == AMD64_RDX) {
3035                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3036                                 amd64_cdq (code);
3037                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3038                         } else {
3039                                 amd64_cdq (code);
3040                                 amd64_div_reg (code, ins->sreg2, TRUE);
3041                         }
3042                         break;
3043                 case OP_LDIV_UN:
3044                 case OP_LREM_UN:
3045                         if (ins->sreg2 == AMD64_RDX) {
3046                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3047                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3048                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3049                         } else {
3050                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3051                                 amd64_div_reg (code, ins->sreg2, FALSE);
3052                         }
3053                         break;
3054                 case OP_IDIV:
3055                 case OP_IREM:
3056                         if (ins->sreg2 == AMD64_RDX) {
3057                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3058                                 amd64_cdq_size (code, 4);
3059                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3060                         } else {
3061                                 amd64_cdq_size (code, 4);
3062                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3063                         }
3064                         break;
3065                 case OP_IDIV_UN:
3066                 case OP_IREM_UN:
3067                         if (ins->sreg2 == AMD64_RDX) {
3068                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3069                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3070                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3071                         } else {
3072                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3073                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3074                         }
3075                         break;
3076                 case OP_IREM_IMM: {
3077                         int power = mono_is_power_of_two (ins->inst_imm);
3078
3079                         g_assert (ins->sreg1 == X86_EAX);
3080                         g_assert (ins->dreg == X86_EAX);
3081                         g_assert (power >= 0);
3082
3083                         /* Based on gcc code */
3084
3085                         /* Add compensation for negative dividents */
3086                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3087                         if (power > 1)
3088                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3089                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3090                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3091                         /* Compute remainder */
3092                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3093                         /* Remove compensation */
3094                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3095                         break;
3096                 }
3097                 case OP_LMUL_OVF:
3098                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3099                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3100                         break;
3101                 case OP_LOR:
3102                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3103                         break;
3104                 case OP_OR_IMM:
3105                 case OP_LOR_IMM:
3106                         g_assert (amd64_is_imm32 (ins->inst_imm));
3107                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3108                         break;
3109                 case OP_LXOR:
3110                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3111                         break;
3112                 case OP_XOR_IMM:
3113                 case OP_LXOR_IMM:
3114                         g_assert (amd64_is_imm32 (ins->inst_imm));
3115                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3116                         break;
3117                 case OP_LSHL:
3118                         g_assert (ins->sreg2 == AMD64_RCX);
3119                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3120                         break;
3121                 case OP_LSHR:
3122                         g_assert (ins->sreg2 == AMD64_RCX);
3123                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3124                         break;
3125                 case OP_SHR_IMM:
3126                         g_assert (amd64_is_imm32 (ins->inst_imm));
3127                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3128                         break;
3129                 case OP_LSHR_IMM:
3130                         g_assert (amd64_is_imm32 (ins->inst_imm));
3131                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3132                         break;
3133                 case OP_SHR_UN_IMM:
3134                         g_assert (amd64_is_imm32 (ins->inst_imm));
3135                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3136                         break;
3137                 case OP_LSHR_UN_IMM:
3138                         g_assert (amd64_is_imm32 (ins->inst_imm));
3139                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3140                         break;
3141                 case OP_LSHR_UN:
3142                         g_assert (ins->sreg2 == AMD64_RCX);
3143                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3144                         break;
3145                 case OP_SHL_IMM:
3146                         g_assert (amd64_is_imm32 (ins->inst_imm));
3147                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3148                         break;
3149                 case OP_LSHL_IMM:
3150                         g_assert (amd64_is_imm32 (ins->inst_imm));
3151                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3152                         break;
3153
3154                 case OP_IADDCC:
3155                 case OP_IADD:
3156                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3157                         break;
3158                 case OP_IADC:
3159                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3160                         break;
3161                 case OP_IADD_IMM:
3162                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3163                         break;
3164                 case OP_IADC_IMM:
3165                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3166                         break;
3167                 case OP_ISUBCC:
3168                 case OP_ISUB:
3169                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3170                         break;
3171                 case OP_ISBB:
3172                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3173                         break;
3174                 case OP_ISUB_IMM:
3175                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3176                         break;
3177                 case OP_ISBB_IMM:
3178                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3179                         break;
3180                 case OP_IAND:
3181                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3182                         break;
3183                 case OP_IAND_IMM:
3184                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3185                         break;
3186                 case OP_IOR:
3187                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3188                         break;
3189                 case OP_IOR_IMM:
3190                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3191                         break;
3192                 case OP_IXOR:
3193                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3194                         break;
3195                 case OP_IXOR_IMM:
3196                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3197                         break;
3198                 case OP_INEG:
3199                         amd64_neg_reg_size (code, ins->sreg1, 4);
3200                         break;
3201                 case OP_INOT:
3202                         amd64_not_reg_size (code, ins->sreg1, 4);
3203                         break;
3204                 case OP_ISHL:
3205                         g_assert (ins->sreg2 == AMD64_RCX);
3206                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3207                         break;
3208                 case OP_ISHR:
3209                         g_assert (ins->sreg2 == AMD64_RCX);
3210                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3211                         break;
3212                 case OP_ISHR_IMM:
3213                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3214                         break;
3215                 case OP_ISHR_UN_IMM:
3216                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3217                         break;
3218                 case OP_ISHR_UN:
3219                         g_assert (ins->sreg2 == AMD64_RCX);
3220                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3221                         break;
3222                 case OP_ISHL_IMM:
3223                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3224                         break;
3225                 case OP_IMUL:
3226                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3227                         break;
3228                 case OP_IMUL_OVF:
3229                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3230                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3231                         break;
3232                 case OP_IMUL_OVF_UN:
3233                 case OP_LMUL_OVF_UN: {
3234                         /* the mul operation and the exception check should most likely be split */
3235                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3236                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3237                         /*g_assert (ins->sreg2 == X86_EAX);
3238                         g_assert (ins->dreg == X86_EAX);*/
3239                         if (ins->sreg2 == X86_EAX) {
3240                                 non_eax_reg = ins->sreg1;
3241                         } else if (ins->sreg1 == X86_EAX) {
3242                                 non_eax_reg = ins->sreg2;
3243                         } else {
3244                                 /* no need to save since we're going to store to it anyway */
3245                                 if (ins->dreg != X86_EAX) {
3246                                         saved_eax = TRUE;
3247                                         amd64_push_reg (code, X86_EAX);
3248                                 }
3249                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3250                                 non_eax_reg = ins->sreg2;
3251                         }
3252                         if (ins->dreg == X86_EDX) {
3253                                 if (!saved_eax) {
3254                                         saved_eax = TRUE;
3255                                         amd64_push_reg (code, X86_EAX);
3256                                 }
3257                         } else {
3258                                 saved_edx = TRUE;
3259                                 amd64_push_reg (code, X86_EDX);
3260                         }
3261                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3262                         /* save before the check since pop and mov don't change the flags */
3263                         if (ins->dreg != X86_EAX)
3264                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3265                         if (saved_edx)
3266                                 amd64_pop_reg (code, X86_EDX);
3267                         if (saved_eax)
3268                                 amd64_pop_reg (code, X86_EAX);
3269                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3270                         break;
3271                 }
3272                 case OP_ICOMPARE:
3273                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3274                         break;
3275                 case OP_ICOMPARE_IMM:
3276                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3277                         break;
3278                 case OP_IBEQ:
3279                 case OP_IBLT:
3280                 case OP_IBGT:
3281                 case OP_IBGE:
3282                 case OP_IBLE:
3283                 case OP_LBEQ:
3284                 case OP_LBLT:
3285                 case OP_LBGT:
3286                 case OP_LBGE:
3287                 case OP_LBLE:
3288                 case OP_IBNE_UN:
3289                 case OP_IBLT_UN:
3290                 case OP_IBGT_UN:
3291                 case OP_IBGE_UN:
3292                 case OP_IBLE_UN:
3293                 case OP_LBNE_UN:
3294                 case OP_LBLT_UN:
3295                 case OP_LBGT_UN:
3296                 case OP_LBGE_UN:
3297                 case OP_LBLE_UN:
3298                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3299                         break;
3300
3301                 case OP_CMOV_IEQ:
3302                 case OP_CMOV_IGE:
3303                 case OP_CMOV_IGT:
3304                 case OP_CMOV_ILE:
3305                 case OP_CMOV_ILT:
3306                 case OP_CMOV_INE_UN:
3307                 case OP_CMOV_IGE_UN:
3308                 case OP_CMOV_IGT_UN:
3309                 case OP_CMOV_ILE_UN:
3310                 case OP_CMOV_ILT_UN:
3311                 case OP_CMOV_LEQ:
3312                 case OP_CMOV_LGE:
3313                 case OP_CMOV_LGT:
3314                 case OP_CMOV_LLE:
3315                 case OP_CMOV_LLT:
3316                 case OP_CMOV_LNE_UN:
3317                 case OP_CMOV_LGE_UN:
3318                 case OP_CMOV_LGT_UN:
3319                 case OP_CMOV_LLE_UN:
3320                 case OP_CMOV_LLT_UN:
3321                         g_assert (ins->dreg == ins->sreg1);
3322                         /* This needs to operate on 64 bit values */
3323                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3324                         break;
3325
3326                 case OP_LNOT:
3327                         amd64_not_reg (code, ins->sreg1);
3328                         break;
3329                 case OP_LNEG:
3330                         amd64_neg_reg (code, ins->sreg1);
3331                         break;
3332
3333                 case OP_ICONST:
3334                 case OP_I8CONST:
3335                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3336                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3337                         else
3338                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3339                         break;
3340                 case OP_AOTCONST:
3341                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3342                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3343                         break;
3344                 case OP_JUMP_TABLE:
3345                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3346                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3347                         break;
3348                 case OP_MOVE:
3349                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3350                         break;
3351                 case OP_AMD64_SET_XMMREG_R4: {
3352                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3353                         break;
3354                 }
3355                 case OP_AMD64_SET_XMMREG_R8: {
3356                         if (ins->dreg != ins->sreg1)
3357                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3358                         break;
3359                 }
3360                 case OP_TAILCALL: {
3361                         /*
3362                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3363                          * Keep in sync with the code in emit_epilog.
3364                          */
3365                         int pos = 0, i;
3366
3367                         /* FIXME: no tracing support... */
3368                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3369                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3370
3371                         g_assert (!cfg->method->save_lmf);
3372
3373                         if (cfg->arch.omit_fp) {
3374                                 guint32 save_offset = 0;
3375                                 /* Pop callee-saved registers */
3376                                 for (i = 0; i < AMD64_NREG; ++i)
3377                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3378                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3379                                                 save_offset += 8;
3380                                         }
3381                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3382                         }
3383                         else {
3384                                 for (i = 0; i < AMD64_NREG; ++i)
3385                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3386                                                 pos -= sizeof (gpointer);
3387
3388                                 if (pos)
3389                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3390
3391                                 /* Pop registers in reverse order */
3392                                 for (i = AMD64_NREG - 1; i > 0; --i)
3393                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3394                                                 amd64_pop_reg (code, i);
3395                                         }
3396
3397                                 amd64_leave (code);
3398                         }
3399
3400                         offset = code - cfg->native_code;
3401                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3402                         if (cfg->compile_aot)
3403                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3404                         else
3405                                 amd64_set_reg_template (code, AMD64_R11);
3406                         amd64_jump_reg (code, AMD64_R11);
3407                         break;
3408                 }
3409                 case OP_CHECK_THIS:
3410                         /* ensure ins->sreg1 is not NULL */
3411                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3412                         break;
3413                 case OP_ARGLIST: {
3414                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3415                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3416                         break;
3417                 }
3418                 case OP_CALL:
3419                 case OP_FCALL:
3420                 case OP_LCALL:
3421                 case OP_VCALL:
3422                 case OP_VCALL2:
3423                 case OP_VOIDCALL:
3424                         call = (MonoCallInst*)ins;
3425                         /*
3426                          * The AMD64 ABI forces callers to know about varargs.
3427                          */
3428                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3429                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3430                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3431                                 /*
3432                                  * Since the unmanaged calling convention doesn't contain a
3433                                  * 'vararg' entry, we have to treat every pinvoke call as a
3434                                  * potential vararg call.
3435                                  */
3436                                 guint32 nregs, i;
3437                                 nregs = 0;
3438                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3439                                         if (call->used_fregs & (1 << i))
3440                                                 nregs ++;
3441                                 if (!nregs)
3442                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3443                                 else
3444                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3445                         }
3446
3447                         if (ins->flags & MONO_INST_HAS_METHOD)
3448                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3449                         else
3450                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3451                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3452                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3453                         code = emit_move_return_value (cfg, ins, code);
3454                         break;
3455                 case OP_FCALL_REG:
3456                 case OP_LCALL_REG:
3457                 case OP_VCALL_REG:
3458                 case OP_VCALL2_REG:
3459                 case OP_VOIDCALL_REG:
3460                 case OP_CALL_REG:
3461                         call = (MonoCallInst*)ins;
3462
3463                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3464                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3465                                 ins->sreg1 = AMD64_R11;
3466                         }
3467
3468                         /*
3469                          * The AMD64 ABI forces callers to know about varargs.
3470                          */
3471                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3472                                 if (ins->sreg1 == AMD64_RAX) {
3473                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3474                                         ins->sreg1 = AMD64_R11;
3475                                 }
3476                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3477                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3478                                 /*
3479                                  * Since the unmanaged calling convention doesn't contain a
3480                                  * 'vararg' entry, we have to treat every pinvoke call as a
3481                                  * potential vararg call.
3482                                  */
3483                                 guint32 nregs, i;
3484                                 nregs = 0;
3485                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3486                                         if (call->used_fregs & (1 << i))
3487                                                 nregs ++;
3488                                 if (ins->sreg1 == AMD64_RAX) {
3489                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3490                                         ins->sreg1 = AMD64_R11;
3491                                 }
3492                                 if (!nregs)
3493                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3494                                 else
3495                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3496                         }
3497
3498                         amd64_call_reg (code, ins->sreg1);
3499                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3500                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3501                         code = emit_move_return_value (cfg, ins, code);
3502                         break;
3503                 case OP_FCALL_MEMBASE:
3504                 case OP_LCALL_MEMBASE:
3505                 case OP_VCALL_MEMBASE:
3506                 case OP_VCALL2_MEMBASE:
3507                 case OP_VOIDCALL_MEMBASE:
3508                 case OP_CALL_MEMBASE:
3509                         call = (MonoCallInst*)ins;
3510
3511                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3512                                 /*
3513                                  * Can't use R11 because it is clobbered by the trampoline
3514                                  * code, and the reg value is needed by get_vcall_slot_addr.
3515                                  */
3516                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3517                                 ins->sreg1 = AMD64_RAX;
3518                         }
3519
3520                         if (call->method && ins->inst_offset < 0) {
3521                                 gssize val;
3522
3523                                 /*
3524                                  * This is a possible IMT call so save the IMT method in the proper
3525                                  * register. We don't use the generic code in method-to-ir.c, because
3526                                  * we need to disassemble this in get_vcall_slot_addr (), so we have to
3527                                  * maintain control over the layout of the code.
3528                                  * Also put the base reg in %rax to simplify find_imt_method ().
3529                                  */
3530                                 if (ins->sreg1 != AMD64_RAX) {
3531                                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3532                                         ins->sreg1 = AMD64_RAX;
3533                                 }
3534                                 val = (gssize)(gpointer)call->method;
3535
3536                                 // FIXME: Generics sharing
3537 #if 0
3538                                 if ((((guint64)val) >> 32) == 0)
3539                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3540                                 else
3541                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3542 #endif
3543                         }
3544
3545                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3546                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3547                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3548                         code = emit_move_return_value (cfg, ins, code);
3549                         break;
3550                 case OP_AMD64_SAVE_SP_TO_LMF:
3551                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3552                         break;
3553                 case OP_X86_PUSH:
3554                         amd64_push_reg (code, ins->sreg1);
3555                         break;
3556                 case OP_X86_PUSH_IMM:
3557                         g_assert (amd64_is_imm32 (ins->inst_imm));
3558                         amd64_push_imm (code, ins->inst_imm);
3559                         break;
3560                 case OP_X86_PUSH_MEMBASE:
3561                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3562                         break;
3563                 case OP_X86_PUSH_OBJ: {
3564                         int size = ALIGN_TO (ins->inst_imm, 8);
3565                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3566                         amd64_push_reg (code, AMD64_RDI);
3567                         amd64_push_reg (code, AMD64_RSI);
3568                         amd64_push_reg (code, AMD64_RCX);
3569                         if (ins->inst_offset)
3570                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3571                         else
3572                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3573                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
3574                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
3575                         amd64_cld (code);
3576                         amd64_prefix (code, X86_REP_PREFIX);
3577                         amd64_movsd (code);
3578                         amd64_pop_reg (code, AMD64_RCX);
3579                         amd64_pop_reg (code, AMD64_RSI);
3580                         amd64_pop_reg (code, AMD64_RDI);
3581                         break;
3582                 }
3583                 case OP_X86_LEA:
3584                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3585                         break;
3586                 case OP_X86_LEA_MEMBASE:
3587                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3588                         break;
3589                 case OP_X86_XCHG:
3590                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3591                         break;
3592                 case OP_LOCALLOC:
3593                         /* keep alignment */
3594                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3595                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3596                         code = mono_emit_stack_alloc (code, ins);
3597                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3598                         break;
3599                 case OP_LOCALLOC_IMM: {
3600                         guint32 size = ins->inst_imm;
3601                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3602
3603                         if (ins->flags & MONO_INST_INIT) {
3604                                 if (size < 64) {
3605                                         int i;
3606
3607                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3608                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3609
3610                                         for (i = 0; i < size; i += 8)
3611                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
3612                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3613                                 } else {
3614                                         amd64_mov_reg_imm (code, ins->dreg, size);
3615                                         ins->sreg1 = ins->dreg;
3616
3617                                         code = mono_emit_stack_alloc (code, ins);
3618                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3619                                 }
3620                         } else {
3621                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3622                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3623                         }
3624                         break;
3625                 }
3626                 case OP_THROW: {
3627                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3628                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3629                                              (gpointer)"mono_arch_throw_exception", FALSE);
3630                         break;
3631                 }
3632                 case OP_RETHROW: {
3633                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3634                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3635                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
3636                         break;
3637                 }
3638                 case OP_CALL_HANDLER:
3639                         /* Align stack */
3640                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3641                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3642                         amd64_call_imm (code, 0);
3643                         /* Restore stack alignment */
3644                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3645                         break;
3646                 case OP_START_HANDLER: {
3647                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3648                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3649                         break;
3650                 }
3651                 case OP_ENDFINALLY: {
3652                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3653                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3654                         amd64_ret (code);
3655                         break;
3656                 }
3657                 case OP_ENDFILTER: {
3658                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3659                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3660                         /* The local allocator will put the result into RAX */
3661                         amd64_ret (code);
3662                         break;
3663                 }
3664
3665                 case OP_LABEL:
3666                         ins->inst_c0 = code - cfg->native_code;
3667                         break;
3668                 case OP_BR:
3669                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3670                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3671                         //break;
3672                         if (ins->flags & MONO_INST_BRLABEL) {
3673                                 if (ins->inst_i0->inst_c0) {
3674                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3675                                 } else {
3676                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3677                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3678                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3679                                                 x86_jump8 (code, 0);
3680                                         else
3681                                                 x86_jump32 (code, 0);
3682                                 }
3683                         } else {
3684                                 if (ins->inst_target_bb->native_offset) {
3685                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3686                                 } else {
3687                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3688                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3689                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3690                                                 x86_jump8 (code, 0);
3691                                         else
3692                                                 x86_jump32 (code, 0);
3693                                 }
3694                         }
3695                         break;
3696                 case OP_BR_REG:
3697                         amd64_jump_reg (code, ins->sreg1);
3698                         break;
3699                 case OP_CEQ:
3700                 case OP_LCEQ:
3701                 case OP_ICEQ:
3702                 case OP_CLT:
3703                 case OP_LCLT:
3704                 case OP_ICLT:
3705                 case OP_CGT:
3706                 case OP_ICGT:
3707                 case OP_LCGT:
3708                 case OP_CLT_UN:
3709                 case OP_LCLT_UN:
3710                 case OP_ICLT_UN:
3711                 case OP_CGT_UN:
3712                 case OP_LCGT_UN:
3713                 case OP_ICGT_UN:
3714                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3715                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3716                         break;
3717                 case OP_COND_EXC_EQ:
3718                 case OP_COND_EXC_NE_UN:
3719                 case OP_COND_EXC_LT:
3720                 case OP_COND_EXC_LT_UN:
3721                 case OP_COND_EXC_GT:
3722                 case OP_COND_EXC_GT_UN:
3723                 case OP_COND_EXC_GE:
3724                 case OP_COND_EXC_GE_UN:
3725                 case OP_COND_EXC_LE:
3726                 case OP_COND_EXC_LE_UN:
3727                 case OP_COND_EXC_IEQ:
3728                 case OP_COND_EXC_INE_UN:
3729                 case OP_COND_EXC_ILT:
3730                 case OP_COND_EXC_ILT_UN:
3731                 case OP_COND_EXC_IGT:
3732                 case OP_COND_EXC_IGT_UN:
3733                 case OP_COND_EXC_IGE:
3734                 case OP_COND_EXC_IGE_UN:
3735                 case OP_COND_EXC_ILE:
3736                 case OP_COND_EXC_ILE_UN:
3737                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3738                         break;
3739                 case OP_COND_EXC_OV:
3740                 case OP_COND_EXC_NO:
3741                 case OP_COND_EXC_C:
3742                 case OP_COND_EXC_NC:
3743                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3744                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3745                         break;
3746                 case OP_COND_EXC_IOV:
3747                 case OP_COND_EXC_INO:
3748                 case OP_COND_EXC_IC:
3749                 case OP_COND_EXC_INC:
3750                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3751                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3752                         break;
3753
3754                 /* floating point opcodes */
3755                 case OP_R8CONST: {
3756                         double d = *(double *)ins->inst_p0;
3757
3758                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
3759                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3760                         }
3761                         else {
3762                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3763                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3764                         }
3765                         break;
3766                 }
3767                 case OP_R4CONST: {
3768                         float f = *(float *)ins->inst_p0;
3769
3770                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
3771                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3772                         }
3773                         else {
3774                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3775                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3776                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3777                         }
3778                         break;
3779                 }
3780                 case OP_STORER8_MEMBASE_REG:
3781                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3782                         break;
3783                 case OP_LOADR8_SPILL_MEMBASE:
3784                         g_assert_not_reached ();
3785                         break;
3786                 case OP_LOADR8_MEMBASE:
3787                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3788                         break;
3789                 case OP_STORER4_MEMBASE_REG:
3790                         /* This requires a double->single conversion */
3791                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3792                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3793                         break;
3794                 case OP_LOADR4_MEMBASE:
3795                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3796                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3797                         break;
3798                 case OP_ICONV_TO_R4: /* FIXME: change precision */
3799                 case OP_ICONV_TO_R8:
3800                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3801                         break;
3802                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3803                 case OP_LCONV_TO_R8:
3804                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3805                         break;
3806                 case OP_FCONV_TO_R4:
3807                         /* FIXME: nothing to do ?? */
3808                         break;
3809                 case OP_FCONV_TO_I1:
3810                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3811                         break;
3812                 case OP_FCONV_TO_U1:
3813                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3814                         break;
3815                 case OP_FCONV_TO_I2:
3816                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3817                         break;
3818                 case OP_FCONV_TO_U2:
3819                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3820                         break;
3821                 case OP_FCONV_TO_U4:
3822                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
3823                         break;
3824                 case OP_FCONV_TO_I4:
3825                 case OP_FCONV_TO_I:
3826                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3827                         break;
3828                 case OP_FCONV_TO_I8:
3829                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3830                         break;
3831                 case OP_LCONV_TO_R_UN: {
3832                         guint8 *br [2];
3833
3834                         /* Based on gcc code */
3835                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3836                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
3837
3838                         /* Positive case */
3839                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3840                         br [1] = code; x86_jump8 (code, 0);
3841                         amd64_patch (br [0], code);
3842
3843                         /* Negative case */
3844                         /* Save to the red zone */
3845                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
3846                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
3847                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
3848                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3849                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
3850                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
3851                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
3852                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
3853                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
3854                         /* Restore */
3855                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
3856                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
3857                         amd64_patch (br [1], code);
3858                         break;
3859                 }
3860                 case OP_LCONV_TO_OVF_U4:
3861                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3862                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3863                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3864                         break;
3865                 case OP_LCONV_TO_OVF_I4_UN:
3866                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3867                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3868                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3869                         break;
3870                 case OP_FMOVE:
3871                         if (ins->dreg != ins->sreg1)
3872                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3873                         break;
3874                 case OP_FADD:
3875                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3876                         break;
3877                 case OP_FSUB:
3878                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3879                         break;
3880                 case OP_FMUL:
3881                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3882                         break;
3883                 case OP_FDIV:
3884                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3885                         break;
3886                 case OP_FNEG: {
3887                         static double r8_0 = -0.0;
3888
3889                         g_assert (ins->sreg1 == ins->dreg);
3890
3891                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3892                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3893                         break;
3894                 }
3895                 case OP_SIN:
3896                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3897                         break;
3898                 case OP_COS:
3899                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3900                         break;
3901                 case OP_ABS: {
3902                         static guint64 d = 0x7fffffffffffffffUL;
3903
3904                         g_assert (ins->sreg1 == ins->dreg);
3905
3906                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
3907                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3908                         break;
3909                 }
3910                 case OP_SQRT:
3911                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3912                         break;
3913                 case OP_IMIN:
3914                         g_assert (cfg->opt & MONO_OPT_CMOV);
3915                         g_assert (ins->dreg == ins->sreg1);
3916                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3917                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
3918                         break;
3919                 case OP_IMIN_UN:
3920                         g_assert (cfg->opt & MONO_OPT_CMOV);
3921                         g_assert (ins->dreg == ins->sreg1);
3922                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3923                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
3924                         break;
3925                 case OP_IMAX:
3926                         g_assert (cfg->opt & MONO_OPT_CMOV);
3927                         g_assert (ins->dreg == ins->sreg1);
3928                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3929                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
3930                         break;
3931                 case OP_IMAX_UN:
3932                         g_assert (cfg->opt & MONO_OPT_CMOV);
3933                         g_assert (ins->dreg == ins->sreg1);
3934                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3935                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
3936                         break;
3937                 case OP_LMIN:
3938                         g_assert (cfg->opt & MONO_OPT_CMOV);
3939                         g_assert (ins->dreg == ins->sreg1);
3940                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3941                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3942                         break;
3943                 case OP_LMIN_UN:
3944                         g_assert (cfg->opt & MONO_OPT_CMOV);
3945                         g_assert (ins->dreg == ins->sreg1);
3946                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3947                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3948                         break;
3949                 case OP_LMAX:
3950                         g_assert (cfg->opt & MONO_OPT_CMOV);
3951                         g_assert (ins->dreg == ins->sreg1);
3952                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3953                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3954                         break;
3955                 case OP_LMAX_UN:
3956                         g_assert (cfg->opt & MONO_OPT_CMOV);
3957                         g_assert (ins->dreg == ins->sreg1);
3958                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3959                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3960                         break;
3961                 case OP_X86_FPOP:
3962                         break;
3963                 case OP_FCOMPARE:
3964                         /*
3965                          * The two arguments are swapped because the fbranch instructions
3966                          * depend on this for the non-sse case to work.
3967                          */
3968                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3969                         break;
3970                 case OP_FCEQ: {
3971                         /* zeroing the register at the start results in
3972                          * shorter and faster code (we can also remove the widening op)
3973                          */
3974                         guchar *unordered_check;
3975                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3976                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3977                         unordered_check = code;
3978                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3979                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3980                         amd64_patch (unordered_check, code);
3981                         break;
3982                 }
3983                 case OP_FCLT:
3984                 case OP_FCLT_UN:
3985                         /* zeroing the register at the start results in
3986                          * shorter and faster code (we can also remove the widening op)
3987                          */
3988                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3989                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3990                         if (ins->opcode == OP_FCLT_UN) {
3991                                 guchar *unordered_check = code;
3992                                 guchar *jump_to_end;
3993                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3994                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3995                                 jump_to_end = code;
3996                                 x86_jump8 (code, 0);
3997                                 amd64_patch (unordered_check, code);
3998                                 amd64_inc_reg (code, ins->dreg);
3999                                 amd64_patch (jump_to_end, code);
4000                         } else {
4001                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4002                         }
4003                         break;
4004                 case OP_FCGT:
4005                 case OP_FCGT_UN: {
4006                         /* zeroing the register at the start results in
4007                          * shorter and faster code (we can also remove the widening op)
4008                          */
4009                         guchar *unordered_check;
4010                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4011                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4012                         if (ins->opcode == OP_FCGT) {
4013                                 unordered_check = code;
4014                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4015                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4016                                 amd64_patch (unordered_check, code);
4017                         } else {
4018                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4019                         }
4020                         break;
4021                 }
4022                 case OP_FCLT_MEMBASE:
4023                 case OP_FCGT_MEMBASE:
4024                 case OP_FCLT_UN_MEMBASE:
4025                 case OP_FCGT_UN_MEMBASE:
4026                 case OP_FCEQ_MEMBASE: {
4027                         guchar *unordered_check, *jump_to_end;
4028                         int x86_cond;
4029
4030                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4031                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4032
4033                         switch (ins->opcode) {
4034                         case OP_FCEQ_MEMBASE:
4035                                 x86_cond = X86_CC_EQ;
4036                                 break;
4037                         case OP_FCLT_MEMBASE:
4038                         case OP_FCLT_UN_MEMBASE:
4039                                 x86_cond = X86_CC_LT;
4040                                 break;
4041                         case OP_FCGT_MEMBASE:
4042                         case OP_FCGT_UN_MEMBASE:
4043                                 x86_cond = X86_CC_GT;
4044                                 break;
4045                         default:
4046                                 g_assert_not_reached ();
4047                         }
4048
4049                         unordered_check = code;
4050                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4051                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4052
4053                         switch (ins->opcode) {
4054                         case OP_FCEQ_MEMBASE:
4055                         case OP_FCLT_MEMBASE:
4056                         case OP_FCGT_MEMBASE:
4057                                 amd64_patch (unordered_check, code);
4058                                 break;
4059                         case OP_FCLT_UN_MEMBASE:
4060                         case OP_FCGT_UN_MEMBASE:
4061                                 jump_to_end = code;
4062                                 x86_jump8 (code, 0);
4063                                 amd64_patch (unordered_check, code);
4064                                 amd64_inc_reg (code, ins->dreg);
4065                                 amd64_patch (jump_to_end, code);
4066                                 break;
4067                         default:
4068                                 break;
4069                         }
4070                         break;
4071                 }
4072                 case OP_FBEQ: {
4073                         guchar *jump = code;
4074                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4075                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4076                         amd64_patch (jump, code);
4077                         break;
4078                 }
4079                 case OP_FBNE_UN:
4080                         /* Branch if C013 != 100 */
4081                         /* branch if !ZF or (PF|CF) */
4082                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4083                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4084                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4085                         break;
4086                 case OP_FBLT:
4087                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4088                         break;
4089                 case OP_FBLT_UN:
4090                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4091                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4092                         break;
4093                 case OP_FBGT:
4094                 case OP_FBGT_UN:
4095                         if (ins->opcode == OP_FBGT) {
4096                                 guchar *br1;
4097
4098                                 /* skip branch if C1=1 */
4099                                 br1 = code;
4100                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4101                                 /* branch if (C0 | C3) = 1 */
4102                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4103                                 amd64_patch (br1, code);
4104                                 break;
4105                         } else {
4106                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4107                         }
4108                         break;
4109                 case OP_FBGE: {
4110                         /* Branch if C013 == 100 or 001 */
4111                         guchar *br1;
4112
4113                         /* skip branch if C1=1 */
4114                         br1 = code;
4115                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4116                         /* branch if (C0 | C3) = 1 */
4117                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4118                         amd64_patch (br1, code);
4119                         break;
4120                 }
4121                 case OP_FBGE_UN:
4122                         /* Branch if C013 == 000 */
4123                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4124                         break;
4125                 case OP_FBLE: {
4126                         /* Branch if C013=000 or 100 */
4127                         guchar *br1;
4128
4129                         /* skip branch if C1=1 */
4130                         br1 = code;
4131                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4132                         /* branch if C0=0 */
4133                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4134                         amd64_patch (br1, code);
4135                         break;
4136                 }
4137                 case OP_FBLE_UN:
4138                         /* Branch if C013 != 001 */
4139                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4140                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4141                         break;
4142                 case OP_CKFINITE:
4143                         /* Transfer value to the fp stack */
4144                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4145                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4146                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4147
4148                         amd64_push_reg (code, AMD64_RAX);
4149                         amd64_fxam (code);
4150                         amd64_fnstsw (code);
4151                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4152                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4153                         amd64_pop_reg (code, AMD64_RAX);
4154                         amd64_fstp (code, 0);
4155                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4156                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4157                         break;
4158                 case OP_TLS_GET: {
4159                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4160                         break;
4161                 }
4162                 case OP_MEMORY_BARRIER: {
4163                         /* Not needed on amd64 */
4164                         break;
4165                 }
4166                 case OP_ATOMIC_ADD_I4:
4167                 case OP_ATOMIC_ADD_I8: {
4168                         int dreg = ins->dreg;
4169                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4170
4171                         if (dreg == ins->inst_basereg)
4172                                 dreg = AMD64_R11;
4173
4174                         if (dreg != ins->sreg2)
4175                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4176
4177                         x86_prefix (code, X86_LOCK_PREFIX);
4178                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4179
4180                         if (dreg != ins->dreg)
4181                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4182
4183                         break;
4184                 }
4185                 case OP_ATOMIC_ADD_NEW_I4:
4186                 case OP_ATOMIC_ADD_NEW_I8: {
4187                         int dreg = ins->dreg;
4188                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4189
4190                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4191                                 dreg = AMD64_R11;
4192
4193                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4194                         amd64_prefix (code, X86_LOCK_PREFIX);
4195                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4196                         /* dreg contains the old value, add with sreg2 value */
4197                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4198
4199                         if (ins->dreg != dreg)
4200                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4201
4202                         break;
4203                 }
4204                 case OP_ATOMIC_EXCHANGE_I4:
4205                 case OP_ATOMIC_EXCHANGE_I8:
4206                 case OP_ATOMIC_CAS_IMM_I4: {
4207                         guchar *br[2];
4208                         int sreg2 = ins->sreg2;
4209                         int breg = ins->inst_basereg;
4210                         guint32 size;
4211                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4212
4213                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4214                                 size = 8;
4215                         else
4216                                 size = 4;
4217
4218                         /*
4219                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4220                          * an explanation of how this works.
4221                          */
4222
4223                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4224                          * hack to overcome limits in x86 reg allocator
4225                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4226                          */
4227                         g_assert (ins->dreg == AMD64_RAX);
4228
4229                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4230                                 /* Highly unlikely, but possible */
4231                                 need_push = TRUE;
4232
4233                         /* The pushes invalidate rsp */
4234                         if ((breg == AMD64_RAX) || need_push) {
4235                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4236                                 breg = AMD64_R11;
4237                         }
4238
4239                         /* We need the EAX reg for the comparand */
4240                         if (ins->sreg2 == AMD64_RAX) {
4241                                 if (breg != AMD64_R11) {
4242                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4243                                         sreg2 = AMD64_R11;
4244                                 } else {
4245                                         g_assert (need_push);
4246                                         amd64_push_reg (code, AMD64_RDX);
4247                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4248                                         sreg2 = AMD64_RDX;
4249                                         rdx_pushed = TRUE;
4250                                 }
4251                         }
4252
4253                         if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4254                                 if (ins->backend.data == NULL)
4255                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4256                                 else
4257                                         amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4258
4259                                 amd64_prefix (code, X86_LOCK_PREFIX);
4260                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4261                         } else {
4262                                 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4263
4264                                 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4265                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4266                                 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4267                                 amd64_patch (br [1], br [0]);
4268                         }
4269
4270                         if (rdx_pushed)
4271                                 amd64_pop_reg (code, AMD64_RDX);
4272
4273                         break;
4274                 }
4275                 default:
4276                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4277                         g_assert_not_reached ();
4278                 }
4279
4280                 if ((code - cfg->native_code - offset) > max_len) {
4281                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4282                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4283                         g_assert_not_reached ();
4284                 }
4285
4286                 cpos += max_len;
4287
4288                 last_ins = ins;
4289                 last_offset = offset;
4290         }
4291
4292         cfg->code_len = code - cfg->native_code;
4293 }
4294
4295 #endif /* DISABLE_JIT */
4296
4297 void
4298 mono_arch_register_lowlevel_calls (void)
4299 {
4300         /* The signature doesn't matter */
4301         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4302 }
4303
4304 void
4305 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4306 {
4307         MonoJumpInfo *patch_info;
4308         gboolean compile_aot = !run_cctors;
4309
4310         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4311                 unsigned char *ip = patch_info->ip.i + code;
4312                 unsigned char *target;
4313
4314                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4315
4316                 if (compile_aot) {
4317                         switch (patch_info->type) {
4318                         case MONO_PATCH_INFO_BB:
4319                         case MONO_PATCH_INFO_LABEL:
4320                                 break;
4321                         default:
4322                                 /* No need to patch these */
4323                                 continue;
4324                         }
4325                 }
4326
4327                 switch (patch_info->type) {
4328                 case MONO_PATCH_INFO_NONE:
4329                         continue;
4330                 case MONO_PATCH_INFO_METHOD_REL:
4331                 case MONO_PATCH_INFO_R8:
4332                 case MONO_PATCH_INFO_R4:
4333                         g_assert_not_reached ();
4334                         continue;
4335                 case MONO_PATCH_INFO_BB:
4336                         break;
4337                 default:
4338                         break;
4339                 }
4340
4341                 /*
4342                  * Debug code to help track down problems where the target of a near call is
4343                  * is not valid.
4344                  */
4345                 if (amd64_is_near_call (ip)) {
4346                         gint64 disp = (guint8*)target - (guint8*)ip;
4347
4348                         if (!amd64_is_imm32 (disp)) {
4349                                 printf ("TYPE: %d\n", patch_info->type);
4350                                 switch (patch_info->type) {
4351                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4352                                         printf ("V: %s\n", patch_info->data.name);
4353                                         break;
4354                                 case MONO_PATCH_INFO_METHOD_JUMP:
4355                                 case MONO_PATCH_INFO_METHOD:
4356                                         printf ("V: %s\n", patch_info->data.method->name);
4357                                         break;
4358                                 default:
4359                                         break;
4360                                 }
4361                         }
4362                 }
4363
4364                 amd64_patch (ip, (gpointer)target);
4365         }
4366 }
4367
4368 static int
4369 get_max_epilog_size (MonoCompile *cfg)
4370 {
4371         int max_epilog_size = 16;
4372
4373         if (cfg->method->save_lmf)
4374                 max_epilog_size += 256;
4375
4376         if (mono_jit_trace_calls != NULL)
4377                 max_epilog_size += 50;
4378
4379         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4380                 max_epilog_size += 50;
4381
4382         max_epilog_size += (AMD64_NREG * 2);
4383
4384         return max_epilog_size;
4385 }
4386
4387 /*
4388  * This macro is used for testing whenever the unwinder works correctly at every point
4389  * where an async exception can happen.
4390  */
4391 /* This will generate a SIGSEGV at the given point in the code */
4392 #define async_exc_point(code) do { \
4393     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4394          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4395              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4396          cfg->arch.async_point_count ++; \
4397     } \
4398 } while (0)
4399
4400 guint8 *
4401 mono_arch_emit_prolog (MonoCompile *cfg)
4402 {
4403         MonoMethod *method = cfg->method;
4404         MonoBasicBlock *bb;
4405         MonoMethodSignature *sig;
4406         MonoInst *ins;
4407         int alloc_size, pos, max_offset, i, cfa_offset, quad, max_epilog_size;
4408         guint8 *code;
4409         CallInfo *cinfo;
4410         gint32 lmf_offset = cfg->arch.lmf_offset;
4411         gboolean args_clobbered = FALSE;
4412         gboolean trace = FALSE;
4413
4414         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4415
4416         code = cfg->native_code = g_malloc (cfg->code_size);
4417
4418         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4419                 trace = TRUE;
4420
4421         /* Amount of stack space allocated by register saving code */
4422         pos = 0;
4423
4424         /* Offset between RSP and the CFA */
4425         cfa_offset = 0;
4426
4427         /*
4428          * The prolog consists of the following parts:
4429          * FP present:
4430          * - push rbp, mov rbp, rsp
4431          * - save callee saved regs using pushes
4432          * - allocate frame
4433          * - save rgctx if needed
4434          * - save lmf if needed
4435          * FP not present:
4436          * - allocate frame
4437          * - save rgctx if needed
4438          * - save lmf if needed
4439          * - save callee saved regs using moves
4440          */
4441
4442         // CFA = sp + 8
4443         cfa_offset = 8;
4444         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
4445         // IP saved at CFA - 8
4446         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
4447         async_exc_point (code);
4448
4449         if (!cfg->arch.omit_fp) {
4450                 amd64_push_reg (code, AMD64_RBP);
4451                 cfa_offset += 8;
4452                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4453                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
4454                 async_exc_point (code);
4455 #ifdef PLATFORM_WIN32
4456                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4457 #endif
4458
4459                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4460                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
4461                 async_exc_point (code);
4462 #ifdef PLATFORM_WIN32
4463                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4464 #endif
4465         }
4466
4467         /* Save callee saved registers */
4468         if (!cfg->arch.omit_fp && !method->save_lmf) {
4469                 int offset = cfa_offset;
4470
4471                 for (i = 0; i < AMD64_NREG; ++i)
4472                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4473                                 amd64_push_reg (code, i);
4474                                 pos += sizeof (gpointer);
4475                                 offset += 8;
4476                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
4477                                 async_exc_point (code);
4478                         }
4479         }
4480
4481         if (cfg->arch.omit_fp) {
4482                 /*
4483                  * On enter, the stack is misaligned by the the pushing of the return
4484                  * address. It is either made aligned by the pushing of %rbp, or by
4485                  * this.
4486                  */
4487                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4488                 if ((alloc_size % 16) == 0)
4489                         alloc_size += 8;
4490         } else {
4491                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4492
4493                 alloc_size -= pos;
4494         }
4495
4496         cfg->arch.stack_alloc_size = alloc_size;
4497
4498         /* Allocate stack frame */
4499         if (alloc_size) {
4500                 /* See mono_emit_stack_alloc */
4501 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4502                 guint32 remaining_size = alloc_size;
4503                 while (remaining_size >= 0x1000) {
4504                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4505                         if (cfg->arch.omit_fp) {
4506                                 cfa_offset += 0x1000;
4507                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4508                         }
4509                         async_exc_point (code);
4510 #ifdef PLATFORM_WIN32
4511                         if (cfg->arch.omit_fp)
4512                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4513 #endif
4514
4515                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4516                         remaining_size -= 0x1000;
4517                 }
4518                 if (remaining_size) {
4519                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4520                         if (cfg->arch.omit_fp) {
4521                                 cfa_offset += remaining_size;
4522                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4523                                 async_exc_point (code);
4524                         }
4525 #ifdef PLATFORM_WIN32
4526                         if (cfg->arch.omit_fp)
4527                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4528 #endif
4529                 }
4530 #else
4531                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4532                 if (cfg->arch.omit_fp) {
4533                         cfa_offset += alloc_size;
4534                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4535                         async_exc_point (code);
4536                 }
4537 #endif
4538         }
4539
4540         /* Stack alignment check */
4541 #if 0
4542         {
4543                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4544                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4545                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4546                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4547                 amd64_breakpoint (code);
4548         }
4549 #endif
4550
4551         /* Save LMF */
4552         if (method->save_lmf) {
4553                 /*
4554                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4555                  */
4556                 /* sp is saved right before calls */
4557                 /* Skip method (only needed for trampoline LMF frames) */
4558                 /* Save callee saved regs */
4559                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4560                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4561                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4562                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4563                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4564                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4565         }
4566
4567         /* Save callee saved registers */
4568         if (cfg->arch.omit_fp && !method->save_lmf) {
4569                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4570
4571                 /* Save caller saved registers after sp is adjusted */
4572                 /* The registers are saved at the bottom of the frame */
4573                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4574                 for (i = 0; i < AMD64_NREG; ++i)
4575                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4576                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4577                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
4578                                 save_area_offset += 8;
4579                                 async_exc_point (code);
4580                         }
4581         }
4582
4583         /* store runtime generic context */
4584         if (cfg->rgctx_var) {
4585                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4586                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4587
4588                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4589         }
4590
4591         /* compute max_offset in order to use short forward jumps */
4592         max_offset = 0;
4593         max_epilog_size = get_max_epilog_size (cfg);
4594         if (cfg->opt & MONO_OPT_BRANCH) {
4595                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4596                         MonoInst *ins;
4597                         bb->max_offset = max_offset;
4598
4599                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4600                                 max_offset += 6;
4601                         /* max alignment for loops */
4602                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4603                                 max_offset += LOOP_ALIGNMENT;
4604
4605                         MONO_BB_FOR_EACH_INS (bb, ins) {
4606                                 if (ins->opcode == OP_LABEL)
4607                                         ins->inst_c1 = max_offset;
4608
4609                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4610                         }
4611
4612                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
4613                                 /* The tracing code can be quite large */
4614                                 max_offset += max_epilog_size;
4615                 }
4616         }
4617
4618         sig = mono_method_signature (method);
4619         pos = 0;
4620
4621         cinfo = cfg->arch.cinfo;
4622
4623         if (sig->ret->type != MONO_TYPE_VOID) {
4624                 /* Save volatile arguments to the stack */
4625                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4626                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4627         }
4628
4629         /* Keep this in sync with emit_load_volatile_arguments */
4630         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4631                 ArgInfo *ainfo = cinfo->args + i;
4632                 gint32 stack_offset;
4633                 MonoType *arg_type;
4634
4635                 ins = cfg->args [i];
4636
4637                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4638                         /* Unused arguments */
4639                         continue;
4640
4641                 if (sig->hasthis && (i == 0))
4642                         arg_type = &mono_defaults.object_class->byval_arg;
4643                 else
4644                         arg_type = sig->params [i - sig->hasthis];
4645
4646                 stack_offset = ainfo->offset + ARGS_OFFSET;
4647
4648                 if (cfg->globalra) {
4649                         /* All the other moves are done by the register allocator */
4650                         switch (ainfo->storage) {
4651                         case ArgInFloatSSEReg:
4652                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
4653                                 break;
4654                         case ArgValuetypeInReg:
4655                                 for (quad = 0; quad < 2; quad ++) {
4656                                         switch (ainfo->pair_storage [quad]) {
4657                                         case ArgInIReg:
4658                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4659                                                 break;
4660                                         case ArgInFloatSSEReg:
4661                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4662                                                 break;
4663                                         case ArgInDoubleSSEReg:
4664                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4665                                                 break;
4666                                         case ArgNone:
4667                                                 break;
4668                                         default:
4669                                                 g_assert_not_reached ();
4670                                         }
4671                                 }
4672                                 break;
4673                         default:
4674                                 break;
4675                         }
4676
4677                         continue;
4678                 }
4679
4680                 /* Save volatile arguments to the stack */
4681                 if (ins->opcode != OP_REGVAR) {
4682                         switch (ainfo->storage) {
4683                         case ArgInIReg: {
4684                                 guint32 size = 8;
4685
4686                                 /* FIXME: I1 etc */
4687                                 /*
4688                                 if (stack_offset & 0x1)
4689                                         size = 1;
4690                                 else if (stack_offset & 0x2)
4691                                         size = 2;
4692                                 else if (stack_offset & 0x4)
4693                                         size = 4;
4694                                 else
4695                                         size = 8;
4696                                 */
4697                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
4698                                 break;
4699                         }
4700                         case ArgInFloatSSEReg:
4701                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4702                                 break;
4703                         case ArgInDoubleSSEReg:
4704                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4705                                 break;
4706                         case ArgValuetypeInReg:
4707                                 for (quad = 0; quad < 2; quad ++) {
4708                                         switch (ainfo->pair_storage [quad]) {
4709                                         case ArgInIReg:
4710                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4711                                                 break;
4712                                         case ArgInFloatSSEReg:
4713                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4714                                                 break;
4715                                         case ArgInDoubleSSEReg:
4716                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4717                                                 break;
4718                                         case ArgNone:
4719                                                 break;
4720                                         default:
4721                                                 g_assert_not_reached ();
4722                                         }
4723                                 }
4724                                 break;
4725                         case ArgValuetypeAddrInIReg:
4726                                 if (ainfo->pair_storage [0] == ArgInIReg)
4727                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
4728                                 break;
4729                         default:
4730                                 break;
4731                         }
4732                 } else {
4733                         /* Argument allocated to (non-volatile) register */
4734                         switch (ainfo->storage) {
4735                         case ArgInIReg:
4736                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
4737                                 break;
4738                         case ArgOnStack:
4739                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4740                                 break;
4741                         default:
4742                                 g_assert_not_reached ();
4743                         }
4744                 }
4745         }
4746
4747         /* Might need to attach the thread to the JIT  or change the domain for the callback */
4748         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4749                 guint64 domain = (guint64)cfg->domain;
4750
4751                 args_clobbered = TRUE;
4752
4753                 /*
4754                  * The call might clobber argument registers, but they are already
4755                  * saved to the stack/global regs.
4756                  */
4757                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4758                         guint8 *buf, *no_domain_branch;
4759
4760                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
4761                         if ((domain >> 32) == 0)
4762                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4763                         else
4764                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4765                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
4766                         no_domain_branch = code;
4767                         x86_branch8 (code, X86_CC_NE, 0, 0);
4768                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4769                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4770                         buf = code;
4771                         x86_branch8 (code, X86_CC_NE, 0, 0);
4772                         amd64_patch (no_domain_branch, code);
4773                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4774                                           (gpointer)"mono_jit_thread_attach", TRUE);
4775                         amd64_patch (buf, code);
4776 #ifdef PLATFORM_WIN32
4777                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4778                         /* FIXME: Add a separate key for LMF to avoid this */
4779                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4780 #endif
4781                 } else {
4782                         g_assert (!cfg->compile_aot);
4783                         if ((domain >> 32) == 0)
4784                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4785                         else
4786                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4787                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4788                                           (gpointer)"mono_jit_thread_attach", TRUE);
4789                 }
4790         }
4791
4792         if (method->save_lmf) {
4793                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4794                         /*
4795                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4796                          * through the mono_lmf_addr TLS variable.
4797                          */
4798                         /* %rax = previous_lmf */
4799                         x86_prefix (code, X86_FS_PREFIX);
4800                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4801
4802                         /* Save previous_lmf */
4803                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4804                         /* Set new lmf */
4805                         if (lmf_offset == 0) {
4806                                 x86_prefix (code, X86_FS_PREFIX);
4807                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
4808                         } else {
4809                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4810                                 x86_prefix (code, X86_FS_PREFIX);
4811                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4812                         }
4813                 } else {
4814                         if (lmf_addr_tls_offset != -1) {
4815                                 /* Load lmf quicky using the FS register */
4816                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4817 #ifdef PLATFORM_WIN32
4818                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4819                                 /* FIXME: Add a separate key for LMF to avoid this */
4820                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4821 #endif
4822                         }
4823                         else {
4824                                 /*
4825                                  * The call might clobber argument registers, but they are already
4826                                  * saved to the stack/global regs.
4827                                  */
4828                                 args_clobbered = TRUE;
4829                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4830                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
4831                         }
4832
4833                         /* Save lmf_addr */
4834                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4835                         /* Save previous_lmf */
4836                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4837                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4838                         /* Set new lmf */
4839                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4840                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4841                 }
4842         }
4843
4844         if (trace) {
4845                 args_clobbered = TRUE;
4846                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4847         }
4848
4849         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4850                 args_clobbered = TRUE;
4851
4852         /*
4853          * Optimize the common case of the first bblock making a call with the same
4854          * arguments as the method. This works because the arguments are still in their
4855          * original argument registers.
4856          * FIXME: Generalize this
4857          */
4858         if (!args_clobbered) {
4859                 MonoBasicBlock *first_bb = cfg->bb_entry;
4860                 MonoInst *next;
4861
4862                 next = mono_bb_first_ins (first_bb);
4863                 if (!next && first_bb->next_bb) {
4864                         first_bb = first_bb->next_bb;
4865                         next = mono_bb_first_ins (first_bb);
4866                 }
4867
4868                 if (first_bb->in_count > 1)
4869                         next = NULL;
4870
4871                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
4872                         ArgInfo *ainfo = cinfo->args + i;
4873                         gboolean match = FALSE;
4874
4875                         ins = cfg->args [i];
4876                         if (ins->opcode != OP_REGVAR) {
4877                                 switch (ainfo->storage) {
4878                                 case ArgInIReg: {
4879                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
4880                                                 if (next->dreg == ainfo->reg) {
4881                                                         NULLIFY_INS (next);
4882                                                         match = TRUE;
4883                                                 } else {
4884                                                         next->opcode = OP_MOVE;
4885                                                         next->sreg1 = ainfo->reg;
4886                                                         /* Only continue if the instruction doesn't change argument regs */
4887                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
4888                                                                 match = TRUE;
4889                                                 }
4890                                         }
4891                                         break;
4892                                 }
4893                                 default:
4894                                         break;
4895                                 }
4896                         } else {
4897                                 /* Argument allocated to (non-volatile) register */
4898                                 switch (ainfo->storage) {
4899                                 case ArgInIReg:
4900                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
4901                                                 NULLIFY_INS (next);
4902                                                 match = TRUE;
4903                                         }
4904                                         break;
4905                                 default:
4906                                         break;
4907                                 }
4908                         }
4909
4910                         if (match) {
4911                                 next = next->next;
4912                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
4913                                 if (!next)
4914                                         break;
4915                         }
4916                 }
4917         }
4918
4919         cfg->code_len = code - cfg->native_code;
4920
4921         g_assert (cfg->code_len < cfg->code_size);
4922
4923         return code;
4924 }
4925
4926 void
4927 mono_arch_emit_epilog (MonoCompile *cfg)
4928 {
4929         MonoMethod *method = cfg->method;
4930         int quad, pos, i;
4931         guint8 *code;
4932         int max_epilog_size;
4933         CallInfo *cinfo;
4934         gint32 lmf_offset = cfg->arch.lmf_offset;
4935
4936         max_epilog_size = get_max_epilog_size (cfg);
4937
4938         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4939                 cfg->code_size *= 2;
4940                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4941                 mono_jit_stats.code_reallocs++;
4942         }
4943
4944         code = cfg->native_code + cfg->code_len;
4945
4946         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4947                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4948
4949         /* the code restoring the registers must be kept in sync with OP_JMP */
4950         pos = 0;
4951
4952         if (method->save_lmf) {
4953                 /* check if we need to restore protection of the stack after a stack overflow */
4954                 if (mono_get_jit_tls_offset () != -1) {
4955                         guint8 *patch;
4956                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
4957                         /* we load the value in a separate instruction: this mechanism may be
4958                          * used later as a safer way to do thread interruption
4959                          */
4960                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
4961                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4962                         patch = code;
4963                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
4964                         /* note that the call trampoline will preserve eax/edx */
4965                         x86_call_reg (code, X86_ECX);
4966                         x86_patch (patch, code);
4967                 } else {
4968                         /* FIXME: maybe save the jit tls in the prolog */
4969                 }
4970                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4971                         /*
4972                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4973                          * through the mono_lmf_addr TLS variable.
4974                          */
4975                         /* reg = previous_lmf */
4976                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4977                         x86_prefix (code, X86_FS_PREFIX);
4978                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4979                 } else {
4980                         /* Restore previous lmf */
4981                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4982                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4983                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4984                 }
4985
4986                 /* Restore caller saved regs */
4987                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4988                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
4989                 }
4990                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4991                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4992                 }
4993                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4994                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4995                 }
4996                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4997                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4998                 }
4999                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5000                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5001                 }
5002                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5003                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5004                 }
5005         } else {
5006
5007                 if (cfg->arch.omit_fp) {
5008                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5009
5010                         for (i = 0; i < AMD64_NREG; ++i)
5011                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5012                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5013                                         save_area_offset += 8;
5014                                 }
5015                 }
5016                 else {
5017                         for (i = 0; i < AMD64_NREG; ++i)
5018                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5019                                         pos -= sizeof (gpointer);
5020
5021                         if (pos) {
5022                                 if (pos == - sizeof (gpointer)) {
5023                                         /* Only one register, so avoid lea */
5024                                         for (i = AMD64_NREG - 1; i > 0; --i)
5025                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5026                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5027                                                 }
5028                                 }
5029                                 else {
5030                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5031
5032                                         /* Pop registers in reverse order */
5033                                         for (i = AMD64_NREG - 1; i > 0; --i)
5034                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5035                                                         amd64_pop_reg (code, i);
5036                                                 }
5037                                 }
5038                         }
5039                 }
5040         }
5041
5042         /* Load returned vtypes into registers if needed */
5043         cinfo = cfg->arch.cinfo;
5044         if (cinfo->ret.storage == ArgValuetypeInReg) {
5045                 ArgInfo *ainfo = &cinfo->ret;
5046                 MonoInst *inst = cfg->ret;
5047
5048                 for (quad = 0; quad < 2; quad ++) {
5049                         switch (ainfo->pair_storage [quad]) {
5050                         case ArgInIReg:
5051                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5052                                 break;
5053                         case ArgInFloatSSEReg:
5054                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5055                                 break;
5056                         case ArgInDoubleSSEReg:
5057                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5058                                 break;
5059                         case ArgNone:
5060                                 break;
5061                         default:
5062                                 g_assert_not_reached ();
5063                         }
5064                 }
5065         }
5066
5067         if (cfg->arch.omit_fp) {
5068                 if (cfg->arch.stack_alloc_size)
5069                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5070         } else {
5071                 amd64_leave (code);
5072         }
5073         async_exc_point (code);
5074         amd64_ret (code);
5075
5076         cfg->code_len = code - cfg->native_code;
5077
5078         g_assert (cfg->code_len < cfg->code_size);
5079
5080         if (cfg->arch.omit_fp) {
5081                 /*
5082                  * Encode the stack size into used_int_regs so the exception handler
5083                  * can access it.
5084                  */
5085                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5086                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5087         }
5088 }
5089
5090 void
5091 mono_arch_emit_exceptions (MonoCompile *cfg)
5092 {
5093         MonoJumpInfo *patch_info;
5094         int nthrows, i;
5095         guint8 *code;
5096         MonoClass *exc_classes [16];
5097         guint8 *exc_throw_start [16], *exc_throw_end [16];
5098         guint32 code_size = 0;
5099
5100         /* Compute needed space */
5101         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5102                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5103                         code_size += 40;
5104                 if (patch_info->type == MONO_PATCH_INFO_R8)
5105                         code_size += 8 + 15; /* sizeof (double) + alignment */
5106                 if (patch_info->type == MONO_PATCH_INFO_R4)
5107                         code_size += 4 + 15; /* sizeof (float) + alignment */
5108         }
5109
5110         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5111                 cfg->code_size *= 2;
5112                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5113                 mono_jit_stats.code_reallocs++;
5114         }
5115
5116         code = cfg->native_code + cfg->code_len;
5117
5118         /* add code to raise exceptions */
5119         nthrows = 0;
5120         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5121                 switch (patch_info->type) {
5122                 case MONO_PATCH_INFO_EXC: {
5123                         MonoClass *exc_class;
5124                         guint8 *buf, *buf2;
5125                         guint32 throw_ip;
5126
5127                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5128
5129                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5130                         g_assert (exc_class);
5131                         throw_ip = patch_info->ip.i;
5132
5133                         //x86_breakpoint (code);
5134                         /* Find a throw sequence for the same exception class */
5135                         for (i = 0; i < nthrows; ++i)
5136                                 if (exc_classes [i] == exc_class)
5137                                         break;
5138                         if (i < nthrows) {
5139                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5140                                 x86_jump_code (code, exc_throw_start [i]);
5141                                 patch_info->type = MONO_PATCH_INFO_NONE;
5142                         }
5143                         else {
5144                                 buf = code;
5145                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5146                                 buf2 = code;
5147
5148                                 if (nthrows < 16) {
5149                                         exc_classes [nthrows] = exc_class;
5150                                         exc_throw_start [nthrows] = code;
5151                                 }
5152                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5153
5154                                 patch_info->type = MONO_PATCH_INFO_NONE;
5155
5156                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5157
5158                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5159                                 while (buf < buf2)
5160                                         x86_nop (buf);
5161
5162                                 if (nthrows < 16) {
5163                                         exc_throw_end [nthrows] = code;
5164                                         nthrows ++;
5165                                 }
5166                         }
5167                         break;
5168                 }
5169                 default:
5170                         /* do nothing */
5171                         break;
5172                 }
5173         }
5174
5175         /* Handle relocations with RIP relative addressing */
5176         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5177                 gboolean remove = FALSE;
5178
5179                 switch (patch_info->type) {
5180                 case MONO_PATCH_INFO_R8:
5181                 case MONO_PATCH_INFO_R4: {
5182                         guint8 *pos;
5183
5184                         /* The SSE opcodes require a 16 byte alignment */
5185                         code = (guint8*)ALIGN_TO (code, 16);
5186
5187                         pos = cfg->native_code + patch_info->ip.i;
5188
5189                         if (IS_REX (pos [1]))
5190                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5191                         else
5192                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5193
5194                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5195                                 *(double*)code = *(double*)patch_info->data.target;
5196                                 code += sizeof (double);
5197                         } else {
5198                                 *(float*)code = *(float*)patch_info->data.target;
5199                                 code += sizeof (float);
5200                         }
5201
5202                         remove = TRUE;
5203                         break;
5204                 }
5205                 default:
5206                         break;
5207                 }
5208
5209                 if (remove) {
5210                         if (patch_info == cfg->patch_info)
5211                                 cfg->patch_info = patch_info->next;
5212                         else {
5213                                 MonoJumpInfo *tmp;
5214
5215                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5216                                         ;
5217                                 tmp->next = patch_info->next;
5218                         }
5219                 }
5220         }
5221
5222         cfg->code_len = code - cfg->native_code;
5223
5224         g_assert (cfg->code_len < cfg->code_size);
5225
5226 }
5227
5228 void*
5229 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5230 {
5231         guchar *code = p;
5232         CallInfo *cinfo = NULL;
5233         MonoMethodSignature *sig;
5234         MonoInst *inst;
5235         int i, n, stack_area = 0;
5236
5237         /* Keep this in sync with mono_arch_get_argument_info */
5238
5239         if (enable_arguments) {
5240                 /* Allocate a new area on the stack and save arguments there */
5241                 sig = mono_method_signature (cfg->method);
5242
5243                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5244
5245                 n = sig->param_count + sig->hasthis;
5246
5247                 stack_area = ALIGN_TO (n * 8, 16);
5248
5249                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5250
5251                 for (i = 0; i < n; ++i) {
5252                         inst = cfg->args [i];
5253
5254                         if (inst->opcode == OP_REGVAR)
5255                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5256                         else {
5257                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5258                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5259                         }
5260                 }
5261         }
5262
5263         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5264         amd64_set_reg_template (code, AMD64_ARG_REG1);
5265         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5266         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5267
5268         if (enable_arguments)
5269                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5270
5271         return code;
5272 }
5273
5274 enum {
5275         SAVE_NONE,
5276         SAVE_STRUCT,
5277         SAVE_EAX,
5278         SAVE_EAX_EDX,
5279         SAVE_XMM
5280 };
5281
5282 void*
5283 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5284 {
5285         guchar *code = p;
5286         int save_mode = SAVE_NONE;
5287         MonoMethod *method = cfg->method;
5288         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5289
5290         switch (rtype) {
5291         case MONO_TYPE_VOID:
5292                 /* special case string .ctor icall */
5293                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5294                         save_mode = SAVE_EAX;
5295                 else
5296                         save_mode = SAVE_NONE;
5297                 break;
5298         case MONO_TYPE_I8:
5299         case MONO_TYPE_U8:
5300                 save_mode = SAVE_EAX;
5301                 break;
5302         case MONO_TYPE_R4:
5303         case MONO_TYPE_R8:
5304                 save_mode = SAVE_XMM;
5305                 break;
5306         case MONO_TYPE_GENERICINST:
5307                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5308                         save_mode = SAVE_EAX;
5309                         break;
5310                 }
5311                 /* Fall through */
5312         case MONO_TYPE_VALUETYPE:
5313                 save_mode = SAVE_STRUCT;
5314                 break;
5315         default:
5316                 save_mode = SAVE_EAX;
5317                 break;
5318         }
5319
5320         /* Save the result and copy it into the proper argument register */
5321         switch (save_mode) {
5322         case SAVE_EAX:
5323                 amd64_push_reg (code, AMD64_RAX);
5324                 /* Align stack */
5325                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5326                 if (enable_arguments)
5327                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5328                 break;
5329         case SAVE_STRUCT:
5330                 /* FIXME: */
5331                 if (enable_arguments)
5332                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5333                 break;
5334         case SAVE_XMM:
5335                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5336                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5337                 /* Align stack */
5338                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5339                 /*
5340                  * The result is already in the proper argument register so no copying
5341                  * needed.
5342                  */
5343                 break;
5344         case SAVE_NONE:
5345                 break;
5346         default:
5347                 g_assert_not_reached ();
5348         }
5349
5350         /* Set %al since this is a varargs call */
5351         if (save_mode == SAVE_XMM)
5352                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5353         else
5354                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5355
5356         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5357         amd64_set_reg_template (code, AMD64_ARG_REG1);
5358         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5359
5360         /* Restore result */
5361         switch (save_mode) {
5362         case SAVE_EAX:
5363                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5364                 amd64_pop_reg (code, AMD64_RAX);
5365                 break;
5366         case SAVE_STRUCT:
5367                 /* FIXME: */
5368                 break;
5369         case SAVE_XMM:
5370                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5371                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5372                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5373                 break;
5374         case SAVE_NONE:
5375                 break;
5376         default:
5377                 g_assert_not_reached ();
5378         }
5379
5380         return code;
5381 }
5382
5383 void
5384 mono_arch_flush_icache (guint8 *code, gint size)
5385 {
5386         /* Not needed */
5387 }
5388
5389 void
5390 mono_arch_flush_register_windows (void)
5391 {
5392 }
5393
5394 gboolean
5395 mono_arch_is_inst_imm (gint64 imm)
5396 {
5397         return amd64_is_imm32 (imm);
5398 }
5399
5400 /*
5401  * Determine whenever the trap whose info is in SIGINFO is caused by
5402  * integer overflow.
5403  */
5404 gboolean
5405 mono_arch_is_int_overflow (void *sigctx, void *info)
5406 {
5407         MonoContext ctx;
5408         guint8* rip;
5409         int reg;
5410         gint64 value;
5411
5412         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5413
5414         rip = (guint8*)ctx.rip;
5415
5416         if (IS_REX (rip [0])) {
5417                 reg = amd64_rex_b (rip [0]);
5418                 rip ++;
5419         }
5420         else
5421                 reg = 0;
5422
5423         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5424                 /* idiv REG */
5425                 reg += x86_modrm_rm (rip [1]);
5426
5427                 switch (reg) {
5428                 case AMD64_RAX:
5429                         value = ctx.rax;
5430                         break;
5431                 case AMD64_RBX:
5432                         value = ctx.rbx;
5433                         break;
5434                 case AMD64_RCX:
5435                         value = ctx.rcx;
5436                         break;
5437                 case AMD64_RDX:
5438                         value = ctx.rdx;
5439                         break;
5440                 case AMD64_RBP:
5441                         value = ctx.rbp;
5442                         break;
5443                 case AMD64_RSP:
5444                         value = ctx.rsp;
5445                         break;
5446                 case AMD64_RSI:
5447                         value = ctx.rsi;
5448                         break;
5449                 case AMD64_RDI:
5450                         value = ctx.rdi;
5451                         break;
5452                 case AMD64_R12:
5453                         value = ctx.r12;
5454                         break;
5455                 case AMD64_R13:
5456                         value = ctx.r13;
5457                         break;
5458                 case AMD64_R14:
5459                         value = ctx.r14;
5460                         break;
5461                 case AMD64_R15:
5462                         value = ctx.r15;
5463                         break;
5464                 default:
5465                         g_assert_not_reached ();
5466                         reg = -1;
5467                 }
5468
5469                 if (value == -1)
5470                         return TRUE;
5471         }
5472
5473         return FALSE;
5474 }
5475
5476 guint32
5477 mono_arch_get_patch_offset (guint8 *code)
5478 {
5479         return 3;
5480 }
5481
5482 /**
5483  * mono_breakpoint_clean_code:
5484  *
5485  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5486  * breakpoints in the original code, they are removed in the copy.
5487  *
5488  * Returns TRUE if no sw breakpoint was present.
5489  */
5490 gboolean
5491 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5492 {
5493         int i;
5494         gboolean can_write = TRUE;
5495         /*
5496          * If method_start is non-NULL we need to perform bound checks, since we access memory
5497          * at code - offset we could go before the start of the method and end up in a different
5498          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5499          * instead.
5500          */
5501         if (!method_start || code - offset >= method_start) {
5502                 memcpy (buf, code - offset, size);
5503         } else {
5504                 int diff = code - method_start;
5505                 memset (buf, 0, size);
5506                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5507         }
5508         code -= offset;
5509         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5510                 int idx = mono_breakpoint_info_index [i];
5511                 guint8 *ptr;
5512                 if (idx < 1)
5513                         continue;
5514                 ptr = mono_breakpoint_info [idx].address;
5515                 if (ptr >= code && ptr < code + size) {
5516                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5517                         can_write = FALSE;
5518                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5519                         buf [ptr - code] = saved_byte;
5520                 }
5521         }
5522         return can_write;
5523 }
5524
5525 gpointer
5526 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5527 {
5528         guint8 buf [10];
5529         guint32 reg;
5530         gint32 disp;
5531         guint8 rex = 0;
5532
5533         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5534         code = buf + 9;
5535
5536         *displacement = 0;
5537
5538         /* go to the start of the call instruction
5539          *
5540          * address_byte = (m << 6) | (o << 3) | reg
5541          * call opcode: 0xff address_byte displacement
5542          * 0xff m=1,o=2 imm8
5543          * 0xff m=2,o=2 imm32
5544          */
5545         code -= 7;
5546
5547         /*
5548          * A given byte sequence can match more than case here, so we have to be
5549          * really careful about the ordering of the cases. Longer sequences
5550          * come first.
5551          */
5552 #ifdef MONO_ARCH_HAVE_IMT
5553         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5554                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5555                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
5556                  * ff 50 fc                call   *0xfffffffc(%rax)
5557                  */
5558                 reg = amd64_modrm_rm (code [5]);
5559                 disp = (signed char)code [6];
5560                 /* R10 is clobbered by the IMT thunk code */
5561                 g_assert (reg != AMD64_R10);
5562         }
5563 #else
5564         if (0) {
5565         }
5566 #endif
5567         else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5568                         /*
5569                          * This is a interface call
5570                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
5571                          * ff 10                  callq  *(%rax)
5572                          */
5573                 if (IS_REX (code [4]))
5574                         rex = code [4];
5575                 reg = amd64_modrm_rm (code [6]);
5576                 disp = 0;
5577                 /* R10 is clobbered by the IMT thunk code */
5578                 g_assert (reg != AMD64_R10);
5579         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5580                 /* call OFFSET(%rip) */
5581                 disp = *(guint32*)(code + 3);
5582                 return (gpointer*)(code + disp + 7);
5583         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
5584                 /* call *[r12+disp32] */
5585                 if (IS_REX (code [-1]))
5586                         rex = code [-1];
5587                 reg = AMD64_RSP;
5588                 disp = *(gint32*)(code + 3);
5589         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5590                 /* call *[reg+disp32] */
5591                 if (IS_REX (code [0]))
5592                         rex = code [0];
5593                 reg = amd64_modrm_rm (code [2]);
5594                 disp = *(gint32*)(code + 3);
5595                 /* R10 is clobbered by the IMT thunk code */
5596                 g_assert (reg != AMD64_R10);
5597         } else if (code [2] == 0xe8) {
5598                 /* call <ADDR> */
5599                 return NULL;
5600         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
5601                 /* call *[r12+disp32] */
5602                 if (IS_REX (code [2]))
5603                         rex = code [2];
5604                 reg = AMD64_RSP;
5605                 disp = *(gint8*)(code + 6);
5606         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5607                 /* call *%reg */
5608                 return NULL;
5609         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5610                 /* call *[reg+disp8] */
5611                 if (IS_REX (code [3]))
5612                         rex = code [3];
5613                 reg = amd64_modrm_rm (code [5]);
5614                 disp = *(gint8*)(code + 6);
5615                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5616         }
5617         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5618                         /*
5619                          * This is a interface call: should check the above code can't catch it earlier
5620                          * 8b 40 30   mov    0x30(%eax),%eax
5621                          * ff 10      call   *(%eax)
5622                          */
5623                 if (IS_REX (code [4]))
5624                         rex = code [4];
5625                 reg = amd64_modrm_rm (code [6]);
5626                 disp = 0;
5627         }
5628         else
5629                 g_assert_not_reached ();
5630
5631         reg += amd64_rex_b (rex);
5632
5633         /* R11 is clobbered by the trampoline code */
5634         g_assert (reg != AMD64_R11);
5635
5636         *displacement = disp;
5637         return regs [reg];
5638 }
5639
5640 gpointer*
5641 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5642 {
5643         gpointer vt;
5644         int displacement;
5645         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5646         if (!vt)
5647                 return NULL;
5648         return (gpointer*)((char*)vt + displacement);
5649 }
5650
5651 int
5652 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
5653 {
5654         int this_reg = AMD64_ARG_REG1;
5655
5656         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5657                 CallInfo *cinfo;
5658
5659                 if (!gsctx && code)
5660                         gsctx = mono_get_generic_context_from_code (code);
5661
5662                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5663
5664                 if (cinfo->ret.storage != ArgValuetypeInReg)
5665                         this_reg = AMD64_ARG_REG2;
5666                 g_free (cinfo);
5667         }
5668
5669         return this_reg;
5670 }
5671
5672 gpointer
5673 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
5674 {
5675         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
5676 }
5677
5678 #define MAX_ARCH_DELEGATE_PARAMS 10
5679
5680 gpointer
5681 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5682 {
5683         guint8 *code, *start;
5684         int i;
5685
5686         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5687                 return NULL;
5688
5689         /* FIXME: Support more cases */
5690         if (MONO_TYPE_ISSTRUCT (sig->ret))
5691                 return NULL;
5692
5693         if (has_target) {
5694                 static guint8* cached = NULL;
5695
5696                 if (cached)
5697                         return cached;
5698
5699                 start = code = mono_global_codeman_reserve (64);
5700
5701                 /* Replace the this argument with the target */
5702                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5703                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
5704                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5705
5706                 g_assert ((code - start) < 64);
5707
5708                 mono_debug_add_delegate_trampoline (start, code - start);
5709
5710                 mono_memory_barrier ();
5711
5712                 cached = start;
5713         } else {
5714                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5715                 for (i = 0; i < sig->param_count; ++i)
5716                         if (!mono_is_regsize_var (sig->params [i]))
5717                                 return NULL;
5718                 if (sig->param_count > 4)
5719                         return NULL;
5720
5721                 code = cache [sig->param_count];
5722                 if (code)
5723                         return code;
5724
5725                 start = code = mono_global_codeman_reserve (64);
5726
5727                 if (sig->param_count == 0) {
5728                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5729                 } else {
5730                         /* We have to shift the arguments left */
5731                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5732                         for (i = 0; i < sig->param_count; ++i) {
5733 #ifdef PLATFORM_WIN32
5734                                 if (i < 3)
5735                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5736                                 else
5737                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
5738 #else
5739                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5740 #endif
5741                         }
5742
5743                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5744                 }
5745                 g_assert ((code - start) < 64);
5746
5747                 mono_debug_add_delegate_trampoline (start, code - start);
5748
5749                 mono_memory_barrier ();
5750
5751                 cache [sig->param_count] = start;
5752         }
5753
5754         return start;
5755 }
5756
5757 /*
5758  * Support for fast access to the thread-local lmf structure using the GS
5759  * segment register on NPTL + kernel 2.6.x.
5760  */
5761
5762 static gboolean tls_offset_inited = FALSE;
5763
5764 void
5765 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5766 {
5767         if (!tls_offset_inited) {
5768 #ifdef PLATFORM_WIN32
5769                 /*
5770                  * We need to init this multiple times, since when we are first called, the key might not
5771                  * be initialized yet.
5772                  */
5773                 appdomain_tls_offset = mono_domain_get_tls_key ();
5774                 lmf_tls_offset = mono_get_jit_tls_key ();
5775                 thread_tls_offset = mono_thread_get_tls_key ();
5776                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
5777
5778                 /* Only 64 tls entries can be accessed using inline code */
5779                 if (appdomain_tls_offset >= 64)
5780                         appdomain_tls_offset = -1;
5781                 if (lmf_tls_offset >= 64)
5782                         lmf_tls_offset = -1;
5783                 if (thread_tls_offset >= 64)
5784                         thread_tls_offset = -1;
5785 #else
5786                 tls_offset_inited = TRUE;
5787 #ifdef MONO_XEN_OPT
5788                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5789 #endif
5790                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5791                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5792                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5793                 thread_tls_offset = mono_thread_get_tls_offset ();
5794 #endif
5795         }
5796 }
5797
5798 void
5799 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5800 {
5801 }
5802
5803 #ifdef MONO_ARCH_HAVE_IMT
5804
5805 #define CMP_SIZE (6 + 1)
5806 #define CMP_REG_REG_SIZE (4 + 1)
5807 #define BR_SMALL_SIZE 2
5808 #define BR_LARGE_SIZE 6
5809 #define MOV_REG_IMM_SIZE 10
5810 #define MOV_REG_IMM_32BIT_SIZE 6
5811 #define JUMP_REG_SIZE (2 + 1)
5812
5813 static int
5814 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5815 {
5816         int i, distance = 0;
5817         for (i = start; i < target; ++i)
5818                 distance += imt_entries [i]->chunk_size;
5819         return distance;
5820 }
5821
5822 /*
5823  * LOCKING: called with the domain lock held
5824  */
5825 gpointer
5826 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5827         gpointer fail_tramp)
5828 {
5829         int i;
5830         int size = 0;
5831         guint8 *code, *start;
5832         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
5833
5834         for (i = 0; i < count; ++i) {
5835                 MonoIMTCheckItem *item = imt_entries [i];
5836                 if (item->is_equals) {
5837                         if (item->check_target_idx) {
5838                                 if (!item->compare_done) {
5839                                         if (amd64_is_imm32 (item->key))
5840                                                 item->chunk_size += CMP_SIZE;
5841                                         else
5842                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5843                                 }
5844                                 if (vtable_is_32bit)
5845                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5846                                 else
5847                                         item->chunk_size += MOV_REG_IMM_SIZE;
5848                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
5849                         } else {
5850                                 if (fail_tramp) {
5851                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
5852                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
5853                                 } else {
5854                                         if (vtable_is_32bit)
5855                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5856                                         else
5857                                                 item->chunk_size += MOV_REG_IMM_SIZE;
5858                                         item->chunk_size += JUMP_REG_SIZE;
5859                                         /* with assert below:
5860                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5861                                          */
5862                                 }
5863                         }
5864                 } else {
5865                         if (amd64_is_imm32 (item->key))
5866                                 item->chunk_size += CMP_SIZE;
5867                         else
5868                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5869                         item->chunk_size += BR_LARGE_SIZE;
5870                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5871                 }
5872                 size += item->chunk_size;
5873         }
5874         if (fail_tramp)
5875                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5876         else
5877                 code = mono_code_manager_reserve (domain->code_mp, size);
5878         start = code;
5879         for (i = 0; i < count; ++i) {
5880                 MonoIMTCheckItem *item = imt_entries [i];
5881                 item->code_target = code;
5882                 if (item->is_equals) {
5883                         if (item->check_target_idx) {
5884                                 if (!item->compare_done) {
5885                                         if (amd64_is_imm32 (item->key))
5886                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5887                                         else {
5888                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5889                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5890                                         }
5891                                 }
5892                                 item->jmp_code = code;
5893                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5894                                 /* See the comment below about R10 */
5895                                 if (fail_tramp) {
5896                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5897                                         amd64_jump_reg (code, AMD64_R10);
5898                                 } else {
5899                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5900                                         amd64_jump_membase (code, AMD64_R10, 0);
5901                                 }
5902                         } else {
5903                                 if (fail_tramp) {
5904                                         if (amd64_is_imm32 (item->key))
5905                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5906                                         else {
5907                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5908                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5909                                         }
5910                                         item->jmp_code = code;
5911                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5912                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5913                                         amd64_jump_reg (code, AMD64_R10);
5914                                         amd64_patch (item->jmp_code, code);
5915                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
5916                                         amd64_jump_reg (code, AMD64_R10);
5917                                         item->jmp_code = NULL;
5918
5919                                 } else {
5920                                         /* enable the commented code to assert on wrong method */
5921 #if 0
5922                                         if (amd64_is_imm32 (item->key))
5923                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5924                                         else {
5925                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5926                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5927                                         }
5928                                         item->jmp_code = code;
5929                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5930                                         /* See the comment below about R10 */
5931                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5932                                         amd64_jump_membase (code, AMD64_R10, 0);
5933                                         amd64_patch (item->jmp_code, code);
5934                                         amd64_breakpoint (code);
5935                                         item->jmp_code = NULL;
5936 #else
5937                                         /* We're using R10 here because R11
5938                                            needs to be preserved.  R10 needs
5939                                            to be preserved for calls which
5940                                            require a runtime generic context,
5941                                            but interface calls don't. */
5942                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5943                                         amd64_jump_membase (code, AMD64_R10, 0);
5944 #endif
5945                                 }
5946                         }
5947                 } else {
5948                         if (amd64_is_imm32 (item->key))
5949                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5950                         else {
5951                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5952                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5953                         }
5954                         item->jmp_code = code;
5955                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5956                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5957                         else
5958                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5959                 }
5960                 g_assert (code - item->code_target <= item->chunk_size);
5961         }
5962         /* patch the branches to get to the target items */
5963         for (i = 0; i < count; ++i) {
5964                 MonoIMTCheckItem *item = imt_entries [i];
5965                 if (item->jmp_code) {
5966                         if (item->check_target_idx) {
5967                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5968                         }
5969                 }
5970         }
5971
5972         if (!fail_tramp)
5973                 mono_stats.imt_thunks_size += code - start;
5974         g_assert (code - start <= size);
5975
5976         return start;
5977 }
5978
5979 MonoMethod*
5980 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
5981 {
5982         return regs [MONO_ARCH_IMT_REG];
5983 }
5984
5985 MonoObject*
5986 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
5987 {
5988         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
5989 }
5990
5991 void
5992 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5993 {
5994         /* Done by the implementation of the CALL_MEMBASE opcodes */
5995 }
5996 #endif
5997
5998 MonoVTable*
5999 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6000 {
6001         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6002 }
6003
6004 MonoInst*
6005 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6006 {
6007         MonoInst *ins = NULL;
6008         int opcode = 0;
6009
6010         if (cmethod->klass == mono_defaults.math_class) {
6011                 if (strcmp (cmethod->name, "Sin") == 0) {
6012                         opcode = OP_SIN;
6013                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6014                         opcode = OP_COS;
6015                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6016                         opcode = OP_SQRT;
6017                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6018                         opcode = OP_ABS;
6019                 }
6020
6021                 if (opcode) {
6022                         MONO_INST_NEW (cfg, ins, opcode);
6023                         ins->type = STACK_R8;
6024                         ins->dreg = mono_alloc_freg (cfg);
6025                         ins->sreg1 = args [0]->dreg;
6026                         MONO_ADD_INS (cfg->cbb, ins);
6027                 }
6028
6029                 opcode = 0;
6030                 if (cfg->opt & MONO_OPT_CMOV) {
6031                         if (strcmp (cmethod->name, "Min") == 0) {
6032                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6033                                         opcode = OP_IMIN;
6034                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6035                                         opcode = OP_IMIN_UN;
6036                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6037                                         opcode = OP_LMIN;
6038                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6039                                         opcode = OP_LMIN_UN;
6040                         } else if (strcmp (cmethod->name, "Max") == 0) {
6041                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6042                                         opcode = OP_IMAX;
6043                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6044                                         opcode = OP_IMAX_UN;
6045                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6046                                         opcode = OP_LMAX;
6047                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6048                                         opcode = OP_LMAX_UN;
6049                         }
6050                 }
6051
6052                 if (opcode) {
6053                         MONO_INST_NEW (cfg, ins, opcode);
6054                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6055                         ins->dreg = mono_alloc_ireg (cfg);
6056                         ins->sreg1 = args [0]->dreg;
6057                         ins->sreg2 = args [1]->dreg;
6058                         MONO_ADD_INS (cfg->cbb, ins);
6059                 }
6060
6061 #if 0
6062                 /* OP_FREM is not IEEE compatible */
6063                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6064                         MONO_INST_NEW (cfg, ins, OP_FREM);
6065                         ins->inst_i0 = args [0];
6066                         ins->inst_i1 = args [1];
6067                 }
6068 #endif
6069         }
6070
6071         /*
6072          * Can't implement CompareExchange methods this way since they have
6073          * three arguments.
6074          */
6075
6076         return ins;
6077 }
6078
6079 gboolean
6080 mono_arch_print_tree (MonoInst *tree, int arity)
6081 {
6082         return 0;
6083 }
6084
6085 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6086 {
6087         MonoInst* ins;
6088
6089         if (appdomain_tls_offset == -1)
6090                 return NULL;
6091
6092         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6093         ins->inst_offset = appdomain_tls_offset;
6094         return ins;
6095 }
6096
6097 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6098 {
6099         MonoInst* ins;
6100
6101         if (thread_tls_offset == -1)
6102                 return NULL;
6103
6104         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6105         ins->inst_offset = thread_tls_offset;
6106         return ins;
6107 }
6108
6109 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6110
6111 gpointer
6112 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6113 {
6114         switch (reg) {
6115         case AMD64_RCX: return (gpointer)ctx->rcx;
6116         case AMD64_RDX: return (gpointer)ctx->rdx;
6117         case AMD64_RBX: return (gpointer)ctx->rbx;
6118         case AMD64_RBP: return (gpointer)ctx->rbp;
6119         case AMD64_RSP: return (gpointer)ctx->rsp;
6120         default:
6121                 if (reg < 8)
6122                         return _CTX_REG (ctx, rax, reg);
6123                 else if (reg >= 12)
6124                         return _CTX_REG (ctx, r12, reg - 12);
6125                 else
6126                         g_assert_not_reached ();
6127         }
6128 }