2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/abi-details.h>
24 #include <mono/metadata/appdomain.h>
25 #include <mono/metadata/debug-helpers.h>
26 #include <mono/metadata/threads.h>
27 #include <mono/metadata/profiler-private.h>
28 #include <mono/metadata/mono-debug.h>
29 #include <mono/metadata/gc-internal.h>
30 #include <mono/utils/mono-math.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-tls.h>
34 #include <mono/utils/mono-hwcap-x86.h>
35 #include <mono/utils/mono-threads.h>
39 #include "mini-amd64.h"
40 #include "cpu-amd64.h"
41 #include "debugger-agent.h"
45 static gboolean optimize_for_xen = TRUE;
47 #define optimize_for_xen 0
50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
57 /* Under windows, the calling convention is never stdcall */
58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
63 /* This mutex protects architecture specific caches */
64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
66 static mono_mutex_t mini_arch_mutex;
69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
72 * The code generated for sequence points reads from this location, which is
73 * made read-only when single stepping is enabled.
75 static gpointer ss_trigger_page;
77 /* Enabled breakpoints read from this trigger page */
78 static gpointer bp_trigger_page;
80 /* The size of the breakpoint sequence */
81 static int breakpoint_size;
83 /* The size of the breakpoint instruction causing the actual fault */
84 static int breakpoint_fault_size;
86 /* The size of the single step instruction causing the actual fault */
87 static int single_step_fault_size;
89 /* The single step trampoline */
90 static gpointer ss_trampoline;
92 /* Offset between fp and the first argument in the callee */
93 #define ARGS_OFFSET 16
94 #define GP_SCRATCH_REG AMD64_R11
97 * AMD64 register usage:
98 * - callee saved registers are used for global register allocation
99 * - %r11 is used for materializing 64 bit constants in opcodes
100 * - the rest is used for local allocation
104 * Floating point comparison results:
114 mono_arch_regname (int reg)
117 case AMD64_RAX: return "%rax";
118 case AMD64_RBX: return "%rbx";
119 case AMD64_RCX: return "%rcx";
120 case AMD64_RDX: return "%rdx";
121 case AMD64_RSP: return "%rsp";
122 case AMD64_RBP: return "%rbp";
123 case AMD64_RDI: return "%rdi";
124 case AMD64_RSI: return "%rsi";
125 case AMD64_R8: return "%r8";
126 case AMD64_R9: return "%r9";
127 case AMD64_R10: return "%r10";
128 case AMD64_R11: return "%r11";
129 case AMD64_R12: return "%r12";
130 case AMD64_R13: return "%r13";
131 case AMD64_R14: return "%r14";
132 case AMD64_R15: return "%r15";
137 static const char * packed_xmmregs [] = {
138 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
139 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
142 static const char * single_xmmregs [] = {
143 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
144 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
148 mono_arch_fregname (int reg)
150 if (reg < AMD64_XMM_NREG)
151 return single_xmmregs [reg];
157 mono_arch_xregname (int reg)
159 if (reg < AMD64_XMM_NREG)
160 return packed_xmmregs [reg];
169 return mono_debug_count ();
175 static inline gboolean
176 amd64_is_near_call (guint8 *code)
179 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
182 return code [0] == 0xe8;
185 #ifdef __native_client_codegen__
187 /* Keep track of instruction "depth", that is, the level of sub-instruction */
188 /* for any given instruction. For instance, amd64_call_reg resolves to */
189 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
190 /* We only want to force bundle alignment for the top level instruction, */
191 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
192 static MonoNativeTlsKey nacl_instruction_depth;
194 static MonoNativeTlsKey nacl_rex_tag;
195 static MonoNativeTlsKey nacl_legacy_prefix_tag;
198 amd64_nacl_clear_legacy_prefix_tag ()
200 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
204 amd64_nacl_tag_legacy_prefix (guint8* code)
206 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
207 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
211 amd64_nacl_tag_rex (guint8* code)
213 mono_native_tls_set_value (nacl_rex_tag, code);
217 amd64_nacl_get_legacy_prefix_tag ()
219 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
223 amd64_nacl_get_rex_tag ()
225 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
228 /* Increment the instruction "depth" described above */
230 amd64_nacl_instruction_pre ()
232 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
234 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
237 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
238 /* alignment if depth == 0 (top level instruction) */
239 /* IN: start, end pointers to instruction beginning and end */
240 /* OUT: start, end pointers to beginning and end after possible alignment */
241 /* GLOBALS: nacl_instruction_depth defined above */
243 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
245 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
247 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
249 g_assert ( depth >= 0 );
251 uintptr_t space_in_block;
253 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
254 /* if legacy prefix is present, and if it was emitted before */
255 /* the start of the instruction sequence, adjust the start */
256 if (prefix != NULL && prefix < *start) {
257 g_assert (*start - prefix <= 3);/* only 3 are allowed */
260 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
261 instlen = (uintptr_t)(*end - *start);
262 /* Only check for instructions which are less than */
263 /* kNaClAlignment. The only instructions that should ever */
264 /* be that long are call sequences, which are already */
265 /* padded out to align the return to the next bundle. */
266 if (instlen > space_in_block && instlen < kNaClAlignment) {
267 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
268 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
269 const size_t length = (size_t)((*end)-(*start));
270 g_assert (length < MAX_NACL_INST_LENGTH);
272 memcpy (copy_of_instruction, *start, length);
273 *start = mono_arch_nacl_pad (*start, space_in_block);
274 memcpy (*start, copy_of_instruction, length);
275 *end = *start + length;
277 amd64_nacl_clear_legacy_prefix_tag ();
278 amd64_nacl_tag_rex (NULL);
282 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
283 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
284 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
285 /* make sure the upper 32-bits are cleared, and use that register in the */
286 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
288 /* pointer to current instruction stream (in the */
289 /* middle of an instruction, after opcode is emitted) */
290 /* basereg/offset/dreg */
291 /* operands of normal membase address */
293 /* pointer to the end of the membase/memindex emit */
294 /* GLOBALS: nacl_rex_tag */
295 /* position in instruction stream that rex prefix was emitted */
296 /* nacl_legacy_prefix_tag */
297 /* (possibly NULL) position in instruction of legacy x86 prefix */
299 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
301 gint8 true_basereg = basereg;
303 /* Cache these values, they might change */
304 /* as new instructions are emitted below. */
305 guint8* rex_tag = amd64_nacl_get_rex_tag ();
306 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
308 /* 'basereg' is given masked to 0x7 at this point, so check */
309 /* the rex prefix to see if this is an extended register. */
310 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
314 #define X86_LEA_OPCODE (0x8D)
316 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
317 guint8* old_instruction_start;
319 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
320 /* 32-bits of the old base register (new index register) */
322 guint8* buf_ptr = buf;
325 g_assert (rex_tag != NULL);
327 if (IS_REX(*rex_tag)) {
328 /* The old rex.B should be the new rex.X */
329 if (*rex_tag & AMD64_REX_B) {
330 *rex_tag |= AMD64_REX_X;
332 /* Since our new base is %r15 set rex.B */
333 *rex_tag |= AMD64_REX_B;
335 /* Shift the instruction by one byte */
336 /* so we can insert a rex prefix */
337 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
339 /* New rex prefix only needs rex.B for %r15 base */
340 *rex_tag = AMD64_REX(AMD64_REX_B);
343 if (legacy_prefix_tag) {
344 old_instruction_start = legacy_prefix_tag;
346 old_instruction_start = rex_tag;
349 /* Clears the upper 32-bits of the previous base register */
350 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
351 insert_len = buf_ptr - buf;
353 /* Move the old instruction forward to make */
354 /* room for 'mov' stored in 'buf_ptr' */
355 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
357 memcpy (old_instruction_start, buf, insert_len);
359 /* Sandboxed replacement for the normal membase_emit */
360 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
363 /* Normal default behavior, emit membase memory location */
364 x86_membase_emit_body (*code, dreg, basereg, offset);
369 static inline unsigned char*
370 amd64_skip_nops (unsigned char* code)
375 if ( code[0] == 0x90) {
379 if ( code[0] == 0x66 && code[1] == 0x90) {
383 if (code[0] == 0x0f && code[1] == 0x1f
384 && code[2] == 0x00) {
388 if (code[0] == 0x0f && code[1] == 0x1f
389 && code[2] == 0x40 && code[3] == 0x00) {
393 if (code[0] == 0x0f && code[1] == 0x1f
394 && code[2] == 0x44 && code[3] == 0x00
395 && code[4] == 0x00) {
399 if (code[0] == 0x66 && code[1] == 0x0f
400 && code[2] == 0x1f && code[3] == 0x44
401 && code[4] == 0x00 && code[5] == 0x00) {
405 if (code[0] == 0x0f && code[1] == 0x1f
406 && code[2] == 0x80 && code[3] == 0x00
407 && code[4] == 0x00 && code[5] == 0x00
408 && code[6] == 0x00) {
412 if (code[0] == 0x0f && code[1] == 0x1f
413 && code[2] == 0x84 && code[3] == 0x00
414 && code[4] == 0x00 && code[5] == 0x00
415 && code[6] == 0x00 && code[7] == 0x00) {
424 mono_arch_nacl_skip_nops (guint8* code)
426 return amd64_skip_nops(code);
429 #endif /*__native_client_codegen__*/
432 amd64_patch (unsigned char* code, gpointer target)
436 #ifdef __native_client_codegen__
437 code = amd64_skip_nops (code);
439 #if defined(__native_client_codegen__) && defined(__native_client__)
440 if (nacl_is_code_address (code)) {
441 /* For tail calls, code is patched after being installed */
442 /* but not through the normal "patch callsite" method. */
443 unsigned char buf[kNaClAlignment];
444 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
446 memcpy (buf, aligned_code, kNaClAlignment);
447 /* Patch a temp buffer of bundle size, */
448 /* then install to actual location. */
449 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
450 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
454 target = nacl_modify_patch_target (target);
458 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
463 if ((code [0] & 0xf8) == 0xb8) {
464 /* amd64_set_reg_template */
465 *(guint64*)(code + 1) = (guint64)target;
467 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
468 /* mov 0(%rip), %dreg */
469 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
471 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
472 /* call *<OFFSET>(%rip) */
473 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
475 else if (code [0] == 0xe8) {
477 gint64 disp = (guint8*)target - (guint8*)code;
478 g_assert (amd64_is_imm32 (disp));
479 x86_patch (code, (unsigned char*)target);
482 x86_patch (code, (unsigned char*)target);
486 mono_amd64_patch (unsigned char* code, gpointer target)
488 amd64_patch (code, target);
497 ArgValuetypeAddrInIReg,
498 ArgNone /* only in pair_storage */
506 /* Only if storage == ArgValuetypeInReg */
507 ArgStorage pair_storage [2];
509 /* The size of each pair */
519 gboolean need_stack_align;
520 gboolean vtype_retaddr;
521 /* The index of the vret arg in the argument list */
528 #define DEBUG(a) if (cfg->verbose_level > 1) a
531 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
533 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
535 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
537 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
541 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
543 ainfo->offset = *stack_size;
545 if (*gr >= PARAM_REGS) {
546 ainfo->storage = ArgOnStack;
547 /* Since the same stack slot size is used for all arg */
548 /* types, it needs to be big enough to hold them all */
549 (*stack_size) += sizeof(mgreg_t);
552 ainfo->storage = ArgInIReg;
553 ainfo->reg = param_regs [*gr];
559 #define FLOAT_PARAM_REGS 4
561 #define FLOAT_PARAM_REGS 8
565 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
567 ainfo->offset = *stack_size;
569 if (*gr >= FLOAT_PARAM_REGS) {
570 ainfo->storage = ArgOnStack;
571 /* Since the same stack slot size is used for both float */
572 /* types, it needs to be big enough to hold them both */
573 (*stack_size) += sizeof(mgreg_t);
576 /* A double register */
578 ainfo->storage = ArgInDoubleSSEReg;
580 ainfo->storage = ArgInFloatSSEReg;
586 typedef enum ArgumentClass {
594 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
596 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
599 ptype = mini_type_get_underlying_type (gsctx, type);
600 switch (ptype->type) {
609 case MONO_TYPE_STRING:
610 case MONO_TYPE_OBJECT:
611 case MONO_TYPE_CLASS:
612 case MONO_TYPE_SZARRAY:
614 case MONO_TYPE_FNPTR:
615 case MONO_TYPE_ARRAY:
618 class2 = ARG_CLASS_INTEGER;
623 class2 = ARG_CLASS_INTEGER;
625 class2 = ARG_CLASS_SSE;
629 case MONO_TYPE_TYPEDBYREF:
630 g_assert_not_reached ();
632 case MONO_TYPE_GENERICINST:
633 if (!mono_type_generic_inst_is_valuetype (ptype)) {
634 class2 = ARG_CLASS_INTEGER;
638 case MONO_TYPE_VALUETYPE: {
639 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
642 for (i = 0; i < info->num_fields; ++i) {
644 class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
649 g_assert_not_reached ();
653 if (class1 == class2)
655 else if (class1 == ARG_CLASS_NO_CLASS)
657 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
658 class1 = ARG_CLASS_MEMORY;
659 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
660 class1 = ARG_CLASS_INTEGER;
662 class1 = ARG_CLASS_SSE;
666 #ifdef __native_client_codegen__
668 /* Default alignment for Native Client is 32-byte. */
669 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
671 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
672 /* Check that alignment doesn't cross an alignment boundary. */
674 mono_arch_nacl_pad(guint8 *code, int pad)
676 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
678 if (pad == 0) return code;
679 /* assertion: alignment cannot cross a block boundary */
680 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
681 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
682 while (pad >= kMaxPadding) {
683 amd64_padding (code, kMaxPadding);
686 if (pad != 0) amd64_padding (code, pad);
692 count_fields_nested (MonoClass *klass)
694 MonoMarshalType *info;
697 info = mono_marshal_load_type_info (klass);
700 for (i = 0; i < info->num_fields; ++i) {
701 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
702 count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
710 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
712 MonoMarshalType *info;
715 info = mono_marshal_load_type_info (klass);
717 for (i = 0; i < info->num_fields; ++i) {
718 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
719 index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
721 memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
722 fields [index].offset += offset;
730 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
732 guint32 *gr, guint32 *fr, guint32 *stack_size)
734 guint32 size, quad, nquads, i, nfields;
735 /* Keep track of the size used in each quad so we can */
736 /* use the right size when copying args/return vars. */
737 guint32 quadsize [2] = {8, 8};
738 ArgumentClass args [2];
739 MonoMarshalType *info = NULL;
740 MonoMarshalField *fields = NULL;
742 MonoGenericSharingContext tmp_gsctx;
743 gboolean pass_on_stack = FALSE;
746 * The gsctx currently contains no data, it is only used for checking whenever
747 * open types are allowed, some callers like mono_arch_get_argument_info ()
748 * don't pass it to us, so work around that.
753 klass = mono_class_from_mono_type (type);
754 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
756 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
757 /* We pass and return vtypes of size 8 in a register */
758 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
759 pass_on_stack = TRUE;
763 pass_on_stack = TRUE;
767 /* If this struct can't be split up naturally into 8-byte */
768 /* chunks (registers), pass it on the stack. */
769 if (sig->pinvoke && !pass_on_stack) {
773 info = mono_marshal_load_type_info (klass);
777 * Collect field information recursively to be able to
778 * handle nested structures.
780 nfields = count_fields_nested (klass);
781 fields = g_new0 (MonoMarshalField, nfields);
782 collect_field_info_nested (klass, fields, 0, 0);
784 for (i = 0; i < nfields; ++i) {
785 field_size = mono_marshal_type_size (fields [i].field->type,
787 &align, TRUE, klass->unicode);
788 if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
789 pass_on_stack = TRUE;
796 /* Allways pass in memory */
797 ainfo->offset = *stack_size;
798 *stack_size += ALIGN_TO (size, 8);
799 ainfo->storage = ArgOnStack;
805 /* FIXME: Handle structs smaller than 8 bytes */
806 //if ((size % 8) != 0)
815 int n = mono_class_value_size (klass, NULL);
817 quadsize [0] = n >= 8 ? 8 : n;
818 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
820 /* Always pass in 1 or 2 integer registers */
821 args [0] = ARG_CLASS_INTEGER;
822 args [1] = ARG_CLASS_INTEGER;
823 /* Only the simplest cases are supported */
824 if (is_return && nquads != 1) {
825 args [0] = ARG_CLASS_MEMORY;
826 args [1] = ARG_CLASS_MEMORY;
830 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
831 * The X87 and SSEUP stuff is left out since there are no such types in
838 if (info->native_size > 16) {
839 ainfo->offset = *stack_size;
840 *stack_size += ALIGN_TO (info->native_size, 8);
841 ainfo->storage = ArgOnStack;
847 switch (info->native_size) {
848 case 1: case 2: case 4: case 8:
852 ainfo->storage = ArgOnStack;
853 ainfo->offset = *stack_size;
854 *stack_size += ALIGN_TO (info->native_size, 8);
857 ainfo->storage = ArgValuetypeAddrInIReg;
859 if (*gr < PARAM_REGS) {
860 ainfo->pair_storage [0] = ArgInIReg;
861 ainfo->pair_regs [0] = param_regs [*gr];
865 ainfo->pair_storage [0] = ArgOnStack;
866 ainfo->offset = *stack_size;
876 args [0] = ARG_CLASS_NO_CLASS;
877 args [1] = ARG_CLASS_NO_CLASS;
878 for (quad = 0; quad < nquads; ++quad) {
881 ArgumentClass class1;
884 class1 = ARG_CLASS_MEMORY;
886 class1 = ARG_CLASS_NO_CLASS;
887 for (i = 0; i < nfields; ++i) {
888 size = mono_marshal_type_size (fields [i].field->type,
890 &align, TRUE, klass->unicode);
891 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
892 /* Unaligned field */
896 /* Skip fields in other quad */
897 if ((quad == 0) && (fields [i].offset >= 8))
899 if ((quad == 1) && (fields [i].offset < 8))
902 /* How far into this quad this data extends.*/
903 /* (8 is size of quad) */
904 quadsize [quad] = fields [i].offset + size - (quad * 8);
906 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
908 g_assert (class1 != ARG_CLASS_NO_CLASS);
909 args [quad] = class1;
915 /* Post merger cleanup */
916 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
917 args [0] = args [1] = ARG_CLASS_MEMORY;
919 /* Allocate registers */
924 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
926 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
929 ainfo->storage = ArgValuetypeInReg;
930 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
931 g_assert (quadsize [0] <= 8);
932 g_assert (quadsize [1] <= 8);
933 ainfo->pair_size [0] = quadsize [0];
934 ainfo->pair_size [1] = quadsize [1];
935 ainfo->nregs = nquads;
936 for (quad = 0; quad < nquads; ++quad) {
937 switch (args [quad]) {
938 case ARG_CLASS_INTEGER:
939 if (*gr >= PARAM_REGS)
940 args [quad] = ARG_CLASS_MEMORY;
942 ainfo->pair_storage [quad] = ArgInIReg;
944 ainfo->pair_regs [quad] = return_regs [*gr];
946 ainfo->pair_regs [quad] = param_regs [*gr];
951 if (*fr >= FLOAT_PARAM_REGS)
952 args [quad] = ARG_CLASS_MEMORY;
954 if (quadsize[quad] <= 4)
955 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
956 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
957 ainfo->pair_regs [quad] = *fr;
961 case ARG_CLASS_MEMORY:
964 g_assert_not_reached ();
968 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
969 /* Revert possible register assignments */
973 ainfo->offset = *stack_size;
975 *stack_size += ALIGN_TO (info->native_size, 8);
977 *stack_size += nquads * sizeof(mgreg_t);
978 ainfo->storage = ArgOnStack;
986 * Obtain information about a call according to the calling convention.
987 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
988 * Draft Version 0.23" document for more information.
991 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
993 guint32 i, gr, fr, pstart;
995 int n = sig->hasthis + sig->param_count;
996 guint32 stack_size = 0;
998 gboolean is_pinvoke = sig->pinvoke;
1001 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1003 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1011 /* Reserve space where the callee can save the argument registers */
1012 stack_size = 4 * sizeof (mgreg_t);
1016 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1017 switch (ret_type->type) {
1027 case MONO_TYPE_FNPTR:
1028 case MONO_TYPE_CLASS:
1029 case MONO_TYPE_OBJECT:
1030 case MONO_TYPE_SZARRAY:
1031 case MONO_TYPE_ARRAY:
1032 case MONO_TYPE_STRING:
1033 cinfo->ret.storage = ArgInIReg;
1034 cinfo->ret.reg = AMD64_RAX;
1038 cinfo->ret.storage = ArgInIReg;
1039 cinfo->ret.reg = AMD64_RAX;
1042 cinfo->ret.storage = ArgInFloatSSEReg;
1043 cinfo->ret.reg = AMD64_XMM0;
1046 cinfo->ret.storage = ArgInDoubleSSEReg;
1047 cinfo->ret.reg = AMD64_XMM0;
1049 case MONO_TYPE_GENERICINST:
1050 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1051 cinfo->ret.storage = ArgInIReg;
1052 cinfo->ret.reg = AMD64_RAX;
1056 #if defined( __native_client_codegen__ )
1057 case MONO_TYPE_TYPEDBYREF:
1059 case MONO_TYPE_VALUETYPE: {
1060 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1062 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1063 if (cinfo->ret.storage == ArgOnStack) {
1064 cinfo->vtype_retaddr = TRUE;
1065 /* The caller passes the address where the value is stored */
1069 #if !defined( __native_client_codegen__ )
1070 case MONO_TYPE_TYPEDBYREF:
1071 /* Same as a valuetype with size 24 */
1072 cinfo->vtype_retaddr = TRUE;
1075 case MONO_TYPE_VOID:
1078 g_error ("Can't handle as return value 0x%x", ret_type->type);
1083 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1084 * the first argument, allowing 'this' to be always passed in the first arg reg.
1085 * Also do this if the first argument is a reference type, since virtual calls
1086 * are sometimes made using calli without sig->hasthis set, like in the delegate
1089 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1091 add_general (&gr, &stack_size, cinfo->args + 0);
1093 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1096 add_general (&gr, &stack_size, &cinfo->ret);
1097 cinfo->vret_arg_index = 1;
1101 add_general (&gr, &stack_size, cinfo->args + 0);
1103 if (cinfo->vtype_retaddr)
1104 add_general (&gr, &stack_size, &cinfo->ret);
1107 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1109 fr = FLOAT_PARAM_REGS;
1111 /* Emit the signature cookie just before the implicit arguments */
1112 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1115 for (i = pstart; i < sig->param_count; ++i) {
1116 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1120 /* The float param registers and other param registers must be the same index on Windows x64.*/
1127 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1128 /* We allways pass the sig cookie on the stack for simplicity */
1130 * Prevent implicit arguments + the sig cookie from being passed
1134 fr = FLOAT_PARAM_REGS;
1136 /* Emit the signature cookie just before the implicit arguments */
1137 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1140 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1141 switch (ptype->type) {
1144 add_general (&gr, &stack_size, ainfo);
1148 add_general (&gr, &stack_size, ainfo);
1152 add_general (&gr, &stack_size, ainfo);
1157 case MONO_TYPE_FNPTR:
1158 case MONO_TYPE_CLASS:
1159 case MONO_TYPE_OBJECT:
1160 case MONO_TYPE_STRING:
1161 case MONO_TYPE_SZARRAY:
1162 case MONO_TYPE_ARRAY:
1163 add_general (&gr, &stack_size, ainfo);
1165 case MONO_TYPE_GENERICINST:
1166 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1167 add_general (&gr, &stack_size, ainfo);
1171 case MONO_TYPE_VALUETYPE:
1172 case MONO_TYPE_TYPEDBYREF:
1173 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1178 add_general (&gr, &stack_size, ainfo);
1181 add_float (&fr, &stack_size, ainfo, FALSE);
1184 add_float (&fr, &stack_size, ainfo, TRUE);
1187 g_assert_not_reached ();
1191 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1193 fr = FLOAT_PARAM_REGS;
1195 /* Emit the signature cookie just before the implicit arguments */
1196 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1199 cinfo->stack_usage = stack_size;
1200 cinfo->reg_usage = gr;
1201 cinfo->freg_usage = fr;
1206 * mono_arch_get_argument_info:
1207 * @csig: a method signature
1208 * @param_count: the number of parameters to consider
1209 * @arg_info: an array to store the result infos
1211 * Gathers information on parameters such as size, alignment and
1212 * padding. arg_info should be large enought to hold param_count + 1 entries.
1214 * Returns the size of the argument area on the stack.
1217 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1220 CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1221 guint32 args_size = cinfo->stack_usage;
1223 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1224 if (csig->hasthis) {
1225 arg_info [0].offset = 0;
1228 for (k = 0; k < param_count; k++) {
1229 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1231 arg_info [k + 1].size = 0;
1240 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1244 MonoType *callee_ret;
1246 c1 = get_call_info (NULL, NULL, caller_sig);
1247 c2 = get_call_info (NULL, NULL, callee_sig);
1248 res = c1->stack_usage >= c2->stack_usage;
1249 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1250 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1251 /* An address on the callee's stack is passed as the first argument */
1261 * Initialize the cpu to execute managed code.
1264 mono_arch_cpu_init (void)
1269 /* spec compliance requires running with double precision */
1270 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1271 fpcw &= ~X86_FPCW_PRECC_MASK;
1272 fpcw |= X86_FPCW_PREC_DOUBLE;
1273 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1274 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1276 /* TODO: This is crashing on Win64 right now.
1277 * _control87 (_PC_53, MCW_PC);
1283 * Initialize architecture specific code.
1286 mono_arch_init (void)
1290 mono_mutex_init_recursive (&mini_arch_mutex);
1291 #if defined(__native_client_codegen__)
1292 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1293 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1294 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1295 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1298 #ifdef MONO_ARCH_NOMAP32BIT
1299 flags = MONO_MMAP_READ;
1300 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1301 breakpoint_size = 13;
1302 breakpoint_fault_size = 3;
1304 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1305 /* amd64_mov_reg_mem () */
1306 breakpoint_size = 8;
1307 breakpoint_fault_size = 8;
1310 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1311 single_step_fault_size = 4;
1313 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1314 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1315 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1317 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1318 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1319 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1320 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1324 * Cleanup architecture specific code.
1327 mono_arch_cleanup (void)
1329 mono_mutex_destroy (&mini_arch_mutex);
1330 #if defined(__native_client_codegen__)
1331 mono_native_tls_free (nacl_instruction_depth);
1332 mono_native_tls_free (nacl_rex_tag);
1333 mono_native_tls_free (nacl_legacy_prefix_tag);
1338 * This function returns the optimizations supported on this cpu.
1341 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1347 if (mono_hwcap_x86_has_cmov) {
1348 opts |= MONO_OPT_CMOV;
1350 if (mono_hwcap_x86_has_fcmov)
1351 opts |= MONO_OPT_FCMOV;
1353 *exclude_mask |= MONO_OPT_FCMOV;
1355 *exclude_mask |= MONO_OPT_CMOV;
1362 * This function test for all SSE functions supported.
1364 * Returns a bitmask corresponding to all supported versions.
1368 mono_arch_cpu_enumerate_simd_versions (void)
1370 guint32 sse_opts = 0;
1372 if (mono_hwcap_x86_has_sse1)
1373 sse_opts |= SIMD_VERSION_SSE1;
1375 if (mono_hwcap_x86_has_sse2)
1376 sse_opts |= SIMD_VERSION_SSE2;
1378 if (mono_hwcap_x86_has_sse3)
1379 sse_opts |= SIMD_VERSION_SSE3;
1381 if (mono_hwcap_x86_has_ssse3)
1382 sse_opts |= SIMD_VERSION_SSSE3;
1384 if (mono_hwcap_x86_has_sse41)
1385 sse_opts |= SIMD_VERSION_SSE41;
1387 if (mono_hwcap_x86_has_sse42)
1388 sse_opts |= SIMD_VERSION_SSE42;
1390 if (mono_hwcap_x86_has_sse4a)
1391 sse_opts |= SIMD_VERSION_SSE4a;
1399 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1404 for (i = 0; i < cfg->num_varinfo; i++) {
1405 MonoInst *ins = cfg->varinfo [i];
1406 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1409 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1412 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1413 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1416 if (mono_is_regsize_var (ins->inst_vtype)) {
1417 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1418 g_assert (i == vmv->idx);
1419 vars = g_list_prepend (vars, vmv);
1423 vars = mono_varlist_sort (cfg, vars, 0);
1429 * mono_arch_compute_omit_fp:
1431 * Determine whenever the frame pointer can be eliminated.
1434 mono_arch_compute_omit_fp (MonoCompile *cfg)
1436 MonoMethodSignature *sig;
1437 MonoMethodHeader *header;
1441 if (cfg->arch.omit_fp_computed)
1444 header = cfg->header;
1446 sig = mono_method_signature (cfg->method);
1448 if (!cfg->arch.cinfo)
1449 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1450 cinfo = cfg->arch.cinfo;
1453 * FIXME: Remove some of the restrictions.
1455 cfg->arch.omit_fp = TRUE;
1456 cfg->arch.omit_fp_computed = TRUE;
1458 #ifdef __native_client_codegen__
1459 /* NaCl modules may not change the value of RBP, so it cannot be */
1460 /* used as a normal register, but it can be used as a frame pointer*/
1461 cfg->disable_omit_fp = TRUE;
1462 cfg->arch.omit_fp = FALSE;
1465 if (cfg->disable_omit_fp)
1466 cfg->arch.omit_fp = FALSE;
1468 if (!debug_omit_fp ())
1469 cfg->arch.omit_fp = FALSE;
1471 if (cfg->method->save_lmf)
1472 cfg->arch.omit_fp = FALSE;
1474 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1475 cfg->arch.omit_fp = FALSE;
1476 if (header->num_clauses)
1477 cfg->arch.omit_fp = FALSE;
1478 if (cfg->param_area)
1479 cfg->arch.omit_fp = FALSE;
1480 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1481 cfg->arch.omit_fp = FALSE;
1482 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1483 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1484 cfg->arch.omit_fp = FALSE;
1485 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1486 ArgInfo *ainfo = &cinfo->args [i];
1488 if (ainfo->storage == ArgOnStack) {
1490 * The stack offset can only be determined when the frame
1493 cfg->arch.omit_fp = FALSE;
1498 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1499 MonoInst *ins = cfg->varinfo [i];
1502 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1507 mono_arch_get_global_int_regs (MonoCompile *cfg)
1511 mono_arch_compute_omit_fp (cfg);
1513 if (cfg->arch.omit_fp)
1514 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1516 /* We use the callee saved registers for global allocation */
1517 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1518 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1519 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1520 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1521 #ifndef __native_client_codegen__
1522 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1525 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1526 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1533 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1538 /* All XMM registers */
1539 for (i = 0; i < 16; ++i)
1540 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1546 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1548 static GList *r = NULL;
1553 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1554 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1555 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1556 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1557 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1558 #ifndef __native_client_codegen__
1559 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1562 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1563 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1564 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1565 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1566 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1567 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1568 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1569 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1571 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1578 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1581 static GList *r = NULL;
1586 for (i = 0; i < AMD64_XMM_NREG; ++i)
1587 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1589 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1596 * mono_arch_regalloc_cost:
1598 * Return the cost, in number of memory references, of the action of
1599 * allocating the variable VMV into a register during global register
1603 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1605 MonoInst *ins = cfg->varinfo [vmv->idx];
1607 if (cfg->method->save_lmf)
1608 /* The register is already saved */
1609 /* substract 1 for the invisible store in the prolog */
1610 return (ins->opcode == OP_ARG) ? 0 : 1;
1613 return (ins->opcode == OP_ARG) ? 1 : 2;
1617 * mono_arch_fill_argument_info:
1619 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1623 mono_arch_fill_argument_info (MonoCompile *cfg)
1626 MonoMethodSignature *sig;
1631 sig = mono_method_signature (cfg->method);
1633 cinfo = cfg->arch.cinfo;
1634 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1637 * Contrary to mono_arch_allocate_vars (), the information should describe
1638 * where the arguments are at the beginning of the method, not where they can be
1639 * accessed during the execution of the method. The later makes no sense for the
1640 * global register allocator, since a variable can be in more than one location.
1642 if (sig_ret->type != MONO_TYPE_VOID) {
1643 switch (cinfo->ret.storage) {
1645 case ArgInFloatSSEReg:
1646 case ArgInDoubleSSEReg:
1647 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1648 cfg->vret_addr->opcode = OP_REGVAR;
1649 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1652 cfg->ret->opcode = OP_REGVAR;
1653 cfg->ret->inst_c0 = cinfo->ret.reg;
1656 case ArgValuetypeInReg:
1657 cfg->ret->opcode = OP_REGOFFSET;
1658 cfg->ret->inst_basereg = -1;
1659 cfg->ret->inst_offset = -1;
1662 g_assert_not_reached ();
1666 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1667 ArgInfo *ainfo = &cinfo->args [i];
1669 ins = cfg->args [i];
1671 switch (ainfo->storage) {
1673 case ArgInFloatSSEReg:
1674 case ArgInDoubleSSEReg:
1675 ins->opcode = OP_REGVAR;
1676 ins->inst_c0 = ainfo->reg;
1679 ins->opcode = OP_REGOFFSET;
1680 ins->inst_basereg = -1;
1681 ins->inst_offset = -1;
1683 case ArgValuetypeInReg:
1685 ins->opcode = OP_NOP;
1688 g_assert_not_reached ();
1694 mono_arch_allocate_vars (MonoCompile *cfg)
1697 MonoMethodSignature *sig;
1700 guint32 locals_stack_size, locals_stack_align;
1704 sig = mono_method_signature (cfg->method);
1706 cinfo = cfg->arch.cinfo;
1707 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1709 mono_arch_compute_omit_fp (cfg);
1712 * We use the ABI calling conventions for managed code as well.
1713 * Exception: valuetypes are only sometimes passed or returned in registers.
1717 * The stack looks like this:
1718 * <incoming arguments passed on the stack>
1720 * <lmf/caller saved registers>
1723 * <localloc area> -> grows dynamically
1727 if (cfg->arch.omit_fp) {
1728 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1729 cfg->frame_reg = AMD64_RSP;
1732 /* Locals are allocated backwards from %fp */
1733 cfg->frame_reg = AMD64_RBP;
1737 cfg->arch.saved_iregs = cfg->used_int_regs;
1738 if (cfg->method->save_lmf)
1739 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1740 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1742 if (cfg->arch.omit_fp)
1743 cfg->arch.reg_save_area_offset = offset;
1744 /* Reserve space for callee saved registers */
1745 for (i = 0; i < AMD64_NREG; ++i)
1746 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1747 offset += sizeof(mgreg_t);
1749 if (!cfg->arch.omit_fp)
1750 cfg->arch.reg_save_area_offset = -offset;
1752 if (sig_ret->type != MONO_TYPE_VOID) {
1753 switch (cinfo->ret.storage) {
1755 case ArgInFloatSSEReg:
1756 case ArgInDoubleSSEReg:
1757 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1758 /* The register is volatile */
1759 cfg->vret_addr->opcode = OP_REGOFFSET;
1760 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1761 if (cfg->arch.omit_fp) {
1762 cfg->vret_addr->inst_offset = offset;
1766 cfg->vret_addr->inst_offset = -offset;
1768 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1769 printf ("vret_addr =");
1770 mono_print_ins (cfg->vret_addr);
1774 cfg->ret->opcode = OP_REGVAR;
1775 cfg->ret->inst_c0 = cinfo->ret.reg;
1778 case ArgValuetypeInReg:
1779 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1780 cfg->ret->opcode = OP_REGOFFSET;
1781 cfg->ret->inst_basereg = cfg->frame_reg;
1782 if (cfg->arch.omit_fp) {
1783 cfg->ret->inst_offset = offset;
1784 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1786 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1787 cfg->ret->inst_offset = - offset;
1791 g_assert_not_reached ();
1793 cfg->ret->dreg = cfg->ret->inst_c0;
1796 /* Allocate locals */
1797 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1798 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1799 char *mname = mono_method_full_name (cfg->method, TRUE);
1800 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1801 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1806 if (locals_stack_align) {
1807 offset += (locals_stack_align - 1);
1808 offset &= ~(locals_stack_align - 1);
1810 if (cfg->arch.omit_fp) {
1811 cfg->locals_min_stack_offset = offset;
1812 cfg->locals_max_stack_offset = offset + locals_stack_size;
1814 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1815 cfg->locals_max_stack_offset = - offset;
1818 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1819 if (offsets [i] != -1) {
1820 MonoInst *ins = cfg->varinfo [i];
1821 ins->opcode = OP_REGOFFSET;
1822 ins->inst_basereg = cfg->frame_reg;
1823 if (cfg->arch.omit_fp)
1824 ins->inst_offset = (offset + offsets [i]);
1826 ins->inst_offset = - (offset + offsets [i]);
1827 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1830 offset += locals_stack_size;
1832 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1833 g_assert (!cfg->arch.omit_fp);
1834 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1835 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1838 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1839 ins = cfg->args [i];
1840 if (ins->opcode != OP_REGVAR) {
1841 ArgInfo *ainfo = &cinfo->args [i];
1842 gboolean inreg = TRUE;
1844 /* FIXME: Allocate volatile arguments to registers */
1845 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1849 * Under AMD64, all registers used to pass arguments to functions
1850 * are volatile across calls.
1851 * FIXME: Optimize this.
1853 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1856 ins->opcode = OP_REGOFFSET;
1858 switch (ainfo->storage) {
1860 case ArgInFloatSSEReg:
1861 case ArgInDoubleSSEReg:
1863 ins->opcode = OP_REGVAR;
1864 ins->dreg = ainfo->reg;
1868 g_assert (!cfg->arch.omit_fp);
1869 ins->opcode = OP_REGOFFSET;
1870 ins->inst_basereg = cfg->frame_reg;
1871 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1873 case ArgValuetypeInReg:
1875 case ArgValuetypeAddrInIReg: {
1877 g_assert (!cfg->arch.omit_fp);
1879 MONO_INST_NEW (cfg, indir, 0);
1880 indir->opcode = OP_REGOFFSET;
1881 if (ainfo->pair_storage [0] == ArgInIReg) {
1882 indir->inst_basereg = cfg->frame_reg;
1883 offset = ALIGN_TO (offset, sizeof (gpointer));
1884 offset += (sizeof (gpointer));
1885 indir->inst_offset = - offset;
1888 indir->inst_basereg = cfg->frame_reg;
1889 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1892 ins->opcode = OP_VTARG_ADDR;
1893 ins->inst_left = indir;
1901 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1902 ins->opcode = OP_REGOFFSET;
1903 ins->inst_basereg = cfg->frame_reg;
1904 /* These arguments are saved to the stack in the prolog */
1905 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1906 if (cfg->arch.omit_fp) {
1907 ins->inst_offset = offset;
1908 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1909 // Arguments are yet supported by the stack map creation code
1910 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1912 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1913 ins->inst_offset = - offset;
1914 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1920 cfg->stack_offset = offset;
1924 mono_arch_create_vars (MonoCompile *cfg)
1926 MonoMethodSignature *sig;
1930 sig = mono_method_signature (cfg->method);
1932 if (!cfg->arch.cinfo)
1933 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1934 cinfo = cfg->arch.cinfo;
1936 if (cinfo->ret.storage == ArgValuetypeInReg)
1937 cfg->ret_var_is_local = TRUE;
1939 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1940 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1941 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1942 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1943 printf ("vret_addr = ");
1944 mono_print_ins (cfg->vret_addr);
1948 if (cfg->gen_sdb_seq_points) {
1951 if (cfg->compile_aot) {
1952 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1953 ins->flags |= MONO_INST_VOLATILE;
1954 cfg->arch.seq_point_info_var = ins;
1956 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1957 ins->flags |= MONO_INST_VOLATILE;
1958 cfg->arch.ss_tramp_var = ins;
1961 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1962 ins->flags |= MONO_INST_VOLATILE;
1963 cfg->arch.ss_trigger_page_var = ins;
1966 if (cfg->method->save_lmf)
1967 cfg->create_lmf_var = TRUE;
1969 if (cfg->method->save_lmf) {
1971 #if !defined(TARGET_WIN32)
1972 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1973 cfg->lmf_ir_mono_lmf = TRUE;
1979 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1985 MONO_INST_NEW (cfg, ins, OP_MOVE);
1986 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1987 ins->sreg1 = tree->dreg;
1988 MONO_ADD_INS (cfg->cbb, ins);
1989 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1991 case ArgInFloatSSEReg:
1992 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1993 ins->dreg = mono_alloc_freg (cfg);
1994 ins->sreg1 = tree->dreg;
1995 MONO_ADD_INS (cfg->cbb, ins);
1997 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1999 case ArgInDoubleSSEReg:
2000 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2001 ins->dreg = mono_alloc_freg (cfg);
2002 ins->sreg1 = tree->dreg;
2003 MONO_ADD_INS (cfg->cbb, ins);
2005 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2009 g_assert_not_reached ();
2014 arg_storage_to_load_membase (ArgStorage storage)
2018 #if defined(__mono_ilp32__)
2019 return OP_LOADI8_MEMBASE;
2021 return OP_LOAD_MEMBASE;
2023 case ArgInDoubleSSEReg:
2024 return OP_LOADR8_MEMBASE;
2025 case ArgInFloatSSEReg:
2026 return OP_LOADR4_MEMBASE;
2028 g_assert_not_reached ();
2035 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2037 MonoMethodSignature *tmp_sig;
2040 if (call->tail_call)
2043 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2046 * mono_ArgIterator_Setup assumes the signature cookie is
2047 * passed first and all the arguments which were before it are
2048 * passed on the stack after the signature. So compensate by
2049 * passing a different signature.
2051 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2052 tmp_sig->param_count -= call->signature->sentinelpos;
2053 tmp_sig->sentinelpos = 0;
2054 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2056 sig_reg = mono_alloc_ireg (cfg);
2057 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2059 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2063 static inline LLVMArgStorage
2064 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2068 return LLVMArgInIReg;
2072 g_assert_not_reached ();
2078 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2084 LLVMCallInfo *linfo;
2085 MonoType *t, *sig_ret;
2087 n = sig->param_count + sig->hasthis;
2088 sig_ret = mini_get_underlying_type (cfg, sig->ret);
2090 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2092 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2095 * LLVM always uses the native ABI while we use our own ABI, the
2096 * only difference is the handling of vtypes:
2097 * - we only pass/receive them in registers in some cases, and only
2098 * in 1 or 2 integer registers.
2100 if (cinfo->ret.storage == ArgValuetypeInReg) {
2102 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2103 cfg->disable_llvm = TRUE;
2107 linfo->ret.storage = LLVMArgVtypeInReg;
2108 for (j = 0; j < 2; ++j)
2109 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2112 if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2113 /* Vtype returned using a hidden argument */
2114 linfo->ret.storage = LLVMArgVtypeRetAddr;
2115 linfo->vret_arg_index = cinfo->vret_arg_index;
2118 for (i = 0; i < n; ++i) {
2119 ainfo = cinfo->args + i;
2121 if (i >= sig->hasthis)
2122 t = sig->params [i - sig->hasthis];
2124 t = &mono_defaults.int_class->byval_arg;
2126 linfo->args [i].storage = LLVMArgNone;
2128 switch (ainfo->storage) {
2130 linfo->args [i].storage = LLVMArgInIReg;
2132 case ArgInDoubleSSEReg:
2133 case ArgInFloatSSEReg:
2134 linfo->args [i].storage = LLVMArgInFPReg;
2137 if (MONO_TYPE_ISSTRUCT (t)) {
2138 linfo->args [i].storage = LLVMArgVtypeByVal;
2140 linfo->args [i].storage = LLVMArgInIReg;
2142 if (t->type == MONO_TYPE_R4)
2143 linfo->args [i].storage = LLVMArgInFPReg;
2144 else if (t->type == MONO_TYPE_R8)
2145 linfo->args [i].storage = LLVMArgInFPReg;
2149 case ArgValuetypeInReg:
2151 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2152 cfg->disable_llvm = TRUE;
2156 linfo->args [i].storage = LLVMArgVtypeInReg;
2157 for (j = 0; j < 2; ++j)
2158 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2161 cfg->exception_message = g_strdup ("ainfo->storage");
2162 cfg->disable_llvm = TRUE;
2172 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2175 MonoMethodSignature *sig;
2181 sig = call->signature;
2182 n = sig->param_count + sig->hasthis;
2184 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2188 if (COMPILE_LLVM (cfg)) {
2189 /* We shouldn't be called in the llvm case */
2190 cfg->disable_llvm = TRUE;
2195 * Emit all arguments which are passed on the stack to prevent register
2196 * allocation problems.
2198 for (i = 0; i < n; ++i) {
2200 ainfo = cinfo->args + i;
2202 in = call->args [i];
2204 if (sig->hasthis && i == 0)
2205 t = &mono_defaults.object_class->byval_arg;
2207 t = sig->params [i - sig->hasthis];
2209 t = mini_get_underlying_type (cfg, t);
2210 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2212 if (t->type == MONO_TYPE_R4)
2213 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2214 else if (t->type == MONO_TYPE_R8)
2215 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2217 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2219 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2221 if (cfg->compute_gc_maps) {
2224 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2230 * Emit all parameters passed in registers in non-reverse order for better readability
2231 * and to help the optimization in emit_prolog ().
2233 for (i = 0; i < n; ++i) {
2234 ainfo = cinfo->args + i;
2236 in = call->args [i];
2238 if (ainfo->storage == ArgInIReg)
2239 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2242 for (i = n - 1; i >= 0; --i) {
2245 ainfo = cinfo->args + i;
2247 in = call->args [i];
2249 if (sig->hasthis && i == 0)
2250 t = &mono_defaults.object_class->byval_arg;
2252 t = sig->params [i - sig->hasthis];
2253 t = mini_get_underlying_type (cfg, t);
2255 switch (ainfo->storage) {
2259 case ArgInFloatSSEReg:
2260 case ArgInDoubleSSEReg:
2261 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2264 case ArgValuetypeInReg:
2265 case ArgValuetypeAddrInIReg:
2266 if (ainfo->storage == ArgOnStack && call->tail_call) {
2267 MonoInst *call_inst = (MonoInst*)call;
2268 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2269 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2270 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
2274 if (t->type == MONO_TYPE_TYPEDBYREF) {
2275 size = sizeof (MonoTypedRef);
2276 align = sizeof (gpointer);
2280 size = mono_type_native_stack_size (t, &align);
2283 * Other backends use mono_type_stack_size (), but that
2284 * aligns the size to 8, which is larger than the size of
2285 * the source, leading to reads of invalid memory if the
2286 * source is at the end of address space.
2288 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2291 g_assert (in->klass);
2293 if (ainfo->storage == ArgOnStack && size >= 10000) {
2294 /* Avoid asserts in emit_memcpy () */
2295 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2296 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2297 /* Continue normally */
2301 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2302 arg->sreg1 = in->dreg;
2303 arg->klass = mono_class_from_mono_type (t);
2304 arg->backend.size = size;
2305 arg->inst_p0 = call;
2306 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2307 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2309 MONO_ADD_INS (cfg->cbb, arg);
2314 g_assert_not_reached ();
2317 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2318 /* Emit the signature cookie just before the implicit arguments */
2319 emit_sig_cookie (cfg, call, cinfo);
2322 /* Handle the case where there are no implicit arguments */
2323 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2324 emit_sig_cookie (cfg, call, cinfo);
2326 sig_ret = mini_get_underlying_type (cfg, sig->ret);
2327 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2330 if (cinfo->ret.storage == ArgValuetypeInReg) {
2331 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2333 * Tell the JIT to use a more efficient calling convention: call using
2334 * OP_CALL, compute the result location after the call, and save the
2337 call->vret_in_reg = TRUE;
2339 * Nullify the instruction computing the vret addr to enable
2340 * future optimizations.
2343 NULLIFY_INS (call->vret_var);
2345 if (call->tail_call)
2348 * The valuetype is in RAX:RDX after the call, need to be copied to
2349 * the stack. Push the address here, so the call instruction can
2352 if (!cfg->arch.vret_addr_loc) {
2353 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2354 /* Prevent it from being register allocated or optimized away */
2355 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2358 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2362 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2363 vtarg->sreg1 = call->vret_var->dreg;
2364 vtarg->dreg = mono_alloc_preg (cfg);
2365 MONO_ADD_INS (cfg->cbb, vtarg);
2367 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2371 if (cfg->method->save_lmf) {
2372 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2373 MONO_ADD_INS (cfg->cbb, arg);
2376 call->stack_usage = cinfo->stack_usage;
2380 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2383 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2384 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2385 int size = ins->backend.size;
2387 if (ainfo->storage == ArgValuetypeInReg) {
2391 for (part = 0; part < 2; ++part) {
2392 if (ainfo->pair_storage [part] == ArgNone)
2395 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2396 load->inst_basereg = src->dreg;
2397 load->inst_offset = part * sizeof(mgreg_t);
2399 switch (ainfo->pair_storage [part]) {
2401 load->dreg = mono_alloc_ireg (cfg);
2403 case ArgInDoubleSSEReg:
2404 case ArgInFloatSSEReg:
2405 load->dreg = mono_alloc_freg (cfg);
2408 g_assert_not_reached ();
2410 MONO_ADD_INS (cfg->cbb, load);
2412 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2414 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2415 MonoInst *vtaddr, *load;
2416 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2418 MONO_INST_NEW (cfg, load, OP_LDADDR);
2419 cfg->has_indirection = TRUE;
2420 load->inst_p0 = vtaddr;
2421 vtaddr->flags |= MONO_INST_INDIRECT;
2422 load->type = STACK_MP;
2423 load->klass = vtaddr->klass;
2424 load->dreg = mono_alloc_ireg (cfg);
2425 MONO_ADD_INS (cfg->cbb, load);
2426 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2428 if (ainfo->pair_storage [0] == ArgInIReg) {
2429 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2430 arg->dreg = mono_alloc_ireg (cfg);
2431 arg->sreg1 = load->dreg;
2433 MONO_ADD_INS (cfg->cbb, arg);
2434 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2436 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2440 int dreg = mono_alloc_ireg (cfg);
2442 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2443 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2444 } else if (size <= 40) {
2445 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2447 // FIXME: Code growth
2448 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2451 if (cfg->compute_gc_maps) {
2453 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2459 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2461 MonoType *ret = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
2463 if (ret->type == MONO_TYPE_R4) {
2464 if (COMPILE_LLVM (cfg))
2465 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2467 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2469 } else if (ret->type == MONO_TYPE_R8) {
2470 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2474 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2477 #endif /* DISABLE_JIT */
2479 #define EMIT_COND_BRANCH(ins,cond,sign) \
2480 if (ins->inst_true_bb->native_offset) { \
2481 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2483 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2484 if ((cfg->opt & MONO_OPT_BRANCH) && \
2485 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2486 x86_branch8 (code, cond, 0, sign); \
2488 x86_branch32 (code, cond, 0, sign); \
2492 MonoMethodSignature *sig;
2497 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2505 switch (cinfo->ret.storage) {
2509 case ArgValuetypeInReg: {
2510 ArgInfo *ainfo = &cinfo->ret;
2512 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2514 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2522 for (i = 0; i < cinfo->nargs; ++i) {
2523 ArgInfo *ainfo = &cinfo->args [i];
2524 switch (ainfo->storage) {
2527 case ArgValuetypeInReg:
2528 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2530 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2542 * mono_arch_dyn_call_prepare:
2544 * Return a pointer to an arch-specific structure which contains information
2545 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2546 * supported for SIG.
2547 * This function is equivalent to ffi_prep_cif in libffi.
2550 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2552 ArchDynCallInfo *info;
2555 cinfo = get_call_info (NULL, NULL, sig);
2557 if (!dyn_call_supported (sig, cinfo)) {
2562 info = g_new0 (ArchDynCallInfo, 1);
2563 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2565 info->cinfo = cinfo;
2567 return (MonoDynCallInfo*)info;
2571 * mono_arch_dyn_call_free:
2573 * Free a MonoDynCallInfo structure.
2576 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2578 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2580 g_free (ainfo->cinfo);
2584 #if !defined(__native_client__)
2585 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2586 #define GREG_TO_PTR(greg) (gpointer)(greg)
2588 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2589 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2590 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2594 * mono_arch_get_start_dyn_call:
2596 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2597 * store the result into BUF.
2598 * ARGS should be an array of pointers pointing to the arguments.
2599 * RET should point to a memory buffer large enought to hold the result of the
2601 * This function should be as fast as possible, any work which does not depend
2602 * on the actual values of the arguments should be done in
2603 * mono_arch_dyn_call_prepare ().
2604 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2608 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2610 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2611 DynCallArgs *p = (DynCallArgs*)buf;
2612 int arg_index, greg, i, pindex;
2613 MonoMethodSignature *sig = dinfo->sig;
2615 g_assert (buf_len >= sizeof (DynCallArgs));
2624 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2625 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2630 if (dinfo->cinfo->vtype_retaddr)
2631 p->regs [greg ++] = PTR_TO_GREG(ret);
2633 for (i = pindex; i < sig->param_count; i++) {
2634 MonoType *t = mini_type_get_underlying_type (NULL, sig->params [i]);
2635 gpointer *arg = args [arg_index ++];
2638 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2643 case MONO_TYPE_STRING:
2644 case MONO_TYPE_CLASS:
2645 case MONO_TYPE_ARRAY:
2646 case MONO_TYPE_SZARRAY:
2647 case MONO_TYPE_OBJECT:
2651 #if !defined(__mono_ilp32__)
2655 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2656 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2658 #if defined(__mono_ilp32__)
2661 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2662 p->regs [greg ++] = *(guint64*)(arg);
2666 p->regs [greg ++] = *(guint8*)(arg);
2669 p->regs [greg ++] = *(gint8*)(arg);
2672 p->regs [greg ++] = *(gint16*)(arg);
2675 p->regs [greg ++] = *(guint16*)(arg);
2678 p->regs [greg ++] = *(gint32*)(arg);
2681 p->regs [greg ++] = *(guint32*)(arg);
2683 case MONO_TYPE_GENERICINST:
2684 if (MONO_TYPE_IS_REFERENCE (t)) {
2685 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2690 case MONO_TYPE_VALUETYPE: {
2691 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2693 g_assert (ainfo->storage == ArgValuetypeInReg);
2694 if (ainfo->pair_storage [0] != ArgNone) {
2695 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2696 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2698 if (ainfo->pair_storage [1] != ArgNone) {
2699 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2700 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2705 g_assert_not_reached ();
2709 g_assert (greg <= PARAM_REGS);
2713 * mono_arch_finish_dyn_call:
2715 * Store the result of a dyn call into the return value buffer passed to
2716 * start_dyn_call ().
2717 * This function should be as fast as possible, any work which does not depend
2718 * on the actual values of the arguments should be done in
2719 * mono_arch_dyn_call_prepare ().
2722 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2724 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2725 MonoMethodSignature *sig = dinfo->sig;
2726 guint8 *ret = ((DynCallArgs*)buf)->ret;
2727 mgreg_t res = ((DynCallArgs*)buf)->res;
2728 MonoType *sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
2730 switch (sig_ret->type) {
2731 case MONO_TYPE_VOID:
2732 *(gpointer*)ret = NULL;
2734 case MONO_TYPE_STRING:
2735 case MONO_TYPE_CLASS:
2736 case MONO_TYPE_ARRAY:
2737 case MONO_TYPE_SZARRAY:
2738 case MONO_TYPE_OBJECT:
2742 *(gpointer*)ret = GREG_TO_PTR(res);
2748 *(guint8*)ret = res;
2751 *(gint16*)ret = res;
2754 *(guint16*)ret = res;
2757 *(gint32*)ret = res;
2760 *(guint32*)ret = res;
2763 *(gint64*)ret = res;
2766 *(guint64*)ret = res;
2768 case MONO_TYPE_GENERICINST:
2769 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2770 *(gpointer*)ret = GREG_TO_PTR(res);
2775 case MONO_TYPE_VALUETYPE:
2776 if (dinfo->cinfo->vtype_retaddr) {
2779 ArgInfo *ainfo = &dinfo->cinfo->ret;
2781 g_assert (ainfo->storage == ArgValuetypeInReg);
2783 if (ainfo->pair_storage [0] != ArgNone) {
2784 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2785 ((mgreg_t*)ret)[0] = res;
2788 g_assert (ainfo->pair_storage [1] == ArgNone);
2792 g_assert_not_reached ();
2796 /* emit an exception if condition is fail */
2797 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2799 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2800 if (tins == NULL) { \
2801 mono_add_patch_info (cfg, code - cfg->native_code, \
2802 MONO_PATCH_INFO_EXC, exc_name); \
2803 x86_branch32 (code, cond, 0, signed); \
2805 EMIT_COND_BRANCH (tins, cond, signed); \
2809 #define EMIT_FPCOMPARE(code) do { \
2810 amd64_fcompp (code); \
2811 amd64_fnstsw (code); \
2814 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2815 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2816 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2817 amd64_ ##op (code); \
2818 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2819 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2823 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2825 gboolean no_patch = FALSE;
2828 * FIXME: Add support for thunks
2831 gboolean near_call = FALSE;
2834 * Indirect calls are expensive so try to make a near call if possible.
2835 * The caller memory is allocated by the code manager so it is
2836 * guaranteed to be at a 32 bit offset.
2839 if (patch_type != MONO_PATCH_INFO_ABS) {
2840 /* The target is in memory allocated using the code manager */
2843 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2844 if (((MonoMethod*)data)->klass->image->aot_module)
2845 /* The callee might be an AOT method */
2847 if (((MonoMethod*)data)->dynamic)
2848 /* The target is in malloc-ed memory */
2852 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2854 * The call might go directly to a native function without
2857 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2859 gconstpointer target = mono_icall_get_wrapper (mi);
2860 if ((((guint64)target) >> 32) != 0)
2866 MonoJumpInfo *jinfo = NULL;
2868 if (cfg->abs_patches)
2869 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2871 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2872 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2873 if (mi && (((guint64)mi->func) >> 32) == 0)
2878 * This is not really an optimization, but required because the
2879 * generic class init trampolines use R11 to pass the vtable.
2884 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2886 if (info->func == info->wrapper) {
2888 if ((((guint64)info->func) >> 32) == 0)
2892 /* See the comment in mono_codegen () */
2893 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2897 else if ((((guint64)data) >> 32) == 0) {
2904 if (cfg->method->dynamic)
2905 /* These methods are allocated using malloc */
2908 #ifdef MONO_ARCH_NOMAP32BIT
2911 #if defined(__native_client__)
2912 /* Always use near_call == TRUE for Native Client */
2915 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2916 if (optimize_for_xen)
2919 if (cfg->compile_aot) {
2926 * Align the call displacement to an address divisible by 4 so it does
2927 * not span cache lines. This is required for code patching to work on SMP
2930 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2931 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2932 amd64_padding (code, pad_size);
2934 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2935 amd64_call_code (code, 0);
2938 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2939 amd64_set_reg_template (code, GP_SCRATCH_REG);
2940 amd64_call_reg (code, GP_SCRATCH_REG);
2947 static inline guint8*
2948 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2951 if (win64_adjust_stack)
2952 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2954 code = emit_call_body (cfg, code, patch_type, data);
2956 if (win64_adjust_stack)
2957 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2964 store_membase_imm_to_store_membase_reg (int opcode)
2967 case OP_STORE_MEMBASE_IMM:
2968 return OP_STORE_MEMBASE_REG;
2969 case OP_STOREI4_MEMBASE_IMM:
2970 return OP_STOREI4_MEMBASE_REG;
2971 case OP_STOREI8_MEMBASE_IMM:
2972 return OP_STOREI8_MEMBASE_REG;
2980 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2983 * mono_arch_peephole_pass_1:
2985 * Perform peephole opts which should/can be performed before local regalloc
2988 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2992 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2993 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2995 switch (ins->opcode) {
2999 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3001 * X86_LEA is like ADD, but doesn't have the
3002 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3003 * its operand to 64 bit.
3005 ins->opcode = OP_X86_LEA_MEMBASE;
3006 ins->inst_basereg = ins->sreg1;
3011 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3015 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3016 * the latter has length 2-3 instead of 6 (reverse constant
3017 * propagation). These instruction sequences are very common
3018 * in the initlocals bblock.
3020 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3021 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3022 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3023 ins2->sreg1 = ins->dreg;
3024 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3026 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3029 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3037 case OP_COMPARE_IMM:
3038 case OP_LCOMPARE_IMM:
3039 /* OP_COMPARE_IMM (reg, 0)
3041 * OP_AMD64_TEST_NULL (reg)
3044 ins->opcode = OP_AMD64_TEST_NULL;
3046 case OP_ICOMPARE_IMM:
3048 ins->opcode = OP_X86_TEST_NULL;
3050 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3052 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3053 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3055 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3056 * OP_COMPARE_IMM reg, imm
3058 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3060 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3061 ins->inst_basereg == last_ins->inst_destbasereg &&
3062 ins->inst_offset == last_ins->inst_offset) {
3063 ins->opcode = OP_ICOMPARE_IMM;
3064 ins->sreg1 = last_ins->sreg1;
3066 /* check if we can remove cmp reg,0 with test null */
3068 ins->opcode = OP_X86_TEST_NULL;
3074 mono_peephole_ins (bb, ins);
3079 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3083 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3084 switch (ins->opcode) {
3087 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3088 /* reg = 0 -> XOR (reg, reg) */
3089 /* XOR sets cflags on x86, so we cant do it always */
3090 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3091 ins->opcode = OP_LXOR;
3092 ins->sreg1 = ins->dreg;
3093 ins->sreg2 = ins->dreg;
3101 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3102 * 0 result into 64 bits.
3104 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3105 ins->opcode = OP_IXOR;
3109 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3113 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3114 * the latter has length 2-3 instead of 6 (reverse constant
3115 * propagation). These instruction sequences are very common
3116 * in the initlocals bblock.
3118 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3119 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3120 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3121 ins2->sreg1 = ins->dreg;
3122 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3124 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3127 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3136 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3137 ins->opcode = OP_X86_INC_REG;
3140 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3141 ins->opcode = OP_X86_DEC_REG;
3145 mono_peephole_ins (bb, ins);
3149 #define NEW_INS(cfg,ins,dest,op) do { \
3150 MONO_INST_NEW ((cfg), (dest), (op)); \
3151 (dest)->cil_code = (ins)->cil_code; \
3152 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3156 * mono_arch_lowering_pass:
3158 * Converts complex opcodes into simpler ones so that each IR instruction
3159 * corresponds to one machine instruction.
3162 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3164 MonoInst *ins, *n, *temp;
3167 * FIXME: Need to add more instructions, but the current machine
3168 * description can't model some parts of the composite instructions like
3171 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3172 switch (ins->opcode) {
3176 case OP_IDIV_UN_IMM:
3177 case OP_IREM_UN_IMM:
3180 mono_decompose_op_imm (cfg, bb, ins);
3182 case OP_COMPARE_IMM:
3183 case OP_LCOMPARE_IMM:
3184 if (!amd64_is_imm32 (ins->inst_imm)) {
3185 NEW_INS (cfg, ins, temp, OP_I8CONST);
3186 temp->inst_c0 = ins->inst_imm;
3187 temp->dreg = mono_alloc_ireg (cfg);
3188 ins->opcode = OP_COMPARE;
3189 ins->sreg2 = temp->dreg;
3192 #ifndef __mono_ilp32__
3193 case OP_LOAD_MEMBASE:
3195 case OP_LOADI8_MEMBASE:
3196 #ifndef __native_client_codegen__
3197 /* Don't generate memindex opcodes (to simplify */
3198 /* read sandboxing) */
3199 if (!amd64_is_imm32 (ins->inst_offset)) {
3200 NEW_INS (cfg, ins, temp, OP_I8CONST);
3201 temp->inst_c0 = ins->inst_offset;
3202 temp->dreg = mono_alloc_ireg (cfg);
3203 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3204 ins->inst_indexreg = temp->dreg;
3208 #ifndef __mono_ilp32__
3209 case OP_STORE_MEMBASE_IMM:
3211 case OP_STOREI8_MEMBASE_IMM:
3212 if (!amd64_is_imm32 (ins->inst_imm)) {
3213 NEW_INS (cfg, ins, temp, OP_I8CONST);
3214 temp->inst_c0 = ins->inst_imm;
3215 temp->dreg = mono_alloc_ireg (cfg);
3216 ins->opcode = OP_STOREI8_MEMBASE_REG;
3217 ins->sreg1 = temp->dreg;
3220 #ifdef MONO_ARCH_SIMD_INTRINSICS
3221 case OP_EXPAND_I1: {
3222 int temp_reg1 = mono_alloc_ireg (cfg);
3223 int temp_reg2 = mono_alloc_ireg (cfg);
3224 int original_reg = ins->sreg1;
3226 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3227 temp->sreg1 = original_reg;
3228 temp->dreg = temp_reg1;
3230 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3231 temp->sreg1 = temp_reg1;
3232 temp->dreg = temp_reg2;
3235 NEW_INS (cfg, ins, temp, OP_LOR);
3236 temp->sreg1 = temp->dreg = temp_reg2;
3237 temp->sreg2 = temp_reg1;
3239 ins->opcode = OP_EXPAND_I2;
3240 ins->sreg1 = temp_reg2;
3249 bb->max_vreg = cfg->next_vreg;
3253 branch_cc_table [] = {
3254 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3255 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3256 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3259 /* Maps CMP_... constants to X86_CC_... constants */
3262 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3263 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3267 cc_signed_table [] = {
3268 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3269 FALSE, FALSE, FALSE, FALSE
3272 /*#include "cprop.c"*/
3274 static unsigned char*
3275 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3278 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3280 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3283 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3285 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3289 static unsigned char*
3290 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3292 int sreg = tree->sreg1;
3293 int need_touch = FALSE;
3295 #if defined(TARGET_WIN32)
3297 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3298 if (!tree->flags & MONO_INST_INIT)
3307 * If requested stack size is larger than one page,
3308 * perform stack-touch operation
3311 * Generate stack probe code.
3312 * Under Windows, it is necessary to allocate one page at a time,
3313 * "touching" stack after each successful sub-allocation. This is
3314 * because of the way stack growth is implemented - there is a
3315 * guard page before the lowest stack page that is currently commited.
3316 * Stack normally grows sequentially so OS traps access to the
3317 * guard page and commits more pages when needed.
3319 amd64_test_reg_imm (code, sreg, ~0xFFF);
3320 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3322 br[2] = code; /* loop */
3323 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3324 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3325 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3326 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3327 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3328 amd64_patch (br[3], br[2]);
3329 amd64_test_reg_reg (code, sreg, sreg);
3330 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3331 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3333 br[1] = code; x86_jump8 (code, 0);
3335 amd64_patch (br[0], code);
3336 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3337 amd64_patch (br[1], code);
3338 amd64_patch (br[4], code);
3341 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3343 if (tree->flags & MONO_INST_INIT) {
3345 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3346 amd64_push_reg (code, AMD64_RAX);
3349 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3350 amd64_push_reg (code, AMD64_RCX);
3353 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3354 amd64_push_reg (code, AMD64_RDI);
3358 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3359 if (sreg != AMD64_RCX)
3360 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3361 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3363 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3364 if (cfg->param_area)
3365 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3367 #if defined(__default_codegen__)
3368 amd64_prefix (code, X86_REP_PREFIX);
3370 #elif defined(__native_client_codegen__)
3371 /* NaCl stos pseudo-instruction */
3372 amd64_codegen_pre(code);
3373 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3374 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3375 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3376 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3377 amd64_prefix (code, X86_REP_PREFIX);
3379 amd64_codegen_post(code);
3380 #endif /* __native_client_codegen__ */
3382 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3383 amd64_pop_reg (code, AMD64_RDI);
3384 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3385 amd64_pop_reg (code, AMD64_RCX);
3386 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3387 amd64_pop_reg (code, AMD64_RAX);
3393 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3398 /* Move return value to the target register */
3399 /* FIXME: do this in the local reg allocator */
3400 switch (ins->opcode) {
3403 case OP_CALL_MEMBASE:
3406 case OP_LCALL_MEMBASE:
3407 g_assert (ins->dreg == AMD64_RAX);
3411 case OP_FCALL_MEMBASE: {
3412 MonoType *rtype = mini_get_underlying_type (cfg, ((MonoCallInst*)ins)->signature->ret);
3413 if (rtype->type == MONO_TYPE_R4) {
3414 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3417 if (ins->dreg != AMD64_XMM0)
3418 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3424 case OP_RCALL_MEMBASE:
3425 if (ins->dreg != AMD64_XMM0)
3426 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3430 case OP_VCALL_MEMBASE:
3433 case OP_VCALL2_MEMBASE:
3434 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3435 if (cinfo->ret.storage == ArgValuetypeInReg) {
3436 MonoInst *loc = cfg->arch.vret_addr_loc;
3438 /* Load the destination address */
3439 g_assert (loc->opcode == OP_REGOFFSET);
3440 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3442 for (quad = 0; quad < 2; quad ++) {
3443 switch (cinfo->ret.pair_storage [quad]) {
3445 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3447 case ArgInFloatSSEReg:
3448 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3450 case ArgInDoubleSSEReg:
3451 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3466 #endif /* DISABLE_JIT */
3469 static int tls_gs_offset;
3473 mono_amd64_have_tls_get (void)
3476 static gboolean have_tls_get = FALSE;
3477 static gboolean inited = FALSE;
3481 return have_tls_get;
3483 #if MONO_HAVE_FAST_TLS
3484 ins = (guint8*)pthread_getspecific;
3487 * We're looking for these two instructions:
3489 * mov %gs:[offset](,%rdi,8),%rax
3492 have_tls_get = ins [0] == 0x65 &&
3502 tls_gs_offset = ins[5];
3507 return have_tls_get;
3508 #elif defined(TARGET_ANDROID)
3516 mono_amd64_get_tls_gs_offset (void)
3519 return tls_gs_offset;
3521 g_assert_not_reached ();
3527 * mono_amd64_emit_tls_get:
3528 * @code: buffer to store code to
3529 * @dreg: hard register where to place the result
3530 * @tls_offset: offset info
3532 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3533 * the dreg register the item in the thread local storage identified
3536 * Returns: a pointer to the end of the stored code
3539 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3542 if (tls_offset < 64) {
3543 x86_prefix (code, X86_GS_PREFIX);
3544 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3548 g_assert (tls_offset < 0x440);
3549 /* Load TEB->TlsExpansionSlots */
3550 x86_prefix (code, X86_GS_PREFIX);
3551 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3552 amd64_test_reg_reg (code, dreg, dreg);
3554 amd64_branch (code, X86_CC_EQ, code, TRUE);
3555 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3556 amd64_patch (buf [0], code);
3558 #elif defined(__APPLE__)
3559 x86_prefix (code, X86_GS_PREFIX);
3560 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3562 if (optimize_for_xen) {
3563 x86_prefix (code, X86_FS_PREFIX);
3564 amd64_mov_reg_mem (code, dreg, 0, 8);
3565 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3567 x86_prefix (code, X86_FS_PREFIX);
3568 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3575 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3577 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3579 if (dreg != offset_reg)
3580 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3581 amd64_prefix (code, X86_GS_PREFIX);
3582 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3583 #elif defined(__linux__)
3586 if (dreg == offset_reg) {
3587 /* Use a temporary reg by saving it to the redzone */
3588 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3589 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3590 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3591 offset_reg = tmpreg;
3593 x86_prefix (code, X86_FS_PREFIX);
3594 amd64_mov_reg_mem (code, dreg, 0, 8);
3595 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3597 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3599 g_assert_not_reached ();
3605 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3608 g_assert_not_reached ();
3609 #elif defined(__APPLE__)
3610 x86_prefix (code, X86_GS_PREFIX);
3611 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3613 g_assert (!optimize_for_xen);
3614 x86_prefix (code, X86_FS_PREFIX);
3615 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3621 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3623 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3625 g_assert_not_reached ();
3626 #elif defined(__APPLE__)
3627 x86_prefix (code, X86_GS_PREFIX);
3628 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3630 x86_prefix (code, X86_FS_PREFIX);
3631 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3637 * mono_arch_translate_tls_offset:
3639 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3642 mono_arch_translate_tls_offset (int offset)
3645 return tls_gs_offset + (offset * 8);
3654 * Emit code to initialize an LMF structure at LMF_OFFSET.
3657 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3660 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3663 * sp is saved right before calls but we need to save it here too so
3664 * async stack walks would work.
3666 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3668 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3669 if (cfg->arch.omit_fp && cfa_offset != -1)
3670 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3672 /* These can't contain refs */
3673 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3674 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3675 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3676 /* These are handled automatically by the stack marking code */
3677 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3682 #define REAL_PRINT_REG(text,reg) \
3683 mono_assert (reg >= 0); \
3684 amd64_push_reg (code, AMD64_RAX); \
3685 amd64_push_reg (code, AMD64_RDX); \
3686 amd64_push_reg (code, AMD64_RCX); \
3687 amd64_push_reg (code, reg); \
3688 amd64_push_imm (code, reg); \
3689 amd64_push_imm (code, text " %d %p\n"); \
3690 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3691 amd64_call_reg (code, AMD64_RAX); \
3692 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3693 amd64_pop_reg (code, AMD64_RCX); \
3694 amd64_pop_reg (code, AMD64_RDX); \
3695 amd64_pop_reg (code, AMD64_RAX);
3697 /* benchmark and set based on cpu */
3698 #define LOOP_ALIGNMENT 8
3699 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3703 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3708 guint8 *code = cfg->native_code + cfg->code_len;
3711 /* Fix max_offset estimate for each successor bb */
3712 if (cfg->opt & MONO_OPT_BRANCH) {
3713 int current_offset = cfg->code_len;
3714 MonoBasicBlock *current_bb;
3715 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3716 current_bb->max_offset = current_offset;
3717 current_offset += current_bb->max_length;
3721 if (cfg->opt & MONO_OPT_LOOP) {
3722 int pad, align = LOOP_ALIGNMENT;
3723 /* set alignment depending on cpu */
3724 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3726 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3727 amd64_padding (code, pad);
3728 cfg->code_len += pad;
3729 bb->native_offset = cfg->code_len;
3733 #if defined(__native_client_codegen__)
3734 /* For Native Client, all indirect call/jump targets must be */
3735 /* 32-byte aligned. Exception handler blocks are jumped to */
3736 /* indirectly as well. */
3737 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3738 (bb->flags & BB_EXCEPTION_HANDLER);
3740 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3741 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3742 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3743 cfg->code_len += pad;
3744 bb->native_offset = cfg->code_len;
3746 #endif /*__native_client_codegen__*/
3748 if (cfg->verbose_level > 2)
3749 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3751 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3752 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3753 g_assert (!cfg->compile_aot);
3755 cov->data [bb->dfn].cil_code = bb->cil_code;
3756 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3757 /* this is not thread save, but good enough */
3758 amd64_inc_membase (code, AMD64_R11, 0);
3761 offset = code - cfg->native_code;
3763 mono_debug_open_block (cfg, bb, offset);
3765 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3766 x86_breakpoint (code);
3768 MONO_BB_FOR_EACH_INS (bb, ins) {
3769 offset = code - cfg->native_code;
3771 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3773 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3775 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3776 cfg->code_size *= 2;
3777 cfg->native_code = mono_realloc_native_code(cfg);
3778 code = cfg->native_code + offset;
3779 cfg->stat_code_reallocs++;
3782 if (cfg->debug_info)
3783 mono_debug_record_line_number (cfg, ins, offset);
3785 switch (ins->opcode) {
3787 amd64_mul_reg (code, ins->sreg2, TRUE);
3790 amd64_mul_reg (code, ins->sreg2, FALSE);
3792 case OP_X86_SETEQ_MEMBASE:
3793 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3795 case OP_STOREI1_MEMBASE_IMM:
3796 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3798 case OP_STOREI2_MEMBASE_IMM:
3799 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3801 case OP_STOREI4_MEMBASE_IMM:
3802 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3804 case OP_STOREI1_MEMBASE_REG:
3805 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3807 case OP_STOREI2_MEMBASE_REG:
3808 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3810 /* In AMD64 NaCl, pointers are 4 bytes, */
3811 /* so STORE_* != STOREI8_*. Likewise below. */
3812 case OP_STORE_MEMBASE_REG:
3813 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3815 case OP_STOREI8_MEMBASE_REG:
3816 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3818 case OP_STOREI4_MEMBASE_REG:
3819 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3821 case OP_STORE_MEMBASE_IMM:
3822 #ifndef __native_client_codegen__
3823 /* In NaCl, this could be a PCONST type, which could */
3824 /* mean a pointer type was copied directly into the */
3825 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3826 /* the value would be 0x00000000FFFFFFFF which is */
3827 /* not proper for an imm32 unless you cast it. */
3828 g_assert (amd64_is_imm32 (ins->inst_imm));
3830 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3832 case OP_STOREI8_MEMBASE_IMM:
3833 g_assert (amd64_is_imm32 (ins->inst_imm));
3834 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3837 #ifdef __mono_ilp32__
3838 /* In ILP32, pointers are 4 bytes, so separate these */
3839 /* cases, use literal 8 below where we really want 8 */
3840 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3841 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3845 // FIXME: Decompose this earlier
3846 if (amd64_is_imm32 (ins->inst_imm))
3847 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3849 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3850 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3854 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3855 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3858 // FIXME: Decompose this earlier
3859 if (amd64_is_imm32 (ins->inst_imm))
3860 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3862 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3863 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3867 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3868 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3871 /* For NaCl, pointers are 4 bytes, so separate these */
3872 /* cases, use literal 8 below where we really want 8 */
3873 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3874 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3876 case OP_LOAD_MEMBASE:
3877 g_assert (amd64_is_imm32 (ins->inst_offset));
3878 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3880 case OP_LOADI8_MEMBASE:
3881 /* Use literal 8 instead of sizeof pointer or */
3882 /* register, we really want 8 for this opcode */
3883 g_assert (amd64_is_imm32 (ins->inst_offset));
3884 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3886 case OP_LOADI4_MEMBASE:
3887 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3889 case OP_LOADU4_MEMBASE:
3890 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3892 case OP_LOADU1_MEMBASE:
3893 /* The cpu zero extends the result into 64 bits */
3894 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3896 case OP_LOADI1_MEMBASE:
3897 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3899 case OP_LOADU2_MEMBASE:
3900 /* The cpu zero extends the result into 64 bits */
3901 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3903 case OP_LOADI2_MEMBASE:
3904 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3906 case OP_AMD64_LOADI8_MEMINDEX:
3907 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3909 case OP_LCONV_TO_I1:
3910 case OP_ICONV_TO_I1:
3912 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3914 case OP_LCONV_TO_I2:
3915 case OP_ICONV_TO_I2:
3917 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3919 case OP_LCONV_TO_U1:
3920 case OP_ICONV_TO_U1:
3921 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3923 case OP_LCONV_TO_U2:
3924 case OP_ICONV_TO_U2:
3925 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3928 /* Clean out the upper word */
3929 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3932 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3936 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3938 case OP_COMPARE_IMM:
3939 #if defined(__mono_ilp32__)
3940 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3941 g_assert (amd64_is_imm32 (ins->inst_imm));
3942 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3945 case OP_LCOMPARE_IMM:
3946 g_assert (amd64_is_imm32 (ins->inst_imm));
3947 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3949 case OP_X86_COMPARE_REG_MEMBASE:
3950 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3952 case OP_X86_TEST_NULL:
3953 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3955 case OP_AMD64_TEST_NULL:
3956 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3959 case OP_X86_ADD_REG_MEMBASE:
3960 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3962 case OP_X86_SUB_REG_MEMBASE:
3963 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3965 case OP_X86_AND_REG_MEMBASE:
3966 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3968 case OP_X86_OR_REG_MEMBASE:
3969 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3971 case OP_X86_XOR_REG_MEMBASE:
3972 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3975 case OP_X86_ADD_MEMBASE_IMM:
3976 /* FIXME: Make a 64 version too */
3977 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3979 case OP_X86_SUB_MEMBASE_IMM:
3980 g_assert (amd64_is_imm32 (ins->inst_imm));
3981 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3983 case OP_X86_AND_MEMBASE_IMM:
3984 g_assert (amd64_is_imm32 (ins->inst_imm));
3985 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3987 case OP_X86_OR_MEMBASE_IMM:
3988 g_assert (amd64_is_imm32 (ins->inst_imm));
3989 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3991 case OP_X86_XOR_MEMBASE_IMM:
3992 g_assert (amd64_is_imm32 (ins->inst_imm));
3993 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3995 case OP_X86_ADD_MEMBASE_REG:
3996 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3998 case OP_X86_SUB_MEMBASE_REG:
3999 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4001 case OP_X86_AND_MEMBASE_REG:
4002 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4004 case OP_X86_OR_MEMBASE_REG:
4005 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4007 case OP_X86_XOR_MEMBASE_REG:
4008 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4010 case OP_X86_INC_MEMBASE:
4011 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4013 case OP_X86_INC_REG:
4014 amd64_inc_reg_size (code, ins->dreg, 4);
4016 case OP_X86_DEC_MEMBASE:
4017 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4019 case OP_X86_DEC_REG:
4020 amd64_dec_reg_size (code, ins->dreg, 4);
4022 case OP_X86_MUL_REG_MEMBASE:
4023 case OP_X86_MUL_MEMBASE_REG:
4024 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4026 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4027 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4029 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4030 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4032 case OP_AMD64_COMPARE_MEMBASE_REG:
4033 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4035 case OP_AMD64_COMPARE_MEMBASE_IMM:
4036 g_assert (amd64_is_imm32 (ins->inst_imm));
4037 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4039 case OP_X86_COMPARE_MEMBASE8_IMM:
4040 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4042 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4043 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4045 case OP_AMD64_COMPARE_REG_MEMBASE:
4046 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4049 case OP_AMD64_ADD_REG_MEMBASE:
4050 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4052 case OP_AMD64_SUB_REG_MEMBASE:
4053 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4055 case OP_AMD64_AND_REG_MEMBASE:
4056 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4058 case OP_AMD64_OR_REG_MEMBASE:
4059 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4061 case OP_AMD64_XOR_REG_MEMBASE:
4062 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4065 case OP_AMD64_ADD_MEMBASE_REG:
4066 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4068 case OP_AMD64_SUB_MEMBASE_REG:
4069 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4071 case OP_AMD64_AND_MEMBASE_REG:
4072 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4074 case OP_AMD64_OR_MEMBASE_REG:
4075 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4077 case OP_AMD64_XOR_MEMBASE_REG:
4078 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4081 case OP_AMD64_ADD_MEMBASE_IMM:
4082 g_assert (amd64_is_imm32 (ins->inst_imm));
4083 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4085 case OP_AMD64_SUB_MEMBASE_IMM:
4086 g_assert (amd64_is_imm32 (ins->inst_imm));
4087 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4089 case OP_AMD64_AND_MEMBASE_IMM:
4090 g_assert (amd64_is_imm32 (ins->inst_imm));
4091 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4093 case OP_AMD64_OR_MEMBASE_IMM:
4094 g_assert (amd64_is_imm32 (ins->inst_imm));
4095 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4097 case OP_AMD64_XOR_MEMBASE_IMM:
4098 g_assert (amd64_is_imm32 (ins->inst_imm));
4099 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4103 amd64_breakpoint (code);
4105 case OP_RELAXED_NOP:
4106 x86_prefix (code, X86_REP_PREFIX);
4114 case OP_DUMMY_STORE:
4115 case OP_DUMMY_ICONST:
4116 case OP_DUMMY_R8CONST:
4117 case OP_NOT_REACHED:
4120 case OP_IL_SEQ_POINT:
4121 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4123 case OP_SEQ_POINT: {
4126 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4127 if (cfg->compile_aot) {
4128 MonoInst *var = cfg->arch.ss_tramp_var;
4131 /* Load ss_tramp_var */
4132 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4133 /* Load the trampoline address */
4134 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4135 /* Call it if it is non-null */
4136 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4138 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4139 amd64_call_reg (code, AMD64_R11);
4140 amd64_patch (label, code);
4143 * Read from the single stepping trigger page. This will cause a
4144 * SIGSEGV when single stepping is enabled.
4145 * We do this _before_ the breakpoint, so single stepping after
4146 * a breakpoint is hit will step to the next IL offset.
4148 MonoInst *var = cfg->arch.ss_trigger_page_var;
4150 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4151 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4156 * This is the address which is saved in seq points,
4158 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4160 if (cfg->compile_aot) {
4161 guint32 offset = code - cfg->native_code;
4163 MonoInst *info_var = cfg->arch.seq_point_info_var;
4167 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4168 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4169 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4170 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4171 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4173 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4174 /* Call the trampoline */
4175 amd64_call_reg (code, AMD64_R11);
4176 amd64_patch (label, code);
4179 * A placeholder for a possible breakpoint inserted by
4180 * mono_arch_set_breakpoint ().
4182 for (i = 0; i < breakpoint_size; ++i)
4186 * Add an additional nop so skipping the bp doesn't cause the ip to point
4187 * to another IL offset.
4195 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4198 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4202 g_assert (amd64_is_imm32 (ins->inst_imm));
4203 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4206 g_assert (amd64_is_imm32 (ins->inst_imm));
4207 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4212 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4215 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4219 g_assert (amd64_is_imm32 (ins->inst_imm));
4220 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4223 g_assert (amd64_is_imm32 (ins->inst_imm));
4224 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4227 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4231 g_assert (amd64_is_imm32 (ins->inst_imm));
4232 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4235 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4240 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4242 switch (ins->inst_imm) {
4246 if (ins->dreg != ins->sreg1)
4247 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4248 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4251 /* LEA r1, [r2 + r2*2] */
4252 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4255 /* LEA r1, [r2 + r2*4] */
4256 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4259 /* LEA r1, [r2 + r2*2] */
4261 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4262 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4265 /* LEA r1, [r2 + r2*8] */
4266 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4269 /* LEA r1, [r2 + r2*4] */
4271 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4272 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4275 /* LEA r1, [r2 + r2*2] */
4277 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4278 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4281 /* LEA r1, [r2 + r2*4] */
4282 /* LEA r1, [r1 + r1*4] */
4283 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4284 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4287 /* LEA r1, [r2 + r2*4] */
4289 /* LEA r1, [r1 + r1*4] */
4290 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4291 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4292 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4295 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4302 #if defined( __native_client_codegen__ )
4303 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4304 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4306 /* Regalloc magic makes the div/rem cases the same */
4307 if (ins->sreg2 == AMD64_RDX) {
4308 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4310 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4313 amd64_div_reg (code, ins->sreg2, TRUE);
4318 #if defined( __native_client_codegen__ )
4319 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4320 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4322 if (ins->sreg2 == AMD64_RDX) {
4323 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4324 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4325 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4327 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4328 amd64_div_reg (code, ins->sreg2, FALSE);
4333 #if defined( __native_client_codegen__ )
4334 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4335 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4337 if (ins->sreg2 == AMD64_RDX) {
4338 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4339 amd64_cdq_size (code, 4);
4340 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4342 amd64_cdq_size (code, 4);
4343 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4348 #if defined( __native_client_codegen__ )
4349 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4350 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4352 if (ins->sreg2 == AMD64_RDX) {
4353 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4354 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4355 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4357 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4358 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4362 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4363 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4366 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4370 g_assert (amd64_is_imm32 (ins->inst_imm));
4371 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4374 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4378 g_assert (amd64_is_imm32 (ins->inst_imm));
4379 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4382 g_assert (ins->sreg2 == AMD64_RCX);
4383 amd64_shift_reg (code, X86_SHL, ins->dreg);
4386 g_assert (ins->sreg2 == AMD64_RCX);
4387 amd64_shift_reg (code, X86_SAR, ins->dreg);
4391 g_assert (amd64_is_imm32 (ins->inst_imm));
4392 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4395 g_assert (amd64_is_imm32 (ins->inst_imm));
4396 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4398 case OP_LSHR_UN_IMM:
4399 g_assert (amd64_is_imm32 (ins->inst_imm));
4400 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4403 g_assert (ins->sreg2 == AMD64_RCX);
4404 amd64_shift_reg (code, X86_SHR, ins->dreg);
4408 g_assert (amd64_is_imm32 (ins->inst_imm));
4409 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4414 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4417 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4420 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4423 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4427 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4430 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4433 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4436 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4439 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4442 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4445 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4448 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4451 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4454 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4457 amd64_neg_reg_size (code, ins->sreg1, 4);
4460 amd64_not_reg_size (code, ins->sreg1, 4);
4463 g_assert (ins->sreg2 == AMD64_RCX);
4464 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4467 g_assert (ins->sreg2 == AMD64_RCX);
4468 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4471 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4473 case OP_ISHR_UN_IMM:
4474 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4477 g_assert (ins->sreg2 == AMD64_RCX);
4478 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4481 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4484 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4487 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4488 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4490 case OP_IMUL_OVF_UN:
4491 case OP_LMUL_OVF_UN: {
4492 /* the mul operation and the exception check should most likely be split */
4493 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4494 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4495 /*g_assert (ins->sreg2 == X86_EAX);
4496 g_assert (ins->dreg == X86_EAX);*/
4497 if (ins->sreg2 == X86_EAX) {
4498 non_eax_reg = ins->sreg1;
4499 } else if (ins->sreg1 == X86_EAX) {
4500 non_eax_reg = ins->sreg2;
4502 /* no need to save since we're going to store to it anyway */
4503 if (ins->dreg != X86_EAX) {
4505 amd64_push_reg (code, X86_EAX);
4507 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4508 non_eax_reg = ins->sreg2;
4510 if (ins->dreg == X86_EDX) {
4513 amd64_push_reg (code, X86_EAX);
4517 amd64_push_reg (code, X86_EDX);
4519 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4520 /* save before the check since pop and mov don't change the flags */
4521 if (ins->dreg != X86_EAX)
4522 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4524 amd64_pop_reg (code, X86_EDX);
4526 amd64_pop_reg (code, X86_EAX);
4527 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4531 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4533 case OP_ICOMPARE_IMM:
4534 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4556 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4564 case OP_CMOV_INE_UN:
4565 case OP_CMOV_IGE_UN:
4566 case OP_CMOV_IGT_UN:
4567 case OP_CMOV_ILE_UN:
4568 case OP_CMOV_ILT_UN:
4574 case OP_CMOV_LNE_UN:
4575 case OP_CMOV_LGE_UN:
4576 case OP_CMOV_LGT_UN:
4577 case OP_CMOV_LLE_UN:
4578 case OP_CMOV_LLT_UN:
4579 g_assert (ins->dreg == ins->sreg1);
4580 /* This needs to operate on 64 bit values */
4581 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4585 amd64_not_reg (code, ins->sreg1);
4588 amd64_neg_reg (code, ins->sreg1);
4593 if ((((guint64)ins->inst_c0) >> 32) == 0)
4594 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4596 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4599 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4600 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4603 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4604 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4607 if (ins->dreg != ins->sreg1)
4608 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4610 case OP_AMD64_SET_XMMREG_R4: {
4612 if (ins->dreg != ins->sreg1)
4613 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4615 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4619 case OP_AMD64_SET_XMMREG_R8: {
4620 if (ins->dreg != ins->sreg1)
4621 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4625 MonoCallInst *call = (MonoCallInst*)ins;
4626 int i, save_area_offset;
4628 g_assert (!cfg->method->save_lmf);
4630 /* Restore callee saved registers */
4631 save_area_offset = cfg->arch.reg_save_area_offset;
4632 for (i = 0; i < AMD64_NREG; ++i)
4633 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4634 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4635 save_area_offset += 8;
4638 if (cfg->arch.omit_fp) {
4639 if (cfg->arch.stack_alloc_size)
4640 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4642 if (call->stack_usage)
4645 /* Copy arguments on the stack to our argument area */
4646 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4647 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4648 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4654 offset = code - cfg->native_code;
4655 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4656 if (cfg->compile_aot)
4657 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4659 amd64_set_reg_template (code, AMD64_R11);
4660 amd64_jump_reg (code, AMD64_R11);
4661 ins->flags |= MONO_INST_GC_CALLSITE;
4662 ins->backend.pc_offset = code - cfg->native_code;
4666 /* ensure ins->sreg1 is not NULL */
4667 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4670 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4671 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4681 call = (MonoCallInst*)ins;
4683 * The AMD64 ABI forces callers to know about varargs.
4685 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4686 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4687 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4689 * Since the unmanaged calling convention doesn't contain a
4690 * 'vararg' entry, we have to treat every pinvoke call as a
4691 * potential vararg call.
4695 for (i = 0; i < AMD64_XMM_NREG; ++i)
4696 if (call->used_fregs & (1 << i))
4699 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4701 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4704 if (ins->flags & MONO_INST_HAS_METHOD)
4705 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4707 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4708 ins->flags |= MONO_INST_GC_CALLSITE;
4709 ins->backend.pc_offset = code - cfg->native_code;
4710 code = emit_move_return_value (cfg, ins, code);
4717 case OP_VOIDCALL_REG:
4719 call = (MonoCallInst*)ins;
4721 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4722 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4723 ins->sreg1 = AMD64_R11;
4727 * The AMD64 ABI forces callers to know about varargs.
4729 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4730 if (ins->sreg1 == AMD64_RAX) {
4731 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4732 ins->sreg1 = AMD64_R11;
4734 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4735 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4737 * Since the unmanaged calling convention doesn't contain a
4738 * 'vararg' entry, we have to treat every pinvoke call as a
4739 * potential vararg call.
4743 for (i = 0; i < AMD64_XMM_NREG; ++i)
4744 if (call->used_fregs & (1 << i))
4746 if (ins->sreg1 == AMD64_RAX) {
4747 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4748 ins->sreg1 = AMD64_R11;
4751 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4753 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4756 amd64_call_reg (code, ins->sreg1);
4757 ins->flags |= MONO_INST_GC_CALLSITE;
4758 ins->backend.pc_offset = code - cfg->native_code;
4759 code = emit_move_return_value (cfg, ins, code);
4761 case OP_FCALL_MEMBASE:
4762 case OP_RCALL_MEMBASE:
4763 case OP_LCALL_MEMBASE:
4764 case OP_VCALL_MEMBASE:
4765 case OP_VCALL2_MEMBASE:
4766 case OP_VOIDCALL_MEMBASE:
4767 case OP_CALL_MEMBASE:
4768 call = (MonoCallInst*)ins;
4770 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4771 ins->flags |= MONO_INST_GC_CALLSITE;
4772 ins->backend.pc_offset = code - cfg->native_code;
4773 code = emit_move_return_value (cfg, ins, code);
4777 MonoInst *var = cfg->dyn_call_var;
4779 g_assert (var->opcode == OP_REGOFFSET);
4781 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4782 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4784 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4786 /* Save args buffer */
4787 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4789 /* Set argument registers */
4790 for (i = 0; i < PARAM_REGS; ++i)
4791 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4794 amd64_call_reg (code, AMD64_R10);
4796 ins->flags |= MONO_INST_GC_CALLSITE;
4797 ins->backend.pc_offset = code - cfg->native_code;
4800 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4801 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4804 case OP_AMD64_SAVE_SP_TO_LMF: {
4805 MonoInst *lmf_var = cfg->lmf_var;
4806 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4810 g_assert_not_reached ();
4811 amd64_push_reg (code, ins->sreg1);
4813 case OP_X86_PUSH_IMM:
4814 g_assert_not_reached ();
4815 g_assert (amd64_is_imm32 (ins->inst_imm));
4816 amd64_push_imm (code, ins->inst_imm);
4818 case OP_X86_PUSH_MEMBASE:
4819 g_assert_not_reached ();
4820 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4822 case OP_X86_PUSH_OBJ: {
4823 int size = ALIGN_TO (ins->inst_imm, 8);
4825 g_assert_not_reached ();
4827 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4828 amd64_push_reg (code, AMD64_RDI);
4829 amd64_push_reg (code, AMD64_RSI);
4830 amd64_push_reg (code, AMD64_RCX);
4831 if (ins->inst_offset)
4832 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4834 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4835 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4836 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4838 amd64_prefix (code, X86_REP_PREFIX);
4840 amd64_pop_reg (code, AMD64_RCX);
4841 amd64_pop_reg (code, AMD64_RSI);
4842 amd64_pop_reg (code, AMD64_RDI);
4845 case OP_GENERIC_CLASS_INIT: {
4846 static int byte_offset = -1;
4847 static guint8 bitmask;
4850 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4852 if (byte_offset < 0)
4853 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4855 amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4857 amd64_branch8 (code, X86_CC_NZ, -1, 1);
4859 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ADDR, "specific_trampoline_generic_class_init", FALSE);
4860 ins->flags |= MONO_INST_GC_CALLSITE;
4861 ins->backend.pc_offset = code - cfg->native_code;
4863 x86_patch (jump, code);
4868 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4870 case OP_X86_LEA_MEMBASE:
4871 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4874 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4877 /* keep alignment */
4878 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4879 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4880 code = mono_emit_stack_alloc (cfg, code, ins);
4881 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4882 if (cfg->param_area)
4883 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4885 case OP_LOCALLOC_IMM: {
4886 guint32 size = ins->inst_imm;
4887 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4889 if (ins->flags & MONO_INST_INIT) {
4893 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4894 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4896 for (i = 0; i < size; i += 8)
4897 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4898 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4900 amd64_mov_reg_imm (code, ins->dreg, size);
4901 ins->sreg1 = ins->dreg;
4903 code = mono_emit_stack_alloc (cfg, code, ins);
4904 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4907 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4908 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4910 if (cfg->param_area)
4911 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4915 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4916 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4917 (gpointer)"mono_arch_throw_exception", FALSE);
4918 ins->flags |= MONO_INST_GC_CALLSITE;
4919 ins->backend.pc_offset = code - cfg->native_code;
4923 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4924 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4925 (gpointer)"mono_arch_rethrow_exception", FALSE);
4926 ins->flags |= MONO_INST_GC_CALLSITE;
4927 ins->backend.pc_offset = code - cfg->native_code;
4930 case OP_CALL_HANDLER:
4932 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4933 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4934 amd64_call_imm (code, 0);
4935 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4936 /* Restore stack alignment */
4937 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4939 case OP_START_HANDLER: {
4940 /* Even though we're saving RSP, use sizeof */
4941 /* gpointer because spvar is of type IntPtr */
4942 /* see: mono_create_spvar_for_region */
4943 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4944 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4946 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4947 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4949 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4953 case OP_ENDFINALLY: {
4954 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4955 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4959 case OP_ENDFILTER: {
4960 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4961 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4962 /* The local allocator will put the result into RAX */
4967 if (ins->dreg != AMD64_RAX)
4968 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4971 ins->inst_c0 = code - cfg->native_code;
4974 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4975 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4977 if (ins->inst_target_bb->native_offset) {
4978 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4980 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4981 if ((cfg->opt & MONO_OPT_BRANCH) &&
4982 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4983 x86_jump8 (code, 0);
4985 x86_jump32 (code, 0);
4989 amd64_jump_reg (code, ins->sreg1);
5012 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5013 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5015 case OP_COND_EXC_EQ:
5016 case OP_COND_EXC_NE_UN:
5017 case OP_COND_EXC_LT:
5018 case OP_COND_EXC_LT_UN:
5019 case OP_COND_EXC_GT:
5020 case OP_COND_EXC_GT_UN:
5021 case OP_COND_EXC_GE:
5022 case OP_COND_EXC_GE_UN:
5023 case OP_COND_EXC_LE:
5024 case OP_COND_EXC_LE_UN:
5025 case OP_COND_EXC_IEQ:
5026 case OP_COND_EXC_INE_UN:
5027 case OP_COND_EXC_ILT:
5028 case OP_COND_EXC_ILT_UN:
5029 case OP_COND_EXC_IGT:
5030 case OP_COND_EXC_IGT_UN:
5031 case OP_COND_EXC_IGE:
5032 case OP_COND_EXC_IGE_UN:
5033 case OP_COND_EXC_ILE:
5034 case OP_COND_EXC_ILE_UN:
5035 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5037 case OP_COND_EXC_OV:
5038 case OP_COND_EXC_NO:
5040 case OP_COND_EXC_NC:
5041 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5042 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5044 case OP_COND_EXC_IOV:
5045 case OP_COND_EXC_INO:
5046 case OP_COND_EXC_IC:
5047 case OP_COND_EXC_INC:
5048 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5049 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5052 /* floating point opcodes */
5054 double d = *(double *)ins->inst_p0;
5056 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5057 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5060 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5061 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5066 float f = *(float *)ins->inst_p0;
5068 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5070 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5072 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5075 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5076 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5078 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5082 case OP_STORER8_MEMBASE_REG:
5083 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5085 case OP_LOADR8_MEMBASE:
5086 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5088 case OP_STORER4_MEMBASE_REG:
5090 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5092 /* This requires a double->single conversion */
5093 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5094 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5097 case OP_LOADR4_MEMBASE:
5099 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5101 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5102 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5105 case OP_ICONV_TO_R4:
5107 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5109 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5110 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5113 case OP_ICONV_TO_R8:
5114 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5116 case OP_LCONV_TO_R4:
5118 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5120 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5121 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5124 case OP_LCONV_TO_R8:
5125 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5127 case OP_FCONV_TO_R4:
5129 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5131 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5132 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5135 case OP_FCONV_TO_I1:
5136 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5138 case OP_FCONV_TO_U1:
5139 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5141 case OP_FCONV_TO_I2:
5142 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5144 case OP_FCONV_TO_U2:
5145 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5147 case OP_FCONV_TO_U4:
5148 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5150 case OP_FCONV_TO_I4:
5152 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5154 case OP_FCONV_TO_I8:
5155 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5158 case OP_RCONV_TO_I1:
5159 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5160 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5162 case OP_RCONV_TO_U1:
5163 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5164 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5166 case OP_RCONV_TO_I2:
5167 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5168 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5170 case OP_RCONV_TO_U2:
5171 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5172 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5174 case OP_RCONV_TO_I4:
5175 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5177 case OP_RCONV_TO_U4:
5178 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5180 case OP_RCONV_TO_I8:
5181 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5183 case OP_RCONV_TO_R8:
5184 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5186 case OP_RCONV_TO_R4:
5187 if (ins->dreg != ins->sreg1)
5188 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5191 case OP_LCONV_TO_R_UN: {
5194 /* Based on gcc code */
5195 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5196 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5199 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5200 br [1] = code; x86_jump8 (code, 0);
5201 amd64_patch (br [0], code);
5204 /* Save to the red zone */
5205 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5206 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5207 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5208 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5209 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5210 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5211 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5212 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5213 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5215 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5216 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5217 amd64_patch (br [1], code);
5220 case OP_LCONV_TO_OVF_U4:
5221 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5222 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5223 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5225 case OP_LCONV_TO_OVF_I4_UN:
5226 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5227 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5228 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5231 if (ins->dreg != ins->sreg1)
5232 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5235 if (ins->dreg != ins->sreg1)
5236 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5238 case OP_MOVE_F_TO_I4:
5240 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5242 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5243 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5246 case OP_MOVE_I4_TO_F:
5247 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5249 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5251 case OP_MOVE_F_TO_I8:
5252 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5254 case OP_MOVE_I8_TO_F:
5255 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5258 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5261 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5264 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5267 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5270 static double r8_0 = -0.0;
5272 g_assert (ins->sreg1 == ins->dreg);
5274 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5275 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5279 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5282 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5285 static guint64 d = 0x7fffffffffffffffUL;
5287 g_assert (ins->sreg1 == ins->dreg);
5289 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5290 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5294 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5298 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5301 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5304 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5307 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5310 static float r4_0 = -0.0;
5312 g_assert (ins->sreg1 == ins->dreg);
5314 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5315 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5316 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5321 g_assert (cfg->opt & MONO_OPT_CMOV);
5322 g_assert (ins->dreg == ins->sreg1);
5323 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5324 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5327 g_assert (cfg->opt & MONO_OPT_CMOV);
5328 g_assert (ins->dreg == ins->sreg1);
5329 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5330 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5333 g_assert (cfg->opt & MONO_OPT_CMOV);
5334 g_assert (ins->dreg == ins->sreg1);
5335 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5336 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5339 g_assert (cfg->opt & MONO_OPT_CMOV);
5340 g_assert (ins->dreg == ins->sreg1);
5341 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5342 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5345 g_assert (cfg->opt & MONO_OPT_CMOV);
5346 g_assert (ins->dreg == ins->sreg1);
5347 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5348 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5351 g_assert (cfg->opt & MONO_OPT_CMOV);
5352 g_assert (ins->dreg == ins->sreg1);
5353 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5354 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5357 g_assert (cfg->opt & MONO_OPT_CMOV);
5358 g_assert (ins->dreg == ins->sreg1);
5359 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5360 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5363 g_assert (cfg->opt & MONO_OPT_CMOV);
5364 g_assert (ins->dreg == ins->sreg1);
5365 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5366 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5372 * The two arguments are swapped because the fbranch instructions
5373 * depend on this for the non-sse case to work.
5375 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5379 * FIXME: Get rid of this.
5380 * The two arguments are swapped because the fbranch instructions
5381 * depend on this for the non-sse case to work.
5383 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5387 /* zeroing the register at the start results in
5388 * shorter and faster code (we can also remove the widening op)
5390 guchar *unordered_check;
5392 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5393 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5394 unordered_check = code;
5395 x86_branch8 (code, X86_CC_P, 0, FALSE);
5397 if (ins->opcode == OP_FCEQ) {
5398 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5399 amd64_patch (unordered_check, code);
5401 guchar *jump_to_end;
5402 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5404 x86_jump8 (code, 0);
5405 amd64_patch (unordered_check, code);
5406 amd64_inc_reg (code, ins->dreg);
5407 amd64_patch (jump_to_end, code);
5413 /* zeroing the register at the start results in
5414 * shorter and faster code (we can also remove the widening op)
5416 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5417 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5418 if (ins->opcode == OP_FCLT_UN) {
5419 guchar *unordered_check = code;
5420 guchar *jump_to_end;
5421 x86_branch8 (code, X86_CC_P, 0, FALSE);
5422 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5424 x86_jump8 (code, 0);
5425 amd64_patch (unordered_check, code);
5426 amd64_inc_reg (code, ins->dreg);
5427 amd64_patch (jump_to_end, code);
5429 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5434 guchar *unordered_check;
5435 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5436 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5437 unordered_check = code;
5438 x86_branch8 (code, X86_CC_P, 0, FALSE);
5439 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5440 amd64_patch (unordered_check, code);
5445 /* zeroing the register at the start results in
5446 * shorter and faster code (we can also remove the widening op)
5448 guchar *unordered_check;
5450 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5451 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5452 if (ins->opcode == OP_FCGT) {
5453 unordered_check = code;
5454 x86_branch8 (code, X86_CC_P, 0, FALSE);
5455 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5456 amd64_patch (unordered_check, code);
5458 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5463 guchar *unordered_check;
5464 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5465 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5466 unordered_check = code;
5467 x86_branch8 (code, X86_CC_P, 0, FALSE);
5468 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5469 amd64_patch (unordered_check, code);
5479 gboolean unordered = FALSE;
5481 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5482 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5484 switch (ins->opcode) {
5486 x86_cond = X86_CC_EQ;
5489 x86_cond = X86_CC_LT;
5492 x86_cond = X86_CC_GT;
5495 x86_cond = X86_CC_GT;
5499 x86_cond = X86_CC_LT;
5503 g_assert_not_reached ();
5508 guchar *unordered_check;
5509 guchar *jump_to_end;
5511 unordered_check = code;
5512 x86_branch8 (code, X86_CC_P, 0, FALSE);
5513 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5515 x86_jump8 (code, 0);
5516 amd64_patch (unordered_check, code);
5517 amd64_inc_reg (code, ins->dreg);
5518 amd64_patch (jump_to_end, code);
5520 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5524 case OP_FCLT_MEMBASE:
5525 case OP_FCGT_MEMBASE:
5526 case OP_FCLT_UN_MEMBASE:
5527 case OP_FCGT_UN_MEMBASE:
5528 case OP_FCEQ_MEMBASE: {
5529 guchar *unordered_check, *jump_to_end;
5532 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5533 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5535 switch (ins->opcode) {
5536 case OP_FCEQ_MEMBASE:
5537 x86_cond = X86_CC_EQ;
5539 case OP_FCLT_MEMBASE:
5540 case OP_FCLT_UN_MEMBASE:
5541 x86_cond = X86_CC_LT;
5543 case OP_FCGT_MEMBASE:
5544 case OP_FCGT_UN_MEMBASE:
5545 x86_cond = X86_CC_GT;
5548 g_assert_not_reached ();
5551 unordered_check = code;
5552 x86_branch8 (code, X86_CC_P, 0, FALSE);
5553 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5555 switch (ins->opcode) {
5556 case OP_FCEQ_MEMBASE:
5557 case OP_FCLT_MEMBASE:
5558 case OP_FCGT_MEMBASE:
5559 amd64_patch (unordered_check, code);
5561 case OP_FCLT_UN_MEMBASE:
5562 case OP_FCGT_UN_MEMBASE:
5564 x86_jump8 (code, 0);
5565 amd64_patch (unordered_check, code);
5566 amd64_inc_reg (code, ins->dreg);
5567 amd64_patch (jump_to_end, code);
5575 guchar *jump = code;
5576 x86_branch8 (code, X86_CC_P, 0, TRUE);
5577 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5578 amd64_patch (jump, code);
5582 /* Branch if C013 != 100 */
5583 /* branch if !ZF or (PF|CF) */
5584 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5585 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5586 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5589 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5592 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5593 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5597 if (ins->opcode == OP_FBGT) {
5600 /* skip branch if C1=1 */
5602 x86_branch8 (code, X86_CC_P, 0, FALSE);
5603 /* branch if (C0 | C3) = 1 */
5604 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5605 amd64_patch (br1, code);
5608 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5612 /* Branch if C013 == 100 or 001 */
5615 /* skip branch if C1=1 */
5617 x86_branch8 (code, X86_CC_P, 0, FALSE);
5618 /* branch if (C0 | C3) = 1 */
5619 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5620 amd64_patch (br1, code);
5624 /* Branch if C013 == 000 */
5625 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5628 /* Branch if C013=000 or 100 */
5631 /* skip branch if C1=1 */
5633 x86_branch8 (code, X86_CC_P, 0, FALSE);
5634 /* branch if C0=0 */
5635 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5636 amd64_patch (br1, code);
5640 /* Branch if C013 != 001 */
5641 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5642 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5645 /* Transfer value to the fp stack */
5646 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5647 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5648 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5650 amd64_push_reg (code, AMD64_RAX);
5652 amd64_fnstsw (code);
5653 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5654 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5655 amd64_pop_reg (code, AMD64_RAX);
5656 amd64_fstp (code, 0);
5657 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5658 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5661 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5664 case OP_TLS_GET_REG:
5665 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5668 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5671 case OP_TLS_SET_REG: {
5672 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5675 case OP_MEMORY_BARRIER: {
5676 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5680 case OP_ATOMIC_ADD_I4:
5681 case OP_ATOMIC_ADD_I8: {
5682 int dreg = ins->dreg;
5683 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5685 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5688 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5689 amd64_prefix (code, X86_LOCK_PREFIX);
5690 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5691 /* dreg contains the old value, add with sreg2 value */
5692 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5694 if (ins->dreg != dreg)
5695 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5699 case OP_ATOMIC_EXCHANGE_I4:
5700 case OP_ATOMIC_EXCHANGE_I8: {
5701 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5703 /* LOCK prefix is implied. */
5704 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5705 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5706 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5709 case OP_ATOMIC_CAS_I4:
5710 case OP_ATOMIC_CAS_I8: {
5713 if (ins->opcode == OP_ATOMIC_CAS_I8)
5719 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5720 * an explanation of how this works.
5722 g_assert (ins->sreg3 == AMD64_RAX);
5723 g_assert (ins->sreg1 != AMD64_RAX);
5724 g_assert (ins->sreg1 != ins->sreg2);
5726 amd64_prefix (code, X86_LOCK_PREFIX);
5727 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5729 if (ins->dreg != AMD64_RAX)
5730 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5733 case OP_ATOMIC_LOAD_I1: {
5734 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5737 case OP_ATOMIC_LOAD_U1: {
5738 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5741 case OP_ATOMIC_LOAD_I2: {
5742 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5745 case OP_ATOMIC_LOAD_U2: {
5746 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5749 case OP_ATOMIC_LOAD_I4: {
5750 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5753 case OP_ATOMIC_LOAD_U4:
5754 case OP_ATOMIC_LOAD_I8:
5755 case OP_ATOMIC_LOAD_U8: {
5756 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5759 case OP_ATOMIC_LOAD_R4: {
5760 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5761 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5764 case OP_ATOMIC_LOAD_R8: {
5765 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5768 case OP_ATOMIC_STORE_I1:
5769 case OP_ATOMIC_STORE_U1:
5770 case OP_ATOMIC_STORE_I2:
5771 case OP_ATOMIC_STORE_U2:
5772 case OP_ATOMIC_STORE_I4:
5773 case OP_ATOMIC_STORE_U4:
5774 case OP_ATOMIC_STORE_I8:
5775 case OP_ATOMIC_STORE_U8: {
5778 switch (ins->opcode) {
5779 case OP_ATOMIC_STORE_I1:
5780 case OP_ATOMIC_STORE_U1:
5783 case OP_ATOMIC_STORE_I2:
5784 case OP_ATOMIC_STORE_U2:
5787 case OP_ATOMIC_STORE_I4:
5788 case OP_ATOMIC_STORE_U4:
5791 case OP_ATOMIC_STORE_I8:
5792 case OP_ATOMIC_STORE_U8:
5797 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5799 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5803 case OP_ATOMIC_STORE_R4: {
5804 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5805 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5807 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5811 case OP_ATOMIC_STORE_R8: {
5814 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5818 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5822 case OP_CARD_TABLE_WBARRIER: {
5823 int ptr = ins->sreg1;
5824 int value = ins->sreg2;
5826 int nursery_shift, card_table_shift;
5827 gpointer card_table_mask;
5828 size_t nursery_size;
5830 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5831 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5832 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5834 /*If either point to the stack we can simply avoid the WB. This happens due to
5835 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5837 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5841 * We need one register we can clobber, we choose EDX and make sreg1
5842 * fixed EAX to work around limitations in the local register allocator.
5843 * sreg2 might get allocated to EDX, but that is not a problem since
5844 * we use it before clobbering EDX.
5846 g_assert (ins->sreg1 == AMD64_RAX);
5849 * This is the code we produce:
5852 * edx >>= nursery_shift
5853 * cmp edx, (nursery_start >> nursery_shift)
5856 * edx >>= card_table_shift
5862 if (mono_gc_card_table_nursery_check ()) {
5863 if (value != AMD64_RDX)
5864 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5865 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5866 if (shifted_nursery_start >> 31) {
5868 * The value we need to compare against is 64 bits, so we need
5869 * another spare register. We use RBX, which we save and
5872 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5873 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5874 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5875 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5877 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5879 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5881 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5882 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5883 if (card_table_mask)
5884 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5886 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5887 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5889 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5891 if (mono_gc_card_table_nursery_check ())
5892 x86_patch (br, code);
5895 #ifdef MONO_ARCH_SIMD_INTRINSICS
5896 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5898 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5901 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5904 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5907 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5910 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5913 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5916 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5917 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5920 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5923 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5926 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5929 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5932 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5935 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5938 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5941 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5944 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5947 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5950 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5953 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5956 case OP_PSHUFLEW_HIGH:
5957 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5958 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5960 case OP_PSHUFLEW_LOW:
5961 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5962 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5965 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5966 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5969 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5970 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5973 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5974 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5978 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5981 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5984 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5987 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5990 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5993 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5996 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5997 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6000 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6003 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6006 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6009 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6012 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6015 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6018 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6021 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6024 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6027 case OP_EXTRACT_MASK:
6028 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6032 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6035 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6038 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6042 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6045 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6048 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6051 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6055 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6058 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6061 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6064 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6068 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6071 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6074 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6078 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6081 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6084 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6088 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6091 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6095 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6098 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6101 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6105 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6108 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6111 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6115 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6118 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6121 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6124 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6128 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6131 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6134 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6137 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6140 case OP_PSUM_ABS_DIFF:
6141 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6144 case OP_UNPACK_LOWB:
6145 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6147 case OP_UNPACK_LOWW:
6148 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6150 case OP_UNPACK_LOWD:
6151 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6153 case OP_UNPACK_LOWQ:
6154 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6156 case OP_UNPACK_LOWPS:
6157 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6159 case OP_UNPACK_LOWPD:
6160 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6163 case OP_UNPACK_HIGHB:
6164 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6166 case OP_UNPACK_HIGHW:
6167 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6169 case OP_UNPACK_HIGHD:
6170 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6172 case OP_UNPACK_HIGHQ:
6173 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6175 case OP_UNPACK_HIGHPS:
6176 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6178 case OP_UNPACK_HIGHPD:
6179 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6183 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6186 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6189 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6192 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6195 case OP_PADDB_SAT_UN:
6196 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6198 case OP_PSUBB_SAT_UN:
6199 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6201 case OP_PADDW_SAT_UN:
6202 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6204 case OP_PSUBW_SAT_UN:
6205 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6209 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6212 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6215 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6218 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6222 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6225 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6228 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6230 case OP_PMULW_HIGH_UN:
6231 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6234 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6238 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6241 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6245 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6248 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6252 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6255 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6259 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6262 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6266 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6269 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6273 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6276 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6280 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6283 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6286 /*TODO: This is appart of the sse spec but not added
6288 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6291 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6296 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6299 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6302 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6305 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6308 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6311 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6314 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6317 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6320 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6323 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6327 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6330 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6334 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6335 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6337 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6342 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6344 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6345 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6349 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6351 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6352 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6353 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6357 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6359 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6362 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6364 case OP_EXTRACTX_U2:
6365 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6367 case OP_INSERTX_U1_SLOW:
6368 /*sreg1 is the extracted ireg (scratch)
6369 /sreg2 is the to be inserted ireg (scratch)
6370 /dreg is the xreg to receive the value*/
6372 /*clear the bits from the extracted word*/
6373 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6374 /*shift the value to insert if needed*/
6375 if (ins->inst_c0 & 1)
6376 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6377 /*join them together*/
6378 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6379 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6381 case OP_INSERTX_I4_SLOW:
6382 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6383 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6384 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6386 case OP_INSERTX_I8_SLOW:
6387 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6389 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6391 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6394 case OP_INSERTX_R4_SLOW:
6395 switch (ins->inst_c0) {
6398 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6400 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6403 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6405 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6407 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6408 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6411 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6413 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6415 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6416 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6419 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6421 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6423 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6424 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6428 case OP_INSERTX_R8_SLOW:
6430 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6432 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6434 case OP_STOREX_MEMBASE_REG:
6435 case OP_STOREX_MEMBASE:
6436 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6438 case OP_LOADX_MEMBASE:
6439 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6441 case OP_LOADX_ALIGNED_MEMBASE:
6442 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6444 case OP_STOREX_ALIGNED_MEMBASE_REG:
6445 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6447 case OP_STOREX_NTA_MEMBASE_REG:
6448 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6450 case OP_PREFETCH_MEMBASE:
6451 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6455 /*FIXME the peephole pass should have killed this*/
6456 if (ins->dreg != ins->sreg1)
6457 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6460 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6462 case OP_ICONV_TO_R4_RAW:
6463 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6466 case OP_FCONV_TO_R8_X:
6467 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6470 case OP_XCONV_R8_TO_I4:
6471 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6472 switch (ins->backend.source_opcode) {
6473 case OP_FCONV_TO_I1:
6474 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6476 case OP_FCONV_TO_U1:
6477 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6479 case OP_FCONV_TO_I2:
6480 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6482 case OP_FCONV_TO_U2:
6483 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6489 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6490 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6491 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6494 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6495 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6498 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6499 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6503 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6505 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6506 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6508 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6511 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6512 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6515 case OP_LIVERANGE_START: {
6516 if (cfg->verbose_level > 1)
6517 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6518 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6521 case OP_LIVERANGE_END: {
6522 if (cfg->verbose_level > 1)
6523 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6524 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6527 case OP_GC_SAFE_POINT: {
6528 const char *polling_func = NULL;
6529 int compare_val = 0;
6532 #if defined (USE_COOP_GC)
6533 polling_func = "mono_threads_state_poll";
6535 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
6536 polling_func = "mono_nacl_gc";
6537 compare_val = 0xFFFFFFFF;
6542 amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6543 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6544 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6545 amd64_patch (br[0], code);
6549 case OP_GC_LIVENESS_DEF:
6550 case OP_GC_LIVENESS_USE:
6551 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6552 ins->backend.pc_offset = code - cfg->native_code;
6554 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6555 ins->backend.pc_offset = code - cfg->native_code;
6556 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6559 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6560 g_assert_not_reached ();
6563 if ((code - cfg->native_code - offset) > max_len) {
6564 #if !defined(__native_client_codegen__)
6565 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6566 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6567 g_assert_not_reached ();
6572 cfg->code_len = code - cfg->native_code;
6575 #endif /* DISABLE_JIT */
6578 mono_arch_register_lowlevel_calls (void)
6580 /* The signature doesn't matter */
6581 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6585 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6587 unsigned char *ip = ji->ip.i + code;
6590 * Debug code to help track down problems where the target of a near call is
6593 if (amd64_is_near_call (ip)) {
6594 gint64 disp = (guint8*)target - (guint8*)ip;
6596 if (!amd64_is_imm32 (disp)) {
6597 printf ("TYPE: %d\n", ji->type);
6599 case MONO_PATCH_INFO_INTERNAL_METHOD:
6600 printf ("V: %s\n", ji->data.name);
6602 case MONO_PATCH_INFO_METHOD_JUMP:
6603 case MONO_PATCH_INFO_METHOD:
6604 printf ("V: %s\n", ji->data.method->name);
6612 amd64_patch (ip, (gpointer)target);
6618 get_max_epilog_size (MonoCompile *cfg)
6620 int max_epilog_size = 16;
6622 if (cfg->method->save_lmf)
6623 max_epilog_size += 256;
6625 if (mono_jit_trace_calls != NULL)
6626 max_epilog_size += 50;
6628 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6629 max_epilog_size += 50;
6631 max_epilog_size += (AMD64_NREG * 2);
6633 return max_epilog_size;
6637 * This macro is used for testing whenever the unwinder works correctly at every point
6638 * where an async exception can happen.
6640 /* This will generate a SIGSEGV at the given point in the code */
6641 #define async_exc_point(code) do { \
6642 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6643 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6644 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6645 cfg->arch.async_point_count ++; \
6650 mono_arch_emit_prolog (MonoCompile *cfg)
6652 MonoMethod *method = cfg->method;
6654 MonoMethodSignature *sig;
6656 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6659 MonoInst *lmf_var = cfg->lmf_var;
6660 gboolean args_clobbered = FALSE;
6661 gboolean trace = FALSE;
6662 #ifdef __native_client_codegen__
6663 guint alignment_check;
6666 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6668 #if defined(__default_codegen__)
6669 code = cfg->native_code = g_malloc (cfg->code_size);
6670 #elif defined(__native_client_codegen__)
6671 /* native_code_alloc is not 32-byte aligned, native_code is. */
6672 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6674 /* Align native_code to next nearest kNaclAlignment byte. */
6675 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6676 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6678 code = cfg->native_code;
6680 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6681 g_assert (alignment_check == 0);
6684 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6687 /* Amount of stack space allocated by register saving code */
6690 /* Offset between RSP and the CFA */
6694 * The prolog consists of the following parts:
6696 * - push rbp, mov rbp, rsp
6697 * - save callee saved regs using pushes
6699 * - save rgctx if needed
6700 * - save lmf if needed
6703 * - save rgctx if needed
6704 * - save lmf if needed
6705 * - save callee saved regs using moves
6710 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6711 // IP saved at CFA - 8
6712 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6713 async_exc_point (code);
6714 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6716 if (!cfg->arch.omit_fp) {
6717 amd64_push_reg (code, AMD64_RBP);
6719 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6720 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6721 async_exc_point (code);
6723 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6725 /* These are handled automatically by the stack marking code */
6726 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6728 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6729 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6730 async_exc_point (code);
6732 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6736 /* The param area is always at offset 0 from sp */
6737 /* This needs to be allocated here, since it has to come after the spill area */
6738 if (cfg->param_area) {
6739 if (cfg->arch.omit_fp)
6741 g_assert_not_reached ();
6742 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6745 if (cfg->arch.omit_fp) {
6747 * On enter, the stack is misaligned by the pushing of the return
6748 * address. It is either made aligned by the pushing of %rbp, or by
6751 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6752 if ((alloc_size % 16) == 0) {
6754 /* Mark the padding slot as NOREF */
6755 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6758 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6759 if (cfg->stack_offset != alloc_size) {
6760 /* Mark the padding slot as NOREF */
6761 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6763 cfg->arch.sp_fp_offset = alloc_size;
6767 cfg->arch.stack_alloc_size = alloc_size;
6769 /* Allocate stack frame */
6771 /* See mono_emit_stack_alloc */
6772 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6773 guint32 remaining_size = alloc_size;
6774 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6775 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6776 guint32 offset = code - cfg->native_code;
6777 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6778 while (required_code_size >= (cfg->code_size - offset))
6779 cfg->code_size *= 2;
6780 cfg->native_code = mono_realloc_native_code (cfg);
6781 code = cfg->native_code + offset;
6782 cfg->stat_code_reallocs++;
6785 while (remaining_size >= 0x1000) {
6786 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6787 if (cfg->arch.omit_fp) {
6788 cfa_offset += 0x1000;
6789 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6791 async_exc_point (code);
6793 if (cfg->arch.omit_fp)
6794 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6797 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6798 remaining_size -= 0x1000;
6800 if (remaining_size) {
6801 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6802 if (cfg->arch.omit_fp) {
6803 cfa_offset += remaining_size;
6804 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6805 async_exc_point (code);
6808 if (cfg->arch.omit_fp)
6809 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6813 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6814 if (cfg->arch.omit_fp) {
6815 cfa_offset += alloc_size;
6816 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6817 async_exc_point (code);
6822 /* Stack alignment check */
6825 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6826 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6827 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6828 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6829 amd64_breakpoint (code);
6833 if (mini_get_debug_options ()->init_stacks) {
6834 /* Fill the stack frame with a dummy value to force deterministic behavior */
6836 /* Save registers to the red zone */
6837 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6838 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6840 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6841 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6842 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6845 #if defined(__default_codegen__)
6846 amd64_prefix (code, X86_REP_PREFIX);
6848 #elif defined(__native_client_codegen__)
6849 /* NaCl stos pseudo-instruction */
6850 amd64_codegen_pre (code);
6851 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6852 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6853 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6854 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6855 amd64_prefix (code, X86_REP_PREFIX);
6857 amd64_codegen_post (code);
6858 #endif /* __native_client_codegen__ */
6860 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6861 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6865 if (method->save_lmf)
6866 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6868 /* Save callee saved registers */
6869 if (cfg->arch.omit_fp) {
6870 save_area_offset = cfg->arch.reg_save_area_offset;
6871 /* Save caller saved registers after sp is adjusted */
6872 /* The registers are saved at the bottom of the frame */
6873 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6875 /* The registers are saved just below the saved rbp */
6876 save_area_offset = cfg->arch.reg_save_area_offset;
6879 for (i = 0; i < AMD64_NREG; ++i) {
6880 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6881 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6883 if (cfg->arch.omit_fp) {
6884 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6885 /* These are handled automatically by the stack marking code */
6886 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6888 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6892 save_area_offset += 8;
6893 async_exc_point (code);
6897 /* store runtime generic context */
6898 if (cfg->rgctx_var) {
6899 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6900 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6902 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6904 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6905 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6908 /* compute max_length in order to use short forward jumps */
6909 max_epilog_size = get_max_epilog_size (cfg);
6910 if (cfg->opt & MONO_OPT_BRANCH) {
6911 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6915 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6917 /* max alignment for loops */
6918 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6919 max_length += LOOP_ALIGNMENT;
6920 #ifdef __native_client_codegen__
6921 /* max alignment for native client */
6922 max_length += kNaClAlignment;
6925 MONO_BB_FOR_EACH_INS (bb, ins) {
6926 #ifdef __native_client_codegen__
6928 int space_in_block = kNaClAlignment -
6929 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6930 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6931 if (space_in_block < max_len && max_len < kNaClAlignment) {
6932 max_length += space_in_block;
6935 #endif /*__native_client_codegen__*/
6936 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6939 /* Take prolog and epilog instrumentation into account */
6940 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6941 max_length += max_epilog_size;
6943 bb->max_length = max_length;
6947 sig = mono_method_signature (method);
6950 cinfo = cfg->arch.cinfo;
6952 if (sig->ret->type != MONO_TYPE_VOID) {
6953 /* Save volatile arguments to the stack */
6954 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6955 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6958 /* Keep this in sync with emit_load_volatile_arguments */
6959 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6960 ArgInfo *ainfo = cinfo->args + i;
6962 ins = cfg->args [i];
6964 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6965 /* Unused arguments */
6968 /* Save volatile arguments to the stack */
6969 if (ins->opcode != OP_REGVAR) {
6970 switch (ainfo->storage) {
6976 if (stack_offset & 0x1)
6978 else if (stack_offset & 0x2)
6980 else if (stack_offset & 0x4)
6985 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6988 * Save the original location of 'this',
6989 * get_generic_info_from_stack_frame () needs this to properly look up
6990 * the argument value during the handling of async exceptions.
6992 if (ins == cfg->args [0]) {
6993 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6994 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6998 case ArgInFloatSSEReg:
6999 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7001 case ArgInDoubleSSEReg:
7002 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7004 case ArgValuetypeInReg:
7005 for (quad = 0; quad < 2; quad ++) {
7006 switch (ainfo->pair_storage [quad]) {
7008 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7010 case ArgInFloatSSEReg:
7011 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7013 case ArgInDoubleSSEReg:
7014 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7019 g_assert_not_reached ();
7023 case ArgValuetypeAddrInIReg:
7024 if (ainfo->pair_storage [0] == ArgInIReg)
7025 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7031 /* Argument allocated to (non-volatile) register */
7032 switch (ainfo->storage) {
7034 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7037 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7040 g_assert_not_reached ();
7043 if (ins == cfg->args [0]) {
7044 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7045 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7050 if (cfg->method->save_lmf)
7051 args_clobbered = TRUE;
7054 args_clobbered = TRUE;
7055 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7058 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7059 args_clobbered = TRUE;
7062 * Optimize the common case of the first bblock making a call with the same
7063 * arguments as the method. This works because the arguments are still in their
7064 * original argument registers.
7065 * FIXME: Generalize this
7067 if (!args_clobbered) {
7068 MonoBasicBlock *first_bb = cfg->bb_entry;
7070 int filter = FILTER_IL_SEQ_POINT;
7072 next = mono_bb_first_inst (first_bb, filter);
7073 if (!next && first_bb->next_bb) {
7074 first_bb = first_bb->next_bb;
7075 next = mono_bb_first_inst (first_bb, filter);
7078 if (first_bb->in_count > 1)
7081 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7082 ArgInfo *ainfo = cinfo->args + i;
7083 gboolean match = FALSE;
7085 ins = cfg->args [i];
7086 if (ins->opcode != OP_REGVAR) {
7087 switch (ainfo->storage) {
7089 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7090 if (next->dreg == ainfo->reg) {
7094 next->opcode = OP_MOVE;
7095 next->sreg1 = ainfo->reg;
7096 /* Only continue if the instruction doesn't change argument regs */
7097 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7107 /* Argument allocated to (non-volatile) register */
7108 switch (ainfo->storage) {
7110 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7121 next = mono_inst_next (next, filter);
7122 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7129 if (cfg->gen_sdb_seq_points) {
7130 MonoInst *info_var = cfg->arch.seq_point_info_var;
7132 /* Initialize seq_point_info_var */
7133 if (cfg->compile_aot) {
7134 /* Initialize the variable from a GOT slot */
7135 /* Same as OP_AOTCONST */
7136 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7137 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7138 g_assert (info_var->opcode == OP_REGOFFSET);
7139 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7142 if (cfg->compile_aot) {
7143 /* Initialize ss_tramp_var */
7144 ins = cfg->arch.ss_tramp_var;
7145 g_assert (ins->opcode == OP_REGOFFSET);
7147 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7148 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7149 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7151 /* Initialize ss_trigger_page_var */
7152 ins = cfg->arch.ss_trigger_page_var;
7154 g_assert (ins->opcode == OP_REGOFFSET);
7156 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7157 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7161 cfg->code_len = code - cfg->native_code;
7163 g_assert (cfg->code_len < cfg->code_size);
7169 mono_arch_emit_epilog (MonoCompile *cfg)
7171 MonoMethod *method = cfg->method;
7174 int max_epilog_size;
7176 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7177 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7179 max_epilog_size = get_max_epilog_size (cfg);
7181 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7182 cfg->code_size *= 2;
7183 cfg->native_code = mono_realloc_native_code (cfg);
7184 cfg->stat_code_reallocs++;
7186 code = cfg->native_code + cfg->code_len;
7188 cfg->has_unwind_info_for_epilog = TRUE;
7190 /* Mark the start of the epilog */
7191 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7193 /* Save the uwind state which is needed by the out-of-line code */
7194 mono_emit_unwind_op_remember_state (cfg, code);
7196 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7197 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7199 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7201 if (method->save_lmf) {
7202 /* check if we need to restore protection of the stack after a stack overflow */
7203 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7205 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7206 /* we load the value in a separate instruction: this mechanism may be
7207 * used later as a safer way to do thread interruption
7209 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7210 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7212 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7213 /* note that the call trampoline will preserve eax/edx */
7214 x86_call_reg (code, X86_ECX);
7215 x86_patch (patch, code);
7217 /* FIXME: maybe save the jit tls in the prolog */
7219 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7220 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7224 /* Restore callee saved regs */
7225 for (i = 0; i < AMD64_NREG; ++i) {
7226 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7227 /* Restore only used_int_regs, not arch.saved_iregs */
7228 if (cfg->used_int_regs & (1 << i)) {
7229 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7230 mono_emit_unwind_op_same_value (cfg, code, i);
7231 async_exc_point (code);
7233 save_area_offset += 8;
7237 /* Load returned vtypes into registers if needed */
7238 cinfo = cfg->arch.cinfo;
7239 if (cinfo->ret.storage == ArgValuetypeInReg) {
7240 ArgInfo *ainfo = &cinfo->ret;
7241 MonoInst *inst = cfg->ret;
7243 for (quad = 0; quad < 2; quad ++) {
7244 switch (ainfo->pair_storage [quad]) {
7246 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7248 case ArgInFloatSSEReg:
7249 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7251 case ArgInDoubleSSEReg:
7252 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7257 g_assert_not_reached ();
7262 if (cfg->arch.omit_fp) {
7263 if (cfg->arch.stack_alloc_size) {
7264 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7268 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7270 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7271 async_exc_point (code);
7274 /* Restore the unwind state to be the same as before the epilog */
7275 mono_emit_unwind_op_restore_state (cfg, code);
7277 cfg->code_len = code - cfg->native_code;
7279 g_assert (cfg->code_len < cfg->code_size);
7283 mono_arch_emit_exceptions (MonoCompile *cfg)
7285 MonoJumpInfo *patch_info;
7288 MonoClass *exc_classes [16];
7289 guint8 *exc_throw_start [16], *exc_throw_end [16];
7290 guint32 code_size = 0;
7292 /* Compute needed space */
7293 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7294 if (patch_info->type == MONO_PATCH_INFO_EXC)
7296 if (patch_info->type == MONO_PATCH_INFO_R8)
7297 code_size += 8 + 15; /* sizeof (double) + alignment */
7298 if (patch_info->type == MONO_PATCH_INFO_R4)
7299 code_size += 4 + 15; /* sizeof (float) + alignment */
7300 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7301 code_size += 8 + 7; /*sizeof (void*) + alignment */
7304 #ifdef __native_client_codegen__
7305 /* Give us extra room on Native Client. This could be */
7306 /* more carefully calculated, but bundle alignment makes */
7307 /* it much trickier, so *2 like other places is good. */
7311 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7312 cfg->code_size *= 2;
7313 cfg->native_code = mono_realloc_native_code (cfg);
7314 cfg->stat_code_reallocs++;
7317 code = cfg->native_code + cfg->code_len;
7319 /* add code to raise exceptions */
7321 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7322 switch (patch_info->type) {
7323 case MONO_PATCH_INFO_EXC: {
7324 MonoClass *exc_class;
7328 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7330 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7331 g_assert (exc_class);
7332 throw_ip = patch_info->ip.i;
7334 //x86_breakpoint (code);
7335 /* Find a throw sequence for the same exception class */
7336 for (i = 0; i < nthrows; ++i)
7337 if (exc_classes [i] == exc_class)
7340 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7341 x86_jump_code (code, exc_throw_start [i]);
7342 patch_info->type = MONO_PATCH_INFO_NONE;
7346 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7350 exc_classes [nthrows] = exc_class;
7351 exc_throw_start [nthrows] = code;
7353 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7355 patch_info->type = MONO_PATCH_INFO_NONE;
7357 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7359 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7364 exc_throw_end [nthrows] = code;
7374 g_assert(code < cfg->native_code + cfg->code_size);
7377 /* Handle relocations with RIP relative addressing */
7378 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7379 gboolean remove = FALSE;
7380 guint8 *orig_code = code;
7382 switch (patch_info->type) {
7383 case MONO_PATCH_INFO_R8:
7384 case MONO_PATCH_INFO_R4: {
7385 guint8 *pos, *patch_pos;
7388 /* The SSE opcodes require a 16 byte alignment */
7389 #if defined(__default_codegen__)
7390 code = (guint8*)ALIGN_TO (code, 16);
7391 #elif defined(__native_client_codegen__)
7393 /* Pad this out with HLT instructions */
7394 /* or we can get garbage bytes emitted */
7395 /* which will fail validation */
7396 guint8 *aligned_code;
7397 /* extra align to make room for */
7398 /* mov/push below */
7399 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7400 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7401 /* The technique of hiding data in an */
7402 /* instruction has a problem here: we */
7403 /* need the data aligned to a 16-byte */
7404 /* boundary but the instruction cannot */
7405 /* cross the bundle boundary. so only */
7406 /* odd multiples of 16 can be used */
7407 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7410 while (code < aligned_code) {
7411 *(code++) = 0xf4; /* hlt */
7416 pos = cfg->native_code + patch_info->ip.i;
7417 if (IS_REX (pos [1])) {
7418 patch_pos = pos + 5;
7419 target_pos = code - pos - 9;
7422 patch_pos = pos + 4;
7423 target_pos = code - pos - 8;
7426 if (patch_info->type == MONO_PATCH_INFO_R8) {
7427 #ifdef __native_client_codegen__
7428 /* Hide 64-bit data in a */
7429 /* "mov imm64, r11" instruction. */
7430 /* write it before the start of */
7432 *(code-2) = 0x49; /* prefix */
7433 *(code-1) = 0xbb; /* mov X, %r11 */
7435 *(double*)code = *(double*)patch_info->data.target;
7436 code += sizeof (double);
7438 #ifdef __native_client_codegen__
7439 /* Hide 32-bit data in a */
7440 /* "push imm32" instruction. */
7441 *(code-1) = 0x68; /* push */
7443 *(float*)code = *(float*)patch_info->data.target;
7444 code += sizeof (float);
7447 *(guint32*)(patch_pos) = target_pos;
7452 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7455 if (cfg->compile_aot)
7458 /*loading is faster against aligned addresses.*/
7459 code = (guint8*)ALIGN_TO (code, 8);
7460 memset (orig_code, 0, code - orig_code);
7462 pos = cfg->native_code + patch_info->ip.i;
7464 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7465 if (IS_REX (pos [1]))
7466 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7468 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7470 *(gpointer*)code = (gpointer)patch_info->data.target;
7471 code += sizeof (gpointer);
7481 if (patch_info == cfg->patch_info)
7482 cfg->patch_info = patch_info->next;
7486 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7488 tmp->next = patch_info->next;
7491 g_assert (code < cfg->native_code + cfg->code_size);
7494 cfg->code_len = code - cfg->native_code;
7496 g_assert (cfg->code_len < cfg->code_size);
7500 #endif /* DISABLE_JIT */
7503 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7506 MonoMethodSignature *sig;
7508 int i, n, stack_area = 0;
7510 /* Keep this in sync with mono_arch_get_argument_info */
7512 if (enable_arguments) {
7513 /* Allocate a new area on the stack and save arguments there */
7514 sig = mono_method_signature (cfg->method);
7516 n = sig->param_count + sig->hasthis;
7518 stack_area = ALIGN_TO (n * 8, 16);
7520 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7522 for (i = 0; i < n; ++i) {
7523 inst = cfg->args [i];
7525 if (inst->opcode == OP_REGVAR)
7526 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7528 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7529 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7534 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7535 amd64_set_reg_template (code, AMD64_ARG_REG1);
7536 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7537 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7539 if (enable_arguments)
7540 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7554 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7557 int save_mode = SAVE_NONE;
7558 MonoMethod *method = cfg->method;
7559 MonoType *ret_type = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
7562 switch (ret_type->type) {
7563 case MONO_TYPE_VOID:
7564 /* special case string .ctor icall */
7565 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7566 save_mode = SAVE_EAX;
7568 save_mode = SAVE_NONE;
7572 save_mode = SAVE_EAX;
7576 save_mode = SAVE_XMM;
7578 case MONO_TYPE_GENERICINST:
7579 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7580 save_mode = SAVE_EAX;
7584 case MONO_TYPE_VALUETYPE:
7585 save_mode = SAVE_STRUCT;
7588 save_mode = SAVE_EAX;
7592 /* Save the result and copy it into the proper argument register */
7593 switch (save_mode) {
7595 amd64_push_reg (code, AMD64_RAX);
7597 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7598 if (enable_arguments)
7599 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7603 if (enable_arguments)
7604 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7607 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7608 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7610 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7612 * The result is already in the proper argument register so no copying
7619 g_assert_not_reached ();
7622 /* Set %al since this is a varargs call */
7623 if (save_mode == SAVE_XMM)
7624 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7626 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7628 if (preserve_argument_registers) {
7629 for (i = 0; i < PARAM_REGS; ++i)
7630 amd64_push_reg (code, param_regs [i]);
7633 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7634 amd64_set_reg_template (code, AMD64_ARG_REG1);
7635 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7637 if (preserve_argument_registers) {
7638 for (i = PARAM_REGS - 1; i >= 0; --i)
7639 amd64_pop_reg (code, param_regs [i]);
7642 /* Restore result */
7643 switch (save_mode) {
7645 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7646 amd64_pop_reg (code, AMD64_RAX);
7652 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7653 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7654 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7659 g_assert_not_reached ();
7666 mono_arch_flush_icache (guint8 *code, gint size)
7672 mono_arch_flush_register_windows (void)
7677 mono_arch_is_inst_imm (gint64 imm)
7679 return amd64_is_imm32 (imm);
7683 * Determine whenever the trap whose info is in SIGINFO is caused by
7687 mono_arch_is_int_overflow (void *sigctx, void *info)
7694 mono_sigctx_to_monoctx (sigctx, &ctx);
7696 rip = (guint8*)ctx.gregs [AMD64_RIP];
7698 if (IS_REX (rip [0])) {
7699 reg = amd64_rex_b (rip [0]);
7705 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7707 reg += x86_modrm_rm (rip [1]);
7709 value = ctx.gregs [reg];
7719 mono_arch_get_patch_offset (guint8 *code)
7725 * mono_breakpoint_clean_code:
7727 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7728 * breakpoints in the original code, they are removed in the copy.
7730 * Returns TRUE if no sw breakpoint was present.
7733 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7736 * If method_start is non-NULL we need to perform bound checks, since we access memory
7737 * at code - offset we could go before the start of the method and end up in a different
7738 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7741 if (!method_start || code - offset >= method_start) {
7742 memcpy (buf, code - offset, size);
7744 int diff = code - method_start;
7745 memset (buf, 0, size);
7746 memcpy (buf + offset - diff, method_start, diff + size - offset);
7751 #if defined(__native_client_codegen__)
7752 /* For membase calls, we want the base register. for Native Client, */
7753 /* all indirect calls have the following sequence with the given sizes: */
7754 /* mov %eXX,%eXX [2-3] */
7755 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7756 /* and $0xffffffffffffffe0,%r11d [4] */
7757 /* add %r15,%r11 [3] */
7758 /* callq *%r11 [3] */
7761 /* Determine if code points to a NaCl call-through-register sequence, */
7762 /* (i.e., the last 3 instructions listed above) */
7764 is_nacl_call_reg_sequence(guint8* code)
7766 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7767 "\x4d\x03\xdf" /* add */
7768 "\x41\xff\xd3"; /* call */
7769 return memcmp(code, sequence, 10) == 0;
7772 /* Determine if code points to the first opcode of the mov membase component */
7773 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7774 /* (there could be a REX prefix before the opcode but it is ignored) */
7776 is_nacl_indirect_call_membase_sequence(guint8* code)
7778 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7779 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7780 /* and that src reg = dest reg */
7781 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7782 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7784 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7785 /* and has dst of r11 and base of r15 */
7786 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7787 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7789 #endif /* __native_client_codegen__ */
7792 mono_arch_get_this_arg_reg (guint8 *code)
7794 return AMD64_ARG_REG1;
7798 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7800 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7803 #define MAX_ARCH_DELEGATE_PARAMS 10
7806 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7808 guint8 *code, *start;
7812 start = code = mono_global_codeman_reserve (64);
7814 /* Replace the this argument with the target */
7815 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7816 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7817 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7819 g_assert ((code - start) < 64);
7821 start = code = mono_global_codeman_reserve (64);
7823 if (param_count == 0) {
7824 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7826 /* We have to shift the arguments left */
7827 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7828 for (i = 0; i < param_count; ++i) {
7831 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7833 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7835 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7839 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7841 g_assert ((code - start) < 64);
7844 nacl_global_codeman_validate (&start, 64, &code);
7845 mono_arch_flush_icache (start, code - start);
7848 *code_len = code - start;
7850 if (mono_jit_map_is_enabled ()) {
7853 buff = (char*)"delegate_invoke_has_target";
7855 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7856 mono_emit_jit_tramp (start, code - start, buff);
7860 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7865 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7868 get_delegate_virtual_invoke_impl (gboolean load_imt_reg, int offset, guint32 *code_len)
7870 guint8 *code, *start;
7873 if (offset / sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7876 start = code = mono_global_codeman_reserve (size);
7878 /* Replace the this argument with the target */
7879 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7880 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7883 /* Load the IMT reg */
7884 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7887 /* Load the vtable */
7888 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7889 amd64_jump_membase (code, AMD64_RAX, offset);
7890 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7893 *code_len = code - start;
7899 * mono_arch_get_delegate_invoke_impls:
7901 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7905 mono_arch_get_delegate_invoke_impls (void)
7913 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7914 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7916 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7917 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7918 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7919 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7920 g_free (tramp_name);
7923 for (i = 0; i < MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7924 code = get_delegate_virtual_invoke_impl (TRUE, i * SIZEOF_VOID_P, &code_len);
7925 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", i);
7926 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7927 g_free (tramp_name);
7929 code = get_delegate_virtual_invoke_impl (FALSE, i * SIZEOF_VOID_P, &code_len);
7930 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", i);
7931 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7932 g_free (tramp_name);
7939 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7941 guint8 *code, *start;
7944 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7947 /* FIXME: Support more cases */
7948 if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7952 static guint8* cached = NULL;
7958 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7960 start = get_delegate_invoke_impl (TRUE, 0, NULL);
7962 mono_memory_barrier ();
7966 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7967 for (i = 0; i < sig->param_count; ++i)
7968 if (!mono_is_regsize_var (sig->params [i]))
7970 if (sig->param_count > 4)
7973 code = cache [sig->param_count];
7977 if (mono_aot_only) {
7978 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7979 start = mono_aot_get_trampoline (name);
7982 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7985 mono_memory_barrier ();
7987 cache [sig->param_count] = start;
7994 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7996 return get_delegate_virtual_invoke_impl (load_imt_reg, offset, NULL);
8000 mono_arch_finish_init (void)
8002 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8003 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8008 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8012 #if defined(__default_codegen__)
8013 #define CMP_SIZE (6 + 1)
8014 #define CMP_REG_REG_SIZE (4 + 1)
8015 #define BR_SMALL_SIZE 2
8016 #define BR_LARGE_SIZE 6
8017 #define MOV_REG_IMM_SIZE 10
8018 #define MOV_REG_IMM_32BIT_SIZE 6
8019 #define JUMP_REG_SIZE (2 + 1)
8020 #elif defined(__native_client_codegen__)
8021 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8022 #define CMP_SIZE ((6 + 1) * 2 - 1)
8023 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8024 #define BR_SMALL_SIZE (2 * 2 - 1)
8025 #define BR_LARGE_SIZE (6 * 2 - 1)
8026 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8027 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8028 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8029 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8030 /* Jump membase's size is large and unpredictable */
8031 /* in native client, just pad it out a whole bundle. */
8032 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8036 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8038 int i, distance = 0;
8039 for (i = start; i < target; ++i)
8040 distance += imt_entries [i]->chunk_size;
8045 * LOCKING: called with the domain lock held
8048 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8049 gpointer fail_tramp)
8053 guint8 *code, *start;
8054 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8056 for (i = 0; i < count; ++i) {
8057 MonoIMTCheckItem *item = imt_entries [i];
8058 if (item->is_equals) {
8059 if (item->check_target_idx) {
8060 if (!item->compare_done) {
8061 if (amd64_is_imm32 (item->key))
8062 item->chunk_size += CMP_SIZE;
8064 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8066 if (item->has_target_code) {
8067 item->chunk_size += MOV_REG_IMM_SIZE;
8069 if (vtable_is_32bit)
8070 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8072 item->chunk_size += MOV_REG_IMM_SIZE;
8073 #ifdef __native_client_codegen__
8074 item->chunk_size += JUMP_MEMBASE_SIZE;
8077 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8080 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8081 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8083 if (vtable_is_32bit)
8084 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8086 item->chunk_size += MOV_REG_IMM_SIZE;
8087 item->chunk_size += JUMP_REG_SIZE;
8088 /* with assert below:
8089 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8091 #ifdef __native_client_codegen__
8092 item->chunk_size += JUMP_MEMBASE_SIZE;
8097 if (amd64_is_imm32 (item->key))
8098 item->chunk_size += CMP_SIZE;
8100 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8101 item->chunk_size += BR_LARGE_SIZE;
8102 imt_entries [item->check_target_idx]->compare_done = TRUE;
8104 size += item->chunk_size;
8106 #if defined(__native_client__) && defined(__native_client_codegen__)
8107 /* In Native Client, we don't re-use thunks, allocate from the */
8108 /* normal code manager paths. */
8109 code = mono_domain_code_reserve (domain, size);
8112 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8114 code = mono_domain_code_reserve (domain, size);
8117 for (i = 0; i < count; ++i) {
8118 MonoIMTCheckItem *item = imt_entries [i];
8119 item->code_target = code;
8120 if (item->is_equals) {
8121 gboolean fail_case = !item->check_target_idx && fail_tramp;
8123 if (item->check_target_idx || fail_case) {
8124 if (!item->compare_done || fail_case) {
8125 if (amd64_is_imm32 (item->key))
8126 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8128 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8129 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8132 item->jmp_code = code;
8133 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8134 if (item->has_target_code) {
8135 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8136 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8138 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8139 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8143 amd64_patch (item->jmp_code, code);
8144 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8145 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8146 item->jmp_code = NULL;
8149 /* enable the commented code to assert on wrong method */
8151 if (amd64_is_imm32 (item->key))
8152 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8154 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8155 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8157 item->jmp_code = code;
8158 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8159 /* See the comment below about R10 */
8160 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8161 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8162 amd64_patch (item->jmp_code, code);
8163 amd64_breakpoint (code);
8164 item->jmp_code = NULL;
8166 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8167 needs to be preserved. R10 needs
8168 to be preserved for calls which
8169 require a runtime generic context,
8170 but interface calls don't. */
8171 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8172 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8176 if (amd64_is_imm32 (item->key))
8177 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8179 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8180 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8182 item->jmp_code = code;
8183 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8184 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8186 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8188 g_assert (code - item->code_target <= item->chunk_size);
8190 /* patch the branches to get to the target items */
8191 for (i = 0; i < count; ++i) {
8192 MonoIMTCheckItem *item = imt_entries [i];
8193 if (item->jmp_code) {
8194 if (item->check_target_idx) {
8195 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8201 mono_stats.imt_thunks_size += code - start;
8202 g_assert (code - start <= size);
8204 nacl_domain_code_validate(domain, &start, size, &code);
8205 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8211 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8213 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8217 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8219 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8223 mono_arch_get_cie_program (void)
8227 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8228 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8236 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8238 MonoInst *ins = NULL;
8241 if (cmethod->klass == mono_defaults.math_class) {
8242 if (strcmp (cmethod->name, "Sin") == 0) {
8244 } else if (strcmp (cmethod->name, "Cos") == 0) {
8246 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8248 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8252 if (opcode && fsig->param_count == 1) {
8253 MONO_INST_NEW (cfg, ins, opcode);
8254 ins->type = STACK_R8;
8255 ins->dreg = mono_alloc_freg (cfg);
8256 ins->sreg1 = args [0]->dreg;
8257 MONO_ADD_INS (cfg->cbb, ins);
8261 if (cfg->opt & MONO_OPT_CMOV) {
8262 if (strcmp (cmethod->name, "Min") == 0) {
8263 if (fsig->params [0]->type == MONO_TYPE_I4)
8265 if (fsig->params [0]->type == MONO_TYPE_U4)
8266 opcode = OP_IMIN_UN;
8267 else if (fsig->params [0]->type == MONO_TYPE_I8)
8269 else if (fsig->params [0]->type == MONO_TYPE_U8)
8270 opcode = OP_LMIN_UN;
8271 } else if (strcmp (cmethod->name, "Max") == 0) {
8272 if (fsig->params [0]->type == MONO_TYPE_I4)
8274 if (fsig->params [0]->type == MONO_TYPE_U4)
8275 opcode = OP_IMAX_UN;
8276 else if (fsig->params [0]->type == MONO_TYPE_I8)
8278 else if (fsig->params [0]->type == MONO_TYPE_U8)
8279 opcode = OP_LMAX_UN;
8283 if (opcode && fsig->param_count == 2) {
8284 MONO_INST_NEW (cfg, ins, opcode);
8285 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8286 ins->dreg = mono_alloc_ireg (cfg);
8287 ins->sreg1 = args [0]->dreg;
8288 ins->sreg2 = args [1]->dreg;
8289 MONO_ADD_INS (cfg->cbb, ins);
8293 /* OP_FREM is not IEEE compatible */
8294 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8295 MONO_INST_NEW (cfg, ins, OP_FREM);
8296 ins->inst_i0 = args [0];
8297 ins->inst_i1 = args [1];
8307 mono_arch_print_tree (MonoInst *tree, int arity)
8313 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8315 return ctx->gregs [reg];
8319 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8321 ctx->gregs [reg] = val;
8325 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8327 gpointer *sp, old_value;
8331 bp = MONO_CONTEXT_GET_BP (ctx);
8332 sp = *(gpointer*)(bp + clause->exvar_offset);
8335 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8344 * mono_arch_emit_load_aotconst:
8346 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8347 * TARGET from the mscorlib GOT in full-aot code.
8348 * On AMD64, the result is placed into R11.
8351 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8353 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8354 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8360 * mono_arch_get_trampolines:
8362 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8366 mono_arch_get_trampolines (gboolean aot)
8368 return mono_amd64_get_exception_trampolines (aot);
8371 /* Soft Debug support */
8372 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8375 * mono_arch_set_breakpoint:
8377 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8378 * The location should contain code emitted by OP_SEQ_POINT.
8381 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8384 guint8 *orig_code = code;
8387 guint32 native_offset = ip - (guint8*)ji->code_start;
8388 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8390 g_assert (info->bp_addrs [native_offset] == 0);
8391 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8394 * In production, we will use int3 (has to fix the size in the md
8395 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8398 g_assert (code [0] == 0x90);
8399 if (breakpoint_size == 8) {
8400 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8402 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8403 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8406 g_assert (code - orig_code == breakpoint_size);
8411 * mono_arch_clear_breakpoint:
8413 * Clear the breakpoint at IP.
8416 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8422 guint32 native_offset = ip - (guint8*)ji->code_start;
8423 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8425 info->bp_addrs [native_offset] = NULL;
8427 for (i = 0; i < breakpoint_size; ++i)
8433 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8436 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8437 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8442 siginfo_t* sinfo = (siginfo_t*) info;
8443 /* Sometimes the address is off by 4 */
8444 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8452 * mono_arch_skip_breakpoint:
8454 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8455 * we resume, the instruction is not executed again.
8458 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8461 /* The breakpoint instruction is a call */
8463 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8468 * mono_arch_start_single_stepping:
8470 * Start single stepping.
8473 mono_arch_start_single_stepping (void)
8475 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8476 ss_trampoline = mini_get_single_step_trampoline ();
8480 * mono_arch_stop_single_stepping:
8482 * Stop single stepping.
8485 mono_arch_stop_single_stepping (void)
8487 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8488 ss_trampoline = NULL;
8492 * mono_arch_is_single_step_event:
8494 * Return whenever the machine state in SIGCTX corresponds to a single
8498 mono_arch_is_single_step_event (void *info, void *sigctx)
8501 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8502 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8507 siginfo_t* sinfo = (siginfo_t*) info;
8508 /* Sometimes the address is off by 4 */
8509 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8517 * mono_arch_skip_single_step:
8519 * Modify CTX so the ip is placed after the single step trigger instruction,
8520 * we resume, the instruction is not executed again.
8523 mono_arch_skip_single_step (MonoContext *ctx)
8525 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8529 * mono_arch_create_seq_point_info:
8531 * Return a pointer to a data structure which is used by the sequence
8532 * point implementation in AOTed code.
8535 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8540 // FIXME: Add a free function
8542 mono_domain_lock (domain);
8543 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8545 mono_domain_unlock (domain);
8548 ji = mono_jit_info_table_find (domain, (char*)code);
8551 // FIXME: Optimize the size
8552 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8554 info->ss_tramp_addr = &ss_trampoline;
8556 mono_domain_lock (domain);
8557 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8559 mono_domain_unlock (domain);
8566 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8568 ext->lmf.previous_lmf = prev_lmf;
8569 /* Mark that this is a MonoLMFExt */
8570 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8571 ext->lmf.rsp = (gssize)ext;
8577 mono_arch_opcode_supported (int opcode)
8580 case OP_ATOMIC_ADD_I4:
8581 case OP_ATOMIC_ADD_I8:
8582 case OP_ATOMIC_EXCHANGE_I4:
8583 case OP_ATOMIC_EXCHANGE_I8:
8584 case OP_ATOMIC_CAS_I4:
8585 case OP_ATOMIC_CAS_I8:
8586 case OP_ATOMIC_LOAD_I1:
8587 case OP_ATOMIC_LOAD_I2:
8588 case OP_ATOMIC_LOAD_I4:
8589 case OP_ATOMIC_LOAD_I8:
8590 case OP_ATOMIC_LOAD_U1:
8591 case OP_ATOMIC_LOAD_U2:
8592 case OP_ATOMIC_LOAD_U4:
8593 case OP_ATOMIC_LOAD_U8:
8594 case OP_ATOMIC_LOAD_R4:
8595 case OP_ATOMIC_LOAD_R8:
8596 case OP_ATOMIC_STORE_I1:
8597 case OP_ATOMIC_STORE_I2:
8598 case OP_ATOMIC_STORE_I4:
8599 case OP_ATOMIC_STORE_I8:
8600 case OP_ATOMIC_STORE_U1:
8601 case OP_ATOMIC_STORE_U2:
8602 case OP_ATOMIC_STORE_U4:
8603 case OP_ATOMIC_STORE_U8:
8604 case OP_ATOMIC_STORE_R4:
8605 case OP_ATOMIC_STORE_R8: