mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/metadata/gc-internal.h>
  27 #include <mono/utils/mono-math.h>
  28 #include <mono/utils/mono-mmap.h>
  29
  30 #include "trace.h"
  31 #include "ir-emit.h"
  32 #include "mini-amd64.h"
  33 #include "cpu-amd64.h"
  34 #include "debugger-agent.h"
  35
  36 static gint lmf_tls_offset = -1;
  37 static gint lmf_addr_tls_offset = -1;
  38 static gint appdomain_tls_offset = -1;
  39
  40 #ifdef MONO_XEN_OPT
  41 static gboolean optimize_for_xen = TRUE;
  42 #else
  43 #define optimize_for_xen 0
  44 #endif
  45
  46 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  47
  48 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  49
  50 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  51
  52 #ifdef HOST_WIN32
  53 /* Under windows, the calling convention is never stdcall */
  54 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  55 #else
  56 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  57 #endif
  58
  59 /* This mutex protects architecture specific caches */
  60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  62 static CRITICAL_SECTION mini_arch_mutex;
  63
  64 MonoBreakpointInfo
  65 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  66
  67 /*
  68  * The code generated for sequence points reads from this location, which is
  69  * made read-only when single stepping is enabled.
  70  */
  71 static gpointer ss_trigger_page;
  72
  73 /* Enabled breakpoints read from this trigger page */
  74 static gpointer bp_trigger_page;
  75
  76 /* The size of the breakpoint sequence */
  77 static int breakpoint_size;
  78
  79 /* The size of the breakpoint instruction causing the actual fault */
  80 static int breakpoint_fault_size;
  81
  82 /* The size of the single step instruction causing the actual fault */
  83 static int single_step_fault_size;
  84
  85 #ifdef HOST_WIN32
  86 /* On Win64 always reserve first 32 bytes for first four arguments */
  87 #define ARGS_OFFSET 48
  88 #else
  89 #define ARGS_OFFSET 16
  90 #endif
  91 #define GP_SCRATCH_REG AMD64_R11
  92
  93 /*
  94  * AMD64 register usage:
  95  * - callee saved registers are used for global register allocation
  96  * - %r11 is used for materializing 64 bit constants in opcodes
  97  * - the rest is used for local allocation
  98  */
  99
 100 /*
 101  * Floating point comparison results:
 102  *                  ZF PF CF
 103  * A > B            0  0  0
 104  * A < B            0  0  1
 105  * A = B            1  0  0
 106  * A > B            0  0  0
 107  * UNORDERED        1  1  1
 108  */
 109
 110 const char*
 111 mono_arch_regname (int reg)
 112 {
 113         switch (reg) {
 114         case AMD64_RAX: return "%rax";
 115         case AMD64_RBX: return "%rbx";
 116         case AMD64_RCX: return "%rcx";
 117         case AMD64_RDX: return "%rdx";
 118         case AMD64_RSP: return "%rsp";
 119         case AMD64_RBP: return "%rbp";
 120         case AMD64_RDI: return "%rdi";
 121         case AMD64_RSI: return "%rsi";
 122         case AMD64_R8: return "%r8";
 123         case AMD64_R9: return "%r9";
 124         case AMD64_R10: return "%r10";
 125         case AMD64_R11: return "%r11";
 126         case AMD64_R12: return "%r12";
 127         case AMD64_R13: return "%r13";
 128         case AMD64_R14: return "%r14";
 129         case AMD64_R15: return "%r15";
 130         }
 131         return "unknown";
 132 }
 133
 134 static const char * packed_xmmregs [] = {
 135         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 136         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 137 };
 138
 139 static const char * single_xmmregs [] = {
 140         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 141         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 142 };
 143
 144 const char*
 145 mono_arch_fregname (int reg)
 146 {
 147         if (reg < AMD64_XMM_NREG)
 148                 return single_xmmregs [reg];
 149         else
 150                 return "unknown";
 151 }
 152
 153 const char *
 154 mono_arch_xregname (int reg)
 155 {
 156         if (reg < AMD64_XMM_NREG)
 157                 return packed_xmmregs [reg];
 158         else
 159                 return "unknown";
 160 }
 161
 162 G_GNUC_UNUSED static void
 163 break_count (void)
 164 {
 165 }
 166
 167 G_GNUC_UNUSED static gboolean
 168 debug_count (void)
 169 {
 170         static int count = 0;
 171         count ++;
 172
 173         if (!getenv ("COUNT"))
 174                 return TRUE;
 175
 176         if (count == atoi (getenv ("COUNT"))) {
 177                 break_count ();
 178         }
 179
 180         if (count > atoi (getenv ("COUNT"))) {
 181                 return FALSE;
 182         }
 183
 184         return TRUE;
 185 }
 186
 187 static gboolean
 188 debug_omit_fp (void)
 189 {
 190 #if 0
 191         return debug_count ();
 192 #else
 193         return TRUE;
 194 #endif
 195 }
 196
 197 static inline gboolean
 198 amd64_is_near_call (guint8 *code)
 199 {
 200         /* Skip REX */
 201         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 202                 code += 1;
 203
 204         return code [0] == 0xe8;
 205 }
 206
 207 static inline void
 208 amd64_patch (unsigned char* code, gpointer target)
 209 {
 210         guint8 rex = 0;
 211
 212         /* Skip REX */
 213         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 214                 rex = code [0];
 215                 code += 1;
 216         }
 217
 218         if ((code [0] & 0xf8) == 0xb8) {
 219                 /* amd64_set_reg_template */
 220                 *(guint64*)(code + 1) = (guint64)target;
 221         }
 222         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 223                 /* mov 0(%rip), %dreg */
 224                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 225         }
 226         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 227                 /* call *<OFFSET>(%rip) */
 228                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 229         }
 230         else if ((code [0] == 0xe8)) {
 231                 /* call <DISP> */
 232                 gint64 disp = (guint8*)target - (guint8*)code;
 233                 g_assert (amd64_is_imm32 (disp));
 234                 x86_patch (code, (unsigned char*)target);
 235         }
 236         else
 237                 x86_patch (code, (unsigned char*)target);
 238 }
 239
 240 void
 241 mono_amd64_patch (unsigned char* code, gpointer target)
 242 {
 243         amd64_patch (code, target);
 244 }
 245
 246 typedef enum {
 247         ArgInIReg,
 248         ArgInFloatSSEReg,
 249         ArgInDoubleSSEReg,
 250         ArgOnStack,
 251         ArgValuetypeInReg,
 252         ArgValuetypeAddrInIReg,
 253         ArgNone /* only in pair_storage */
 254 } ArgStorage;
 255
 256 typedef struct {
 257         gint16 offset;
 258         gint8  reg;
 259         ArgStorage storage;
 260
 261         /* Only if storage == ArgValuetypeInReg */
 262         ArgStorage pair_storage [2];
 263         gint8 pair_regs [2];
 264 } ArgInfo;
 265
 266 typedef struct {
 267         int nargs;
 268         guint32 stack_usage;
 269         guint32 reg_usage;
 270         guint32 freg_usage;
 271         gboolean need_stack_align;
 272         gboolean vtype_retaddr;
 273         /* The index of the vret arg in the argument list */
 274         int vret_arg_index;
 275         ArgInfo ret;
 276         ArgInfo sig_cookie;
 277         ArgInfo args [1];
 278 } CallInfo;
 279
 280 #define DEBUG(a) if (cfg->verbose_level > 1) a
 281
 282 #ifdef HOST_WIN32
 283 #define PARAM_REGS 4
 284
 285 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 286
 287 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 288 #else
 289 #define PARAM_REGS 6
 290
 291 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 292
 293  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 294 #endif
 295
 296 static void inline
 297 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 298 {
 299     ainfo->offset = *stack_size;
 300
 301     if (*gr >= PARAM_REGS) {
 302                 ainfo->storage = ArgOnStack;
 303                 (*stack_size) += sizeof (gpointer);
 304     }
 305     else {
 306                 ainfo->storage = ArgInIReg;
 307                 ainfo->reg = param_regs [*gr];
 308                 (*gr) ++;
 309     }
 310 }
 311
 312 #ifdef HOST_WIN32
 313 #define FLOAT_PARAM_REGS 4
 314 #else
 315 #define FLOAT_PARAM_REGS 8
 316 #endif
 317
 318 static void inline
 319 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 320 {
 321     ainfo->offset = *stack_size;
 322
 323     if (*gr >= FLOAT_PARAM_REGS) {
 324                 ainfo->storage = ArgOnStack;
 325                 (*stack_size) += sizeof (gpointer);
 326     }
 327     else {
 328                 /* A double register */
 329                 if (is_double)
 330                         ainfo->storage = ArgInDoubleSSEReg;
 331                 else
 332                         ainfo->storage = ArgInFloatSSEReg;
 333                 ainfo->reg = *gr;
 334                 (*gr) += 1;
 335     }
 336 }
 337
 338 typedef enum ArgumentClass {
 339         ARG_CLASS_NO_CLASS,
 340         ARG_CLASS_MEMORY,
 341         ARG_CLASS_INTEGER,
 342         ARG_CLASS_SSE
 343 } ArgumentClass;
 344
 345 static ArgumentClass
 346 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 347 {
 348         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 349         MonoType *ptype;
 350
 351         ptype = mini_type_get_underlying_type (NULL, type);
 352         switch (ptype->type) {
 353         case MONO_TYPE_BOOLEAN:
 354         case MONO_TYPE_CHAR:
 355         case MONO_TYPE_I1:
 356         case MONO_TYPE_U1:
 357         case MONO_TYPE_I2:
 358         case MONO_TYPE_U2:
 359         case MONO_TYPE_I4:
 360         case MONO_TYPE_U4:
 361         case MONO_TYPE_I:
 362         case MONO_TYPE_U:
 363         case MONO_TYPE_STRING:
 364         case MONO_TYPE_OBJECT:
 365         case MONO_TYPE_CLASS:
 366         case MONO_TYPE_SZARRAY:
 367         case MONO_TYPE_PTR:
 368         case MONO_TYPE_FNPTR:
 369         case MONO_TYPE_ARRAY:
 370         case MONO_TYPE_I8:
 371         case MONO_TYPE_U8:
 372                 class2 = ARG_CLASS_INTEGER;
 373                 break;
 374         case MONO_TYPE_R4:
 375         case MONO_TYPE_R8:
 376 #ifdef HOST_WIN32
 377                 class2 = ARG_CLASS_INTEGER;
 378 #else
 379                 class2 = ARG_CLASS_SSE;
 380 #endif
 381                 break;
 382
 383         case MONO_TYPE_TYPEDBYREF:
 384                 g_assert_not_reached ();
 385
 386         case MONO_TYPE_GENERICINST:
 387                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 388                         class2 = ARG_CLASS_INTEGER;
 389                         break;
 390                 }
 391                 /* fall through */
 392         case MONO_TYPE_VALUETYPE: {
 393                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 394                 int i;
 395
 396                 for (i = 0; i < info->num_fields; ++i) {
 397                         class2 = class1;
 398                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 399                 }
 400                 break;
 401         }
 402         default:
 403                 g_assert_not_reached ();
 404         }
 405
 406         /* Merge */
 407         if (class1 == class2)
 408                 ;
 409         else if (class1 == ARG_CLASS_NO_CLASS)
 410                 class1 = class2;
 411         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 412                 class1 = ARG_CLASS_MEMORY;
 413         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 414                 class1 = ARG_CLASS_INTEGER;
 415         else
 416                 class1 = ARG_CLASS_SSE;
 417
 418         return class1;
 419 }
 420
 421 static void
 422 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 423                            gboolean is_return,
 424                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 425 {
 426         guint32 size, quad, nquads, i;
 427         ArgumentClass args [2];
 428         MonoMarshalType *info = NULL;
 429         MonoClass *klass;
 430         MonoGenericSharingContext tmp_gsctx;
 431         gboolean pass_on_stack = FALSE;
 432
 433         /*
 434          * The gsctx currently contains no data, it is only used for checking whenever
 435          * open types are allowed, some callers like mono_arch_get_argument_info ()
 436          * don't pass it to us, so work around that.
 437          */
 438         if (!gsctx)
 439                 gsctx = &tmp_gsctx;
 440
 441         klass = mono_class_from_mono_type (type);
 442         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 443 #ifndef HOST_WIN32
 444         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 445                 /* We pass and return vtypes of size 8 in a register */
 446         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 447                 pass_on_stack = TRUE;
 448         }
 449 #else
 450         if (!sig->pinvoke) {
 451                 pass_on_stack = TRUE;
 452         }
 453 #endif
 454
 455         if (pass_on_stack) {
 456                 /* Allways pass in memory */
 457                 ainfo->offset = *stack_size;
 458                 *stack_size += ALIGN_TO (size, 8);
 459                 ainfo->storage = ArgOnStack;
 460
 461                 return;
 462         }
 463
 464         /* FIXME: Handle structs smaller than 8 bytes */
 465         //if ((size % 8) != 0)
 466         //      NOT_IMPLEMENTED;
 467
 468         if (size > 8)
 469                 nquads = 2;
 470         else
 471                 nquads = 1;
 472
 473         if (!sig->pinvoke) {
 474                 /* Always pass in 1 or 2 integer registers */
 475                 args [0] = ARG_CLASS_INTEGER;
 476                 args [1] = ARG_CLASS_INTEGER;
 477                 /* Only the simplest cases are supported */
 478                 if (is_return && nquads != 1) {
 479                         args [0] = ARG_CLASS_MEMORY;
 480                         args [1] = ARG_CLASS_MEMORY;
 481                 }
 482         } else {
 483                 /*
 484                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 485                  * The X87 and SSEUP stuff is left out since there are no such types in
 486                  * the CLR.
 487                  */
 488                 info = mono_marshal_load_type_info (klass);
 489                 g_assert (info);
 490
 491 #ifndef HOST_WIN32
 492                 if (info->native_size > 16) {
 493                         ainfo->offset = *stack_size;
 494                         *stack_size += ALIGN_TO (info->native_size, 8);
 495                         ainfo->storage = ArgOnStack;
 496
 497                         return;
 498                 }
 499 #else
 500                 switch (info->native_size) {
 501                 case 1: case 2: case 4: case 8:
 502                         break;
 503                 default:
 504                         if (is_return) {
 505                                 ainfo->storage = ArgOnStack;
 506                                 ainfo->offset = *stack_size;
 507                                 *stack_size += ALIGN_TO (info->native_size, 8);
 508                         }
 509                         else {
 510                                 ainfo->storage = ArgValuetypeAddrInIReg;
 511
 512                                 if (*gr < PARAM_REGS) {
 513                                         ainfo->pair_storage [0] = ArgInIReg;
 514                                         ainfo->pair_regs [0] = param_regs [*gr];
 515                                         (*gr) ++;
 516                                 }
 517                                 else {
 518                                         ainfo->pair_storage [0] = ArgOnStack;
 519                                         ainfo->offset = *stack_size;
 520                                         *stack_size += 8;
 521                                 }
 522                         }
 523
 524                         return;
 525                 }
 526 #endif
 527
 528                 args [0] = ARG_CLASS_NO_CLASS;
 529                 args [1] = ARG_CLASS_NO_CLASS;
 530                 for (quad = 0; quad < nquads; ++quad) {
 531                         int size;
 532                         guint32 align;
 533                         ArgumentClass class1;
 534
 535                         if (info->num_fields == 0)
 536                                 class1 = ARG_CLASS_MEMORY;
 537                         else
 538                                 class1 = ARG_CLASS_NO_CLASS;
 539                         for (i = 0; i < info->num_fields; ++i) {
 540                                 size = mono_marshal_type_size (info->fields [i].field->type,
 541                                                                                            info->fields [i].mspec,
 542                                                                                            &align, TRUE, klass->unicode);
 543                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 544                                         /* Unaligned field */
 545                                         NOT_IMPLEMENTED;
 546                                 }
 547
 548                                 /* Skip fields in other quad */
 549                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 550                                         continue;
 551                                 if ((quad == 1) && (info->fields [i].offset < 8))
 552                                         continue;
 553
 554                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 555                         }
 556                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 557                         args [quad] = class1;
 558                 }
 559         }
 560
 561         /* Post merger cleanup */
 562         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 563                 args [0] = args [1] = ARG_CLASS_MEMORY;
 564
 565         /* Allocate registers */
 566         {
 567                 int orig_gr = *gr;
 568                 int orig_fr = *fr;
 569
 570                 ainfo->storage = ArgValuetypeInReg;
 571                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 572                 for (quad = 0; quad < nquads; ++quad) {
 573                         switch (args [quad]) {
 574                         case ARG_CLASS_INTEGER:
 575                                 if (*gr >= PARAM_REGS)
 576                                         args [quad] = ARG_CLASS_MEMORY;
 577                                 else {
 578                                         ainfo->pair_storage [quad] = ArgInIReg;
 579                                         if (is_return)
 580                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 581                                         else
 582                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 583                                         (*gr) ++;
 584                                 }
 585                                 break;
 586                         case ARG_CLASS_SSE:
 587                                 if (*fr >= FLOAT_PARAM_REGS)
 588                                         args [quad] = ARG_CLASS_MEMORY;
 589                                 else {
 590                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 591                                         ainfo->pair_regs [quad] = *fr;
 592                                         (*fr) ++;
 593                                 }
 594                                 break;
 595                         case ARG_CLASS_MEMORY:
 596                                 break;
 597                         default:
 598                                 g_assert_not_reached ();
 599                         }
 600                 }
 601
 602                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 603                         /* Revert possible register assignments */
 604                         *gr = orig_gr;
 605                         *fr = orig_fr;
 606
 607                         ainfo->offset = *stack_size;
 608                         if (sig->pinvoke)
 609                                 *stack_size += ALIGN_TO (info->native_size, 8);
 610                         else
 611                                 *stack_size += nquads * sizeof (gpointer);
 612                         ainfo->storage = ArgOnStack;
 613                 }
 614         }
 615 }
 616
 617 /*
 618  * get_call_info:
 619  *
 620  *  Obtain information about a call according to the calling convention.
 621  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 622  * Draft Version 0.23" document for more information.
 623  */
 624 static CallInfo*
 625 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 626 {
 627         guint32 i, gr, fr, pstart;
 628         MonoType *ret_type;
 629         int n = sig->hasthis + sig->param_count;
 630         guint32 stack_size = 0;
 631         CallInfo *cinfo;
 632
 633         if (mp)
 634                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 635         else
 636                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 637
 638         cinfo->nargs = n;
 639
 640         gr = 0;
 641         fr = 0;
 642
 643         /* return value */
 644         {
 645                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 646                 switch (ret_type->type) {
 647                 case MONO_TYPE_BOOLEAN:
 648                 case MONO_TYPE_I1:
 649                 case MONO_TYPE_U1:
 650                 case MONO_TYPE_I2:
 651                 case MONO_TYPE_U2:
 652                 case MONO_TYPE_CHAR:
 653                 case MONO_TYPE_I4:
 654                 case MONO_TYPE_U4:
 655                 case MONO_TYPE_I:
 656                 case MONO_TYPE_U:
 657                 case MONO_TYPE_PTR:
 658                 case MONO_TYPE_FNPTR:
 659                 case MONO_TYPE_CLASS:
 660                 case MONO_TYPE_OBJECT:
 661                 case MONO_TYPE_SZARRAY:
 662                 case MONO_TYPE_ARRAY:
 663                 case MONO_TYPE_STRING:
 664                         cinfo->ret.storage = ArgInIReg;
 665                         cinfo->ret.reg = AMD64_RAX;
 666                         break;
 667                 case MONO_TYPE_U8:
 668                 case MONO_TYPE_I8:
 669                         cinfo->ret.storage = ArgInIReg;
 670                         cinfo->ret.reg = AMD64_RAX;
 671                         break;
 672                 case MONO_TYPE_R4:
 673                         cinfo->ret.storage = ArgInFloatSSEReg;
 674                         cinfo->ret.reg = AMD64_XMM0;
 675                         break;
 676                 case MONO_TYPE_R8:
 677                         cinfo->ret.storage = ArgInDoubleSSEReg;
 678                         cinfo->ret.reg = AMD64_XMM0;
 679                         break;
 680                 case MONO_TYPE_GENERICINST:
 681                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 682                                 cinfo->ret.storage = ArgInIReg;
 683                                 cinfo->ret.reg = AMD64_RAX;
 684                                 break;
 685                         }
 686                         /* fall through */
 687                 case MONO_TYPE_VALUETYPE: {
 688                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 689
 690                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 691                         if (cinfo->ret.storage == ArgOnStack) {
 692                                 cinfo->vtype_retaddr = TRUE;
 693                                 /* The caller passes the address where the value is stored */
 694                         }
 695                         break;
 696                 }
 697                 case MONO_TYPE_TYPEDBYREF:
 698                         /* Same as a valuetype with size 24 */
 699                         cinfo->vtype_retaddr = TRUE;
 700                         break;
 701                 case MONO_TYPE_VOID:
 702                         break;
 703                 default:
 704                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 705                 }
 706         }
 707
 708         pstart = 0;
 709         /*
 710          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 711          * the first argument, allowing 'this' to be always passed in the first arg reg.
 712          * Also do this if the first argument is a reference type, since virtual calls
 713          * are sometimes made using calli without sig->hasthis set, like in the delegate
 714          * invoke wrappers.
 715          */
 716         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
 717                 if (sig->hasthis) {
 718                         add_general (&gr, &stack_size, cinfo->args + 0);
 719                 } else {
 720                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 721                         pstart = 1;
 722                 }
 723                 add_general (&gr, &stack_size, &cinfo->ret);
 724                 cinfo->vret_arg_index = 1;
 725         } else {
 726                 /* this */
 727                 if (sig->hasthis)
 728                         add_general (&gr, &stack_size, cinfo->args + 0);
 729
 730                 if (cinfo->vtype_retaddr)
 731                         add_general (&gr, &stack_size, &cinfo->ret);
 732         }
 733
 734         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 735                 gr = PARAM_REGS;
 736                 fr = FLOAT_PARAM_REGS;
 737
 738                 /* Emit the signature cookie just before the implicit arguments */
 739                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 740         }
 741
 742         for (i = pstart; i < sig->param_count; ++i) {
 743                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 744                 MonoType *ptype;
 745
 746 #ifdef HOST_WIN32
 747                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 748                 if (gr > fr)
 749                         fr = gr;
 750                 else if (fr > gr)
 751                         gr = fr;
 752 #endif
 753
 754                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 755                         /* We allways pass the sig cookie on the stack for simplicity */
 756                         /*
 757                          * Prevent implicit arguments + the sig cookie from being passed
 758                          * in registers.
 759                          */
 760                         gr = PARAM_REGS;
 761                         fr = FLOAT_PARAM_REGS;
 762
 763                         /* Emit the signature cookie just before the implicit arguments */
 764                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 765                 }
 766
 767                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 768                 switch (ptype->type) {
 769                 case MONO_TYPE_BOOLEAN:
 770                 case MONO_TYPE_I1:
 771                 case MONO_TYPE_U1:
 772                         add_general (&gr, &stack_size, ainfo);
 773                         break;
 774                 case MONO_TYPE_I2:
 775                 case MONO_TYPE_U2:
 776                 case MONO_TYPE_CHAR:
 777                         add_general (&gr, &stack_size, ainfo);
 778                         break;
 779                 case MONO_TYPE_I4:
 780                 case MONO_TYPE_U4:
 781                         add_general (&gr, &stack_size, ainfo);
 782                         break;
 783                 case MONO_TYPE_I:
 784                 case MONO_TYPE_U:
 785                 case MONO_TYPE_PTR:
 786                 case MONO_TYPE_FNPTR:
 787                 case MONO_TYPE_CLASS:
 788                 case MONO_TYPE_OBJECT:
 789                 case MONO_TYPE_STRING:
 790                 case MONO_TYPE_SZARRAY:
 791                 case MONO_TYPE_ARRAY:
 792                         add_general (&gr, &stack_size, ainfo);
 793                         break;
 794                 case MONO_TYPE_GENERICINST:
 795                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 796                                 add_general (&gr, &stack_size, ainfo);
 797                                 break;
 798                         }
 799                         /* fall through */
 800                 case MONO_TYPE_VALUETYPE:
 801                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 802                         break;
 803                 case MONO_TYPE_TYPEDBYREF:
 804 #ifdef HOST_WIN32
 805                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 806 #else
 807                         stack_size += sizeof (MonoTypedRef);
 808                         ainfo->storage = ArgOnStack;
 809 #endif
 810                         break;
 811                 case MONO_TYPE_U8:
 812                 case MONO_TYPE_I8:
 813                         add_general (&gr, &stack_size, ainfo);
 814                         break;
 815                 case MONO_TYPE_R4:
 816                         add_float (&fr, &stack_size, ainfo, FALSE);
 817                         break;
 818                 case MONO_TYPE_R8:
 819                         add_float (&fr, &stack_size, ainfo, TRUE);
 820                         break;
 821                 default:
 822                         g_assert_not_reached ();
 823                 }
 824         }
 825
 826         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 827                 gr = PARAM_REGS;
 828                 fr = FLOAT_PARAM_REGS;
 829
 830                 /* Emit the signature cookie just before the implicit arguments */
 831                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 832         }
 833
 834 #ifdef HOST_WIN32
 835         // There always is 32 bytes reserved on the stack when calling on Winx64
 836         stack_size += 0x20;
 837 #endif
 838
 839         if (stack_size & 0x8) {
 840                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 841                 cinfo->need_stack_align = TRUE;
 842                 stack_size += 8;
 843         }
 844
 845         cinfo->stack_usage = stack_size;
 846         cinfo->reg_usage = gr;
 847         cinfo->freg_usage = fr;
 848         return cinfo;
 849 }
 850
 851 /*
 852  * mono_arch_get_argument_info:
 853  * @csig:  a method signature
 854  * @param_count: the number of parameters to consider
 855  * @arg_info: an array to store the result infos
 856  *
 857  * Gathers information on parameters such as size, alignment and
 858  * padding. arg_info should be large enought to hold param_count + 1 entries.
 859  *
 860  * Returns the size of the argument area on the stack.
 861  */
 862 int
 863 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 864 {
 865         int k;
 866         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 867         guint32 args_size = cinfo->stack_usage;
 868
 869         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 870         if (csig->hasthis) {
 871                 arg_info [0].offset = 0;
 872         }
 873
 874         for (k = 0; k < param_count; k++) {
 875                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 876                 /* FIXME: */
 877                 arg_info [k + 1].size = 0;
 878         }
 879
 880         g_free (cinfo);
 881
 882         return args_size;
 883 }
 884
 885 gboolean
 886 mono_amd64_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
 887 {
 888         CallInfo *c1, *c2;
 889         gboolean res;
 890
 891         c1 = get_call_info (NULL, NULL, caller_sig, FALSE);
 892         c2 = get_call_info (NULL, NULL, callee_sig, FALSE);
 893         res = c1->stack_usage >= c2->stack_usage;
 894         if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
 895                 /* An address on the callee's stack is passed as the first argument */
 896                 res = FALSE;
 897
 898         g_free (c1);
 899         g_free (c2);
 900
 901         return res;
 902 }
 903
 904 static int
 905 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 906 {
 907 #ifndef _MSC_VER
 908         __asm__ __volatile__ ("cpuid"
 909                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 910                 : "a" (id));
 911 #else
 912         int info[4];
 913         __cpuid(info, id);
 914         *p_eax = info[0];
 915         *p_ebx = info[1];
 916         *p_ecx = info[2];
 917         *p_edx = info[3];
 918 #endif
 919         return 1;
 920 }
 921
 922 /*
 923  * Initialize the cpu to execute managed code.
 924  */
 925 void
 926 mono_arch_cpu_init (void)
 927 {
 928 #ifndef _MSC_VER
 929         guint16 fpcw;
 930
 931         /* spec compliance requires running with double precision */
 932         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 933         fpcw &= ~X86_FPCW_PRECC_MASK;
 934         fpcw |= X86_FPCW_PREC_DOUBLE;
 935         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 936         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 937 #else
 938         /* TODO: This is crashing on Win64 right now.
 939         * _control87 (_PC_53, MCW_PC);
 940         */
 941 #endif
 942 }
 943
 944 /*
 945  * Initialize architecture specific code.
 946  */
 947 void
 948 mono_arch_init (void)
 949 {
 950         int flags;
 951
 952         InitializeCriticalSection (&mini_arch_mutex);
 953
 954 #ifdef MONO_ARCH_NOMAP32BIT
 955         flags = MONO_MMAP_READ;
 956         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
 957         breakpoint_size = 13;
 958         breakpoint_fault_size = 3;
 959         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
 960         single_step_fault_size = 5;
 961 #else
 962         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
 963         /* amd64_mov_reg_mem () */
 964         breakpoint_size = 8;
 965         breakpoint_fault_size = 8;
 966         single_step_fault_size = 8;
 967 #endif
 968
 969         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 970         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 971         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 972
 973         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
 974         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
 975         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
 976 }
 977
 978 /*
 979  * Cleanup architecture specific code.
 980  */
 981 void
 982 mono_arch_cleanup (void)
 983 {
 984         DeleteCriticalSection (&mini_arch_mutex);
 985 }
 986
 987 /*
 988  * This function returns the optimizations supported on this cpu.
 989  */
 990 guint32
 991 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 992 {
 993         int eax, ebx, ecx, edx;
 994         guint32 opts = 0;
 995
 996         *exclude_mask = 0;
 997         /* Feature Flags function, flags returned in EDX. */
 998         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 999                 if (edx & (1 << 15)) {
1000                         opts |= MONO_OPT_CMOV;
1001                         if (edx & 1)
1002                                 opts |= MONO_OPT_FCMOV;
1003                         else
1004                                 *exclude_mask |= MONO_OPT_FCMOV;
1005                 } else
1006                         *exclude_mask |= MONO_OPT_CMOV;
1007         }
1008
1009         return opts;
1010 }
1011
1012 /*
1013  * This function test for all SSE functions supported.
1014  *
1015  * Returns a bitmask corresponding to all supported versions.
1016  *
1017  */
1018 guint32
1019 mono_arch_cpu_enumerate_simd_versions (void)
1020 {
1021         int eax, ebx, ecx, edx;
1022         guint32 sse_opts = 0;
1023
1024         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1025                 if (edx & (1 << 25))
1026                         sse_opts |= SIMD_VERSION_SSE1;
1027                 if (edx & (1 << 26))
1028                         sse_opts |= SIMD_VERSION_SSE2;
1029                 if (ecx & (1 << 0))
1030                         sse_opts |= SIMD_VERSION_SSE3;
1031                 if (ecx & (1 << 9))
1032                         sse_opts |= SIMD_VERSION_SSSE3;
1033                 if (ecx & (1 << 19))
1034                         sse_opts |= SIMD_VERSION_SSE41;
1035                 if (ecx & (1 << 20))
1036                         sse_opts |= SIMD_VERSION_SSE42;
1037         }
1038
1039         /* Yes, all this needs to be done to check for sse4a.
1040            See: "Amd: CPUID Specification"
1041          */
1042         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1043                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1044                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1045                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1046                         if (ecx & (1 << 6))
1047                                 sse_opts |= SIMD_VERSION_SSE4a;
1048                 }
1049         }
1050
1051         return sse_opts;
1052 }
1053
1054 #ifndef DISABLE_JIT
1055
1056 GList *
1057 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1058 {
1059         GList *vars = NULL;
1060         int i;
1061
1062         for (i = 0; i < cfg->num_varinfo; i++) {
1063                 MonoInst *ins = cfg->varinfo [i];
1064                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1065
1066                 /* unused vars */
1067                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1068                         continue;
1069
1070                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1071                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1072                         continue;
1073
1074                 if (mono_is_regsize_var (ins->inst_vtype)) {
1075                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1076                         g_assert (i == vmv->idx);
1077                         vars = g_list_prepend (vars, vmv);
1078                 }
1079         }
1080
1081         vars = mono_varlist_sort (cfg, vars, 0);
1082
1083         return vars;
1084 }
1085
1086 /**
1087  * mono_arch_compute_omit_fp:
1088  *
1089  *   Determine whenever the frame pointer can be eliminated.
1090  */
1091 static void
1092 mono_arch_compute_omit_fp (MonoCompile *cfg)
1093 {
1094         MonoMethodSignature *sig;
1095         MonoMethodHeader *header;
1096         int i, locals_size;
1097         CallInfo *cinfo;
1098
1099         if (cfg->arch.omit_fp_computed)
1100                 return;
1101
1102         header = cfg->header;
1103
1104         sig = mono_method_signature (cfg->method);
1105
1106         if (!cfg->arch.cinfo)
1107                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1108         cinfo = cfg->arch.cinfo;
1109
1110         /*
1111          * FIXME: Remove some of the restrictions.
1112          */
1113         cfg->arch.omit_fp = TRUE;
1114         cfg->arch.omit_fp_computed = TRUE;
1115
1116         if (cfg->disable_omit_fp)
1117                 cfg->arch.omit_fp = FALSE;
1118
1119         if (!debug_omit_fp ())
1120                 cfg->arch.omit_fp = FALSE;
1121         /*
1122         if (cfg->method->save_lmf)
1123                 cfg->arch.omit_fp = FALSE;
1124         */
1125         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1126                 cfg->arch.omit_fp = FALSE;
1127         if (header->num_clauses)
1128                 cfg->arch.omit_fp = FALSE;
1129         if (cfg->param_area)
1130                 cfg->arch.omit_fp = FALSE;
1131         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1132                 cfg->arch.omit_fp = FALSE;
1133         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1134                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1135                 cfg->arch.omit_fp = FALSE;
1136         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1137                 ArgInfo *ainfo = &cinfo->args [i];
1138
1139                 if (ainfo->storage == ArgOnStack) {
1140                         /*
1141                          * The stack offset can only be determined when the frame
1142                          * size is known.
1143                          */
1144                         cfg->arch.omit_fp = FALSE;
1145                 }
1146         }
1147
1148         locals_size = 0;
1149         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1150                 MonoInst *ins = cfg->varinfo [i];
1151                 int ialign;
1152
1153                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1154         }
1155 }
1156
1157 GList *
1158 mono_arch_get_global_int_regs (MonoCompile *cfg)
1159 {
1160         GList *regs = NULL;
1161
1162         mono_arch_compute_omit_fp (cfg);
1163
1164         if (cfg->globalra) {
1165                 if (cfg->arch.omit_fp)
1166                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1167
1168                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1169                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1170                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1171                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1172                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1173
1174                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1175                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1176                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1177                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1178                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1179                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1180                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1181                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1182         } else {
1183                 if (cfg->arch.omit_fp)
1184                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1185
1186                 /* We use the callee saved registers for global allocation */
1187                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1188                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1189                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1190                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1191                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1192 #ifdef HOST_WIN32
1193                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1194                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1195 #endif
1196         }
1197
1198         return regs;
1199 }
1200
1201 GList*
1202 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1203 {
1204         GList *regs = NULL;
1205         int i;
1206
1207         /* All XMM registers */
1208         for (i = 0; i < 16; ++i)
1209                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1210
1211         return regs;
1212 }
1213
1214 GList*
1215 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1216 {
1217         static GList *r = NULL;
1218
1219         if (r == NULL) {
1220                 GList *regs = NULL;
1221
1222                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1223                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1224                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1225                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1226                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1227                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1228
1229                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1230                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1231                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1232                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1233                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1234                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1235                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1236                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1237
1238                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1239         }
1240
1241         return r;
1242 }
1243
1244 GList*
1245 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1246 {
1247         int i;
1248         static GList *r = NULL;
1249
1250         if (r == NULL) {
1251                 GList *regs = NULL;
1252
1253                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1254                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1255
1256                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1257         }
1258
1259         return r;
1260 }
1261
1262 /*
1263  * mono_arch_regalloc_cost:
1264  *
1265  *  Return the cost, in number of memory references, of the action of
1266  * allocating the variable VMV into a register during global register
1267  * allocation.
1268  */
1269 guint32
1270 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1271 {
1272         MonoInst *ins = cfg->varinfo [vmv->idx];
1273
1274         if (cfg->method->save_lmf)
1275                 /* The register is already saved */
1276                 /* substract 1 for the invisible store in the prolog */
1277                 return (ins->opcode == OP_ARG) ? 0 : 1;
1278         else
1279                 /* push+pop */
1280                 return (ins->opcode == OP_ARG) ? 1 : 2;
1281 }
1282
1283 /*
1284  * mono_arch_fill_argument_info:
1285  *
1286  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1287  * of the method.
1288  */
1289 void
1290 mono_arch_fill_argument_info (MonoCompile *cfg)
1291 {
1292         MonoMethodSignature *sig;
1293         MonoMethodHeader *header;
1294         MonoInst *ins;
1295         int i;
1296         CallInfo *cinfo;
1297
1298         header = cfg->header;
1299
1300         sig = mono_method_signature (cfg->method);
1301
1302         cinfo = cfg->arch.cinfo;
1303
1304         /*
1305          * Contrary to mono_arch_allocate_vars (), the information should describe
1306          * where the arguments are at the beginning of the method, not where they can be
1307          * accessed during the execution of the method. The later makes no sense for the
1308          * global register allocator, since a variable can be in more than one location.
1309          */
1310         if (sig->ret->type != MONO_TYPE_VOID) {
1311                 switch (cinfo->ret.storage) {
1312                 case ArgInIReg:
1313                 case ArgInFloatSSEReg:
1314                 case ArgInDoubleSSEReg:
1315                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1316                                 cfg->vret_addr->opcode = OP_REGVAR;
1317                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1318                         }
1319                         else {
1320                                 cfg->ret->opcode = OP_REGVAR;
1321                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1322                         }
1323                         break;
1324                 case ArgValuetypeInReg:
1325                         cfg->ret->opcode = OP_REGOFFSET;
1326                         cfg->ret->inst_basereg = -1;
1327                         cfg->ret->inst_offset = -1;
1328                         break;
1329                 default:
1330                         g_assert_not_reached ();
1331                 }
1332         }
1333
1334         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1335                 ArgInfo *ainfo = &cinfo->args [i];
1336                 MonoType *arg_type;
1337
1338                 ins = cfg->args [i];
1339
1340                 if (sig->hasthis && (i == 0))
1341                         arg_type = &mono_defaults.object_class->byval_arg;
1342                 else
1343                         arg_type = sig->params [i - sig->hasthis];
1344
1345                 switch (ainfo->storage) {
1346                 case ArgInIReg:
1347                 case ArgInFloatSSEReg:
1348                 case ArgInDoubleSSEReg:
1349                         ins->opcode = OP_REGVAR;
1350                         ins->inst_c0 = ainfo->reg;
1351                         break;
1352                 case ArgOnStack:
1353                         ins->opcode = OP_REGOFFSET;
1354                         ins->inst_basereg = -1;
1355                         ins->inst_offset = -1;
1356                         break;
1357                 case ArgValuetypeInReg:
1358                         /* Dummy */
1359                         ins->opcode = OP_NOP;
1360                         break;
1361                 default:
1362                         g_assert_not_reached ();
1363                 }
1364         }
1365 }
1366
1367 void
1368 mono_arch_allocate_vars (MonoCompile *cfg)
1369 {
1370         MonoMethodSignature *sig;
1371         MonoMethodHeader *header;
1372         MonoInst *ins;
1373         int i, offset;
1374         guint32 locals_stack_size, locals_stack_align;
1375         gint32 *offsets;
1376         CallInfo *cinfo;
1377
1378         header = cfg->header;
1379
1380         sig = mono_method_signature (cfg->method);
1381
1382         cinfo = cfg->arch.cinfo;
1383
1384         mono_arch_compute_omit_fp (cfg);
1385
1386         /*
1387          * We use the ABI calling conventions for managed code as well.
1388          * Exception: valuetypes are only sometimes passed or returned in registers.
1389          */
1390
1391         /*
1392          * The stack looks like this:
1393          * <incoming arguments passed on the stack>
1394          * <return value>
1395          * <lmf/caller saved registers>
1396          * <locals>
1397          * <spill area>
1398          * <localloc area>  -> grows dynamically
1399          * <params area>
1400          */
1401
1402         if (cfg->arch.omit_fp) {
1403                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1404                 cfg->frame_reg = AMD64_RSP;
1405                 offset = 0;
1406         } else {
1407                 /* Locals are allocated backwards from %fp */
1408                 cfg->frame_reg = AMD64_RBP;
1409                 offset = 0;
1410         }
1411
1412         if (cfg->method->save_lmf) {
1413                 /* Reserve stack space for saving LMF */
1414                 if (cfg->arch.omit_fp) {
1415                         cfg->arch.lmf_offset = offset;
1416                         offset += sizeof (MonoLMF);
1417                 }
1418                 else {
1419                         offset += sizeof (MonoLMF);
1420                         cfg->arch.lmf_offset = -offset;
1421                 }
1422         } else {
1423                 if (cfg->arch.omit_fp)
1424                         cfg->arch.reg_save_area_offset = offset;
1425                 /* Reserve space for caller saved registers */
1426                 for (i = 0; i < AMD64_NREG; ++i)
1427                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1428                                 offset += sizeof (gpointer);
1429                         }
1430         }
1431
1432         if (sig->ret->type != MONO_TYPE_VOID) {
1433                 switch (cinfo->ret.storage) {
1434                 case ArgInIReg:
1435                 case ArgInFloatSSEReg:
1436                 case ArgInDoubleSSEReg:
1437                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1438                                 if (cfg->globalra) {
1439                                         cfg->vret_addr->opcode = OP_REGVAR;
1440                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1441                                 } else {
1442                                         /* The register is volatile */
1443                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1444                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1445                                         if (cfg->arch.omit_fp) {
1446                                                 cfg->vret_addr->inst_offset = offset;
1447                                                 offset += 8;
1448                                         } else {
1449                                                 offset += 8;
1450                                                 cfg->vret_addr->inst_offset = -offset;
1451                                         }
1452                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1453                                                 printf ("vret_addr =");
1454                                                 mono_print_ins (cfg->vret_addr);
1455                                         }
1456                                 }
1457                         }
1458                         else {
1459                                 cfg->ret->opcode = OP_REGVAR;
1460                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1461                         }
1462                         break;
1463                 case ArgValuetypeInReg:
1464                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1465                         cfg->ret->opcode = OP_REGOFFSET;
1466                         cfg->ret->inst_basereg = cfg->frame_reg;
1467                         if (cfg->arch.omit_fp) {
1468                                 cfg->ret->inst_offset = offset;
1469                                 offset += 16;
1470                         } else {
1471                                 offset += 16;
1472                                 cfg->ret->inst_offset = - offset;
1473                         }
1474                         break;
1475                 default:
1476                         g_assert_not_reached ();
1477                 }
1478                 if (!cfg->globalra)
1479                         cfg->ret->dreg = cfg->ret->inst_c0;
1480         }
1481
1482         /* Allocate locals */
1483         if (!cfg->globalra) {
1484                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1485                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1486                         char *mname = mono_method_full_name (cfg->method, TRUE);
1487                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1488                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1489                         g_free (mname);
1490                         return;
1491                 }
1492
1493                 if (locals_stack_align) {
1494                         offset += (locals_stack_align - 1);
1495                         offset &= ~(locals_stack_align - 1);
1496                 }
1497                 if (cfg->arch.omit_fp) {
1498                         cfg->locals_min_stack_offset = offset;
1499                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1500                 } else {
1501                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1502                         cfg->locals_max_stack_offset = - offset;
1503                 }
1504
1505                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1506                         if (offsets [i] != -1) {
1507                                 MonoInst *ins = cfg->varinfo [i];
1508                                 ins->opcode = OP_REGOFFSET;
1509                                 ins->inst_basereg = cfg->frame_reg;
1510                                 if (cfg->arch.omit_fp)
1511                                         ins->inst_offset = (offset + offsets [i]);
1512                                 else
1513                                         ins->inst_offset = - (offset + offsets [i]);
1514                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1515                         }
1516                 }
1517                 offset += locals_stack_size;
1518         }
1519
1520         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1521                 g_assert (!cfg->arch.omit_fp);
1522                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1523                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1524         }
1525
1526         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1527                 ins = cfg->args [i];
1528                 if (ins->opcode != OP_REGVAR) {
1529                         ArgInfo *ainfo = &cinfo->args [i];
1530                         gboolean inreg = TRUE;
1531                         MonoType *arg_type;
1532
1533                         if (sig->hasthis && (i == 0))
1534                                 arg_type = &mono_defaults.object_class->byval_arg;
1535                         else
1536                                 arg_type = sig->params [i - sig->hasthis];
1537
1538                         if (cfg->globalra) {
1539                                 /* The new allocator needs info about the original locations of the arguments */
1540                                 switch (ainfo->storage) {
1541                                 case ArgInIReg:
1542                                 case ArgInFloatSSEReg:
1543                                 case ArgInDoubleSSEReg:
1544                                         ins->opcode = OP_REGVAR;
1545                                         ins->inst_c0 = ainfo->reg;
1546                                         break;
1547                                 case ArgOnStack:
1548                                         g_assert (!cfg->arch.omit_fp);
1549                                         ins->opcode = OP_REGOFFSET;
1550                                         ins->inst_basereg = cfg->frame_reg;
1551                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1552                                         break;
1553                                 case ArgValuetypeInReg:
1554                                         ins->opcode = OP_REGOFFSET;
1555                                         ins->inst_basereg = cfg->frame_reg;
1556                                         /* These arguments are saved to the stack in the prolog */
1557                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1558                                         if (cfg->arch.omit_fp) {
1559                                                 ins->inst_offset = offset;
1560                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1561                                         } else {
1562                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1563                                                 ins->inst_offset = - offset;
1564                                         }
1565                                         break;
1566                                 default:
1567                                         g_assert_not_reached ();
1568                                 }
1569
1570                                 continue;
1571                         }
1572
1573                         /* FIXME: Allocate volatile arguments to registers */
1574                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1575                                 inreg = FALSE;
1576
1577                         /*
1578                          * Under AMD64, all registers used to pass arguments to functions
1579                          * are volatile across calls.
1580                          * FIXME: Optimize this.
1581                          */
1582                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1583                                 inreg = FALSE;
1584
1585                         ins->opcode = OP_REGOFFSET;
1586
1587                         switch (ainfo->storage) {
1588                         case ArgInIReg:
1589                         case ArgInFloatSSEReg:
1590                         case ArgInDoubleSSEReg:
1591                                 if (inreg) {
1592                                         ins->opcode = OP_REGVAR;
1593                                         ins->dreg = ainfo->reg;
1594                                 }
1595                                 break;
1596                         case ArgOnStack:
1597                                 g_assert (!cfg->arch.omit_fp);
1598                                 ins->opcode = OP_REGOFFSET;
1599                                 ins->inst_basereg = cfg->frame_reg;
1600                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1601                                 break;
1602                         case ArgValuetypeInReg:
1603                                 break;
1604                         case ArgValuetypeAddrInIReg: {
1605                                 MonoInst *indir;
1606                                 g_assert (!cfg->arch.omit_fp);
1607
1608                                 MONO_INST_NEW (cfg, indir, 0);
1609                                 indir->opcode = OP_REGOFFSET;
1610                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1611                                         indir->inst_basereg = cfg->frame_reg;
1612                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1613                                         offset += (sizeof (gpointer));
1614                                         indir->inst_offset = - offset;
1615                                 }
1616                                 else {
1617                                         indir->inst_basereg = cfg->frame_reg;
1618                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1619                                 }
1620
1621                                 ins->opcode = OP_VTARG_ADDR;
1622                                 ins->inst_left = indir;
1623
1624                                 break;
1625                         }
1626                         default:
1627                                 NOT_IMPLEMENTED;
1628                         }
1629
1630                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1631                                 ins->opcode = OP_REGOFFSET;
1632                                 ins->inst_basereg = cfg->frame_reg;
1633                                 /* These arguments are saved to the stack in the prolog */
1634                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1635                                 if (cfg->arch.omit_fp) {
1636                                         ins->inst_offset = offset;
1637                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1638                                         // Arguments are yet supported by the stack map creation code
1639                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1640                                 } else {
1641                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1642                                         ins->inst_offset = - offset;
1643                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1644                                 }
1645                         }
1646                 }
1647         }
1648
1649         cfg->stack_offset = offset;
1650 }
1651
1652 void
1653 mono_arch_create_vars (MonoCompile *cfg)
1654 {
1655         MonoMethodSignature *sig;
1656         CallInfo *cinfo;
1657
1658         sig = mono_method_signature (cfg->method);
1659
1660         if (!cfg->arch.cinfo)
1661                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1662         cinfo = cfg->arch.cinfo;
1663
1664         if (cinfo->ret.storage == ArgValuetypeInReg)
1665                 cfg->ret_var_is_local = TRUE;
1666
1667         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1668                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1669                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1670                         printf ("vret_addr = ");
1671                         mono_print_ins (cfg->vret_addr);
1672                 }
1673         }
1674
1675         if (cfg->gen_seq_points) {
1676                 MonoInst *ins;
1677
1678             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1679                 ins->flags |= MONO_INST_VOLATILE;
1680                 cfg->arch.ss_trigger_page_var = ins;
1681         }
1682
1683 #ifdef MONO_AMD64_NO_PUSHES
1684         /*
1685          * When this is set, we pass arguments on the stack by moves, and by allocating
1686          * a bigger stack frame, instead of pushes.
1687          * Pushes complicate exception handling because the arguments on the stack have
1688          * to be popped each time a frame is unwound. They also make fp elimination
1689          * impossible.
1690          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1691          * on a new frame which doesn't include a param area.
1692          */
1693         cfg->arch.no_pushes = TRUE;
1694 #endif
1695 }
1696
1697 static void
1698 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1699 {
1700         MonoInst *ins;
1701
1702         switch (storage) {
1703         case ArgInIReg:
1704                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1705                 ins->dreg = mono_alloc_ireg (cfg);
1706                 ins->sreg1 = tree->dreg;
1707                 MONO_ADD_INS (cfg->cbb, ins);
1708                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1709                 break;
1710         case ArgInFloatSSEReg:
1711                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1712                 ins->dreg = mono_alloc_freg (cfg);
1713                 ins->sreg1 = tree->dreg;
1714                 MONO_ADD_INS (cfg->cbb, ins);
1715
1716                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1717                 break;
1718         case ArgInDoubleSSEReg:
1719                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1720                 ins->dreg = mono_alloc_freg (cfg);
1721                 ins->sreg1 = tree->dreg;
1722                 MONO_ADD_INS (cfg->cbb, ins);
1723
1724                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1725
1726                 break;
1727         default:
1728                 g_assert_not_reached ();
1729         }
1730 }
1731
1732 static int
1733 arg_storage_to_load_membase (ArgStorage storage)
1734 {
1735         switch (storage) {
1736         case ArgInIReg:
1737                 return OP_LOAD_MEMBASE;
1738         case ArgInDoubleSSEReg:
1739                 return OP_LOADR8_MEMBASE;
1740         case ArgInFloatSSEReg:
1741                 return OP_LOADR4_MEMBASE;
1742         default:
1743                 g_assert_not_reached ();
1744         }
1745
1746         return -1;
1747 }
1748
1749 static void
1750 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1751 {
1752         MonoInst *arg;
1753         MonoMethodSignature *tmp_sig;
1754         MonoInst *sig_arg;
1755
1756         if (call->tail_call)
1757                 NOT_IMPLEMENTED;
1758
1759         /* FIXME: Add support for signature tokens to AOT */
1760         cfg->disable_aot = TRUE;
1761
1762         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1763
1764         /*
1765          * mono_ArgIterator_Setup assumes the signature cookie is
1766          * passed first and all the arguments which were before it are
1767          * passed on the stack after the signature. So compensate by
1768          * passing a different signature.
1769          */
1770         tmp_sig = mono_metadata_signature_dup (call->signature);
1771         tmp_sig->param_count -= call->signature->sentinelpos;
1772         tmp_sig->sentinelpos = 0;
1773         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1774
1775         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1776         sig_arg->dreg = mono_alloc_ireg (cfg);
1777         sig_arg->inst_p0 = tmp_sig;
1778         MONO_ADD_INS (cfg->cbb, sig_arg);
1779
1780         if (cfg->arch.no_pushes) {
1781                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1782         } else {
1783                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1784                 arg->sreg1 = sig_arg->dreg;
1785                 MONO_ADD_INS (cfg->cbb, arg);
1786         }
1787 }
1788
1789 static inline LLVMArgStorage
1790 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1791 {
1792         switch (storage) {
1793         case ArgInIReg:
1794                 return LLVMArgInIReg;
1795         case ArgNone:
1796                 return LLVMArgNone;
1797         default:
1798                 g_assert_not_reached ();
1799                 return LLVMArgNone;
1800         }
1801 }
1802
1803 #ifdef ENABLE_LLVM
1804 LLVMCallInfo*
1805 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1806 {
1807         int i, n;
1808         CallInfo *cinfo;
1809         ArgInfo *ainfo;
1810         int j;
1811         LLVMCallInfo *linfo;
1812         MonoType *t;
1813
1814         n = sig->param_count + sig->hasthis;
1815
1816         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1817
1818         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1819
1820         /*
1821          * LLVM always uses the native ABI while we use our own ABI, the
1822          * only difference is the handling of vtypes:
1823          * - we only pass/receive them in registers in some cases, and only
1824          *   in 1 or 2 integer registers.
1825          */
1826         if (cinfo->ret.storage == ArgValuetypeInReg) {
1827                 if (sig->pinvoke) {
1828                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1829                         cfg->disable_llvm = TRUE;
1830                         return linfo;
1831                 }
1832
1833                 linfo->ret.storage = LLVMArgVtypeInReg;
1834                 for (j = 0; j < 2; ++j)
1835                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1836         }
1837
1838         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1839                 /* Vtype returned using a hidden argument */
1840                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1841                 linfo->vret_arg_index = cinfo->vret_arg_index;
1842         }
1843
1844         for (i = 0; i < n; ++i) {
1845                 ainfo = cinfo->args + i;
1846
1847                 if (i >= sig->hasthis)
1848                         t = sig->params [i - sig->hasthis];
1849                 else
1850                         t = &mono_defaults.int_class->byval_arg;
1851
1852                 linfo->args [i].storage = LLVMArgNone;
1853
1854                 switch (ainfo->storage) {
1855                 case ArgInIReg:
1856                         linfo->args [i].storage = LLVMArgInIReg;
1857                         break;
1858                 case ArgInDoubleSSEReg:
1859                 case ArgInFloatSSEReg:
1860                         linfo->args [i].storage = LLVMArgInFPReg;
1861                         break;
1862                 case ArgOnStack:
1863                         if (MONO_TYPE_ISSTRUCT (t)) {
1864                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1865                         } else {
1866                                 linfo->args [i].storage = LLVMArgInIReg;
1867                                 if (!t->byref) {
1868                                         if (t->type == MONO_TYPE_R4)
1869                                                 linfo->args [i].storage = LLVMArgInFPReg;
1870                                         else if (t->type == MONO_TYPE_R8)
1871                                                 linfo->args [i].storage = LLVMArgInFPReg;
1872                                 }
1873                         }
1874                         break;
1875                 case ArgValuetypeInReg:
1876                         if (sig->pinvoke) {
1877                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1878                                 cfg->disable_llvm = TRUE;
1879                                 return linfo;
1880                         }
1881
1882                         linfo->args [i].storage = LLVMArgVtypeInReg;
1883                         for (j = 0; j < 2; ++j)
1884                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1885                         break;
1886                 default:
1887                         cfg->exception_message = g_strdup ("ainfo->storage");
1888                         cfg->disable_llvm = TRUE;
1889                         break;
1890                 }
1891         }
1892
1893         return linfo;
1894 }
1895 #endif
1896
1897 void
1898 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1899 {
1900         MonoInst *arg, *in;
1901         MonoMethodSignature *sig;
1902         int i, n, stack_size;
1903         CallInfo *cinfo;
1904         ArgInfo *ainfo;
1905
1906         stack_size = 0;
1907
1908         sig = call->signature;
1909         n = sig->param_count + sig->hasthis;
1910
1911         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1912
1913         if (COMPILE_LLVM (cfg)) {
1914                 /* We shouldn't be called in the llvm case */
1915                 cfg->disable_llvm = TRUE;
1916                 return;
1917         }
1918
1919         if (cinfo->need_stack_align) {
1920                 if (!cfg->arch.no_pushes)
1921                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1922         }
1923
1924         /*
1925          * Emit all arguments which are passed on the stack to prevent register
1926          * allocation problems.
1927          */
1928         if (cfg->arch.no_pushes) {
1929                 for (i = 0; i < n; ++i) {
1930                         MonoType *t;
1931                         ainfo = cinfo->args + i;
1932
1933                         in = call->args [i];
1934
1935                         if (sig->hasthis && i == 0)
1936                                 t = &mono_defaults.object_class->byval_arg;
1937                         else
1938                                 t = sig->params [i - sig->hasthis];
1939
1940                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1941                                 if (!t->byref) {
1942                                         if (t->type == MONO_TYPE_R4)
1943                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1944                                         else if (t->type == MONO_TYPE_R8)
1945                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1946                                         else
1947                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1948                                 } else {
1949                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1950                                 }
1951                         }
1952                 }
1953         }
1954
1955         /*
1956          * Emit all parameters passed in registers in non-reverse order for better readability
1957          * and to help the optimization in emit_prolog ().
1958          */
1959         for (i = 0; i < n; ++i) {
1960                 ainfo = cinfo->args + i;
1961
1962                 in = call->args [i];
1963
1964                 if (ainfo->storage == ArgInIReg)
1965                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1966         }
1967
1968         for (i = n - 1; i >= 0; --i) {
1969                 ainfo = cinfo->args + i;
1970
1971                 in = call->args [i];
1972
1973                 switch (ainfo->storage) {
1974                 case ArgInIReg:
1975                         /* Already done */
1976                         break;
1977                 case ArgInFloatSSEReg:
1978                 case ArgInDoubleSSEReg:
1979                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1980                         break;
1981                 case ArgOnStack:
1982                 case ArgValuetypeInReg:
1983                 case ArgValuetypeAddrInIReg:
1984                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1985                                 MonoInst *call_inst = (MonoInst*)call;
1986                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1987                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1988                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1989                                 guint32 align;
1990                                 guint32 size;
1991
1992                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1993                                         size = sizeof (MonoTypedRef);
1994                                         align = sizeof (gpointer);
1995                                 }
1996                                 else {
1997                                         if (sig->pinvoke)
1998                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1999                                         else {
2000                                                 /*
2001                                                  * Other backends use mono_type_stack_size (), but that
2002                                                  * aligns the size to 8, which is larger than the size of
2003                                                  * the source, leading to reads of invalid memory if the
2004                                                  * source is at the end of address space.
2005                                                  */
2006                                                 size = mono_class_value_size (in->klass, &align);
2007                                         }
2008                                 }
2009                                 g_assert (in->klass);
2010
2011                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2012                                         /* Avoid asserts in emit_memcpy () */
2013                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2014                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2015                                         /* Continue normally */
2016                                 }
2017
2018                                 if (size > 0) {
2019                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2020                                         arg->sreg1 = in->dreg;
2021                                         arg->klass = in->klass;
2022                                         arg->backend.size = size;
2023                                         arg->inst_p0 = call;
2024                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2025                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2026
2027                                         MONO_ADD_INS (cfg->cbb, arg);
2028                                 }
2029                         } else {
2030                                 if (cfg->arch.no_pushes) {
2031                                         /* Already done */
2032                                 } else {
2033                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2034                                         arg->sreg1 = in->dreg;
2035                                         if (!sig->params [i - sig->hasthis]->byref) {
2036                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2037                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2038                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2039                                                         arg->inst_destbasereg = X86_ESP;
2040                                                         arg->inst_offset = 0;
2041                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2042                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2043                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2044                                                         arg->inst_destbasereg = X86_ESP;
2045                                                         arg->inst_offset = 0;
2046                                                 }
2047                                         }
2048                                         MONO_ADD_INS (cfg->cbb, arg);
2049                                 }
2050                         }
2051                         break;
2052                 default:
2053                         g_assert_not_reached ();
2054                 }
2055
2056                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2057                         /* Emit the signature cookie just before the implicit arguments */
2058                         emit_sig_cookie (cfg, call, cinfo);
2059         }
2060
2061         /* Handle the case where there are no implicit arguments */
2062         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2063                 emit_sig_cookie (cfg, call, cinfo);
2064
2065         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2066                 MonoInst *vtarg;
2067
2068                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2069                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2070                                 /*
2071                                  * Tell the JIT to use a more efficient calling convention: call using
2072                                  * OP_CALL, compute the result location after the call, and save the
2073                                  * result there.
2074                                  */
2075                                 call->vret_in_reg = TRUE;
2076                                 /*
2077                                  * Nullify the instruction computing the vret addr to enable
2078                                  * future optimizations.
2079                                  */
2080                                 if (call->vret_var)
2081                                         NULLIFY_INS (call->vret_var);
2082                         } else {
2083                                 if (call->tail_call)
2084                                         NOT_IMPLEMENTED;
2085                                 /*
2086                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2087                                  * the stack. Push the address here, so the call instruction can
2088                                  * access it.
2089                                  */
2090                                 if (!cfg->arch.vret_addr_loc) {
2091                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2092                                         /* Prevent it from being register allocated or optimized away */
2093                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2094                                 }
2095
2096                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2097                         }
2098                 }
2099                 else {
2100                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2101                         vtarg->sreg1 = call->vret_var->dreg;
2102                         vtarg->dreg = mono_alloc_preg (cfg);
2103                         MONO_ADD_INS (cfg->cbb, vtarg);
2104
2105                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2106                 }
2107         }
2108
2109 #ifdef HOST_WIN32
2110         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2111                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2112         }
2113 #endif
2114
2115         if (cfg->method->save_lmf) {
2116                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2117                 MONO_ADD_INS (cfg->cbb, arg);
2118         }
2119
2120         call->stack_usage = cinfo->stack_usage;
2121 }
2122
2123 void
2124 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2125 {
2126         MonoInst *arg;
2127         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2128         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2129         int size = ins->backend.size;
2130
2131         if (ainfo->storage == ArgValuetypeInReg) {
2132                 MonoInst *load;
2133                 int part;
2134
2135                 for (part = 0; part < 2; ++part) {
2136                         if (ainfo->pair_storage [part] == ArgNone)
2137                                 continue;
2138
2139                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2140                         load->inst_basereg = src->dreg;
2141                         load->inst_offset = part * sizeof (gpointer);
2142
2143                         switch (ainfo->pair_storage [part]) {
2144                         case ArgInIReg:
2145                                 load->dreg = mono_alloc_ireg (cfg);
2146                                 break;
2147                         case ArgInDoubleSSEReg:
2148                         case ArgInFloatSSEReg:
2149                                 load->dreg = mono_alloc_freg (cfg);
2150                                 break;
2151                         default:
2152                                 g_assert_not_reached ();
2153                         }
2154                         MONO_ADD_INS (cfg->cbb, load);
2155
2156                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2157                 }
2158         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2159                 MonoInst *vtaddr, *load;
2160                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2161
2162                 g_assert (!cfg->arch.no_pushes);
2163
2164                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2165                 load->inst_p0 = vtaddr;
2166                 vtaddr->flags |= MONO_INST_INDIRECT;
2167                 load->type = STACK_MP;
2168                 load->klass = vtaddr->klass;
2169                 load->dreg = mono_alloc_ireg (cfg);
2170                 MONO_ADD_INS (cfg->cbb, load);
2171                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2172
2173                 if (ainfo->pair_storage [0] == ArgInIReg) {
2174                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2175                         arg->dreg = mono_alloc_ireg (cfg);
2176                         arg->sreg1 = load->dreg;
2177                         arg->inst_imm = 0;
2178                         MONO_ADD_INS (cfg->cbb, arg);
2179                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2180                 } else {
2181                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2182                         arg->sreg1 = load->dreg;
2183                         MONO_ADD_INS (cfg->cbb, arg);
2184                 }
2185         } else {
2186                 if (size == 8) {
2187                         if (cfg->arch.no_pushes) {
2188                                 int dreg = mono_alloc_ireg (cfg);
2189
2190                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2191                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2192                         } else {
2193                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2194                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2195                                 arg->inst_basereg = src->dreg;
2196                                 arg->inst_offset = 0;
2197                                 MONO_ADD_INS (cfg->cbb, arg);
2198                         }
2199                 } else if (size <= 40) {
2200                         if (cfg->arch.no_pushes) {
2201                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2202                         } else {
2203                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2204                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2205                         }
2206                 } else {
2207                         if (cfg->arch.no_pushes) {
2208                                 // FIXME: Code growth
2209                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2210                         } else {
2211                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2212                                 arg->inst_basereg = src->dreg;
2213                                 arg->inst_offset = 0;
2214                                 arg->inst_imm = size;
2215                                 MONO_ADD_INS (cfg->cbb, arg);
2216                         }
2217                 }
2218         }
2219 }
2220
2221 void
2222 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2223 {
2224         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2225
2226         if (ret->type == MONO_TYPE_R4) {
2227                 if (COMPILE_LLVM (cfg))
2228                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2229                 else
2230                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2231                 return;
2232         } else if (ret->type == MONO_TYPE_R8) {
2233                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2234                 return;
2235         }
2236
2237         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2238 }
2239
2240 #endif /* DISABLE_JIT */
2241
2242 #define EMIT_COND_BRANCH(ins,cond,sign) \
2243         if (ins->inst_true_bb->native_offset) { \
2244                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2245         } else { \
2246                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2247                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2248             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2249                         x86_branch8 (code, cond, 0, sign); \
2250                 else \
2251                         x86_branch32 (code, cond, 0, sign); \
2252 }
2253
2254 typedef struct {
2255         MonoMethodSignature *sig;
2256         CallInfo *cinfo;
2257 } ArchDynCallInfo;
2258
2259 typedef struct {
2260         mgreg_t regs [PARAM_REGS];
2261         mgreg_t res;
2262         guint8 *ret;
2263 } DynCallArgs;
2264
2265 static gboolean
2266 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2267 {
2268         int i;
2269
2270 #ifdef HOST_WIN32
2271         return FALSE;
2272 #endif
2273
2274         switch (cinfo->ret.storage) {
2275         case ArgNone:
2276         case ArgInIReg:
2277                 break;
2278         case ArgValuetypeInReg: {
2279                 ArgInfo *ainfo = &cinfo->ret;
2280
2281                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2282                         return FALSE;
2283                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2284                         return FALSE;
2285                 break;
2286         }
2287         default:
2288                 return FALSE;
2289         }
2290
2291         for (i = 0; i < cinfo->nargs; ++i) {
2292                 ArgInfo *ainfo = &cinfo->args [i];
2293                 switch (ainfo->storage) {
2294                 case ArgInIReg:
2295                         break;
2296                 case ArgValuetypeInReg:
2297                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2298                                 return FALSE;
2299                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2300                                 return FALSE;
2301                         break;
2302                 default:
2303                         return FALSE;
2304                 }
2305         }
2306
2307         return TRUE;
2308 }
2309
2310 /*
2311  * mono_arch_dyn_call_prepare:
2312  *
2313  *   Return a pointer to an arch-specific structure which contains information
2314  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2315  * supported for SIG.
2316  * This function is equivalent to ffi_prep_cif in libffi.
2317  */
2318 MonoDynCallInfo*
2319 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2320 {
2321         ArchDynCallInfo *info;
2322         CallInfo *cinfo;
2323
2324         cinfo = get_call_info (NULL, NULL, sig, FALSE);
2325
2326         if (!dyn_call_supported (sig, cinfo)) {
2327                 g_free (cinfo);
2328                 return NULL;
2329         }
2330
2331         info = g_new0 (ArchDynCallInfo, 1);
2332         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2333         info->sig = sig;
2334         info->cinfo = cinfo;
2335
2336         return (MonoDynCallInfo*)info;
2337 }
2338
2339 /*
2340  * mono_arch_dyn_call_free:
2341  *
2342  *   Free a MonoDynCallInfo structure.
2343  */
2344 void
2345 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2346 {
2347         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2348
2349         g_free (ainfo->cinfo);
2350         g_free (ainfo);
2351 }
2352
2353 /*
2354  * mono_arch_get_start_dyn_call:
2355  *
2356  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2357  * store the result into BUF.
2358  * ARGS should be an array of pointers pointing to the arguments.
2359  * RET should point to a memory buffer large enought to hold the result of the
2360  * call.
2361  * This function should be as fast as possible, any work which does not depend
2362  * on the actual values of the arguments should be done in
2363  * mono_arch_dyn_call_prepare ().
2364  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2365  * libffi.
2366  */
2367 void
2368 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2369 {
2370         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2371         DynCallArgs *p = (DynCallArgs*)buf;
2372         int arg_index, greg, i, pindex;
2373         MonoMethodSignature *sig = dinfo->sig;
2374
2375         g_assert (buf_len >= sizeof (DynCallArgs));
2376
2377         p->res = 0;
2378         p->ret = ret;
2379
2380         arg_index = 0;
2381         greg = 0;
2382         pindex = 0;
2383
2384         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2385                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2386                 if (!sig->hasthis)
2387                         pindex = 1;
2388         }
2389
2390         if (dinfo->cinfo->vtype_retaddr)
2391                 p->regs [greg ++] = (mgreg_t)ret;
2392
2393         for (i = pindex; i < sig->param_count; i++) {
2394                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2395                 gpointer *arg = args [arg_index ++];
2396
2397                 if (t->byref) {
2398                         p->regs [greg ++] = (mgreg_t)*(arg);
2399                         continue;
2400                 }
2401
2402                 switch (t->type) {
2403                 case MONO_TYPE_STRING:
2404                 case MONO_TYPE_CLASS:
2405                 case MONO_TYPE_ARRAY:
2406                 case MONO_TYPE_SZARRAY:
2407                 case MONO_TYPE_OBJECT:
2408                 case MONO_TYPE_PTR:
2409                 case MONO_TYPE_I:
2410                 case MONO_TYPE_U:
2411                 case MONO_TYPE_I8:
2412                 case MONO_TYPE_U8:
2413                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2414                         p->regs [greg ++] = (mgreg_t)*(arg);
2415                         break;
2416                 case MONO_TYPE_BOOLEAN:
2417                 case MONO_TYPE_U1:
2418                         p->regs [greg ++] = *(guint8*)(arg);
2419                         break;
2420                 case MONO_TYPE_I1:
2421                         p->regs [greg ++] = *(gint8*)(arg);
2422                         break;
2423                 case MONO_TYPE_I2:
2424                         p->regs [greg ++] = *(gint16*)(arg);
2425                         break;
2426                 case MONO_TYPE_U2:
2427                 case MONO_TYPE_CHAR:
2428                         p->regs [greg ++] = *(guint16*)(arg);
2429                         break;
2430                 case MONO_TYPE_I4:
2431                         p->regs [greg ++] = *(gint32*)(arg);
2432                         break;
2433                 case MONO_TYPE_U4:
2434                         p->regs [greg ++] = *(guint32*)(arg);
2435                         break;
2436                 case MONO_TYPE_GENERICINST:
2437                     if (MONO_TYPE_IS_REFERENCE (t)) {
2438                                 p->regs [greg ++] = (mgreg_t)*(arg);
2439                                 break;
2440                         } else {
2441                                 /* Fall through */
2442                         }
2443                 case MONO_TYPE_VALUETYPE: {
2444                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2445
2446                         g_assert (ainfo->storage == ArgValuetypeInReg);
2447                         if (ainfo->pair_storage [0] != ArgNone) {
2448                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2449                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2450                         }
2451                         if (ainfo->pair_storage [1] != ArgNone) {
2452                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2453                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2454                         }
2455                         break;
2456                 }
2457                 default:
2458                         g_assert_not_reached ();
2459                 }
2460         }
2461
2462         g_assert (greg <= PARAM_REGS);
2463 }
2464
2465 /*
2466  * mono_arch_finish_dyn_call:
2467  *
2468  *   Store the result of a dyn call into the return value buffer passed to
2469  * start_dyn_call ().
2470  * This function should be as fast as possible, any work which does not depend
2471  * on the actual values of the arguments should be done in
2472  * mono_arch_dyn_call_prepare ().
2473  */
2474 void
2475 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2476 {
2477         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2478         MonoMethodSignature *sig = dinfo->sig;
2479         guint8 *ret = ((DynCallArgs*)buf)->ret;
2480         mgreg_t res = ((DynCallArgs*)buf)->res;
2481
2482         switch (mono_type_get_underlying_type (sig->ret)->type) {
2483         case MONO_TYPE_VOID:
2484                 *(gpointer*)ret = NULL;
2485                 break;
2486         case MONO_TYPE_STRING:
2487         case MONO_TYPE_CLASS:
2488         case MONO_TYPE_ARRAY:
2489         case MONO_TYPE_SZARRAY:
2490         case MONO_TYPE_OBJECT:
2491         case MONO_TYPE_I:
2492         case MONO_TYPE_U:
2493         case MONO_TYPE_PTR:
2494                 *(gpointer*)ret = (gpointer)res;
2495                 break;
2496         case MONO_TYPE_I1:
2497                 *(gint8*)ret = res;
2498                 break;
2499         case MONO_TYPE_U1:
2500         case MONO_TYPE_BOOLEAN:
2501                 *(guint8*)ret = res;
2502                 break;
2503         case MONO_TYPE_I2:
2504                 *(gint16*)ret = res;
2505                 break;
2506         case MONO_TYPE_U2:
2507         case MONO_TYPE_CHAR:
2508                 *(guint16*)ret = res;
2509                 break;
2510         case MONO_TYPE_I4:
2511                 *(gint32*)ret = res;
2512                 break;
2513         case MONO_TYPE_U4:
2514                 *(guint32*)ret = res;
2515                 break;
2516         case MONO_TYPE_I8:
2517                 *(gint64*)ret = res;
2518                 break;
2519         case MONO_TYPE_U8:
2520                 *(guint64*)ret = res;
2521                 break;
2522         case MONO_TYPE_GENERICINST:
2523                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2524                         *(gpointer*)ret = (gpointer)res;
2525                         break;
2526                 } else {
2527                         /* Fall through */
2528                 }
2529         case MONO_TYPE_VALUETYPE:
2530                 if (dinfo->cinfo->vtype_retaddr) {
2531                         /* Nothing to do */
2532                 } else {
2533                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2534
2535                         g_assert (ainfo->storage == ArgValuetypeInReg);
2536
2537                         if (ainfo->pair_storage [0] != ArgNone) {
2538                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2539                                 ((mgreg_t*)ret)[0] = res;
2540                         }
2541
2542                         g_assert (ainfo->pair_storage [1] == ArgNone);
2543                 }
2544                 break;
2545         default:
2546                 g_assert_not_reached ();
2547         }
2548 }
2549
2550 /* emit an exception if condition is fail */
2551 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2552         do {                                                        \
2553                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2554                 if (tins == NULL) {                                                                             \
2555                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2556                                         MONO_PATCH_INFO_EXC, exc_name);  \
2557                         x86_branch32 (code, cond, 0, signed);               \
2558                 } else {        \
2559                         EMIT_COND_BRANCH (tins, cond, signed);  \
2560                 }                       \
2561         } while (0);
2562
2563 #define EMIT_FPCOMPARE(code) do { \
2564         amd64_fcompp (code); \
2565         amd64_fnstsw (code); \
2566 } while (0);
2567
2568 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2569     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2570         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2571         amd64_ ##op (code); \
2572         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2573         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2574 } while (0);
2575
2576 static guint8*
2577 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2578 {
2579         gboolean no_patch = FALSE;
2580
2581         /*
2582          * FIXME: Add support for thunks
2583          */
2584         {
2585                 gboolean near_call = FALSE;
2586
2587                 /*
2588                  * Indirect calls are expensive so try to make a near call if possible.
2589                  * The caller memory is allocated by the code manager so it is
2590                  * guaranteed to be at a 32 bit offset.
2591                  */
2592
2593                 if (patch_type != MONO_PATCH_INFO_ABS) {
2594                         /* The target is in memory allocated using the code manager */
2595                         near_call = TRUE;
2596
2597                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2598                                 if (((MonoMethod*)data)->klass->image->aot_module)
2599                                         /* The callee might be an AOT method */
2600                                         near_call = FALSE;
2601                                 if (((MonoMethod*)data)->dynamic)
2602                                         /* The target is in malloc-ed memory */
2603                                         near_call = FALSE;
2604                         }
2605
2606                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2607                                 /*
2608                                  * The call might go directly to a native function without
2609                                  * the wrapper.
2610                                  */
2611                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2612                                 if (mi) {
2613                                         gconstpointer target = mono_icall_get_wrapper (mi);
2614                                         if ((((guint64)target) >> 32) != 0)
2615                                                 near_call = FALSE;
2616                                 }
2617                         }
2618                 }
2619                 else {
2620                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2621                                 /*
2622                                  * This is not really an optimization, but required because the
2623                                  * generic class init trampolines use R11 to pass the vtable.
2624                                  */
2625                                 near_call = TRUE;
2626                         } else {
2627                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2628                                 if (info) {
2629                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2630                                                 strstr (cfg->method->name, info->name)) {
2631                                                 /* A call to the wrapped function */
2632                                                 if ((((guint64)data) >> 32) == 0)
2633                                                         near_call = TRUE;
2634                                                 no_patch = TRUE;
2635                                         }
2636                                         else if (info->func == info->wrapper) {
2637                                                 /* No wrapper */
2638                                                 if ((((guint64)info->func) >> 32) == 0)
2639                                                         near_call = TRUE;
2640                                         }
2641                                         else {
2642                                                 /* See the comment in mono_codegen () */
2643                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2644                                                         near_call = TRUE;
2645                                         }
2646                                 }
2647                                 else if ((((guint64)data) >> 32) == 0) {
2648                                         near_call = TRUE;
2649                                         no_patch = TRUE;
2650                                 }
2651                         }
2652                 }
2653
2654                 if (cfg->method->dynamic)
2655                         /* These methods are allocated using malloc */
2656                         near_call = FALSE;
2657
2658 #ifdef MONO_ARCH_NOMAP32BIT
2659                 near_call = FALSE;
2660 #endif
2661
2662                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2663                 if (optimize_for_xen)
2664                         near_call = FALSE;
2665
2666                 if (cfg->compile_aot) {
2667                         near_call = TRUE;
2668                         no_patch = TRUE;
2669                 }
2670
2671                 if (near_call) {
2672                         /*
2673                          * Align the call displacement to an address divisible by 4 so it does
2674                          * not span cache lines. This is required for code patching to work on SMP
2675                          * systems.
2676                          */
2677                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2678                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2679                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2680                         amd64_call_code (code, 0);
2681                 }
2682                 else {
2683                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2684                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2685                         amd64_call_reg (code, GP_SCRATCH_REG);
2686                 }
2687         }
2688
2689         return code;
2690 }
2691
2692 static inline guint8*
2693 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2694 {
2695 #ifdef HOST_WIN32
2696         if (win64_adjust_stack)
2697                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2698 #endif
2699         code = emit_call_body (cfg, code, patch_type, data);
2700 #ifdef HOST_WIN32
2701         if (win64_adjust_stack)
2702                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2703 #endif
2704
2705         return code;
2706 }
2707
2708 static inline int
2709 store_membase_imm_to_store_membase_reg (int opcode)
2710 {
2711         switch (opcode) {
2712         case OP_STORE_MEMBASE_IMM:
2713                 return OP_STORE_MEMBASE_REG;
2714         case OP_STOREI4_MEMBASE_IMM:
2715                 return OP_STOREI4_MEMBASE_REG;
2716         case OP_STOREI8_MEMBASE_IMM:
2717                 return OP_STOREI8_MEMBASE_REG;
2718         }
2719
2720         return -1;
2721 }
2722
2723 #ifndef DISABLE_JIT
2724
2725 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2726
2727 /*
2728  * mono_arch_peephole_pass_1:
2729  *
2730  *   Perform peephole opts which should/can be performed before local regalloc
2731  */
2732 void
2733 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2734 {
2735         MonoInst *ins, *n;
2736
2737         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2738                 MonoInst *last_ins = ins->prev;
2739
2740                 switch (ins->opcode) {
2741                 case OP_ADD_IMM:
2742                 case OP_IADD_IMM:
2743                 case OP_LADD_IMM:
2744                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2745                                 /*
2746                                  * X86_LEA is like ADD, but doesn't have the
2747                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2748                                  * its operand to 64 bit.
2749                                  */
2750                                 ins->opcode = OP_X86_LEA_MEMBASE;
2751                                 ins->inst_basereg = ins->sreg1;
2752                         }
2753                         break;
2754                 case OP_LXOR:
2755                 case OP_IXOR:
2756                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2757                                 MonoInst *ins2;
2758
2759                                 /*
2760                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2761                                  * the latter has length 2-3 instead of 6 (reverse constant
2762                                  * propagation). These instruction sequences are very common
2763                                  * in the initlocals bblock.
2764                                  */
2765                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2766                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2767                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2768                                                 ins2->sreg1 = ins->dreg;
2769                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2770                                                 /* Continue */
2771                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2772                                                 NULLIFY_INS (ins2);
2773                                                 /* Continue */
2774                                         } else {
2775                                                 break;
2776                                         }
2777                                 }
2778                         }
2779                         break;
2780                 case OP_COMPARE_IMM:
2781                 case OP_LCOMPARE_IMM:
2782                         /* OP_COMPARE_IMM (reg, 0)
2783                          * -->
2784                          * OP_AMD64_TEST_NULL (reg)
2785                          */
2786                         if (!ins->inst_imm)
2787                                 ins->opcode = OP_AMD64_TEST_NULL;
2788                         break;
2789                 case OP_ICOMPARE_IMM:
2790                         if (!ins->inst_imm)
2791                                 ins->opcode = OP_X86_TEST_NULL;
2792                         break;
2793                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2794                         /*
2795                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2796                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2797                          * -->
2798                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2799                          * OP_COMPARE_IMM reg, imm
2800                          *
2801                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2802                          */
2803                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2804                             ins->inst_basereg == last_ins->inst_destbasereg &&
2805                             ins->inst_offset == last_ins->inst_offset) {
2806                                         ins->opcode = OP_ICOMPARE_IMM;
2807                                         ins->sreg1 = last_ins->sreg1;
2808
2809                                         /* check if we can remove cmp reg,0 with test null */
2810                                         if (!ins->inst_imm)
2811                                                 ins->opcode = OP_X86_TEST_NULL;
2812                                 }
2813
2814                         break;
2815                 }
2816
2817                 mono_peephole_ins (bb, ins);
2818         }
2819 }
2820
2821 void
2822 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2823 {
2824         MonoInst *ins, *n;
2825
2826         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2827                 switch (ins->opcode) {
2828                 case OP_ICONST:
2829                 case OP_I8CONST: {
2830                         /* reg = 0 -> XOR (reg, reg) */
2831                         /* XOR sets cflags on x86, so we cant do it always */
2832                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2833                                 ins->opcode = OP_LXOR;
2834                                 ins->sreg1 = ins->dreg;
2835                                 ins->sreg2 = ins->dreg;
2836                                 /* Fall through */
2837                         } else {
2838                                 break;
2839                         }
2840                 }
2841                 case OP_LXOR:
2842                         /*
2843                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2844                          * 0 result into 64 bits.
2845                          */
2846                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2847                                 ins->opcode = OP_IXOR;
2848                         }
2849                         /* Fall through */
2850                 case OP_IXOR:
2851                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2852                                 MonoInst *ins2;
2853
2854                                 /*
2855                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2856                                  * the latter has length 2-3 instead of 6 (reverse constant
2857                                  * propagation). These instruction sequences are very common
2858                                  * in the initlocals bblock.
2859                                  */
2860                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2861                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2862                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2863                                                 ins2->sreg1 = ins->dreg;
2864                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START)) {
2865                                                 /* Continue */
2866                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2867                                                 NULLIFY_INS (ins2);
2868                                                 /* Continue */
2869                                         } else {
2870                                                 break;
2871                                         }
2872                                 }
2873                         }
2874                         break;
2875                 case OP_IADD_IMM:
2876                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2877                                 ins->opcode = OP_X86_INC_REG;
2878                         break;
2879                 case OP_ISUB_IMM:
2880                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2881                                 ins->opcode = OP_X86_DEC_REG;
2882                         break;
2883                 }
2884
2885                 mono_peephole_ins (bb, ins);
2886         }
2887 }
2888
2889 #define NEW_INS(cfg,ins,dest,op) do {   \
2890                 MONO_INST_NEW ((cfg), (dest), (op)); \
2891         (dest)->cil_code = (ins)->cil_code; \
2892         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2893         } while (0)
2894
2895 /*
2896  * mono_arch_lowering_pass:
2897  *
2898  *  Converts complex opcodes into simpler ones so that each IR instruction
2899  * corresponds to one machine instruction.
2900  */
2901 void
2902 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2903 {
2904         MonoInst *ins, *n, *temp;
2905
2906         /*
2907          * FIXME: Need to add more instructions, but the current machine
2908          * description can't model some parts of the composite instructions like
2909          * cdq.
2910          */
2911         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2912                 switch (ins->opcode) {
2913                 case OP_DIV_IMM:
2914                 case OP_REM_IMM:
2915                 case OP_IDIV_IMM:
2916                 case OP_IDIV_UN_IMM:
2917                 case OP_IREM_UN_IMM:
2918                         mono_decompose_op_imm (cfg, bb, ins);
2919                         break;
2920                 case OP_IREM_IMM:
2921                         /* Keep the opcode if we can implement it efficiently */
2922                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2923                                 mono_decompose_op_imm (cfg, bb, ins);
2924                         break;
2925                 case OP_COMPARE_IMM:
2926                 case OP_LCOMPARE_IMM:
2927                         if (!amd64_is_imm32 (ins->inst_imm)) {
2928                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2929                                 temp->inst_c0 = ins->inst_imm;
2930                                 temp->dreg = mono_alloc_ireg (cfg);
2931                                 ins->opcode = OP_COMPARE;
2932                                 ins->sreg2 = temp->dreg;
2933                         }
2934                         break;
2935                 case OP_LOAD_MEMBASE:
2936                 case OP_LOADI8_MEMBASE:
2937                         if (!amd64_is_imm32 (ins->inst_offset)) {
2938                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2939                                 temp->inst_c0 = ins->inst_offset;
2940                                 temp->dreg = mono_alloc_ireg (cfg);
2941                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2942                                 ins->inst_indexreg = temp->dreg;
2943                         }
2944                         break;
2945                 case OP_STORE_MEMBASE_IMM:
2946                 case OP_STOREI8_MEMBASE_IMM:
2947                         if (!amd64_is_imm32 (ins->inst_imm)) {
2948                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2949                                 temp->inst_c0 = ins->inst_imm;
2950                                 temp->dreg = mono_alloc_ireg (cfg);
2951                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2952                                 ins->sreg1 = temp->dreg;
2953                         }
2954                         break;
2955 #ifdef MONO_ARCH_SIMD_INTRINSICS
2956                 case OP_EXPAND_I1: {
2957                                 int temp_reg1 = mono_alloc_ireg (cfg);
2958                                 int temp_reg2 = mono_alloc_ireg (cfg);
2959                                 int original_reg = ins->sreg1;
2960
2961                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2962                                 temp->sreg1 = original_reg;
2963                                 temp->dreg = temp_reg1;
2964
2965                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2966                                 temp->sreg1 = temp_reg1;
2967                                 temp->dreg = temp_reg2;
2968                                 temp->inst_imm = 8;
2969
2970                                 NEW_INS (cfg, ins, temp, OP_LOR);
2971                                 temp->sreg1 = temp->dreg = temp_reg2;
2972                                 temp->sreg2 = temp_reg1;
2973
2974                                 ins->opcode = OP_EXPAND_I2;
2975                                 ins->sreg1 = temp_reg2;
2976                         }
2977                         break;
2978 #endif
2979                 default:
2980                         break;
2981                 }
2982         }
2983
2984         bb->max_vreg = cfg->next_vreg;
2985 }
2986
2987 static const int
2988 branch_cc_table [] = {
2989         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2990         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2991         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2992 };
2993
2994 /* Maps CMP_... constants to X86_CC_... constants */
2995 static const int
2996 cc_table [] = {
2997         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2998         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2999 };
3000
3001 static const int
3002 cc_signed_table [] = {
3003         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3004         FALSE, FALSE, FALSE, FALSE
3005 };
3006
3007 /*#include "cprop.c"*/
3008
3009 static unsigned char*
3010 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3011 {
3012         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3013
3014         if (size == 1)
3015                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3016         else if (size == 2)
3017                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3018         return code;
3019 }
3020
3021 static unsigned char*
3022 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3023 {
3024         int sreg = tree->sreg1;
3025         int need_touch = FALSE;
3026
3027 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3028         if (!tree->flags & MONO_INST_INIT)
3029                 need_touch = TRUE;
3030 #endif
3031
3032         if (need_touch) {
3033                 guint8* br[5];
3034
3035                 /*
3036                  * Under Windows:
3037                  * If requested stack size is larger than one page,
3038                  * perform stack-touch operation
3039                  */
3040                 /*
3041                  * Generate stack probe code.
3042                  * Under Windows, it is necessary to allocate one page at a time,
3043                  * "touching" stack after each successful sub-allocation. This is
3044                  * because of the way stack growth is implemented - there is a
3045                  * guard page before the lowest stack page that is currently commited.
3046                  * Stack normally grows sequentially so OS traps access to the
3047                  * guard page and commits more pages when needed.
3048                  */
3049                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3050                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3051
3052                 br[2] = code; /* loop */
3053                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3054                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3055                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3056                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3057                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3058                 amd64_patch (br[3], br[2]);
3059                 amd64_test_reg_reg (code, sreg, sreg);
3060                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3061                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3062
3063                 br[1] = code; x86_jump8 (code, 0);
3064
3065                 amd64_patch (br[0], code);
3066                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3067                 amd64_patch (br[1], code);
3068                 amd64_patch (br[4], code);
3069         }
3070         else
3071                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3072
3073         if (tree->flags & MONO_INST_INIT) {
3074                 int offset = 0;
3075                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3076                         amd64_push_reg (code, AMD64_RAX);
3077                         offset += 8;
3078                 }
3079                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3080                         amd64_push_reg (code, AMD64_RCX);
3081                         offset += 8;
3082                 }
3083                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3084                         amd64_push_reg (code, AMD64_RDI);
3085                         offset += 8;
3086                 }
3087
3088                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3089                 if (sreg != AMD64_RCX)
3090                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3091                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3092
3093                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3094                 if (cfg->param_area && cfg->arch.no_pushes)
3095                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3096                 amd64_cld (code);
3097                 amd64_prefix (code, X86_REP_PREFIX);
3098                 amd64_stosl (code);
3099
3100                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3101                         amd64_pop_reg (code, AMD64_RDI);
3102                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3103                         amd64_pop_reg (code, AMD64_RCX);
3104                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3105                         amd64_pop_reg (code, AMD64_RAX);
3106         }
3107         return code;
3108 }
3109
3110 static guint8*
3111 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3112 {
3113         CallInfo *cinfo;
3114         guint32 quad;
3115
3116         /* Move return value to the target register */
3117         /* FIXME: do this in the local reg allocator */
3118         switch (ins->opcode) {
3119         case OP_CALL:
3120         case OP_CALL_REG:
3121         case OP_CALL_MEMBASE:
3122         case OP_LCALL:
3123         case OP_LCALL_REG:
3124         case OP_LCALL_MEMBASE:
3125                 g_assert (ins->dreg == AMD64_RAX);
3126                 break;
3127         case OP_FCALL:
3128         case OP_FCALL_REG:
3129         case OP_FCALL_MEMBASE:
3130                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3131                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3132                 }
3133                 else {
3134                         if (ins->dreg != AMD64_XMM0)
3135                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3136                 }
3137                 break;
3138         case OP_VCALL:
3139         case OP_VCALL_REG:
3140         case OP_VCALL_MEMBASE:
3141         case OP_VCALL2:
3142         case OP_VCALL2_REG:
3143         case OP_VCALL2_MEMBASE:
3144                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3145                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3146                         MonoInst *loc = cfg->arch.vret_addr_loc;
3147
3148                         /* Load the destination address */
3149                         g_assert (loc->opcode == OP_REGOFFSET);
3150                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3151
3152                         for (quad = 0; quad < 2; quad ++) {
3153                                 switch (cinfo->ret.pair_storage [quad]) {
3154                                 case ArgInIReg:
3155                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3156                                         break;
3157                                 case ArgInFloatSSEReg:
3158                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3159                                         break;
3160                                 case ArgInDoubleSSEReg:
3161                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3162                                         break;
3163                                 case ArgNone:
3164                                         break;
3165                                 default:
3166                                         NOT_IMPLEMENTED;
3167                                 }
3168                         }
3169                 }
3170                 break;
3171         }
3172
3173         return code;
3174 }
3175
3176 #endif /* DISABLE_JIT */
3177
3178 /*
3179  * mono_amd64_emit_tls_get:
3180  * @code: buffer to store code to
3181  * @dreg: hard register where to place the result
3182  * @tls_offset: offset info
3183  *
3184  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3185  * the dreg register the item in the thread local storage identified
3186  * by tls_offset.
3187  *
3188  * Returns: a pointer to the end of the stored code
3189  */
3190 guint8*
3191 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3192 {
3193 #ifdef HOST_WIN32
3194         g_assert (tls_offset < 64);
3195         x86_prefix (code, X86_GS_PREFIX);
3196         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3197 #else
3198         if (optimize_for_xen) {
3199                 x86_prefix (code, X86_FS_PREFIX);
3200                 amd64_mov_reg_mem (code, dreg, 0, 8);
3201                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3202         } else {
3203                 x86_prefix (code, X86_FS_PREFIX);
3204                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3205         }
3206 #endif
3207         return code;
3208 }
3209
3210 #define REAL_PRINT_REG(text,reg) \
3211 mono_assert (reg >= 0); \
3212 amd64_push_reg (code, AMD64_RAX); \
3213 amd64_push_reg (code, AMD64_RDX); \
3214 amd64_push_reg (code, AMD64_RCX); \
3215 amd64_push_reg (code, reg); \
3216 amd64_push_imm (code, reg); \
3217 amd64_push_imm (code, text " %d %p\n"); \
3218 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3219 amd64_call_reg (code, AMD64_RAX); \
3220 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3221 amd64_pop_reg (code, AMD64_RCX); \
3222 amd64_pop_reg (code, AMD64_RDX); \
3223 amd64_pop_reg (code, AMD64_RAX);
3224
3225 /* benchmark and set based on cpu */
3226 #define LOOP_ALIGNMENT 8
3227 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3228
3229 #ifndef DISABLE_JIT
3230
3231 void
3232 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3233 {
3234         MonoInst *ins;
3235         MonoCallInst *call;
3236         guint offset;
3237         guint8 *code = cfg->native_code + cfg->code_len;
3238         MonoInst *last_ins = NULL;
3239         guint last_offset = 0;
3240         int max_len;
3241
3242         /* Fix max_offset estimate for each successor bb */
3243         if (cfg->opt & MONO_OPT_BRANCH) {
3244                 int current_offset = cfg->code_len;
3245                 MonoBasicBlock *current_bb;
3246                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3247                         current_bb->max_offset = current_offset;
3248                         current_offset += current_bb->max_length;
3249                 }
3250         }
3251
3252         if (cfg->opt & MONO_OPT_LOOP) {
3253                 int pad, align = LOOP_ALIGNMENT;
3254                 /* set alignment depending on cpu */
3255                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3256                         pad = align - pad;
3257                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3258                         amd64_padding (code, pad);
3259                         cfg->code_len += pad;
3260                         bb->native_offset = cfg->code_len;
3261                 }
3262         }
3263
3264         if (cfg->verbose_level > 2)
3265                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3266
3267         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3268                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3269                 g_assert (!cfg->compile_aot);
3270
3271                 cov->data [bb->dfn].cil_code = bb->cil_code;
3272                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3273                 /* this is not thread save, but good enough */
3274                 amd64_inc_membase (code, AMD64_R11, 0);
3275         }
3276
3277         offset = code - cfg->native_code;
3278
3279         mono_debug_open_block (cfg, bb, offset);
3280
3281     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3282                 x86_breakpoint (code);
3283
3284         MONO_BB_FOR_EACH_INS (bb, ins) {
3285                 offset = code - cfg->native_code;
3286
3287                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3288
3289                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3290                         cfg->code_size *= 2;
3291                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3292                         code = cfg->native_code + offset;
3293                         mono_jit_stats.code_reallocs++;
3294                 }
3295
3296                 if (cfg->debug_info)
3297                         mono_debug_record_line_number (cfg, ins, offset);
3298
3299                 switch (ins->opcode) {
3300                 case OP_BIGMUL:
3301                         amd64_mul_reg (code, ins->sreg2, TRUE);
3302                         break;
3303                 case OP_BIGMUL_UN:
3304                         amd64_mul_reg (code, ins->sreg2, FALSE);
3305                         break;
3306                 case OP_X86_SETEQ_MEMBASE:
3307                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3308                         break;
3309                 case OP_STOREI1_MEMBASE_IMM:
3310                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3311                         break;
3312                 case OP_STOREI2_MEMBASE_IMM:
3313                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3314                         break;
3315                 case OP_STOREI4_MEMBASE_IMM:
3316                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3317                         break;
3318                 case OP_STOREI1_MEMBASE_REG:
3319                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3320                         break;
3321                 case OP_STOREI2_MEMBASE_REG:
3322                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3323                         break;
3324                 case OP_STORE_MEMBASE_REG:
3325                 case OP_STOREI8_MEMBASE_REG:
3326                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3327                         break;
3328                 case OP_STOREI4_MEMBASE_REG:
3329                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3330                         break;
3331                 case OP_STORE_MEMBASE_IMM:
3332                 case OP_STOREI8_MEMBASE_IMM:
3333                         g_assert (amd64_is_imm32 (ins->inst_imm));
3334                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3335                         break;
3336                 case OP_LOAD_MEM:
3337                 case OP_LOADI8_MEM:
3338                         // FIXME: Decompose this earlier
3339                         if (amd64_is_imm32 (ins->inst_imm))
3340                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3341                         else {
3342                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3343                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3344                         }
3345                         break;
3346                 case OP_LOADI4_MEM:
3347                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3348                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3349                         break;
3350                 case OP_LOADU4_MEM:
3351                         // FIXME: Decompose this earlier
3352                         if (amd64_is_imm32 (ins->inst_imm))
3353                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3354                         else {
3355                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3356                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3357                         }
3358                         break;
3359                 case OP_LOADU1_MEM:
3360                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3361                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3362                         break;
3363                 case OP_LOADU2_MEM:
3364                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3365                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3366                         break;
3367                 case OP_LOAD_MEMBASE:
3368                 case OP_LOADI8_MEMBASE:
3369                         g_assert (amd64_is_imm32 (ins->inst_offset));
3370                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3371                         break;
3372                 case OP_LOADI4_MEMBASE:
3373                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3374                         break;
3375                 case OP_LOADU4_MEMBASE:
3376                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3377                         break;
3378                 case OP_LOADU1_MEMBASE:
3379                         /* The cpu zero extends the result into 64 bits */
3380                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3381                         break;
3382                 case OP_LOADI1_MEMBASE:
3383                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3384                         break;
3385                 case OP_LOADU2_MEMBASE:
3386                         /* The cpu zero extends the result into 64 bits */
3387                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3388                         break;
3389                 case OP_LOADI2_MEMBASE:
3390                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3391                         break;
3392                 case OP_AMD64_LOADI8_MEMINDEX:
3393                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3394                         break;
3395                 case OP_LCONV_TO_I1:
3396                 case OP_ICONV_TO_I1:
3397                 case OP_SEXT_I1:
3398                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3399                         break;
3400                 case OP_LCONV_TO_I2:
3401                 case OP_ICONV_TO_I2:
3402                 case OP_SEXT_I2:
3403                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3404                         break;
3405                 case OP_LCONV_TO_U1:
3406                 case OP_ICONV_TO_U1:
3407                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3408                         break;
3409                 case OP_LCONV_TO_U2:
3410                 case OP_ICONV_TO_U2:
3411                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3412                         break;
3413                 case OP_ZEXT_I4:
3414                         /* Clean out the upper word */
3415                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3416                         break;
3417                 case OP_SEXT_I4:
3418                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3419                         break;
3420                 case OP_COMPARE:
3421                 case OP_LCOMPARE:
3422                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3423                         break;
3424                 case OP_COMPARE_IMM:
3425                 case OP_LCOMPARE_IMM:
3426                         g_assert (amd64_is_imm32 (ins->inst_imm));
3427                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3428                         break;
3429                 case OP_X86_COMPARE_REG_MEMBASE:
3430                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3431                         break;
3432                 case OP_X86_TEST_NULL:
3433                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3434                         break;
3435                 case OP_AMD64_TEST_NULL:
3436                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3437                         break;
3438
3439                 case OP_X86_ADD_REG_MEMBASE:
3440                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3441                         break;
3442                 case OP_X86_SUB_REG_MEMBASE:
3443                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3444                         break;
3445                 case OP_X86_AND_REG_MEMBASE:
3446                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3447                         break;
3448                 case OP_X86_OR_REG_MEMBASE:
3449                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3450                         break;
3451                 case OP_X86_XOR_REG_MEMBASE:
3452                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3453                         break;
3454
3455                 case OP_X86_ADD_MEMBASE_IMM:
3456                         /* FIXME: Make a 64 version too */
3457                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3458                         break;
3459                 case OP_X86_SUB_MEMBASE_IMM:
3460                         g_assert (amd64_is_imm32 (ins->inst_imm));
3461                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3462                         break;
3463                 case OP_X86_AND_MEMBASE_IMM:
3464                         g_assert (amd64_is_imm32 (ins->inst_imm));
3465                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3466                         break;
3467                 case OP_X86_OR_MEMBASE_IMM:
3468                         g_assert (amd64_is_imm32 (ins->inst_imm));
3469                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3470                         break;
3471                 case OP_X86_XOR_MEMBASE_IMM:
3472                         g_assert (amd64_is_imm32 (ins->inst_imm));
3473                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3474                         break;
3475                 case OP_X86_ADD_MEMBASE_REG:
3476                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3477                         break;
3478                 case OP_X86_SUB_MEMBASE_REG:
3479                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3480                         break;
3481                 case OP_X86_AND_MEMBASE_REG:
3482                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3483                         break;
3484                 case OP_X86_OR_MEMBASE_REG:
3485                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3486                         break;
3487                 case OP_X86_XOR_MEMBASE_REG:
3488                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3489                         break;
3490                 case OP_X86_INC_MEMBASE:
3491                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3492                         break;
3493                 case OP_X86_INC_REG:
3494                         amd64_inc_reg_size (code, ins->dreg, 4);
3495                         break;
3496                 case OP_X86_DEC_MEMBASE:
3497                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3498                         break;
3499                 case OP_X86_DEC_REG:
3500                         amd64_dec_reg_size (code, ins->dreg, 4);
3501                         break;
3502                 case OP_X86_MUL_REG_MEMBASE:
3503                 case OP_X86_MUL_MEMBASE_REG:
3504                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3505                         break;
3506                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3507                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3508                         break;
3509                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3510                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3511                         break;
3512                 case OP_AMD64_COMPARE_MEMBASE_REG:
3513                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3514                         break;
3515                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3516                         g_assert (amd64_is_imm32 (ins->inst_imm));
3517                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3518                         break;
3519                 case OP_X86_COMPARE_MEMBASE8_IMM:
3520                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3521                         break;
3522                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3523                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3524                         break;
3525                 case OP_AMD64_COMPARE_REG_MEMBASE:
3526                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3527                         break;
3528
3529                 case OP_AMD64_ADD_REG_MEMBASE:
3530                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3531                         break;
3532                 case OP_AMD64_SUB_REG_MEMBASE:
3533                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3534                         break;
3535                 case OP_AMD64_AND_REG_MEMBASE:
3536                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3537                         break;
3538                 case OP_AMD64_OR_REG_MEMBASE:
3539                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3540                         break;
3541                 case OP_AMD64_XOR_REG_MEMBASE:
3542                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3543                         break;
3544
3545                 case OP_AMD64_ADD_MEMBASE_REG:
3546                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3547                         break;
3548                 case OP_AMD64_SUB_MEMBASE_REG:
3549                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3550                         break;
3551                 case OP_AMD64_AND_MEMBASE_REG:
3552                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3553                         break;
3554                 case OP_AMD64_OR_MEMBASE_REG:
3555                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3556                         break;
3557                 case OP_AMD64_XOR_MEMBASE_REG:
3558                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3559                         break;
3560
3561                 case OP_AMD64_ADD_MEMBASE_IMM:
3562                         g_assert (amd64_is_imm32 (ins->inst_imm));
3563                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3564                         break;
3565                 case OP_AMD64_SUB_MEMBASE_IMM:
3566                         g_assert (amd64_is_imm32 (ins->inst_imm));
3567                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3568                         break;
3569                 case OP_AMD64_AND_MEMBASE_IMM:
3570                         g_assert (amd64_is_imm32 (ins->inst_imm));
3571                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3572                         break;
3573                 case OP_AMD64_OR_MEMBASE_IMM:
3574                         g_assert (amd64_is_imm32 (ins->inst_imm));
3575                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3576                         break;
3577                 case OP_AMD64_XOR_MEMBASE_IMM:
3578                         g_assert (amd64_is_imm32 (ins->inst_imm));
3579                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3580                         break;
3581
3582                 case OP_BREAK:
3583                         amd64_breakpoint (code);
3584                         break;
3585                 case OP_RELAXED_NOP:
3586                         x86_prefix (code, X86_REP_PREFIX);
3587                         x86_nop (code);
3588                         break;
3589                 case OP_HARD_NOP:
3590                         x86_nop (code);
3591                         break;
3592                 case OP_NOP:
3593                 case OP_DUMMY_USE:
3594                 case OP_DUMMY_STORE:
3595                 case OP_NOT_REACHED:
3596                 case OP_NOT_NULL:
3597                         break;
3598                 case OP_SEQ_POINT: {
3599                         int i;
3600
3601                         if (cfg->compile_aot)
3602                                 NOT_IMPLEMENTED;
3603
3604                         /*
3605                          * Read from the single stepping trigger page. This will cause a
3606                          * SIGSEGV when single stepping is enabled.
3607                          * We do this _before_ the breakpoint, so single stepping after
3608                          * a breakpoint is hit will step to the next IL offset.
3609                          */
3610                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3611                                 if (((guint64)ss_trigger_page >> 32) == 0)
3612                                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3613                                 else {
3614                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
3615
3616                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
3617                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
3618                                 }
3619                         }
3620
3621                         /*
3622                          * This is the address which is saved in seq points,
3623                          * get_ip_for_single_step () / get_ip_for_breakpoint () needs to compute this
3624                          * from the address of the instruction causing the fault.
3625                          */
3626                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3627
3628                         /*
3629                          * A placeholder for a possible breakpoint inserted by
3630                          * mono_arch_set_breakpoint ().
3631                          */
3632                         for (i = 0; i < breakpoint_size; ++i)
3633                                 x86_nop (code);
3634                         break;
3635                 }
3636                 case OP_ADDCC:
3637                 case OP_LADD:
3638                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3639                         break;
3640                 case OP_ADC:
3641                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3642                         break;
3643                 case OP_ADD_IMM:
3644                 case OP_LADD_IMM:
3645                         g_assert (amd64_is_imm32 (ins->inst_imm));
3646                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3647                         break;
3648                 case OP_ADC_IMM:
3649                         g_assert (amd64_is_imm32 (ins->inst_imm));
3650                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3651                         break;
3652                 case OP_SUBCC:
3653                 case OP_LSUB:
3654                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3655                         break;
3656                 case OP_SBB:
3657                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3658                         break;
3659                 case OP_SUB_IMM:
3660                 case OP_LSUB_IMM:
3661                         g_assert (amd64_is_imm32 (ins->inst_imm));
3662                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3663                         break;
3664                 case OP_SBB_IMM:
3665                         g_assert (amd64_is_imm32 (ins->inst_imm));
3666                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3667                         break;
3668                 case OP_LAND:
3669                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3670                         break;
3671                 case OP_AND_IMM:
3672                 case OP_LAND_IMM:
3673                         g_assert (amd64_is_imm32 (ins->inst_imm));
3674                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3675                         break;
3676                 case OP_LMUL:
3677                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3678                         break;
3679                 case OP_MUL_IMM:
3680                 case OP_LMUL_IMM:
3681                 case OP_IMUL_IMM: {
3682                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3683
3684                         switch (ins->inst_imm) {
3685                         case 2:
3686                                 /* MOV r1, r2 */
3687                                 /* ADD r1, r1 */
3688                                 if (ins->dreg != ins->sreg1)
3689                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3690                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3691                                 break;
3692                         case 3:
3693                                 /* LEA r1, [r2 + r2*2] */
3694                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3695                                 break;
3696                         case 5:
3697                                 /* LEA r1, [r2 + r2*4] */
3698                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3699                                 break;
3700                         case 6:
3701                                 /* LEA r1, [r2 + r2*2] */
3702                                 /* ADD r1, r1          */
3703                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3704                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3705                                 break;
3706                         case 9:
3707                                 /* LEA r1, [r2 + r2*8] */
3708                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3709                                 break;
3710                         case 10:
3711                                 /* LEA r1, [r2 + r2*4] */
3712                                 /* ADD r1, r1          */
3713                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3714                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3715                                 break;
3716                         case 12:
3717                                 /* LEA r1, [r2 + r2*2] */
3718                                 /* SHL r1, 2           */
3719                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3720                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3721                                 break;
3722                         case 25:
3723                                 /* LEA r1, [r2 + r2*4] */
3724                                 /* LEA r1, [r1 + r1*4] */
3725                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3726                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3727                                 break;
3728                         case 100:
3729                                 /* LEA r1, [r2 + r2*4] */
3730                                 /* SHL r1, 2           */
3731                                 /* LEA r1, [r1 + r1*4] */
3732                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3733                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3734                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3735                                 break;
3736                         default:
3737                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3738                                 break;
3739                         }
3740                         break;
3741                 }
3742                 case OP_LDIV:
3743                 case OP_LREM:
3744                         /* Regalloc magic makes the div/rem cases the same */
3745                         if (ins->sreg2 == AMD64_RDX) {
3746                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3747                                 amd64_cdq (code);
3748                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3749                         } else {
3750                                 amd64_cdq (code);
3751                                 amd64_div_reg (code, ins->sreg2, TRUE);
3752                         }
3753                         break;
3754                 case OP_LDIV_UN:
3755                 case OP_LREM_UN:
3756                         if (ins->sreg2 == AMD64_RDX) {
3757                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3758                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3759                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3760                         } else {
3761                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3762                                 amd64_div_reg (code, ins->sreg2, FALSE);
3763                         }
3764                         break;
3765                 case OP_IDIV:
3766                 case OP_IREM:
3767                         if (ins->sreg2 == AMD64_RDX) {
3768                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3769                                 amd64_cdq_size (code, 4);
3770                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3771                         } else {
3772                                 amd64_cdq_size (code, 4);
3773                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3774                         }
3775                         break;
3776                 case OP_IDIV_UN:
3777                 case OP_IREM_UN:
3778                         if (ins->sreg2 == AMD64_RDX) {
3779                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3780                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3781                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3782                         } else {
3783                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3784                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3785                         }
3786                         break;
3787                 case OP_IREM_IMM: {
3788                         int power = mono_is_power_of_two (ins->inst_imm);
3789
3790                         g_assert (ins->sreg1 == X86_EAX);
3791                         g_assert (ins->dreg == X86_EAX);
3792                         g_assert (power >= 0);
3793
3794                         if (power == 0) {
3795                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3796                                 break;
3797                         }
3798
3799                         /* Based on gcc code */
3800
3801                         /* Add compensation for negative dividents */
3802                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3803                         if (power > 1)
3804                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3805                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3806                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3807                         /* Compute remainder */
3808                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3809                         /* Remove compensation */
3810                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3811                         break;
3812                 }
3813                 case OP_LMUL_OVF:
3814                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3815                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3816                         break;
3817                 case OP_LOR:
3818                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3819                         break;
3820                 case OP_OR_IMM:
3821                 case OP_LOR_IMM:
3822                         g_assert (amd64_is_imm32 (ins->inst_imm));
3823                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3824                         break;
3825                 case OP_LXOR:
3826                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3827                         break;
3828                 case OP_XOR_IMM:
3829                 case OP_LXOR_IMM:
3830                         g_assert (amd64_is_imm32 (ins->inst_imm));
3831                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3832                         break;
3833                 case OP_LSHL:
3834                         g_assert (ins->sreg2 == AMD64_RCX);
3835                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3836                         break;
3837                 case OP_LSHR:
3838                         g_assert (ins->sreg2 == AMD64_RCX);
3839                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3840                         break;
3841                 case OP_SHR_IMM:
3842                         g_assert (amd64_is_imm32 (ins->inst_imm));
3843                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3844                         break;
3845                 case OP_LSHR_IMM:
3846                         g_assert (amd64_is_imm32 (ins->inst_imm));
3847                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3848                         break;
3849                 case OP_SHR_UN_IMM:
3850                         g_assert (amd64_is_imm32 (ins->inst_imm));
3851                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3852                         break;
3853                 case OP_LSHR_UN_IMM:
3854                         g_assert (amd64_is_imm32 (ins->inst_imm));
3855                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3856                         break;
3857                 case OP_LSHR_UN:
3858                         g_assert (ins->sreg2 == AMD64_RCX);
3859                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3860                         break;
3861                 case OP_SHL_IMM:
3862                         g_assert (amd64_is_imm32 (ins->inst_imm));
3863                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3864                         break;
3865                 case OP_LSHL_IMM:
3866                         g_assert (amd64_is_imm32 (ins->inst_imm));
3867                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3868                         break;
3869
3870                 case OP_IADDCC:
3871                 case OP_IADD:
3872                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3873                         break;
3874                 case OP_IADC:
3875                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3876                         break;
3877                 case OP_IADD_IMM:
3878                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3879                         break;
3880                 case OP_IADC_IMM:
3881                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3882                         break;
3883                 case OP_ISUBCC:
3884                 case OP_ISUB:
3885                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3886                         break;
3887                 case OP_ISBB:
3888                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3889                         break;
3890                 case OP_ISUB_IMM:
3891                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3892                         break;
3893                 case OP_ISBB_IMM:
3894                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3895                         break;
3896                 case OP_IAND:
3897                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3898                         break;
3899                 case OP_IAND_IMM:
3900                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3901                         break;
3902                 case OP_IOR:
3903                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3904                         break;
3905                 case OP_IOR_IMM:
3906                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3907                         break;
3908                 case OP_IXOR:
3909                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3910                         break;
3911                 case OP_IXOR_IMM:
3912                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3913                         break;
3914                 case OP_INEG:
3915                         amd64_neg_reg_size (code, ins->sreg1, 4);
3916                         break;
3917                 case OP_INOT:
3918                         amd64_not_reg_size (code, ins->sreg1, 4);
3919                         break;
3920                 case OP_ISHL:
3921                         g_assert (ins->sreg2 == AMD64_RCX);
3922                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3923                         break;
3924                 case OP_ISHR:
3925                         g_assert (ins->sreg2 == AMD64_RCX);
3926                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3927                         break;
3928                 case OP_ISHR_IMM:
3929                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3930                         break;
3931                 case OP_ISHR_UN_IMM:
3932                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3933                         break;
3934                 case OP_ISHR_UN:
3935                         g_assert (ins->sreg2 == AMD64_RCX);
3936                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3937                         break;
3938                 case OP_ISHL_IMM:
3939                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3940                         break;
3941                 case OP_IMUL:
3942                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3943                         break;
3944                 case OP_IMUL_OVF:
3945                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3946                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3947                         break;
3948                 case OP_IMUL_OVF_UN:
3949                 case OP_LMUL_OVF_UN: {
3950                         /* the mul operation and the exception check should most likely be split */
3951                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3952                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3953                         /*g_assert (ins->sreg2 == X86_EAX);
3954                         g_assert (ins->dreg == X86_EAX);*/
3955                         if (ins->sreg2 == X86_EAX) {
3956                                 non_eax_reg = ins->sreg1;
3957                         } else if (ins->sreg1 == X86_EAX) {
3958                                 non_eax_reg = ins->sreg2;
3959                         } else {
3960                                 /* no need to save since we're going to store to it anyway */
3961                                 if (ins->dreg != X86_EAX) {
3962                                         saved_eax = TRUE;
3963                                         amd64_push_reg (code, X86_EAX);
3964                                 }
3965                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3966                                 non_eax_reg = ins->sreg2;
3967                         }
3968                         if (ins->dreg == X86_EDX) {
3969                                 if (!saved_eax) {
3970                                         saved_eax = TRUE;
3971                                         amd64_push_reg (code, X86_EAX);
3972                                 }
3973                         } else {
3974                                 saved_edx = TRUE;
3975                                 amd64_push_reg (code, X86_EDX);
3976                         }
3977                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3978                         /* save before the check since pop and mov don't change the flags */
3979                         if (ins->dreg != X86_EAX)
3980                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3981                         if (saved_edx)
3982                                 amd64_pop_reg (code, X86_EDX);
3983                         if (saved_eax)
3984                                 amd64_pop_reg (code, X86_EAX);
3985                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3986                         break;
3987                 }
3988                 case OP_ICOMPARE:
3989                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3990                         break;
3991                 case OP_ICOMPARE_IMM:
3992                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3993                         break;
3994                 case OP_IBEQ:
3995                 case OP_IBLT:
3996                 case OP_IBGT:
3997                 case OP_IBGE:
3998                 case OP_IBLE:
3999                 case OP_LBEQ:
4000                 case OP_LBLT:
4001                 case OP_LBGT:
4002                 case OP_LBGE:
4003                 case OP_LBLE:
4004                 case OP_IBNE_UN:
4005                 case OP_IBLT_UN:
4006                 case OP_IBGT_UN:
4007                 case OP_IBGE_UN:
4008                 case OP_IBLE_UN:
4009                 case OP_LBNE_UN:
4010                 case OP_LBLT_UN:
4011                 case OP_LBGT_UN:
4012                 case OP_LBGE_UN:
4013                 case OP_LBLE_UN:
4014                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4015                         break;
4016
4017                 case OP_CMOV_IEQ:
4018                 case OP_CMOV_IGE:
4019                 case OP_CMOV_IGT:
4020                 case OP_CMOV_ILE:
4021                 case OP_CMOV_ILT:
4022                 case OP_CMOV_INE_UN:
4023                 case OP_CMOV_IGE_UN:
4024                 case OP_CMOV_IGT_UN:
4025                 case OP_CMOV_ILE_UN:
4026                 case OP_CMOV_ILT_UN:
4027                 case OP_CMOV_LEQ:
4028                 case OP_CMOV_LGE:
4029                 case OP_CMOV_LGT:
4030                 case OP_CMOV_LLE:
4031                 case OP_CMOV_LLT:
4032                 case OP_CMOV_LNE_UN:
4033                 case OP_CMOV_LGE_UN:
4034                 case OP_CMOV_LGT_UN:
4035                 case OP_CMOV_LLE_UN:
4036                 case OP_CMOV_LLT_UN:
4037                         g_assert (ins->dreg == ins->sreg1);
4038                         /* This needs to operate on 64 bit values */
4039                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4040                         break;
4041
4042                 case OP_LNOT:
4043                         amd64_not_reg (code, ins->sreg1);
4044                         break;
4045                 case OP_LNEG:
4046                         amd64_neg_reg (code, ins->sreg1);
4047                         break;
4048
4049                 case OP_ICONST:
4050                 case OP_I8CONST:
4051                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4052                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4053                         else
4054                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4055                         break;
4056                 case OP_AOTCONST:
4057                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4058                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
4059                         break;
4060                 case OP_JUMP_TABLE:
4061                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4062                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4063                         break;
4064                 case OP_MOVE:
4065                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4066                         break;
4067                 case OP_AMD64_SET_XMMREG_R4: {
4068                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4069                         break;
4070                 }
4071                 case OP_AMD64_SET_XMMREG_R8: {
4072                         if (ins->dreg != ins->sreg1)
4073                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4074                         break;
4075                 }
4076                 case OP_TAILCALL: {
4077                         MonoCallInst *call = (MonoCallInst*)ins;
4078                         int pos = 0, i;
4079
4080                         /* FIXME: no tracing support... */
4081                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4082                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
4083
4084                         g_assert (!cfg->method->save_lmf);
4085
4086                         if (cfg->arch.omit_fp) {
4087                                 guint32 save_offset = 0;
4088                                 /* Pop callee-saved registers */
4089                                 for (i = 0; i < AMD64_NREG; ++i)
4090                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4091                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4092                                                 save_offset += 8;
4093                                         }
4094                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4095
4096                                 // FIXME:
4097                                 if (call->stack_usage)
4098                                         NOT_IMPLEMENTED;
4099                         }
4100                         else {
4101                                 for (i = 0; i < AMD64_NREG; ++i)
4102                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4103                                                 pos -= sizeof (gpointer);
4104
4105                                 /* Restore callee-saved registers */
4106                                 for (i = AMD64_NREG - 1; i > 0; --i) {
4107                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4108                                                 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4109                                                 pos += 8;
4110                                         }
4111                                 }
4112
4113                                 /* Copy arguments on the stack to our argument area */
4114                                 for (i = 0; i < call->stack_usage; i += 8) {
4115                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, 8);
4116                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, 8);
4117                                 }
4118
4119                                 if (pos)
4120                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4121
4122                                 amd64_leave (code);
4123                         }
4124
4125                         offset = code - cfg->native_code;
4126                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4127                         if (cfg->compile_aot)
4128                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4129                         else
4130                                 amd64_set_reg_template (code, AMD64_R11);
4131                         amd64_jump_reg (code, AMD64_R11);
4132                         break;
4133                 }
4134                 case OP_CHECK_THIS:
4135                         /* ensure ins->sreg1 is not NULL */
4136                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4137                         break;
4138                 case OP_ARGLIST: {
4139                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4140                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4141                         break;
4142                 }
4143                 case OP_CALL:
4144                 case OP_FCALL:
4145                 case OP_LCALL:
4146                 case OP_VCALL:
4147                 case OP_VCALL2:
4148                 case OP_VOIDCALL:
4149                         call = (MonoCallInst*)ins;
4150                         /*
4151                          * The AMD64 ABI forces callers to know about varargs.
4152                          */
4153                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4154                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4155                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4156                                 /*
4157                                  * Since the unmanaged calling convention doesn't contain a
4158                                  * 'vararg' entry, we have to treat every pinvoke call as a
4159                                  * potential vararg call.
4160                                  */
4161                                 guint32 nregs, i;
4162                                 nregs = 0;
4163                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4164                                         if (call->used_fregs & (1 << i))
4165                                                 nregs ++;
4166                                 if (!nregs)
4167                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4168                                 else
4169                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4170                         }
4171
4172                         if (ins->flags & MONO_INST_HAS_METHOD)
4173                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4174                         else
4175                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4176                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4177                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4178                         code = emit_move_return_value (cfg, ins, code);
4179                         break;
4180                 case OP_FCALL_REG:
4181                 case OP_LCALL_REG:
4182                 case OP_VCALL_REG:
4183                 case OP_VCALL2_REG:
4184                 case OP_VOIDCALL_REG:
4185                 case OP_CALL_REG:
4186                         call = (MonoCallInst*)ins;
4187
4188                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4189                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4190                                 ins->sreg1 = AMD64_R11;
4191                         }
4192
4193                         /*
4194                          * The AMD64 ABI forces callers to know about varargs.
4195                          */
4196                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4197                                 if (ins->sreg1 == AMD64_RAX) {
4198                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4199                                         ins->sreg1 = AMD64_R11;
4200                                 }
4201                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4202                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4203                                 /*
4204                                  * Since the unmanaged calling convention doesn't contain a
4205                                  * 'vararg' entry, we have to treat every pinvoke call as a
4206                                  * potential vararg call.
4207                                  */
4208                                 guint32 nregs, i;
4209                                 nregs = 0;
4210                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4211                                         if (call->used_fregs & (1 << i))
4212                                                 nregs ++;
4213                                 if (ins->sreg1 == AMD64_RAX) {
4214                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4215                                         ins->sreg1 = AMD64_R11;
4216                                 }
4217                                 if (!nregs)
4218                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4219                                 else
4220                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4221                         }
4222
4223                         amd64_call_reg (code, ins->sreg1);
4224                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4225                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4226                         code = emit_move_return_value (cfg, ins, code);
4227                         break;
4228                 case OP_FCALL_MEMBASE:
4229                 case OP_LCALL_MEMBASE:
4230                 case OP_VCALL_MEMBASE:
4231                 case OP_VCALL2_MEMBASE:
4232                 case OP_VOIDCALL_MEMBASE:
4233                 case OP_CALL_MEMBASE:
4234                         call = (MonoCallInst*)ins;
4235
4236                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4237                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4238                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4239                         code = emit_move_return_value (cfg, ins, code);
4240                         break;
4241                 case OP_DYN_CALL: {
4242                         int i;
4243                         MonoInst *var = cfg->dyn_call_var;
4244
4245                         g_assert (var->opcode == OP_REGOFFSET);
4246
4247                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4248                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4249                         /* r10 = ftn */
4250                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4251
4252                         /* Save args buffer */
4253                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4254
4255                         /* Set argument registers */
4256                         for (i = 0; i < PARAM_REGS; ++i)
4257                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4258
4259                         /* Make the call */
4260                         amd64_call_reg (code, AMD64_R10);
4261
4262                         /* Save result */
4263                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4264                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4265                         break;
4266                 }
4267                 case OP_AMD64_SAVE_SP_TO_LMF:
4268                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4269                         break;
4270                 case OP_X86_PUSH:
4271                         g_assert (!cfg->arch.no_pushes);
4272                         amd64_push_reg (code, ins->sreg1);
4273                         break;
4274                 case OP_X86_PUSH_IMM:
4275                         g_assert (!cfg->arch.no_pushes);
4276                         g_assert (amd64_is_imm32 (ins->inst_imm));
4277                         amd64_push_imm (code, ins->inst_imm);
4278                         break;
4279                 case OP_X86_PUSH_MEMBASE:
4280                         g_assert (!cfg->arch.no_pushes);
4281                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4282                         break;
4283                 case OP_X86_PUSH_OBJ: {
4284                         int size = ALIGN_TO (ins->inst_imm, 8);
4285
4286                         g_assert (!cfg->arch.no_pushes);
4287
4288                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4289                         amd64_push_reg (code, AMD64_RDI);
4290                         amd64_push_reg (code, AMD64_RSI);
4291                         amd64_push_reg (code, AMD64_RCX);
4292                         if (ins->inst_offset)
4293                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4294                         else
4295                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4296                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4297                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4298                         amd64_cld (code);
4299                         amd64_prefix (code, X86_REP_PREFIX);
4300                         amd64_movsd (code);
4301                         amd64_pop_reg (code, AMD64_RCX);
4302                         amd64_pop_reg (code, AMD64_RSI);
4303                         amd64_pop_reg (code, AMD64_RDI);
4304                         break;
4305                 }
4306                 case OP_X86_LEA:
4307                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4308                         break;
4309                 case OP_X86_LEA_MEMBASE:
4310                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4311                         break;
4312                 case OP_X86_XCHG:
4313                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4314                         break;
4315                 case OP_LOCALLOC:
4316                         /* keep alignment */
4317                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4318                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4319                         code = mono_emit_stack_alloc (cfg, code, ins);
4320                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4321                         if (cfg->param_area && cfg->arch.no_pushes)
4322                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4323                         break;
4324                 case OP_LOCALLOC_IMM: {
4325                         guint32 size = ins->inst_imm;
4326                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4327
4328                         if (ins->flags & MONO_INST_INIT) {
4329                                 if (size < 64) {
4330                                         int i;
4331
4332                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4333                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4334
4335                                         for (i = 0; i < size; i += 8)
4336                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4337                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4338                                 } else {
4339                                         amd64_mov_reg_imm (code, ins->dreg, size);
4340                                         ins->sreg1 = ins->dreg;
4341
4342                                         code = mono_emit_stack_alloc (cfg, code, ins);
4343                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4344                                 }
4345                         } else {
4346                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4347                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4348                         }
4349                         if (cfg->param_area && cfg->arch.no_pushes)
4350                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4351                         break;
4352                 }
4353                 case OP_THROW: {
4354                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4355                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4356                                              (gpointer)"mono_arch_throw_exception", FALSE);
4357                         break;
4358                 }
4359                 case OP_RETHROW: {
4360                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4361                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4362                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4363                         break;
4364                 }
4365                 case OP_CALL_HANDLER:
4366                         /* Align stack */
4367                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4368                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4369                         amd64_call_imm (code, 0);
4370                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4371                         /* Restore stack alignment */
4372                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4373                         break;
4374                 case OP_START_HANDLER: {
4375                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4376                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4377
4378                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4379                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4380                                 cfg->param_area && cfg->arch.no_pushes) {
4381                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4382                         }
4383                         break;
4384                 }
4385                 case OP_ENDFINALLY: {
4386                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4387                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4388                         amd64_ret (code);
4389                         break;
4390                 }
4391                 case OP_ENDFILTER: {
4392                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4393                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4394                         /* The local allocator will put the result into RAX */
4395                         amd64_ret (code);
4396                         break;
4397                 }
4398
4399                 case OP_LABEL:
4400                         ins->inst_c0 = code - cfg->native_code;
4401                         break;
4402                 case OP_BR:
4403                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4404                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4405                         //break;
4406                                 if (ins->inst_target_bb->native_offset) {
4407                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4408                                 } else {
4409                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4410                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4411                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4412                                                 x86_jump8 (code, 0);
4413                                         else
4414                                                 x86_jump32 (code, 0);
4415                         }
4416                         break;
4417                 case OP_BR_REG:
4418                         amd64_jump_reg (code, ins->sreg1);
4419                         break;
4420                 case OP_CEQ:
4421                 case OP_LCEQ:
4422                 case OP_ICEQ:
4423                 case OP_CLT:
4424                 case OP_LCLT:
4425                 case OP_ICLT:
4426                 case OP_CGT:
4427                 case OP_ICGT:
4428                 case OP_LCGT:
4429                 case OP_CLT_UN:
4430                 case OP_LCLT_UN:
4431                 case OP_ICLT_UN:
4432                 case OP_CGT_UN:
4433                 case OP_LCGT_UN:
4434                 case OP_ICGT_UN:
4435                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4436                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4437                         break;
4438                 case OP_COND_EXC_EQ:
4439                 case OP_COND_EXC_NE_UN:
4440                 case OP_COND_EXC_LT:
4441                 case OP_COND_EXC_LT_UN:
4442                 case OP_COND_EXC_GT:
4443                 case OP_COND_EXC_GT_UN:
4444                 case OP_COND_EXC_GE:
4445                 case OP_COND_EXC_GE_UN:
4446                 case OP_COND_EXC_LE:
4447                 case OP_COND_EXC_LE_UN:
4448                 case OP_COND_EXC_IEQ:
4449                 case OP_COND_EXC_INE_UN:
4450                 case OP_COND_EXC_ILT:
4451                 case OP_COND_EXC_ILT_UN:
4452                 case OP_COND_EXC_IGT:
4453                 case OP_COND_EXC_IGT_UN:
4454                 case OP_COND_EXC_IGE:
4455                 case OP_COND_EXC_IGE_UN:
4456                 case OP_COND_EXC_ILE:
4457                 case OP_COND_EXC_ILE_UN:
4458                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4459                         break;
4460                 case OP_COND_EXC_OV:
4461                 case OP_COND_EXC_NO:
4462                 case OP_COND_EXC_C:
4463                 case OP_COND_EXC_NC:
4464                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4465                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4466                         break;
4467                 case OP_COND_EXC_IOV:
4468                 case OP_COND_EXC_INO:
4469                 case OP_COND_EXC_IC:
4470                 case OP_COND_EXC_INC:
4471                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4472                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4473                         break;
4474
4475                 /* floating point opcodes */
4476                 case OP_R8CONST: {
4477                         double d = *(double *)ins->inst_p0;
4478
4479                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4480                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4481                         }
4482                         else {
4483                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4484                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4485                         }
4486                         break;
4487                 }
4488                 case OP_R4CONST: {
4489                         float f = *(float *)ins->inst_p0;
4490
4491                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4492                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4493                         }
4494                         else {
4495                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4496                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4497                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4498                         }
4499                         break;
4500                 }
4501                 case OP_STORER8_MEMBASE_REG:
4502                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4503                         break;
4504                 case OP_LOADR8_MEMBASE:
4505                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4506                         break;
4507                 case OP_STORER4_MEMBASE_REG:
4508                         /* This requires a double->single conversion */
4509                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4510                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4511                         break;
4512                 case OP_LOADR4_MEMBASE:
4513                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4514                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4515                         break;
4516                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4517                 case OP_ICONV_TO_R8:
4518                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4519                         break;
4520                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4521                 case OP_LCONV_TO_R8:
4522                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4523                         break;
4524                 case OP_FCONV_TO_R4:
4525                         /* FIXME: nothing to do ?? */
4526                         break;
4527                 case OP_FCONV_TO_I1:
4528                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4529                         break;
4530                 case OP_FCONV_TO_U1:
4531                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4532                         break;
4533                 case OP_FCONV_TO_I2:
4534                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4535                         break;
4536                 case OP_FCONV_TO_U2:
4537                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4538                         break;
4539                 case OP_FCONV_TO_U4:
4540                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4541                         break;
4542                 case OP_FCONV_TO_I4:
4543                 case OP_FCONV_TO_I:
4544                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4545                         break;
4546                 case OP_FCONV_TO_I8:
4547                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4548                         break;
4549                 case OP_LCONV_TO_R_UN: {
4550                         guint8 *br [2];
4551
4552                         /* Based on gcc code */
4553                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4554                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4555
4556                         /* Positive case */
4557                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4558                         br [1] = code; x86_jump8 (code, 0);
4559                         amd64_patch (br [0], code);
4560
4561                         /* Negative case */
4562                         /* Save to the red zone */
4563                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4564                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4565                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4566                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4567                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4568                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4569                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4570                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4571                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4572                         /* Restore */
4573                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4574                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4575                         amd64_patch (br [1], code);
4576                         break;
4577                 }
4578                 case OP_LCONV_TO_OVF_U4:
4579                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4580                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4581                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4582                         break;
4583                 case OP_LCONV_TO_OVF_I4_UN:
4584                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4585                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4586                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4587                         break;
4588                 case OP_FMOVE:
4589                         if (ins->dreg != ins->sreg1)
4590                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4591                         break;
4592                 case OP_FADD:
4593                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4594                         break;
4595                 case OP_FSUB:
4596                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4597                         break;
4598                 case OP_FMUL:
4599                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4600                         break;
4601                 case OP_FDIV:
4602                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4603                         break;
4604                 case OP_FNEG: {
4605                         static double r8_0 = -0.0;
4606
4607                         g_assert (ins->sreg1 == ins->dreg);
4608
4609                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4610                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4611                         break;
4612                 }
4613                 case OP_SIN:
4614                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4615                         break;
4616                 case OP_COS:
4617                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4618                         break;
4619                 case OP_ABS: {
4620                         static guint64 d = 0x7fffffffffffffffUL;
4621
4622                         g_assert (ins->sreg1 == ins->dreg);
4623
4624                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4625                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4626                         break;
4627                 }
4628                 case OP_SQRT:
4629                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4630                         break;
4631                 case OP_IMIN:
4632                         g_assert (cfg->opt & MONO_OPT_CMOV);
4633                         g_assert (ins->dreg == ins->sreg1);
4634                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4635                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4636                         break;
4637                 case OP_IMIN_UN:
4638                         g_assert (cfg->opt & MONO_OPT_CMOV);
4639                         g_assert (ins->dreg == ins->sreg1);
4640                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4641                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4642                         break;
4643                 case OP_IMAX:
4644                         g_assert (cfg->opt & MONO_OPT_CMOV);
4645                         g_assert (ins->dreg == ins->sreg1);
4646                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4647                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4648                         break;
4649                 case OP_IMAX_UN:
4650                         g_assert (cfg->opt & MONO_OPT_CMOV);
4651                         g_assert (ins->dreg == ins->sreg1);
4652                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4653                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4654                         break;
4655                 case OP_LMIN:
4656                         g_assert (cfg->opt & MONO_OPT_CMOV);
4657                         g_assert (ins->dreg == ins->sreg1);
4658                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4659                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4660                         break;
4661                 case OP_LMIN_UN:
4662                         g_assert (cfg->opt & MONO_OPT_CMOV);
4663                         g_assert (ins->dreg == ins->sreg1);
4664                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4665                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4666                         break;
4667                 case OP_LMAX:
4668                         g_assert (cfg->opt & MONO_OPT_CMOV);
4669                         g_assert (ins->dreg == ins->sreg1);
4670                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4671                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4672                         break;
4673                 case OP_LMAX_UN:
4674                         g_assert (cfg->opt & MONO_OPT_CMOV);
4675                         g_assert (ins->dreg == ins->sreg1);
4676                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4677                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4678                         break;
4679                 case OP_X86_FPOP:
4680                         break;
4681                 case OP_FCOMPARE:
4682                         /*
4683                          * The two arguments are swapped because the fbranch instructions
4684                          * depend on this for the non-sse case to work.
4685                          */
4686                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4687                         break;
4688                 case OP_FCEQ: {
4689                         /* zeroing the register at the start results in
4690                          * shorter and faster code (we can also remove the widening op)
4691                          */
4692                         guchar *unordered_check;
4693                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4694                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4695                         unordered_check = code;
4696                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4697                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4698                         amd64_patch (unordered_check, code);
4699                         break;
4700                 }
4701                 case OP_FCLT:
4702                 case OP_FCLT_UN:
4703                         /* zeroing the register at the start results in
4704                          * shorter and faster code (we can also remove the widening op)
4705                          */
4706                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4707                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4708                         if (ins->opcode == OP_FCLT_UN) {
4709                                 guchar *unordered_check = code;
4710                                 guchar *jump_to_end;
4711                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4712                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4713                                 jump_to_end = code;
4714                                 x86_jump8 (code, 0);
4715                                 amd64_patch (unordered_check, code);
4716                                 amd64_inc_reg (code, ins->dreg);
4717                                 amd64_patch (jump_to_end, code);
4718                         } else {
4719                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4720                         }
4721                         break;
4722                 case OP_FCGT:
4723                 case OP_FCGT_UN: {
4724                         /* zeroing the register at the start results in
4725                          * shorter and faster code (we can also remove the widening op)
4726                          */
4727                         guchar *unordered_check;
4728                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4729                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4730                         if (ins->opcode == OP_FCGT) {
4731                                 unordered_check = code;
4732                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4733                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4734                                 amd64_patch (unordered_check, code);
4735                         } else {
4736                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4737                         }
4738                         break;
4739                 }
4740                 case OP_FCLT_MEMBASE:
4741                 case OP_FCGT_MEMBASE:
4742                 case OP_FCLT_UN_MEMBASE:
4743                 case OP_FCGT_UN_MEMBASE:
4744                 case OP_FCEQ_MEMBASE: {
4745                         guchar *unordered_check, *jump_to_end;
4746                         int x86_cond;
4747
4748                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4749                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4750
4751                         switch (ins->opcode) {
4752                         case OP_FCEQ_MEMBASE:
4753                                 x86_cond = X86_CC_EQ;
4754                                 break;
4755                         case OP_FCLT_MEMBASE:
4756                         case OP_FCLT_UN_MEMBASE:
4757                                 x86_cond = X86_CC_LT;
4758                                 break;
4759                         case OP_FCGT_MEMBASE:
4760                         case OP_FCGT_UN_MEMBASE:
4761                                 x86_cond = X86_CC_GT;
4762                                 break;
4763                         default:
4764                                 g_assert_not_reached ();
4765                         }
4766
4767                         unordered_check = code;
4768                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4769                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4770
4771                         switch (ins->opcode) {
4772                         case OP_FCEQ_MEMBASE:
4773                         case OP_FCLT_MEMBASE:
4774                         case OP_FCGT_MEMBASE:
4775                                 amd64_patch (unordered_check, code);
4776                                 break;
4777                         case OP_FCLT_UN_MEMBASE:
4778                         case OP_FCGT_UN_MEMBASE:
4779                                 jump_to_end = code;
4780                                 x86_jump8 (code, 0);
4781                                 amd64_patch (unordered_check, code);
4782                                 amd64_inc_reg (code, ins->dreg);
4783                                 amd64_patch (jump_to_end, code);
4784                                 break;
4785                         default:
4786                                 break;
4787                         }
4788                         break;
4789                 }
4790                 case OP_FBEQ: {
4791                         guchar *jump = code;
4792                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4793                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4794                         amd64_patch (jump, code);
4795                         break;
4796                 }
4797                 case OP_FBNE_UN:
4798                         /* Branch if C013 != 100 */
4799                         /* branch if !ZF or (PF|CF) */
4800                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4801                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4802                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4803                         break;
4804                 case OP_FBLT:
4805                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4806                         break;
4807                 case OP_FBLT_UN:
4808                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4809                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4810                         break;
4811                 case OP_FBGT:
4812                 case OP_FBGT_UN:
4813                         if (ins->opcode == OP_FBGT) {
4814                                 guchar *br1;
4815
4816                                 /* skip branch if C1=1 */
4817                                 br1 = code;
4818                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4819                                 /* branch if (C0 | C3) = 1 */
4820                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4821                                 amd64_patch (br1, code);
4822                                 break;
4823                         } else {
4824                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4825                         }
4826                         break;
4827                 case OP_FBGE: {
4828                         /* Branch if C013 == 100 or 001 */
4829                         guchar *br1;
4830
4831                         /* skip branch if C1=1 */
4832                         br1 = code;
4833                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4834                         /* branch if (C0 | C3) = 1 */
4835                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4836                         amd64_patch (br1, code);
4837                         break;
4838                 }
4839                 case OP_FBGE_UN:
4840                         /* Branch if C013 == 000 */
4841                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4842                         break;
4843                 case OP_FBLE: {
4844                         /* Branch if C013=000 or 100 */
4845                         guchar *br1;
4846
4847                         /* skip branch if C1=1 */
4848                         br1 = code;
4849                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4850                         /* branch if C0=0 */
4851                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4852                         amd64_patch (br1, code);
4853                         break;
4854                 }
4855                 case OP_FBLE_UN:
4856                         /* Branch if C013 != 001 */
4857                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4858                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4859                         break;
4860                 case OP_CKFINITE:
4861                         /* Transfer value to the fp stack */
4862                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4863                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4864                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4865
4866                         amd64_push_reg (code, AMD64_RAX);
4867                         amd64_fxam (code);
4868                         amd64_fnstsw (code);
4869                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4870                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4871                         amd64_pop_reg (code, AMD64_RAX);
4872                         amd64_fstp (code, 0);
4873                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4874                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4875                         break;
4876                 case OP_TLS_GET: {
4877                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4878                         break;
4879                 }
4880                 case OP_MEMORY_BARRIER: {
4881                         /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4882                         x86_prefix (code, X86_LOCK_PREFIX);
4883                         amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
4884                         break;
4885                 }
4886                 case OP_ATOMIC_ADD_I4:
4887                 case OP_ATOMIC_ADD_I8: {
4888                         int dreg = ins->dreg;
4889                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4890
4891                         if (dreg == ins->inst_basereg)
4892                                 dreg = AMD64_R11;
4893
4894                         if (dreg != ins->sreg2)
4895                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4896
4897                         x86_prefix (code, X86_LOCK_PREFIX);
4898                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4899
4900                         if (dreg != ins->dreg)
4901                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4902
4903                         break;
4904                 }
4905                 case OP_ATOMIC_ADD_NEW_I4:
4906                 case OP_ATOMIC_ADD_NEW_I8: {
4907                         int dreg = ins->dreg;
4908                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4909
4910                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4911                                 dreg = AMD64_R11;
4912
4913                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4914                         amd64_prefix (code, X86_LOCK_PREFIX);
4915                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4916                         /* dreg contains the old value, add with sreg2 value */
4917                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4918
4919                         if (ins->dreg != dreg)
4920                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4921
4922                         break;
4923                 }
4924                 case OP_ATOMIC_EXCHANGE_I4:
4925                 case OP_ATOMIC_EXCHANGE_I8: {
4926                         guchar *br[2];
4927                         int sreg2 = ins->sreg2;
4928                         int breg = ins->inst_basereg;
4929                         guint32 size;
4930                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4931
4932                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4933                                 size = 8;
4934                         else
4935                                 size = 4;
4936
4937                         /*
4938                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4939                          * an explanation of how this works.
4940                          */
4941
4942                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4943                          * hack to overcome limits in x86 reg allocator
4944                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4945                          */
4946                         g_assert (ins->dreg == AMD64_RAX);
4947
4948                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4949                                 /* Highly unlikely, but possible */
4950                                 need_push = TRUE;
4951
4952                         /* The pushes invalidate rsp */
4953                         if ((breg == AMD64_RAX) || need_push) {
4954                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4955                                 breg = AMD64_R11;
4956                         }
4957
4958                         /* We need the EAX reg for the comparand */
4959                         if (ins->sreg2 == AMD64_RAX) {
4960                                 if (breg != AMD64_R11) {
4961                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4962                                         sreg2 = AMD64_R11;
4963                                 } else {
4964                                         g_assert (need_push);
4965                                         amd64_push_reg (code, AMD64_RDX);
4966                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4967                                         sreg2 = AMD64_RDX;
4968                                         rdx_pushed = TRUE;
4969                                 }
4970                         }
4971
4972                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4973
4974                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4975                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4976                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4977                         amd64_patch (br [1], br [0]);
4978
4979                         if (rdx_pushed)
4980                                 amd64_pop_reg (code, AMD64_RDX);
4981
4982                         break;
4983                 }
4984                 case OP_ATOMIC_CAS_I4:
4985                 case OP_ATOMIC_CAS_I8: {
4986                         guint32 size;
4987
4988                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4989                                 size = 8;
4990                         else
4991                                 size = 4;
4992
4993                         /*
4994                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4995                          * an explanation of how this works.
4996                          */
4997                         g_assert (ins->sreg3 == AMD64_RAX);
4998                         g_assert (ins->sreg1 != AMD64_RAX);
4999                         g_assert (ins->sreg1 != ins->sreg2);
5000
5001                         amd64_prefix (code, X86_LOCK_PREFIX);
5002                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5003
5004                         if (ins->dreg != AMD64_RAX)
5005                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5006                         break;
5007                 }
5008                 case OP_CARD_TABLE_WBARRIER: {
5009                         int ptr = ins->sreg1;
5010                         int value = ins->sreg2;
5011                         guchar *br;
5012                         int nursery_shift, card_table_shift;
5013                         gpointer card_table_mask;
5014                         size_t nursery_size;
5015
5016                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5017                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5018
5019                         /*If either point to the stack we can simply avoid the WB. This happens due to
5020                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5021                          */
5022                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5023                                 continue;
5024
5025                         /*
5026                          * We need one register we can clobber, we choose EDX and make sreg1
5027                          * fixed EAX to work around limitations in the local register allocator.
5028                          * sreg2 might get allocated to EDX, but that is not a problem since
5029                          * we use it before clobbering EDX.
5030                          */
5031                         g_assert (ins->sreg1 == AMD64_RAX);
5032
5033                         /*
5034                          * This is the code we produce:
5035                          *
5036                          *   edx = value
5037                          *   edx >>= nursery_shift
5038                          *   cmp edx, (nursery_start >> nursery_shift)
5039                          *   jne done
5040                          *   edx = ptr
5041                          *   edx >>= card_table_shift
5042                          *   edx += cardtable
5043                          *   [edx] = 1
5044                          * done:
5045                          */
5046
5047                         if (value != AMD64_RDX)
5048                                 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5049                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5050                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, nursery_start >> nursery_shift);
5051                         br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5052                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5053                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5054                         if (card_table_mask)
5055                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5056
5057                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5058                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5059
5060                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5061                         x86_patch (br, code);
5062                         break;
5063                 }
5064 #ifdef MONO_ARCH_SIMD_INTRINSICS
5065                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5066                 case OP_ADDPS:
5067                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5068                         break;
5069                 case OP_DIVPS:
5070                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5071                         break;
5072                 case OP_MULPS:
5073                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5074                         break;
5075                 case OP_SUBPS:
5076                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5077                         break;
5078                 case OP_MAXPS:
5079                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5080                         break;
5081                 case OP_MINPS:
5082                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5083                         break;
5084                 case OP_COMPPS:
5085                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5086                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5087                         break;
5088                 case OP_ANDPS:
5089                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5090                         break;
5091                 case OP_ANDNPS:
5092                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5093                         break;
5094                 case OP_ORPS:
5095                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5096                         break;
5097                 case OP_XORPS:
5098                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5099                         break;
5100                 case OP_SQRTPS:
5101                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5102                         break;
5103                 case OP_RSQRTPS:
5104                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5105                         break;
5106                 case OP_RCPPS:
5107                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5108                         break;
5109                 case OP_ADDSUBPS:
5110                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5111                         break;
5112                 case OP_HADDPS:
5113                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5114                         break;
5115                 case OP_HSUBPS:
5116                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5117                         break;
5118                 case OP_DUPPS_HIGH:
5119                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5120                         break;
5121                 case OP_DUPPS_LOW:
5122                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5123                         break;
5124
5125                 case OP_PSHUFLEW_HIGH:
5126                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5127                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5128                         break;
5129                 case OP_PSHUFLEW_LOW:
5130                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5131                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5132                         break;
5133                 case OP_PSHUFLED:
5134                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5135                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5136                         break;
5137
5138                 case OP_ADDPD:
5139                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5140                         break;
5141                 case OP_DIVPD:
5142                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5143                         break;
5144                 case OP_MULPD:
5145                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5146                         break;
5147                 case OP_SUBPD:
5148                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5149                         break;
5150                 case OP_MAXPD:
5151                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5152                         break;
5153                 case OP_MINPD:
5154                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5155                         break;
5156                 case OP_COMPPD:
5157                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5158                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5159                         break;
5160                 case OP_ANDPD:
5161                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5162                         break;
5163                 case OP_ANDNPD:
5164                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5165                         break;
5166                 case OP_ORPD:
5167                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5168                         break;
5169                 case OP_XORPD:
5170                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5171                         break;
5172                 case OP_SQRTPD:
5173                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5174                         break;
5175                 case OP_ADDSUBPD:
5176                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5177                         break;
5178                 case OP_HADDPD:
5179                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5180                         break;
5181                 case OP_HSUBPD:
5182                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5183                         break;
5184                 case OP_DUPPD:
5185                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5186                         break;
5187
5188                 case OP_EXTRACT_MASK:
5189                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5190                         break;
5191
5192                 case OP_PAND:
5193                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5194                         break;
5195                 case OP_POR:
5196                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5197                         break;
5198                 case OP_PXOR:
5199                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5200                         break;
5201
5202                 case OP_PADDB:
5203                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5204                         break;
5205                 case OP_PADDW:
5206                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5207                         break;
5208                 case OP_PADDD:
5209                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5210                         break;
5211                 case OP_PADDQ:
5212                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5213                         break;
5214
5215                 case OP_PSUBB:
5216                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5217                         break;
5218                 case OP_PSUBW:
5219                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5220                         break;
5221                 case OP_PSUBD:
5222                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5223                         break;
5224                 case OP_PSUBQ:
5225                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5226                         break;
5227
5228                 case OP_PMAXB_UN:
5229                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5230                         break;
5231                 case OP_PMAXW_UN:
5232                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5233                         break;
5234                 case OP_PMAXD_UN:
5235                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5236                         break;
5237
5238                 case OP_PMAXB:
5239                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5240                         break;
5241                 case OP_PMAXW:
5242                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5243                         break;
5244                 case OP_PMAXD:
5245                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5246                         break;
5247
5248                 case OP_PAVGB_UN:
5249                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5250                         break;
5251                 case OP_PAVGW_UN:
5252                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5253                         break;
5254
5255                 case OP_PMINB_UN:
5256                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5257                         break;
5258                 case OP_PMINW_UN:
5259                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5260                         break;
5261                 case OP_PMIND_UN:
5262                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5263                         break;
5264
5265                 case OP_PMINB:
5266                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5267                         break;
5268                 case OP_PMINW:
5269                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5270                         break;
5271                 case OP_PMIND:
5272                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5273                         break;
5274
5275                 case OP_PCMPEQB:
5276                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5277                         break;
5278                 case OP_PCMPEQW:
5279                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5280                         break;
5281                 case OP_PCMPEQD:
5282                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5283                         break;
5284                 case OP_PCMPEQQ:
5285                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5286                         break;
5287
5288                 case OP_PCMPGTB:
5289                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5290                         break;
5291                 case OP_PCMPGTW:
5292                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5293                         break;
5294                 case OP_PCMPGTD:
5295                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5296                         break;
5297                 case OP_PCMPGTQ:
5298                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5299                         break;
5300
5301                 case OP_PSUM_ABS_DIFF:
5302                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5303                         break;
5304
5305                 case OP_UNPACK_LOWB:
5306                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5307                         break;
5308                 case OP_UNPACK_LOWW:
5309                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5310                         break;
5311                 case OP_UNPACK_LOWD:
5312                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5313                         break;
5314                 case OP_UNPACK_LOWQ:
5315                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5316                         break;
5317                 case OP_UNPACK_LOWPS:
5318                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5319                         break;
5320                 case OP_UNPACK_LOWPD:
5321                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5322                         break;
5323
5324                 case OP_UNPACK_HIGHB:
5325                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5326                         break;
5327                 case OP_UNPACK_HIGHW:
5328                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5329                         break;
5330                 case OP_UNPACK_HIGHD:
5331                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5332                         break;
5333                 case OP_UNPACK_HIGHQ:
5334                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5335                         break;
5336                 case OP_UNPACK_HIGHPS:
5337                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5338                         break;
5339                 case OP_UNPACK_HIGHPD:
5340                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5341                         break;
5342
5343                 case OP_PACKW:
5344                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5345                         break;
5346                 case OP_PACKD:
5347                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5348                         break;
5349                 case OP_PACKW_UN:
5350                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5351                         break;
5352                 case OP_PACKD_UN:
5353                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5354                         break;
5355
5356                 case OP_PADDB_SAT_UN:
5357                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5358                         break;
5359                 case OP_PSUBB_SAT_UN:
5360                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5361                         break;
5362                 case OP_PADDW_SAT_UN:
5363                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5364                         break;
5365                 case OP_PSUBW_SAT_UN:
5366                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5367                         break;
5368
5369                 case OP_PADDB_SAT:
5370                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5371                         break;
5372                 case OP_PSUBB_SAT:
5373                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5374                         break;
5375                 case OP_PADDW_SAT:
5376                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5377                         break;
5378                 case OP_PSUBW_SAT:
5379                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5380                         break;
5381
5382                 case OP_PMULW:
5383                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5384                         break;
5385                 case OP_PMULD:
5386                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5387                         break;
5388                 case OP_PMULQ:
5389                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5390                         break;
5391                 case OP_PMULW_HIGH_UN:
5392                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5393                         break;
5394                 case OP_PMULW_HIGH:
5395                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5396                         break;
5397
5398                 case OP_PSHRW:
5399                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5400                         break;
5401                 case OP_PSHRW_REG:
5402                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5403                         break;
5404
5405                 case OP_PSARW:
5406                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5407                         break;
5408                 case OP_PSARW_REG:
5409                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5410                         break;
5411
5412                 case OP_PSHLW:
5413                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5414                         break;
5415                 case OP_PSHLW_REG:
5416                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5417                         break;
5418
5419                 case OP_PSHRD:
5420                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5421                         break;
5422                 case OP_PSHRD_REG:
5423                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5424                         break;
5425
5426                 case OP_PSARD:
5427                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5428                         break;
5429                 case OP_PSARD_REG:
5430                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5431                         break;
5432
5433                 case OP_PSHLD:
5434                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5435                         break;
5436                 case OP_PSHLD_REG:
5437                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5438                         break;
5439
5440                 case OP_PSHRQ:
5441                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5442                         break;
5443                 case OP_PSHRQ_REG:
5444                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5445                         break;
5446
5447                 /*TODO: This is appart of the sse spec but not added
5448                 case OP_PSARQ:
5449                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5450                         break;
5451                 case OP_PSARQ_REG:
5452                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5453                         break;
5454                 */
5455
5456                 case OP_PSHLQ:
5457                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5458                         break;
5459                 case OP_PSHLQ_REG:
5460                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5461                         break;
5462
5463                 case OP_ICONV_TO_X:
5464                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5465                         break;
5466                 case OP_EXTRACT_I4:
5467                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5468                         break;
5469                 case OP_EXTRACT_I8:
5470                         if (ins->inst_c0) {
5471                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5472                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5473                         } else {
5474                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5475                         }
5476                         break;
5477                 case OP_EXTRACT_I1:
5478                 case OP_EXTRACT_U1:
5479                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5480                         if (ins->inst_c0)
5481                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5482                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5483                         break;
5484                 case OP_EXTRACT_I2:
5485                 case OP_EXTRACT_U2:
5486                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5487                         if (ins->inst_c0)
5488                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5489                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5490                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5491                         break;
5492                 case OP_EXTRACT_R8:
5493                         if (ins->inst_c0)
5494                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5495                         else
5496                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5497                         break;
5498                 case OP_INSERT_I2:
5499                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5500                         break;
5501                 case OP_EXTRACTX_U2:
5502                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5503                         break;
5504                 case OP_INSERTX_U1_SLOW:
5505                         /*sreg1 is the extracted ireg (scratch)
5506                         /sreg2 is the to be inserted ireg (scratch)
5507                         /dreg is the xreg to receive the value*/
5508
5509                         /*clear the bits from the extracted word*/
5510                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5511                         /*shift the value to insert if needed*/
5512                         if (ins->inst_c0 & 1)
5513                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5514                         /*join them together*/
5515                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5516                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5517                         break;
5518                 case OP_INSERTX_I4_SLOW:
5519                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5520                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5521                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5522                         break;
5523                 case OP_INSERTX_I8_SLOW:
5524                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5525                         if (ins->inst_c0)
5526                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5527                         else
5528                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5529                         break;
5530
5531                 case OP_INSERTX_R4_SLOW:
5532                         switch (ins->inst_c0) {
5533                         case 0:
5534                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5535                                 break;
5536                         case 1:
5537                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5538                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5539                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5540                                 break;
5541                         case 2:
5542                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5543                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5544                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5545                                 break;
5546                         case 3:
5547                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5548                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5549                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5550                                 break;
5551                         }
5552                         break;
5553                 case OP_INSERTX_R8_SLOW:
5554                         if (ins->inst_c0)
5555                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5556                         else
5557                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5558                         break;
5559                 case OP_STOREX_MEMBASE_REG:
5560                 case OP_STOREX_MEMBASE:
5561                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5562                         break;
5563                 case OP_LOADX_MEMBASE:
5564                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5565                         break;
5566                 case OP_LOADX_ALIGNED_MEMBASE:
5567                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5568                         break;
5569                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5570                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5571                         break;
5572                 case OP_STOREX_NTA_MEMBASE_REG:
5573                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5574                         break;
5575                 case OP_PREFETCH_MEMBASE:
5576                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5577                         break;
5578
5579                 case OP_XMOVE:
5580                         /*FIXME the peephole pass should have killed this*/
5581                         if (ins->dreg != ins->sreg1)
5582                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5583                         break;
5584                 case OP_XZERO:
5585                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5586                         break;
5587                 case OP_ICONV_TO_R8_RAW:
5588                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5589                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5590                         break;
5591
5592                 case OP_FCONV_TO_R8_X:
5593                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5594                         break;
5595
5596                 case OP_XCONV_R8_TO_I4:
5597                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5598                         switch (ins->backend.source_opcode) {
5599                         case OP_FCONV_TO_I1:
5600                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5601                                 break;
5602                         case OP_FCONV_TO_U1:
5603                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5604                                 break;
5605                         case OP_FCONV_TO_I2:
5606                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5607                                 break;
5608                         case OP_FCONV_TO_U2:
5609                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5610                                 break;
5611                         }
5612                         break;
5613
5614                 case OP_EXPAND_I2:
5615                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5616                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5617                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5618                         break;
5619                 case OP_EXPAND_I4:
5620                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5621                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5622                         break;
5623                 case OP_EXPAND_I8:
5624                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5625                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5626                         break;
5627                 case OP_EXPAND_R4:
5628                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5629                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5630                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5631                         break;
5632                 case OP_EXPAND_R8:
5633                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5634                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5635                         break;
5636 #endif
5637                 case OP_LIVERANGE_START: {
5638                         if (cfg->verbose_level > 1)
5639                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5640                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5641                         break;
5642                 }
5643                 case OP_LIVERANGE_END: {
5644                         if (cfg->verbose_level > 1)
5645                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5646                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5647                         break;
5648                 }
5649                 default:
5650                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5651                         g_assert_not_reached ();
5652                 }
5653
5654                 if ((code - cfg->native_code - offset) > max_len) {
5655                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5656                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5657                         g_assert_not_reached ();
5658                 }
5659
5660                 last_ins = ins;
5661                 last_offset = offset;
5662         }
5663
5664         cfg->code_len = code - cfg->native_code;
5665 }
5666
5667 #endif /* DISABLE_JIT */
5668
5669 void
5670 mono_arch_register_lowlevel_calls (void)
5671 {
5672         /* The signature doesn't matter */
5673         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5674 }
5675
5676 void
5677 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5678 {
5679         MonoJumpInfo *patch_info;
5680         gboolean compile_aot = !run_cctors;
5681
5682         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5683                 unsigned char *ip = patch_info->ip.i + code;
5684                 unsigned char *target;
5685
5686                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5687
5688                 if (compile_aot) {
5689                         switch (patch_info->type) {
5690                         case MONO_PATCH_INFO_BB:
5691                         case MONO_PATCH_INFO_LABEL:
5692                                 break;
5693                         default:
5694                                 /* No need to patch these */
5695                                 continue;
5696                         }
5697                 }
5698
5699                 switch (patch_info->type) {
5700                 case MONO_PATCH_INFO_NONE:
5701                         continue;
5702                 case MONO_PATCH_INFO_METHOD_REL:
5703                 case MONO_PATCH_INFO_R8:
5704                 case MONO_PATCH_INFO_R4:
5705                         g_assert_not_reached ();
5706                         continue;
5707                 case MONO_PATCH_INFO_BB:
5708                         break;
5709                 default:
5710                         break;
5711                 }
5712
5713                 /*
5714                  * Debug code to help track down problems where the target of a near call is
5715                  * is not valid.
5716                  */
5717                 if (amd64_is_near_call (ip)) {
5718                         gint64 disp = (guint8*)target - (guint8*)ip;
5719
5720                         if (!amd64_is_imm32 (disp)) {
5721                                 printf ("TYPE: %d\n", patch_info->type);
5722                                 switch (patch_info->type) {
5723                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5724                                         printf ("V: %s\n", patch_info->data.name);
5725                                         break;
5726                                 case MONO_PATCH_INFO_METHOD_JUMP:
5727                                 case MONO_PATCH_INFO_METHOD:
5728                                         printf ("V: %s\n", patch_info->data.method->name);
5729                                         break;
5730                                 default:
5731                                         break;
5732                                 }
5733                         }
5734                 }
5735
5736                 amd64_patch (ip, (gpointer)target);
5737         }
5738 }
5739
5740 #ifndef DISABLE_JIT
5741
5742 static int
5743 get_max_epilog_size (MonoCompile *cfg)
5744 {
5745         int max_epilog_size = 16;
5746
5747         if (cfg->method->save_lmf)
5748                 max_epilog_size += 256;
5749
5750         if (mono_jit_trace_calls != NULL)
5751                 max_epilog_size += 50;
5752
5753         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5754                 max_epilog_size += 50;
5755
5756         max_epilog_size += (AMD64_NREG * 2);
5757
5758         return max_epilog_size;
5759 }
5760
5761 /*
5762  * This macro is used for testing whenever the unwinder works correctly at every point
5763  * where an async exception can happen.
5764  */
5765 /* This will generate a SIGSEGV at the given point in the code */
5766 #define async_exc_point(code) do { \
5767     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5768          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5769              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5770          cfg->arch.async_point_count ++; \
5771     } \
5772 } while (0)
5773
5774 guint8 *
5775 mono_arch_emit_prolog (MonoCompile *cfg)
5776 {
5777         MonoMethod *method = cfg->method;
5778         MonoBasicBlock *bb;
5779         MonoMethodSignature *sig;
5780         MonoInst *ins;
5781         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5782         guint8 *code;
5783         CallInfo *cinfo;
5784         gint32 lmf_offset = cfg->arch.lmf_offset;
5785         gboolean args_clobbered = FALSE;
5786         gboolean trace = FALSE;
5787
5788         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
5789
5790         code = cfg->native_code = g_malloc (cfg->code_size);
5791
5792         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5793                 trace = TRUE;
5794
5795         /* Amount of stack space allocated by register saving code */
5796         pos = 0;
5797
5798         /* Offset between RSP and the CFA */
5799         cfa_offset = 0;
5800
5801         /*
5802          * The prolog consists of the following parts:
5803          * FP present:
5804          * - push rbp, mov rbp, rsp
5805          * - save callee saved regs using pushes
5806          * - allocate frame
5807          * - save rgctx if needed
5808          * - save lmf if needed
5809          * FP not present:
5810          * - allocate frame
5811          * - save rgctx if needed
5812          * - save lmf if needed
5813          * - save callee saved regs using moves
5814          */
5815
5816         // CFA = sp + 8
5817         cfa_offset = 8;
5818         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5819         // IP saved at CFA - 8
5820         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5821         async_exc_point (code);
5822
5823         if (!cfg->arch.omit_fp) {
5824                 amd64_push_reg (code, AMD64_RBP);
5825                 cfa_offset += 8;
5826                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5827                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5828                 async_exc_point (code);
5829 #ifdef HOST_WIN32
5830                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5831 #endif
5832
5833                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5834                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5835                 async_exc_point (code);
5836 #ifdef HOST_WIN32
5837                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5838 #endif
5839         }
5840
5841         /* Save callee saved registers */
5842         if (!cfg->arch.omit_fp && !method->save_lmf) {
5843                 int offset = cfa_offset;
5844
5845                 for (i = 0; i < AMD64_NREG; ++i)
5846                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5847                                 amd64_push_reg (code, i);
5848                                 pos += sizeof (gpointer);
5849                                 offset += 8;
5850                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5851                                 async_exc_point (code);
5852                         }
5853         }
5854
5855         /* The param area is always at offset 0 from sp */
5856         /* This needs to be allocated here, since it has to come after the spill area */
5857         if (cfg->arch.no_pushes && cfg->param_area) {
5858                 if (cfg->arch.omit_fp)
5859                         // FIXME:
5860                         g_assert_not_reached ();
5861                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5862         }
5863
5864         if (cfg->arch.omit_fp) {
5865                 /*
5866                  * On enter, the stack is misaligned by the the pushing of the return
5867                  * address. It is either made aligned by the pushing of %rbp, or by
5868                  * this.
5869                  */
5870                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5871                 if ((alloc_size % 16) == 0)
5872                         alloc_size += 8;
5873         } else {
5874                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5875
5876                 alloc_size -= pos;
5877         }
5878
5879         cfg->arch.stack_alloc_size = alloc_size;
5880
5881         /* Allocate stack frame */
5882         if (alloc_size) {
5883                 /* See mono_emit_stack_alloc */
5884 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5885                 guint32 remaining_size = alloc_size;
5886                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5887                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
5888                 guint32 offset = code - cfg->native_code;
5889                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5890                         while (required_code_size >= (cfg->code_size - offset))
5891                                 cfg->code_size *= 2;
5892                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5893                         code = cfg->native_code + offset;
5894                         mono_jit_stats.code_reallocs++;
5895                 }
5896
5897                 while (remaining_size >= 0x1000) {
5898                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5899                         if (cfg->arch.omit_fp) {
5900                                 cfa_offset += 0x1000;
5901                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5902                         }
5903                         async_exc_point (code);
5904 #ifdef HOST_WIN32
5905                         if (cfg->arch.omit_fp)
5906                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5907 #endif
5908
5909                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5910                         remaining_size -= 0x1000;
5911                 }
5912                 if (remaining_size) {
5913                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5914                         if (cfg->arch.omit_fp) {
5915                                 cfa_offset += remaining_size;
5916                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5917                                 async_exc_point (code);
5918                         }
5919 #ifdef HOST_WIN32
5920                         if (cfg->arch.omit_fp)
5921                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5922 #endif
5923                 }
5924 #else
5925                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5926                 if (cfg->arch.omit_fp) {
5927                         cfa_offset += alloc_size;
5928                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5929                         async_exc_point (code);
5930                 }
5931 #endif
5932         }
5933
5934         /* Stack alignment check */
5935 #if 0
5936         {
5937                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5938                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5939                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5940                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5941                 amd64_breakpoint (code);
5942         }
5943 #endif
5944
5945 #ifndef TARGET_WIN32
5946         if (mini_get_debug_options ()->init_stacks) {
5947                 /* Fill the stack frame with a dummy value to force deterministic behavior */
5948
5949                 /* Save registers to the red zone */
5950                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
5951                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5952
5953                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
5954                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
5955                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
5956
5957                 amd64_cld (code);
5958                 amd64_prefix (code, X86_REP_PREFIX);
5959                 amd64_stosl (code);
5960
5961                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
5962                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5963         }
5964 #endif
5965
5966         /* Save LMF */
5967         if (method->save_lmf) {
5968                 /*
5969                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5970                  */
5971                 /*
5972                  * sp is saved right before calls but we need to save it here too so
5973                  * async stack walks would work.
5974                  */
5975                 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5976                 /* Skip method (only needed for trampoline LMF frames) */
5977                 /* Save callee saved regs */
5978                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5979                         int offset;
5980
5981                         switch (i) {
5982                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5983                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5984                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5985                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5986                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5987                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5988 #ifdef HOST_WIN32
5989                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5990                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5991 #endif
5992                         default:
5993                                 offset = -1;
5994                                 break;
5995                         }
5996
5997                         if (offset != -1) {
5998                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5999                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
6000                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
6001                         }
6002                 }
6003         }
6004
6005         /* Save callee saved registers */
6006         if (cfg->arch.omit_fp && !method->save_lmf) {
6007                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6008
6009                 /* Save caller saved registers after sp is adjusted */
6010                 /* The registers are saved at the bottom of the frame */
6011                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6012                 for (i = 0; i < AMD64_NREG; ++i)
6013                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6014                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
6015                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6016                                 save_area_offset += 8;
6017                                 async_exc_point (code);
6018                         }
6019         }
6020
6021         /* store runtime generic context */
6022         if (cfg->rgctx_var) {
6023                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6024                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6025
6026                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
6027         }
6028
6029         /* compute max_length in order to use short forward jumps */
6030         max_epilog_size = get_max_epilog_size (cfg);
6031         if (cfg->opt & MONO_OPT_BRANCH) {
6032                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6033                         MonoInst *ins;
6034                         int max_length = 0;
6035
6036                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6037                                 max_length += 6;
6038                         /* max alignment for loops */
6039                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6040                                 max_length += LOOP_ALIGNMENT;
6041
6042                         MONO_BB_FOR_EACH_INS (bb, ins) {
6043                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6044                         }
6045
6046                         /* Take prolog and epilog instrumentation into account */
6047                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6048                                 max_length += max_epilog_size;
6049
6050                         bb->max_length = max_length;
6051                 }
6052         }
6053
6054         sig = mono_method_signature (method);
6055         pos = 0;
6056
6057         cinfo = cfg->arch.cinfo;
6058
6059         if (sig->ret->type != MONO_TYPE_VOID) {
6060                 /* Save volatile arguments to the stack */
6061                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6062                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6063         }
6064
6065         /* Keep this in sync with emit_load_volatile_arguments */
6066         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6067                 ArgInfo *ainfo = cinfo->args + i;
6068                 gint32 stack_offset;
6069                 MonoType *arg_type;
6070
6071                 ins = cfg->args [i];
6072
6073                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6074                         /* Unused arguments */
6075                         continue;
6076
6077                 if (sig->hasthis && (i == 0))
6078                         arg_type = &mono_defaults.object_class->byval_arg;
6079                 else
6080                         arg_type = sig->params [i - sig->hasthis];
6081
6082                 stack_offset = ainfo->offset + ARGS_OFFSET;
6083
6084                 if (cfg->globalra) {
6085                         /* All the other moves are done by the register allocator */
6086                         switch (ainfo->storage) {
6087                         case ArgInFloatSSEReg:
6088                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6089                                 break;
6090                         case ArgValuetypeInReg:
6091                                 for (quad = 0; quad < 2; quad ++) {
6092                                         switch (ainfo->pair_storage [quad]) {
6093                                         case ArgInIReg:
6094                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6095                                                 break;
6096                                         case ArgInFloatSSEReg:
6097                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6098                                                 break;
6099                                         case ArgInDoubleSSEReg:
6100                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6101                                                 break;
6102                                         case ArgNone:
6103                                                 break;
6104                                         default:
6105                                                 g_assert_not_reached ();
6106                                         }
6107                                 }
6108                                 break;
6109                         default:
6110                                 break;
6111                         }
6112
6113                         continue;
6114                 }
6115
6116                 /* Save volatile arguments to the stack */
6117                 if (ins->opcode != OP_REGVAR) {
6118                         switch (ainfo->storage) {
6119                         case ArgInIReg: {
6120                                 guint32 size = 8;
6121
6122                                 /* FIXME: I1 etc */
6123                                 /*
6124                                 if (stack_offset & 0x1)
6125                                         size = 1;
6126                                 else if (stack_offset & 0x2)
6127                                         size = 2;
6128                                 else if (stack_offset & 0x4)
6129                                         size = 4;
6130                                 else
6131                                         size = 8;
6132                                 */
6133                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6134                                 break;
6135                         }
6136                         case ArgInFloatSSEReg:
6137                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6138                                 break;
6139                         case ArgInDoubleSSEReg:
6140                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6141                                 break;
6142                         case ArgValuetypeInReg:
6143                                 for (quad = 0; quad < 2; quad ++) {
6144                                         switch (ainfo->pair_storage [quad]) {
6145                                         case ArgInIReg:
6146                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6147                                                 break;
6148                                         case ArgInFloatSSEReg:
6149                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6150                                                 break;
6151                                         case ArgInDoubleSSEReg:
6152                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6153                                                 break;
6154                                         case ArgNone:
6155                                                 break;
6156                                         default:
6157                                                 g_assert_not_reached ();
6158                                         }
6159                                 }
6160                                 break;
6161                         case ArgValuetypeAddrInIReg:
6162                                 if (ainfo->pair_storage [0] == ArgInIReg)
6163                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6164                                 break;
6165                         default:
6166                                 break;
6167                         }
6168                 } else {
6169                         /* Argument allocated to (non-volatile) register */
6170                         switch (ainfo->storage) {
6171                         case ArgInIReg:
6172                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6173                                 break;
6174                         case ArgOnStack:
6175                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6176                                 break;
6177                         default:
6178                                 g_assert_not_reached ();
6179                         }
6180                 }
6181         }
6182
6183         /* Might need to attach the thread to the JIT  or change the domain for the callback */
6184         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6185                 guint64 domain = (guint64)cfg->domain;
6186
6187                 args_clobbered = TRUE;
6188
6189                 /*
6190                  * The call might clobber argument registers, but they are already
6191                  * saved to the stack/global regs.
6192                  */
6193                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6194                         guint8 *buf, *no_domain_branch;
6195
6196                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6197                         if (cfg->compile_aot) {
6198                                 /* AOT code is only used in the root domain */
6199                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6200                         } else {
6201                                 if ((domain >> 32) == 0)
6202                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6203                                 else
6204                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6205                         }
6206                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6207                         no_domain_branch = code;
6208                         x86_branch8 (code, X86_CC_NE, 0, 0);
6209                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6210                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6211                         buf = code;
6212                         x86_branch8 (code, X86_CC_NE, 0, 0);
6213                         amd64_patch (no_domain_branch, code);
6214                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6215                                           (gpointer)"mono_jit_thread_attach", TRUE);
6216                         amd64_patch (buf, code);
6217 #ifdef HOST_WIN32
6218                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6219                         /* FIXME: Add a separate key for LMF to avoid this */
6220                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6221 #endif
6222                 } else {
6223                         g_assert (!cfg->compile_aot);
6224                         if (cfg->compile_aot) {
6225                                 /* AOT code is only used in the root domain */
6226                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6227                         } else {
6228                                 if ((domain >> 32) == 0)
6229                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6230                                 else
6231                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6232                         }
6233                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6234                                           (gpointer)"mono_jit_thread_attach", TRUE);
6235                 }
6236         }
6237
6238         if (method->save_lmf) {
6239                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6240                         /*
6241                          * Optimized version which uses the mono_lmf TLS variable instead of
6242                          * indirection through the mono_lmf_addr TLS variable.
6243                          */
6244                         /* %rax = previous_lmf */
6245                         x86_prefix (code, X86_FS_PREFIX);
6246                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6247
6248                         /* Save previous_lmf */
6249                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6250                         /* Set new lmf */
6251                         if (lmf_offset == 0) {
6252                                 x86_prefix (code, X86_FS_PREFIX);
6253                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6254                         } else {
6255                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6256                                 x86_prefix (code, X86_FS_PREFIX);
6257                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6258                         }
6259                 } else {
6260                         if (lmf_addr_tls_offset != -1) {
6261                                 /* Load lmf quicky using the FS register */
6262                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6263 #ifdef HOST_WIN32
6264                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6265                                 /* FIXME: Add a separate key for LMF to avoid this */
6266                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6267 #endif
6268                         }
6269                         else {
6270                                 /*
6271                                  * The call might clobber argument registers, but they are already
6272                                  * saved to the stack/global regs.
6273                                  */
6274                                 args_clobbered = TRUE;
6275                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6276                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6277                         }
6278
6279                         /* Save lmf_addr */
6280                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6281                         /* Save previous_lmf */
6282                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6283                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6284                         /* Set new lmf */
6285                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6286                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6287                 }
6288         }
6289
6290         if (trace) {
6291                 args_clobbered = TRUE;
6292                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6293         }
6294
6295         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6296                 args_clobbered = TRUE;
6297
6298         /*
6299          * Optimize the common case of the first bblock making a call with the same
6300          * arguments as the method. This works because the arguments are still in their
6301          * original argument registers.
6302          * FIXME: Generalize this
6303          */
6304         if (!args_clobbered) {
6305                 MonoBasicBlock *first_bb = cfg->bb_entry;
6306                 MonoInst *next;
6307
6308                 next = mono_bb_first_ins (first_bb);
6309                 if (!next && first_bb->next_bb) {
6310                         first_bb = first_bb->next_bb;
6311                         next = mono_bb_first_ins (first_bb);
6312                 }
6313
6314                 if (first_bb->in_count > 1)
6315                         next = NULL;
6316
6317                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6318                         ArgInfo *ainfo = cinfo->args + i;
6319                         gboolean match = FALSE;
6320
6321                         ins = cfg->args [i];
6322                         if (ins->opcode != OP_REGVAR) {
6323                                 switch (ainfo->storage) {
6324                                 case ArgInIReg: {
6325                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6326                                                 if (next->dreg == ainfo->reg) {
6327                                                         NULLIFY_INS (next);
6328                                                         match = TRUE;
6329                                                 } else {
6330                                                         next->opcode = OP_MOVE;
6331                                                         next->sreg1 = ainfo->reg;
6332                                                         /* Only continue if the instruction doesn't change argument regs */
6333                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6334                                                                 match = TRUE;
6335                                                 }
6336                                         }
6337                                         break;
6338                                 }
6339                                 default:
6340                                         break;
6341                                 }
6342                         } else {
6343                                 /* Argument allocated to (non-volatile) register */
6344                                 switch (ainfo->storage) {
6345                                 case ArgInIReg:
6346                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6347                                                 NULLIFY_INS (next);
6348                                                 match = TRUE;
6349                                         }
6350                                         break;
6351                                 default:
6352                                         break;
6353                                 }
6354                         }
6355
6356                         if (match) {
6357                                 next = next->next;
6358                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6359                                 if (!next)
6360                                         break;
6361                         }
6362                 }
6363         }
6364
6365         /* Initialize ss_trigger_page_var */
6366         if (cfg->arch.ss_trigger_page_var) {
6367                 MonoInst *var = cfg->arch.ss_trigger_page_var;
6368
6369                 g_assert (!cfg->compile_aot);
6370                 g_assert (var->opcode == OP_REGOFFSET);
6371
6372                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6373                 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
6374         }
6375
6376         cfg->code_len = code - cfg->native_code;
6377
6378         g_assert (cfg->code_len < cfg->code_size);
6379
6380         return code;
6381 }
6382
6383 void
6384 mono_arch_emit_epilog (MonoCompile *cfg)
6385 {
6386         MonoMethod *method = cfg->method;
6387         int quad, pos, i;
6388         guint8 *code;
6389         int max_epilog_size;
6390         CallInfo *cinfo;
6391         gint32 lmf_offset = cfg->arch.lmf_offset;
6392
6393         max_epilog_size = get_max_epilog_size (cfg);
6394
6395         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6396                 cfg->code_size *= 2;
6397                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6398                 mono_jit_stats.code_reallocs++;
6399         }
6400
6401         code = cfg->native_code + cfg->code_len;
6402
6403         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6404                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6405
6406         /* the code restoring the registers must be kept in sync with OP_JMP */
6407         pos = 0;
6408
6409         if (method->save_lmf) {
6410                 /* check if we need to restore protection of the stack after a stack overflow */
6411                 if (mono_get_jit_tls_offset () != -1) {
6412                         guint8 *patch;
6413                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6414                         /* we load the value in a separate instruction: this mechanism may be
6415                          * used later as a safer way to do thread interruption
6416                          */
6417                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6418                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6419                         patch = code;
6420                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6421                         /* note that the call trampoline will preserve eax/edx */
6422                         x86_call_reg (code, X86_ECX);
6423                         x86_patch (patch, code);
6424                 } else {
6425                         /* FIXME: maybe save the jit tls in the prolog */
6426                 }
6427                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6428                         /*
6429                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6430                          * through the mono_lmf_addr TLS variable.
6431                          */
6432                         /* reg = previous_lmf */
6433                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6434                         x86_prefix (code, X86_FS_PREFIX);
6435                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6436                 } else {
6437                         /* Restore previous lmf */
6438                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6439                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6440                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6441                 }
6442
6443                 /* Restore caller saved regs */
6444                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6445                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6446                 }
6447                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6448                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6449                 }
6450                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6451                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6452                 }
6453                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6454                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6455                 }
6456                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6457                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6458                 }
6459                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6460                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6461                 }
6462 #ifdef HOST_WIN32
6463                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6464                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6465                 }
6466                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6467                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6468                 }
6469 #endif
6470         } else {
6471
6472                 if (cfg->arch.omit_fp) {
6473                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6474
6475                         for (i = 0; i < AMD64_NREG; ++i)
6476                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6477                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6478                                         save_area_offset += 8;
6479                                 }
6480                 }
6481                 else {
6482                         for (i = 0; i < AMD64_NREG; ++i)
6483                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6484                                         pos -= sizeof (gpointer);
6485
6486                         if (pos) {
6487                                 if (pos == - sizeof (gpointer)) {
6488                                         /* Only one register, so avoid lea */
6489                                         for (i = AMD64_NREG - 1; i > 0; --i)
6490                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6491                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6492                                                 }
6493                                 }
6494                                 else {
6495                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6496
6497                                         /* Pop registers in reverse order */
6498                                         for (i = AMD64_NREG - 1; i > 0; --i)
6499                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6500                                                         amd64_pop_reg (code, i);
6501                                                 }
6502                                 }
6503                         }
6504                 }
6505         }
6506
6507         /* Load returned vtypes into registers if needed */
6508         cinfo = cfg->arch.cinfo;
6509         if (cinfo->ret.storage == ArgValuetypeInReg) {
6510                 ArgInfo *ainfo = &cinfo->ret;
6511                 MonoInst *inst = cfg->ret;
6512
6513                 for (quad = 0; quad < 2; quad ++) {
6514                         switch (ainfo->pair_storage [quad]) {
6515                         case ArgInIReg:
6516                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6517                                 break;
6518                         case ArgInFloatSSEReg:
6519                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6520                                 break;
6521                         case ArgInDoubleSSEReg:
6522                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6523                                 break;
6524                         case ArgNone:
6525                                 break;
6526                         default:
6527                                 g_assert_not_reached ();
6528                         }
6529                 }
6530         }
6531
6532         if (cfg->arch.omit_fp) {
6533                 if (cfg->arch.stack_alloc_size)
6534                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6535         } else {
6536                 amd64_leave (code);
6537         }
6538         async_exc_point (code);
6539         amd64_ret (code);
6540
6541         cfg->code_len = code - cfg->native_code;
6542
6543         g_assert (cfg->code_len < cfg->code_size);
6544 }
6545
6546 void
6547 mono_arch_emit_exceptions (MonoCompile *cfg)
6548 {
6549         MonoJumpInfo *patch_info;
6550         int nthrows, i;
6551         guint8 *code;
6552         MonoClass *exc_classes [16];
6553         guint8 *exc_throw_start [16], *exc_throw_end [16];
6554         guint32 code_size = 0;
6555
6556         /* Compute needed space */
6557         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6558                 if (patch_info->type == MONO_PATCH_INFO_EXC)
6559                         code_size += 40;
6560                 if (patch_info->type == MONO_PATCH_INFO_R8)
6561                         code_size += 8 + 15; /* sizeof (double) + alignment */
6562                 if (patch_info->type == MONO_PATCH_INFO_R4)
6563                         code_size += 4 + 15; /* sizeof (float) + alignment */
6564                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
6565                         code_size += 8 + 7; /*sizeof (void*) + alignment */
6566         }
6567
6568         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6569                 cfg->code_size *= 2;
6570                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6571                 mono_jit_stats.code_reallocs++;
6572         }
6573
6574         code = cfg->native_code + cfg->code_len;
6575
6576         /* add code to raise exceptions */
6577         nthrows = 0;
6578         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6579                 switch (patch_info->type) {
6580                 case MONO_PATCH_INFO_EXC: {
6581                         MonoClass *exc_class;
6582                         guint8 *buf, *buf2;
6583                         guint32 throw_ip;
6584
6585                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
6586
6587                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6588                         g_assert (exc_class);
6589                         throw_ip = patch_info->ip.i;
6590
6591                         //x86_breakpoint (code);
6592                         /* Find a throw sequence for the same exception class */
6593                         for (i = 0; i < nthrows; ++i)
6594                                 if (exc_classes [i] == exc_class)
6595                                         break;
6596                         if (i < nthrows) {
6597                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6598                                 x86_jump_code (code, exc_throw_start [i]);
6599                                 patch_info->type = MONO_PATCH_INFO_NONE;
6600                         }
6601                         else {
6602                                 buf = code;
6603                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6604                                 buf2 = code;
6605
6606                                 if (nthrows < 16) {
6607                                         exc_classes [nthrows] = exc_class;
6608                                         exc_throw_start [nthrows] = code;
6609                                 }
6610                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
6611
6612                                 patch_info->type = MONO_PATCH_INFO_NONE;
6613
6614                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6615
6616                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6617                                 while (buf < buf2)
6618                                         x86_nop (buf);
6619
6620                                 if (nthrows < 16) {
6621                                         exc_throw_end [nthrows] = code;
6622                                         nthrows ++;
6623                                 }
6624                         }
6625                         break;
6626                 }
6627                 default:
6628                         /* do nothing */
6629                         break;
6630                 }
6631         }
6632
6633         /* Handle relocations with RIP relative addressing */
6634         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6635                 gboolean remove = FALSE;
6636                 guint8 *orig_code = code;
6637
6638                 switch (patch_info->type) {
6639                 case MONO_PATCH_INFO_R8:
6640                 case MONO_PATCH_INFO_R4: {
6641                         guint8 *pos;
6642
6643                         /* The SSE opcodes require a 16 byte alignment */
6644                         code = (guint8*)ALIGN_TO (code, 16);
6645                         memset (orig_code, 0, code - orig_code);
6646
6647                         pos = cfg->native_code + patch_info->ip.i;
6648
6649                         if (IS_REX (pos [1]))
6650                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6651                         else
6652                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6653
6654                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6655                                 *(double*)code = *(double*)patch_info->data.target;
6656                                 code += sizeof (double);
6657                         } else {
6658                                 *(float*)code = *(float*)patch_info->data.target;
6659                                 code += sizeof (float);
6660                         }
6661
6662                         remove = TRUE;
6663                         break;
6664                 }
6665                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
6666                         guint8 *pos;
6667
6668                         if (cfg->compile_aot)
6669                                 continue;
6670
6671                         /*loading is faster against aligned addresses.*/
6672                         code = (guint8*)ALIGN_TO (code, 8);
6673                         memset (orig_code, 0, code - orig_code);
6674
6675                         pos = cfg->native_code + patch_info->ip.i;
6676
6677                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
6678                         if (IS_REX (pos [1]))
6679                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6680                         else
6681                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
6682
6683                         *(gpointer*)code = (gpointer)patch_info->data.target;
6684                         code += sizeof (gpointer);
6685
6686                         remove = TRUE;
6687                         break;
6688                 }
6689                 default:
6690                         break;
6691                 }
6692
6693                 if (remove) {
6694                         if (patch_info == cfg->patch_info)
6695                                 cfg->patch_info = patch_info->next;
6696                         else {
6697                                 MonoJumpInfo *tmp;
6698
6699                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6700                                         ;
6701                                 tmp->next = patch_info->next;
6702                         }
6703                 }
6704         }
6705
6706         cfg->code_len = code - cfg->native_code;
6707
6708         g_assert (cfg->code_len < cfg->code_size);
6709
6710 }
6711
6712 #endif /* DISABLE_JIT */
6713
6714 void*
6715 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6716 {
6717         guchar *code = p;
6718         CallInfo *cinfo = NULL;
6719         MonoMethodSignature *sig;
6720         MonoInst *inst;
6721         int i, n, stack_area = 0;
6722
6723         /* Keep this in sync with mono_arch_get_argument_info */
6724
6725         if (enable_arguments) {
6726                 /* Allocate a new area on the stack and save arguments there */
6727                 sig = mono_method_signature (cfg->method);
6728
6729                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6730
6731                 n = sig->param_count + sig->hasthis;
6732
6733                 stack_area = ALIGN_TO (n * 8, 16);
6734
6735                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6736
6737                 for (i = 0; i < n; ++i) {
6738                         inst = cfg->args [i];
6739
6740                         if (inst->opcode == OP_REGVAR)
6741                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6742                         else {
6743                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6744                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6745                         }
6746                 }
6747         }
6748
6749         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6750         amd64_set_reg_template (code, AMD64_ARG_REG1);
6751         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6752         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6753
6754         if (enable_arguments)
6755                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6756
6757         return code;
6758 }
6759
6760 enum {
6761         SAVE_NONE,
6762         SAVE_STRUCT,
6763         SAVE_EAX,
6764         SAVE_EAX_EDX,
6765         SAVE_XMM
6766 };
6767
6768 void*
6769 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6770 {
6771         guchar *code = p;
6772         int save_mode = SAVE_NONE;
6773         MonoMethod *method = cfg->method;
6774         MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
6775
6776         switch (ret_type->type) {
6777         case MONO_TYPE_VOID:
6778                 /* special case string .ctor icall */
6779                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6780                         save_mode = SAVE_EAX;
6781                 else
6782                         save_mode = SAVE_NONE;
6783                 break;
6784         case MONO_TYPE_I8:
6785         case MONO_TYPE_U8:
6786                 save_mode = SAVE_EAX;
6787                 break;
6788         case MONO_TYPE_R4:
6789         case MONO_TYPE_R8:
6790                 save_mode = SAVE_XMM;
6791                 break;
6792         case MONO_TYPE_GENERICINST:
6793                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
6794                         save_mode = SAVE_EAX;
6795                         break;
6796                 }
6797                 /* Fall through */
6798         case MONO_TYPE_VALUETYPE:
6799                 save_mode = SAVE_STRUCT;
6800                 break;
6801         default:
6802                 save_mode = SAVE_EAX;
6803                 break;
6804         }
6805
6806         /* Save the result and copy it into the proper argument register */
6807         switch (save_mode) {
6808         case SAVE_EAX:
6809                 amd64_push_reg (code, AMD64_RAX);
6810                 /* Align stack */
6811                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6812                 if (enable_arguments)
6813                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6814                 break;
6815         case SAVE_STRUCT:
6816                 /* FIXME: */
6817                 if (enable_arguments)
6818                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6819                 break;
6820         case SAVE_XMM:
6821                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6822                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6823                 /* Align stack */
6824                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6825                 /*
6826                  * The result is already in the proper argument register so no copying
6827                  * needed.
6828                  */
6829                 break;
6830         case SAVE_NONE:
6831                 break;
6832         default:
6833                 g_assert_not_reached ();
6834         }
6835
6836         /* Set %al since this is a varargs call */
6837         if (save_mode == SAVE_XMM)
6838                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6839         else
6840                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6841
6842         if (preserve_argument_registers) {
6843                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6844                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6845         }
6846
6847         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6848         amd64_set_reg_template (code, AMD64_ARG_REG1);
6849         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6850
6851         if (preserve_argument_registers) {
6852                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6853                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6854         }
6855
6856         /* Restore result */
6857         switch (save_mode) {
6858         case SAVE_EAX:
6859                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6860                 amd64_pop_reg (code, AMD64_RAX);
6861                 break;
6862         case SAVE_STRUCT:
6863                 /* FIXME: */
6864                 break;
6865         case SAVE_XMM:
6866                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6867                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6868                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6869                 break;
6870         case SAVE_NONE:
6871                 break;
6872         default:
6873                 g_assert_not_reached ();
6874         }
6875
6876         return code;
6877 }
6878
6879 void
6880 mono_arch_flush_icache (guint8 *code, gint size)
6881 {
6882         /* Not needed */
6883 }
6884
6885 void
6886 mono_arch_flush_register_windows (void)
6887 {
6888 }
6889
6890 gboolean
6891 mono_arch_is_inst_imm (gint64 imm)
6892 {
6893         return amd64_is_imm32 (imm);
6894 }
6895
6896 /*
6897  * Determine whenever the trap whose info is in SIGINFO is caused by
6898  * integer overflow.
6899  */
6900 gboolean
6901 mono_arch_is_int_overflow (void *sigctx, void *info)
6902 {
6903         MonoContext ctx;
6904         guint8* rip;
6905         int reg;
6906         gint64 value;
6907
6908         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6909
6910         rip = (guint8*)ctx.rip;
6911
6912         if (IS_REX (rip [0])) {
6913                 reg = amd64_rex_b (rip [0]);
6914                 rip ++;
6915         }
6916         else
6917                 reg = 0;
6918
6919         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6920                 /* idiv REG */
6921                 reg += x86_modrm_rm (rip [1]);
6922
6923                 switch (reg) {
6924                 case AMD64_RAX:
6925                         value = ctx.rax;
6926                         break;
6927                 case AMD64_RBX:
6928                         value = ctx.rbx;
6929                         break;
6930                 case AMD64_RCX:
6931                         value = ctx.rcx;
6932                         break;
6933                 case AMD64_RDX:
6934                         value = ctx.rdx;
6935                         break;
6936                 case AMD64_RBP:
6937                         value = ctx.rbp;
6938                         break;
6939                 case AMD64_RSP:
6940                         value = ctx.rsp;
6941                         break;
6942                 case AMD64_RSI:
6943                         value = ctx.rsi;
6944                         break;
6945                 case AMD64_RDI:
6946                         value = ctx.rdi;
6947                         break;
6948                 case AMD64_R12:
6949                         value = ctx.r12;
6950                         break;
6951                 case AMD64_R13:
6952                         value = ctx.r13;
6953                         break;
6954                 case AMD64_R14:
6955                         value = ctx.r14;
6956                         break;
6957                 case AMD64_R15:
6958                         value = ctx.r15;
6959                         break;
6960                 default:
6961                         g_assert_not_reached ();
6962                         reg = -1;
6963                 }
6964
6965                 if (value == -1)
6966                         return TRUE;
6967         }
6968
6969         return FALSE;
6970 }
6971
6972 guint32
6973 mono_arch_get_patch_offset (guint8 *code)
6974 {
6975         return 3;
6976 }
6977
6978 /**
6979  * mono_breakpoint_clean_code:
6980  *
6981  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6982  * breakpoints in the original code, they are removed in the copy.
6983  *
6984  * Returns TRUE if no sw breakpoint was present.
6985  */
6986 gboolean
6987 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6988 {
6989         int i;
6990         gboolean can_write = TRUE;
6991         /*
6992          * If method_start is non-NULL we need to perform bound checks, since we access memory
6993          * at code - offset we could go before the start of the method and end up in a different
6994          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6995          * instead.
6996          */
6997         if (!method_start || code - offset >= method_start) {
6998                 memcpy (buf, code - offset, size);
6999         } else {
7000                 int diff = code - method_start;
7001                 memset (buf, 0, size);
7002                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7003         }
7004         code -= offset;
7005         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7006                 int idx = mono_breakpoint_info_index [i];
7007                 guint8 *ptr;
7008                 if (idx < 1)
7009                         continue;
7010                 ptr = mono_breakpoint_info [idx].address;
7011                 if (ptr >= code && ptr < code + size) {
7012                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7013                         can_write = FALSE;
7014                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7015                         buf [ptr - code] = saved_byte;
7016                 }
7017         }
7018         return can_write;
7019 }
7020
7021 int
7022 mono_arch_get_this_arg_reg (guint8 *code)
7023 {
7024         return AMD64_ARG_REG1;
7025 }
7026
7027 gpointer
7028 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7029 {
7030         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7031 }
7032
7033 #define MAX_ARCH_DELEGATE_PARAMS 10
7034
7035 static gpointer
7036 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7037 {
7038         guint8 *code, *start;
7039         int i;
7040
7041         if (has_target) {
7042                 start = code = mono_global_codeman_reserve (64);
7043
7044                 /* Replace the this argument with the target */
7045                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7046                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7047                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7048
7049                 g_assert ((code - start) < 64);
7050         } else {
7051                 start = code = mono_global_codeman_reserve (64);
7052
7053                 if (param_count == 0) {
7054                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7055                 } else {
7056                         /* We have to shift the arguments left */
7057                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7058                         for (i = 0; i < param_count; ++i) {
7059 #ifdef HOST_WIN32
7060                                 if (i < 3)
7061                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7062                                 else
7063                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7064 #else
7065                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7066 #endif
7067                         }
7068
7069                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7070                 }
7071                 g_assert ((code - start) < 64);
7072         }
7073
7074         mono_debug_add_delegate_trampoline (start, code - start);
7075
7076         if (code_len)
7077                 *code_len = code - start;
7078
7079
7080         if (mono_jit_map_is_enabled ()) {
7081                 char *buff;
7082                 if (has_target)
7083                         buff = (char*)"delegate_invoke_has_target";
7084                 else
7085                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7086                 mono_emit_jit_tramp (start, code - start, buff);
7087                 if (!has_target)
7088                         g_free (buff);
7089         }
7090
7091         return start;
7092 }
7093
7094 /*
7095  * mono_arch_get_delegate_invoke_impls:
7096  *
7097  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7098  * trampolines.
7099  */
7100 GSList*
7101 mono_arch_get_delegate_invoke_impls (void)
7102 {
7103         GSList *res = NULL;
7104         guint8 *code;
7105         guint32 code_len;
7106         int i;
7107
7108         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7109         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7110
7111         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7112                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7113                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7114         }
7115
7116         return res;
7117 }
7118
7119 gpointer
7120 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7121 {
7122         guint8 *code, *start;
7123         int i;
7124
7125         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7126                 return NULL;
7127
7128         /* FIXME: Support more cases */
7129         if (MONO_TYPE_ISSTRUCT (sig->ret))
7130                 return NULL;
7131
7132         if (has_target) {
7133                 static guint8* cached = NULL;
7134
7135                 if (cached)
7136                         return cached;
7137
7138                 if (mono_aot_only)
7139                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7140                 else
7141                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7142
7143                 mono_memory_barrier ();
7144
7145                 cached = start;
7146         } else {
7147                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7148                 for (i = 0; i < sig->param_count; ++i)
7149                         if (!mono_is_regsize_var (sig->params [i]))
7150                                 return NULL;
7151                 if (sig->param_count > 4)
7152                         return NULL;
7153
7154                 code = cache [sig->param_count];
7155                 if (code)
7156                         return code;
7157
7158                 if (mono_aot_only) {
7159                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7160                         start = mono_aot_get_trampoline (name);
7161                         g_free (name);
7162                 } else {
7163                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7164                 }
7165
7166                 mono_memory_barrier ();
7167
7168                 cache [sig->param_count] = start;
7169         }
7170
7171         return start;
7172 }
7173
7174 /*
7175  * Support for fast access to the thread-local lmf structure using the GS
7176  * segment register on NPTL + kernel 2.6.x.
7177  */
7178
7179 static gboolean tls_offset_inited = FALSE;
7180
7181 void
7182 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7183 {
7184         if (!tls_offset_inited) {
7185 #ifdef HOST_WIN32
7186                 /*
7187                  * We need to init this multiple times, since when we are first called, the key might not
7188                  * be initialized yet.
7189                  */
7190                 appdomain_tls_offset = mono_domain_get_tls_key ();
7191                 lmf_tls_offset = mono_get_jit_tls_key ();
7192                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7193
7194                 /* Only 64 tls entries can be accessed using inline code */
7195                 if (appdomain_tls_offset >= 64)
7196                         appdomain_tls_offset = -1;
7197                 if (lmf_tls_offset >= 64)
7198                         lmf_tls_offset = -1;
7199 #else
7200                 tls_offset_inited = TRUE;
7201 #ifdef MONO_XEN_OPT
7202                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7203 #endif
7204                 appdomain_tls_offset = mono_domain_get_tls_offset ();
7205                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7206                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7207 #endif
7208         }
7209 }
7210
7211 void
7212 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7213 {
7214 }
7215
7216 #ifdef MONO_ARCH_HAVE_IMT
7217
7218 #define CMP_SIZE (6 + 1)
7219 #define CMP_REG_REG_SIZE (4 + 1)
7220 #define BR_SMALL_SIZE 2
7221 #define BR_LARGE_SIZE 6
7222 #define MOV_REG_IMM_SIZE 10
7223 #define MOV_REG_IMM_32BIT_SIZE 6
7224 #define JUMP_REG_SIZE (2 + 1)
7225
7226 static int
7227 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7228 {
7229         int i, distance = 0;
7230         for (i = start; i < target; ++i)
7231                 distance += imt_entries [i]->chunk_size;
7232         return distance;
7233 }
7234
7235 /*
7236  * LOCKING: called with the domain lock held
7237  */
7238 gpointer
7239 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7240         gpointer fail_tramp)
7241 {
7242         int i;
7243         int size = 0;
7244         guint8 *code, *start;
7245         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7246
7247         for (i = 0; i < count; ++i) {
7248                 MonoIMTCheckItem *item = imt_entries [i];
7249                 if (item->is_equals) {
7250                         if (item->check_target_idx) {
7251                                 if (!item->compare_done) {
7252                                         if (amd64_is_imm32 (item->key))
7253                                                 item->chunk_size += CMP_SIZE;
7254                                         else
7255                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7256                                 }
7257                                 if (item->has_target_code) {
7258                                         item->chunk_size += MOV_REG_IMM_SIZE;
7259                                 } else {
7260                                         if (vtable_is_32bit)
7261                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7262                                         else
7263                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7264                                 }
7265                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7266                         } else {
7267                                 if (fail_tramp) {
7268                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7269                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7270                                 } else {
7271                                         if (vtable_is_32bit)
7272                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7273                                         else
7274                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7275                                         item->chunk_size += JUMP_REG_SIZE;
7276                                         /* with assert below:
7277                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7278                                          */
7279                                 }
7280                         }
7281                 } else {
7282                         if (amd64_is_imm32 (item->key))
7283                                 item->chunk_size += CMP_SIZE;
7284                         else
7285                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7286                         item->chunk_size += BR_LARGE_SIZE;
7287                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7288                 }
7289                 size += item->chunk_size;
7290         }
7291         if (fail_tramp)
7292                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7293         else
7294                 code = mono_domain_code_reserve (domain, size);
7295         start = code;
7296         for (i = 0; i < count; ++i) {
7297                 MonoIMTCheckItem *item = imt_entries [i];
7298                 item->code_target = code;
7299                 if (item->is_equals) {
7300                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7301
7302                         if (item->check_target_idx || fail_case) {
7303                                 if (!item->compare_done || fail_case) {
7304                                         if (amd64_is_imm32 (item->key))
7305                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7306                                         else {
7307                                                 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7308                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7309                                         }
7310                                 }
7311                                 item->jmp_code = code;
7312                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7313                                 if (item->has_target_code) {
7314                                         amd64_mov_reg_imm (code, AMD64_R11, item->value.target_code);
7315                                         amd64_jump_reg (code, AMD64_R11);
7316                                 } else {
7317                                         amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7318                                         amd64_jump_membase (code, AMD64_R11, 0);
7319                                 }
7320
7321                                 if (fail_case) {
7322                                         amd64_patch (item->jmp_code, code);
7323                                         amd64_mov_reg_imm (code, AMD64_R11, fail_tramp);
7324                                         amd64_jump_reg (code, AMD64_R11);
7325                                         item->jmp_code = NULL;
7326                                 }
7327                         } else {
7328                                 /* enable the commented code to assert on wrong method */
7329 #if 0
7330                                 if (amd64_is_imm32 (item->key))
7331                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7332                                 else {
7333                                         amd64_mov_reg_imm (code, AMD64_R11, item->key);
7334                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7335                                 }
7336                                 item->jmp_code = code;
7337                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7338                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7339                                 amd64_jump_membase (code, AMD64_R11, 0);
7340                                 amd64_patch (item->jmp_code, code);
7341                                 amd64_breakpoint (code);
7342                                 item->jmp_code = NULL;
7343 #else
7344                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7345                                 amd64_jump_membase (code, AMD64_R11, 0);
7346 #endif
7347                         }
7348                 } else {
7349                         if (amd64_is_imm32 (item->key))
7350                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7351                         else {
7352                                 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7353                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7354                         }
7355                         item->jmp_code = code;
7356                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7357                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7358                         else
7359                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7360                 }
7361                 g_assert (code - item->code_target <= item->chunk_size);
7362         }
7363         /* patch the branches to get to the target items */
7364         for (i = 0; i < count; ++i) {
7365                 MonoIMTCheckItem *item = imt_entries [i];
7366                 if (item->jmp_code) {
7367                         if (item->check_target_idx) {
7368                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7369                         }
7370                 }
7371         }
7372
7373         if (!fail_tramp)
7374                 mono_stats.imt_thunks_size += code - start;
7375         g_assert (code - start <= size);
7376
7377         return start;
7378 }
7379
7380 MonoMethod*
7381 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7382 {
7383         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7384 }
7385 #endif
7386
7387 MonoVTable*
7388 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7389 {
7390         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7391 }
7392
7393 GSList*
7394 mono_arch_get_cie_program (void)
7395 {
7396         GSList *l = NULL;
7397
7398         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
7399         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
7400
7401         return l;
7402 }
7403
7404 MonoInst*
7405 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7406 {
7407         MonoInst *ins = NULL;
7408         int opcode = 0;
7409
7410         if (cmethod->klass == mono_defaults.math_class) {
7411                 if (strcmp (cmethod->name, "Sin") == 0) {
7412                         opcode = OP_SIN;
7413                 } else if (strcmp (cmethod->name, "Cos") == 0) {
7414                         opcode = OP_COS;
7415                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7416                         opcode = OP_SQRT;
7417                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7418                         opcode = OP_ABS;
7419                 }
7420
7421                 if (opcode) {
7422                         MONO_INST_NEW (cfg, ins, opcode);
7423                         ins->type = STACK_R8;
7424                         ins->dreg = mono_alloc_freg (cfg);
7425                         ins->sreg1 = args [0]->dreg;
7426                         MONO_ADD_INS (cfg->cbb, ins);
7427                 }
7428
7429                 opcode = 0;
7430                 if (cfg->opt & MONO_OPT_CMOV) {
7431                         if (strcmp (cmethod->name, "Min") == 0) {
7432                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7433                                         opcode = OP_IMIN;
7434                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7435                                         opcode = OP_IMIN_UN;
7436                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7437                                         opcode = OP_LMIN;
7438                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7439                                         opcode = OP_LMIN_UN;
7440                         } else if (strcmp (cmethod->name, "Max") == 0) {
7441                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7442                                         opcode = OP_IMAX;
7443                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7444                                         opcode = OP_IMAX_UN;
7445                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7446                                         opcode = OP_LMAX;
7447                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7448                                         opcode = OP_LMAX_UN;
7449                         }
7450                 }
7451
7452                 if (opcode) {
7453                         MONO_INST_NEW (cfg, ins, opcode);
7454                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7455                         ins->dreg = mono_alloc_ireg (cfg);
7456                         ins->sreg1 = args [0]->dreg;
7457                         ins->sreg2 = args [1]->dreg;
7458                         MONO_ADD_INS (cfg->cbb, ins);
7459                 }
7460
7461 #if 0
7462                 /* OP_FREM is not IEEE compatible */
7463                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7464                         MONO_INST_NEW (cfg, ins, OP_FREM);
7465                         ins->inst_i0 = args [0];
7466                         ins->inst_i1 = args [1];
7467                 }
7468 #endif
7469         }
7470
7471         /*
7472          * Can't implement CompareExchange methods this way since they have
7473          * three arguments.
7474          */
7475
7476         return ins;
7477 }
7478
7479 gboolean
7480 mono_arch_print_tree (MonoInst *tree, int arity)
7481 {
7482         return 0;
7483 }
7484
7485 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7486 {
7487         MonoInst* ins;
7488
7489         if (appdomain_tls_offset == -1)
7490                 return NULL;
7491
7492         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7493         ins->inst_offset = appdomain_tls_offset;
7494         return ins;
7495 }
7496
7497 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7498
7499 gpointer
7500 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7501 {
7502         switch (reg) {
7503         case AMD64_RCX: return (gpointer)ctx->rcx;
7504         case AMD64_RDX: return (gpointer)ctx->rdx;
7505         case AMD64_RBX: return (gpointer)ctx->rbx;
7506         case AMD64_RBP: return (gpointer)ctx->rbp;
7507         case AMD64_RSP: return (gpointer)ctx->rsp;
7508         default:
7509                 if (reg < 8)
7510                         return _CTX_REG (ctx, rax, reg);
7511                 else if (reg >= 12)
7512                         return _CTX_REG (ctx, r12, reg - 12);
7513                 else
7514                         g_assert_not_reached ();
7515         }
7516 }
7517
7518 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
7519 gpointer
7520 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7521 {
7522         int offset;
7523         gpointer *sp, old_value;
7524         char *bp;
7525         const unsigned char *handler;
7526
7527         /*Decode the first instruction to figure out where did we store the spvar*/
7528         /*Our jit MUST generate the following:
7529          mov    %rsp, ?(%rbp)
7530
7531          Which is encoded as: REX.W 0x89 mod_rm
7532          mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
7533                 mod (reg + imm8):  01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
7534                 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
7535
7536         FIXME can we generate frameless methods on this case?
7537
7538         */
7539         handler = clause->handler_start;
7540
7541         /*REX.W*/
7542         if (*handler != 0x48)
7543                 return NULL;
7544         ++handler;
7545
7546         /*mov r, r/m */
7547         if (*handler != 0x89)
7548                 return NULL;
7549         ++handler;
7550
7551         if (*handler == 0x65)
7552                 offset = *(signed char*)(handler + 1);
7553         else if (*handler == 0xA5)
7554                 offset = *(int*)(handler + 1);
7555         else
7556                 return NULL;
7557
7558         /*Load the spvar*/
7559         bp = MONO_CONTEXT_GET_BP (ctx);
7560         sp = *(gpointer*)(bp + offset);
7561
7562         old_value = *sp;
7563         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7564                 return old_value;
7565
7566         *sp = new_value;
7567
7568         return old_value;
7569 }
7570
7571 /*
7572  * mono_arch_emit_load_aotconst:
7573  *
7574  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
7575  * TARGET from the mscorlib GOT in full-aot code.
7576  * On AMD64, the result is placed into R11.
7577  */
7578 guint8*
7579 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
7580 {
7581         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
7582         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
7583
7584         return code;
7585 }
7586
7587 /*
7588  * mono_arch_get_trampolines:
7589  *
7590  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
7591  * for AOT.
7592  */
7593 GSList *
7594 mono_arch_get_trampolines (gboolean aot)
7595 {
7596         MonoTrampInfo *info;
7597         GSList *tramps = NULL;
7598
7599         mono_arch_get_throw_pending_exception (&info, aot);
7600
7601         tramps = g_slist_append (tramps, info);
7602
7603         return tramps;
7604 }
7605
7606 /* Soft Debug support */
7607 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7608
7609 /*
7610  * mono_arch_set_breakpoint:
7611  *
7612  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7613  * The location should contain code emitted by OP_SEQ_POINT.
7614  */
7615 void
7616 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7617 {
7618         guint8 *code = ip;
7619         guint8 *orig_code = code;
7620
7621         /*
7622          * In production, we will use int3 (has to fix the size in the md
7623          * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7624          * instead.
7625          */
7626         g_assert (code [0] == 0x90);
7627         if (breakpoint_size == 8) {
7628                 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7629         } else {
7630                 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
7631                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
7632         }
7633
7634         g_assert (code - orig_code == breakpoint_size);
7635 }
7636
7637 /*
7638  * mono_arch_clear_breakpoint:
7639  *
7640  *   Clear the breakpoint at IP.
7641  */
7642 void
7643 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7644 {
7645         guint8 *code = ip;
7646         int i;
7647
7648         for (i = 0; i < breakpoint_size; ++i)
7649                 x86_nop (code);
7650 }
7651
7652 gboolean
7653 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7654 {
7655 #ifdef HOST_WIN32
7656         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7657         return FALSE;
7658 #else
7659         siginfo_t* sinfo = (siginfo_t*) info;
7660         /* Sometimes the address is off by 4 */
7661         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7662                 return TRUE;
7663         else
7664                 return FALSE;
7665 #endif
7666 }
7667
7668 /*
7669  * mono_arch_get_ip_for_breakpoint:
7670  *
7671  *   Convert the ip in CTX to the address where a breakpoint was placed.
7672  */
7673 guint8*
7674 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7675 {
7676         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7677
7678         /* ip points to the instruction causing the fault */
7679         ip -= (breakpoint_size - breakpoint_fault_size);
7680
7681         return ip;
7682 }
7683
7684 /*
7685  * mono_arch_skip_breakpoint:
7686  *
7687  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
7688  * we resume, the instruction is not executed again.
7689  */
7690 void
7691 mono_arch_skip_breakpoint (MonoContext *ctx)
7692 {
7693         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
7694 }
7695
7696 /*
7697  * mono_arch_start_single_stepping:
7698  *
7699  *   Start single stepping.
7700  */
7701 void
7702 mono_arch_start_single_stepping (void)
7703 {
7704         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7705 }
7706
7707 /*
7708  * mono_arch_stop_single_stepping:
7709  *
7710  *   Stop single stepping.
7711  */
7712 void
7713 mono_arch_stop_single_stepping (void)
7714 {
7715         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7716 }
7717
7718 /*
7719  * mono_arch_is_single_step_event:
7720  *
7721  *   Return whenever the machine state in SIGCTX corresponds to a single
7722  * step event.
7723  */
7724 gboolean
7725 mono_arch_is_single_step_event (void *info, void *sigctx)
7726 {
7727 #ifdef HOST_WIN32
7728         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7729         return FALSE;
7730 #else
7731         siginfo_t* sinfo = (siginfo_t*) info;
7732         /* Sometimes the address is off by 4 */
7733         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7734                 return TRUE;
7735         else
7736                 return FALSE;
7737 #endif
7738 }
7739
7740 /*
7741  * mono_arch_get_ip_for_single_step:
7742  *
7743  *   Convert the ip in CTX to the address stored in seq_points.
7744  */
7745 guint8*
7746 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7747 {
7748         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7749
7750         ip += single_step_fault_size;
7751
7752         return ip;
7753 }
7754
7755 /*
7756  * mono_arch_skip_single_step:
7757  *
7758  *   Modify CTX so the ip is placed after the single step trigger instruction,
7759  * we resume, the instruction is not executed again.
7760  */
7761 void
7762 mono_arch_skip_single_step (MonoContext *ctx)
7763 {
7764         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
7765 }
7766
7767 /*
7768  * mono_arch_create_seq_point_info:
7769  *
7770  *   Return a pointer to a data structure which is used by the sequence
7771  * point implementation in AOTed code.
7772  */
7773 gpointer
7774 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7775 {
7776         NOT_IMPLEMENTED;
7777         return NULL;
7778 }
7779
7780 #endif