mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/appdomain.h>
  24 #include <mono/metadata/debug-helpers.h>
  25 #include <mono/metadata/threads.h>
  26 #include <mono/metadata/profiler-private.h>
  27 #include <mono/metadata/mono-debug.h>
  28 #include <mono/metadata/gc-internal.h>
  29 #include <mono/utils/mono-math.h>
  30 #include <mono/utils/mono-mmap.h>
  31 #include <mono/utils/mono-memory-model.h>
  32 #include <mono/utils/mono-tls.h>
  33 #include <mono/utils/mono-hwcap-x86.h>
  34
  35 #include "trace.h"
  36 #include "ir-emit.h"
  37 #include "mini-amd64.h"
  38 #include "cpu-amd64.h"
  39 #include "debugger-agent.h"
  40 #include "mini-gc.h"
  41
  42 #ifdef HOST_WIN32
  43 static gint jit_tls_offset = -1;
  44 #endif
  45
  46 #ifdef MONO_XEN_OPT
  47 static gboolean optimize_for_xen = TRUE;
  48 #else
  49 #define optimize_for_xen 0
  50 #endif
  51
  52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  53
  54 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  55
  56 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  57
  58 #ifdef HOST_WIN32
  59 /* Under windows, the calling convention is never stdcall */
  60 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  61 #else
  62 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  63 #endif
  64
  65 /* This mutex protects architecture specific caches */
  66 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  67 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  68 static CRITICAL_SECTION mini_arch_mutex;
  69
  70 MonoBreakpointInfo
  71 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  72
  73 /* Structure used by the sequence points in AOTed code */
  74 typedef struct {
  75         gpointer ss_trigger_page;
  76         gpointer bp_trigger_page;
  77         gpointer bp_addrs [MONO_ZERO_LEN_ARRAY];
  78 } SeqPointInfo;
  79
  80 /*
  81  * The code generated for sequence points reads from this location, which is
  82  * made read-only when single stepping is enabled.
  83  */
  84 static gpointer ss_trigger_page;
  85
  86 /* Enabled breakpoints read from this trigger page */
  87 static gpointer bp_trigger_page;
  88
  89 /* The size of the breakpoint sequence */
  90 static int breakpoint_size;
  91
  92 /* The size of the breakpoint instruction causing the actual fault */
  93 static int breakpoint_fault_size;
  94
  95 /* The size of the single step instruction causing the actual fault */
  96 static int single_step_fault_size;
  97
  98 #ifdef HOST_WIN32
  99 /* On Win64 always reserve first 32 bytes for first four arguments */
 100 #define ARGS_OFFSET 48
 101 #else
 102 #define ARGS_OFFSET 16
 103 #endif
 104 #define GP_SCRATCH_REG AMD64_R11
 105
 106 /*
 107  * AMD64 register usage:
 108  * - callee saved registers are used for global register allocation
 109  * - %r11 is used for materializing 64 bit constants in opcodes
 110  * - the rest is used for local allocation
 111  */
 112
 113 /*
 114  * Floating point comparison results:
 115  *                  ZF PF CF
 116  * A > B            0  0  0
 117  * A < B            0  0  1
 118  * A = B            1  0  0
 119  * A > B            0  0  0
 120  * UNORDERED        1  1  1
 121  */
 122
 123 const char*
 124 mono_arch_regname (int reg)
 125 {
 126         switch (reg) {
 127         case AMD64_RAX: return "%rax";
 128         case AMD64_RBX: return "%rbx";
 129         case AMD64_RCX: return "%rcx";
 130         case AMD64_RDX: return "%rdx";
 131         case AMD64_RSP: return "%rsp";
 132         case AMD64_RBP: return "%rbp";
 133         case AMD64_RDI: return "%rdi";
 134         case AMD64_RSI: return "%rsi";
 135         case AMD64_R8: return "%r8";
 136         case AMD64_R9: return "%r9";
 137         case AMD64_R10: return "%r10";
 138         case AMD64_R11: return "%r11";
 139         case AMD64_R12: return "%r12";
 140         case AMD64_R13: return "%r13";
 141         case AMD64_R14: return "%r14";
 142         case AMD64_R15: return "%r15";
 143         }
 144         return "unknown";
 145 }
 146
 147 static const char * packed_xmmregs [] = {
 148         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 149         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 150 };
 151
 152 static const char * single_xmmregs [] = {
 153         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 154         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 155 };
 156
 157 const char*
 158 mono_arch_fregname (int reg)
 159 {
 160         if (reg < AMD64_XMM_NREG)
 161                 return single_xmmregs [reg];
 162         else
 163                 return "unknown";
 164 }
 165
 166 const char *
 167 mono_arch_xregname (int reg)
 168 {
 169         if (reg < AMD64_XMM_NREG)
 170                 return packed_xmmregs [reg];
 171         else
 172                 return "unknown";
 173 }
 174
 175 static gboolean
 176 debug_omit_fp (void)
 177 {
 178 #if 0
 179         return mono_debug_count ();
 180 #else
 181         return TRUE;
 182 #endif
 183 }
 184
 185 static inline gboolean
 186 amd64_is_near_call (guint8 *code)
 187 {
 188         /* Skip REX */
 189         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 190                 code += 1;
 191
 192         return code [0] == 0xe8;
 193 }
 194
 195 #ifdef __native_client_codegen__
 196
 197 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 198 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 199 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 200 /* We only want to force bundle alignment for the top level instruction,    */
 201 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 202 static MonoNativeTlsKey nacl_instruction_depth;
 203
 204 static MonoNativeTlsKey nacl_rex_tag;
 205 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 206
 207 void
 208 amd64_nacl_clear_legacy_prefix_tag ()
 209 {
 210         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 211 }
 212
 213 void
 214 amd64_nacl_tag_legacy_prefix (guint8* code)
 215 {
 216         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 217                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 218 }
 219
 220 void
 221 amd64_nacl_tag_rex (guint8* code)
 222 {
 223         mono_native_tls_set_value (nacl_rex_tag, code);
 224 }
 225
 226 guint8*
 227 amd64_nacl_get_legacy_prefix_tag ()
 228 {
 229         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 230 }
 231
 232 guint8*
 233 amd64_nacl_get_rex_tag ()
 234 {
 235         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 236 }
 237
 238 /* Increment the instruction "depth" described above */
 239 void
 240 amd64_nacl_instruction_pre ()
 241 {
 242         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 243         depth++;
 244         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 245 }
 246
 247 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 248 /* alignment if depth == 0 (top level instruction)                          */
 249 /* IN: start, end    pointers to instruction beginning and end              */
 250 /* OUT: start, end   pointers to beginning and end after possible alignment */
 251 /* GLOBALS: nacl_instruction_depth     defined above                        */
 252 void
 253 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 254 {
 255         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 256         depth--;
 257         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 258
 259         g_assert ( depth >= 0 );
 260         if (depth == 0) {
 261                 uintptr_t space_in_block;
 262                 uintptr_t instlen;
 263                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 264                 /* if legacy prefix is present, and if it was emitted before */
 265                 /* the start of the instruction sequence, adjust the start   */
 266                 if (prefix != NULL && prefix < *start) {
 267                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 268                         *start = prefix;
 269                 }
 270                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 271                 instlen = (uintptr_t)(*end - *start);
 272                 /* Only check for instructions which are less than        */
 273                 /* kNaClAlignment. The only instructions that should ever */
 274                 /* be that long are call sequences, which are already     */
 275                 /* padded out to align the return to the next bundle.     */
 276                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 277                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 278                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 279                         const size_t length = (size_t)((*end)-(*start));
 280                         g_assert (length < MAX_NACL_INST_LENGTH);
 281
 282                         memcpy (copy_of_instruction, *start, length);
 283                         *start = mono_arch_nacl_pad (*start, space_in_block);
 284                         memcpy (*start, copy_of_instruction, length);
 285                         *end = *start + length;
 286                 }
 287                 amd64_nacl_clear_legacy_prefix_tag ();
 288                 amd64_nacl_tag_rex (NULL);
 289         }
 290 }
 291
 292 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 293 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 294 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 295 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 296 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 297 /* IN:      code                                                            */
 298 /*             pointer to current instruction stream (in the                */
 299 /*             middle of an instruction, after opcode is emitted)           */
 300 /*          basereg/offset/dreg                                             */
 301 /*             operands of normal membase address                           */
 302 /* OUT:     code                                                            */
 303 /*             pointer to the end of the membase/memindex emit              */
 304 /* GLOBALS: nacl_rex_tag                                                    */
 305 /*             position in instruction stream that rex prefix was emitted   */
 306 /*          nacl_legacy_prefix_tag                                          */
 307 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 308 void
 309 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 310 {
 311         gint8 true_basereg = basereg;
 312
 313         /* Cache these values, they might change  */
 314         /* as new instructions are emitted below. */
 315         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 316         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 317
 318         /* 'basereg' is given masked to 0x7 at this point, so check */
 319         /* the rex prefix to see if this is an extended register.   */
 320         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 321                 true_basereg |= 0x8;
 322         }
 323
 324 #define X86_LEA_OPCODE (0x8D)
 325
 326         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 327                 guint8* old_instruction_start;
 328
 329                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 330                 /* 32-bits of the old base register (new index register)     */
 331                 guint8 buf[32];
 332                 guint8* buf_ptr = buf;
 333                 size_t insert_len;
 334
 335                 g_assert (rex_tag != NULL);
 336
 337                 if (IS_REX(*rex_tag)) {
 338                         /* The old rex.B should be the new rex.X */
 339                         if (*rex_tag & AMD64_REX_B) {
 340                                 *rex_tag |= AMD64_REX_X;
 341                         }
 342                         /* Since our new base is %r15 set rex.B */
 343                         *rex_tag |= AMD64_REX_B;
 344                 } else {
 345                         /* Shift the instruction by one byte  */
 346                         /* so we can insert a rex prefix      */
 347                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 348                         *code += 1;
 349                         /* New rex prefix only needs rex.B for %r15 base */
 350                         *rex_tag = AMD64_REX(AMD64_REX_B);
 351                 }
 352
 353                 if (legacy_prefix_tag) {
 354                         old_instruction_start = legacy_prefix_tag;
 355                 } else {
 356                         old_instruction_start = rex_tag;
 357                 }
 358
 359                 /* Clears the upper 32-bits of the previous base register */
 360                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 361                 insert_len = buf_ptr - buf;
 362
 363                 /* Move the old instruction forward to make */
 364                 /* room for 'mov' stored in 'buf_ptr'       */
 365                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 366                 *code += insert_len;
 367                 memcpy (old_instruction_start, buf, insert_len);
 368
 369                 /* Sandboxed replacement for the normal membase_emit */
 370                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 371
 372         } else {
 373                 /* Normal default behavior, emit membase memory location */
 374                 x86_membase_emit_body (*code, dreg, basereg, offset);
 375         }
 376 }
 377
 378
 379 static inline unsigned char*
 380 amd64_skip_nops (unsigned char* code)
 381 {
 382         guint8 in_nop;
 383         do {
 384                 in_nop = 0;
 385                 if (   code[0] == 0x90) {
 386                         in_nop = 1;
 387                         code += 1;
 388                 }
 389                 if (   code[0] == 0x66 && code[1] == 0x90) {
 390                         in_nop = 1;
 391                         code += 2;
 392                 }
 393                 if (code[0] == 0x0f && code[1] == 0x1f
 394                  && code[2] == 0x00) {
 395                         in_nop = 1;
 396                         code += 3;
 397                 }
 398                 if (code[0] == 0x0f && code[1] == 0x1f
 399                  && code[2] == 0x40 && code[3] == 0x00) {
 400                         in_nop = 1;
 401                         code += 4;
 402                 }
 403                 if (code[0] == 0x0f && code[1] == 0x1f
 404                  && code[2] == 0x44 && code[3] == 0x00
 405                  && code[4] == 0x00) {
 406                         in_nop = 1;
 407                         code += 5;
 408                 }
 409                 if (code[0] == 0x66 && code[1] == 0x0f
 410                  && code[2] == 0x1f && code[3] == 0x44
 411                  && code[4] == 0x00 && code[5] == 0x00) {
 412                         in_nop = 1;
 413                         code += 6;
 414                 }
 415                 if (code[0] == 0x0f && code[1] == 0x1f
 416                  && code[2] == 0x80 && code[3] == 0x00
 417                  && code[4] == 0x00 && code[5] == 0x00
 418                  && code[6] == 0x00) {
 419                         in_nop = 1;
 420                         code += 7;
 421                 }
 422                 if (code[0] == 0x0f && code[1] == 0x1f
 423                  && code[2] == 0x84 && code[3] == 0x00
 424                  && code[4] == 0x00 && code[5] == 0x00
 425                  && code[6] == 0x00 && code[7] == 0x00) {
 426                         in_nop = 1;
 427                         code += 8;
 428                 }
 429         } while ( in_nop );
 430         return code;
 431 }
 432
 433 guint8*
 434 mono_arch_nacl_skip_nops (guint8* code)
 435 {
 436   return amd64_skip_nops(code);
 437 }
 438
 439 #endif /*__native_client_codegen__*/
 440
 441 static inline void
 442 amd64_patch (unsigned char* code, gpointer target)
 443 {
 444         guint8 rex = 0;
 445
 446 #ifdef __native_client_codegen__
 447         code = amd64_skip_nops (code);
 448 #endif
 449 #if defined(__native_client_codegen__) && defined(__native_client__)
 450         if (nacl_is_code_address (code)) {
 451                 /* For tail calls, code is patched after being installed */
 452                 /* but not through the normal "patch callsite" method.   */
 453                 unsigned char buf[kNaClAlignment];
 454                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 455                 int ret;
 456                 memcpy (buf, aligned_code, kNaClAlignment);
 457                 /* Patch a temp buffer of bundle size, */
 458                 /* then install to actual location.    */
 459                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 460                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 461                 g_assert (ret == 0);
 462                 return;
 463         }
 464         target = nacl_modify_patch_target (target);
 465 #endif
 466
 467         /* Skip REX */
 468         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 469                 rex = code [0];
 470                 code += 1;
 471         }
 472
 473         if ((code [0] & 0xf8) == 0xb8) {
 474                 /* amd64_set_reg_template */
 475                 *(guint64*)(code + 1) = (guint64)target;
 476         }
 477         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 478                 /* mov 0(%rip), %dreg */
 479                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 480         }
 481         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 482                 /* call *<OFFSET>(%rip) */
 483                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 484         }
 485         else if (code [0] == 0xe8) {
 486                 /* call <DISP> */
 487                 gint64 disp = (guint8*)target - (guint8*)code;
 488                 g_assert (amd64_is_imm32 (disp));
 489                 x86_patch (code, (unsigned char*)target);
 490         }
 491         else
 492                 x86_patch (code, (unsigned char*)target);
 493 }
 494
 495 void
 496 mono_amd64_patch (unsigned char* code, gpointer target)
 497 {
 498         amd64_patch (code, target);
 499 }
 500
 501 typedef enum {
 502         ArgInIReg,
 503         ArgInFloatSSEReg,
 504         ArgInDoubleSSEReg,
 505         ArgOnStack,
 506         ArgValuetypeInReg,
 507         ArgValuetypeAddrInIReg,
 508         ArgNone /* only in pair_storage */
 509 } ArgStorage;
 510
 511 typedef struct {
 512         gint16 offset;
 513         gint8  reg;
 514         ArgStorage storage;
 515
 516         /* Only if storage == ArgValuetypeInReg */
 517         ArgStorage pair_storage [2];
 518         gint8 pair_regs [2];
 519         int nregs;
 520 } ArgInfo;
 521
 522 typedef struct {
 523         int nargs;
 524         guint32 stack_usage;
 525         guint32 reg_usage;
 526         guint32 freg_usage;
 527         gboolean need_stack_align;
 528         gboolean vtype_retaddr;
 529         /* The index of the vret arg in the argument list */
 530         int vret_arg_index;
 531         ArgInfo ret;
 532         ArgInfo sig_cookie;
 533         ArgInfo args [1];
 534 } CallInfo;
 535
 536 #define DEBUG(a) if (cfg->verbose_level > 1) a
 537
 538 #ifdef HOST_WIN32
 539 #define PARAM_REGS 4
 540
 541 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 542
 543 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 544 #else
 545 #define PARAM_REGS 6
 546
 547 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 548
 549  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 550 #endif
 551
 552 static void inline
 553 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 554 {
 555     ainfo->offset = *stack_size;
 556
 557     if (*gr >= PARAM_REGS) {
 558                 ainfo->storage = ArgOnStack;
 559                 /* Since the same stack slot size is used for all arg */
 560                 /*  types, it needs to be big enough to hold them all */
 561                 (*stack_size) += sizeof(mgreg_t);
 562     }
 563     else {
 564                 ainfo->storage = ArgInIReg;
 565                 ainfo->reg = param_regs [*gr];
 566                 (*gr) ++;
 567     }
 568 }
 569
 570 #ifdef HOST_WIN32
 571 #define FLOAT_PARAM_REGS 4
 572 #else
 573 #define FLOAT_PARAM_REGS 8
 574 #endif
 575
 576 static void inline
 577 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 578 {
 579     ainfo->offset = *stack_size;
 580
 581     if (*gr >= FLOAT_PARAM_REGS) {
 582                 ainfo->storage = ArgOnStack;
 583                 /* Since the same stack slot size is used for both float */
 584                 /*  types, it needs to be big enough to hold them both */
 585                 (*stack_size) += sizeof(mgreg_t);
 586     }
 587     else {
 588                 /* A double register */
 589                 if (is_double)
 590                         ainfo->storage = ArgInDoubleSSEReg;
 591                 else
 592                         ainfo->storage = ArgInFloatSSEReg;
 593                 ainfo->reg = *gr;
 594                 (*gr) += 1;
 595     }
 596 }
 597
 598 typedef enum ArgumentClass {
 599         ARG_CLASS_NO_CLASS,
 600         ARG_CLASS_MEMORY,
 601         ARG_CLASS_INTEGER,
 602         ARG_CLASS_SSE
 603 } ArgumentClass;
 604
 605 static ArgumentClass
 606 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 607 {
 608         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 609         MonoType *ptype;
 610
 611         ptype = mini_type_get_underlying_type (gsctx, type);
 612         switch (ptype->type) {
 613         case MONO_TYPE_BOOLEAN:
 614         case MONO_TYPE_CHAR:
 615         case MONO_TYPE_I1:
 616         case MONO_TYPE_U1:
 617         case MONO_TYPE_I2:
 618         case MONO_TYPE_U2:
 619         case MONO_TYPE_I4:
 620         case MONO_TYPE_U4:
 621         case MONO_TYPE_I:
 622         case MONO_TYPE_U:
 623         case MONO_TYPE_STRING:
 624         case MONO_TYPE_OBJECT:
 625         case MONO_TYPE_CLASS:
 626         case MONO_TYPE_SZARRAY:
 627         case MONO_TYPE_PTR:
 628         case MONO_TYPE_FNPTR:
 629         case MONO_TYPE_ARRAY:
 630         case MONO_TYPE_I8:
 631         case MONO_TYPE_U8:
 632                 class2 = ARG_CLASS_INTEGER;
 633                 break;
 634         case MONO_TYPE_R4:
 635         case MONO_TYPE_R8:
 636 #ifdef HOST_WIN32
 637                 class2 = ARG_CLASS_INTEGER;
 638 #else
 639                 class2 = ARG_CLASS_SSE;
 640 #endif
 641                 break;
 642
 643         case MONO_TYPE_TYPEDBYREF:
 644                 g_assert_not_reached ();
 645
 646         case MONO_TYPE_GENERICINST:
 647                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 648                         class2 = ARG_CLASS_INTEGER;
 649                         break;
 650                 }
 651                 /* fall through */
 652         case MONO_TYPE_VALUETYPE: {
 653                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 654                 int i;
 655
 656                 for (i = 0; i < info->num_fields; ++i) {
 657                         class2 = class1;
 658                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 659                 }
 660                 break;
 661         }
 662         default:
 663                 g_assert_not_reached ();
 664         }
 665
 666         /* Merge */
 667         if (class1 == class2)
 668                 ;
 669         else if (class1 == ARG_CLASS_NO_CLASS)
 670                 class1 = class2;
 671         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 672                 class1 = ARG_CLASS_MEMORY;
 673         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 674                 class1 = ARG_CLASS_INTEGER;
 675         else
 676                 class1 = ARG_CLASS_SSE;
 677
 678         return class1;
 679 }
 680 #ifdef __native_client_codegen__
 681
 682 /* Default alignment for Native Client is 32-byte. */
 683 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 684
 685 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 686 /* Check that alignment doesn't cross an alignment boundary.             */
 687 guint8*
 688 mono_arch_nacl_pad(guint8 *code, int pad)
 689 {
 690         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 691
 692         if (pad == 0) return code;
 693         /* assertion: alignment cannot cross a block boundary */
 694         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 695                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 696         while (pad >= kMaxPadding) {
 697                 amd64_padding (code, kMaxPadding);
 698                 pad -= kMaxPadding;
 699         }
 700         if (pad != 0) amd64_padding (code, pad);
 701         return code;
 702 }
 703 #endif
 704
 705 static void
 706 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 707                            gboolean is_return,
 708                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 709 {
 710         guint32 size, quad, nquads, i;
 711         /* Keep track of the size used in each quad so we can */
 712         /* use the right size when copying args/return vars.  */
 713         guint32 quadsize [2] = {8, 8};
 714         ArgumentClass args [2];
 715         MonoMarshalType *info = NULL;
 716         MonoClass *klass;
 717         MonoGenericSharingContext tmp_gsctx;
 718         gboolean pass_on_stack = FALSE;
 719
 720         /*
 721          * The gsctx currently contains no data, it is only used for checking whenever
 722          * open types are allowed, some callers like mono_arch_get_argument_info ()
 723          * don't pass it to us, so work around that.
 724          */
 725         if (!gsctx)
 726                 gsctx = &tmp_gsctx;
 727
 728         klass = mono_class_from_mono_type (type);
 729         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 730 #ifndef HOST_WIN32
 731         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 732                 /* We pass and return vtypes of size 8 in a register */
 733         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 734                 pass_on_stack = TRUE;
 735         }
 736 #else
 737         if (!sig->pinvoke) {
 738                 pass_on_stack = TRUE;
 739         }
 740 #endif
 741
 742         /* If this struct can't be split up naturally into 8-byte */
 743         /* chunks (registers), pass it on the stack.              */
 744         if (sig->pinvoke && !pass_on_stack) {
 745                 guint32 align;
 746                 guint32 field_size;
 747
 748                 info = mono_marshal_load_type_info (klass);
 749                 g_assert(info);
 750                 for (i = 0; i < info->num_fields; ++i) {
 751                         field_size = mono_marshal_type_size (info->fields [i].field->type,
 752                                                            info->fields [i].mspec,
 753                                                            &align, TRUE, klass->unicode);
 754                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
 755                                 pass_on_stack = TRUE;
 756                                 break;
 757                         }
 758                 }
 759         }
 760
 761         if (pass_on_stack) {
 762                 /* Allways pass in memory */
 763                 ainfo->offset = *stack_size;
 764                 *stack_size += ALIGN_TO (size, 8);
 765                 ainfo->storage = ArgOnStack;
 766
 767                 return;
 768         }
 769
 770         /* FIXME: Handle structs smaller than 8 bytes */
 771         //if ((size % 8) != 0)
 772         //      NOT_IMPLEMENTED;
 773
 774         if (size > 8)
 775                 nquads = 2;
 776         else
 777                 nquads = 1;
 778
 779         if (!sig->pinvoke) {
 780                 /* Always pass in 1 or 2 integer registers */
 781                 args [0] = ARG_CLASS_INTEGER;
 782                 args [1] = ARG_CLASS_INTEGER;
 783                 /* Only the simplest cases are supported */
 784                 if (is_return && nquads != 1) {
 785                         args [0] = ARG_CLASS_MEMORY;
 786                         args [1] = ARG_CLASS_MEMORY;
 787                 }
 788         } else {
 789                 /*
 790                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 791                  * The X87 and SSEUP stuff is left out since there are no such types in
 792                  * the CLR.
 793                  */
 794                 info = mono_marshal_load_type_info (klass);
 795                 g_assert (info);
 796
 797 #ifndef HOST_WIN32
 798                 if (info->native_size > 16) {
 799                         ainfo->offset = *stack_size;
 800                         *stack_size += ALIGN_TO (info->native_size, 8);
 801                         ainfo->storage = ArgOnStack;
 802
 803                         return;
 804                 }
 805 #else
 806                 switch (info->native_size) {
 807                 case 1: case 2: case 4: case 8:
 808                         break;
 809                 default:
 810                         if (is_return) {
 811                                 ainfo->storage = ArgOnStack;
 812                                 ainfo->offset = *stack_size;
 813                                 *stack_size += ALIGN_TO (info->native_size, 8);
 814                         }
 815                         else {
 816                                 ainfo->storage = ArgValuetypeAddrInIReg;
 817
 818                                 if (*gr < PARAM_REGS) {
 819                                         ainfo->pair_storage [0] = ArgInIReg;
 820                                         ainfo->pair_regs [0] = param_regs [*gr];
 821                                         (*gr) ++;
 822                                 }
 823                                 else {
 824                                         ainfo->pair_storage [0] = ArgOnStack;
 825                                         ainfo->offset = *stack_size;
 826                                         *stack_size += 8;
 827                                 }
 828                         }
 829
 830                         return;
 831                 }
 832 #endif
 833
 834                 args [0] = ARG_CLASS_NO_CLASS;
 835                 args [1] = ARG_CLASS_NO_CLASS;
 836                 for (quad = 0; quad < nquads; ++quad) {
 837                         int size;
 838                         guint32 align;
 839                         ArgumentClass class1;
 840
 841                         if (info->num_fields == 0)
 842                                 class1 = ARG_CLASS_MEMORY;
 843                         else
 844                                 class1 = ARG_CLASS_NO_CLASS;
 845                         for (i = 0; i < info->num_fields; ++i) {
 846                                 size = mono_marshal_type_size (info->fields [i].field->type,
 847                                                                                            info->fields [i].mspec,
 848                                                                                            &align, TRUE, klass->unicode);
 849                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 850                                         /* Unaligned field */
 851                                         NOT_IMPLEMENTED;
 852                                 }
 853
 854                                 /* Skip fields in other quad */
 855                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 856                                         continue;
 857                                 if ((quad == 1) && (info->fields [i].offset < 8))
 858                                         continue;
 859
 860                                 /* How far into this quad this data extends.*/
 861                                 /* (8 is size of quad) */
 862                                 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
 863
 864                                 class1 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class1);
 865                         }
 866                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 867                         args [quad] = class1;
 868                 }
 869         }
 870
 871         /* Post merger cleanup */
 872         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 873                 args [0] = args [1] = ARG_CLASS_MEMORY;
 874
 875         /* Allocate registers */
 876         {
 877                 int orig_gr = *gr;
 878                 int orig_fr = *fr;
 879
 880                 ainfo->storage = ArgValuetypeInReg;
 881                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 882                 ainfo->nregs = nquads;
 883                 for (quad = 0; quad < nquads; ++quad) {
 884                         switch (args [quad]) {
 885                         case ARG_CLASS_INTEGER:
 886                                 if (*gr >= PARAM_REGS)
 887                                         args [quad] = ARG_CLASS_MEMORY;
 888                                 else {
 889                                         ainfo->pair_storage [quad] = ArgInIReg;
 890                                         if (is_return)
 891                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 892                                         else
 893                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 894                                         (*gr) ++;
 895                                 }
 896                                 break;
 897                         case ARG_CLASS_SSE:
 898                                 if (*fr >= FLOAT_PARAM_REGS)
 899                                         args [quad] = ARG_CLASS_MEMORY;
 900                                 else {
 901                                         if (quadsize[quad] <= 4)
 902                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 903                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 904                                         ainfo->pair_regs [quad] = *fr;
 905                                         (*fr) ++;
 906                                 }
 907                                 break;
 908                         case ARG_CLASS_MEMORY:
 909                                 break;
 910                         default:
 911                                 g_assert_not_reached ();
 912                         }
 913                 }
 914
 915                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 916                         /* Revert possible register assignments */
 917                         *gr = orig_gr;
 918                         *fr = orig_fr;
 919
 920                         ainfo->offset = *stack_size;
 921                         if (sig->pinvoke)
 922                                 *stack_size += ALIGN_TO (info->native_size, 8);
 923                         else
 924                                 *stack_size += nquads * sizeof(mgreg_t);
 925                         ainfo->storage = ArgOnStack;
 926                 }
 927         }
 928 }
 929
 930 /*
 931  * get_call_info:
 932  *
 933  *  Obtain information about a call according to the calling convention.
 934  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 935  * Draft Version 0.23" document for more information.
 936  */
 937 static CallInfo*
 938 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 939 {
 940         guint32 i, gr, fr, pstart;
 941         MonoType *ret_type;
 942         int n = sig->hasthis + sig->param_count;
 943         guint32 stack_size = 0;
 944         CallInfo *cinfo;
 945         gboolean is_pinvoke = sig->pinvoke;
 946
 947         if (mp)
 948                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 949         else
 950                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 951
 952         cinfo->nargs = n;
 953
 954         gr = 0;
 955         fr = 0;
 956
 957         /* return value */
 958         {
 959                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 960                 switch (ret_type->type) {
 961                 case MONO_TYPE_BOOLEAN:
 962                 case MONO_TYPE_I1:
 963                 case MONO_TYPE_U1:
 964                 case MONO_TYPE_I2:
 965                 case MONO_TYPE_U2:
 966                 case MONO_TYPE_CHAR:
 967                 case MONO_TYPE_I4:
 968                 case MONO_TYPE_U4:
 969                 case MONO_TYPE_I:
 970                 case MONO_TYPE_U:
 971                 case MONO_TYPE_PTR:
 972                 case MONO_TYPE_FNPTR:
 973                 case MONO_TYPE_CLASS:
 974                 case MONO_TYPE_OBJECT:
 975                 case MONO_TYPE_SZARRAY:
 976                 case MONO_TYPE_ARRAY:
 977                 case MONO_TYPE_STRING:
 978                         cinfo->ret.storage = ArgInIReg;
 979                         cinfo->ret.reg = AMD64_RAX;
 980                         break;
 981                 case MONO_TYPE_U8:
 982                 case MONO_TYPE_I8:
 983                         cinfo->ret.storage = ArgInIReg;
 984                         cinfo->ret.reg = AMD64_RAX;
 985                         break;
 986                 case MONO_TYPE_R4:
 987                         cinfo->ret.storage = ArgInFloatSSEReg;
 988                         cinfo->ret.reg = AMD64_XMM0;
 989                         break;
 990                 case MONO_TYPE_R8:
 991                         cinfo->ret.storage = ArgInDoubleSSEReg;
 992                         cinfo->ret.reg = AMD64_XMM0;
 993                         break;
 994                 case MONO_TYPE_GENERICINST:
 995                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 996                                 cinfo->ret.storage = ArgInIReg;
 997                                 cinfo->ret.reg = AMD64_RAX;
 998                                 break;
 999                         }
1000                         /* fall through */
1001 #if defined( __native_client_codegen__ )
1002                 case MONO_TYPE_TYPEDBYREF:
1003 #endif
1004                 case MONO_TYPE_VALUETYPE: {
1005                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1006
1007                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1008                         if (cinfo->ret.storage == ArgOnStack) {
1009                                 cinfo->vtype_retaddr = TRUE;
1010                                 /* The caller passes the address where the value is stored */
1011                         }
1012                         break;
1013                 }
1014 #if !defined( __native_client_codegen__ )
1015                 case MONO_TYPE_TYPEDBYREF:
1016                         /* Same as a valuetype with size 24 */
1017                         cinfo->vtype_retaddr = TRUE;
1018                         break;
1019 #endif
1020                 case MONO_TYPE_VOID:
1021                         break;
1022                 default:
1023                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1024                 }
1025         }
1026
1027         pstart = 0;
1028         /*
1029          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1030          * the first argument, allowing 'this' to be always passed in the first arg reg.
1031          * Also do this if the first argument is a reference type, since virtual calls
1032          * are sometimes made using calli without sig->hasthis set, like in the delegate
1033          * invoke wrappers.
1034          */
1035         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1036                 if (sig->hasthis) {
1037                         add_general (&gr, &stack_size, cinfo->args + 0);
1038                 } else {
1039                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1040                         pstart = 1;
1041                 }
1042                 add_general (&gr, &stack_size, &cinfo->ret);
1043                 cinfo->vret_arg_index = 1;
1044         } else {
1045                 /* this */
1046                 if (sig->hasthis)
1047                         add_general (&gr, &stack_size, cinfo->args + 0);
1048
1049                 if (cinfo->vtype_retaddr)
1050                         add_general (&gr, &stack_size, &cinfo->ret);
1051         }
1052
1053         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1054                 gr = PARAM_REGS;
1055                 fr = FLOAT_PARAM_REGS;
1056
1057                 /* Emit the signature cookie just before the implicit arguments */
1058                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1059         }
1060
1061         for (i = pstart; i < sig->param_count; ++i) {
1062                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1063                 MonoType *ptype;
1064
1065 #ifdef HOST_WIN32
1066                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1067                 if (gr > fr)
1068                         fr = gr;
1069                 else if (fr > gr)
1070                         gr = fr;
1071 #endif
1072
1073                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1074                         /* We allways pass the sig cookie on the stack for simplicity */
1075                         /*
1076                          * Prevent implicit arguments + the sig cookie from being passed
1077                          * in registers.
1078                          */
1079                         gr = PARAM_REGS;
1080                         fr = FLOAT_PARAM_REGS;
1081
1082                         /* Emit the signature cookie just before the implicit arguments */
1083                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1084                 }
1085
1086                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1087                 switch (ptype->type) {
1088                 case MONO_TYPE_BOOLEAN:
1089                 case MONO_TYPE_I1:
1090                 case MONO_TYPE_U1:
1091                         add_general (&gr, &stack_size, ainfo);
1092                         break;
1093                 case MONO_TYPE_I2:
1094                 case MONO_TYPE_U2:
1095                 case MONO_TYPE_CHAR:
1096                         add_general (&gr, &stack_size, ainfo);
1097                         break;
1098                 case MONO_TYPE_I4:
1099                 case MONO_TYPE_U4:
1100                         add_general (&gr, &stack_size, ainfo);
1101                         break;
1102                 case MONO_TYPE_I:
1103                 case MONO_TYPE_U:
1104                 case MONO_TYPE_PTR:
1105                 case MONO_TYPE_FNPTR:
1106                 case MONO_TYPE_CLASS:
1107                 case MONO_TYPE_OBJECT:
1108                 case MONO_TYPE_STRING:
1109                 case MONO_TYPE_SZARRAY:
1110                 case MONO_TYPE_ARRAY:
1111                         add_general (&gr, &stack_size, ainfo);
1112                         break;
1113                 case MONO_TYPE_GENERICINST:
1114                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1115                                 add_general (&gr, &stack_size, ainfo);
1116                                 break;
1117                         }
1118                         /* fall through */
1119                 case MONO_TYPE_VALUETYPE:
1120                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1121                         break;
1122                 case MONO_TYPE_TYPEDBYREF:
1123 #if defined( HOST_WIN32 ) || defined( __native_client_codegen__ )
1124                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1125 #else
1126                         stack_size += sizeof (MonoTypedRef);
1127                         ainfo->storage = ArgOnStack;
1128 #endif
1129                         break;
1130                 case MONO_TYPE_U8:
1131                 case MONO_TYPE_I8:
1132                         add_general (&gr, &stack_size, ainfo);
1133                         break;
1134                 case MONO_TYPE_R4:
1135                         add_float (&fr, &stack_size, ainfo, FALSE);
1136                         break;
1137                 case MONO_TYPE_R8:
1138                         add_float (&fr, &stack_size, ainfo, TRUE);
1139                         break;
1140                 default:
1141                         g_assert_not_reached ();
1142                 }
1143         }
1144
1145         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1146                 gr = PARAM_REGS;
1147                 fr = FLOAT_PARAM_REGS;
1148
1149                 /* Emit the signature cookie just before the implicit arguments */
1150                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1151         }
1152
1153 #ifdef HOST_WIN32
1154         // There always is 32 bytes reserved on the stack when calling on Winx64
1155         stack_size += 0x20;
1156 #endif
1157
1158 #ifndef MONO_AMD64_NO_PUSHES
1159         if (stack_size & 0x8) {
1160                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1161                 cinfo->need_stack_align = TRUE;
1162                 stack_size += 8;
1163         }
1164 #endif
1165
1166         cinfo->stack_usage = stack_size;
1167         cinfo->reg_usage = gr;
1168         cinfo->freg_usage = fr;
1169         return cinfo;
1170 }
1171
1172 /*
1173  * mono_arch_get_argument_info:
1174  * @csig:  a method signature
1175  * @param_count: the number of parameters to consider
1176  * @arg_info: an array to store the result infos
1177  *
1178  * Gathers information on parameters such as size, alignment and
1179  * padding. arg_info should be large enought to hold param_count + 1 entries.
1180  *
1181  * Returns the size of the argument area on the stack.
1182  */
1183 int
1184 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1185 {
1186         int k;
1187         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1188         guint32 args_size = cinfo->stack_usage;
1189
1190         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1191         if (csig->hasthis) {
1192                 arg_info [0].offset = 0;
1193         }
1194
1195         for (k = 0; k < param_count; k++) {
1196                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1197                 /* FIXME: */
1198                 arg_info [k + 1].size = 0;
1199         }
1200
1201         g_free (cinfo);
1202
1203         return args_size;
1204 }
1205
1206 gboolean
1207 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1208 {
1209         CallInfo *c1, *c2;
1210         gboolean res;
1211         MonoType *callee_ret;
1212
1213         c1 = get_call_info (NULL, NULL, caller_sig);
1214         c2 = get_call_info (NULL, NULL, callee_sig);
1215         res = c1->stack_usage >= c2->stack_usage;
1216         callee_ret = mini_replace_type (callee_sig->ret);
1217         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1218                 /* An address on the callee's stack is passed as the first argument */
1219                 res = FALSE;
1220
1221         g_free (c1);
1222         g_free (c2);
1223
1224         return res;
1225 }
1226
1227 /*
1228  * Initialize the cpu to execute managed code.
1229  */
1230 void
1231 mono_arch_cpu_init (void)
1232 {
1233 #ifndef _MSC_VER
1234         guint16 fpcw;
1235
1236         /* spec compliance requires running with double precision */
1237         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1238         fpcw &= ~X86_FPCW_PRECC_MASK;
1239         fpcw |= X86_FPCW_PREC_DOUBLE;
1240         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1241         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1242 #else
1243         /* TODO: This is crashing on Win64 right now.
1244         * _control87 (_PC_53, MCW_PC);
1245         */
1246 #endif
1247 }
1248
1249 /*
1250  * Initialize architecture specific code.
1251  */
1252 void
1253 mono_arch_init (void)
1254 {
1255         int flags;
1256
1257         InitializeCriticalSection (&mini_arch_mutex);
1258 #if defined(__native_client_codegen__)
1259         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1260         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1261         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1262         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1263 #endif
1264
1265 #ifdef MONO_ARCH_NOMAP32BIT
1266         flags = MONO_MMAP_READ;
1267         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1268         breakpoint_size = 13;
1269         breakpoint_fault_size = 3;
1270 #else
1271         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1272         /* amd64_mov_reg_mem () */
1273         breakpoint_size = 8;
1274         breakpoint_fault_size = 8;
1275 #endif
1276
1277         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1278         single_step_fault_size = 4;
1279
1280         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1281         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1282         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1283
1284         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1285         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1286         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1287 }
1288
1289 /*
1290  * Cleanup architecture specific code.
1291  */
1292 void
1293 mono_arch_cleanup (void)
1294 {
1295         DeleteCriticalSection (&mini_arch_mutex);
1296 #if defined(__native_client_codegen__)
1297         mono_native_tls_free (nacl_instruction_depth);
1298         mono_native_tls_free (nacl_rex_tag);
1299         mono_native_tls_free (nacl_legacy_prefix_tag);
1300 #endif
1301 }
1302
1303 /*
1304  * This function returns the optimizations supported on this cpu.
1305  */
1306 guint32
1307 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1308 {
1309         guint32 opts = 0;
1310
1311         *exclude_mask = 0;
1312
1313         if (mono_hwcap_x86_has_cmov) {
1314                 opts |= MONO_OPT_CMOV;
1315
1316                 if (mono_hwcap_x86_has_fcmov)
1317                         opts |= MONO_OPT_FCMOV;
1318                 else
1319                         *exclude_mask |= MONO_OPT_FCMOV;
1320         } else {
1321                 *exclude_mask |= MONO_OPT_CMOV;
1322         }
1323
1324         return opts;
1325 }
1326
1327 /*
1328  * This function test for all SSE functions supported.
1329  *
1330  * Returns a bitmask corresponding to all supported versions.
1331  *
1332  */
1333 guint32
1334 mono_arch_cpu_enumerate_simd_versions (void)
1335 {
1336         guint32 sse_opts = 0;
1337
1338         if (mono_hwcap_x86_has_sse1)
1339                 sse_opts |= SIMD_VERSION_SSE1;
1340
1341         if (mono_hwcap_x86_has_sse2)
1342                 sse_opts |= SIMD_VERSION_SSE2;
1343
1344         if (mono_hwcap_x86_has_sse3)
1345                 sse_opts |= SIMD_VERSION_SSE3;
1346
1347         if (mono_hwcap_x86_has_ssse3)
1348                 sse_opts |= SIMD_VERSION_SSSE3;
1349
1350         if (mono_hwcap_x86_has_sse41)
1351                 sse_opts |= SIMD_VERSION_SSE41;
1352
1353         if (mono_hwcap_x86_has_sse42)
1354                 sse_opts |= SIMD_VERSION_SSE42;
1355
1356         if (mono_hwcap_x86_has_sse4a)
1357                 sse_opts |= SIMD_VERSION_SSE4a;
1358
1359         return sse_opts;
1360 }
1361
1362 #ifndef DISABLE_JIT
1363
1364 GList *
1365 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1366 {
1367         GList *vars = NULL;
1368         int i;
1369
1370         for (i = 0; i < cfg->num_varinfo; i++) {
1371                 MonoInst *ins = cfg->varinfo [i];
1372                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1373
1374                 /* unused vars */
1375                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1376                         continue;
1377
1378                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1379                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1380                         continue;
1381
1382                 if (mono_is_regsize_var (ins->inst_vtype)) {
1383                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1384                         g_assert (i == vmv->idx);
1385                         vars = g_list_prepend (vars, vmv);
1386                 }
1387         }
1388
1389         vars = mono_varlist_sort (cfg, vars, 0);
1390
1391         return vars;
1392 }
1393
1394 /**
1395  * mono_arch_compute_omit_fp:
1396  *
1397  *   Determine whenever the frame pointer can be eliminated.
1398  */
1399 static void
1400 mono_arch_compute_omit_fp (MonoCompile *cfg)
1401 {
1402         MonoMethodSignature *sig;
1403         MonoMethodHeader *header;
1404         int i, locals_size;
1405         CallInfo *cinfo;
1406
1407         if (cfg->arch.omit_fp_computed)
1408                 return;
1409
1410         header = cfg->header;
1411
1412         sig = mono_method_signature (cfg->method);
1413
1414         if (!cfg->arch.cinfo)
1415                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1416         cinfo = cfg->arch.cinfo;
1417
1418         /*
1419          * FIXME: Remove some of the restrictions.
1420          */
1421         cfg->arch.omit_fp = TRUE;
1422         cfg->arch.omit_fp_computed = TRUE;
1423
1424 #ifdef __native_client_codegen__
1425         /* NaCl modules may not change the value of RBP, so it cannot be */
1426         /* used as a normal register, but it can be used as a frame pointer*/
1427         cfg->disable_omit_fp = TRUE;
1428         cfg->arch.omit_fp = FALSE;
1429 #endif
1430
1431 #ifdef HOST_WIN32
1432         cfg->arch.omit_fp = FALSE;
1433 #endif
1434
1435         if (cfg->disable_omit_fp)
1436                 cfg->arch.omit_fp = FALSE;
1437
1438         if (!debug_omit_fp ())
1439                 cfg->arch.omit_fp = FALSE;
1440         /*
1441         if (cfg->method->save_lmf)
1442                 cfg->arch.omit_fp = FALSE;
1443         */
1444         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1445                 cfg->arch.omit_fp = FALSE;
1446         if (header->num_clauses)
1447                 cfg->arch.omit_fp = FALSE;
1448         if (cfg->param_area)
1449                 cfg->arch.omit_fp = FALSE;
1450         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1451                 cfg->arch.omit_fp = FALSE;
1452         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1453                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1454                 cfg->arch.omit_fp = FALSE;
1455         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1456                 ArgInfo *ainfo = &cinfo->args [i];
1457
1458                 if (ainfo->storage == ArgOnStack) {
1459                         /*
1460                          * The stack offset can only be determined when the frame
1461                          * size is known.
1462                          */
1463                         cfg->arch.omit_fp = FALSE;
1464                 }
1465         }
1466
1467         locals_size = 0;
1468         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1469                 MonoInst *ins = cfg->varinfo [i];
1470                 int ialign;
1471
1472                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1473         }
1474 }
1475
1476 GList *
1477 mono_arch_get_global_int_regs (MonoCompile *cfg)
1478 {
1479         GList *regs = NULL;
1480
1481         mono_arch_compute_omit_fp (cfg);
1482
1483         if (cfg->globalra) {
1484                 if (cfg->arch.omit_fp)
1485                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1486
1487                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1488                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1489                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1490                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1491 #ifndef __native_client_codegen__
1492                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1493 #endif
1494
1495                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1496                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1497                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1498                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1499                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1500                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1501                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1502                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1503         } else {
1504                 if (cfg->arch.omit_fp)
1505                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1506
1507                 /* We use the callee saved registers for global allocation */
1508                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1509                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1510                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1511                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1512 #ifndef __native_client_codegen__
1513                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1514 #endif
1515 #ifdef HOST_WIN32
1516                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1517                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1518 #endif
1519         }
1520
1521         return regs;
1522 }
1523
1524 GList*
1525 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1526 {
1527         GList *regs = NULL;
1528         int i;
1529
1530         /* All XMM registers */
1531         for (i = 0; i < 16; ++i)
1532                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1533
1534         return regs;
1535 }
1536
1537 GList*
1538 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1539 {
1540         static GList *r = NULL;
1541
1542         if (r == NULL) {
1543                 GList *regs = NULL;
1544
1545                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1546                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1547                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1548                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1549                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1550 #ifndef __native_client_codegen__
1551                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1552 #endif
1553
1554                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1555                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1556                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1557                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1558                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1559                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1560                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1561                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1562
1563                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1564         }
1565
1566         return r;
1567 }
1568
1569 GList*
1570 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1571 {
1572         int i;
1573         static GList *r = NULL;
1574
1575         if (r == NULL) {
1576                 GList *regs = NULL;
1577
1578                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1579                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1580
1581                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1582         }
1583
1584         return r;
1585 }
1586
1587 /*
1588  * mono_arch_regalloc_cost:
1589  *
1590  *  Return the cost, in number of memory references, of the action of
1591  * allocating the variable VMV into a register during global register
1592  * allocation.
1593  */
1594 guint32
1595 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1596 {
1597         MonoInst *ins = cfg->varinfo [vmv->idx];
1598
1599         if (cfg->method->save_lmf)
1600                 /* The register is already saved */
1601                 /* substract 1 for the invisible store in the prolog */
1602                 return (ins->opcode == OP_ARG) ? 0 : 1;
1603         else
1604                 /* push+pop */
1605                 return (ins->opcode == OP_ARG) ? 1 : 2;
1606 }
1607
1608 /*
1609  * mono_arch_fill_argument_info:
1610  *
1611  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1612  * of the method.
1613  */
1614 void
1615 mono_arch_fill_argument_info (MonoCompile *cfg)
1616 {
1617         MonoType *sig_ret;
1618         MonoMethodSignature *sig;
1619         MonoMethodHeader *header;
1620         MonoInst *ins;
1621         int i;
1622         CallInfo *cinfo;
1623
1624         header = cfg->header;
1625
1626         sig = mono_method_signature (cfg->method);
1627
1628         cinfo = cfg->arch.cinfo;
1629         sig_ret = mini_replace_type (sig->ret);
1630
1631         /*
1632          * Contrary to mono_arch_allocate_vars (), the information should describe
1633          * where the arguments are at the beginning of the method, not where they can be
1634          * accessed during the execution of the method. The later makes no sense for the
1635          * global register allocator, since a variable can be in more than one location.
1636          */
1637         if (sig_ret->type != MONO_TYPE_VOID) {
1638                 switch (cinfo->ret.storage) {
1639                 case ArgInIReg:
1640                 case ArgInFloatSSEReg:
1641                 case ArgInDoubleSSEReg:
1642                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1643                                 cfg->vret_addr->opcode = OP_REGVAR;
1644                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1645                         }
1646                         else {
1647                                 cfg->ret->opcode = OP_REGVAR;
1648                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1649                         }
1650                         break;
1651                 case ArgValuetypeInReg:
1652                         cfg->ret->opcode = OP_REGOFFSET;
1653                         cfg->ret->inst_basereg = -1;
1654                         cfg->ret->inst_offset = -1;
1655                         break;
1656                 default:
1657                         g_assert_not_reached ();
1658                 }
1659         }
1660
1661         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1662                 ArgInfo *ainfo = &cinfo->args [i];
1663                 MonoType *arg_type;
1664
1665                 ins = cfg->args [i];
1666
1667                 if (sig->hasthis && (i == 0))
1668                         arg_type = &mono_defaults.object_class->byval_arg;
1669                 else
1670                         arg_type = sig->params [i - sig->hasthis];
1671
1672                 switch (ainfo->storage) {
1673                 case ArgInIReg:
1674                 case ArgInFloatSSEReg:
1675                 case ArgInDoubleSSEReg:
1676                         ins->opcode = OP_REGVAR;
1677                         ins->inst_c0 = ainfo->reg;
1678                         break;
1679                 case ArgOnStack:
1680                         ins->opcode = OP_REGOFFSET;
1681                         ins->inst_basereg = -1;
1682                         ins->inst_offset = -1;
1683                         break;
1684                 case ArgValuetypeInReg:
1685                         /* Dummy */
1686                         ins->opcode = OP_NOP;
1687                         break;
1688                 default:
1689                         g_assert_not_reached ();
1690                 }
1691         }
1692 }
1693
1694 void
1695 mono_arch_allocate_vars (MonoCompile *cfg)
1696 {
1697         MonoType *sig_ret;
1698         MonoMethodSignature *sig;
1699         MonoMethodHeader *header;
1700         MonoInst *ins;
1701         int i, offset;
1702         guint32 locals_stack_size, locals_stack_align;
1703         gint32 *offsets;
1704         CallInfo *cinfo;
1705
1706         header = cfg->header;
1707
1708         sig = mono_method_signature (cfg->method);
1709
1710         cinfo = cfg->arch.cinfo;
1711         sig_ret = mini_replace_type (sig->ret);
1712
1713         mono_arch_compute_omit_fp (cfg);
1714
1715         /*
1716          * We use the ABI calling conventions for managed code as well.
1717          * Exception: valuetypes are only sometimes passed or returned in registers.
1718          */
1719
1720         /*
1721          * The stack looks like this:
1722          * <incoming arguments passed on the stack>
1723          * <return value>
1724          * <lmf/caller saved registers>
1725          * <locals>
1726          * <spill area>
1727          * <localloc area>  -> grows dynamically
1728          * <params area>
1729          */
1730
1731         if (cfg->arch.omit_fp) {
1732                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1733                 cfg->frame_reg = AMD64_RSP;
1734                 offset = 0;
1735         } else {
1736                 /* Locals are allocated backwards from %fp */
1737                 cfg->frame_reg = AMD64_RBP;
1738                 offset = 0;
1739         }
1740
1741         if (cfg->method->save_lmf) {
1742                 /* The LMF var is allocated normally */
1743         } else {
1744                 if (cfg->arch.omit_fp)
1745                         cfg->arch.reg_save_area_offset = offset;
1746                 /* Reserve space for callee saved registers */
1747                 for (i = 0; i < AMD64_NREG; ++i)
1748                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1749                                 offset += sizeof(mgreg_t);
1750                         }
1751                 if (!cfg->arch.omit_fp)
1752                         cfg->arch.reg_save_area_offset = -offset;
1753         }
1754
1755         if (sig_ret->type != MONO_TYPE_VOID) {
1756                 switch (cinfo->ret.storage) {
1757                 case ArgInIReg:
1758                 case ArgInFloatSSEReg:
1759                 case ArgInDoubleSSEReg:
1760                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1761                                 if (cfg->globalra) {
1762                                         cfg->vret_addr->opcode = OP_REGVAR;
1763                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1764                                 } else {
1765                                         /* The register is volatile */
1766                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1767                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1768                                         if (cfg->arch.omit_fp) {
1769                                                 cfg->vret_addr->inst_offset = offset;
1770                                                 offset += 8;
1771                                         } else {
1772                                                 offset += 8;
1773                                                 cfg->vret_addr->inst_offset = -offset;
1774                                         }
1775                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1776                                                 printf ("vret_addr =");
1777                                                 mono_print_ins (cfg->vret_addr);
1778                                         }
1779                                 }
1780                         }
1781                         else {
1782                                 cfg->ret->opcode = OP_REGVAR;
1783                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1784                         }
1785                         break;
1786                 case ArgValuetypeInReg:
1787                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1788                         cfg->ret->opcode = OP_REGOFFSET;
1789                         cfg->ret->inst_basereg = cfg->frame_reg;
1790                         if (cfg->arch.omit_fp) {
1791                                 cfg->ret->inst_offset = offset;
1792                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1793                         } else {
1794                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1795                                 cfg->ret->inst_offset = - offset;
1796                         }
1797                         break;
1798                 default:
1799                         g_assert_not_reached ();
1800                 }
1801                 if (!cfg->globalra)
1802                         cfg->ret->dreg = cfg->ret->inst_c0;
1803         }
1804
1805         /* Allocate locals */
1806         if (!cfg->globalra) {
1807                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1808                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1809                         char *mname = mono_method_full_name (cfg->method, TRUE);
1810                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1811                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1812                         g_free (mname);
1813                         return;
1814                 }
1815
1816                 if (locals_stack_align) {
1817                         offset += (locals_stack_align - 1);
1818                         offset &= ~(locals_stack_align - 1);
1819                 }
1820                 if (cfg->arch.omit_fp) {
1821                         cfg->locals_min_stack_offset = offset;
1822                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1823                 } else {
1824                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1825                         cfg->locals_max_stack_offset = - offset;
1826                 }
1827
1828                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1829                         if (offsets [i] != -1) {
1830                                 MonoInst *ins = cfg->varinfo [i];
1831                                 ins->opcode = OP_REGOFFSET;
1832                                 ins->inst_basereg = cfg->frame_reg;
1833                                 if (cfg->arch.omit_fp)
1834                                         ins->inst_offset = (offset + offsets [i]);
1835                                 else
1836                                         ins->inst_offset = - (offset + offsets [i]);
1837                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1838                         }
1839                 }
1840                 offset += locals_stack_size;
1841         }
1842
1843         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1844                 g_assert (!cfg->arch.omit_fp);
1845                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1846                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1847         }
1848
1849         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1850                 ins = cfg->args [i];
1851                 if (ins->opcode != OP_REGVAR) {
1852                         ArgInfo *ainfo = &cinfo->args [i];
1853                         gboolean inreg = TRUE;
1854                         MonoType *arg_type;
1855
1856                         if (sig->hasthis && (i == 0))
1857                                 arg_type = &mono_defaults.object_class->byval_arg;
1858                         else
1859                                 arg_type = sig->params [i - sig->hasthis];
1860
1861                         if (cfg->globalra) {
1862                                 /* The new allocator needs info about the original locations of the arguments */
1863                                 switch (ainfo->storage) {
1864                                 case ArgInIReg:
1865                                 case ArgInFloatSSEReg:
1866                                 case ArgInDoubleSSEReg:
1867                                         ins->opcode = OP_REGVAR;
1868                                         ins->inst_c0 = ainfo->reg;
1869                                         break;
1870                                 case ArgOnStack:
1871                                         g_assert (!cfg->arch.omit_fp);
1872                                         ins->opcode = OP_REGOFFSET;
1873                                         ins->inst_basereg = cfg->frame_reg;
1874                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1875                                         break;
1876                                 case ArgValuetypeInReg:
1877                                         ins->opcode = OP_REGOFFSET;
1878                                         ins->inst_basereg = cfg->frame_reg;
1879                                         /* These arguments are saved to the stack in the prolog */
1880                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1881                                         if (cfg->arch.omit_fp) {
1882                                                 ins->inst_offset = offset;
1883                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1884                                         } else {
1885                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1886                                                 ins->inst_offset = - offset;
1887                                         }
1888                                         break;
1889                                 default:
1890                                         g_assert_not_reached ();
1891                                 }
1892
1893                                 continue;
1894                         }
1895
1896                         /* FIXME: Allocate volatile arguments to registers */
1897                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1898                                 inreg = FALSE;
1899
1900                         /*
1901                          * Under AMD64, all registers used to pass arguments to functions
1902                          * are volatile across calls.
1903                          * FIXME: Optimize this.
1904                          */
1905                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1906                                 inreg = FALSE;
1907
1908                         ins->opcode = OP_REGOFFSET;
1909
1910                         switch (ainfo->storage) {
1911                         case ArgInIReg:
1912                         case ArgInFloatSSEReg:
1913                         case ArgInDoubleSSEReg:
1914                                 if (inreg) {
1915                                         ins->opcode = OP_REGVAR;
1916                                         ins->dreg = ainfo->reg;
1917                                 }
1918                                 break;
1919                         case ArgOnStack:
1920                                 g_assert (!cfg->arch.omit_fp);
1921                                 ins->opcode = OP_REGOFFSET;
1922                                 ins->inst_basereg = cfg->frame_reg;
1923                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1924                                 break;
1925                         case ArgValuetypeInReg:
1926                                 break;
1927                         case ArgValuetypeAddrInIReg: {
1928                                 MonoInst *indir;
1929                                 g_assert (!cfg->arch.omit_fp);
1930
1931                                 MONO_INST_NEW (cfg, indir, 0);
1932                                 indir->opcode = OP_REGOFFSET;
1933                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1934                                         indir->inst_basereg = cfg->frame_reg;
1935                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1936                                         offset += (sizeof (gpointer));
1937                                         indir->inst_offset = - offset;
1938                                 }
1939                                 else {
1940                                         indir->inst_basereg = cfg->frame_reg;
1941                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1942                                 }
1943
1944                                 ins->opcode = OP_VTARG_ADDR;
1945                                 ins->inst_left = indir;
1946
1947                                 break;
1948                         }
1949                         default:
1950                                 NOT_IMPLEMENTED;
1951                         }
1952
1953                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1954                                 ins->opcode = OP_REGOFFSET;
1955                                 ins->inst_basereg = cfg->frame_reg;
1956                                 /* These arguments are saved to the stack in the prolog */
1957                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1958                                 if (cfg->arch.omit_fp) {
1959                                         ins->inst_offset = offset;
1960                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1961                                         // Arguments are yet supported by the stack map creation code
1962                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1963                                 } else {
1964                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1965                                         ins->inst_offset = - offset;
1966                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1967                                 }
1968                         }
1969                 }
1970         }
1971
1972         cfg->stack_offset = offset;
1973 }
1974
1975 void
1976 mono_arch_create_vars (MonoCompile *cfg)
1977 {
1978         MonoMethodSignature *sig;
1979         CallInfo *cinfo;
1980         MonoType *sig_ret;
1981
1982         sig = mono_method_signature (cfg->method);
1983
1984         if (!cfg->arch.cinfo)
1985                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1986         cinfo = cfg->arch.cinfo;
1987
1988         if (cinfo->ret.storage == ArgValuetypeInReg)
1989                 cfg->ret_var_is_local = TRUE;
1990
1991         sig_ret = mini_replace_type (sig->ret);
1992         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1993                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1994                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1995                         printf ("vret_addr = ");
1996                         mono_print_ins (cfg->vret_addr);
1997                 }
1998         }
1999
2000         if (cfg->gen_seq_points) {
2001                 MonoInst *ins;
2002
2003                 if (cfg->compile_aot) {
2004                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2005                         ins->flags |= MONO_INST_VOLATILE;
2006                         cfg->arch.seq_point_info_var = ins;
2007                 }
2008
2009             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2010                 ins->flags |= MONO_INST_VOLATILE;
2011                 cfg->arch.ss_trigger_page_var = ins;
2012         }
2013
2014 #ifdef MONO_AMD64_NO_PUSHES
2015         /*
2016          * When this is set, we pass arguments on the stack by moves, and by allocating
2017          * a bigger stack frame, instead of pushes.
2018          * Pushes complicate exception handling because the arguments on the stack have
2019          * to be popped each time a frame is unwound. They also make fp elimination
2020          * impossible.
2021          * FIXME: This doesn't work inside filter/finally clauses, since those execute
2022          * on a new frame which doesn't include a param area.
2023          */
2024         cfg->arch.no_pushes = TRUE;
2025 #endif
2026
2027         if (cfg->method->save_lmf)
2028                 cfg->create_lmf_var = TRUE;
2029
2030 #if !defined(HOST_WIN32)
2031         if (cfg->method->save_lmf) {
2032                 cfg->lmf_ir = TRUE;
2033                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2034                         cfg->lmf_ir_mono_lmf = TRUE;
2035         }
2036 #endif
2037
2038 #ifndef MONO_AMD64_NO_PUSHES
2039         cfg->arch_eh_jit_info = 1;
2040 #endif
2041 }
2042
2043 static void
2044 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2045 {
2046         MonoInst *ins;
2047
2048         switch (storage) {
2049         case ArgInIReg:
2050                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2051                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2052                 ins->sreg1 = tree->dreg;
2053                 MONO_ADD_INS (cfg->cbb, ins);
2054                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2055                 break;
2056         case ArgInFloatSSEReg:
2057                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2058                 ins->dreg = mono_alloc_freg (cfg);
2059                 ins->sreg1 = tree->dreg;
2060                 MONO_ADD_INS (cfg->cbb, ins);
2061
2062                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2063                 break;
2064         case ArgInDoubleSSEReg:
2065                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2066                 ins->dreg = mono_alloc_freg (cfg);
2067                 ins->sreg1 = tree->dreg;
2068                 MONO_ADD_INS (cfg->cbb, ins);
2069
2070                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2071
2072                 break;
2073         default:
2074                 g_assert_not_reached ();
2075         }
2076 }
2077
2078 static int
2079 arg_storage_to_load_membase (ArgStorage storage)
2080 {
2081         switch (storage) {
2082         case ArgInIReg:
2083 #if defined(__mono_ilp32__)
2084                 return OP_LOADI8_MEMBASE;
2085 #else
2086                 return OP_LOAD_MEMBASE;
2087 #endif
2088         case ArgInDoubleSSEReg:
2089                 return OP_LOADR8_MEMBASE;
2090         case ArgInFloatSSEReg:
2091                 return OP_LOADR4_MEMBASE;
2092         default:
2093                 g_assert_not_reached ();
2094         }
2095
2096         return -1;
2097 }
2098
2099 static void
2100 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2101 {
2102         MonoInst *arg;
2103         MonoMethodSignature *tmp_sig;
2104         int sig_reg;
2105
2106         if (call->tail_call)
2107                 NOT_IMPLEMENTED;
2108
2109         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2110
2111         /*
2112          * mono_ArgIterator_Setup assumes the signature cookie is
2113          * passed first and all the arguments which were before it are
2114          * passed on the stack after the signature. So compensate by
2115          * passing a different signature.
2116          */
2117         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2118         tmp_sig->param_count -= call->signature->sentinelpos;
2119         tmp_sig->sentinelpos = 0;
2120         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2121
2122         sig_reg = mono_alloc_ireg (cfg);
2123         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2124
2125         if (cfg->arch.no_pushes) {
2126                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2127         } else {
2128                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2129                 arg->sreg1 = sig_reg;
2130                 MONO_ADD_INS (cfg->cbb, arg);
2131         }
2132 }
2133
2134 static inline LLVMArgStorage
2135 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2136 {
2137         switch (storage) {
2138         case ArgInIReg:
2139                 return LLVMArgInIReg;
2140         case ArgNone:
2141                 return LLVMArgNone;
2142         default:
2143                 g_assert_not_reached ();
2144                 return LLVMArgNone;
2145         }
2146 }
2147
2148 #ifdef ENABLE_LLVM
2149 LLVMCallInfo*
2150 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2151 {
2152         int i, n;
2153         CallInfo *cinfo;
2154         ArgInfo *ainfo;
2155         int j;
2156         LLVMCallInfo *linfo;
2157         MonoType *t, *sig_ret;
2158
2159         n = sig->param_count + sig->hasthis;
2160         sig_ret = mini_replace_type (sig->ret);
2161
2162         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2163
2164         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2165
2166         /*
2167          * LLVM always uses the native ABI while we use our own ABI, the
2168          * only difference is the handling of vtypes:
2169          * - we only pass/receive them in registers in some cases, and only
2170          *   in 1 or 2 integer registers.
2171          */
2172         if (cinfo->ret.storage == ArgValuetypeInReg) {
2173                 if (sig->pinvoke) {
2174                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2175                         cfg->disable_llvm = TRUE;
2176                         return linfo;
2177                 }
2178
2179                 linfo->ret.storage = LLVMArgVtypeInReg;
2180                 for (j = 0; j < 2; ++j)
2181                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2182         }
2183
2184         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2185                 /* Vtype returned using a hidden argument */
2186                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2187                 linfo->vret_arg_index = cinfo->vret_arg_index;
2188         }
2189
2190         for (i = 0; i < n; ++i) {
2191                 ainfo = cinfo->args + i;
2192
2193                 if (i >= sig->hasthis)
2194                         t = sig->params [i - sig->hasthis];
2195                 else
2196                         t = &mono_defaults.int_class->byval_arg;
2197
2198                 linfo->args [i].storage = LLVMArgNone;
2199
2200                 switch (ainfo->storage) {
2201                 case ArgInIReg:
2202                         linfo->args [i].storage = LLVMArgInIReg;
2203                         break;
2204                 case ArgInDoubleSSEReg:
2205                 case ArgInFloatSSEReg:
2206                         linfo->args [i].storage = LLVMArgInFPReg;
2207                         break;
2208                 case ArgOnStack:
2209                         if (MONO_TYPE_ISSTRUCT (t)) {
2210                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2211                         } else {
2212                                 linfo->args [i].storage = LLVMArgInIReg;
2213                                 if (!t->byref) {
2214                                         if (t->type == MONO_TYPE_R4)
2215                                                 linfo->args [i].storage = LLVMArgInFPReg;
2216                                         else if (t->type == MONO_TYPE_R8)
2217                                                 linfo->args [i].storage = LLVMArgInFPReg;
2218                                 }
2219                         }
2220                         break;
2221                 case ArgValuetypeInReg:
2222                         if (sig->pinvoke) {
2223                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2224                                 cfg->disable_llvm = TRUE;
2225                                 return linfo;
2226                         }
2227
2228                         linfo->args [i].storage = LLVMArgVtypeInReg;
2229                         for (j = 0; j < 2; ++j)
2230                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2231                         break;
2232                 default:
2233                         cfg->exception_message = g_strdup ("ainfo->storage");
2234                         cfg->disable_llvm = TRUE;
2235                         break;
2236                 }
2237         }
2238
2239         return linfo;
2240 }
2241 #endif
2242
2243 void
2244 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2245 {
2246         MonoInst *arg, *in;
2247         MonoMethodSignature *sig;
2248         MonoType *sig_ret;
2249         int i, n, stack_size;
2250         CallInfo *cinfo;
2251         ArgInfo *ainfo;
2252
2253         stack_size = 0;
2254
2255         sig = call->signature;
2256         n = sig->param_count + sig->hasthis;
2257
2258         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2259
2260         sig_ret = sig->ret;
2261
2262         if (COMPILE_LLVM (cfg)) {
2263                 /* We shouldn't be called in the llvm case */
2264                 cfg->disable_llvm = TRUE;
2265                 return;
2266         }
2267
2268         if (cinfo->need_stack_align) {
2269                 if (!cfg->arch.no_pushes)
2270                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2271         }
2272
2273         /*
2274          * Emit all arguments which are passed on the stack to prevent register
2275          * allocation problems.
2276          */
2277         if (cfg->arch.no_pushes) {
2278                 for (i = 0; i < n; ++i) {
2279                         MonoType *t;
2280                         ainfo = cinfo->args + i;
2281
2282                         in = call->args [i];
2283
2284                         if (sig->hasthis && i == 0)
2285                                 t = &mono_defaults.object_class->byval_arg;
2286                         else
2287                                 t = sig->params [i - sig->hasthis];
2288
2289                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2290                                 if (!t->byref) {
2291                                         if (t->type == MONO_TYPE_R4)
2292                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2293                                         else if (t->type == MONO_TYPE_R8)
2294                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2295                                         else
2296                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2297                                 } else {
2298                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2299                                 }
2300                                 if (cfg->compute_gc_maps) {
2301                                         MonoInst *def;
2302
2303                                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2304                                 }
2305                         }
2306                 }
2307         }
2308
2309         /*
2310          * Emit all parameters passed in registers in non-reverse order for better readability
2311          * and to help the optimization in emit_prolog ().
2312          */
2313         for (i = 0; i < n; ++i) {
2314                 ainfo = cinfo->args + i;
2315
2316                 in = call->args [i];
2317
2318                 if (ainfo->storage == ArgInIReg)
2319                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2320         }
2321
2322         for (i = n - 1; i >= 0; --i) {
2323                 ainfo = cinfo->args + i;
2324
2325                 in = call->args [i];
2326
2327                 switch (ainfo->storage) {
2328                 case ArgInIReg:
2329                         /* Already done */
2330                         break;
2331                 case ArgInFloatSSEReg:
2332                 case ArgInDoubleSSEReg:
2333                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2334                         break;
2335                 case ArgOnStack:
2336                 case ArgValuetypeInReg:
2337                 case ArgValuetypeAddrInIReg:
2338                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2339                                 MonoInst *call_inst = (MonoInst*)call;
2340                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2341                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2342                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2343                                 guint32 align;
2344                                 guint32 size;
2345
2346                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2347                                         size = sizeof (MonoTypedRef);
2348                                         align = sizeof (gpointer);
2349                                 }
2350                                 else {
2351                                         if (sig->pinvoke)
2352                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2353                                         else {
2354                                                 /*
2355                                                  * Other backends use mono_type_stack_size (), but that
2356                                                  * aligns the size to 8, which is larger than the size of
2357                                                  * the source, leading to reads of invalid memory if the
2358                                                  * source is at the end of address space.
2359                                                  */
2360                                                 size = mono_class_value_size (in->klass, &align);
2361                                         }
2362                                 }
2363                                 g_assert (in->klass);
2364
2365                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2366                                         /* Avoid asserts in emit_memcpy () */
2367                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2368                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2369                                         /* Continue normally */
2370                                 }
2371
2372                                 if (size > 0) {
2373                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2374                                         arg->sreg1 = in->dreg;
2375                                         arg->klass = in->klass;
2376                                         arg->backend.size = size;
2377                                         arg->inst_p0 = call;
2378                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2379                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2380
2381                                         MONO_ADD_INS (cfg->cbb, arg);
2382                                 }
2383                         } else {
2384                                 if (cfg->arch.no_pushes) {
2385                                         /* Already done */
2386                                 } else {
2387                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2388                                         arg->sreg1 = in->dreg;
2389                                         if (!sig->params [i - sig->hasthis]->byref) {
2390                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2391                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2392                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2393                                                         arg->inst_destbasereg = X86_ESP;
2394                                                         arg->inst_offset = 0;
2395                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2396                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2397                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2398                                                         arg->inst_destbasereg = X86_ESP;
2399                                                         arg->inst_offset = 0;
2400                                                 }
2401                                         }
2402                                         MONO_ADD_INS (cfg->cbb, arg);
2403                                 }
2404                         }
2405                         break;
2406                 default:
2407                         g_assert_not_reached ();
2408                 }
2409
2410                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2411                         /* Emit the signature cookie just before the implicit arguments */
2412                         emit_sig_cookie (cfg, call, cinfo);
2413         }
2414
2415         /* Handle the case where there are no implicit arguments */
2416         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2417                 emit_sig_cookie (cfg, call, cinfo);
2418
2419         sig_ret = mini_replace_type (sig->ret);
2420         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2421                 MonoInst *vtarg;
2422
2423                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2424                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2425                                 /*
2426                                  * Tell the JIT to use a more efficient calling convention: call using
2427                                  * OP_CALL, compute the result location after the call, and save the
2428                                  * result there.
2429                                  */
2430                                 call->vret_in_reg = TRUE;
2431                                 /*
2432                                  * Nullify the instruction computing the vret addr to enable
2433                                  * future optimizations.
2434                                  */
2435                                 if (call->vret_var)
2436                                         NULLIFY_INS (call->vret_var);
2437                         } else {
2438                                 if (call->tail_call)
2439                                         NOT_IMPLEMENTED;
2440                                 /*
2441                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2442                                  * the stack. Push the address here, so the call instruction can
2443                                  * access it.
2444                                  */
2445                                 if (!cfg->arch.vret_addr_loc) {
2446                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2447                                         /* Prevent it from being register allocated or optimized away */
2448                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2449                                 }
2450
2451                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2452                         }
2453                 }
2454                 else {
2455                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2456                         vtarg->sreg1 = call->vret_var->dreg;
2457                         vtarg->dreg = mono_alloc_preg (cfg);
2458                         MONO_ADD_INS (cfg->cbb, vtarg);
2459
2460                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2461                 }
2462         }
2463
2464 #ifdef HOST_WIN32
2465         if (call->inst.opcode != OP_TAILCALL) {
2466                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2467         }
2468 #endif
2469
2470         if (cfg->method->save_lmf) {
2471                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2472                 MONO_ADD_INS (cfg->cbb, arg);
2473         }
2474
2475         call->stack_usage = cinfo->stack_usage;
2476 }
2477
2478 void
2479 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2480 {
2481         MonoInst *arg;
2482         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2483         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2484         int size = ins->backend.size;
2485
2486         if (ainfo->storage == ArgValuetypeInReg) {
2487                 MonoInst *load;
2488                 int part;
2489
2490                 for (part = 0; part < 2; ++part) {
2491                         if (ainfo->pair_storage [part] == ArgNone)
2492                                 continue;
2493
2494                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2495                         load->inst_basereg = src->dreg;
2496                         load->inst_offset = part * sizeof(mgreg_t);
2497
2498                         switch (ainfo->pair_storage [part]) {
2499                         case ArgInIReg:
2500                                 load->dreg = mono_alloc_ireg (cfg);
2501                                 break;
2502                         case ArgInDoubleSSEReg:
2503                         case ArgInFloatSSEReg:
2504                                 load->dreg = mono_alloc_freg (cfg);
2505                                 break;
2506                         default:
2507                                 g_assert_not_reached ();
2508                         }
2509                         MONO_ADD_INS (cfg->cbb, load);
2510
2511                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2512                 }
2513         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2514                 MonoInst *vtaddr, *load;
2515                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2516
2517                 g_assert (!cfg->arch.no_pushes);
2518
2519                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2520                 cfg->has_indirection = TRUE;
2521                 load->inst_p0 = vtaddr;
2522                 vtaddr->flags |= MONO_INST_INDIRECT;
2523                 load->type = STACK_MP;
2524                 load->klass = vtaddr->klass;
2525                 load->dreg = mono_alloc_ireg (cfg);
2526                 MONO_ADD_INS (cfg->cbb, load);
2527                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2528
2529                 if (ainfo->pair_storage [0] == ArgInIReg) {
2530                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2531                         arg->dreg = mono_alloc_ireg (cfg);
2532                         arg->sreg1 = load->dreg;
2533                         arg->inst_imm = 0;
2534                         MONO_ADD_INS (cfg->cbb, arg);
2535                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2536                 } else {
2537                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2538                         arg->sreg1 = load->dreg;
2539                         MONO_ADD_INS (cfg->cbb, arg);
2540                 }
2541         } else {
2542                 if (size == 8) {
2543                         if (cfg->arch.no_pushes) {
2544                                 int dreg = mono_alloc_ireg (cfg);
2545
2546                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2547                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2548                         } else {
2549                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2550                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2551                                 arg->inst_basereg = src->dreg;
2552                                 arg->inst_offset = 0;
2553                                 MONO_ADD_INS (cfg->cbb, arg);
2554                         }
2555                 } else if (size <= 40) {
2556                         if (cfg->arch.no_pushes) {
2557                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2558                         } else {
2559                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2560                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2561                         }
2562                 } else {
2563                         if (cfg->arch.no_pushes) {
2564                                 // FIXME: Code growth
2565                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2566                         } else {
2567                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2568                                 arg->inst_basereg = src->dreg;
2569                                 arg->inst_offset = 0;
2570                                 arg->inst_imm = size;
2571                                 MONO_ADD_INS (cfg->cbb, arg);
2572                         }
2573                 }
2574
2575                 if (cfg->compute_gc_maps) {
2576                         MonoInst *def;
2577                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2578                 }
2579         }
2580 }
2581
2582 void
2583 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2584 {
2585         MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2586
2587         if (ret->type == MONO_TYPE_R4) {
2588                 if (COMPILE_LLVM (cfg))
2589                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2590                 else
2591                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2592                 return;
2593         } else if (ret->type == MONO_TYPE_R8) {
2594                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2595                 return;
2596         }
2597
2598         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2599 }
2600
2601 #endif /* DISABLE_JIT */
2602
2603 #define EMIT_COND_BRANCH(ins,cond,sign) \
2604         if (ins->inst_true_bb->native_offset) { \
2605                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2606         } else { \
2607                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2608                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2609             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2610                         x86_branch8 (code, cond, 0, sign); \
2611                 else \
2612                         x86_branch32 (code, cond, 0, sign); \
2613 }
2614
2615 typedef struct {
2616         MonoMethodSignature *sig;
2617         CallInfo *cinfo;
2618 } ArchDynCallInfo;
2619
2620 typedef struct {
2621         mgreg_t regs [PARAM_REGS];
2622         mgreg_t res;
2623         guint8 *ret;
2624 } DynCallArgs;
2625
2626 static gboolean
2627 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2628 {
2629         int i;
2630
2631 #ifdef HOST_WIN32
2632         return FALSE;
2633 #endif
2634
2635         switch (cinfo->ret.storage) {
2636         case ArgNone:
2637         case ArgInIReg:
2638                 break;
2639         case ArgValuetypeInReg: {
2640                 ArgInfo *ainfo = &cinfo->ret;
2641
2642                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2643                         return FALSE;
2644                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2645                         return FALSE;
2646                 break;
2647         }
2648         default:
2649                 return FALSE;
2650         }
2651
2652         for (i = 0; i < cinfo->nargs; ++i) {
2653                 ArgInfo *ainfo = &cinfo->args [i];
2654                 switch (ainfo->storage) {
2655                 case ArgInIReg:
2656                         break;
2657                 case ArgValuetypeInReg:
2658                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2659                                 return FALSE;
2660                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2661                                 return FALSE;
2662                         break;
2663                 default:
2664                         return FALSE;
2665                 }
2666         }
2667
2668         return TRUE;
2669 }
2670
2671 /*
2672  * mono_arch_dyn_call_prepare:
2673  *
2674  *   Return a pointer to an arch-specific structure which contains information
2675  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2676  * supported for SIG.
2677  * This function is equivalent to ffi_prep_cif in libffi.
2678  */
2679 MonoDynCallInfo*
2680 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2681 {
2682         ArchDynCallInfo *info;
2683         CallInfo *cinfo;
2684
2685         cinfo = get_call_info (NULL, NULL, sig);
2686
2687         if (!dyn_call_supported (sig, cinfo)) {
2688                 g_free (cinfo);
2689                 return NULL;
2690         }
2691
2692         info = g_new0 (ArchDynCallInfo, 1);
2693         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2694         info->sig = sig;
2695         info->cinfo = cinfo;
2696
2697         return (MonoDynCallInfo*)info;
2698 }
2699
2700 /*
2701  * mono_arch_dyn_call_free:
2702  *
2703  *   Free a MonoDynCallInfo structure.
2704  */
2705 void
2706 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2707 {
2708         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2709
2710         g_free (ainfo->cinfo);
2711         g_free (ainfo);
2712 }
2713
2714 #if !defined(__native_client__)
2715 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2716 #define GREG_TO_PTR(greg) (gpointer)(greg)
2717 #else
2718 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2719 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2720 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2721 #endif
2722
2723 /*
2724  * mono_arch_get_start_dyn_call:
2725  *
2726  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2727  * store the result into BUF.
2728  * ARGS should be an array of pointers pointing to the arguments.
2729  * RET should point to a memory buffer large enought to hold the result of the
2730  * call.
2731  * This function should be as fast as possible, any work which does not depend
2732  * on the actual values of the arguments should be done in
2733  * mono_arch_dyn_call_prepare ().
2734  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2735  * libffi.
2736  */
2737 void
2738 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2739 {
2740         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2741         DynCallArgs *p = (DynCallArgs*)buf;
2742         int arg_index, greg, i, pindex;
2743         MonoMethodSignature *sig = dinfo->sig;
2744
2745         g_assert (buf_len >= sizeof (DynCallArgs));
2746
2747         p->res = 0;
2748         p->ret = ret;
2749
2750         arg_index = 0;
2751         greg = 0;
2752         pindex = 0;
2753
2754         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2755                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2756                 if (!sig->hasthis)
2757                         pindex = 1;
2758         }
2759
2760         if (dinfo->cinfo->vtype_retaddr)
2761                 p->regs [greg ++] = PTR_TO_GREG(ret);
2762
2763         for (i = pindex; i < sig->param_count; i++) {
2764                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2765                 gpointer *arg = args [arg_index ++];
2766
2767                 if (t->byref) {
2768                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2769                         continue;
2770                 }
2771
2772                 switch (t->type) {
2773                 case MONO_TYPE_STRING:
2774                 case MONO_TYPE_CLASS:
2775                 case MONO_TYPE_ARRAY:
2776                 case MONO_TYPE_SZARRAY:
2777                 case MONO_TYPE_OBJECT:
2778                 case MONO_TYPE_PTR:
2779                 case MONO_TYPE_I:
2780                 case MONO_TYPE_U:
2781 #if !defined(__mono_ilp32__)
2782                 case MONO_TYPE_I8:
2783                 case MONO_TYPE_U8:
2784 #endif
2785                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2786                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2787                         break;
2788 #if defined(__mono_ilp32__)
2789                 case MONO_TYPE_I8:
2790                 case MONO_TYPE_U8:
2791                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2792                         p->regs [greg ++] = *(guint64*)(arg);
2793                         break;
2794 #endif
2795                 case MONO_TYPE_BOOLEAN:
2796                 case MONO_TYPE_U1:
2797                         p->regs [greg ++] = *(guint8*)(arg);
2798                         break;
2799                 case MONO_TYPE_I1:
2800                         p->regs [greg ++] = *(gint8*)(arg);
2801                         break;
2802                 case MONO_TYPE_I2:
2803                         p->regs [greg ++] = *(gint16*)(arg);
2804                         break;
2805                 case MONO_TYPE_U2:
2806                 case MONO_TYPE_CHAR:
2807                         p->regs [greg ++] = *(guint16*)(arg);
2808                         break;
2809                 case MONO_TYPE_I4:
2810                         p->regs [greg ++] = *(gint32*)(arg);
2811                         break;
2812                 case MONO_TYPE_U4:
2813                         p->regs [greg ++] = *(guint32*)(arg);
2814                         break;
2815                 case MONO_TYPE_GENERICINST:
2816                     if (MONO_TYPE_IS_REFERENCE (t)) {
2817                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2818                                 break;
2819                         } else {
2820                                 /* Fall through */
2821                         }
2822                 case MONO_TYPE_VALUETYPE: {
2823                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2824
2825                         g_assert (ainfo->storage == ArgValuetypeInReg);
2826                         if (ainfo->pair_storage [0] != ArgNone) {
2827                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2828                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2829                         }
2830                         if (ainfo->pair_storage [1] != ArgNone) {
2831                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2832                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2833                         }
2834                         break;
2835                 }
2836                 default:
2837                         g_assert_not_reached ();
2838                 }
2839         }
2840
2841         g_assert (greg <= PARAM_REGS);
2842 }
2843
2844 /*
2845  * mono_arch_finish_dyn_call:
2846  *
2847  *   Store the result of a dyn call into the return value buffer passed to
2848  * start_dyn_call ().
2849  * This function should be as fast as possible, any work which does not depend
2850  * on the actual values of the arguments should be done in
2851  * mono_arch_dyn_call_prepare ().
2852  */
2853 void
2854 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2855 {
2856         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2857         MonoMethodSignature *sig = dinfo->sig;
2858         guint8 *ret = ((DynCallArgs*)buf)->ret;
2859         mgreg_t res = ((DynCallArgs*)buf)->res;
2860         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2861
2862         switch (sig_ret->type) {
2863         case MONO_TYPE_VOID:
2864                 *(gpointer*)ret = NULL;
2865                 break;
2866         case MONO_TYPE_STRING:
2867         case MONO_TYPE_CLASS:
2868         case MONO_TYPE_ARRAY:
2869         case MONO_TYPE_SZARRAY:
2870         case MONO_TYPE_OBJECT:
2871         case MONO_TYPE_I:
2872         case MONO_TYPE_U:
2873         case MONO_TYPE_PTR:
2874                 *(gpointer*)ret = GREG_TO_PTR(res);
2875                 break;
2876         case MONO_TYPE_I1:
2877                 *(gint8*)ret = res;
2878                 break;
2879         case MONO_TYPE_U1:
2880         case MONO_TYPE_BOOLEAN:
2881                 *(guint8*)ret = res;
2882                 break;
2883         case MONO_TYPE_I2:
2884                 *(gint16*)ret = res;
2885                 break;
2886         case MONO_TYPE_U2:
2887         case MONO_TYPE_CHAR:
2888                 *(guint16*)ret = res;
2889                 break;
2890         case MONO_TYPE_I4:
2891                 *(gint32*)ret = res;
2892                 break;
2893         case MONO_TYPE_U4:
2894                 *(guint32*)ret = res;
2895                 break;
2896         case MONO_TYPE_I8:
2897                 *(gint64*)ret = res;
2898                 break;
2899         case MONO_TYPE_U8:
2900                 *(guint64*)ret = res;
2901                 break;
2902         case MONO_TYPE_GENERICINST:
2903                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2904                         *(gpointer*)ret = GREG_TO_PTR(res);
2905                         break;
2906                 } else {
2907                         /* Fall through */
2908                 }
2909         case MONO_TYPE_VALUETYPE:
2910                 if (dinfo->cinfo->vtype_retaddr) {
2911                         /* Nothing to do */
2912                 } else {
2913                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2914
2915                         g_assert (ainfo->storage == ArgValuetypeInReg);
2916
2917                         if (ainfo->pair_storage [0] != ArgNone) {
2918                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2919                                 ((mgreg_t*)ret)[0] = res;
2920                         }
2921
2922                         g_assert (ainfo->pair_storage [1] == ArgNone);
2923                 }
2924                 break;
2925         default:
2926                 g_assert_not_reached ();
2927         }
2928 }
2929
2930 /* emit an exception if condition is fail */
2931 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2932         do {                                                        \
2933                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2934                 if (tins == NULL) {                                                                             \
2935                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2936                                         MONO_PATCH_INFO_EXC, exc_name);  \
2937                         x86_branch32 (code, cond, 0, signed);               \
2938                 } else {        \
2939                         EMIT_COND_BRANCH (tins, cond, signed);  \
2940                 }                       \
2941         } while (0);
2942
2943 #define EMIT_FPCOMPARE(code) do { \
2944         amd64_fcompp (code); \
2945         amd64_fnstsw (code); \
2946 } while (0);
2947
2948 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2949     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2950         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2951         amd64_ ##op (code); \
2952         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2953         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2954 } while (0);
2955
2956 static guint8*
2957 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2958 {
2959         gboolean no_patch = FALSE;
2960
2961         /*
2962          * FIXME: Add support for thunks
2963          */
2964         {
2965                 gboolean near_call = FALSE;
2966
2967                 /*
2968                  * Indirect calls are expensive so try to make a near call if possible.
2969                  * The caller memory is allocated by the code manager so it is
2970                  * guaranteed to be at a 32 bit offset.
2971                  */
2972
2973                 if (patch_type != MONO_PATCH_INFO_ABS) {
2974                         /* The target is in memory allocated using the code manager */
2975                         near_call = TRUE;
2976
2977                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2978                                 if (((MonoMethod*)data)->klass->image->aot_module)
2979                                         /* The callee might be an AOT method */
2980                                         near_call = FALSE;
2981                                 if (((MonoMethod*)data)->dynamic)
2982                                         /* The target is in malloc-ed memory */
2983                                         near_call = FALSE;
2984                         }
2985
2986                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2987                                 /*
2988                                  * The call might go directly to a native function without
2989                                  * the wrapper.
2990                                  */
2991                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2992                                 if (mi) {
2993                                         gconstpointer target = mono_icall_get_wrapper (mi);
2994                                         if ((((guint64)target) >> 32) != 0)
2995                                                 near_call = FALSE;
2996                                 }
2997                         }
2998                 }
2999                 else {
3000                         MonoJumpInfo *jinfo = NULL;
3001
3002                         if (cfg->abs_patches)
3003                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
3004                         if (jinfo) {
3005                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3006                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3007                                         if (mi && (((guint64)mi->func) >> 32) == 0)
3008                                                 near_call = TRUE;
3009                                         no_patch = TRUE;
3010                                 } else {
3011                                         /*
3012                                          * This is not really an optimization, but required because the
3013                                          * generic class init trampolines use R11 to pass the vtable.
3014                                          */
3015                                         near_call = TRUE;
3016                                 }
3017                         } else {
3018                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3019                                 if (info) {
3020                                         if (info->func == info->wrapper) {
3021                                                 /* No wrapper */
3022                                                 if ((((guint64)info->func) >> 32) == 0)
3023                                                         near_call = TRUE;
3024                                         }
3025                                         else {
3026                                                 /* See the comment in mono_codegen () */
3027                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3028                                                         near_call = TRUE;
3029                                         }
3030                                 }
3031                                 else if ((((guint64)data) >> 32) == 0) {
3032                                         near_call = TRUE;
3033                                         no_patch = TRUE;
3034                                 }
3035                         }
3036                 }
3037
3038                 if (cfg->method->dynamic)
3039                         /* These methods are allocated using malloc */
3040                         near_call = FALSE;
3041
3042 #ifdef MONO_ARCH_NOMAP32BIT
3043                 near_call = FALSE;
3044 #endif
3045 #if defined(__native_client__)
3046                 /* Always use near_call == TRUE for Native Client */
3047                 near_call = TRUE;
3048 #endif
3049                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3050                 if (optimize_for_xen)
3051                         near_call = FALSE;
3052
3053                 if (cfg->compile_aot) {
3054                         near_call = TRUE;
3055                         no_patch = TRUE;
3056                 }
3057
3058                 if (near_call) {
3059                         /*
3060                          * Align the call displacement to an address divisible by 4 so it does
3061                          * not span cache lines. This is required for code patching to work on SMP
3062                          * systems.
3063                          */
3064                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3065                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3066                                 amd64_padding (code, pad_size);
3067                         }
3068                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3069                         amd64_call_code (code, 0);
3070                 }
3071                 else {
3072                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3073                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3074                         amd64_call_reg (code, GP_SCRATCH_REG);
3075                 }
3076         }
3077
3078         return code;
3079 }
3080
3081 static inline guint8*
3082 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3083 {
3084 #ifdef HOST_WIN32
3085         if (win64_adjust_stack)
3086                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3087 #endif
3088         code = emit_call_body (cfg, code, patch_type, data);
3089 #ifdef HOST_WIN32
3090         if (win64_adjust_stack)
3091                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3092 #endif
3093
3094         return code;
3095 }
3096
3097 static inline int
3098 store_membase_imm_to_store_membase_reg (int opcode)
3099 {
3100         switch (opcode) {
3101         case OP_STORE_MEMBASE_IMM:
3102                 return OP_STORE_MEMBASE_REG;
3103         case OP_STOREI4_MEMBASE_IMM:
3104                 return OP_STOREI4_MEMBASE_REG;
3105         case OP_STOREI8_MEMBASE_IMM:
3106                 return OP_STOREI8_MEMBASE_REG;
3107         }
3108
3109         return -1;
3110 }
3111
3112 #ifndef DISABLE_JIT
3113
3114 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3115
3116 /*
3117  * mono_arch_peephole_pass_1:
3118  *
3119  *   Perform peephole opts which should/can be performed before local regalloc
3120  */
3121 void
3122 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3123 {
3124         MonoInst *ins, *n;
3125
3126         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3127                 MonoInst *last_ins = ins->prev;
3128
3129                 switch (ins->opcode) {
3130                 case OP_ADD_IMM:
3131                 case OP_IADD_IMM:
3132                 case OP_LADD_IMM:
3133                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3134                                 /*
3135                                  * X86_LEA is like ADD, but doesn't have the
3136                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3137                                  * its operand to 64 bit.
3138                                  */
3139                                 ins->opcode = OP_X86_LEA_MEMBASE;
3140                                 ins->inst_basereg = ins->sreg1;
3141                         }
3142                         break;
3143                 case OP_LXOR:
3144                 case OP_IXOR:
3145                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3146                                 MonoInst *ins2;
3147
3148                                 /*
3149                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3150                                  * the latter has length 2-3 instead of 6 (reverse constant
3151                                  * propagation). These instruction sequences are very common
3152                                  * in the initlocals bblock.
3153                                  */
3154                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3155                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3156                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3157                                                 ins2->sreg1 = ins->dreg;
3158                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3159                                                 /* Continue */
3160                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3161                                                 NULLIFY_INS (ins2);
3162                                                 /* Continue */
3163                                         } else {
3164                                                 break;
3165                                         }
3166                                 }
3167                         }
3168                         break;
3169                 case OP_COMPARE_IMM:
3170                 case OP_LCOMPARE_IMM:
3171                         /* OP_COMPARE_IMM (reg, 0)
3172                          * -->
3173                          * OP_AMD64_TEST_NULL (reg)
3174                          */
3175                         if (!ins->inst_imm)
3176                                 ins->opcode = OP_AMD64_TEST_NULL;
3177                         break;
3178                 case OP_ICOMPARE_IMM:
3179                         if (!ins->inst_imm)
3180                                 ins->opcode = OP_X86_TEST_NULL;
3181                         break;
3182                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3183                         /*
3184                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3185                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3186                          * -->
3187                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3188                          * OP_COMPARE_IMM reg, imm
3189                          *
3190                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3191                          */
3192                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3193                             ins->inst_basereg == last_ins->inst_destbasereg &&
3194                             ins->inst_offset == last_ins->inst_offset) {
3195                                         ins->opcode = OP_ICOMPARE_IMM;
3196                                         ins->sreg1 = last_ins->sreg1;
3197
3198                                         /* check if we can remove cmp reg,0 with test null */
3199                                         if (!ins->inst_imm)
3200                                                 ins->opcode = OP_X86_TEST_NULL;
3201                                 }
3202
3203                         break;
3204                 }
3205
3206                 mono_peephole_ins (bb, ins);
3207         }
3208 }
3209
3210 void
3211 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3212 {
3213         MonoInst *ins, *n;
3214
3215         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3216                 switch (ins->opcode) {
3217                 case OP_ICONST:
3218                 case OP_I8CONST: {
3219                         /* reg = 0 -> XOR (reg, reg) */
3220                         /* XOR sets cflags on x86, so we cant do it always */
3221                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3222                                 ins->opcode = OP_LXOR;
3223                                 ins->sreg1 = ins->dreg;
3224                                 ins->sreg2 = ins->dreg;
3225                                 /* Fall through */
3226                         } else {
3227                                 break;
3228                         }
3229                 }
3230                 case OP_LXOR:
3231                         /*
3232                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3233                          * 0 result into 64 bits.
3234                          */
3235                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3236                                 ins->opcode = OP_IXOR;
3237                         }
3238                         /* Fall through */
3239                 case OP_IXOR:
3240                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3241                                 MonoInst *ins2;
3242
3243                                 /*
3244                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3245                                  * the latter has length 2-3 instead of 6 (reverse constant
3246                                  * propagation). These instruction sequences are very common
3247                                  * in the initlocals bblock.
3248                                  */
3249                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3250                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3251                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3252                                                 ins2->sreg1 = ins->dreg;
3253                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3254                                                 /* Continue */
3255                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3256                                                 NULLIFY_INS (ins2);
3257                                                 /* Continue */
3258                                         } else {
3259                                                 break;
3260                                         }
3261                                 }
3262                         }
3263                         break;
3264                 case OP_IADD_IMM:
3265                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3266                                 ins->opcode = OP_X86_INC_REG;
3267                         break;
3268                 case OP_ISUB_IMM:
3269                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3270                                 ins->opcode = OP_X86_DEC_REG;
3271                         break;
3272                 }
3273
3274                 mono_peephole_ins (bb, ins);
3275         }
3276 }
3277
3278 #define NEW_INS(cfg,ins,dest,op) do {   \
3279                 MONO_INST_NEW ((cfg), (dest), (op)); \
3280         (dest)->cil_code = (ins)->cil_code; \
3281         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3282         } while (0)
3283
3284 /*
3285  * mono_arch_lowering_pass:
3286  *
3287  *  Converts complex opcodes into simpler ones so that each IR instruction
3288  * corresponds to one machine instruction.
3289  */
3290 void
3291 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3292 {
3293         MonoInst *ins, *n, *temp;
3294
3295         /*
3296          * FIXME: Need to add more instructions, but the current machine
3297          * description can't model some parts of the composite instructions like
3298          * cdq.
3299          */
3300         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3301                 switch (ins->opcode) {
3302                 case OP_DIV_IMM:
3303                 case OP_REM_IMM:
3304                 case OP_IDIV_IMM:
3305                 case OP_IDIV_UN_IMM:
3306                 case OP_IREM_UN_IMM:
3307                         mono_decompose_op_imm (cfg, bb, ins);
3308                         break;
3309                 case OP_IREM_IMM:
3310                         /* Keep the opcode if we can implement it efficiently */
3311                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
3312                                 mono_decompose_op_imm (cfg, bb, ins);
3313                         break;
3314                 case OP_COMPARE_IMM:
3315                 case OP_LCOMPARE_IMM:
3316                         if (!amd64_is_imm32 (ins->inst_imm)) {
3317                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3318                                 temp->inst_c0 = ins->inst_imm;
3319                                 temp->dreg = mono_alloc_ireg (cfg);
3320                                 ins->opcode = OP_COMPARE;
3321                                 ins->sreg2 = temp->dreg;
3322                         }
3323                         break;
3324 #ifndef __mono_ilp32__
3325                 case OP_LOAD_MEMBASE:
3326 #endif
3327                 case OP_LOADI8_MEMBASE:
3328 #ifndef __native_client_codegen__
3329                 /*  Don't generate memindex opcodes (to simplify */
3330                 /*  read sandboxing) */
3331                         if (!amd64_is_imm32 (ins->inst_offset)) {
3332                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3333                                 temp->inst_c0 = ins->inst_offset;
3334                                 temp->dreg = mono_alloc_ireg (cfg);
3335                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3336                                 ins->inst_indexreg = temp->dreg;
3337                         }
3338 #endif
3339                         break;
3340 #ifndef __mono_ilp32__
3341                 case OP_STORE_MEMBASE_IMM:
3342 #endif
3343                 case OP_STOREI8_MEMBASE_IMM:
3344                         if (!amd64_is_imm32 (ins->inst_imm)) {
3345                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3346                                 temp->inst_c0 = ins->inst_imm;
3347                                 temp->dreg = mono_alloc_ireg (cfg);
3348                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3349                                 ins->sreg1 = temp->dreg;
3350                         }
3351                         break;
3352 #ifdef MONO_ARCH_SIMD_INTRINSICS
3353                 case OP_EXPAND_I1: {
3354                                 int temp_reg1 = mono_alloc_ireg (cfg);
3355                                 int temp_reg2 = mono_alloc_ireg (cfg);
3356                                 int original_reg = ins->sreg1;
3357
3358                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3359                                 temp->sreg1 = original_reg;
3360                                 temp->dreg = temp_reg1;
3361
3362                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3363                                 temp->sreg1 = temp_reg1;
3364                                 temp->dreg = temp_reg2;
3365                                 temp->inst_imm = 8;
3366
3367                                 NEW_INS (cfg, ins, temp, OP_LOR);
3368                                 temp->sreg1 = temp->dreg = temp_reg2;
3369                                 temp->sreg2 = temp_reg1;
3370
3371                                 ins->opcode = OP_EXPAND_I2;
3372                                 ins->sreg1 = temp_reg2;
3373                         }
3374                         break;
3375 #endif
3376                 default:
3377                         break;
3378                 }
3379         }
3380
3381         bb->max_vreg = cfg->next_vreg;
3382 }
3383
3384 static const int
3385 branch_cc_table [] = {
3386         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3387         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3388         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3389 };
3390
3391 /* Maps CMP_... constants to X86_CC_... constants */
3392 static const int
3393 cc_table [] = {
3394         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3395         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3396 };
3397
3398 static const int
3399 cc_signed_table [] = {
3400         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3401         FALSE, FALSE, FALSE, FALSE
3402 };
3403
3404 /*#include "cprop.c"*/
3405
3406 static unsigned char*
3407 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3408 {
3409         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3410
3411         if (size == 1)
3412                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3413         else if (size == 2)
3414                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3415         return code;
3416 }
3417
3418 static unsigned char*
3419 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3420 {
3421         int sreg = tree->sreg1;
3422         int need_touch = FALSE;
3423
3424 #if defined(HOST_WIN32)
3425                 need_touch = TRUE;
3426 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3427         if (!tree->flags & MONO_INST_INIT)
3428                 need_touch = TRUE;
3429 #endif
3430
3431         if (need_touch) {
3432                 guint8* br[5];
3433
3434                 /*
3435                  * Under Windows:
3436                  * If requested stack size is larger than one page,
3437                  * perform stack-touch operation
3438                  */
3439                 /*
3440                  * Generate stack probe code.
3441                  * Under Windows, it is necessary to allocate one page at a time,
3442                  * "touching" stack after each successful sub-allocation. This is
3443                  * because of the way stack growth is implemented - there is a
3444                  * guard page before the lowest stack page that is currently commited.
3445                  * Stack normally grows sequentially so OS traps access to the
3446                  * guard page and commits more pages when needed.
3447                  */
3448                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3449                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3450
3451                 br[2] = code; /* loop */
3452                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3453                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3454                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3455                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3456                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3457                 amd64_patch (br[3], br[2]);
3458                 amd64_test_reg_reg (code, sreg, sreg);
3459                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3460                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3461
3462                 br[1] = code; x86_jump8 (code, 0);
3463
3464                 amd64_patch (br[0], code);
3465                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3466                 amd64_patch (br[1], code);
3467                 amd64_patch (br[4], code);
3468         }
3469         else
3470                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3471
3472         if (tree->flags & MONO_INST_INIT) {
3473                 int offset = 0;
3474                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3475                         amd64_push_reg (code, AMD64_RAX);
3476                         offset += 8;
3477                 }
3478                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3479                         amd64_push_reg (code, AMD64_RCX);
3480                         offset += 8;
3481                 }
3482                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3483                         amd64_push_reg (code, AMD64_RDI);
3484                         offset += 8;
3485                 }
3486
3487                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3488                 if (sreg != AMD64_RCX)
3489                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3490                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3491
3492                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3493                 if (cfg->param_area && cfg->arch.no_pushes)
3494                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3495                 amd64_cld (code);
3496 #if defined(__default_codegen__)
3497                 amd64_prefix (code, X86_REP_PREFIX);
3498                 amd64_stosl (code);
3499 #elif defined(__native_client_codegen__)
3500                 /* NaCl stos pseudo-instruction */
3501                 amd64_codegen_pre(code);
3502                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3503                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3504                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3505                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3506                 amd64_prefix (code, X86_REP_PREFIX);
3507                 amd64_stosl (code);
3508                 amd64_codegen_post(code);
3509 #endif /* __native_client_codegen__ */
3510
3511                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3512                         amd64_pop_reg (code, AMD64_RDI);
3513                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3514                         amd64_pop_reg (code, AMD64_RCX);
3515                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3516                         amd64_pop_reg (code, AMD64_RAX);
3517         }
3518         return code;
3519 }
3520
3521 static guint8*
3522 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3523 {
3524         CallInfo *cinfo;
3525         guint32 quad;
3526
3527         /* Move return value to the target register */
3528         /* FIXME: do this in the local reg allocator */
3529         switch (ins->opcode) {
3530         case OP_CALL:
3531         case OP_CALL_REG:
3532         case OP_CALL_MEMBASE:
3533         case OP_LCALL:
3534         case OP_LCALL_REG:
3535         case OP_LCALL_MEMBASE:
3536                 g_assert (ins->dreg == AMD64_RAX);
3537                 break;
3538         case OP_FCALL:
3539         case OP_FCALL_REG:
3540         case OP_FCALL_MEMBASE:
3541                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3542                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3543                 }
3544                 else {
3545                         if (ins->dreg != AMD64_XMM0)
3546                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3547                 }
3548                 break;
3549         case OP_VCALL:
3550         case OP_VCALL_REG:
3551         case OP_VCALL_MEMBASE:
3552         case OP_VCALL2:
3553         case OP_VCALL2_REG:
3554         case OP_VCALL2_MEMBASE:
3555                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3556                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3557                         MonoInst *loc = cfg->arch.vret_addr_loc;
3558
3559                         /* Load the destination address */
3560                         g_assert (loc->opcode == OP_REGOFFSET);
3561                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3562
3563                         for (quad = 0; quad < 2; quad ++) {
3564                                 switch (cinfo->ret.pair_storage [quad]) {
3565                                 case ArgInIReg:
3566                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3567                                         break;
3568                                 case ArgInFloatSSEReg:
3569                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3570                                         break;
3571                                 case ArgInDoubleSSEReg:
3572                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3573                                         break;
3574                                 case ArgNone:
3575                                         break;
3576                                 default:
3577                                         NOT_IMPLEMENTED;
3578                                 }
3579                         }
3580                 }
3581                 break;
3582         }
3583
3584         return code;
3585 }
3586
3587 #endif /* DISABLE_JIT */
3588
3589 #ifdef __APPLE__
3590 static int tls_gs_offset;
3591 #endif
3592
3593 gboolean
3594 mono_amd64_have_tls_get (void)
3595 {
3596 #ifdef __APPLE__
3597         static gboolean have_tls_get = FALSE;
3598         static gboolean inited = FALSE;
3599         guint8 *ins;
3600
3601         if (inited)
3602                 return have_tls_get;
3603
3604         ins = (guint8*)pthread_getspecific;
3605
3606         /*
3607          * We're looking for these two instructions:
3608          *
3609          * mov    %gs:[offset](,%rdi,8),%rax
3610          * retq
3611          */
3612         have_tls_get = ins [0] == 0x65 &&
3613                        ins [1] == 0x48 &&
3614                        ins [2] == 0x8b &&
3615                        ins [3] == 0x04 &&
3616                        ins [4] == 0xfd &&
3617                        ins [6] == 0x00 &&
3618                        ins [7] == 0x00 &&
3619                        ins [8] == 0x00 &&
3620                        ins [9] == 0xc3;
3621
3622         inited = TRUE;
3623
3624         tls_gs_offset = ins[5];
3625
3626         return have_tls_get;
3627 #else
3628         return TRUE;
3629 #endif
3630 }
3631
3632 int
3633 mono_amd64_get_tls_gs_offset (void)
3634 {
3635 #ifdef TARGET_OSX
3636         return tls_gs_offset;
3637 #else
3638         g_assert_not_reached ();
3639         return -1;
3640 #endif
3641 }
3642
3643 /*
3644  * mono_amd64_emit_tls_get:
3645  * @code: buffer to store code to
3646  * @dreg: hard register where to place the result
3647  * @tls_offset: offset info
3648  *
3649  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3650  * the dreg register the item in the thread local storage identified
3651  * by tls_offset.
3652  *
3653  * Returns: a pointer to the end of the stored code
3654  */
3655 guint8*
3656 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3657 {
3658 #ifdef HOST_WIN32
3659         g_assert (tls_offset < 64);
3660         x86_prefix (code, X86_GS_PREFIX);
3661         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3662 #elif defined(__APPLE__)
3663         x86_prefix (code, X86_GS_PREFIX);
3664         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3665 #else
3666         if (optimize_for_xen) {
3667                 x86_prefix (code, X86_FS_PREFIX);
3668                 amd64_mov_reg_mem (code, dreg, 0, 8);
3669                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3670         } else {
3671                 x86_prefix (code, X86_FS_PREFIX);
3672                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3673         }
3674 #endif
3675         return code;
3676 }
3677
3678 static guint8*
3679 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3680 {
3681         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3682 #ifdef TARGET_OSX
3683         if (dreg != offset_reg)
3684                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3685         amd64_prefix (code, X86_GS_PREFIX);
3686         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3687 #elif defined(__linux__)
3688         int tmpreg = -1;
3689
3690         if (dreg == offset_reg) {
3691                 /* Use a temporary reg by saving it to the redzone */
3692                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3693                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3694                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3695                 offset_reg = tmpreg;
3696         }
3697         x86_prefix (code, X86_FS_PREFIX);
3698         amd64_mov_reg_mem (code, dreg, 0, 8);
3699         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3700         if (tmpreg != -1)
3701                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3702 #else
3703         g_assert_not_reached ();
3704 #endif
3705         return code;
3706 }
3707
3708 static guint8*
3709 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3710 {
3711 #ifdef HOST_WIN32
3712         g_assert_not_reached ();
3713 #elif defined(__APPLE__)
3714         x86_prefix (code, X86_GS_PREFIX);
3715         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3716 #else
3717         g_assert (!optimize_for_xen);
3718         x86_prefix (code, X86_FS_PREFIX);
3719         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3720 #endif
3721         return code;
3722 }
3723
3724 static guint8*
3725 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3726 {
3727         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3728 #ifdef HOST_WIN32
3729         g_assert_not_reached ();
3730 #elif defined(__APPLE__)
3731         x86_prefix (code, X86_GS_PREFIX);
3732         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3733 #else
3734         x86_prefix (code, X86_FS_PREFIX);
3735         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3736 #endif
3737         return code;
3738 }
3739
3740  /*
3741  * mono_arch_translate_tls_offset:
3742  *
3743  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3744  */
3745 int
3746 mono_arch_translate_tls_offset (int offset)
3747 {
3748 #ifdef __APPLE__
3749         return tls_gs_offset + (offset * 8);
3750 #else
3751         return offset;
3752 #endif
3753 }
3754
3755 /*
3756  * emit_setup_lmf:
3757  *
3758  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3759  */
3760 static guint8*
3761 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3762 {
3763         int i;
3764
3765         /*
3766          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3767          */
3768         /*
3769          * sp is saved right before calls but we need to save it here too so
3770          * async stack walks would work.
3771          */
3772         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3773         /* Skip method (only needed for trampoline LMF frames) */
3774         /* Save callee saved regs */
3775         for (i = 0; i < MONO_MAX_IREGS; ++i) {
3776                 int offset;
3777
3778                 switch (i) {
3779                 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
3780                 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
3781                 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
3782                 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
3783                 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
3784 #ifndef __native_client_codegen__
3785                 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
3786 #endif
3787 #ifdef HOST_WIN32
3788                 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
3789                 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
3790 #endif
3791                 default:
3792                         offset = -1;
3793                         break;
3794                 }
3795
3796                 if (offset != -1) {
3797                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
3798                         if ((cfg->arch.omit_fp || (i != AMD64_RBP)) && cfa_offset != -1)
3799                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
3800                 }
3801         }
3802
3803         /* These can't contain refs */
3804         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3805 #ifdef HOST_WIN32
3806         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
3807 #endif
3808         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3809         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3810
3811         /* These are handled automatically by the stack marking code */
3812         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), SLOT_NOREF);
3813         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3814         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), SLOT_NOREF);
3815         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), SLOT_NOREF);
3816         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), SLOT_NOREF);
3817         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), SLOT_NOREF);
3818 #ifdef HOST_WIN32
3819         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), SLOT_NOREF);
3820         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), SLOT_NOREF);
3821 #endif
3822
3823         return code;
3824 }
3825
3826 #ifdef HOST_WIN32
3827 /*
3828  * emit_push_lmf:
3829  *
3830  *   Emit code to push an LMF structure on the LMF stack.
3831  */
3832 static guint8*
3833 emit_push_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, gboolean *args_clobbered)
3834 {
3835         if (jit_tls_offset != -1) {
3836                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, jit_tls_offset);
3837                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
3838         } else {
3839                 /*
3840                  * The call might clobber argument registers, but they are already
3841                  * saved to the stack/global regs.
3842                  */
3843                 if (args_clobbered)
3844                         *args_clobbered = TRUE;
3845                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3846                                                   (gpointer)"mono_get_lmf_addr", TRUE);
3847         }
3848
3849         /* Save lmf_addr */
3850         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, sizeof(gpointer));
3851         /* Save previous_lmf */
3852         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, sizeof(gpointer));
3853         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, sizeof(gpointer));
3854         /* Set new lmf */
3855         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3856         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, sizeof(gpointer));
3857
3858         return code;
3859 }
3860 #endif
3861
3862 #ifdef HOST_WIN32
3863 /*
3864  * emit_pop_lmf:
3865  *
3866  *   Emit code to pop an LMF structure from the LMF stack.
3867  */
3868 static guint8*
3869 emit_pop_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
3870 {
3871         /* Restore previous lmf */
3872         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3873         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sizeof(gpointer));
3874         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, sizeof(gpointer));
3875
3876         return code;
3877 }
3878 #endif
3879
3880 #define REAL_PRINT_REG(text,reg) \
3881 mono_assert (reg >= 0); \
3882 amd64_push_reg (code, AMD64_RAX); \
3883 amd64_push_reg (code, AMD64_RDX); \
3884 amd64_push_reg (code, AMD64_RCX); \
3885 amd64_push_reg (code, reg); \
3886 amd64_push_imm (code, reg); \
3887 amd64_push_imm (code, text " %d %p\n"); \
3888 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3889 amd64_call_reg (code, AMD64_RAX); \
3890 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3891 amd64_pop_reg (code, AMD64_RCX); \
3892 amd64_pop_reg (code, AMD64_RDX); \
3893 amd64_pop_reg (code, AMD64_RAX);
3894
3895 /* benchmark and set based on cpu */
3896 #define LOOP_ALIGNMENT 8
3897 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3898
3899 #ifndef DISABLE_JIT
3900 void
3901 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3902 {
3903         MonoInst *ins;
3904         MonoCallInst *call;
3905         guint offset;
3906         guint8 *code = cfg->native_code + cfg->code_len;
3907         MonoInst *last_ins = NULL;
3908         guint last_offset = 0;
3909         int max_len;
3910
3911         /* Fix max_offset estimate for each successor bb */
3912         if (cfg->opt & MONO_OPT_BRANCH) {
3913                 int current_offset = cfg->code_len;
3914                 MonoBasicBlock *current_bb;
3915                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3916                         current_bb->max_offset = current_offset;
3917                         current_offset += current_bb->max_length;
3918                 }
3919         }
3920
3921         if (cfg->opt & MONO_OPT_LOOP) {
3922                 int pad, align = LOOP_ALIGNMENT;
3923                 /* set alignment depending on cpu */
3924                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3925                         pad = align - pad;
3926                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3927                         amd64_padding (code, pad);
3928                         cfg->code_len += pad;
3929                         bb->native_offset = cfg->code_len;
3930                 }
3931         }
3932
3933 #if defined(__native_client_codegen__)
3934         /* For Native Client, all indirect call/jump targets must be */
3935         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3936         /* indirectly as well.                                       */
3937         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3938                                       (bb->flags & BB_EXCEPTION_HANDLER);
3939
3940         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3941                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3942                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3943                 cfg->code_len += pad;
3944                 bb->native_offset = cfg->code_len;
3945         }
3946 #endif  /*__native_client_codegen__*/
3947
3948         if (cfg->verbose_level > 2)
3949                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3950
3951         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3952                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3953                 g_assert (!cfg->compile_aot);
3954
3955                 cov->data [bb->dfn].cil_code = bb->cil_code;
3956                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3957                 /* this is not thread save, but good enough */
3958                 amd64_inc_membase (code, AMD64_R11, 0);
3959         }
3960
3961         offset = code - cfg->native_code;
3962
3963         mono_debug_open_block (cfg, bb, offset);
3964
3965     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3966                 x86_breakpoint (code);
3967
3968         MONO_BB_FOR_EACH_INS (bb, ins) {
3969                 offset = code - cfg->native_code;
3970
3971                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3972
3973 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3974
3975                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3976                         cfg->code_size *= 2;
3977                         cfg->native_code = mono_realloc_native_code(cfg);
3978                         code = cfg->native_code + offset;
3979                         cfg->stat_code_reallocs++;
3980                 }
3981
3982                 if (cfg->debug_info)
3983                         mono_debug_record_line_number (cfg, ins, offset);
3984
3985                 switch (ins->opcode) {
3986                 case OP_BIGMUL:
3987                         amd64_mul_reg (code, ins->sreg2, TRUE);
3988                         break;
3989                 case OP_BIGMUL_UN:
3990                         amd64_mul_reg (code, ins->sreg2, FALSE);
3991                         break;
3992                 case OP_X86_SETEQ_MEMBASE:
3993                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3994                         break;
3995                 case OP_STOREI1_MEMBASE_IMM:
3996                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3997                         break;
3998                 case OP_STOREI2_MEMBASE_IMM:
3999                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
4000                         break;
4001                 case OP_STOREI4_MEMBASE_IMM:
4002                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
4003                         break;
4004                 case OP_STOREI1_MEMBASE_REG:
4005                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
4006                         break;
4007                 case OP_STOREI2_MEMBASE_REG:
4008                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4009                         break;
4010                 /* In AMD64 NaCl, pointers are 4 bytes, */
4011                 /*  so STORE_* != STOREI8_*. Likewise below. */
4012                 case OP_STORE_MEMBASE_REG:
4013                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4014                         break;
4015                 case OP_STOREI8_MEMBASE_REG:
4016                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4017                         break;
4018                 case OP_STOREI4_MEMBASE_REG:
4019                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4020                         break;
4021                 case OP_STORE_MEMBASE_IMM:
4022 #ifndef __native_client_codegen__
4023                         /* In NaCl, this could be a PCONST type, which could */
4024                         /* mean a pointer type was copied directly into the  */
4025                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
4026                         /* the value would be 0x00000000FFFFFFFF which is    */
4027                         /* not proper for an imm32 unless you cast it.       */
4028                         g_assert (amd64_is_imm32 (ins->inst_imm));
4029 #endif
4030                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4031                         break;
4032                 case OP_STOREI8_MEMBASE_IMM:
4033                         g_assert (amd64_is_imm32 (ins->inst_imm));
4034                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4035                         break;
4036                 case OP_LOAD_MEM:
4037 #ifdef __mono_ilp32__
4038                         /* In ILP32, pointers are 4 bytes, so separate these */
4039                         /* cases, use literal 8 below where we really want 8 */
4040                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4041                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4042                         break;
4043 #endif
4044                 case OP_LOADI8_MEM:
4045                         // FIXME: Decompose this earlier
4046                         if (amd64_is_imm32 (ins->inst_imm))
4047                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4048                         else {
4049                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4050                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4051                         }
4052                         break;
4053                 case OP_LOADI4_MEM:
4054                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4055                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4056                         break;
4057                 case OP_LOADU4_MEM:
4058                         // FIXME: Decompose this earlier
4059                         if (amd64_is_imm32 (ins->inst_imm))
4060                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4061                         else {
4062                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4063                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4064                         }
4065                         break;
4066                 case OP_LOADU1_MEM:
4067                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4068                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4069                         break;
4070                 case OP_LOADU2_MEM:
4071                         /* For NaCl, pointers are 4 bytes, so separate these */
4072                         /* cases, use literal 8 below where we really want 8 */
4073                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4074                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4075                         break;
4076                 case OP_LOAD_MEMBASE:
4077                         g_assert (amd64_is_imm32 (ins->inst_offset));
4078                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4079                         break;
4080                 case OP_LOADI8_MEMBASE:
4081                         /* Use literal 8 instead of sizeof pointer or */
4082                         /* register, we really want 8 for this opcode */
4083                         g_assert (amd64_is_imm32 (ins->inst_offset));
4084                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4085                         break;
4086                 case OP_LOADI4_MEMBASE:
4087                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4088                         break;
4089                 case OP_LOADU4_MEMBASE:
4090                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4091                         break;
4092                 case OP_LOADU1_MEMBASE:
4093                         /* The cpu zero extends the result into 64 bits */
4094                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4095                         break;
4096                 case OP_LOADI1_MEMBASE:
4097                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4098                         break;
4099                 case OP_LOADU2_MEMBASE:
4100                         /* The cpu zero extends the result into 64 bits */
4101                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4102                         break;
4103                 case OP_LOADI2_MEMBASE:
4104                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4105                         break;
4106                 case OP_AMD64_LOADI8_MEMINDEX:
4107                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4108                         break;
4109                 case OP_LCONV_TO_I1:
4110                 case OP_ICONV_TO_I1:
4111                 case OP_SEXT_I1:
4112                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4113                         break;
4114                 case OP_LCONV_TO_I2:
4115                 case OP_ICONV_TO_I2:
4116                 case OP_SEXT_I2:
4117                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4118                         break;
4119                 case OP_LCONV_TO_U1:
4120                 case OP_ICONV_TO_U1:
4121                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4122                         break;
4123                 case OP_LCONV_TO_U2:
4124                 case OP_ICONV_TO_U2:
4125                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4126                         break;
4127                 case OP_ZEXT_I4:
4128                         /* Clean out the upper word */
4129                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4130                         break;
4131                 case OP_SEXT_I4:
4132                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4133                         break;
4134                 case OP_COMPARE:
4135                 case OP_LCOMPARE:
4136                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4137                         break;
4138                 case OP_COMPARE_IMM:
4139 #if defined(__mono_ilp32__)
4140                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4141                         g_assert (amd64_is_imm32 (ins->inst_imm));
4142                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4143                         break;
4144 #endif
4145                 case OP_LCOMPARE_IMM:
4146                         g_assert (amd64_is_imm32 (ins->inst_imm));
4147                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4148                         break;
4149                 case OP_X86_COMPARE_REG_MEMBASE:
4150                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4151                         break;
4152                 case OP_X86_TEST_NULL:
4153                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4154                         break;
4155                 case OP_AMD64_TEST_NULL:
4156                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4157                         break;
4158
4159                 case OP_X86_ADD_REG_MEMBASE:
4160                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4161                         break;
4162                 case OP_X86_SUB_REG_MEMBASE:
4163                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4164                         break;
4165                 case OP_X86_AND_REG_MEMBASE:
4166                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4167                         break;
4168                 case OP_X86_OR_REG_MEMBASE:
4169                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4170                         break;
4171                 case OP_X86_XOR_REG_MEMBASE:
4172                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4173                         break;
4174
4175                 case OP_X86_ADD_MEMBASE_IMM:
4176                         /* FIXME: Make a 64 version too */
4177                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4178                         break;
4179                 case OP_X86_SUB_MEMBASE_IMM:
4180                         g_assert (amd64_is_imm32 (ins->inst_imm));
4181                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4182                         break;
4183                 case OP_X86_AND_MEMBASE_IMM:
4184                         g_assert (amd64_is_imm32 (ins->inst_imm));
4185                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4186                         break;
4187                 case OP_X86_OR_MEMBASE_IMM:
4188                         g_assert (amd64_is_imm32 (ins->inst_imm));
4189                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4190                         break;
4191                 case OP_X86_XOR_MEMBASE_IMM:
4192                         g_assert (amd64_is_imm32 (ins->inst_imm));
4193                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4194                         break;
4195                 case OP_X86_ADD_MEMBASE_REG:
4196                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4197                         break;
4198                 case OP_X86_SUB_MEMBASE_REG:
4199                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4200                         break;
4201                 case OP_X86_AND_MEMBASE_REG:
4202                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4203                         break;
4204                 case OP_X86_OR_MEMBASE_REG:
4205                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4206                         break;
4207                 case OP_X86_XOR_MEMBASE_REG:
4208                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4209                         break;
4210                 case OP_X86_INC_MEMBASE:
4211                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4212                         break;
4213                 case OP_X86_INC_REG:
4214                         amd64_inc_reg_size (code, ins->dreg, 4);
4215                         break;
4216                 case OP_X86_DEC_MEMBASE:
4217                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4218                         break;
4219                 case OP_X86_DEC_REG:
4220                         amd64_dec_reg_size (code, ins->dreg, 4);
4221                         break;
4222                 case OP_X86_MUL_REG_MEMBASE:
4223                 case OP_X86_MUL_MEMBASE_REG:
4224                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4225                         break;
4226                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4227                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4228                         break;
4229                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4230                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4231                         break;
4232                 case OP_AMD64_COMPARE_MEMBASE_REG:
4233                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4234                         break;
4235                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4236                         g_assert (amd64_is_imm32 (ins->inst_imm));
4237                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4238                         break;
4239                 case OP_X86_COMPARE_MEMBASE8_IMM:
4240                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4241                         break;
4242                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4243                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4244                         break;
4245                 case OP_AMD64_COMPARE_REG_MEMBASE:
4246                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4247                         break;
4248
4249                 case OP_AMD64_ADD_REG_MEMBASE:
4250                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4251                         break;
4252                 case OP_AMD64_SUB_REG_MEMBASE:
4253                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4254                         break;
4255                 case OP_AMD64_AND_REG_MEMBASE:
4256                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4257                         break;
4258                 case OP_AMD64_OR_REG_MEMBASE:
4259                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4260                         break;
4261                 case OP_AMD64_XOR_REG_MEMBASE:
4262                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4263                         break;
4264
4265                 case OP_AMD64_ADD_MEMBASE_REG:
4266                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4267                         break;
4268                 case OP_AMD64_SUB_MEMBASE_REG:
4269                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4270                         break;
4271                 case OP_AMD64_AND_MEMBASE_REG:
4272                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4273                         break;
4274                 case OP_AMD64_OR_MEMBASE_REG:
4275                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4276                         break;
4277                 case OP_AMD64_XOR_MEMBASE_REG:
4278                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4279                         break;
4280
4281                 case OP_AMD64_ADD_MEMBASE_IMM:
4282                         g_assert (amd64_is_imm32 (ins->inst_imm));
4283                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4284                         break;
4285                 case OP_AMD64_SUB_MEMBASE_IMM:
4286                         g_assert (amd64_is_imm32 (ins->inst_imm));
4287                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4288                         break;
4289                 case OP_AMD64_AND_MEMBASE_IMM:
4290                         g_assert (amd64_is_imm32 (ins->inst_imm));
4291                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4292                         break;
4293                 case OP_AMD64_OR_MEMBASE_IMM:
4294                         g_assert (amd64_is_imm32 (ins->inst_imm));
4295                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4296                         break;
4297                 case OP_AMD64_XOR_MEMBASE_IMM:
4298                         g_assert (amd64_is_imm32 (ins->inst_imm));
4299                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4300                         break;
4301
4302                 case OP_BREAK:
4303                         amd64_breakpoint (code);
4304                         break;
4305                 case OP_RELAXED_NOP:
4306                         x86_prefix (code, X86_REP_PREFIX);
4307                         x86_nop (code);
4308                         break;
4309                 case OP_HARD_NOP:
4310                         x86_nop (code);
4311                         break;
4312                 case OP_NOP:
4313                 case OP_DUMMY_USE:
4314                 case OP_DUMMY_STORE:
4315                 case OP_DUMMY_ICONST:
4316                 case OP_DUMMY_R8CONST:
4317                 case OP_NOT_REACHED:
4318                 case OP_NOT_NULL:
4319                         break;
4320                 case OP_SEQ_POINT: {
4321                         int i;
4322
4323                         /*
4324                          * Read from the single stepping trigger page. This will cause a
4325                          * SIGSEGV when single stepping is enabled.
4326                          * We do this _before_ the breakpoint, so single stepping after
4327                          * a breakpoint is hit will step to the next IL offset.
4328                          */
4329                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4330                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4331
4332                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4333                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4334                         }
4335
4336                         /*
4337                          * This is the address which is saved in seq points,
4338                          */
4339                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4340
4341                         if (cfg->compile_aot) {
4342                                 guint32 offset = code - cfg->native_code;
4343                                 guint32 val;
4344                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4345
4346                                 /* Load info var */
4347                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4348                                 val = ((offset) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4349                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4350                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4351                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4352                         } else {
4353                                 /*
4354                                  * A placeholder for a possible breakpoint inserted by
4355                                  * mono_arch_set_breakpoint ().
4356                                  */
4357                                 for (i = 0; i < breakpoint_size; ++i)
4358                                         x86_nop (code);
4359                         }
4360                         /*
4361                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4362                          * to another IL offset.
4363                          */
4364                         x86_nop (code);
4365                         break;
4366                 }
4367                 case OP_ADDCC:
4368                 case OP_LADDCC:
4369                 case OP_LADD:
4370                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4371                         break;
4372                 case OP_ADC:
4373                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4374                         break;
4375                 case OP_ADD_IMM:
4376                 case OP_LADD_IMM:
4377                         g_assert (amd64_is_imm32 (ins->inst_imm));
4378                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4379                         break;
4380                 case OP_ADC_IMM:
4381                         g_assert (amd64_is_imm32 (ins->inst_imm));
4382                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4383                         break;
4384                 case OP_SUBCC:
4385                 case OP_LSUBCC:
4386                 case OP_LSUB:
4387                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4388                         break;
4389                 case OP_SBB:
4390                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4391                         break;
4392                 case OP_SUB_IMM:
4393                 case OP_LSUB_IMM:
4394                         g_assert (amd64_is_imm32 (ins->inst_imm));
4395                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4396                         break;
4397                 case OP_SBB_IMM:
4398                         g_assert (amd64_is_imm32 (ins->inst_imm));
4399                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4400                         break;
4401                 case OP_LAND:
4402                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4403                         break;
4404                 case OP_AND_IMM:
4405                 case OP_LAND_IMM:
4406                         g_assert (amd64_is_imm32 (ins->inst_imm));
4407                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4408                         break;
4409                 case OP_LMUL:
4410                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4411                         break;
4412                 case OP_MUL_IMM:
4413                 case OP_LMUL_IMM:
4414                 case OP_IMUL_IMM: {
4415                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4416
4417                         switch (ins->inst_imm) {
4418                         case 2:
4419                                 /* MOV r1, r2 */
4420                                 /* ADD r1, r1 */
4421                                 if (ins->dreg != ins->sreg1)
4422                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4423                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4424                                 break;
4425                         case 3:
4426                                 /* LEA r1, [r2 + r2*2] */
4427                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4428                                 break;
4429                         case 5:
4430                                 /* LEA r1, [r2 + r2*4] */
4431                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4432                                 break;
4433                         case 6:
4434                                 /* LEA r1, [r2 + r2*2] */
4435                                 /* ADD r1, r1          */
4436                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4437                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4438                                 break;
4439                         case 9:
4440                                 /* LEA r1, [r2 + r2*8] */
4441                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4442                                 break;
4443                         case 10:
4444                                 /* LEA r1, [r2 + r2*4] */
4445                                 /* ADD r1, r1          */
4446                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4447                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4448                                 break;
4449                         case 12:
4450                                 /* LEA r1, [r2 + r2*2] */
4451                                 /* SHL r1, 2           */
4452                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4453                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4454                                 break;
4455                         case 25:
4456                                 /* LEA r1, [r2 + r2*4] */
4457                                 /* LEA r1, [r1 + r1*4] */
4458                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4459                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4460                                 break;
4461                         case 100:
4462                                 /* LEA r1, [r2 + r2*4] */
4463                                 /* SHL r1, 2           */
4464                                 /* LEA r1, [r1 + r1*4] */
4465                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4466                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4467                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4468                                 break;
4469                         default:
4470                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4471                                 break;
4472                         }
4473                         break;
4474                 }
4475                 case OP_LDIV:
4476                 case OP_LREM:
4477 #if defined( __native_client_codegen__ )
4478                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4479                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4480 #endif
4481                         /* Regalloc magic makes the div/rem cases the same */
4482                         if (ins->sreg2 == AMD64_RDX) {
4483                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4484                                 amd64_cdq (code);
4485                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4486                         } else {
4487                                 amd64_cdq (code);
4488                                 amd64_div_reg (code, ins->sreg2, TRUE);
4489                         }
4490                         break;
4491                 case OP_LDIV_UN:
4492                 case OP_LREM_UN:
4493 #if defined( __native_client_codegen__ )
4494                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4495                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4496 #endif
4497                         if (ins->sreg2 == AMD64_RDX) {
4498                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4499                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4500                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4501                         } else {
4502                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4503                                 amd64_div_reg (code, ins->sreg2, FALSE);
4504                         }
4505                         break;
4506                 case OP_IDIV:
4507                 case OP_IREM:
4508 #if defined( __native_client_codegen__ )
4509                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4510                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4511 #endif
4512                         if (ins->sreg2 == AMD64_RDX) {
4513                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4514                                 amd64_cdq_size (code, 4);
4515                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4516                         } else {
4517                                 amd64_cdq_size (code, 4);
4518                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4519                         }
4520                         break;
4521                 case OP_IDIV_UN:
4522                 case OP_IREM_UN:
4523 #if defined( __native_client_codegen__ )
4524                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4525                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4526 #endif
4527                         if (ins->sreg2 == AMD64_RDX) {
4528                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4529                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4530                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4531                         } else {
4532                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4533                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4534                         }
4535                         break;
4536                 case OP_IREM_IMM: {
4537                         int power = mono_is_power_of_two (ins->inst_imm);
4538
4539                         g_assert (ins->sreg1 == X86_EAX);
4540                         g_assert (ins->dreg == X86_EAX);
4541                         g_assert (power >= 0);
4542
4543                         if (power == 0) {
4544                                 amd64_mov_reg_imm (code, ins->dreg, 0);
4545                                 break;
4546                         }
4547
4548                         /* Based on gcc code */
4549
4550                         /* Add compensation for negative dividents */
4551                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
4552                         if (power > 1)
4553                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
4554                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
4555                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
4556                         /* Compute remainder */
4557                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
4558                         /* Remove compensation */
4559                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
4560                         break;
4561                 }
4562                 case OP_LMUL_OVF:
4563                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4564                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4565                         break;
4566                 case OP_LOR:
4567                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4568                         break;
4569                 case OP_OR_IMM:
4570                 case OP_LOR_IMM:
4571                         g_assert (amd64_is_imm32 (ins->inst_imm));
4572                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4573                         break;
4574                 case OP_LXOR:
4575                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4576                         break;
4577                 case OP_XOR_IMM:
4578                 case OP_LXOR_IMM:
4579                         g_assert (amd64_is_imm32 (ins->inst_imm));
4580                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4581                         break;
4582                 case OP_LSHL:
4583                         g_assert (ins->sreg2 == AMD64_RCX);
4584                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4585                         break;
4586                 case OP_LSHR:
4587                         g_assert (ins->sreg2 == AMD64_RCX);
4588                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4589                         break;
4590                 case OP_SHR_IMM:
4591                         g_assert (amd64_is_imm32 (ins->inst_imm));
4592                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4593                         break;
4594                 case OP_LSHR_IMM:
4595                         g_assert (amd64_is_imm32 (ins->inst_imm));
4596                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4597                         break;
4598                 case OP_SHR_UN_IMM:
4599                         g_assert (amd64_is_imm32 (ins->inst_imm));
4600                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4601                         break;
4602                 case OP_LSHR_UN_IMM:
4603                         g_assert (amd64_is_imm32 (ins->inst_imm));
4604                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4605                         break;
4606                 case OP_LSHR_UN:
4607                         g_assert (ins->sreg2 == AMD64_RCX);
4608                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4609                         break;
4610                 case OP_SHL_IMM:
4611                         g_assert (amd64_is_imm32 (ins->inst_imm));
4612                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4613                         break;
4614                 case OP_LSHL_IMM:
4615                         g_assert (amd64_is_imm32 (ins->inst_imm));
4616                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4617                         break;
4618
4619                 case OP_IADDCC:
4620                 case OP_IADD:
4621                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4622                         break;
4623                 case OP_IADC:
4624                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4625                         break;
4626                 case OP_IADD_IMM:
4627                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4628                         break;
4629                 case OP_IADC_IMM:
4630                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4631                         break;
4632                 case OP_ISUBCC:
4633                 case OP_ISUB:
4634                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4635                         break;
4636                 case OP_ISBB:
4637                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4638                         break;
4639                 case OP_ISUB_IMM:
4640                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4641                         break;
4642                 case OP_ISBB_IMM:
4643                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4644                         break;
4645                 case OP_IAND:
4646                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4647                         break;
4648                 case OP_IAND_IMM:
4649                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4650                         break;
4651                 case OP_IOR:
4652                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4653                         break;
4654                 case OP_IOR_IMM:
4655                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4656                         break;
4657                 case OP_IXOR:
4658                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4659                         break;
4660                 case OP_IXOR_IMM:
4661                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4662                         break;
4663                 case OP_INEG:
4664                         amd64_neg_reg_size (code, ins->sreg1, 4);
4665                         break;
4666                 case OP_INOT:
4667                         amd64_not_reg_size (code, ins->sreg1, 4);
4668                         break;
4669                 case OP_ISHL:
4670                         g_assert (ins->sreg2 == AMD64_RCX);
4671                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4672                         break;
4673                 case OP_ISHR:
4674                         g_assert (ins->sreg2 == AMD64_RCX);
4675                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4676                         break;
4677                 case OP_ISHR_IMM:
4678                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4679                         break;
4680                 case OP_ISHR_UN_IMM:
4681                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4682                         break;
4683                 case OP_ISHR_UN:
4684                         g_assert (ins->sreg2 == AMD64_RCX);
4685                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4686                         break;
4687                 case OP_ISHL_IMM:
4688                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4689                         break;
4690                 case OP_IMUL:
4691                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4692                         break;
4693                 case OP_IMUL_OVF:
4694                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4695                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4696                         break;
4697                 case OP_IMUL_OVF_UN:
4698                 case OP_LMUL_OVF_UN: {
4699                         /* the mul operation and the exception check should most likely be split */
4700                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4701                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4702                         /*g_assert (ins->sreg2 == X86_EAX);
4703                         g_assert (ins->dreg == X86_EAX);*/
4704                         if (ins->sreg2 == X86_EAX) {
4705                                 non_eax_reg = ins->sreg1;
4706                         } else if (ins->sreg1 == X86_EAX) {
4707                                 non_eax_reg = ins->sreg2;
4708                         } else {
4709                                 /* no need to save since we're going to store to it anyway */
4710                                 if (ins->dreg != X86_EAX) {
4711                                         saved_eax = TRUE;
4712                                         amd64_push_reg (code, X86_EAX);
4713                                 }
4714                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4715                                 non_eax_reg = ins->sreg2;
4716                         }
4717                         if (ins->dreg == X86_EDX) {
4718                                 if (!saved_eax) {
4719                                         saved_eax = TRUE;
4720                                         amd64_push_reg (code, X86_EAX);
4721                                 }
4722                         } else {
4723                                 saved_edx = TRUE;
4724                                 amd64_push_reg (code, X86_EDX);
4725                         }
4726                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4727                         /* save before the check since pop and mov don't change the flags */
4728                         if (ins->dreg != X86_EAX)
4729                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4730                         if (saved_edx)
4731                                 amd64_pop_reg (code, X86_EDX);
4732                         if (saved_eax)
4733                                 amd64_pop_reg (code, X86_EAX);
4734                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4735                         break;
4736                 }
4737                 case OP_ICOMPARE:
4738                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4739                         break;
4740                 case OP_ICOMPARE_IMM:
4741                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4742                         break;
4743                 case OP_IBEQ:
4744                 case OP_IBLT:
4745                 case OP_IBGT:
4746                 case OP_IBGE:
4747                 case OP_IBLE:
4748                 case OP_LBEQ:
4749                 case OP_LBLT:
4750                 case OP_LBGT:
4751                 case OP_LBGE:
4752                 case OP_LBLE:
4753                 case OP_IBNE_UN:
4754                 case OP_IBLT_UN:
4755                 case OP_IBGT_UN:
4756                 case OP_IBGE_UN:
4757                 case OP_IBLE_UN:
4758                 case OP_LBNE_UN:
4759                 case OP_LBLT_UN:
4760                 case OP_LBGT_UN:
4761                 case OP_LBGE_UN:
4762                 case OP_LBLE_UN:
4763                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4764                         break;
4765
4766                 case OP_CMOV_IEQ:
4767                 case OP_CMOV_IGE:
4768                 case OP_CMOV_IGT:
4769                 case OP_CMOV_ILE:
4770                 case OP_CMOV_ILT:
4771                 case OP_CMOV_INE_UN:
4772                 case OP_CMOV_IGE_UN:
4773                 case OP_CMOV_IGT_UN:
4774                 case OP_CMOV_ILE_UN:
4775                 case OP_CMOV_ILT_UN:
4776                 case OP_CMOV_LEQ:
4777                 case OP_CMOV_LGE:
4778                 case OP_CMOV_LGT:
4779                 case OP_CMOV_LLE:
4780                 case OP_CMOV_LLT:
4781                 case OP_CMOV_LNE_UN:
4782                 case OP_CMOV_LGE_UN:
4783                 case OP_CMOV_LGT_UN:
4784                 case OP_CMOV_LLE_UN:
4785                 case OP_CMOV_LLT_UN:
4786                         g_assert (ins->dreg == ins->sreg1);
4787                         /* This needs to operate on 64 bit values */
4788                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4789                         break;
4790
4791                 case OP_LNOT:
4792                         amd64_not_reg (code, ins->sreg1);
4793                         break;
4794                 case OP_LNEG:
4795                         amd64_neg_reg (code, ins->sreg1);
4796                         break;
4797
4798                 case OP_ICONST:
4799                 case OP_I8CONST:
4800                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4801                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4802                         else
4803                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4804                         break;
4805                 case OP_AOTCONST:
4806                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4807                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4808                         break;
4809                 case OP_JUMP_TABLE:
4810                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4811                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4812                         break;
4813                 case OP_MOVE:
4814                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4815                         break;
4816                 case OP_AMD64_SET_XMMREG_R4: {
4817                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4818                         break;
4819                 }
4820                 case OP_AMD64_SET_XMMREG_R8: {
4821                         if (ins->dreg != ins->sreg1)
4822                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4823                         break;
4824                 }
4825                 case OP_TAILCALL: {
4826                         MonoCallInst *call = (MonoCallInst*)ins;
4827                         int i, save_area_offset;
4828
4829                         g_assert (!cfg->method->save_lmf);
4830
4831                         /* Restore callee saved registers */
4832                         save_area_offset = cfg->arch.reg_save_area_offset;
4833                         for (i = 0; i < AMD64_NREG; ++i)
4834                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4835                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4836                                         save_area_offset += 8;
4837                                 }
4838
4839                         if (cfg->arch.omit_fp) {
4840                                 if (cfg->arch.stack_alloc_size)
4841                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4842                                 // FIXME:
4843                                 if (call->stack_usage)
4844                                         NOT_IMPLEMENTED;
4845                         } else {
4846                                 /* Copy arguments on the stack to our argument area */
4847                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4848                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4849                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4850                                 }
4851
4852                                 amd64_leave (code);
4853                         }
4854
4855                         offset = code - cfg->native_code;
4856                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4857                         if (cfg->compile_aot)
4858                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4859                         else
4860                                 amd64_set_reg_template (code, AMD64_R11);
4861                         amd64_jump_reg (code, AMD64_R11);
4862                         ins->flags |= MONO_INST_GC_CALLSITE;
4863                         ins->backend.pc_offset = code - cfg->native_code;
4864                         break;
4865                 }
4866                 case OP_CHECK_THIS:
4867                         /* ensure ins->sreg1 is not NULL */
4868                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4869                         break;
4870                 case OP_ARGLIST: {
4871                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4872                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4873                         break;
4874                 }
4875                 case OP_CALL:
4876                 case OP_FCALL:
4877                 case OP_LCALL:
4878                 case OP_VCALL:
4879                 case OP_VCALL2:
4880                 case OP_VOIDCALL:
4881                         call = (MonoCallInst*)ins;
4882                         /*
4883                          * The AMD64 ABI forces callers to know about varargs.
4884                          */
4885                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4886                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4887                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4888                                 /*
4889                                  * Since the unmanaged calling convention doesn't contain a
4890                                  * 'vararg' entry, we have to treat every pinvoke call as a
4891                                  * potential vararg call.
4892                                  */
4893                                 guint32 nregs, i;
4894                                 nregs = 0;
4895                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4896                                         if (call->used_fregs & (1 << i))
4897                                                 nregs ++;
4898                                 if (!nregs)
4899                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4900                                 else
4901                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4902                         }
4903
4904                         if (ins->flags & MONO_INST_HAS_METHOD)
4905                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4906                         else
4907                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4908                         ins->flags |= MONO_INST_GC_CALLSITE;
4909                         ins->backend.pc_offset = code - cfg->native_code;
4910                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4911                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4912                         code = emit_move_return_value (cfg, ins, code);
4913                         break;
4914                 case OP_FCALL_REG:
4915                 case OP_LCALL_REG:
4916                 case OP_VCALL_REG:
4917                 case OP_VCALL2_REG:
4918                 case OP_VOIDCALL_REG:
4919                 case OP_CALL_REG:
4920                         call = (MonoCallInst*)ins;
4921
4922                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4923                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4924                                 ins->sreg1 = AMD64_R11;
4925                         }
4926
4927                         /*
4928                          * The AMD64 ABI forces callers to know about varargs.
4929                          */
4930                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4931                                 if (ins->sreg1 == AMD64_RAX) {
4932                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4933                                         ins->sreg1 = AMD64_R11;
4934                                 }
4935                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4936                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4937                                 /*
4938                                  * Since the unmanaged calling convention doesn't contain a
4939                                  * 'vararg' entry, we have to treat every pinvoke call as a
4940                                  * potential vararg call.
4941                                  */
4942                                 guint32 nregs, i;
4943                                 nregs = 0;
4944                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4945                                         if (call->used_fregs & (1 << i))
4946                                                 nregs ++;
4947                                 if (ins->sreg1 == AMD64_RAX) {
4948                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4949                                         ins->sreg1 = AMD64_R11;
4950                                 }
4951                                 if (!nregs)
4952                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4953                                 else
4954                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4955                         }
4956
4957                         amd64_call_reg (code, ins->sreg1);
4958                         ins->flags |= MONO_INST_GC_CALLSITE;
4959                         ins->backend.pc_offset = code - cfg->native_code;
4960                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4961                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4962                         code = emit_move_return_value (cfg, ins, code);
4963                         break;
4964                 case OP_FCALL_MEMBASE:
4965                 case OP_LCALL_MEMBASE:
4966                 case OP_VCALL_MEMBASE:
4967                 case OP_VCALL2_MEMBASE:
4968                 case OP_VOIDCALL_MEMBASE:
4969                 case OP_CALL_MEMBASE:
4970                         call = (MonoCallInst*)ins;
4971
4972                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4973                         ins->flags |= MONO_INST_GC_CALLSITE;
4974                         ins->backend.pc_offset = code - cfg->native_code;
4975                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4976                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4977                         code = emit_move_return_value (cfg, ins, code);
4978                         break;
4979                 case OP_DYN_CALL: {
4980                         int i;
4981                         MonoInst *var = cfg->dyn_call_var;
4982
4983                         g_assert (var->opcode == OP_REGOFFSET);
4984
4985                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4986                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4987                         /* r10 = ftn */
4988                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4989
4990                         /* Save args buffer */
4991                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4992
4993                         /* Set argument registers */
4994                         for (i = 0; i < PARAM_REGS; ++i)
4995                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4996
4997                         /* Make the call */
4998                         amd64_call_reg (code, AMD64_R10);
4999
5000                         ins->flags |= MONO_INST_GC_CALLSITE;
5001                         ins->backend.pc_offset = code - cfg->native_code;
5002
5003                         /* Save result */
5004                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
5005                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
5006                         break;
5007                 }
5008                 case OP_AMD64_SAVE_SP_TO_LMF: {
5009                         MonoInst *lmf_var = cfg->lmf_var;
5010                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5011                         break;
5012                 }
5013                 case OP_X86_PUSH:
5014                         g_assert (!cfg->arch.no_pushes);
5015                         amd64_push_reg (code, ins->sreg1);
5016                         break;
5017                 case OP_X86_PUSH_IMM:
5018                         g_assert (!cfg->arch.no_pushes);
5019                         g_assert (amd64_is_imm32 (ins->inst_imm));
5020                         amd64_push_imm (code, ins->inst_imm);
5021                         break;
5022                 case OP_X86_PUSH_MEMBASE:
5023                         g_assert (!cfg->arch.no_pushes);
5024                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5025                         break;
5026                 case OP_X86_PUSH_OBJ: {
5027                         int size = ALIGN_TO (ins->inst_imm, 8);
5028
5029                         g_assert (!cfg->arch.no_pushes);
5030
5031                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5032                         amd64_push_reg (code, AMD64_RDI);
5033                         amd64_push_reg (code, AMD64_RSI);
5034                         amd64_push_reg (code, AMD64_RCX);
5035                         if (ins->inst_offset)
5036                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5037                         else
5038                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5039                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5040                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5041                         amd64_cld (code);
5042                         amd64_prefix (code, X86_REP_PREFIX);
5043                         amd64_movsd (code);
5044                         amd64_pop_reg (code, AMD64_RCX);
5045                         amd64_pop_reg (code, AMD64_RSI);
5046                         amd64_pop_reg (code, AMD64_RDI);
5047                         break;
5048                 }
5049                 case OP_X86_LEA:
5050                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5051                         break;
5052                 case OP_X86_LEA_MEMBASE:
5053                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5054                         break;
5055                 case OP_X86_XCHG:
5056                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5057                         break;
5058                 case OP_LOCALLOC:
5059                         /* keep alignment */
5060                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5061                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5062                         code = mono_emit_stack_alloc (cfg, code, ins);
5063                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5064                         if (cfg->param_area && cfg->arch.no_pushes)
5065                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5066                         break;
5067                 case OP_LOCALLOC_IMM: {
5068                         guint32 size = ins->inst_imm;
5069                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5070
5071                         if (ins->flags & MONO_INST_INIT) {
5072                                 if (size < 64) {
5073                                         int i;
5074
5075                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5076                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5077
5078                                         for (i = 0; i < size; i += 8)
5079                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5080                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5081                                 } else {
5082                                         amd64_mov_reg_imm (code, ins->dreg, size);
5083                                         ins->sreg1 = ins->dreg;
5084
5085                                         code = mono_emit_stack_alloc (cfg, code, ins);
5086                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5087                                 }
5088                         } else {
5089                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5090                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5091                         }
5092                         if (cfg->param_area && cfg->arch.no_pushes)
5093                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5094                         break;
5095                 }
5096                 case OP_THROW: {
5097                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5098                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5099                                              (gpointer)"mono_arch_throw_exception", FALSE);
5100                         ins->flags |= MONO_INST_GC_CALLSITE;
5101                         ins->backend.pc_offset = code - cfg->native_code;
5102                         break;
5103                 }
5104                 case OP_RETHROW: {
5105                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5106                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5107                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5108                         ins->flags |= MONO_INST_GC_CALLSITE;
5109                         ins->backend.pc_offset = code - cfg->native_code;
5110                         break;
5111                 }
5112                 case OP_CALL_HANDLER:
5113                         /* Align stack */
5114                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5115                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5116                         amd64_call_imm (code, 0);
5117                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5118                         /* Restore stack alignment */
5119                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5120                         break;
5121                 case OP_START_HANDLER: {
5122                         /* Even though we're saving RSP, use sizeof */
5123                         /* gpointer because spvar is of type IntPtr */
5124                         /* see: mono_create_spvar_for_region */
5125                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5126                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5127
5128                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5129                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5130                                 cfg->param_area && cfg->arch.no_pushes) {
5131                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5132                         }
5133                         break;
5134                 }
5135                 case OP_ENDFINALLY: {
5136                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5137                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5138                         amd64_ret (code);
5139                         break;
5140                 }
5141                 case OP_ENDFILTER: {
5142                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5143                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5144                         /* The local allocator will put the result into RAX */
5145                         amd64_ret (code);
5146                         break;
5147                 }
5148
5149                 case OP_LABEL:
5150                         ins->inst_c0 = code - cfg->native_code;
5151                         break;
5152                 case OP_BR:
5153                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5154                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5155                         //break;
5156                                 if (ins->inst_target_bb->native_offset) {
5157                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5158                                 } else {
5159                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5160                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5161                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5162                                                 x86_jump8 (code, 0);
5163                                         else
5164                                                 x86_jump32 (code, 0);
5165                         }
5166                         break;
5167                 case OP_BR_REG:
5168                         amd64_jump_reg (code, ins->sreg1);
5169                         break;
5170                 case OP_ICNEQ:
5171                 case OP_ICGE:
5172                 case OP_ICLE:
5173                 case OP_ICGE_UN:
5174                 case OP_ICLE_UN:
5175
5176                 case OP_CEQ:
5177                 case OP_LCEQ:
5178                 case OP_ICEQ:
5179                 case OP_CLT:
5180                 case OP_LCLT:
5181                 case OP_ICLT:
5182                 case OP_CGT:
5183                 case OP_ICGT:
5184                 case OP_LCGT:
5185                 case OP_CLT_UN:
5186                 case OP_LCLT_UN:
5187                 case OP_ICLT_UN:
5188                 case OP_CGT_UN:
5189                 case OP_LCGT_UN:
5190                 case OP_ICGT_UN:
5191                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5192                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5193                         break;
5194                 case OP_COND_EXC_EQ:
5195                 case OP_COND_EXC_NE_UN:
5196                 case OP_COND_EXC_LT:
5197                 case OP_COND_EXC_LT_UN:
5198                 case OP_COND_EXC_GT:
5199                 case OP_COND_EXC_GT_UN:
5200                 case OP_COND_EXC_GE:
5201                 case OP_COND_EXC_GE_UN:
5202                 case OP_COND_EXC_LE:
5203                 case OP_COND_EXC_LE_UN:
5204                 case OP_COND_EXC_IEQ:
5205                 case OP_COND_EXC_INE_UN:
5206                 case OP_COND_EXC_ILT:
5207                 case OP_COND_EXC_ILT_UN:
5208                 case OP_COND_EXC_IGT:
5209                 case OP_COND_EXC_IGT_UN:
5210                 case OP_COND_EXC_IGE:
5211                 case OP_COND_EXC_IGE_UN:
5212                 case OP_COND_EXC_ILE:
5213                 case OP_COND_EXC_ILE_UN:
5214                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5215                         break;
5216                 case OP_COND_EXC_OV:
5217                 case OP_COND_EXC_NO:
5218                 case OP_COND_EXC_C:
5219                 case OP_COND_EXC_NC:
5220                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5221                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5222                         break;
5223                 case OP_COND_EXC_IOV:
5224                 case OP_COND_EXC_INO:
5225                 case OP_COND_EXC_IC:
5226                 case OP_COND_EXC_INC:
5227                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5228                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5229                         break;
5230
5231                 /* floating point opcodes */
5232                 case OP_R8CONST: {
5233                         double d = *(double *)ins->inst_p0;
5234
5235                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5236                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5237                         }
5238                         else {
5239                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5240                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5241                         }
5242                         break;
5243                 }
5244                 case OP_R4CONST: {
5245                         float f = *(float *)ins->inst_p0;
5246
5247                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5248                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5249                         }
5250                         else {
5251                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5252                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5253                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5254                         }
5255                         break;
5256                 }
5257                 case OP_STORER8_MEMBASE_REG:
5258                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5259                         break;
5260                 case OP_LOADR8_MEMBASE:
5261                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5262                         break;
5263                 case OP_STORER4_MEMBASE_REG:
5264                         /* This requires a double->single conversion */
5265                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5266                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5267                         break;
5268                 case OP_LOADR4_MEMBASE:
5269                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5270                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5271                         break;
5272                 case OP_ICONV_TO_R4:
5273                         amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5274                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5275                         break;
5276                 case OP_ICONV_TO_R8:
5277                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5278                         break;
5279                 case OP_LCONV_TO_R4:
5280                         amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5281                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5282                         break;
5283                 case OP_LCONV_TO_R8:
5284                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5285                         break;
5286                 case OP_FCONV_TO_R4:
5287                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5288                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5289                         break;
5290                 case OP_FCONV_TO_I1:
5291                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5292                         break;
5293                 case OP_FCONV_TO_U1:
5294                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5295                         break;
5296                 case OP_FCONV_TO_I2:
5297                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5298                         break;
5299                 case OP_FCONV_TO_U2:
5300                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5301                         break;
5302                 case OP_FCONV_TO_U4:
5303                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5304                         break;
5305                 case OP_FCONV_TO_I4:
5306                 case OP_FCONV_TO_I:
5307                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5308                         break;
5309                 case OP_FCONV_TO_I8:
5310                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5311                         break;
5312                 case OP_LCONV_TO_R_UN: {
5313                         guint8 *br [2];
5314
5315                         /* Based on gcc code */
5316                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5317                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5318
5319                         /* Positive case */
5320                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5321                         br [1] = code; x86_jump8 (code, 0);
5322                         amd64_patch (br [0], code);
5323
5324                         /* Negative case */
5325                         /* Save to the red zone */
5326                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5327                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5328                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5329                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5330                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5331                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5332                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5333                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5334                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5335                         /* Restore */
5336                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5337                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5338                         amd64_patch (br [1], code);
5339                         break;
5340                 }
5341                 case OP_LCONV_TO_OVF_U4:
5342                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5343                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5344                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5345                         break;
5346                 case OP_LCONV_TO_OVF_I4_UN:
5347                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5348                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5349                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5350                         break;
5351                 case OP_FMOVE:
5352                         if (ins->dreg != ins->sreg1)
5353                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5354                         break;
5355                 case OP_FADD:
5356                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5357                         break;
5358                 case OP_FSUB:
5359                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5360                         break;
5361                 case OP_FMUL:
5362                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5363                         break;
5364                 case OP_FDIV:
5365                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5366                         break;
5367                 case OP_FNEG: {
5368                         static double r8_0 = -0.0;
5369
5370                         g_assert (ins->sreg1 == ins->dreg);
5371
5372                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5373                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5374                         break;
5375                 }
5376                 case OP_SIN:
5377                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5378                         break;
5379                 case OP_COS:
5380                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5381                         break;
5382                 case OP_ABS: {
5383                         static guint64 d = 0x7fffffffffffffffUL;
5384
5385                         g_assert (ins->sreg1 == ins->dreg);
5386
5387                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5388                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5389                         break;
5390                 }
5391                 case OP_SQRT:
5392                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5393                         break;
5394                 case OP_IMIN:
5395                         g_assert (cfg->opt & MONO_OPT_CMOV);
5396                         g_assert (ins->dreg == ins->sreg1);
5397                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5398                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5399                         break;
5400                 case OP_IMIN_UN:
5401                         g_assert (cfg->opt & MONO_OPT_CMOV);
5402                         g_assert (ins->dreg == ins->sreg1);
5403                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5404                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5405                         break;
5406                 case OP_IMAX:
5407                         g_assert (cfg->opt & MONO_OPT_CMOV);
5408                         g_assert (ins->dreg == ins->sreg1);
5409                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5410                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5411                         break;
5412                 case OP_IMAX_UN:
5413                         g_assert (cfg->opt & MONO_OPT_CMOV);
5414                         g_assert (ins->dreg == ins->sreg1);
5415                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5416                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5417                         break;
5418                 case OP_LMIN:
5419                         g_assert (cfg->opt & MONO_OPT_CMOV);
5420                         g_assert (ins->dreg == ins->sreg1);
5421                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5422                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5423                         break;
5424                 case OP_LMIN_UN:
5425                         g_assert (cfg->opt & MONO_OPT_CMOV);
5426                         g_assert (ins->dreg == ins->sreg1);
5427                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5428                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5429                         break;
5430                 case OP_LMAX:
5431                         g_assert (cfg->opt & MONO_OPT_CMOV);
5432                         g_assert (ins->dreg == ins->sreg1);
5433                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5434                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5435                         break;
5436                 case OP_LMAX_UN:
5437                         g_assert (cfg->opt & MONO_OPT_CMOV);
5438                         g_assert (ins->dreg == ins->sreg1);
5439                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5440                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5441                         break;
5442                 case OP_X86_FPOP:
5443                         break;
5444                 case OP_FCOMPARE:
5445                         /*
5446                          * The two arguments are swapped because the fbranch instructions
5447                          * depend on this for the non-sse case to work.
5448                          */
5449                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5450                         break;
5451                 case OP_FCNEQ:
5452                 case OP_FCEQ: {
5453                         /* zeroing the register at the start results in
5454                          * shorter and faster code (we can also remove the widening op)
5455                          */
5456                         guchar *unordered_check;
5457                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5458                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5459                         unordered_check = code;
5460                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5461
5462                         if (ins->opcode == OP_FCEQ) {
5463                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5464                                 amd64_patch (unordered_check, code);
5465                         } else {
5466                                 guchar *jump_to_end;
5467                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5468                                 jump_to_end = code;
5469                                 x86_jump8 (code, 0);
5470                                 amd64_patch (unordered_check, code);
5471                                 amd64_inc_reg (code, ins->dreg);
5472                                 amd64_patch (jump_to_end, code);
5473                         }
5474                         break;
5475                 }
5476                 case OP_FCLT:
5477                 case OP_FCLT_UN:
5478                         /* zeroing the register at the start results in
5479                          * shorter and faster code (we can also remove the widening op)
5480                          */
5481                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5482                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5483                         if (ins->opcode == OP_FCLT_UN) {
5484                                 guchar *unordered_check = code;
5485                                 guchar *jump_to_end;
5486                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5487                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5488                                 jump_to_end = code;
5489                                 x86_jump8 (code, 0);
5490                                 amd64_patch (unordered_check, code);
5491                                 amd64_inc_reg (code, ins->dreg);
5492                                 amd64_patch (jump_to_end, code);
5493                         } else {
5494                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5495                         }
5496                         break;
5497                 case OP_FCLE: {
5498                         guchar *unordered_check;
5499                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5500                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5501                         unordered_check = code;
5502                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5503                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5504                         amd64_patch (unordered_check, code);
5505                         break;
5506                 }
5507                 case OP_FCGT:
5508                 case OP_FCGT_UN: {
5509                         /* zeroing the register at the start results in
5510                          * shorter and faster code (we can also remove the widening op)
5511                          */
5512                         guchar *unordered_check;
5513                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5514                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5515                         if (ins->opcode == OP_FCGT) {
5516                                 unordered_check = code;
5517                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5518                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5519                                 amd64_patch (unordered_check, code);
5520                         } else {
5521                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5522                         }
5523                         break;
5524                 }
5525                 case OP_FCGE: {
5526                         guchar *unordered_check;
5527                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5528                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5529                         unordered_check = code;
5530                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5531                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5532                         amd64_patch (unordered_check, code);
5533                         break;
5534                 }
5535
5536                 case OP_FCLT_MEMBASE:
5537                 case OP_FCGT_MEMBASE:
5538                 case OP_FCLT_UN_MEMBASE:
5539                 case OP_FCGT_UN_MEMBASE:
5540                 case OP_FCEQ_MEMBASE: {
5541                         guchar *unordered_check, *jump_to_end;
5542                         int x86_cond;
5543
5544                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5545                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5546
5547                         switch (ins->opcode) {
5548                         case OP_FCEQ_MEMBASE:
5549                                 x86_cond = X86_CC_EQ;
5550                                 break;
5551                         case OP_FCLT_MEMBASE:
5552                         case OP_FCLT_UN_MEMBASE:
5553                                 x86_cond = X86_CC_LT;
5554                                 break;
5555                         case OP_FCGT_MEMBASE:
5556                         case OP_FCGT_UN_MEMBASE:
5557                                 x86_cond = X86_CC_GT;
5558                                 break;
5559                         default:
5560                                 g_assert_not_reached ();
5561                         }
5562
5563                         unordered_check = code;
5564                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5565                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5566
5567                         switch (ins->opcode) {
5568                         case OP_FCEQ_MEMBASE:
5569                         case OP_FCLT_MEMBASE:
5570                         case OP_FCGT_MEMBASE:
5571                                 amd64_patch (unordered_check, code);
5572                                 break;
5573                         case OP_FCLT_UN_MEMBASE:
5574                         case OP_FCGT_UN_MEMBASE:
5575                                 jump_to_end = code;
5576                                 x86_jump8 (code, 0);
5577                                 amd64_patch (unordered_check, code);
5578                                 amd64_inc_reg (code, ins->dreg);
5579                                 amd64_patch (jump_to_end, code);
5580                                 break;
5581                         default:
5582                                 break;
5583                         }
5584                         break;
5585                 }
5586                 case OP_FBEQ: {
5587                         guchar *jump = code;
5588                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5589                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5590                         amd64_patch (jump, code);
5591                         break;
5592                 }
5593                 case OP_FBNE_UN:
5594                         /* Branch if C013 != 100 */
5595                         /* branch if !ZF or (PF|CF) */
5596                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5597                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5598                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5599                         break;
5600                 case OP_FBLT:
5601                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5602                         break;
5603                 case OP_FBLT_UN:
5604                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5605                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5606                         break;
5607                 case OP_FBGT:
5608                 case OP_FBGT_UN:
5609                         if (ins->opcode == OP_FBGT) {
5610                                 guchar *br1;
5611
5612                                 /* skip branch if C1=1 */
5613                                 br1 = code;
5614                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5615                                 /* branch if (C0 | C3) = 1 */
5616                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5617                                 amd64_patch (br1, code);
5618                                 break;
5619                         } else {
5620                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5621                         }
5622                         break;
5623                 case OP_FBGE: {
5624                         /* Branch if C013 == 100 or 001 */
5625                         guchar *br1;
5626
5627                         /* skip branch if C1=1 */
5628                         br1 = code;
5629                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5630                         /* branch if (C0 | C3) = 1 */
5631                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5632                         amd64_patch (br1, code);
5633                         break;
5634                 }
5635                 case OP_FBGE_UN:
5636                         /* Branch if C013 == 000 */
5637                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5638                         break;
5639                 case OP_FBLE: {
5640                         /* Branch if C013=000 or 100 */
5641                         guchar *br1;
5642
5643                         /* skip branch if C1=1 */
5644                         br1 = code;
5645                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5646                         /* branch if C0=0 */
5647                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5648                         amd64_patch (br1, code);
5649                         break;
5650                 }
5651                 case OP_FBLE_UN:
5652                         /* Branch if C013 != 001 */
5653                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5654                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5655                         break;
5656                 case OP_CKFINITE:
5657                         /* Transfer value to the fp stack */
5658                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5659                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5660                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5661
5662                         amd64_push_reg (code, AMD64_RAX);
5663                         amd64_fxam (code);
5664                         amd64_fnstsw (code);
5665                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5666                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5667                         amd64_pop_reg (code, AMD64_RAX);
5668                         amd64_fstp (code, 0);
5669                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5670                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5671                         break;
5672                 case OP_TLS_GET: {
5673                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5674                         break;
5675                 }
5676                 case OP_TLS_GET_REG:
5677                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5678                         break;
5679                 case OP_TLS_SET: {
5680                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5681                         break;
5682                 }
5683                 case OP_TLS_SET_REG: {
5684                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5685                         break;
5686                 }
5687                 case OP_MEMORY_BARRIER: {
5688                         switch (ins->backend.memory_barrier_kind) {
5689                         case StoreLoadBarrier:
5690                         case FullBarrier:
5691                                 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5692                                 x86_prefix (code, X86_LOCK_PREFIX);
5693                                 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5694                                 break;
5695                         }
5696                         break;
5697                 }
5698                 case OP_ATOMIC_ADD_I4:
5699                 case OP_ATOMIC_ADD_I8: {
5700                         int dreg = ins->dreg;
5701                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5702
5703                         if (dreg == ins->inst_basereg)
5704                                 dreg = AMD64_R11;
5705
5706                         if (dreg != ins->sreg2)
5707                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
5708
5709                         x86_prefix (code, X86_LOCK_PREFIX);
5710                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5711
5712                         if (dreg != ins->dreg)
5713                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5714
5715                         break;
5716                 }
5717                 case OP_ATOMIC_ADD_NEW_I4:
5718                 case OP_ATOMIC_ADD_NEW_I8: {
5719                         int dreg = ins->dreg;
5720                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
5721
5722                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5723                                 dreg = AMD64_R11;
5724
5725                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5726                         amd64_prefix (code, X86_LOCK_PREFIX);
5727                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5728                         /* dreg contains the old value, add with sreg2 value */
5729                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5730
5731                         if (ins->dreg != dreg)
5732                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5733
5734                         break;
5735                 }
5736                 case OP_ATOMIC_EXCHANGE_I4:
5737                 case OP_ATOMIC_EXCHANGE_I8: {
5738                         guchar *br[2];
5739                         int sreg2 = ins->sreg2;
5740                         int breg = ins->inst_basereg;
5741                         guint32 size;
5742                         gboolean need_push = FALSE, rdx_pushed = FALSE;
5743
5744                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5745                                 size = 8;
5746                         else
5747                                 size = 4;
5748
5749                         /*
5750                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5751                          * an explanation of how this works.
5752                          */
5753
5754                         /* cmpxchg uses eax as comperand, need to make sure we can use it
5755                          * hack to overcome limits in x86 reg allocator
5756                          * (req: dreg == eax and sreg2 != eax and breg != eax)
5757                          */
5758                         g_assert (ins->dreg == AMD64_RAX);
5759
5760                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5761                                 /* Highly unlikely, but possible */
5762                                 need_push = TRUE;
5763
5764                         /* The pushes invalidate rsp */
5765                         if ((breg == AMD64_RAX) || need_push) {
5766                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5767                                 breg = AMD64_R11;
5768                         }
5769
5770                         /* We need the EAX reg for the comparand */
5771                         if (ins->sreg2 == AMD64_RAX) {
5772                                 if (breg != AMD64_R11) {
5773                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5774                                         sreg2 = AMD64_R11;
5775                                 } else {
5776                                         g_assert (need_push);
5777                                         amd64_push_reg (code, AMD64_RDX);
5778                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5779                                         sreg2 = AMD64_RDX;
5780                                         rdx_pushed = TRUE;
5781                                 }
5782                         }
5783
5784                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5785
5786                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5787                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5788                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5789                         amd64_patch (br [1], br [0]);
5790
5791                         if (rdx_pushed)
5792                                 amd64_pop_reg (code, AMD64_RDX);
5793
5794                         break;
5795                 }
5796                 case OP_ATOMIC_CAS_I4:
5797                 case OP_ATOMIC_CAS_I8: {
5798                         guint32 size;
5799
5800                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5801                                 size = 8;
5802                         else
5803                                 size = 4;
5804
5805                         /*
5806                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5807                          * an explanation of how this works.
5808                          */
5809                         g_assert (ins->sreg3 == AMD64_RAX);
5810                         g_assert (ins->sreg1 != AMD64_RAX);
5811                         g_assert (ins->sreg1 != ins->sreg2);
5812
5813                         amd64_prefix (code, X86_LOCK_PREFIX);
5814                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5815
5816                         if (ins->dreg != AMD64_RAX)
5817                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5818                         break;
5819                 }
5820                 case OP_CARD_TABLE_WBARRIER: {
5821                         int ptr = ins->sreg1;
5822                         int value = ins->sreg2;
5823                         guchar *br = 0;
5824                         int nursery_shift, card_table_shift;
5825                         gpointer card_table_mask;
5826                         size_t nursery_size;
5827
5828                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5829                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5830                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5831
5832                         /*If either point to the stack we can simply avoid the WB. This happens due to
5833                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5834                          */
5835                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5836                                 continue;
5837
5838                         /*
5839                          * We need one register we can clobber, we choose EDX and make sreg1
5840                          * fixed EAX to work around limitations in the local register allocator.
5841                          * sreg2 might get allocated to EDX, but that is not a problem since
5842                          * we use it before clobbering EDX.
5843                          */
5844                         g_assert (ins->sreg1 == AMD64_RAX);
5845
5846                         /*
5847                          * This is the code we produce:
5848                          *
5849                          *   edx = value
5850                          *   edx >>= nursery_shift
5851                          *   cmp edx, (nursery_start >> nursery_shift)
5852                          *   jne done
5853                          *   edx = ptr
5854                          *   edx >>= card_table_shift
5855                          *   edx += cardtable
5856                          *   [edx] = 1
5857                          * done:
5858                          */
5859
5860                         if (mono_gc_card_table_nursery_check ()) {
5861                                 if (value != AMD64_RDX)
5862                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5863                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5864                                 if (shifted_nursery_start >> 31) {
5865                                         /*
5866                                          * The value we need to compare against is 64 bits, so we need
5867                                          * another spare register.  We use RBX, which we save and
5868                                          * restore.
5869                                          */
5870                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5871                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5872                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5873                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5874                                 } else {
5875                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5876                                 }
5877                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5878                         }
5879                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5880                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5881                         if (card_table_mask)
5882                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5883
5884                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5885                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5886
5887                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5888
5889                         if (mono_gc_card_table_nursery_check ())
5890                                 x86_patch (br, code);
5891                         break;
5892                 }
5893 #ifdef MONO_ARCH_SIMD_INTRINSICS
5894                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5895                 case OP_ADDPS:
5896                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5897                         break;
5898                 case OP_DIVPS:
5899                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5900                         break;
5901                 case OP_MULPS:
5902                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5903                         break;
5904                 case OP_SUBPS:
5905                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5906                         break;
5907                 case OP_MAXPS:
5908                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5909                         break;
5910                 case OP_MINPS:
5911                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5912                         break;
5913                 case OP_COMPPS:
5914                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5915                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5916                         break;
5917                 case OP_ANDPS:
5918                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5919                         break;
5920                 case OP_ANDNPS:
5921                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5922                         break;
5923                 case OP_ORPS:
5924                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5925                         break;
5926                 case OP_XORPS:
5927                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5928                         break;
5929                 case OP_SQRTPS:
5930                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5931                         break;
5932                 case OP_RSQRTPS:
5933                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5934                         break;
5935                 case OP_RCPPS:
5936                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5937                         break;
5938                 case OP_ADDSUBPS:
5939                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5940                         break;
5941                 case OP_HADDPS:
5942                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5943                         break;
5944                 case OP_HSUBPS:
5945                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5946                         break;
5947                 case OP_DUPPS_HIGH:
5948                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5949                         break;
5950                 case OP_DUPPS_LOW:
5951                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5952                         break;
5953
5954                 case OP_PSHUFLEW_HIGH:
5955                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5956                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5957                         break;
5958                 case OP_PSHUFLEW_LOW:
5959                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5960                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5961                         break;
5962                 case OP_PSHUFLED:
5963                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5964                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5965                         break;
5966                 case OP_SHUFPS:
5967                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5968                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5969                         break;
5970                 case OP_SHUFPD:
5971                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5972                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5973                         break;
5974
5975                 case OP_ADDPD:
5976                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978                 case OP_DIVPD:
5979                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5980                         break;
5981                 case OP_MULPD:
5982                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5983                         break;
5984                 case OP_SUBPD:
5985                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5986                         break;
5987                 case OP_MAXPD:
5988                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5989                         break;
5990                 case OP_MINPD:
5991                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5992                         break;
5993                 case OP_COMPPD:
5994                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5995                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5996                         break;
5997                 case OP_ANDPD:
5998                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5999                         break;
6000                 case OP_ANDNPD:
6001                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6002                         break;
6003                 case OP_ORPD:
6004                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6005                         break;
6006                 case OP_XORPD:
6007                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6008                         break;
6009                 case OP_SQRTPD:
6010                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6011                         break;
6012                 case OP_ADDSUBPD:
6013                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6014                         break;
6015                 case OP_HADDPD:
6016                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6017                         break;
6018                 case OP_HSUBPD:
6019                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6020                         break;
6021                 case OP_DUPPD:
6022                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6023                         break;
6024
6025                 case OP_EXTRACT_MASK:
6026                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6027                         break;
6028
6029                 case OP_PAND:
6030                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6031                         break;
6032                 case OP_POR:
6033                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6034                         break;
6035                 case OP_PXOR:
6036                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6037                         break;
6038
6039                 case OP_PADDB:
6040                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6041                         break;
6042                 case OP_PADDW:
6043                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6044                         break;
6045                 case OP_PADDD:
6046                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6047                         break;
6048                 case OP_PADDQ:
6049                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051
6052                 case OP_PSUBB:
6053                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6054                         break;
6055                 case OP_PSUBW:
6056                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6057                         break;
6058                 case OP_PSUBD:
6059                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6060                         break;
6061                 case OP_PSUBQ:
6062                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6063                         break;
6064
6065                 case OP_PMAXB_UN:
6066                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6067                         break;
6068                 case OP_PMAXW_UN:
6069                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6070                         break;
6071                 case OP_PMAXD_UN:
6072                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6073                         break;
6074
6075                 case OP_PMAXB:
6076                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6077                         break;
6078                 case OP_PMAXW:
6079                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6080                         break;
6081                 case OP_PMAXD:
6082                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6083                         break;
6084
6085                 case OP_PAVGB_UN:
6086                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6087                         break;
6088                 case OP_PAVGW_UN:
6089                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6090                         break;
6091
6092                 case OP_PMINB_UN:
6093                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095                 case OP_PMINW_UN:
6096                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6097                         break;
6098                 case OP_PMIND_UN:
6099                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6100                         break;
6101
6102                 case OP_PMINB:
6103                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105                 case OP_PMINW:
6106                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108                 case OP_PMIND:
6109                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6110                         break;
6111
6112                 case OP_PCMPEQB:
6113                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_PCMPEQW:
6116                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118                 case OP_PCMPEQD:
6119                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6120                         break;
6121                 case OP_PCMPEQQ:
6122                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6123                         break;
6124
6125                 case OP_PCMPGTB:
6126                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6127                         break;
6128                 case OP_PCMPGTW:
6129                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6130                         break;
6131                 case OP_PCMPGTD:
6132                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6133                         break;
6134                 case OP_PCMPGTQ:
6135                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6136                         break;
6137
6138                 case OP_PSUM_ABS_DIFF:
6139                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6140                         break;
6141
6142                 case OP_UNPACK_LOWB:
6143                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6144                         break;
6145                 case OP_UNPACK_LOWW:
6146                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148                 case OP_UNPACK_LOWD:
6149                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6150                         break;
6151                 case OP_UNPACK_LOWQ:
6152                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6153                         break;
6154                 case OP_UNPACK_LOWPS:
6155                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6156                         break;
6157                 case OP_UNPACK_LOWPD:
6158                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6159                         break;
6160
6161                 case OP_UNPACK_HIGHB:
6162                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6163                         break;
6164                 case OP_UNPACK_HIGHW:
6165                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6166                         break;
6167                 case OP_UNPACK_HIGHD:
6168                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6169                         break;
6170                 case OP_UNPACK_HIGHQ:
6171                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6172                         break;
6173                 case OP_UNPACK_HIGHPS:
6174                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6175                         break;
6176                 case OP_UNPACK_HIGHPD:
6177                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6178                         break;
6179
6180                 case OP_PACKW:
6181                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6182                         break;
6183                 case OP_PACKD:
6184                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6185                         break;
6186                 case OP_PACKW_UN:
6187                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6188                         break;
6189                 case OP_PACKD_UN:
6190                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6191                         break;
6192
6193                 case OP_PADDB_SAT_UN:
6194                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6195                         break;
6196                 case OP_PSUBB_SAT_UN:
6197                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6198                         break;
6199                 case OP_PADDW_SAT_UN:
6200                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6201                         break;
6202                 case OP_PSUBW_SAT_UN:
6203                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6204                         break;
6205
6206                 case OP_PADDB_SAT:
6207                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6208                         break;
6209                 case OP_PSUBB_SAT:
6210                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6211                         break;
6212                 case OP_PADDW_SAT:
6213                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6214                         break;
6215                 case OP_PSUBW_SAT:
6216                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6217                         break;
6218
6219                 case OP_PMULW:
6220                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6221                         break;
6222                 case OP_PMULD:
6223                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6224                         break;
6225                 case OP_PMULQ:
6226                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6227                         break;
6228                 case OP_PMULW_HIGH_UN:
6229                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6230                         break;
6231                 case OP_PMULW_HIGH:
6232                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6233                         break;
6234
6235                 case OP_PSHRW:
6236                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6237                         break;
6238                 case OP_PSHRW_REG:
6239                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6240                         break;
6241
6242                 case OP_PSARW:
6243                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6244                         break;
6245                 case OP_PSARW_REG:
6246                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6247                         break;
6248
6249                 case OP_PSHLW:
6250                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6251                         break;
6252                 case OP_PSHLW_REG:
6253                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6254                         break;
6255
6256                 case OP_PSHRD:
6257                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6258                         break;
6259                 case OP_PSHRD_REG:
6260                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6261                         break;
6262
6263                 case OP_PSARD:
6264                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6265                         break;
6266                 case OP_PSARD_REG:
6267                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6268                         break;
6269
6270                 case OP_PSHLD:
6271                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6272                         break;
6273                 case OP_PSHLD_REG:
6274                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6275                         break;
6276
6277                 case OP_PSHRQ:
6278                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6279                         break;
6280                 case OP_PSHRQ_REG:
6281                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6282                         break;
6283
6284                 /*TODO: This is appart of the sse spec but not added
6285                 case OP_PSARQ:
6286                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6287                         break;
6288                 case OP_PSARQ_REG:
6289                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6290                         break;
6291                 */
6292
6293                 case OP_PSHLQ:
6294                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6295                         break;
6296                 case OP_PSHLQ_REG:
6297                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6298                         break;
6299                 case OP_CVTDQ2PD:
6300                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6301                         break;
6302                 case OP_CVTDQ2PS:
6303                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6304                         break;
6305                 case OP_CVTPD2DQ:
6306                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6307                         break;
6308                 case OP_CVTPD2PS:
6309                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6310                         break;
6311                 case OP_CVTPS2DQ:
6312                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6313                         break;
6314                 case OP_CVTPS2PD:
6315                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6316                         break;
6317                 case OP_CVTTPD2DQ:
6318                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6319                         break;
6320                 case OP_CVTTPS2DQ:
6321                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6322                         break;
6323
6324                 case OP_ICONV_TO_X:
6325                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6326                         break;
6327                 case OP_EXTRACT_I4:
6328                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6329                         break;
6330                 case OP_EXTRACT_I8:
6331                         if (ins->inst_c0) {
6332                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6333                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6334                         } else {
6335                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6336                         }
6337                         break;
6338                 case OP_EXTRACT_I1:
6339                 case OP_EXTRACT_U1:
6340                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6341                         if (ins->inst_c0)
6342                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6343                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6344                         break;
6345                 case OP_EXTRACT_I2:
6346                 case OP_EXTRACT_U2:
6347                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6348                         if (ins->inst_c0)
6349                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6350                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6351                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6352                         break;
6353                 case OP_EXTRACT_R8:
6354                         if (ins->inst_c0)
6355                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6356                         else
6357                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6358                         break;
6359                 case OP_INSERT_I2:
6360                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6361                         break;
6362                 case OP_EXTRACTX_U2:
6363                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6364                         break;
6365                 case OP_INSERTX_U1_SLOW:
6366                         /*sreg1 is the extracted ireg (scratch)
6367                         /sreg2 is the to be inserted ireg (scratch)
6368                         /dreg is the xreg to receive the value*/
6369
6370                         /*clear the bits from the extracted word*/
6371                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6372                         /*shift the value to insert if needed*/
6373                         if (ins->inst_c0 & 1)
6374                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6375                         /*join them together*/
6376                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6377                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6378                         break;
6379                 case OP_INSERTX_I4_SLOW:
6380                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6381                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6382                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6383                         break;
6384                 case OP_INSERTX_I8_SLOW:
6385                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6386                         if (ins->inst_c0)
6387                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6388                         else
6389                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6390                         break;
6391
6392                 case OP_INSERTX_R4_SLOW:
6393                         switch (ins->inst_c0) {
6394                         case 0:
6395                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6396                                 break;
6397                         case 1:
6398                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6399                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6400                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6401                                 break;
6402                         case 2:
6403                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6404                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6405                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6406                                 break;
6407                         case 3:
6408                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6409                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6410                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6411                                 break;
6412                         }
6413                         break;
6414                 case OP_INSERTX_R8_SLOW:
6415                         if (ins->inst_c0)
6416                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6417                         else
6418                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6419                         break;
6420                 case OP_STOREX_MEMBASE_REG:
6421                 case OP_STOREX_MEMBASE:
6422                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6423                         break;
6424                 case OP_LOADX_MEMBASE:
6425                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6426                         break;
6427                 case OP_LOADX_ALIGNED_MEMBASE:
6428                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6429                         break;
6430                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6431                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6432                         break;
6433                 case OP_STOREX_NTA_MEMBASE_REG:
6434                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6435                         break;
6436                 case OP_PREFETCH_MEMBASE:
6437                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6438                         break;
6439
6440                 case OP_XMOVE:
6441                         /*FIXME the peephole pass should have killed this*/
6442                         if (ins->dreg != ins->sreg1)
6443                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6444                         break;
6445                 case OP_XZERO:
6446                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6447                         break;
6448                 case OP_ICONV_TO_R8_RAW:
6449                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6450                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6451                         break;
6452
6453                 case OP_FCONV_TO_R8_X:
6454                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6455                         break;
6456
6457                 case OP_XCONV_R8_TO_I4:
6458                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6459                         switch (ins->backend.source_opcode) {
6460                         case OP_FCONV_TO_I1:
6461                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6462                                 break;
6463                         case OP_FCONV_TO_U1:
6464                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6465                                 break;
6466                         case OP_FCONV_TO_I2:
6467                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6468                                 break;
6469                         case OP_FCONV_TO_U2:
6470                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6471                                 break;
6472                         }
6473                         break;
6474
6475                 case OP_EXPAND_I2:
6476                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6477                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6478                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6479                         break;
6480                 case OP_EXPAND_I4:
6481                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6482                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6483                         break;
6484                 case OP_EXPAND_I8:
6485                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6486                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6487                         break;
6488                 case OP_EXPAND_R4:
6489                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6490                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6491                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6492                         break;
6493                 case OP_EXPAND_R8:
6494                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6495                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6496                         break;
6497 #endif
6498                 case OP_LIVERANGE_START: {
6499                         if (cfg->verbose_level > 1)
6500                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6501                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6502                         break;
6503                 }
6504                 case OP_LIVERANGE_END: {
6505                         if (cfg->verbose_level > 1)
6506                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6507                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6508                         break;
6509                 }
6510                 case OP_NACL_GC_SAFE_POINT: {
6511 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6512                         if (cfg->compile_aot)
6513                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6514                         else {
6515                                 guint8 *br [1];
6516
6517                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6518                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6519                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6520                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6521                                 amd64_patch (br[0], code);
6522                         }
6523 #endif
6524                         break;
6525                 }
6526                 case OP_GC_LIVENESS_DEF:
6527                 case OP_GC_LIVENESS_USE:
6528                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6529                         ins->backend.pc_offset = code - cfg->native_code;
6530                         break;
6531                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6532                         ins->backend.pc_offset = code - cfg->native_code;
6533                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6534                         break;
6535                 default:
6536                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6537                         g_assert_not_reached ();
6538                 }
6539
6540                 if ((code - cfg->native_code - offset) > max_len) {
6541 #if !defined(__native_client_codegen__)
6542                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6543                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6544                         g_assert_not_reached ();
6545 #endif
6546                 }
6547
6548                 last_ins = ins;
6549                 last_offset = offset;
6550         }
6551
6552         cfg->code_len = code - cfg->native_code;
6553 }
6554
6555 #endif /* DISABLE_JIT */
6556
6557 void
6558 mono_arch_register_lowlevel_calls (void)
6559 {
6560         /* The signature doesn't matter */
6561         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6562 }
6563
6564 void
6565 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6566 {
6567         MonoJumpInfo *patch_info;
6568         gboolean compile_aot = !run_cctors;
6569
6570         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6571                 unsigned char *ip = patch_info->ip.i + code;
6572                 unsigned char *target;
6573
6574                 if (compile_aot) {
6575                         switch (patch_info->type) {
6576                         case MONO_PATCH_INFO_BB:
6577                         case MONO_PATCH_INFO_LABEL:
6578                                 break;
6579                         default:
6580                                 /* No need to patch these */
6581                                 continue;
6582                         }
6583                 }
6584
6585                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6586
6587                 switch (patch_info->type) {
6588                 case MONO_PATCH_INFO_NONE:
6589                         continue;
6590                 case MONO_PATCH_INFO_METHOD_REL:
6591                 case MONO_PATCH_INFO_R8:
6592                 case MONO_PATCH_INFO_R4:
6593                         g_assert_not_reached ();
6594                         continue;
6595                 case MONO_PATCH_INFO_BB:
6596                         break;
6597                 default:
6598                         break;
6599                 }
6600
6601                 /*
6602                  * Debug code to help track down problems where the target of a near call is
6603                  * is not valid.
6604                  */
6605                 if (amd64_is_near_call (ip)) {
6606                         gint64 disp = (guint8*)target - (guint8*)ip;
6607
6608                         if (!amd64_is_imm32 (disp)) {
6609                                 printf ("TYPE: %d\n", patch_info->type);
6610                                 switch (patch_info->type) {
6611                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6612                                         printf ("V: %s\n", patch_info->data.name);
6613                                         break;
6614                                 case MONO_PATCH_INFO_METHOD_JUMP:
6615                                 case MONO_PATCH_INFO_METHOD:
6616                                         printf ("V: %s\n", patch_info->data.method->name);
6617                                         break;
6618                                 default:
6619                                         break;
6620                                 }
6621                         }
6622                 }
6623
6624                 amd64_patch (ip, (gpointer)target);
6625         }
6626 }
6627
6628 #ifndef DISABLE_JIT
6629
6630 static int
6631 get_max_epilog_size (MonoCompile *cfg)
6632 {
6633         int max_epilog_size = 16;
6634
6635         if (cfg->method->save_lmf)
6636                 max_epilog_size += 256;
6637
6638         if (mono_jit_trace_calls != NULL)
6639                 max_epilog_size += 50;
6640
6641         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6642                 max_epilog_size += 50;
6643
6644         max_epilog_size += (AMD64_NREG * 2);
6645
6646         return max_epilog_size;
6647 }
6648
6649 /*
6650  * This macro is used for testing whenever the unwinder works correctly at every point
6651  * where an async exception can happen.
6652  */
6653 /* This will generate a SIGSEGV at the given point in the code */
6654 #define async_exc_point(code) do { \
6655     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6656          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6657              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6658          cfg->arch.async_point_count ++; \
6659     } \
6660 } while (0)
6661
6662 guint8 *
6663 mono_arch_emit_prolog (MonoCompile *cfg)
6664 {
6665         MonoMethod *method = cfg->method;
6666         MonoBasicBlock *bb;
6667         MonoMethodSignature *sig;
6668         MonoInst *ins;
6669         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
6670         guint8 *code;
6671         CallInfo *cinfo;
6672         MonoInst *lmf_var = cfg->lmf_var;
6673         gboolean args_clobbered = FALSE;
6674         gboolean trace = FALSE;
6675 #ifdef __native_client_codegen__
6676         guint alignment_check;
6677 #endif
6678
6679         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
6680
6681 #if defined(__default_codegen__)
6682         code = cfg->native_code = g_malloc (cfg->code_size);
6683 #elif defined(__native_client_codegen__)
6684         /* native_code_alloc is not 32-byte aligned, native_code is. */
6685         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6686
6687         /* Align native_code to next nearest kNaclAlignment byte. */
6688         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6689         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6690
6691         code = cfg->native_code;
6692
6693         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6694         g_assert (alignment_check == 0);
6695 #endif
6696
6697         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6698                 trace = TRUE;
6699
6700         /* Amount of stack space allocated by register saving code */
6701         pos = 0;
6702
6703         /* Offset between RSP and the CFA */
6704         cfa_offset = 0;
6705
6706         /*
6707          * The prolog consists of the following parts:
6708          * FP present:
6709          * - push rbp, mov rbp, rsp
6710          * - save callee saved regs using pushes
6711          * - allocate frame
6712          * - save rgctx if needed
6713          * - save lmf if needed
6714          * FP not present:
6715          * - allocate frame
6716          * - save rgctx if needed
6717          * - save lmf if needed
6718          * - save callee saved regs using moves
6719          */
6720
6721         // CFA = sp + 8
6722         cfa_offset = 8;
6723         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6724         // IP saved at CFA - 8
6725         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6726         async_exc_point (code);
6727         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6728
6729         if (!cfg->arch.omit_fp) {
6730                 amd64_push_reg (code, AMD64_RBP);
6731                 cfa_offset += 8;
6732                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6733                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6734                 async_exc_point (code);
6735 #ifdef HOST_WIN32
6736                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6737 #endif
6738                 /* These are handled automatically by the stack marking code */
6739                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6740
6741                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6742                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6743                 async_exc_point (code);
6744 #ifdef HOST_WIN32
6745                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6746 #endif
6747         }
6748
6749         /* The param area is always at offset 0 from sp */
6750         /* This needs to be allocated here, since it has to come after the spill area */
6751         if (cfg->arch.no_pushes && cfg->param_area) {
6752                 if (cfg->arch.omit_fp)
6753                         // FIXME:
6754                         g_assert_not_reached ();
6755                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6756         }
6757
6758         if (cfg->arch.omit_fp) {
6759                 /*
6760                  * On enter, the stack is misaligned by the pushing of the return
6761                  * address. It is either made aligned by the pushing of %rbp, or by
6762                  * this.
6763                  */
6764                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6765                 if ((alloc_size % 16) == 0) {
6766                         alloc_size += 8;
6767                         /* Mark the padding slot as NOREF */
6768                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6769                 }
6770         } else {
6771                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6772                 if (cfg->stack_offset != alloc_size) {
6773                         /* Mark the padding slot as NOREF */
6774                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6775                 }
6776                 cfg->arch.sp_fp_offset = alloc_size;
6777                 alloc_size -= pos;
6778         }
6779
6780         cfg->arch.stack_alloc_size = alloc_size;
6781
6782         /* Allocate stack frame */
6783         if (alloc_size) {
6784                 /* See mono_emit_stack_alloc */
6785 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6786                 guint32 remaining_size = alloc_size;
6787                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6788                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6789                 guint32 offset = code - cfg->native_code;
6790                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6791                         while (required_code_size >= (cfg->code_size - offset))
6792                                 cfg->code_size *= 2;
6793                         cfg->native_code = mono_realloc_native_code (cfg);
6794                         code = cfg->native_code + offset;
6795                         cfg->stat_code_reallocs++;
6796                 }
6797
6798                 while (remaining_size >= 0x1000) {
6799                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6800                         if (cfg->arch.omit_fp) {
6801                                 cfa_offset += 0x1000;
6802                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6803                         }
6804                         async_exc_point (code);
6805 #ifdef HOST_WIN32
6806                         if (cfg->arch.omit_fp)
6807                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6808 #endif
6809
6810                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6811                         remaining_size -= 0x1000;
6812                 }
6813                 if (remaining_size) {
6814                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6815                         if (cfg->arch.omit_fp) {
6816                                 cfa_offset += remaining_size;
6817                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6818                                 async_exc_point (code);
6819                         }
6820 #ifdef HOST_WIN32
6821                         if (cfg->arch.omit_fp)
6822                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6823 #endif
6824                 }
6825 #else
6826                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6827                 if (cfg->arch.omit_fp) {
6828                         cfa_offset += alloc_size;
6829                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6830                         async_exc_point (code);
6831                 }
6832 #endif
6833         }
6834
6835         /* Stack alignment check */
6836 #if 0
6837         {
6838                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6839                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6840                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6841                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6842                 amd64_breakpoint (code);
6843         }
6844 #endif
6845
6846 #ifndef TARGET_WIN32
6847         if (mini_get_debug_options ()->init_stacks) {
6848                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6849
6850                 /* Save registers to the red zone */
6851                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6852                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6853
6854                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6855                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6856                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6857
6858                 amd64_cld (code);
6859 #if defined(__default_codegen__)
6860                 amd64_prefix (code, X86_REP_PREFIX);
6861                 amd64_stosl (code);
6862 #elif defined(__native_client_codegen__)
6863                 /* NaCl stos pseudo-instruction */
6864                 amd64_codegen_pre (code);
6865                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6866                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6867                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6868                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6869                 amd64_prefix (code, X86_REP_PREFIX);
6870                 amd64_stosl (code);
6871                 amd64_codegen_post (code);
6872 #endif /* __native_client_codegen__ */
6873
6874                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6875                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6876         }
6877 #endif
6878
6879         /* Save LMF */
6880         if (method->save_lmf) {
6881                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6882         }
6883
6884         /* Save callee saved registers */
6885         if (!method->save_lmf) {
6886                 gint32 save_area_offset;
6887
6888                 if (cfg->arch.omit_fp) {
6889                         save_area_offset = cfg->arch.reg_save_area_offset;
6890                         /* Save caller saved registers after sp is adjusted */
6891                         /* The registers are saved at the bottom of the frame */
6892                         /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6893                 } else {
6894                         /* The registers are saved just below the saved rbp */
6895                         save_area_offset = cfg->arch.reg_save_area_offset;
6896                 }
6897
6898                 for (i = 0; i < AMD64_NREG; ++i)
6899                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6900                                 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6901
6902                                 if (cfg->arch.omit_fp) {
6903                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6904                                         /* These are handled automatically by the stack marking code */
6905                                         mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6906                                 } else {
6907                                         mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6908                                         // FIXME: GC
6909                                 }
6910
6911                                 save_area_offset += 8;
6912                                 async_exc_point (code);
6913                         }
6914         }
6915
6916         /* store runtime generic context */
6917         if (cfg->rgctx_var) {
6918                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6919                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6920
6921                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6922
6923                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6924                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6925         }
6926
6927         /* compute max_length in order to use short forward jumps */
6928         max_epilog_size = get_max_epilog_size (cfg);
6929         if (cfg->opt & MONO_OPT_BRANCH) {
6930                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6931                         MonoInst *ins;
6932                         int max_length = 0;
6933
6934                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6935                                 max_length += 6;
6936                         /* max alignment for loops */
6937                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6938                                 max_length += LOOP_ALIGNMENT;
6939 #ifdef __native_client_codegen__
6940                         /* max alignment for native client */
6941                         max_length += kNaClAlignment;
6942 #endif
6943
6944                         MONO_BB_FOR_EACH_INS (bb, ins) {
6945 #ifdef __native_client_codegen__
6946                                 {
6947                                         int space_in_block = kNaClAlignment -
6948                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6949                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6950                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6951                                                 max_length += space_in_block;
6952                                         }
6953                                 }
6954 #endif  /*__native_client_codegen__*/
6955                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6956                         }
6957
6958                         /* Take prolog and epilog instrumentation into account */
6959                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6960                                 max_length += max_epilog_size;
6961
6962                         bb->max_length = max_length;
6963                 }
6964         }
6965
6966         sig = mono_method_signature (method);
6967         pos = 0;
6968
6969         cinfo = cfg->arch.cinfo;
6970
6971         if (sig->ret->type != MONO_TYPE_VOID) {
6972                 /* Save volatile arguments to the stack */
6973                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6974                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6975         }
6976
6977         /* Keep this in sync with emit_load_volatile_arguments */
6978         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6979                 ArgInfo *ainfo = cinfo->args + i;
6980                 gint32 stack_offset;
6981                 MonoType *arg_type;
6982
6983                 ins = cfg->args [i];
6984
6985                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6986                         /* Unused arguments */
6987                         continue;
6988
6989                 if (sig->hasthis && (i == 0))
6990                         arg_type = &mono_defaults.object_class->byval_arg;
6991                 else
6992                         arg_type = sig->params [i - sig->hasthis];
6993
6994                 stack_offset = ainfo->offset + ARGS_OFFSET;
6995
6996                 if (cfg->globalra) {
6997                         /* All the other moves are done by the register allocator */
6998                         switch (ainfo->storage) {
6999                         case ArgInFloatSSEReg:
7000                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
7001                                 break;
7002                         case ArgValuetypeInReg:
7003                                 for (quad = 0; quad < 2; quad ++) {
7004                                         switch (ainfo->pair_storage [quad]) {
7005                                         case ArgInIReg:
7006                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7007                                                 break;
7008                                         case ArgInFloatSSEReg:
7009                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7010                                                 break;
7011                                         case ArgInDoubleSSEReg:
7012                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7013                                                 break;
7014                                         case ArgNone:
7015                                                 break;
7016                                         default:
7017                                                 g_assert_not_reached ();
7018                                         }
7019                                 }
7020                                 break;
7021                         default:
7022                                 break;
7023                         }
7024
7025                         continue;
7026                 }
7027
7028                 /* Save volatile arguments to the stack */
7029                 if (ins->opcode != OP_REGVAR) {
7030                         switch (ainfo->storage) {
7031                         case ArgInIReg: {
7032                                 guint32 size = 8;
7033
7034                                 /* FIXME: I1 etc */
7035                                 /*
7036                                 if (stack_offset & 0x1)
7037                                         size = 1;
7038                                 else if (stack_offset & 0x2)
7039                                         size = 2;
7040                                 else if (stack_offset & 0x4)
7041                                         size = 4;
7042                                 else
7043                                         size = 8;
7044                                 */
7045                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7046
7047                                 /*
7048                                  * Save the original location of 'this',
7049                                  * get_generic_info_from_stack_frame () needs this to properly look up
7050                                  * the argument value during the handling of async exceptions.
7051                                  */
7052                                 if (ins == cfg->args [0]) {
7053                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7054                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7055                                 }
7056                                 break;
7057                         }
7058                         case ArgInFloatSSEReg:
7059                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7060                                 break;
7061                         case ArgInDoubleSSEReg:
7062                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7063                                 break;
7064                         case ArgValuetypeInReg:
7065                                 for (quad = 0; quad < 2; quad ++) {
7066                                         switch (ainfo->pair_storage [quad]) {
7067                                         case ArgInIReg:
7068                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7069                                                 break;
7070                                         case ArgInFloatSSEReg:
7071                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7072                                                 break;
7073                                         case ArgInDoubleSSEReg:
7074                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7075                                                 break;
7076                                         case ArgNone:
7077                                                 break;
7078                                         default:
7079                                                 g_assert_not_reached ();
7080                                         }
7081                                 }
7082                                 break;
7083                         case ArgValuetypeAddrInIReg:
7084                                 if (ainfo->pair_storage [0] == ArgInIReg)
7085                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7086                                 break;
7087                         default:
7088                                 break;
7089                         }
7090                 } else {
7091                         /* Argument allocated to (non-volatile) register */
7092                         switch (ainfo->storage) {
7093                         case ArgInIReg:
7094                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7095                                 break;
7096                         case ArgOnStack:
7097                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7098                                 break;
7099                         default:
7100                                 g_assert_not_reached ();
7101                         }
7102
7103                         if (ins == cfg->args [0]) {
7104                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7105                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7106                         }
7107                 }
7108         }
7109
7110 #ifdef HOST_WIN32
7111         if (method->save_lmf) {
7112                 code = emit_push_lmf (cfg, code, lmf_var->inst_offset, &args_clobbered);
7113         }
7114 #else
7115         args_clobbered = TRUE;
7116 #endif
7117
7118         if (trace) {
7119                 args_clobbered = TRUE;
7120                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7121         }
7122
7123         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7124                 args_clobbered = TRUE;
7125
7126         /*
7127          * Optimize the common case of the first bblock making a call with the same
7128          * arguments as the method. This works because the arguments are still in their
7129          * original argument registers.
7130          * FIXME: Generalize this
7131          */
7132         if (!args_clobbered) {
7133                 MonoBasicBlock *first_bb = cfg->bb_entry;
7134                 MonoInst *next;
7135
7136                 next = mono_bb_first_ins (first_bb);
7137                 if (!next && first_bb->next_bb) {
7138                         first_bb = first_bb->next_bb;
7139                         next = mono_bb_first_ins (first_bb);
7140                 }
7141
7142                 if (first_bb->in_count > 1)
7143                         next = NULL;
7144
7145                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7146                         ArgInfo *ainfo = cinfo->args + i;
7147                         gboolean match = FALSE;
7148
7149                         ins = cfg->args [i];
7150                         if (ins->opcode != OP_REGVAR) {
7151                                 switch (ainfo->storage) {
7152                                 case ArgInIReg: {
7153                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7154                                                 if (next->dreg == ainfo->reg) {
7155                                                         NULLIFY_INS (next);
7156                                                         match = TRUE;
7157                                                 } else {
7158                                                         next->opcode = OP_MOVE;
7159                                                         next->sreg1 = ainfo->reg;
7160                                                         /* Only continue if the instruction doesn't change argument regs */
7161                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7162                                                                 match = TRUE;
7163                                                 }
7164                                         }
7165                                         break;
7166                                 }
7167                                 default:
7168                                         break;
7169                                 }
7170                         } else {
7171                                 /* Argument allocated to (non-volatile) register */
7172                                 switch (ainfo->storage) {
7173                                 case ArgInIReg:
7174                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7175                                                 NULLIFY_INS (next);
7176                                                 match = TRUE;
7177                                         }
7178                                         break;
7179                                 default:
7180                                         break;
7181                                 }
7182                         }
7183
7184                         if (match) {
7185                                 next = next->next;
7186                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7187                                 if (!next)
7188                                         break;
7189                         }
7190                 }
7191         }
7192
7193         if (cfg->gen_seq_points) {
7194                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7195
7196                 /* Initialize seq_point_info_var */
7197                 if (cfg->compile_aot) {
7198                         /* Initialize the variable from a GOT slot */
7199                         /* Same as OP_AOTCONST */
7200                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7201                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7202                         g_assert (info_var->opcode == OP_REGOFFSET);
7203                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7204                 }
7205
7206                 /* Initialize ss_trigger_page_var */
7207                 ins = cfg->arch.ss_trigger_page_var;
7208
7209                 g_assert (ins->opcode == OP_REGOFFSET);
7210
7211                 if (cfg->compile_aot) {
7212                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7213                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7214                 } else {
7215                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7216                 }
7217                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7218         }
7219
7220         cfg->code_len = code - cfg->native_code;
7221
7222         g_assert (cfg->code_len < cfg->code_size);
7223
7224         return code;
7225 }
7226
7227 void
7228 mono_arch_emit_epilog (MonoCompile *cfg)
7229 {
7230         MonoMethod *method = cfg->method;
7231         int quad, pos, i;
7232         guint8 *code;
7233         int max_epilog_size;
7234         CallInfo *cinfo;
7235         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7236
7237         max_epilog_size = get_max_epilog_size (cfg);
7238
7239         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7240                 cfg->code_size *= 2;
7241                 cfg->native_code = mono_realloc_native_code (cfg);
7242                 cfg->stat_code_reallocs++;
7243         }
7244
7245         code = cfg->native_code + cfg->code_len;
7246
7247         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7248                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7249
7250         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7251         pos = 0;
7252
7253         if (method->save_lmf) {
7254 #ifdef HOST_WIN32
7255                 code = emit_pop_lmf (cfg, code, lmf_offset);
7256 #endif
7257
7258                 /* check if we need to restore protection of the stack after a stack overflow */
7259                 if (mono_get_jit_tls_offset () != -1) {
7260                         guint8 *patch;
7261                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7262                         /* we load the value in a separate instruction: this mechanism may be
7263                          * used later as a safer way to do thread interruption
7264                          */
7265                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7266                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7267                         patch = code;
7268                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7269                         /* note that the call trampoline will preserve eax/edx */
7270                         x86_call_reg (code, X86_ECX);
7271                         x86_patch (patch, code);
7272                 } else {
7273                         /* FIXME: maybe save the jit tls in the prolog */
7274                 }
7275
7276                 /* Restore caller saved regs */
7277                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7278                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
7279                 }
7280                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
7281                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
7282                 }
7283                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
7284                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
7285                 }
7286                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
7287                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
7288                 }
7289                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
7290                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
7291                 }
7292                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
7293 #if defined(__default_codegen__)
7294                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
7295 #elif defined(__native_client_codegen__)
7296                         g_assert_not_reached();
7297 #endif
7298                 }
7299 #ifdef HOST_WIN32
7300                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
7301                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
7302                 }
7303                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
7304                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
7305                 }
7306 #endif
7307         } else {
7308                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7309
7310                 for (i = 0; i < AMD64_NREG; ++i)
7311                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7312                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7313                                 save_area_offset += 8;
7314                         }
7315         }
7316
7317         /* Load returned vtypes into registers if needed */
7318         cinfo = cfg->arch.cinfo;
7319         if (cinfo->ret.storage == ArgValuetypeInReg) {
7320                 ArgInfo *ainfo = &cinfo->ret;
7321                 MonoInst *inst = cfg->ret;
7322
7323                 for (quad = 0; quad < 2; quad ++) {
7324                         switch (ainfo->pair_storage [quad]) {
7325                         case ArgInIReg:
7326                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7327                                 break;
7328                         case ArgInFloatSSEReg:
7329                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7330                                 break;
7331                         case ArgInDoubleSSEReg:
7332                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7333                                 break;
7334                         case ArgNone:
7335                                 break;
7336                         default:
7337                                 g_assert_not_reached ();
7338                         }
7339                 }
7340         }
7341
7342         if (cfg->arch.omit_fp) {
7343                 if (cfg->arch.stack_alloc_size)
7344                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7345         } else {
7346                 amd64_leave (code);
7347         }
7348         async_exc_point (code);
7349         amd64_ret (code);
7350
7351         cfg->code_len = code - cfg->native_code;
7352
7353         g_assert (cfg->code_len < cfg->code_size);
7354 }
7355
7356 void
7357 mono_arch_emit_exceptions (MonoCompile *cfg)
7358 {
7359         MonoJumpInfo *patch_info;
7360         int nthrows, i;
7361         guint8 *code;
7362         MonoClass *exc_classes [16];
7363         guint8 *exc_throw_start [16], *exc_throw_end [16];
7364         guint32 code_size = 0;
7365
7366         /* Compute needed space */
7367         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7368                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7369                         code_size += 40;
7370                 if (patch_info->type == MONO_PATCH_INFO_R8)
7371                         code_size += 8 + 15; /* sizeof (double) + alignment */
7372                 if (patch_info->type == MONO_PATCH_INFO_R4)
7373                         code_size += 4 + 15; /* sizeof (float) + alignment */
7374                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7375                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7376         }
7377
7378 #ifdef __native_client_codegen__
7379         /* Give us extra room on Native Client.  This could be   */
7380         /* more carefully calculated, but bundle alignment makes */
7381         /* it much trickier, so *2 like other places is good.    */
7382         code_size *= 2;
7383 #endif
7384
7385         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7386                 cfg->code_size *= 2;
7387                 cfg->native_code = mono_realloc_native_code (cfg);
7388                 cfg->stat_code_reallocs++;
7389         }
7390
7391         code = cfg->native_code + cfg->code_len;
7392
7393         /* add code to raise exceptions */
7394         nthrows = 0;
7395         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7396                 switch (patch_info->type) {
7397                 case MONO_PATCH_INFO_EXC: {
7398                         MonoClass *exc_class;
7399                         guint8 *buf, *buf2;
7400                         guint32 throw_ip;
7401
7402                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7403
7404                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7405                         g_assert (exc_class);
7406                         throw_ip = patch_info->ip.i;
7407
7408                         //x86_breakpoint (code);
7409                         /* Find a throw sequence for the same exception class */
7410                         for (i = 0; i < nthrows; ++i)
7411                                 if (exc_classes [i] == exc_class)
7412                                         break;
7413                         if (i < nthrows) {
7414                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7415                                 x86_jump_code (code, exc_throw_start [i]);
7416                                 patch_info->type = MONO_PATCH_INFO_NONE;
7417                         }
7418                         else {
7419                                 buf = code;
7420                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7421                                 buf2 = code;
7422
7423                                 if (nthrows < 16) {
7424                                         exc_classes [nthrows] = exc_class;
7425                                         exc_throw_start [nthrows] = code;
7426                                 }
7427                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7428
7429                                 patch_info->type = MONO_PATCH_INFO_NONE;
7430
7431                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7432
7433                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7434                                 while (buf < buf2)
7435                                         x86_nop (buf);
7436
7437                                 if (nthrows < 16) {
7438                                         exc_throw_end [nthrows] = code;
7439                                         nthrows ++;
7440                                 }
7441                         }
7442                         break;
7443                 }
7444                 default:
7445                         /* do nothing */
7446                         break;
7447                 }
7448                 g_assert(code < cfg->native_code + cfg->code_size);
7449         }
7450
7451         /* Handle relocations with RIP relative addressing */
7452         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7453                 gboolean remove = FALSE;
7454                 guint8 *orig_code = code;
7455
7456                 switch (patch_info->type) {
7457                 case MONO_PATCH_INFO_R8:
7458                 case MONO_PATCH_INFO_R4: {
7459                         guint8 *pos, *patch_pos;
7460                         guint32 target_pos;
7461
7462                         /* The SSE opcodes require a 16 byte alignment */
7463 #if defined(__default_codegen__)
7464                         code = (guint8*)ALIGN_TO (code, 16);
7465 #elif defined(__native_client_codegen__)
7466                         {
7467                                 /* Pad this out with HLT instructions  */
7468                                 /* or we can get garbage bytes emitted */
7469                                 /* which will fail validation          */
7470                                 guint8 *aligned_code;
7471                                 /* extra align to make room for  */
7472                                 /* mov/push below                      */
7473                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7474                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7475                                 /* The technique of hiding data in an  */
7476                                 /* instruction has a problem here: we  */
7477                                 /* need the data aligned to a 16-byte  */
7478                                 /* boundary but the instruction cannot */
7479                                 /* cross the bundle boundary. so only  */
7480                                 /* odd multiples of 16 can be used     */
7481                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7482                                         aligned_code += 16;
7483                                 }
7484                                 while (code < aligned_code) {
7485                                         *(code++) = 0xf4; /* hlt */
7486                                 }
7487                         }
7488 #endif
7489
7490                         pos = cfg->native_code + patch_info->ip.i;
7491                         if (IS_REX (pos [1])) {
7492                                 patch_pos = pos + 5;
7493                                 target_pos = code - pos - 9;
7494                         }
7495                         else {
7496                                 patch_pos = pos + 4;
7497                                 target_pos = code - pos - 8;
7498                         }
7499
7500                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7501 #ifdef __native_client_codegen__
7502                                 /* Hide 64-bit data in a         */
7503                                 /* "mov imm64, r11" instruction. */
7504                                 /* write it before the start of  */
7505                                 /* the data*/
7506                                 *(code-2) = 0x49; /* prefix      */
7507                                 *(code-1) = 0xbb; /* mov X, %r11 */
7508 #endif
7509                                 *(double*)code = *(double*)patch_info->data.target;
7510                                 code += sizeof (double);
7511                         } else {
7512 #ifdef __native_client_codegen__
7513                                 /* Hide 32-bit data in a        */
7514                                 /* "push imm32" instruction.    */
7515                                 *(code-1) = 0x68; /* push */
7516 #endif
7517                                 *(float*)code = *(float*)patch_info->data.target;
7518                                 code += sizeof (float);
7519                         }
7520
7521                         *(guint32*)(patch_pos) = target_pos;
7522
7523                         remove = TRUE;
7524                         break;
7525                 }
7526                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7527                         guint8 *pos;
7528
7529                         if (cfg->compile_aot)
7530                                 continue;
7531
7532                         /*loading is faster against aligned addresses.*/
7533                         code = (guint8*)ALIGN_TO (code, 8);
7534                         memset (orig_code, 0, code - orig_code);
7535
7536                         pos = cfg->native_code + patch_info->ip.i;
7537
7538                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7539                         if (IS_REX (pos [1]))
7540                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7541                         else
7542                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7543
7544                         *(gpointer*)code = (gpointer)patch_info->data.target;
7545                         code += sizeof (gpointer);
7546
7547                         remove = TRUE;
7548                         break;
7549                 }
7550                 default:
7551                         break;
7552                 }
7553
7554                 if (remove) {
7555                         if (patch_info == cfg->patch_info)
7556                                 cfg->patch_info = patch_info->next;
7557                         else {
7558                                 MonoJumpInfo *tmp;
7559
7560                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7561                                         ;
7562                                 tmp->next = patch_info->next;
7563                         }
7564                 }
7565                 g_assert (code < cfg->native_code + cfg->code_size);
7566         }
7567
7568         cfg->code_len = code - cfg->native_code;
7569
7570         g_assert (cfg->code_len < cfg->code_size);
7571
7572 }
7573
7574 #endif /* DISABLE_JIT */
7575
7576 void*
7577 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7578 {
7579         guchar *code = p;
7580         CallInfo *cinfo = NULL;
7581         MonoMethodSignature *sig;
7582         MonoInst *inst;
7583         int i, n, stack_area = 0;
7584
7585         /* Keep this in sync with mono_arch_get_argument_info */
7586
7587         if (enable_arguments) {
7588                 /* Allocate a new area on the stack and save arguments there */
7589                 sig = mono_method_signature (cfg->method);
7590
7591                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7592
7593                 n = sig->param_count + sig->hasthis;
7594
7595                 stack_area = ALIGN_TO (n * 8, 16);
7596
7597                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7598
7599                 for (i = 0; i < n; ++i) {
7600                         inst = cfg->args [i];
7601
7602                         if (inst->opcode == OP_REGVAR)
7603                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7604                         else {
7605                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7606                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7607                         }
7608                 }
7609         }
7610
7611         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7612         amd64_set_reg_template (code, AMD64_ARG_REG1);
7613         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7614         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7615
7616         if (enable_arguments)
7617                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7618
7619         return code;
7620 }
7621
7622 enum {
7623         SAVE_NONE,
7624         SAVE_STRUCT,
7625         SAVE_EAX,
7626         SAVE_EAX_EDX,
7627         SAVE_XMM
7628 };
7629
7630 void*
7631 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7632 {
7633         guchar *code = p;
7634         int save_mode = SAVE_NONE;
7635         MonoMethod *method = cfg->method;
7636         MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7637         int i;
7638
7639         switch (ret_type->type) {
7640         case MONO_TYPE_VOID:
7641                 /* special case string .ctor icall */
7642                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7643                         save_mode = SAVE_EAX;
7644                 else
7645                         save_mode = SAVE_NONE;
7646                 break;
7647         case MONO_TYPE_I8:
7648         case MONO_TYPE_U8:
7649                 save_mode = SAVE_EAX;
7650                 break;
7651         case MONO_TYPE_R4:
7652         case MONO_TYPE_R8:
7653                 save_mode = SAVE_XMM;
7654                 break;
7655         case MONO_TYPE_GENERICINST:
7656                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7657                         save_mode = SAVE_EAX;
7658                         break;
7659                 }
7660                 /* Fall through */
7661         case MONO_TYPE_VALUETYPE:
7662                 save_mode = SAVE_STRUCT;
7663                 break;
7664         default:
7665                 save_mode = SAVE_EAX;
7666                 break;
7667         }
7668
7669         /* Save the result and copy it into the proper argument register */
7670         switch (save_mode) {
7671         case SAVE_EAX:
7672                 amd64_push_reg (code, AMD64_RAX);
7673                 /* Align stack */
7674                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7675                 if (enable_arguments)
7676                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7677                 break;
7678         case SAVE_STRUCT:
7679                 /* FIXME: */
7680                 if (enable_arguments)
7681                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7682                 break;
7683         case SAVE_XMM:
7684                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7685                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7686                 /* Align stack */
7687                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7688                 /*
7689                  * The result is already in the proper argument register so no copying
7690                  * needed.
7691                  */
7692                 break;
7693         case SAVE_NONE:
7694                 break;
7695         default:
7696                 g_assert_not_reached ();
7697         }
7698
7699         /* Set %al since this is a varargs call */
7700         if (save_mode == SAVE_XMM)
7701                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7702         else
7703                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7704
7705         if (preserve_argument_registers) {
7706                 for (i = 0; i < PARAM_REGS; ++i)
7707                         amd64_push_reg (code, param_regs [i]);
7708         }
7709
7710         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7711         amd64_set_reg_template (code, AMD64_ARG_REG1);
7712         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7713
7714         if (preserve_argument_registers) {
7715                 for (i = PARAM_REGS - 1; i >= 0; --i)
7716                         amd64_pop_reg (code, param_regs [i]);
7717         }
7718
7719         /* Restore result */
7720         switch (save_mode) {
7721         case SAVE_EAX:
7722                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7723                 amd64_pop_reg (code, AMD64_RAX);
7724                 break;
7725         case SAVE_STRUCT:
7726                 /* FIXME: */
7727                 break;
7728         case SAVE_XMM:
7729                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7730                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7731                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7732                 break;
7733         case SAVE_NONE:
7734                 break;
7735         default:
7736                 g_assert_not_reached ();
7737         }
7738
7739         return code;
7740 }
7741
7742 void
7743 mono_arch_flush_icache (guint8 *code, gint size)
7744 {
7745         /* Not needed */
7746 }
7747
7748 void
7749 mono_arch_flush_register_windows (void)
7750 {
7751 }
7752
7753 gboolean
7754 mono_arch_is_inst_imm (gint64 imm)
7755 {
7756         return amd64_is_imm32 (imm);
7757 }
7758
7759 /*
7760  * Determine whenever the trap whose info is in SIGINFO is caused by
7761  * integer overflow.
7762  */
7763 gboolean
7764 mono_arch_is_int_overflow (void *sigctx, void *info)
7765 {
7766         MonoContext ctx;
7767         guint8* rip;
7768         int reg;
7769         gint64 value;
7770
7771         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7772
7773         rip = (guint8*)ctx.rip;
7774
7775         if (IS_REX (rip [0])) {
7776                 reg = amd64_rex_b (rip [0]);
7777                 rip ++;
7778         }
7779         else
7780                 reg = 0;
7781
7782         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7783                 /* idiv REG */
7784                 reg += x86_modrm_rm (rip [1]);
7785
7786                 switch (reg) {
7787                 case AMD64_RAX:
7788                         value = ctx.rax;
7789                         break;
7790                 case AMD64_RBX:
7791                         value = ctx.rbx;
7792                         break;
7793                 case AMD64_RCX:
7794                         value = ctx.rcx;
7795                         break;
7796                 case AMD64_RDX:
7797                         value = ctx.rdx;
7798                         break;
7799                 case AMD64_RBP:
7800                         value = ctx.rbp;
7801                         break;
7802                 case AMD64_RSP:
7803                         value = ctx.rsp;
7804                         break;
7805                 case AMD64_RSI:
7806                         value = ctx.rsi;
7807                         break;
7808                 case AMD64_RDI:
7809                         value = ctx.rdi;
7810                         break;
7811                 case AMD64_R12:
7812                         value = ctx.r12;
7813                         break;
7814                 case AMD64_R13:
7815                         value = ctx.r13;
7816                         break;
7817                 case AMD64_R14:
7818                         value = ctx.r14;
7819                         break;
7820                 case AMD64_R15:
7821                         value = ctx.r15;
7822                         break;
7823                 default:
7824                         g_assert_not_reached ();
7825                         reg = -1;
7826                 }
7827
7828                 if (value == -1)
7829                         return TRUE;
7830         }
7831
7832         return FALSE;
7833 }
7834
7835 guint32
7836 mono_arch_get_patch_offset (guint8 *code)
7837 {
7838         return 3;
7839 }
7840
7841 /**
7842  * mono_breakpoint_clean_code:
7843  *
7844  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7845  * breakpoints in the original code, they are removed in the copy.
7846  *
7847  * Returns TRUE if no sw breakpoint was present.
7848  */
7849 gboolean
7850 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7851 {
7852         int i;
7853         gboolean can_write = TRUE;
7854         /*
7855          * If method_start is non-NULL we need to perform bound checks, since we access memory
7856          * at code - offset we could go before the start of the method and end up in a different
7857          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7858          * instead.
7859          */
7860         if (!method_start || code - offset >= method_start) {
7861                 memcpy (buf, code - offset, size);
7862         } else {
7863                 int diff = code - method_start;
7864                 memset (buf, 0, size);
7865                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7866         }
7867         code -= offset;
7868         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7869                 int idx = mono_breakpoint_info_index [i];
7870                 guint8 *ptr;
7871                 if (idx < 1)
7872                         continue;
7873                 ptr = mono_breakpoint_info [idx].address;
7874                 if (ptr >= code && ptr < code + size) {
7875                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7876                         can_write = FALSE;
7877                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7878                         buf [ptr - code] = saved_byte;
7879                 }
7880         }
7881         return can_write;
7882 }
7883
7884 #if defined(__native_client_codegen__)
7885 /* For membase calls, we want the base register. for Native Client,  */
7886 /* all indirect calls have the following sequence with the given sizes: */
7887 /* mov %eXX,%eXX                                [2-3]   */
7888 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7889 /* and $0xffffffffffffffe0,%r11d                [4]     */
7890 /* add %r15,%r11                                [3]     */
7891 /* callq *%r11                                  [3]     */
7892
7893
7894 /* Determine if code points to a NaCl call-through-register sequence, */
7895 /* (i.e., the last 3 instructions listed above) */
7896 int
7897 is_nacl_call_reg_sequence(guint8* code)
7898 {
7899         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7900                                "\x4d\x03\xdf"     /* add */
7901                                "\x41\xff\xd3";   /* call */
7902         return memcmp(code, sequence, 10) == 0;
7903 }
7904
7905 /* Determine if code points to the first opcode of the mov membase component */
7906 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7907 /* (there could be a REX prefix before the opcode but it is ignored) */
7908 static int
7909 is_nacl_indirect_call_membase_sequence(guint8* code)
7910 {
7911                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7912         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7913                /* and that src reg = dest reg */
7914                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7915                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7916                IS_REX(code[2]) &&
7917                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7918                /* and has dst of r11 and base of r15 */
7919                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7920                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7921 }
7922 #endif /* __native_client_codegen__ */
7923
7924 int
7925 mono_arch_get_this_arg_reg (guint8 *code)
7926 {
7927         return AMD64_ARG_REG1;
7928 }
7929
7930 gpointer
7931 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7932 {
7933         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7934 }
7935
7936 #define MAX_ARCH_DELEGATE_PARAMS 10
7937
7938 static gpointer
7939 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7940 {
7941         guint8 *code, *start;
7942         int i;
7943
7944         if (has_target) {
7945                 start = code = mono_global_codeman_reserve (64);
7946
7947                 /* Replace the this argument with the target */
7948                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7949                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7950                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7951
7952                 g_assert ((code - start) < 64);
7953         } else {
7954                 start = code = mono_global_codeman_reserve (64);
7955
7956                 if (param_count == 0) {
7957                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7958                 } else {
7959                         /* We have to shift the arguments left */
7960                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7961                         for (i = 0; i < param_count; ++i) {
7962 #ifdef HOST_WIN32
7963                                 if (i < 3)
7964                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7965                                 else
7966                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7967 #else
7968                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7969 #endif
7970                         }
7971
7972                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7973                 }
7974                 g_assert ((code - start) < 64);
7975         }
7976
7977         nacl_global_codeman_validate(&start, 64, &code);
7978
7979         mono_debug_add_delegate_trampoline (start, code - start);
7980
7981         if (code_len)
7982                 *code_len = code - start;
7983
7984
7985         if (mono_jit_map_is_enabled ()) {
7986                 char *buff;
7987                 if (has_target)
7988                         buff = (char*)"delegate_invoke_has_target";
7989                 else
7990                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7991                 mono_emit_jit_tramp (start, code - start, buff);
7992                 if (!has_target)
7993                         g_free (buff);
7994         }
7995
7996         return start;
7997 }
7998
7999 /*
8000  * mono_arch_get_delegate_invoke_impls:
8001  *
8002  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
8003  * trampolines.
8004  */
8005 GSList*
8006 mono_arch_get_delegate_invoke_impls (void)
8007 {
8008         GSList *res = NULL;
8009         guint8 *code;
8010         guint32 code_len;
8011         int i;
8012         char *tramp_name;
8013
8014         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
8015         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
8016
8017         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
8018                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
8019                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
8020                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
8021                 g_free (tramp_name);
8022         }
8023
8024         return res;
8025 }
8026
8027 gpointer
8028 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8029 {
8030         guint8 *code, *start;
8031         int i;
8032
8033         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8034                 return NULL;
8035
8036         /* FIXME: Support more cases */
8037         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
8038                 return NULL;
8039
8040         if (has_target) {
8041                 static guint8* cached = NULL;
8042
8043                 if (cached)
8044                         return cached;
8045
8046                 if (mono_aot_only)
8047                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8048                 else
8049                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
8050
8051                 mono_memory_barrier ();
8052
8053                 cached = start;
8054         } else {
8055                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8056                 for (i = 0; i < sig->param_count; ++i)
8057                         if (!mono_is_regsize_var (sig->params [i]))
8058                                 return NULL;
8059                 if (sig->param_count > 4)
8060                         return NULL;
8061
8062                 code = cache [sig->param_count];
8063                 if (code)
8064                         return code;
8065
8066                 if (mono_aot_only) {
8067                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8068                         start = mono_aot_get_trampoline (name);
8069                         g_free (name);
8070                 } else {
8071                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8072                 }
8073
8074                 mono_memory_barrier ();
8075
8076                 cache [sig->param_count] = start;
8077         }
8078
8079         return start;
8080 }
8081 void
8082 mono_arch_finish_init (void)
8083 {
8084 #ifdef HOST_WIN32
8085         /*
8086          * We need to init this multiple times, since when we are first called, the key might not
8087          * be initialized yet.
8088          */
8089         jit_tls_offset = mono_get_jit_tls_key ();
8090
8091         /* Only 64 tls entries can be accessed using inline code */
8092         if (jit_tls_offset >= 64)
8093                 jit_tls_offset = -1;
8094 #else
8095 #ifdef MONO_XEN_OPT
8096         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8097 #endif
8098 #endif
8099 }
8100
8101 void
8102 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8103 {
8104 }
8105
8106 #ifdef MONO_ARCH_HAVE_IMT
8107
8108 #if defined(__default_codegen__)
8109 #define CMP_SIZE (6 + 1)
8110 #define CMP_REG_REG_SIZE (4 + 1)
8111 #define BR_SMALL_SIZE 2
8112 #define BR_LARGE_SIZE 6
8113 #define MOV_REG_IMM_SIZE 10
8114 #define MOV_REG_IMM_32BIT_SIZE 6
8115 #define JUMP_REG_SIZE (2 + 1)
8116 #elif defined(__native_client_codegen__)
8117 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8118 #define CMP_SIZE ((6 + 1) * 2 - 1)
8119 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8120 #define BR_SMALL_SIZE (2 * 2 - 1)
8121 #define BR_LARGE_SIZE (6 * 2 - 1)
8122 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8123 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8124 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8125 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8126 /* Jump membase's size is large and unpredictable    */
8127 /* in native client, just pad it out a whole bundle. */
8128 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8129 #endif
8130
8131 static int
8132 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8133 {
8134         int i, distance = 0;
8135         for (i = start; i < target; ++i)
8136                 distance += imt_entries [i]->chunk_size;
8137         return distance;
8138 }
8139
8140 /*
8141  * LOCKING: called with the domain lock held
8142  */
8143 gpointer
8144 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8145         gpointer fail_tramp)
8146 {
8147         int i;
8148         int size = 0;
8149         guint8 *code, *start;
8150         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8151
8152         for (i = 0; i < count; ++i) {
8153                 MonoIMTCheckItem *item = imt_entries [i];
8154                 if (item->is_equals) {
8155                         if (item->check_target_idx) {
8156                                 if (!item->compare_done) {
8157                                         if (amd64_is_imm32 (item->key))
8158                                                 item->chunk_size += CMP_SIZE;
8159                                         else
8160                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8161                                 }
8162                                 if (item->has_target_code) {
8163                                         item->chunk_size += MOV_REG_IMM_SIZE;
8164                                 } else {
8165                                         if (vtable_is_32bit)
8166                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8167                                         else
8168                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8169 #ifdef __native_client_codegen__
8170                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8171 #endif
8172                                 }
8173                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8174                         } else {
8175                                 if (fail_tramp) {
8176                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8177                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8178                                 } else {
8179                                         if (vtable_is_32bit)
8180                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8181                                         else
8182                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8183                                         item->chunk_size += JUMP_REG_SIZE;
8184                                         /* with assert below:
8185                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8186                                          */
8187 #ifdef __native_client_codegen__
8188                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8189 #endif
8190                                 }
8191                         }
8192                 } else {
8193                         if (amd64_is_imm32 (item->key))
8194                                 item->chunk_size += CMP_SIZE;
8195                         else
8196                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8197                         item->chunk_size += BR_LARGE_SIZE;
8198                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8199                 }
8200                 size += item->chunk_size;
8201         }
8202 #if defined(__native_client__) && defined(__native_client_codegen__)
8203         /* In Native Client, we don't re-use thunks, allocate from the */
8204         /* normal code manager paths. */
8205         code = mono_domain_code_reserve (domain, size);
8206 #else
8207         if (fail_tramp)
8208                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8209         else
8210                 code = mono_domain_code_reserve (domain, size);
8211 #endif
8212         start = code;
8213         for (i = 0; i < count; ++i) {
8214                 MonoIMTCheckItem *item = imt_entries [i];
8215                 item->code_target = code;
8216                 if (item->is_equals) {
8217                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8218
8219                         if (item->check_target_idx || fail_case) {
8220                                 if (!item->compare_done || fail_case) {
8221                                         if (amd64_is_imm32 (item->key))
8222                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8223                                         else {
8224                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8225                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8226                                         }
8227                                 }
8228                                 item->jmp_code = code;
8229                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8230                                 if (item->has_target_code) {
8231                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8232                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8233                                 } else {
8234                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8235                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8236                                 }
8237
8238                                 if (fail_case) {
8239                                         amd64_patch (item->jmp_code, code);
8240                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8241                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8242                                         item->jmp_code = NULL;
8243                                 }
8244                         } else {
8245                                 /* enable the commented code to assert on wrong method */
8246 #if 0
8247                                 if (amd64_is_imm32 (item->key))
8248                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8249                                 else {
8250                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8251                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8252                                 }
8253                                 item->jmp_code = code;
8254                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8255                                 /* See the comment below about R10 */
8256                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8257                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8258                                 amd64_patch (item->jmp_code, code);
8259                                 amd64_breakpoint (code);
8260                                 item->jmp_code = NULL;
8261 #else
8262                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8263                                    needs to be preserved.  R10 needs
8264                                    to be preserved for calls which
8265                                    require a runtime generic context,
8266                                    but interface calls don't. */
8267                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8268                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8269 #endif
8270                         }
8271                 } else {
8272                         if (amd64_is_imm32 (item->key))
8273                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8274                         else {
8275                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8276                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8277                         }
8278                         item->jmp_code = code;
8279                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8280                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8281                         else
8282                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8283                 }
8284                 g_assert (code - item->code_target <= item->chunk_size);
8285         }
8286         /* patch the branches to get to the target items */
8287         for (i = 0; i < count; ++i) {
8288                 MonoIMTCheckItem *item = imt_entries [i];
8289                 if (item->jmp_code) {
8290                         if (item->check_target_idx) {
8291                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8292                         }
8293                 }
8294         }
8295
8296         if (!fail_tramp)
8297                 mono_stats.imt_thunks_size += code - start;
8298         g_assert (code - start <= size);
8299
8300         nacl_domain_code_validate(domain, &start, size, &code);
8301
8302         return start;
8303 }
8304
8305 MonoMethod*
8306 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8307 {
8308         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8309 }
8310 #endif
8311
8312 MonoVTable*
8313 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8314 {
8315         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8316 }
8317
8318 GSList*
8319 mono_arch_get_cie_program (void)
8320 {
8321         GSList *l = NULL;
8322
8323         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8324         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8325
8326         return l;
8327 }
8328
8329 MonoInst*
8330 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8331 {
8332         MonoInst *ins = NULL;
8333         int opcode = 0;
8334
8335         if (cmethod->klass == mono_defaults.math_class) {
8336                 if (strcmp (cmethod->name, "Sin") == 0) {
8337                         opcode = OP_SIN;
8338                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8339                         opcode = OP_COS;
8340                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8341                         opcode = OP_SQRT;
8342                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8343                         opcode = OP_ABS;
8344                 }
8345
8346                 if (opcode) {
8347                         MONO_INST_NEW (cfg, ins, opcode);
8348                         ins->type = STACK_R8;
8349                         ins->dreg = mono_alloc_freg (cfg);
8350                         ins->sreg1 = args [0]->dreg;
8351                         MONO_ADD_INS (cfg->cbb, ins);
8352                 }
8353
8354                 opcode = 0;
8355                 if (cfg->opt & MONO_OPT_CMOV) {
8356                         if (strcmp (cmethod->name, "Min") == 0) {
8357                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8358                                         opcode = OP_IMIN;
8359                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8360                                         opcode = OP_IMIN_UN;
8361                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8362                                         opcode = OP_LMIN;
8363                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8364                                         opcode = OP_LMIN_UN;
8365                         } else if (strcmp (cmethod->name, "Max") == 0) {
8366                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8367                                         opcode = OP_IMAX;
8368                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8369                                         opcode = OP_IMAX_UN;
8370                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8371                                         opcode = OP_LMAX;
8372                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8373                                         opcode = OP_LMAX_UN;
8374                         }
8375                 }
8376
8377                 if (opcode) {
8378                         MONO_INST_NEW (cfg, ins, opcode);
8379                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8380                         ins->dreg = mono_alloc_ireg (cfg);
8381                         ins->sreg1 = args [0]->dreg;
8382                         ins->sreg2 = args [1]->dreg;
8383                         MONO_ADD_INS (cfg->cbb, ins);
8384                 }
8385
8386 #if 0
8387                 /* OP_FREM is not IEEE compatible */
8388                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8389                         MONO_INST_NEW (cfg, ins, OP_FREM);
8390                         ins->inst_i0 = args [0];
8391                         ins->inst_i1 = args [1];
8392                 }
8393 #endif
8394         }
8395
8396         /*
8397          * Can't implement CompareExchange methods this way since they have
8398          * three arguments.
8399          */
8400
8401         return ins;
8402 }
8403
8404 gboolean
8405 mono_arch_print_tree (MonoInst *tree, int arity)
8406 {
8407         return 0;
8408 }
8409
8410 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8411
8412 mgreg_t
8413 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8414 {
8415         switch (reg) {
8416         case AMD64_RCX: return ctx->rcx;
8417         case AMD64_RDX: return ctx->rdx;
8418         case AMD64_RBX: return ctx->rbx;
8419         case AMD64_RBP: return ctx->rbp;
8420         case AMD64_RSP: return ctx->rsp;
8421         default:
8422                 return _CTX_REG (ctx, rax, reg);
8423         }
8424 }
8425
8426 void
8427 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8428 {
8429         switch (reg) {
8430         case AMD64_RCX:
8431                 ctx->rcx = val;
8432                 break;
8433         case AMD64_RDX:
8434                 ctx->rdx = val;
8435                 break;
8436         case AMD64_RBX:
8437                 ctx->rbx = val;
8438                 break;
8439         case AMD64_RBP:
8440                 ctx->rbp = val;
8441                 break;
8442         case AMD64_RSP:
8443                 ctx->rsp = val;
8444                 break;
8445         default:
8446                 _CTX_REG (ctx, rax, reg) = val;
8447         }
8448 }
8449
8450 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8451 gpointer
8452 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8453 {
8454         int offset;
8455         gpointer *sp, old_value;
8456         char *bp;
8457         const unsigned char *handler;
8458
8459         /*Decode the first instruction to figure out where did we store the spvar*/
8460         /*Our jit MUST generate the following:
8461          mov    %rsp, ?(%rbp)
8462
8463          Which is encoded as: REX.W 0x89 mod_rm
8464          mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8465                 mod (reg + imm8):  01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8466                 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8467
8468         FIXME can we generate frameless methods on this case?
8469
8470         */
8471         handler = clause->handler_start;
8472
8473         /*REX.W*/
8474         if (*handler != 0x48)
8475                 return NULL;
8476         ++handler;
8477
8478         /*mov r, r/m */
8479         if (*handler != 0x89)
8480                 return NULL;
8481         ++handler;
8482
8483         if (*handler == 0x65)
8484                 offset = *(signed char*)(handler + 1);
8485         else if (*handler == 0xA5)
8486                 offset = *(int*)(handler + 1);
8487         else
8488                 return NULL;
8489
8490         /*Load the spvar*/
8491         bp = MONO_CONTEXT_GET_BP (ctx);
8492         sp = *(gpointer*)(bp + offset);
8493
8494         old_value = *sp;
8495         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8496                 return old_value;
8497
8498         *sp = new_value;
8499
8500         return old_value;
8501 }
8502
8503 /*
8504  * mono_arch_emit_load_aotconst:
8505  *
8506  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8507  * TARGET from the mscorlib GOT in full-aot code.
8508  * On AMD64, the result is placed into R11.
8509  */
8510 guint8*
8511 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8512 {
8513         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8514         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8515
8516         return code;
8517 }
8518
8519 /*
8520  * mono_arch_get_trampolines:
8521  *
8522  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8523  * for AOT.
8524  */
8525 GSList *
8526 mono_arch_get_trampolines (gboolean aot)
8527 {
8528         return mono_amd64_get_exception_trampolines (aot);
8529 }
8530
8531 /* Soft Debug support */
8532 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8533
8534 /*
8535  * mono_arch_set_breakpoint:
8536  *
8537  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8538  * The location should contain code emitted by OP_SEQ_POINT.
8539  */
8540 void
8541 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8542 {
8543         guint8 *code = ip;
8544         guint8 *orig_code = code;
8545
8546         if (ji->from_aot) {
8547                 guint32 native_offset = ip - (guint8*)ji->code_start;
8548                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8549
8550                 g_assert (info->bp_addrs [native_offset] == 0);
8551                 info->bp_addrs [native_offset] = bp_trigger_page;
8552         } else {
8553                 /*
8554                  * In production, we will use int3 (has to fix the size in the md
8555                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8556                  * instead.
8557                  */
8558                 g_assert (code [0] == 0x90);
8559                 if (breakpoint_size == 8) {
8560                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8561                 } else {
8562                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8563                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8564                 }
8565
8566                 g_assert (code - orig_code == breakpoint_size);
8567         }
8568 }
8569
8570 /*
8571  * mono_arch_clear_breakpoint:
8572  *
8573  *   Clear the breakpoint at IP.
8574  */
8575 void
8576 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8577 {
8578         guint8 *code = ip;
8579         int i;
8580
8581         if (ji->from_aot) {
8582                 guint32 native_offset = ip - (guint8*)ji->code_start;
8583                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8584
8585                 g_assert (info->bp_addrs [native_offset] == 0);
8586                 info->bp_addrs [native_offset] = info;
8587         } else {
8588                 for (i = 0; i < breakpoint_size; ++i)
8589                         x86_nop (code);
8590         }
8591 }
8592
8593 gboolean
8594 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8595 {
8596 #ifdef HOST_WIN32
8597         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8598         return FALSE;
8599 #else
8600         siginfo_t* sinfo = (siginfo_t*) info;
8601         /* Sometimes the address is off by 4 */
8602         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8603                 return TRUE;
8604         else
8605                 return FALSE;
8606 #endif
8607 }
8608
8609 /*
8610  * mono_arch_skip_breakpoint:
8611  *
8612  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8613  * we resume, the instruction is not executed again.
8614  */
8615 void
8616 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8617 {
8618         if (ji->from_aot) {
8619                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8620                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8621         } else {
8622                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8623         }
8624 }
8625
8626 /*
8627  * mono_arch_start_single_stepping:
8628  *
8629  *   Start single stepping.
8630  */
8631 void
8632 mono_arch_start_single_stepping (void)
8633 {
8634         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8635 }
8636
8637 /*
8638  * mono_arch_stop_single_stepping:
8639  *
8640  *   Stop single stepping.
8641  */
8642 void
8643 mono_arch_stop_single_stepping (void)
8644 {
8645         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8646 }
8647
8648 /*
8649  * mono_arch_is_single_step_event:
8650  *
8651  *   Return whenever the machine state in SIGCTX corresponds to a single
8652  * step event.
8653  */
8654 gboolean
8655 mono_arch_is_single_step_event (void *info, void *sigctx)
8656 {
8657 #ifdef HOST_WIN32
8658         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8659         return FALSE;
8660 #else
8661         siginfo_t* sinfo = (siginfo_t*) info;
8662         /* Sometimes the address is off by 4 */
8663         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8664                 return TRUE;
8665         else
8666                 return FALSE;
8667 #endif
8668 }
8669
8670 /*
8671  * mono_arch_skip_single_step:
8672  *
8673  *   Modify CTX so the ip is placed after the single step trigger instruction,
8674  * we resume, the instruction is not executed again.
8675  */
8676 void
8677 mono_arch_skip_single_step (MonoContext *ctx)
8678 {
8679         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8680 }
8681
8682 /*
8683  * mono_arch_create_seq_point_info:
8684  *
8685  *   Return a pointer to a data structure which is used by the sequence
8686  * point implementation in AOTed code.
8687  */
8688 gpointer
8689 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8690 {
8691         SeqPointInfo *info;
8692         MonoJitInfo *ji;
8693         int i;
8694
8695         // FIXME: Add a free function
8696
8697         mono_domain_lock (domain);
8698         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8699                                                                 code);
8700         mono_domain_unlock (domain);
8701
8702         if (!info) {
8703                 ji = mono_jit_info_table_find (domain, (char*)code);
8704                 g_assert (ji);
8705
8706                 // FIXME: Optimize the size
8707                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8708
8709                 info->ss_trigger_page = ss_trigger_page;
8710                 info->bp_trigger_page = bp_trigger_page;
8711                 /* Initialize to a valid address */
8712                 for (i = 0; i < ji->code_size; ++i)
8713                         info->bp_addrs [i] = info;
8714
8715                 mono_domain_lock (domain);
8716                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8717                                                          code, info);
8718                 mono_domain_unlock (domain);
8719         }
8720
8721         return info;
8722 }
8723
8724 void
8725 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8726 {
8727         ext->lmf.previous_lmf = prev_lmf;
8728         /* Mark that this is a MonoLMFExt */
8729         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8730         ext->lmf.rsp = (gssize)ext;
8731 }
8732
8733 #endif