mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/metadata/gc-internal.h>
  27 #include <mono/utils/mono-math.h>
  28 #include <mono/utils/mono-mmap.h>
  29
  30 #include "trace.h"
  31 #include "ir-emit.h"
  32 #include "mini-amd64.h"
  33 #include "cpu-amd64.h"
  34 #include "debugger-agent.h"
  35
  36 static gint lmf_tls_offset = -1;
  37 static gint lmf_addr_tls_offset = -1;
  38 static gint appdomain_tls_offset = -1;
  39
  40 #ifdef MONO_XEN_OPT
  41 static gboolean optimize_for_xen = TRUE;
  42 #else
  43 #define optimize_for_xen 0
  44 #endif
  45
  46 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  47
  48 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  49
  50 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  51
  52 #ifdef HOST_WIN32
  53 /* Under windows, the calling convention is never stdcall */
  54 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  55 #else
  56 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  57 #endif
  58
  59 /* This mutex protects architecture specific caches */
  60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  62 static CRITICAL_SECTION mini_arch_mutex;
  63
  64 MonoBreakpointInfo
  65 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  66
  67 /*
  68  * The code generated for sequence points reads from this location, which is
  69  * made read-only when single stepping is enabled.
  70  */
  71 static gpointer ss_trigger_page;
  72
  73 /* Enabled breakpoints read from this trigger page */
  74 static gpointer bp_trigger_page;
  75
  76 /* The size of the breakpoint sequence */
  77 static int breakpoint_size;
  78
  79 /* The size of the breakpoint instruction causing the actual fault */
  80 static int breakpoint_fault_size;
  81
  82 /* The size of the single step instruction causing the actual fault */
  83 static int single_step_fault_size;
  84
  85 #ifdef HOST_WIN32
  86 /* On Win64 always reserve first 32 bytes for first four arguments */
  87 #define ARGS_OFFSET 48
  88 #else
  89 #define ARGS_OFFSET 16
  90 #endif
  91 #define GP_SCRATCH_REG AMD64_R11
  92
  93 /*
  94  * AMD64 register usage:
  95  * - callee saved registers are used for global register allocation
  96  * - %r11 is used for materializing 64 bit constants in opcodes
  97  * - the rest is used for local allocation
  98  */
  99
 100 /*
 101  * Floating point comparison results:
 102  *                  ZF PF CF
 103  * A > B            0  0  0
 104  * A < B            0  0  1
 105  * A = B            1  0  0
 106  * A > B            0  0  0
 107  * UNORDERED        1  1  1
 108  */
 109
 110 const char*
 111 mono_arch_regname (int reg)
 112 {
 113         switch (reg) {
 114         case AMD64_RAX: return "%rax";
 115         case AMD64_RBX: return "%rbx";
 116         case AMD64_RCX: return "%rcx";
 117         case AMD64_RDX: return "%rdx";
 118         case AMD64_RSP: return "%rsp";
 119         case AMD64_RBP: return "%rbp";
 120         case AMD64_RDI: return "%rdi";
 121         case AMD64_RSI: return "%rsi";
 122         case AMD64_R8: return "%r8";
 123         case AMD64_R9: return "%r9";
 124         case AMD64_R10: return "%r10";
 125         case AMD64_R11: return "%r11";
 126         case AMD64_R12: return "%r12";
 127         case AMD64_R13: return "%r13";
 128         case AMD64_R14: return "%r14";
 129         case AMD64_R15: return "%r15";
 130         }
 131         return "unknown";
 132 }
 133
 134 static const char * packed_xmmregs [] = {
 135         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 136         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 137 };
 138
 139 static const char * single_xmmregs [] = {
 140         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 141         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 142 };
 143
 144 const char*
 145 mono_arch_fregname (int reg)
 146 {
 147         if (reg < AMD64_XMM_NREG)
 148                 return single_xmmregs [reg];
 149         else
 150                 return "unknown";
 151 }
 152
 153 const char *
 154 mono_arch_xregname (int reg)
 155 {
 156         if (reg < AMD64_XMM_NREG)
 157                 return packed_xmmregs [reg];
 158         else
 159                 return "unknown";
 160 }
 161
 162 G_GNUC_UNUSED static void
 163 break_count (void)
 164 {
 165 }
 166
 167 G_GNUC_UNUSED static gboolean
 168 debug_count (void)
 169 {
 170         static int count = 0;
 171         count ++;
 172
 173         if (!getenv ("COUNT"))
 174                 return TRUE;
 175
 176         if (count == atoi (getenv ("COUNT"))) {
 177                 break_count ();
 178         }
 179
 180         if (count > atoi (getenv ("COUNT"))) {
 181                 return FALSE;
 182         }
 183
 184         return TRUE;
 185 }
 186
 187 static gboolean
 188 debug_omit_fp (void)
 189 {
 190 #if 0
 191         return debug_count ();
 192 #else
 193         return TRUE;
 194 #endif
 195 }
 196
 197 static inline gboolean
 198 amd64_is_near_call (guint8 *code)
 199 {
 200         /* Skip REX */
 201         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 202                 code += 1;
 203
 204         return code [0] == 0xe8;
 205 }
 206
 207 static inline void
 208 amd64_patch (unsigned char* code, gpointer target)
 209 {
 210         guint8 rex = 0;
 211
 212         /* Skip REX */
 213         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 214                 rex = code [0];
 215                 code += 1;
 216         }
 217
 218         if ((code [0] & 0xf8) == 0xb8) {
 219                 /* amd64_set_reg_template */
 220                 *(guint64*)(code + 1) = (guint64)target;
 221         }
 222         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 223                 /* mov 0(%rip), %dreg */
 224                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 225         }
 226         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 227                 /* call *<OFFSET>(%rip) */
 228                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 229         }
 230         else if ((code [0] == 0xe8)) {
 231                 /* call <DISP> */
 232                 gint64 disp = (guint8*)target - (guint8*)code;
 233                 g_assert (amd64_is_imm32 (disp));
 234                 x86_patch (code, (unsigned char*)target);
 235         }
 236         else
 237                 x86_patch (code, (unsigned char*)target);
 238 }
 239
 240 void
 241 mono_amd64_patch (unsigned char* code, gpointer target)
 242 {
 243         amd64_patch (code, target);
 244 }
 245
 246 typedef enum {
 247         ArgInIReg,
 248         ArgInFloatSSEReg,
 249         ArgInDoubleSSEReg,
 250         ArgOnStack,
 251         ArgValuetypeInReg,
 252         ArgValuetypeAddrInIReg,
 253         ArgNone /* only in pair_storage */
 254 } ArgStorage;
 255
 256 typedef struct {
 257         gint16 offset;
 258         gint8  reg;
 259         ArgStorage storage;
 260
 261         /* Only if storage == ArgValuetypeInReg */
 262         ArgStorage pair_storage [2];
 263         gint8 pair_regs [2];
 264 } ArgInfo;
 265
 266 typedef struct {
 267         int nargs;
 268         guint32 stack_usage;
 269         guint32 reg_usage;
 270         guint32 freg_usage;
 271         gboolean need_stack_align;
 272         gboolean vtype_retaddr;
 273         /* The index of the vret arg in the argument list */
 274         int vret_arg_index;
 275         ArgInfo ret;
 276         ArgInfo sig_cookie;
 277         ArgInfo args [1];
 278 } CallInfo;
 279
 280 #define DEBUG(a) if (cfg->verbose_level > 1) a
 281
 282 #ifdef HOST_WIN32
 283 #define PARAM_REGS 4
 284
 285 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 286
 287 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 288 #else
 289 #define PARAM_REGS 6
 290
 291 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 292
 293  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 294 #endif
 295
 296 static void inline
 297 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 298 {
 299     ainfo->offset = *stack_size;
 300
 301     if (*gr >= PARAM_REGS) {
 302                 ainfo->storage = ArgOnStack;
 303                 (*stack_size) += sizeof (gpointer);
 304     }
 305     else {
 306                 ainfo->storage = ArgInIReg;
 307                 ainfo->reg = param_regs [*gr];
 308                 (*gr) ++;
 309     }
 310 }
 311
 312 #ifdef HOST_WIN32
 313 #define FLOAT_PARAM_REGS 4
 314 #else
 315 #define FLOAT_PARAM_REGS 8
 316 #endif
 317
 318 static void inline
 319 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 320 {
 321     ainfo->offset = *stack_size;
 322
 323     if (*gr >= FLOAT_PARAM_REGS) {
 324                 ainfo->storage = ArgOnStack;
 325                 (*stack_size) += sizeof (gpointer);
 326     }
 327     else {
 328                 /* A double register */
 329                 if (is_double)
 330                         ainfo->storage = ArgInDoubleSSEReg;
 331                 else
 332                         ainfo->storage = ArgInFloatSSEReg;
 333                 ainfo->reg = *gr;
 334                 (*gr) += 1;
 335     }
 336 }
 337
 338 typedef enum ArgumentClass {
 339         ARG_CLASS_NO_CLASS,
 340         ARG_CLASS_MEMORY,
 341         ARG_CLASS_INTEGER,
 342         ARG_CLASS_SSE
 343 } ArgumentClass;
 344
 345 static ArgumentClass
 346 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 347 {
 348         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 349         MonoType *ptype;
 350
 351         ptype = mini_type_get_underlying_type (NULL, type);
 352         switch (ptype->type) {
 353         case MONO_TYPE_BOOLEAN:
 354         case MONO_TYPE_CHAR:
 355         case MONO_TYPE_I1:
 356         case MONO_TYPE_U1:
 357         case MONO_TYPE_I2:
 358         case MONO_TYPE_U2:
 359         case MONO_TYPE_I4:
 360         case MONO_TYPE_U4:
 361         case MONO_TYPE_I:
 362         case MONO_TYPE_U:
 363         case MONO_TYPE_STRING:
 364         case MONO_TYPE_OBJECT:
 365         case MONO_TYPE_CLASS:
 366         case MONO_TYPE_SZARRAY:
 367         case MONO_TYPE_PTR:
 368         case MONO_TYPE_FNPTR:
 369         case MONO_TYPE_ARRAY:
 370         case MONO_TYPE_I8:
 371         case MONO_TYPE_U8:
 372                 class2 = ARG_CLASS_INTEGER;
 373                 break;
 374         case MONO_TYPE_R4:
 375         case MONO_TYPE_R8:
 376 #ifdef HOST_WIN32
 377                 class2 = ARG_CLASS_INTEGER;
 378 #else
 379                 class2 = ARG_CLASS_SSE;
 380 #endif
 381                 break;
 382
 383         case MONO_TYPE_TYPEDBYREF:
 384                 g_assert_not_reached ();
 385
 386         case MONO_TYPE_GENERICINST:
 387                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 388                         class2 = ARG_CLASS_INTEGER;
 389                         break;
 390                 }
 391                 /* fall through */
 392         case MONO_TYPE_VALUETYPE: {
 393                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 394                 int i;
 395
 396                 for (i = 0; i < info->num_fields; ++i) {
 397                         class2 = class1;
 398                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 399                 }
 400                 break;
 401         }
 402         default:
 403                 g_assert_not_reached ();
 404         }
 405
 406         /* Merge */
 407         if (class1 == class2)
 408                 ;
 409         else if (class1 == ARG_CLASS_NO_CLASS)
 410                 class1 = class2;
 411         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 412                 class1 = ARG_CLASS_MEMORY;
 413         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 414                 class1 = ARG_CLASS_INTEGER;
 415         else
 416                 class1 = ARG_CLASS_SSE;
 417
 418         return class1;
 419 }
 420
 421 static void
 422 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 423                            gboolean is_return,
 424                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 425 {
 426         guint32 size, quad, nquads, i;
 427         ArgumentClass args [2];
 428         MonoMarshalType *info = NULL;
 429         MonoClass *klass;
 430         MonoGenericSharingContext tmp_gsctx;
 431         gboolean pass_on_stack = FALSE;
 432
 433         /*
 434          * The gsctx currently contains no data, it is only used for checking whenever
 435          * open types are allowed, some callers like mono_arch_get_argument_info ()
 436          * don't pass it to us, so work around that.
 437          */
 438         if (!gsctx)
 439                 gsctx = &tmp_gsctx;
 440
 441         klass = mono_class_from_mono_type (type);
 442         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 443 #ifndef HOST_WIN32
 444         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 445                 /* We pass and return vtypes of size 8 in a register */
 446         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 447                 pass_on_stack = TRUE;
 448         }
 449 #else
 450         if (!sig->pinvoke) {
 451                 pass_on_stack = TRUE;
 452         }
 453 #endif
 454
 455         if (pass_on_stack) {
 456                 /* Allways pass in memory */
 457                 ainfo->offset = *stack_size;
 458                 *stack_size += ALIGN_TO (size, 8);
 459                 ainfo->storage = ArgOnStack;
 460
 461                 return;
 462         }
 463
 464         /* FIXME: Handle structs smaller than 8 bytes */
 465         //if ((size % 8) != 0)
 466         //      NOT_IMPLEMENTED;
 467
 468         if (size > 8)
 469                 nquads = 2;
 470         else
 471                 nquads = 1;
 472
 473         if (!sig->pinvoke) {
 474                 /* Always pass in 1 or 2 integer registers */
 475                 args [0] = ARG_CLASS_INTEGER;
 476                 args [1] = ARG_CLASS_INTEGER;
 477                 /* Only the simplest cases are supported */
 478                 if (is_return && nquads != 1) {
 479                         args [0] = ARG_CLASS_MEMORY;
 480                         args [1] = ARG_CLASS_MEMORY;
 481                 }
 482         } else {
 483                 /*
 484                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 485                  * The X87 and SSEUP stuff is left out since there are no such types in
 486                  * the CLR.
 487                  */
 488                 info = mono_marshal_load_type_info (klass);
 489                 g_assert (info);
 490
 491 #ifndef HOST_WIN32
 492                 if (info->native_size > 16) {
 493                         ainfo->offset = *stack_size;
 494                         *stack_size += ALIGN_TO (info->native_size, 8);
 495                         ainfo->storage = ArgOnStack;
 496
 497                         return;
 498                 }
 499 #else
 500                 switch (info->native_size) {
 501                 case 1: case 2: case 4: case 8:
 502                         break;
 503                 default:
 504                         if (is_return) {
 505                                 ainfo->storage = ArgOnStack;
 506                                 ainfo->offset = *stack_size;
 507                                 *stack_size += ALIGN_TO (info->native_size, 8);
 508                         }
 509                         else {
 510                                 ainfo->storage = ArgValuetypeAddrInIReg;
 511
 512                                 if (*gr < PARAM_REGS) {
 513                                         ainfo->pair_storage [0] = ArgInIReg;
 514                                         ainfo->pair_regs [0] = param_regs [*gr];
 515                                         (*gr) ++;
 516                                 }
 517                                 else {
 518                                         ainfo->pair_storage [0] = ArgOnStack;
 519                                         ainfo->offset = *stack_size;
 520                                         *stack_size += 8;
 521                                 }
 522                         }
 523
 524                         return;
 525                 }
 526 #endif
 527
 528                 args [0] = ARG_CLASS_NO_CLASS;
 529                 args [1] = ARG_CLASS_NO_CLASS;
 530                 for (quad = 0; quad < nquads; ++quad) {
 531                         int size;
 532                         guint32 align;
 533                         ArgumentClass class1;
 534
 535                         if (info->num_fields == 0)
 536                                 class1 = ARG_CLASS_MEMORY;
 537                         else
 538                                 class1 = ARG_CLASS_NO_CLASS;
 539                         for (i = 0; i < info->num_fields; ++i) {
 540                                 size = mono_marshal_type_size (info->fields [i].field->type,
 541                                                                                            info->fields [i].mspec,
 542                                                                                            &align, TRUE, klass->unicode);
 543                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 544                                         /* Unaligned field */
 545                                         NOT_IMPLEMENTED;
 546                                 }
 547
 548                                 /* Skip fields in other quad */
 549                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 550                                         continue;
 551                                 if ((quad == 1) && (info->fields [i].offset < 8))
 552                                         continue;
 553
 554                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 555                         }
 556                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 557                         args [quad] = class1;
 558                 }
 559         }
 560
 561         /* Post merger cleanup */
 562         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 563                 args [0] = args [1] = ARG_CLASS_MEMORY;
 564
 565         /* Allocate registers */
 566         {
 567                 int orig_gr = *gr;
 568                 int orig_fr = *fr;
 569
 570                 ainfo->storage = ArgValuetypeInReg;
 571                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 572                 for (quad = 0; quad < nquads; ++quad) {
 573                         switch (args [quad]) {
 574                         case ARG_CLASS_INTEGER:
 575                                 if (*gr >= PARAM_REGS)
 576                                         args [quad] = ARG_CLASS_MEMORY;
 577                                 else {
 578                                         ainfo->pair_storage [quad] = ArgInIReg;
 579                                         if (is_return)
 580                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 581                                         else
 582                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 583                                         (*gr) ++;
 584                                 }
 585                                 break;
 586                         case ARG_CLASS_SSE:
 587                                 if (*fr >= FLOAT_PARAM_REGS)
 588                                         args [quad] = ARG_CLASS_MEMORY;
 589                                 else {
 590                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 591                                         ainfo->pair_regs [quad] = *fr;
 592                                         (*fr) ++;
 593                                 }
 594                                 break;
 595                         case ARG_CLASS_MEMORY:
 596                                 break;
 597                         default:
 598                                 g_assert_not_reached ();
 599                         }
 600                 }
 601
 602                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 603                         /* Revert possible register assignments */
 604                         *gr = orig_gr;
 605                         *fr = orig_fr;
 606
 607                         ainfo->offset = *stack_size;
 608                         if (sig->pinvoke)
 609                                 *stack_size += ALIGN_TO (info->native_size, 8);
 610                         else
 611                                 *stack_size += nquads * sizeof (gpointer);
 612                         ainfo->storage = ArgOnStack;
 613                 }
 614         }
 615 }
 616
 617 /*
 618  * get_call_info:
 619  *
 620  *  Obtain information about a call according to the calling convention.
 621  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 622  * Draft Version 0.23" document for more information.
 623  */
 624 static CallInfo*
 625 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 626 {
 627         guint32 i, gr, fr, pstart;
 628         MonoType *ret_type;
 629         int n = sig->hasthis + sig->param_count;
 630         guint32 stack_size = 0;
 631         CallInfo *cinfo;
 632         gboolean is_pinvoke = sig->pinvoke;
 633
 634         if (mp)
 635                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 636         else
 637                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 638
 639         cinfo->nargs = n;
 640
 641         gr = 0;
 642         fr = 0;
 643
 644         /* return value */
 645         {
 646                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 647                 switch (ret_type->type) {
 648                 case MONO_TYPE_BOOLEAN:
 649                 case MONO_TYPE_I1:
 650                 case MONO_TYPE_U1:
 651                 case MONO_TYPE_I2:
 652                 case MONO_TYPE_U2:
 653                 case MONO_TYPE_CHAR:
 654                 case MONO_TYPE_I4:
 655                 case MONO_TYPE_U4:
 656                 case MONO_TYPE_I:
 657                 case MONO_TYPE_U:
 658                 case MONO_TYPE_PTR:
 659                 case MONO_TYPE_FNPTR:
 660                 case MONO_TYPE_CLASS:
 661                 case MONO_TYPE_OBJECT:
 662                 case MONO_TYPE_SZARRAY:
 663                 case MONO_TYPE_ARRAY:
 664                 case MONO_TYPE_STRING:
 665                         cinfo->ret.storage = ArgInIReg;
 666                         cinfo->ret.reg = AMD64_RAX;
 667                         break;
 668                 case MONO_TYPE_U8:
 669                 case MONO_TYPE_I8:
 670                         cinfo->ret.storage = ArgInIReg;
 671                         cinfo->ret.reg = AMD64_RAX;
 672                         break;
 673                 case MONO_TYPE_R4:
 674                         cinfo->ret.storage = ArgInFloatSSEReg;
 675                         cinfo->ret.reg = AMD64_XMM0;
 676                         break;
 677                 case MONO_TYPE_R8:
 678                         cinfo->ret.storage = ArgInDoubleSSEReg;
 679                         cinfo->ret.reg = AMD64_XMM0;
 680                         break;
 681                 case MONO_TYPE_GENERICINST:
 682                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 683                                 cinfo->ret.storage = ArgInIReg;
 684                                 cinfo->ret.reg = AMD64_RAX;
 685                                 break;
 686                         }
 687                         /* fall through */
 688                 case MONO_TYPE_VALUETYPE: {
 689                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 690
 691                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 692                         if (cinfo->ret.storage == ArgOnStack) {
 693                                 cinfo->vtype_retaddr = TRUE;
 694                                 /* The caller passes the address where the value is stored */
 695                         }
 696                         break;
 697                 }
 698                 case MONO_TYPE_TYPEDBYREF:
 699                         /* Same as a valuetype with size 24 */
 700                         cinfo->vtype_retaddr = TRUE;
 701                         break;
 702                 case MONO_TYPE_VOID:
 703                         break;
 704                 default:
 705                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 706                 }
 707         }
 708
 709         pstart = 0;
 710         /*
 711          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 712          * the first argument, allowing 'this' to be always passed in the first arg reg.
 713          * Also do this if the first argument is a reference type, since virtual calls
 714          * are sometimes made using calli without sig->hasthis set, like in the delegate
 715          * invoke wrappers.
 716          */
 717         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
 718                 if (sig->hasthis) {
 719                         add_general (&gr, &stack_size, cinfo->args + 0);
 720                 } else {
 721                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 722                         pstart = 1;
 723                 }
 724                 add_general (&gr, &stack_size, &cinfo->ret);
 725                 cinfo->vret_arg_index = 1;
 726         } else {
 727                 /* this */
 728                 if (sig->hasthis)
 729                         add_general (&gr, &stack_size, cinfo->args + 0);
 730
 731                 if (cinfo->vtype_retaddr)
 732                         add_general (&gr, &stack_size, &cinfo->ret);
 733         }
 734
 735         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 736                 gr = PARAM_REGS;
 737                 fr = FLOAT_PARAM_REGS;
 738
 739                 /* Emit the signature cookie just before the implicit arguments */
 740                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 741         }
 742
 743         for (i = pstart; i < sig->param_count; ++i) {
 744                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 745                 MonoType *ptype;
 746
 747 #ifdef HOST_WIN32
 748                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 749                 if (gr > fr)
 750                         fr = gr;
 751                 else if (fr > gr)
 752                         gr = fr;
 753 #endif
 754
 755                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 756                         /* We allways pass the sig cookie on the stack for simplicity */
 757                         /*
 758                          * Prevent implicit arguments + the sig cookie from being passed
 759                          * in registers.
 760                          */
 761                         gr = PARAM_REGS;
 762                         fr = FLOAT_PARAM_REGS;
 763
 764                         /* Emit the signature cookie just before the implicit arguments */
 765                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 766                 }
 767
 768                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 769                 switch (ptype->type) {
 770                 case MONO_TYPE_BOOLEAN:
 771                 case MONO_TYPE_I1:
 772                 case MONO_TYPE_U1:
 773                         add_general (&gr, &stack_size, ainfo);
 774                         break;
 775                 case MONO_TYPE_I2:
 776                 case MONO_TYPE_U2:
 777                 case MONO_TYPE_CHAR:
 778                         add_general (&gr, &stack_size, ainfo);
 779                         break;
 780                 case MONO_TYPE_I4:
 781                 case MONO_TYPE_U4:
 782                         add_general (&gr, &stack_size, ainfo);
 783                         break;
 784                 case MONO_TYPE_I:
 785                 case MONO_TYPE_U:
 786                 case MONO_TYPE_PTR:
 787                 case MONO_TYPE_FNPTR:
 788                 case MONO_TYPE_CLASS:
 789                 case MONO_TYPE_OBJECT:
 790                 case MONO_TYPE_STRING:
 791                 case MONO_TYPE_SZARRAY:
 792                 case MONO_TYPE_ARRAY:
 793                         add_general (&gr, &stack_size, ainfo);
 794                         break;
 795                 case MONO_TYPE_GENERICINST:
 796                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 797                                 add_general (&gr, &stack_size, ainfo);
 798                                 break;
 799                         }
 800                         /* fall through */
 801                 case MONO_TYPE_VALUETYPE:
 802                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 803                         break;
 804                 case MONO_TYPE_TYPEDBYREF:
 805 #ifdef HOST_WIN32
 806                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 807 #else
 808                         stack_size += sizeof (MonoTypedRef);
 809                         ainfo->storage = ArgOnStack;
 810 #endif
 811                         break;
 812                 case MONO_TYPE_U8:
 813                 case MONO_TYPE_I8:
 814                         add_general (&gr, &stack_size, ainfo);
 815                         break;
 816                 case MONO_TYPE_R4:
 817                         add_float (&fr, &stack_size, ainfo, FALSE);
 818                         break;
 819                 case MONO_TYPE_R8:
 820                         add_float (&fr, &stack_size, ainfo, TRUE);
 821                         break;
 822                 default:
 823                         g_assert_not_reached ();
 824                 }
 825         }
 826
 827         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 828                 gr = PARAM_REGS;
 829                 fr = FLOAT_PARAM_REGS;
 830
 831                 /* Emit the signature cookie just before the implicit arguments */
 832                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 833         }
 834
 835 #ifdef HOST_WIN32
 836         // There always is 32 bytes reserved on the stack when calling on Winx64
 837         stack_size += 0x20;
 838 #endif
 839
 840         if (stack_size & 0x8) {
 841                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 842                 cinfo->need_stack_align = TRUE;
 843                 stack_size += 8;
 844         }
 845
 846         cinfo->stack_usage = stack_size;
 847         cinfo->reg_usage = gr;
 848         cinfo->freg_usage = fr;
 849         return cinfo;
 850 }
 851
 852 /*
 853  * mono_arch_get_argument_info:
 854  * @csig:  a method signature
 855  * @param_count: the number of parameters to consider
 856  * @arg_info: an array to store the result infos
 857  *
 858  * Gathers information on parameters such as size, alignment and
 859  * padding. arg_info should be large enought to hold param_count + 1 entries.
 860  *
 861  * Returns the size of the argument area on the stack.
 862  */
 863 int
 864 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 865 {
 866         int k;
 867         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
 868         guint32 args_size = cinfo->stack_usage;
 869
 870         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 871         if (csig->hasthis) {
 872                 arg_info [0].offset = 0;
 873         }
 874
 875         for (k = 0; k < param_count; k++) {
 876                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 877                 /* FIXME: */
 878                 arg_info [k + 1].size = 0;
 879         }
 880
 881         g_free (cinfo);
 882
 883         return args_size;
 884 }
 885
 886 gboolean
 887 mono_amd64_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
 888 {
 889         CallInfo *c1, *c2;
 890         gboolean res;
 891
 892         c1 = get_call_info (NULL, NULL, caller_sig);
 893         c2 = get_call_info (NULL, NULL, callee_sig);
 894         res = c1->stack_usage >= c2->stack_usage;
 895         if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
 896                 /* An address on the callee's stack is passed as the first argument */
 897                 res = FALSE;
 898
 899         g_free (c1);
 900         g_free (c2);
 901
 902         return res;
 903 }
 904
 905 static int
 906 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 907 {
 908 #ifndef _MSC_VER
 909         __asm__ __volatile__ ("cpuid"
 910                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 911                 : "a" (id));
 912 #else
 913         int info[4];
 914         __cpuid(info, id);
 915         *p_eax = info[0];
 916         *p_ebx = info[1];
 917         *p_ecx = info[2];
 918         *p_edx = info[3];
 919 #endif
 920         return 1;
 921 }
 922
 923 /*
 924  * Initialize the cpu to execute managed code.
 925  */
 926 void
 927 mono_arch_cpu_init (void)
 928 {
 929 #ifndef _MSC_VER
 930         guint16 fpcw;
 931
 932         /* spec compliance requires running with double precision */
 933         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 934         fpcw &= ~X86_FPCW_PRECC_MASK;
 935         fpcw |= X86_FPCW_PREC_DOUBLE;
 936         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 937         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 938 #else
 939         /* TODO: This is crashing on Win64 right now.
 940         * _control87 (_PC_53, MCW_PC);
 941         */
 942 #endif
 943 }
 944
 945 /*
 946  * Initialize architecture specific code.
 947  */
 948 void
 949 mono_arch_init (void)
 950 {
 951         int flags;
 952
 953         InitializeCriticalSection (&mini_arch_mutex);
 954
 955 #ifdef MONO_ARCH_NOMAP32BIT
 956         flags = MONO_MMAP_READ;
 957         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
 958         breakpoint_size = 13;
 959         breakpoint_fault_size = 3;
 960         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
 961         single_step_fault_size = 5;
 962 #else
 963         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
 964         /* amd64_mov_reg_mem () */
 965         breakpoint_size = 8;
 966         breakpoint_fault_size = 8;
 967         single_step_fault_size = 8;
 968 #endif
 969
 970         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 971         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 972         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 973
 974         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
 975         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
 976         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
 977 }
 978
 979 /*
 980  * Cleanup architecture specific code.
 981  */
 982 void
 983 mono_arch_cleanup (void)
 984 {
 985         DeleteCriticalSection (&mini_arch_mutex);
 986 }
 987
 988 /*
 989  * This function returns the optimizations supported on this cpu.
 990  */
 991 guint32
 992 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 993 {
 994         int eax, ebx, ecx, edx;
 995         guint32 opts = 0;
 996
 997         *exclude_mask = 0;
 998         /* Feature Flags function, flags returned in EDX. */
 999         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1000                 if (edx & (1 << 15)) {
1001                         opts |= MONO_OPT_CMOV;
1002                         if (edx & 1)
1003                                 opts |= MONO_OPT_FCMOV;
1004                         else
1005                                 *exclude_mask |= MONO_OPT_FCMOV;
1006                 } else
1007                         *exclude_mask |= MONO_OPT_CMOV;
1008         }
1009
1010         return opts;
1011 }
1012
1013 /*
1014  * This function test for all SSE functions supported.
1015  *
1016  * Returns a bitmask corresponding to all supported versions.
1017  *
1018  */
1019 guint32
1020 mono_arch_cpu_enumerate_simd_versions (void)
1021 {
1022         int eax, ebx, ecx, edx;
1023         guint32 sse_opts = 0;
1024
1025         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1026                 if (edx & (1 << 25))
1027                         sse_opts |= SIMD_VERSION_SSE1;
1028                 if (edx & (1 << 26))
1029                         sse_opts |= SIMD_VERSION_SSE2;
1030                 if (ecx & (1 << 0))
1031                         sse_opts |= SIMD_VERSION_SSE3;
1032                 if (ecx & (1 << 9))
1033                         sse_opts |= SIMD_VERSION_SSSE3;
1034                 if (ecx & (1 << 19))
1035                         sse_opts |= SIMD_VERSION_SSE41;
1036                 if (ecx & (1 << 20))
1037                         sse_opts |= SIMD_VERSION_SSE42;
1038         }
1039
1040         /* Yes, all this needs to be done to check for sse4a.
1041            See: "Amd: CPUID Specification"
1042          */
1043         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1044                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1045                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1046                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1047                         if (ecx & (1 << 6))
1048                                 sse_opts |= SIMD_VERSION_SSE4a;
1049                 }
1050         }
1051
1052         return sse_opts;
1053 }
1054
1055 #ifndef DISABLE_JIT
1056
1057 GList *
1058 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1059 {
1060         GList *vars = NULL;
1061         int i;
1062
1063         for (i = 0; i < cfg->num_varinfo; i++) {
1064                 MonoInst *ins = cfg->varinfo [i];
1065                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1066
1067                 /* unused vars */
1068                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1069                         continue;
1070
1071                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1072                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1073                         continue;
1074
1075                 if (mono_is_regsize_var (ins->inst_vtype)) {
1076                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1077                         g_assert (i == vmv->idx);
1078                         vars = g_list_prepend (vars, vmv);
1079                 }
1080         }
1081
1082         vars = mono_varlist_sort (cfg, vars, 0);
1083
1084         return vars;
1085 }
1086
1087 /**
1088  * mono_arch_compute_omit_fp:
1089  *
1090  *   Determine whenever the frame pointer can be eliminated.
1091  */
1092 static void
1093 mono_arch_compute_omit_fp (MonoCompile *cfg)
1094 {
1095         MonoMethodSignature *sig;
1096         MonoMethodHeader *header;
1097         int i, locals_size;
1098         CallInfo *cinfo;
1099
1100         if (cfg->arch.omit_fp_computed)
1101                 return;
1102
1103         header = cfg->header;
1104
1105         sig = mono_method_signature (cfg->method);
1106
1107         if (!cfg->arch.cinfo)
1108                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1109         cinfo = cfg->arch.cinfo;
1110
1111         /*
1112          * FIXME: Remove some of the restrictions.
1113          */
1114         cfg->arch.omit_fp = TRUE;
1115         cfg->arch.omit_fp_computed = TRUE;
1116
1117         if (cfg->disable_omit_fp)
1118                 cfg->arch.omit_fp = FALSE;
1119
1120         if (!debug_omit_fp ())
1121                 cfg->arch.omit_fp = FALSE;
1122         /*
1123         if (cfg->method->save_lmf)
1124                 cfg->arch.omit_fp = FALSE;
1125         */
1126         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1127                 cfg->arch.omit_fp = FALSE;
1128         if (header->num_clauses)
1129                 cfg->arch.omit_fp = FALSE;
1130         if (cfg->param_area)
1131                 cfg->arch.omit_fp = FALSE;
1132         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1133                 cfg->arch.omit_fp = FALSE;
1134         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1135                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1136                 cfg->arch.omit_fp = FALSE;
1137         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1138                 ArgInfo *ainfo = &cinfo->args [i];
1139
1140                 if (ainfo->storage == ArgOnStack) {
1141                         /*
1142                          * The stack offset can only be determined when the frame
1143                          * size is known.
1144                          */
1145                         cfg->arch.omit_fp = FALSE;
1146                 }
1147         }
1148
1149         locals_size = 0;
1150         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1151                 MonoInst *ins = cfg->varinfo [i];
1152                 int ialign;
1153
1154                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1155         }
1156 }
1157
1158 GList *
1159 mono_arch_get_global_int_regs (MonoCompile *cfg)
1160 {
1161         GList *regs = NULL;
1162
1163         mono_arch_compute_omit_fp (cfg);
1164
1165         if (cfg->globalra) {
1166                 if (cfg->arch.omit_fp)
1167                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1168
1169                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1170                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1171                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1172                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1173                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1174
1175                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1176                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1177                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1178                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1179                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1180                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1181                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1182                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1183         } else {
1184                 if (cfg->arch.omit_fp)
1185                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1186
1187                 /* We use the callee saved registers for global allocation */
1188                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1189                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1190                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1191                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1192                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1193 #ifdef HOST_WIN32
1194                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1195                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1196 #endif
1197         }
1198
1199         return regs;
1200 }
1201
1202 GList*
1203 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1204 {
1205         GList *regs = NULL;
1206         int i;
1207
1208         /* All XMM registers */
1209         for (i = 0; i < 16; ++i)
1210                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1211
1212         return regs;
1213 }
1214
1215 GList*
1216 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1217 {
1218         static GList *r = NULL;
1219
1220         if (r == NULL) {
1221                 GList *regs = NULL;
1222
1223                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1224                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1225                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1226                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1227                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1228                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1229
1230                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1231                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1232                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1233                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1234                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1235                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1236                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1237                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1238
1239                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1240         }
1241
1242         return r;
1243 }
1244
1245 GList*
1246 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1247 {
1248         int i;
1249         static GList *r = NULL;
1250
1251         if (r == NULL) {
1252                 GList *regs = NULL;
1253
1254                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1255                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1256
1257                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1258         }
1259
1260         return r;
1261 }
1262
1263 /*
1264  * mono_arch_regalloc_cost:
1265  *
1266  *  Return the cost, in number of memory references, of the action of
1267  * allocating the variable VMV into a register during global register
1268  * allocation.
1269  */
1270 guint32
1271 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1272 {
1273         MonoInst *ins = cfg->varinfo [vmv->idx];
1274
1275         if (cfg->method->save_lmf)
1276                 /* The register is already saved */
1277                 /* substract 1 for the invisible store in the prolog */
1278                 return (ins->opcode == OP_ARG) ? 0 : 1;
1279         else
1280                 /* push+pop */
1281                 return (ins->opcode == OP_ARG) ? 1 : 2;
1282 }
1283
1284 /*
1285  * mono_arch_fill_argument_info:
1286  *
1287  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1288  * of the method.
1289  */
1290 void
1291 mono_arch_fill_argument_info (MonoCompile *cfg)
1292 {
1293         MonoMethodSignature *sig;
1294         MonoMethodHeader *header;
1295         MonoInst *ins;
1296         int i;
1297         CallInfo *cinfo;
1298
1299         header = cfg->header;
1300
1301         sig = mono_method_signature (cfg->method);
1302
1303         cinfo = cfg->arch.cinfo;
1304
1305         /*
1306          * Contrary to mono_arch_allocate_vars (), the information should describe
1307          * where the arguments are at the beginning of the method, not where they can be
1308          * accessed during the execution of the method. The later makes no sense for the
1309          * global register allocator, since a variable can be in more than one location.
1310          */
1311         if (sig->ret->type != MONO_TYPE_VOID) {
1312                 switch (cinfo->ret.storage) {
1313                 case ArgInIReg:
1314                 case ArgInFloatSSEReg:
1315                 case ArgInDoubleSSEReg:
1316                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1317                                 cfg->vret_addr->opcode = OP_REGVAR;
1318                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1319                         }
1320                         else {
1321                                 cfg->ret->opcode = OP_REGVAR;
1322                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1323                         }
1324                         break;
1325                 case ArgValuetypeInReg:
1326                         cfg->ret->opcode = OP_REGOFFSET;
1327                         cfg->ret->inst_basereg = -1;
1328                         cfg->ret->inst_offset = -1;
1329                         break;
1330                 default:
1331                         g_assert_not_reached ();
1332                 }
1333         }
1334
1335         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1336                 ArgInfo *ainfo = &cinfo->args [i];
1337                 MonoType *arg_type;
1338
1339                 ins = cfg->args [i];
1340
1341                 if (sig->hasthis && (i == 0))
1342                         arg_type = &mono_defaults.object_class->byval_arg;
1343                 else
1344                         arg_type = sig->params [i - sig->hasthis];
1345
1346                 switch (ainfo->storage) {
1347                 case ArgInIReg:
1348                 case ArgInFloatSSEReg:
1349                 case ArgInDoubleSSEReg:
1350                         ins->opcode = OP_REGVAR;
1351                         ins->inst_c0 = ainfo->reg;
1352                         break;
1353                 case ArgOnStack:
1354                         ins->opcode = OP_REGOFFSET;
1355                         ins->inst_basereg = -1;
1356                         ins->inst_offset = -1;
1357                         break;
1358                 case ArgValuetypeInReg:
1359                         /* Dummy */
1360                         ins->opcode = OP_NOP;
1361                         break;
1362                 default:
1363                         g_assert_not_reached ();
1364                 }
1365         }
1366 }
1367
1368 void
1369 mono_arch_allocate_vars (MonoCompile *cfg)
1370 {
1371         MonoMethodSignature *sig;
1372         MonoMethodHeader *header;
1373         MonoInst *ins;
1374         int i, offset;
1375         guint32 locals_stack_size, locals_stack_align;
1376         gint32 *offsets;
1377         CallInfo *cinfo;
1378
1379         header = cfg->header;
1380
1381         sig = mono_method_signature (cfg->method);
1382
1383         cinfo = cfg->arch.cinfo;
1384
1385         mono_arch_compute_omit_fp (cfg);
1386
1387         /*
1388          * We use the ABI calling conventions for managed code as well.
1389          * Exception: valuetypes are only sometimes passed or returned in registers.
1390          */
1391
1392         /*
1393          * The stack looks like this:
1394          * <incoming arguments passed on the stack>
1395          * <return value>
1396          * <lmf/caller saved registers>
1397          * <locals>
1398          * <spill area>
1399          * <localloc area>  -> grows dynamically
1400          * <params area>
1401          */
1402
1403         if (cfg->arch.omit_fp) {
1404                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1405                 cfg->frame_reg = AMD64_RSP;
1406                 offset = 0;
1407         } else {
1408                 /* Locals are allocated backwards from %fp */
1409                 cfg->frame_reg = AMD64_RBP;
1410                 offset = 0;
1411         }
1412
1413         if (cfg->method->save_lmf) {
1414                 /* Reserve stack space for saving LMF */
1415                 if (cfg->arch.omit_fp) {
1416                         cfg->arch.lmf_offset = offset;
1417                         offset += sizeof (MonoLMF);
1418                 }
1419                 else {
1420                         offset += sizeof (MonoLMF);
1421                         cfg->arch.lmf_offset = -offset;
1422                 }
1423         } else {
1424                 if (cfg->arch.omit_fp)
1425                         cfg->arch.reg_save_area_offset = offset;
1426                 /* Reserve space for caller saved registers */
1427                 for (i = 0; i < AMD64_NREG; ++i)
1428                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1429                                 offset += sizeof (gpointer);
1430                         }
1431         }
1432
1433         if (sig->ret->type != MONO_TYPE_VOID) {
1434                 switch (cinfo->ret.storage) {
1435                 case ArgInIReg:
1436                 case ArgInFloatSSEReg:
1437                 case ArgInDoubleSSEReg:
1438                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1439                                 if (cfg->globalra) {
1440                                         cfg->vret_addr->opcode = OP_REGVAR;
1441                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1442                                 } else {
1443                                         /* The register is volatile */
1444                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1445                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1446                                         if (cfg->arch.omit_fp) {
1447                                                 cfg->vret_addr->inst_offset = offset;
1448                                                 offset += 8;
1449                                         } else {
1450                                                 offset += 8;
1451                                                 cfg->vret_addr->inst_offset = -offset;
1452                                         }
1453                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1454                                                 printf ("vret_addr =");
1455                                                 mono_print_ins (cfg->vret_addr);
1456                                         }
1457                                 }
1458                         }
1459                         else {
1460                                 cfg->ret->opcode = OP_REGVAR;
1461                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1462                         }
1463                         break;
1464                 case ArgValuetypeInReg:
1465                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1466                         cfg->ret->opcode = OP_REGOFFSET;
1467                         cfg->ret->inst_basereg = cfg->frame_reg;
1468                         if (cfg->arch.omit_fp) {
1469                                 cfg->ret->inst_offset = offset;
1470                                 offset += 16;
1471                         } else {
1472                                 offset += 16;
1473                                 cfg->ret->inst_offset = - offset;
1474                         }
1475                         break;
1476                 default:
1477                         g_assert_not_reached ();
1478                 }
1479                 if (!cfg->globalra)
1480                         cfg->ret->dreg = cfg->ret->inst_c0;
1481         }
1482
1483         /* Allocate locals */
1484         if (!cfg->globalra) {
1485                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1486                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1487                         char *mname = mono_method_full_name (cfg->method, TRUE);
1488                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1489                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1490                         g_free (mname);
1491                         return;
1492                 }
1493
1494                 if (locals_stack_align) {
1495                         offset += (locals_stack_align - 1);
1496                         offset &= ~(locals_stack_align - 1);
1497                 }
1498                 if (cfg->arch.omit_fp) {
1499                         cfg->locals_min_stack_offset = offset;
1500                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1501                 } else {
1502                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1503                         cfg->locals_max_stack_offset = - offset;
1504                 }
1505
1506                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1507                         if (offsets [i] != -1) {
1508                                 MonoInst *ins = cfg->varinfo [i];
1509                                 ins->opcode = OP_REGOFFSET;
1510                                 ins->inst_basereg = cfg->frame_reg;
1511                                 if (cfg->arch.omit_fp)
1512                                         ins->inst_offset = (offset + offsets [i]);
1513                                 else
1514                                         ins->inst_offset = - (offset + offsets [i]);
1515                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1516                         }
1517                 }
1518                 offset += locals_stack_size;
1519         }
1520
1521         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1522                 g_assert (!cfg->arch.omit_fp);
1523                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1524                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1525         }
1526
1527         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1528                 ins = cfg->args [i];
1529                 if (ins->opcode != OP_REGVAR) {
1530                         ArgInfo *ainfo = &cinfo->args [i];
1531                         gboolean inreg = TRUE;
1532                         MonoType *arg_type;
1533
1534                         if (sig->hasthis && (i == 0))
1535                                 arg_type = &mono_defaults.object_class->byval_arg;
1536                         else
1537                                 arg_type = sig->params [i - sig->hasthis];
1538
1539                         if (cfg->globalra) {
1540                                 /* The new allocator needs info about the original locations of the arguments */
1541                                 switch (ainfo->storage) {
1542                                 case ArgInIReg:
1543                                 case ArgInFloatSSEReg:
1544                                 case ArgInDoubleSSEReg:
1545                                         ins->opcode = OP_REGVAR;
1546                                         ins->inst_c0 = ainfo->reg;
1547                                         break;
1548                                 case ArgOnStack:
1549                                         g_assert (!cfg->arch.omit_fp);
1550                                         ins->opcode = OP_REGOFFSET;
1551                                         ins->inst_basereg = cfg->frame_reg;
1552                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1553                                         break;
1554                                 case ArgValuetypeInReg:
1555                                         ins->opcode = OP_REGOFFSET;
1556                                         ins->inst_basereg = cfg->frame_reg;
1557                                         /* These arguments are saved to the stack in the prolog */
1558                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1559                                         if (cfg->arch.omit_fp) {
1560                                                 ins->inst_offset = offset;
1561                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1562                                         } else {
1563                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1564                                                 ins->inst_offset = - offset;
1565                                         }
1566                                         break;
1567                                 default:
1568                                         g_assert_not_reached ();
1569                                 }
1570
1571                                 continue;
1572                         }
1573
1574                         /* FIXME: Allocate volatile arguments to registers */
1575                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1576                                 inreg = FALSE;
1577
1578                         /*
1579                          * Under AMD64, all registers used to pass arguments to functions
1580                          * are volatile across calls.
1581                          * FIXME: Optimize this.
1582                          */
1583                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1584                                 inreg = FALSE;
1585
1586                         ins->opcode = OP_REGOFFSET;
1587
1588                         switch (ainfo->storage) {
1589                         case ArgInIReg:
1590                         case ArgInFloatSSEReg:
1591                         case ArgInDoubleSSEReg:
1592                                 if (inreg) {
1593                                         ins->opcode = OP_REGVAR;
1594                                         ins->dreg = ainfo->reg;
1595                                 }
1596                                 break;
1597                         case ArgOnStack:
1598                                 g_assert (!cfg->arch.omit_fp);
1599                                 ins->opcode = OP_REGOFFSET;
1600                                 ins->inst_basereg = cfg->frame_reg;
1601                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1602                                 break;
1603                         case ArgValuetypeInReg:
1604                                 break;
1605                         case ArgValuetypeAddrInIReg: {
1606                                 MonoInst *indir;
1607                                 g_assert (!cfg->arch.omit_fp);
1608
1609                                 MONO_INST_NEW (cfg, indir, 0);
1610                                 indir->opcode = OP_REGOFFSET;
1611                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1612                                         indir->inst_basereg = cfg->frame_reg;
1613                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1614                                         offset += (sizeof (gpointer));
1615                                         indir->inst_offset = - offset;
1616                                 }
1617                                 else {
1618                                         indir->inst_basereg = cfg->frame_reg;
1619                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1620                                 }
1621
1622                                 ins->opcode = OP_VTARG_ADDR;
1623                                 ins->inst_left = indir;
1624
1625                                 break;
1626                         }
1627                         default:
1628                                 NOT_IMPLEMENTED;
1629                         }
1630
1631                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1632                                 ins->opcode = OP_REGOFFSET;
1633                                 ins->inst_basereg = cfg->frame_reg;
1634                                 /* These arguments are saved to the stack in the prolog */
1635                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1636                                 if (cfg->arch.omit_fp) {
1637                                         ins->inst_offset = offset;
1638                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1639                                         // Arguments are yet supported by the stack map creation code
1640                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1641                                 } else {
1642                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1643                                         ins->inst_offset = - offset;
1644                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1645                                 }
1646                         }
1647                 }
1648         }
1649
1650         cfg->stack_offset = offset;
1651 }
1652
1653 void
1654 mono_arch_create_vars (MonoCompile *cfg)
1655 {
1656         MonoMethodSignature *sig;
1657         CallInfo *cinfo;
1658
1659         sig = mono_method_signature (cfg->method);
1660
1661         if (!cfg->arch.cinfo)
1662                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1663         cinfo = cfg->arch.cinfo;
1664
1665         if (cinfo->ret.storage == ArgValuetypeInReg)
1666                 cfg->ret_var_is_local = TRUE;
1667
1668         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1669                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1670                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1671                         printf ("vret_addr = ");
1672                         mono_print_ins (cfg->vret_addr);
1673                 }
1674         }
1675
1676         if (cfg->gen_seq_points) {
1677                 MonoInst *ins;
1678
1679             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1680                 ins->flags |= MONO_INST_VOLATILE;
1681                 cfg->arch.ss_trigger_page_var = ins;
1682         }
1683
1684 #ifdef MONO_AMD64_NO_PUSHES
1685         /*
1686          * When this is set, we pass arguments on the stack by moves, and by allocating
1687          * a bigger stack frame, instead of pushes.
1688          * Pushes complicate exception handling because the arguments on the stack have
1689          * to be popped each time a frame is unwound. They also make fp elimination
1690          * impossible.
1691          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1692          * on a new frame which doesn't include a param area.
1693          */
1694         cfg->arch.no_pushes = TRUE;
1695 #endif
1696 }
1697
1698 static void
1699 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1700 {
1701         MonoInst *ins;
1702
1703         switch (storage) {
1704         case ArgInIReg:
1705                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1706                 ins->dreg = mono_alloc_ireg (cfg);
1707                 ins->sreg1 = tree->dreg;
1708                 MONO_ADD_INS (cfg->cbb, ins);
1709                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1710                 break;
1711         case ArgInFloatSSEReg:
1712                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1713                 ins->dreg = mono_alloc_freg (cfg);
1714                 ins->sreg1 = tree->dreg;
1715                 MONO_ADD_INS (cfg->cbb, ins);
1716
1717                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1718                 break;
1719         case ArgInDoubleSSEReg:
1720                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1721                 ins->dreg = mono_alloc_freg (cfg);
1722                 ins->sreg1 = tree->dreg;
1723                 MONO_ADD_INS (cfg->cbb, ins);
1724
1725                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1726
1727                 break;
1728         default:
1729                 g_assert_not_reached ();
1730         }
1731 }
1732
1733 static int
1734 arg_storage_to_load_membase (ArgStorage storage)
1735 {
1736         switch (storage) {
1737         case ArgInIReg:
1738                 return OP_LOAD_MEMBASE;
1739         case ArgInDoubleSSEReg:
1740                 return OP_LOADR8_MEMBASE;
1741         case ArgInFloatSSEReg:
1742                 return OP_LOADR4_MEMBASE;
1743         default:
1744                 g_assert_not_reached ();
1745         }
1746
1747         return -1;
1748 }
1749
1750 static void
1751 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1752 {
1753         MonoInst *arg;
1754         MonoMethodSignature *tmp_sig;
1755         MonoInst *sig_arg;
1756
1757         if (call->tail_call)
1758                 NOT_IMPLEMENTED;
1759
1760         /* FIXME: Add support for signature tokens to AOT */
1761         cfg->disable_aot = TRUE;
1762
1763         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1764
1765         /*
1766          * mono_ArgIterator_Setup assumes the signature cookie is
1767          * passed first and all the arguments which were before it are
1768          * passed on the stack after the signature. So compensate by
1769          * passing a different signature.
1770          */
1771         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1772         tmp_sig->param_count -= call->signature->sentinelpos;
1773         tmp_sig->sentinelpos = 0;
1774         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1775
1776         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1777         sig_arg->dreg = mono_alloc_ireg (cfg);
1778         sig_arg->inst_p0 = tmp_sig;
1779         MONO_ADD_INS (cfg->cbb, sig_arg);
1780
1781         if (cfg->arch.no_pushes) {
1782                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1783         } else {
1784                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1785                 arg->sreg1 = sig_arg->dreg;
1786                 MONO_ADD_INS (cfg->cbb, arg);
1787         }
1788 }
1789
1790 static inline LLVMArgStorage
1791 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1792 {
1793         switch (storage) {
1794         case ArgInIReg:
1795                 return LLVMArgInIReg;
1796         case ArgNone:
1797                 return LLVMArgNone;
1798         default:
1799                 g_assert_not_reached ();
1800                 return LLVMArgNone;
1801         }
1802 }
1803
1804 #ifdef ENABLE_LLVM
1805 LLVMCallInfo*
1806 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1807 {
1808         int i, n;
1809         CallInfo *cinfo;
1810         ArgInfo *ainfo;
1811         int j;
1812         LLVMCallInfo *linfo;
1813         MonoType *t;
1814
1815         n = sig->param_count + sig->hasthis;
1816
1817         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1818
1819         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1820
1821         /*
1822          * LLVM always uses the native ABI while we use our own ABI, the
1823          * only difference is the handling of vtypes:
1824          * - we only pass/receive them in registers in some cases, and only
1825          *   in 1 or 2 integer registers.
1826          */
1827         if (cinfo->ret.storage == ArgValuetypeInReg) {
1828                 if (sig->pinvoke) {
1829                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1830                         cfg->disable_llvm = TRUE;
1831                         return linfo;
1832                 }
1833
1834                 linfo->ret.storage = LLVMArgVtypeInReg;
1835                 for (j = 0; j < 2; ++j)
1836                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1837         }
1838
1839         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1840                 /* Vtype returned using a hidden argument */
1841                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1842                 linfo->vret_arg_index = cinfo->vret_arg_index;
1843         }
1844
1845         for (i = 0; i < n; ++i) {
1846                 ainfo = cinfo->args + i;
1847
1848                 if (i >= sig->hasthis)
1849                         t = sig->params [i - sig->hasthis];
1850                 else
1851                         t = &mono_defaults.int_class->byval_arg;
1852
1853                 linfo->args [i].storage = LLVMArgNone;
1854
1855                 switch (ainfo->storage) {
1856                 case ArgInIReg:
1857                         linfo->args [i].storage = LLVMArgInIReg;
1858                         break;
1859                 case ArgInDoubleSSEReg:
1860                 case ArgInFloatSSEReg:
1861                         linfo->args [i].storage = LLVMArgInFPReg;
1862                         break;
1863                 case ArgOnStack:
1864                         if (MONO_TYPE_ISSTRUCT (t)) {
1865                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1866                         } else {
1867                                 linfo->args [i].storage = LLVMArgInIReg;
1868                                 if (!t->byref) {
1869                                         if (t->type == MONO_TYPE_R4)
1870                                                 linfo->args [i].storage = LLVMArgInFPReg;
1871                                         else if (t->type == MONO_TYPE_R8)
1872                                                 linfo->args [i].storage = LLVMArgInFPReg;
1873                                 }
1874                         }
1875                         break;
1876                 case ArgValuetypeInReg:
1877                         if (sig->pinvoke) {
1878                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1879                                 cfg->disable_llvm = TRUE;
1880                                 return linfo;
1881                         }
1882
1883                         linfo->args [i].storage = LLVMArgVtypeInReg;
1884                         for (j = 0; j < 2; ++j)
1885                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1886                         break;
1887                 default:
1888                         cfg->exception_message = g_strdup ("ainfo->storage");
1889                         cfg->disable_llvm = TRUE;
1890                         break;
1891                 }
1892         }
1893
1894         return linfo;
1895 }
1896 #endif
1897
1898 void
1899 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1900 {
1901         MonoInst *arg, *in;
1902         MonoMethodSignature *sig;
1903         int i, n, stack_size;
1904         CallInfo *cinfo;
1905         ArgInfo *ainfo;
1906
1907         stack_size = 0;
1908
1909         sig = call->signature;
1910         n = sig->param_count + sig->hasthis;
1911
1912         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1913
1914         if (COMPILE_LLVM (cfg)) {
1915                 /* We shouldn't be called in the llvm case */
1916                 cfg->disable_llvm = TRUE;
1917                 return;
1918         }
1919
1920         if (cinfo->need_stack_align) {
1921                 if (!cfg->arch.no_pushes)
1922                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1923         }
1924
1925         /*
1926          * Emit all arguments which are passed on the stack to prevent register
1927          * allocation problems.
1928          */
1929         if (cfg->arch.no_pushes) {
1930                 for (i = 0; i < n; ++i) {
1931                         MonoType *t;
1932                         ainfo = cinfo->args + i;
1933
1934                         in = call->args [i];
1935
1936                         if (sig->hasthis && i == 0)
1937                                 t = &mono_defaults.object_class->byval_arg;
1938                         else
1939                                 t = sig->params [i - sig->hasthis];
1940
1941                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1942                                 if (!t->byref) {
1943                                         if (t->type == MONO_TYPE_R4)
1944                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1945                                         else if (t->type == MONO_TYPE_R8)
1946                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1947                                         else
1948                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1949                                 } else {
1950                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1951                                 }
1952                         }
1953                 }
1954         }
1955
1956         /*
1957          * Emit all parameters passed in registers in non-reverse order for better readability
1958          * and to help the optimization in emit_prolog ().
1959          */
1960         for (i = 0; i < n; ++i) {
1961                 ainfo = cinfo->args + i;
1962
1963                 in = call->args [i];
1964
1965                 if (ainfo->storage == ArgInIReg)
1966                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1967         }
1968
1969         for (i = n - 1; i >= 0; --i) {
1970                 ainfo = cinfo->args + i;
1971
1972                 in = call->args [i];
1973
1974                 switch (ainfo->storage) {
1975                 case ArgInIReg:
1976                         /* Already done */
1977                         break;
1978                 case ArgInFloatSSEReg:
1979                 case ArgInDoubleSSEReg:
1980                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1981                         break;
1982                 case ArgOnStack:
1983                 case ArgValuetypeInReg:
1984                 case ArgValuetypeAddrInIReg:
1985                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1986                                 MonoInst *call_inst = (MonoInst*)call;
1987                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1988                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1989                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1990                                 guint32 align;
1991                                 guint32 size;
1992
1993                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1994                                         size = sizeof (MonoTypedRef);
1995                                         align = sizeof (gpointer);
1996                                 }
1997                                 else {
1998                                         if (sig->pinvoke)
1999                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2000                                         else {
2001                                                 /*
2002                                                  * Other backends use mono_type_stack_size (), but that
2003                                                  * aligns the size to 8, which is larger than the size of
2004                                                  * the source, leading to reads of invalid memory if the
2005                                                  * source is at the end of address space.
2006                                                  */
2007                                                 size = mono_class_value_size (in->klass, &align);
2008                                         }
2009                                 }
2010                                 g_assert (in->klass);
2011
2012                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2013                                         /* Avoid asserts in emit_memcpy () */
2014                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2015                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2016                                         /* Continue normally */
2017                                 }
2018
2019                                 if (size > 0) {
2020                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2021                                         arg->sreg1 = in->dreg;
2022                                         arg->klass = in->klass;
2023                                         arg->backend.size = size;
2024                                         arg->inst_p0 = call;
2025                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2026                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2027
2028                                         MONO_ADD_INS (cfg->cbb, arg);
2029                                 }
2030                         } else {
2031                                 if (cfg->arch.no_pushes) {
2032                                         /* Already done */
2033                                 } else {
2034                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2035                                         arg->sreg1 = in->dreg;
2036                                         if (!sig->params [i - sig->hasthis]->byref) {
2037                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2038                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2039                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2040                                                         arg->inst_destbasereg = X86_ESP;
2041                                                         arg->inst_offset = 0;
2042                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2043                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2044                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2045                                                         arg->inst_destbasereg = X86_ESP;
2046                                                         arg->inst_offset = 0;
2047                                                 }
2048                                         }
2049                                         MONO_ADD_INS (cfg->cbb, arg);
2050                                 }
2051                         }
2052                         break;
2053                 default:
2054                         g_assert_not_reached ();
2055                 }
2056
2057                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2058                         /* Emit the signature cookie just before the implicit arguments */
2059                         emit_sig_cookie (cfg, call, cinfo);
2060         }
2061
2062         /* Handle the case where there are no implicit arguments */
2063         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2064                 emit_sig_cookie (cfg, call, cinfo);
2065
2066         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2067                 MonoInst *vtarg;
2068
2069                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2070                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2071                                 /*
2072                                  * Tell the JIT to use a more efficient calling convention: call using
2073                                  * OP_CALL, compute the result location after the call, and save the
2074                                  * result there.
2075                                  */
2076                                 call->vret_in_reg = TRUE;
2077                                 /*
2078                                  * Nullify the instruction computing the vret addr to enable
2079                                  * future optimizations.
2080                                  */
2081                                 if (call->vret_var)
2082                                         NULLIFY_INS (call->vret_var);
2083                         } else {
2084                                 if (call->tail_call)
2085                                         NOT_IMPLEMENTED;
2086                                 /*
2087                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2088                                  * the stack. Push the address here, so the call instruction can
2089                                  * access it.
2090                                  */
2091                                 if (!cfg->arch.vret_addr_loc) {
2092                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2093                                         /* Prevent it from being register allocated or optimized away */
2094                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2095                                 }
2096
2097                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2098                         }
2099                 }
2100                 else {
2101                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2102                         vtarg->sreg1 = call->vret_var->dreg;
2103                         vtarg->dreg = mono_alloc_preg (cfg);
2104                         MONO_ADD_INS (cfg->cbb, vtarg);
2105
2106                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2107                 }
2108         }
2109
2110 #ifdef HOST_WIN32
2111         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2112                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2113         }
2114 #endif
2115
2116         if (cfg->method->save_lmf) {
2117                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2118                 MONO_ADD_INS (cfg->cbb, arg);
2119         }
2120
2121         call->stack_usage = cinfo->stack_usage;
2122 }
2123
2124 void
2125 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2126 {
2127         MonoInst *arg;
2128         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2129         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2130         int size = ins->backend.size;
2131
2132         if (ainfo->storage == ArgValuetypeInReg) {
2133                 MonoInst *load;
2134                 int part;
2135
2136                 for (part = 0; part < 2; ++part) {
2137                         if (ainfo->pair_storage [part] == ArgNone)
2138                                 continue;
2139
2140                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2141                         load->inst_basereg = src->dreg;
2142                         load->inst_offset = part * sizeof (gpointer);
2143
2144                         switch (ainfo->pair_storage [part]) {
2145                         case ArgInIReg:
2146                                 load->dreg = mono_alloc_ireg (cfg);
2147                                 break;
2148                         case ArgInDoubleSSEReg:
2149                         case ArgInFloatSSEReg:
2150                                 load->dreg = mono_alloc_freg (cfg);
2151                                 break;
2152                         default:
2153                                 g_assert_not_reached ();
2154                         }
2155                         MONO_ADD_INS (cfg->cbb, load);
2156
2157                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2158                 }
2159         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2160                 MonoInst *vtaddr, *load;
2161                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2162
2163                 g_assert (!cfg->arch.no_pushes);
2164
2165                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2166                 load->inst_p0 = vtaddr;
2167                 vtaddr->flags |= MONO_INST_INDIRECT;
2168                 load->type = STACK_MP;
2169                 load->klass = vtaddr->klass;
2170                 load->dreg = mono_alloc_ireg (cfg);
2171                 MONO_ADD_INS (cfg->cbb, load);
2172                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2173
2174                 if (ainfo->pair_storage [0] == ArgInIReg) {
2175                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2176                         arg->dreg = mono_alloc_ireg (cfg);
2177                         arg->sreg1 = load->dreg;
2178                         arg->inst_imm = 0;
2179                         MONO_ADD_INS (cfg->cbb, arg);
2180                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2181                 } else {
2182                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2183                         arg->sreg1 = load->dreg;
2184                         MONO_ADD_INS (cfg->cbb, arg);
2185                 }
2186         } else {
2187                 if (size == 8) {
2188                         if (cfg->arch.no_pushes) {
2189                                 int dreg = mono_alloc_ireg (cfg);
2190
2191                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2192                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2193                         } else {
2194                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2195                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2196                                 arg->inst_basereg = src->dreg;
2197                                 arg->inst_offset = 0;
2198                                 MONO_ADD_INS (cfg->cbb, arg);
2199                         }
2200                 } else if (size <= 40) {
2201                         if (cfg->arch.no_pushes) {
2202                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2203                         } else {
2204                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2205                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2206                         }
2207                 } else {
2208                         if (cfg->arch.no_pushes) {
2209                                 // FIXME: Code growth
2210                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2211                         } else {
2212                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2213                                 arg->inst_basereg = src->dreg;
2214                                 arg->inst_offset = 0;
2215                                 arg->inst_imm = size;
2216                                 MONO_ADD_INS (cfg->cbb, arg);
2217                         }
2218                 }
2219         }
2220 }
2221
2222 void
2223 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2224 {
2225         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2226
2227         if (ret->type == MONO_TYPE_R4) {
2228                 if (COMPILE_LLVM (cfg))
2229                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2230                 else
2231                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2232                 return;
2233         } else if (ret->type == MONO_TYPE_R8) {
2234                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2235                 return;
2236         }
2237
2238         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2239 }
2240
2241 #endif /* DISABLE_JIT */
2242
2243 #define EMIT_COND_BRANCH(ins,cond,sign) \
2244         if (ins->inst_true_bb->native_offset) { \
2245                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2246         } else { \
2247                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2248                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2249             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2250                         x86_branch8 (code, cond, 0, sign); \
2251                 else \
2252                         x86_branch32 (code, cond, 0, sign); \
2253 }
2254
2255 typedef struct {
2256         MonoMethodSignature *sig;
2257         CallInfo *cinfo;
2258 } ArchDynCallInfo;
2259
2260 typedef struct {
2261         mgreg_t regs [PARAM_REGS];
2262         mgreg_t res;
2263         guint8 *ret;
2264 } DynCallArgs;
2265
2266 static gboolean
2267 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2268 {
2269         int i;
2270
2271 #ifdef HOST_WIN32
2272         return FALSE;
2273 #endif
2274
2275         switch (cinfo->ret.storage) {
2276         case ArgNone:
2277         case ArgInIReg:
2278                 break;
2279         case ArgValuetypeInReg: {
2280                 ArgInfo *ainfo = &cinfo->ret;
2281
2282                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2283                         return FALSE;
2284                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2285                         return FALSE;
2286                 break;
2287         }
2288         default:
2289                 return FALSE;
2290         }
2291
2292         for (i = 0; i < cinfo->nargs; ++i) {
2293                 ArgInfo *ainfo = &cinfo->args [i];
2294                 switch (ainfo->storage) {
2295                 case ArgInIReg:
2296                         break;
2297                 case ArgValuetypeInReg:
2298                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2299                                 return FALSE;
2300                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2301                                 return FALSE;
2302                         break;
2303                 default:
2304                         return FALSE;
2305                 }
2306         }
2307
2308         return TRUE;
2309 }
2310
2311 /*
2312  * mono_arch_dyn_call_prepare:
2313  *
2314  *   Return a pointer to an arch-specific structure which contains information
2315  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2316  * supported for SIG.
2317  * This function is equivalent to ffi_prep_cif in libffi.
2318  */
2319 MonoDynCallInfo*
2320 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2321 {
2322         ArchDynCallInfo *info;
2323         CallInfo *cinfo;
2324
2325         cinfo = get_call_info (NULL, NULL, sig);
2326
2327         if (!dyn_call_supported (sig, cinfo)) {
2328                 g_free (cinfo);
2329                 return NULL;
2330         }
2331
2332         info = g_new0 (ArchDynCallInfo, 1);
2333         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2334         info->sig = sig;
2335         info->cinfo = cinfo;
2336
2337         return (MonoDynCallInfo*)info;
2338 }
2339
2340 /*
2341  * mono_arch_dyn_call_free:
2342  *
2343  *   Free a MonoDynCallInfo structure.
2344  */
2345 void
2346 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2347 {
2348         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2349
2350         g_free (ainfo->cinfo);
2351         g_free (ainfo);
2352 }
2353
2354 /*
2355  * mono_arch_get_start_dyn_call:
2356  *
2357  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2358  * store the result into BUF.
2359  * ARGS should be an array of pointers pointing to the arguments.
2360  * RET should point to a memory buffer large enought to hold the result of the
2361  * call.
2362  * This function should be as fast as possible, any work which does not depend
2363  * on the actual values of the arguments should be done in
2364  * mono_arch_dyn_call_prepare ().
2365  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2366  * libffi.
2367  */
2368 void
2369 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2370 {
2371         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2372         DynCallArgs *p = (DynCallArgs*)buf;
2373         int arg_index, greg, i, pindex;
2374         MonoMethodSignature *sig = dinfo->sig;
2375
2376         g_assert (buf_len >= sizeof (DynCallArgs));
2377
2378         p->res = 0;
2379         p->ret = ret;
2380
2381         arg_index = 0;
2382         greg = 0;
2383         pindex = 0;
2384
2385         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2386                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2387                 if (!sig->hasthis)
2388                         pindex = 1;
2389         }
2390
2391         if (dinfo->cinfo->vtype_retaddr)
2392                 p->regs [greg ++] = (mgreg_t)ret;
2393
2394         for (i = pindex; i < sig->param_count; i++) {
2395                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2396                 gpointer *arg = args [arg_index ++];
2397
2398                 if (t->byref) {
2399                         p->regs [greg ++] = (mgreg_t)*(arg);
2400                         continue;
2401                 }
2402
2403                 switch (t->type) {
2404                 case MONO_TYPE_STRING:
2405                 case MONO_TYPE_CLASS:
2406                 case MONO_TYPE_ARRAY:
2407                 case MONO_TYPE_SZARRAY:
2408                 case MONO_TYPE_OBJECT:
2409                 case MONO_TYPE_PTR:
2410                 case MONO_TYPE_I:
2411                 case MONO_TYPE_U:
2412                 case MONO_TYPE_I8:
2413                 case MONO_TYPE_U8:
2414                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2415                         p->regs [greg ++] = (mgreg_t)*(arg);
2416                         break;
2417                 case MONO_TYPE_BOOLEAN:
2418                 case MONO_TYPE_U1:
2419                         p->regs [greg ++] = *(guint8*)(arg);
2420                         break;
2421                 case MONO_TYPE_I1:
2422                         p->regs [greg ++] = *(gint8*)(arg);
2423                         break;
2424                 case MONO_TYPE_I2:
2425                         p->regs [greg ++] = *(gint16*)(arg);
2426                         break;
2427                 case MONO_TYPE_U2:
2428                 case MONO_TYPE_CHAR:
2429                         p->regs [greg ++] = *(guint16*)(arg);
2430                         break;
2431                 case MONO_TYPE_I4:
2432                         p->regs [greg ++] = *(gint32*)(arg);
2433                         break;
2434                 case MONO_TYPE_U4:
2435                         p->regs [greg ++] = *(guint32*)(arg);
2436                         break;
2437                 case MONO_TYPE_GENERICINST:
2438                     if (MONO_TYPE_IS_REFERENCE (t)) {
2439                                 p->regs [greg ++] = (mgreg_t)*(arg);
2440                                 break;
2441                         } else {
2442                                 /* Fall through */
2443                         }
2444                 case MONO_TYPE_VALUETYPE: {
2445                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2446
2447                         g_assert (ainfo->storage == ArgValuetypeInReg);
2448                         if (ainfo->pair_storage [0] != ArgNone) {
2449                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2450                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2451                         }
2452                         if (ainfo->pair_storage [1] != ArgNone) {
2453                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2454                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2455                         }
2456                         break;
2457                 }
2458                 default:
2459                         g_assert_not_reached ();
2460                 }
2461         }
2462
2463         g_assert (greg <= PARAM_REGS);
2464 }
2465
2466 /*
2467  * mono_arch_finish_dyn_call:
2468  *
2469  *   Store the result of a dyn call into the return value buffer passed to
2470  * start_dyn_call ().
2471  * This function should be as fast as possible, any work which does not depend
2472  * on the actual values of the arguments should be done in
2473  * mono_arch_dyn_call_prepare ().
2474  */
2475 void
2476 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2477 {
2478         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2479         MonoMethodSignature *sig = dinfo->sig;
2480         guint8 *ret = ((DynCallArgs*)buf)->ret;
2481         mgreg_t res = ((DynCallArgs*)buf)->res;
2482
2483         switch (mono_type_get_underlying_type (sig->ret)->type) {
2484         case MONO_TYPE_VOID:
2485                 *(gpointer*)ret = NULL;
2486                 break;
2487         case MONO_TYPE_STRING:
2488         case MONO_TYPE_CLASS:
2489         case MONO_TYPE_ARRAY:
2490         case MONO_TYPE_SZARRAY:
2491         case MONO_TYPE_OBJECT:
2492         case MONO_TYPE_I:
2493         case MONO_TYPE_U:
2494         case MONO_TYPE_PTR:
2495                 *(gpointer*)ret = (gpointer)res;
2496                 break;
2497         case MONO_TYPE_I1:
2498                 *(gint8*)ret = res;
2499                 break;
2500         case MONO_TYPE_U1:
2501         case MONO_TYPE_BOOLEAN:
2502                 *(guint8*)ret = res;
2503                 break;
2504         case MONO_TYPE_I2:
2505                 *(gint16*)ret = res;
2506                 break;
2507         case MONO_TYPE_U2:
2508         case MONO_TYPE_CHAR:
2509                 *(guint16*)ret = res;
2510                 break;
2511         case MONO_TYPE_I4:
2512                 *(gint32*)ret = res;
2513                 break;
2514         case MONO_TYPE_U4:
2515                 *(guint32*)ret = res;
2516                 break;
2517         case MONO_TYPE_I8:
2518                 *(gint64*)ret = res;
2519                 break;
2520         case MONO_TYPE_U8:
2521                 *(guint64*)ret = res;
2522                 break;
2523         case MONO_TYPE_GENERICINST:
2524                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2525                         *(gpointer*)ret = (gpointer)res;
2526                         break;
2527                 } else {
2528                         /* Fall through */
2529                 }
2530         case MONO_TYPE_VALUETYPE:
2531                 if (dinfo->cinfo->vtype_retaddr) {
2532                         /* Nothing to do */
2533                 } else {
2534                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2535
2536                         g_assert (ainfo->storage == ArgValuetypeInReg);
2537
2538                         if (ainfo->pair_storage [0] != ArgNone) {
2539                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2540                                 ((mgreg_t*)ret)[0] = res;
2541                         }
2542
2543                         g_assert (ainfo->pair_storage [1] == ArgNone);
2544                 }
2545                 break;
2546         default:
2547                 g_assert_not_reached ();
2548         }
2549 }
2550
2551 /* emit an exception if condition is fail */
2552 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2553         do {                                                        \
2554                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2555                 if (tins == NULL) {                                                                             \
2556                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2557                                         MONO_PATCH_INFO_EXC, exc_name);  \
2558                         x86_branch32 (code, cond, 0, signed);               \
2559                 } else {        \
2560                         EMIT_COND_BRANCH (tins, cond, signed);  \
2561                 }                       \
2562         } while (0);
2563
2564 #define EMIT_FPCOMPARE(code) do { \
2565         amd64_fcompp (code); \
2566         amd64_fnstsw (code); \
2567 } while (0);
2568
2569 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2570     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2571         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2572         amd64_ ##op (code); \
2573         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2574         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2575 } while (0);
2576
2577 static guint8*
2578 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2579 {
2580         gboolean no_patch = FALSE;
2581
2582         /*
2583          * FIXME: Add support for thunks
2584          */
2585         {
2586                 gboolean near_call = FALSE;
2587
2588                 /*
2589                  * Indirect calls are expensive so try to make a near call if possible.
2590                  * The caller memory is allocated by the code manager so it is
2591                  * guaranteed to be at a 32 bit offset.
2592                  */
2593
2594                 if (patch_type != MONO_PATCH_INFO_ABS) {
2595                         /* The target is in memory allocated using the code manager */
2596                         near_call = TRUE;
2597
2598                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2599                                 if (((MonoMethod*)data)->klass->image->aot_module)
2600                                         /* The callee might be an AOT method */
2601                                         near_call = FALSE;
2602                                 if (((MonoMethod*)data)->dynamic)
2603                                         /* The target is in malloc-ed memory */
2604                                         near_call = FALSE;
2605                         }
2606
2607                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2608                                 /*
2609                                  * The call might go directly to a native function without
2610                                  * the wrapper.
2611                                  */
2612                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2613                                 if (mi) {
2614                                         gconstpointer target = mono_icall_get_wrapper (mi);
2615                                         if ((((guint64)target) >> 32) != 0)
2616                                                 near_call = FALSE;
2617                                 }
2618                         }
2619                 }
2620                 else {
2621                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2622                                 /*
2623                                  * This is not really an optimization, but required because the
2624                                  * generic class init trampolines use R11 to pass the vtable.
2625                                  */
2626                                 near_call = TRUE;
2627                         } else {
2628                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2629                                 if (info) {
2630                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2631                                                 strstr (cfg->method->name, info->name)) {
2632                                                 /* A call to the wrapped function */
2633                                                 if ((((guint64)data) >> 32) == 0)
2634                                                         near_call = TRUE;
2635                                                 no_patch = TRUE;
2636                                         }
2637                                         else if (info->func == info->wrapper) {
2638                                                 /* No wrapper */
2639                                                 if ((((guint64)info->func) >> 32) == 0)
2640                                                         near_call = TRUE;
2641                                         }
2642                                         else {
2643                                                 /* See the comment in mono_codegen () */
2644                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2645                                                         near_call = TRUE;
2646                                         }
2647                                 }
2648                                 else if ((((guint64)data) >> 32) == 0) {
2649                                         near_call = TRUE;
2650                                         no_patch = TRUE;
2651                                 }
2652                         }
2653                 }
2654
2655                 if (cfg->method->dynamic)
2656                         /* These methods are allocated using malloc */
2657                         near_call = FALSE;
2658
2659 #ifdef MONO_ARCH_NOMAP32BIT
2660                 near_call = FALSE;
2661 #endif
2662
2663                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2664                 if (optimize_for_xen)
2665                         near_call = FALSE;
2666
2667                 if (cfg->compile_aot) {
2668                         near_call = TRUE;
2669                         no_patch = TRUE;
2670                 }
2671
2672                 if (near_call) {
2673                         /*
2674                          * Align the call displacement to an address divisible by 4 so it does
2675                          * not span cache lines. This is required for code patching to work on SMP
2676                          * systems.
2677                          */
2678                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2679                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2680                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2681                         amd64_call_code (code, 0);
2682                 }
2683                 else {
2684                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2685                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2686                         amd64_call_reg (code, GP_SCRATCH_REG);
2687                 }
2688         }
2689
2690         return code;
2691 }
2692
2693 static inline guint8*
2694 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2695 {
2696 #ifdef HOST_WIN32
2697         if (win64_adjust_stack)
2698                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2699 #endif
2700         code = emit_call_body (cfg, code, patch_type, data);
2701 #ifdef HOST_WIN32
2702         if (win64_adjust_stack)
2703                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2704 #endif
2705
2706         return code;
2707 }
2708
2709 static inline int
2710 store_membase_imm_to_store_membase_reg (int opcode)
2711 {
2712         switch (opcode) {
2713         case OP_STORE_MEMBASE_IMM:
2714                 return OP_STORE_MEMBASE_REG;
2715         case OP_STOREI4_MEMBASE_IMM:
2716                 return OP_STOREI4_MEMBASE_REG;
2717         case OP_STOREI8_MEMBASE_IMM:
2718                 return OP_STOREI8_MEMBASE_REG;
2719         }
2720
2721         return -1;
2722 }
2723
2724 #ifndef DISABLE_JIT
2725
2726 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2727
2728 /*
2729  * mono_arch_peephole_pass_1:
2730  *
2731  *   Perform peephole opts which should/can be performed before local regalloc
2732  */
2733 void
2734 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2735 {
2736         MonoInst *ins, *n;
2737
2738         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2739                 MonoInst *last_ins = ins->prev;
2740
2741                 switch (ins->opcode) {
2742                 case OP_ADD_IMM:
2743                 case OP_IADD_IMM:
2744                 case OP_LADD_IMM:
2745                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2746                                 /*
2747                                  * X86_LEA is like ADD, but doesn't have the
2748                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2749                                  * its operand to 64 bit.
2750                                  */
2751                                 ins->opcode = OP_X86_LEA_MEMBASE;
2752                                 ins->inst_basereg = ins->sreg1;
2753                         }
2754                         break;
2755                 case OP_LXOR:
2756                 case OP_IXOR:
2757                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2758                                 MonoInst *ins2;
2759
2760                                 /*
2761                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2762                                  * the latter has length 2-3 instead of 6 (reverse constant
2763                                  * propagation). These instruction sequences are very common
2764                                  * in the initlocals bblock.
2765                                  */
2766                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2767                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2768                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2769                                                 ins2->sreg1 = ins->dreg;
2770                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2771                                                 /* Continue */
2772                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2773                                                 NULLIFY_INS (ins2);
2774                                                 /* Continue */
2775                                         } else {
2776                                                 break;
2777                                         }
2778                                 }
2779                         }
2780                         break;
2781                 case OP_COMPARE_IMM:
2782                 case OP_LCOMPARE_IMM:
2783                         /* OP_COMPARE_IMM (reg, 0)
2784                          * -->
2785                          * OP_AMD64_TEST_NULL (reg)
2786                          */
2787                         if (!ins->inst_imm)
2788                                 ins->opcode = OP_AMD64_TEST_NULL;
2789                         break;
2790                 case OP_ICOMPARE_IMM:
2791                         if (!ins->inst_imm)
2792                                 ins->opcode = OP_X86_TEST_NULL;
2793                         break;
2794                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2795                         /*
2796                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2797                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2798                          * -->
2799                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2800                          * OP_COMPARE_IMM reg, imm
2801                          *
2802                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2803                          */
2804                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2805                             ins->inst_basereg == last_ins->inst_destbasereg &&
2806                             ins->inst_offset == last_ins->inst_offset) {
2807                                         ins->opcode = OP_ICOMPARE_IMM;
2808                                         ins->sreg1 = last_ins->sreg1;
2809
2810                                         /* check if we can remove cmp reg,0 with test null */
2811                                         if (!ins->inst_imm)
2812                                                 ins->opcode = OP_X86_TEST_NULL;
2813                                 }
2814
2815                         break;
2816                 }
2817
2818                 mono_peephole_ins (bb, ins);
2819         }
2820 }
2821
2822 void
2823 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2824 {
2825         MonoInst *ins, *n;
2826
2827         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2828                 switch (ins->opcode) {
2829                 case OP_ICONST:
2830                 case OP_I8CONST: {
2831                         /* reg = 0 -> XOR (reg, reg) */
2832                         /* XOR sets cflags on x86, so we cant do it always */
2833                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2834                                 ins->opcode = OP_LXOR;
2835                                 ins->sreg1 = ins->dreg;
2836                                 ins->sreg2 = ins->dreg;
2837                                 /* Fall through */
2838                         } else {
2839                                 break;
2840                         }
2841                 }
2842                 case OP_LXOR:
2843                         /*
2844                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2845                          * 0 result into 64 bits.
2846                          */
2847                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2848                                 ins->opcode = OP_IXOR;
2849                         }
2850                         /* Fall through */
2851                 case OP_IXOR:
2852                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2853                                 MonoInst *ins2;
2854
2855                                 /*
2856                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2857                                  * the latter has length 2-3 instead of 6 (reverse constant
2858                                  * propagation). These instruction sequences are very common
2859                                  * in the initlocals bblock.
2860                                  */
2861                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2862                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2863                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2864                                                 ins2->sreg1 = ins->dreg;
2865                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START)) {
2866                                                 /* Continue */
2867                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2868                                                 NULLIFY_INS (ins2);
2869                                                 /* Continue */
2870                                         } else {
2871                                                 break;
2872                                         }
2873                                 }
2874                         }
2875                         break;
2876                 case OP_IADD_IMM:
2877                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2878                                 ins->opcode = OP_X86_INC_REG;
2879                         break;
2880                 case OP_ISUB_IMM:
2881                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2882                                 ins->opcode = OP_X86_DEC_REG;
2883                         break;
2884                 }
2885
2886                 mono_peephole_ins (bb, ins);
2887         }
2888 }
2889
2890 #define NEW_INS(cfg,ins,dest,op) do {   \
2891                 MONO_INST_NEW ((cfg), (dest), (op)); \
2892         (dest)->cil_code = (ins)->cil_code; \
2893         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2894         } while (0)
2895
2896 /*
2897  * mono_arch_lowering_pass:
2898  *
2899  *  Converts complex opcodes into simpler ones so that each IR instruction
2900  * corresponds to one machine instruction.
2901  */
2902 void
2903 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2904 {
2905         MonoInst *ins, *n, *temp;
2906
2907         /*
2908          * FIXME: Need to add more instructions, but the current machine
2909          * description can't model some parts of the composite instructions like
2910          * cdq.
2911          */
2912         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2913                 switch (ins->opcode) {
2914                 case OP_DIV_IMM:
2915                 case OP_REM_IMM:
2916                 case OP_IDIV_IMM:
2917                 case OP_IDIV_UN_IMM:
2918                 case OP_IREM_UN_IMM:
2919                         mono_decompose_op_imm (cfg, bb, ins);
2920                         break;
2921                 case OP_IREM_IMM:
2922                         /* Keep the opcode if we can implement it efficiently */
2923                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2924                                 mono_decompose_op_imm (cfg, bb, ins);
2925                         break;
2926                 case OP_COMPARE_IMM:
2927                 case OP_LCOMPARE_IMM:
2928                         if (!amd64_is_imm32 (ins->inst_imm)) {
2929                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2930                                 temp->inst_c0 = ins->inst_imm;
2931                                 temp->dreg = mono_alloc_ireg (cfg);
2932                                 ins->opcode = OP_COMPARE;
2933                                 ins->sreg2 = temp->dreg;
2934                         }
2935                         break;
2936                 case OP_LOAD_MEMBASE:
2937                 case OP_LOADI8_MEMBASE:
2938                         if (!amd64_is_imm32 (ins->inst_offset)) {
2939                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2940                                 temp->inst_c0 = ins->inst_offset;
2941                                 temp->dreg = mono_alloc_ireg (cfg);
2942                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2943                                 ins->inst_indexreg = temp->dreg;
2944                         }
2945                         break;
2946                 case OP_STORE_MEMBASE_IMM:
2947                 case OP_STOREI8_MEMBASE_IMM:
2948                         if (!amd64_is_imm32 (ins->inst_imm)) {
2949                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2950                                 temp->inst_c0 = ins->inst_imm;
2951                                 temp->dreg = mono_alloc_ireg (cfg);
2952                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2953                                 ins->sreg1 = temp->dreg;
2954                         }
2955                         break;
2956 #ifdef MONO_ARCH_SIMD_INTRINSICS
2957                 case OP_EXPAND_I1: {
2958                                 int temp_reg1 = mono_alloc_ireg (cfg);
2959                                 int temp_reg2 = mono_alloc_ireg (cfg);
2960                                 int original_reg = ins->sreg1;
2961
2962                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2963                                 temp->sreg1 = original_reg;
2964                                 temp->dreg = temp_reg1;
2965
2966                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2967                                 temp->sreg1 = temp_reg1;
2968                                 temp->dreg = temp_reg2;
2969                                 temp->inst_imm = 8;
2970
2971                                 NEW_INS (cfg, ins, temp, OP_LOR);
2972                                 temp->sreg1 = temp->dreg = temp_reg2;
2973                                 temp->sreg2 = temp_reg1;
2974
2975                                 ins->opcode = OP_EXPAND_I2;
2976                                 ins->sreg1 = temp_reg2;
2977                         }
2978                         break;
2979 #endif
2980                 default:
2981                         break;
2982                 }
2983         }
2984
2985         bb->max_vreg = cfg->next_vreg;
2986 }
2987
2988 static const int
2989 branch_cc_table [] = {
2990         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2991         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2992         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2993 };
2994
2995 /* Maps CMP_... constants to X86_CC_... constants */
2996 static const int
2997 cc_table [] = {
2998         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2999         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3000 };
3001
3002 static const int
3003 cc_signed_table [] = {
3004         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3005         FALSE, FALSE, FALSE, FALSE
3006 };
3007
3008 /*#include "cprop.c"*/
3009
3010 static unsigned char*
3011 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3012 {
3013         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3014
3015         if (size == 1)
3016                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3017         else if (size == 2)
3018                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3019         return code;
3020 }
3021
3022 static unsigned char*
3023 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3024 {
3025         int sreg = tree->sreg1;
3026         int need_touch = FALSE;
3027
3028 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3029         if (!tree->flags & MONO_INST_INIT)
3030                 need_touch = TRUE;
3031 #endif
3032
3033         if (need_touch) {
3034                 guint8* br[5];
3035
3036                 /*
3037                  * Under Windows:
3038                  * If requested stack size is larger than one page,
3039                  * perform stack-touch operation
3040                  */
3041                 /*
3042                  * Generate stack probe code.
3043                  * Under Windows, it is necessary to allocate one page at a time,
3044                  * "touching" stack after each successful sub-allocation. This is
3045                  * because of the way stack growth is implemented - there is a
3046                  * guard page before the lowest stack page that is currently commited.
3047                  * Stack normally grows sequentially so OS traps access to the
3048                  * guard page and commits more pages when needed.
3049                  */
3050                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3051                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3052
3053                 br[2] = code; /* loop */
3054                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3055                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3056                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3057                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3058                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3059                 amd64_patch (br[3], br[2]);
3060                 amd64_test_reg_reg (code, sreg, sreg);
3061                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3062                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3063
3064                 br[1] = code; x86_jump8 (code, 0);
3065
3066                 amd64_patch (br[0], code);
3067                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3068                 amd64_patch (br[1], code);
3069                 amd64_patch (br[4], code);
3070         }
3071         else
3072                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3073
3074         if (tree->flags & MONO_INST_INIT) {
3075                 int offset = 0;
3076                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3077                         amd64_push_reg (code, AMD64_RAX);
3078                         offset += 8;
3079                 }
3080                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3081                         amd64_push_reg (code, AMD64_RCX);
3082                         offset += 8;
3083                 }
3084                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3085                         amd64_push_reg (code, AMD64_RDI);
3086                         offset += 8;
3087                 }
3088
3089                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3090                 if (sreg != AMD64_RCX)
3091                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3092                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3093
3094                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3095                 if (cfg->param_area && cfg->arch.no_pushes)
3096                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3097                 amd64_cld (code);
3098                 amd64_prefix (code, X86_REP_PREFIX);
3099                 amd64_stosl (code);
3100
3101                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3102                         amd64_pop_reg (code, AMD64_RDI);
3103                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3104                         amd64_pop_reg (code, AMD64_RCX);
3105                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3106                         amd64_pop_reg (code, AMD64_RAX);
3107         }
3108         return code;
3109 }
3110
3111 static guint8*
3112 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3113 {
3114         CallInfo *cinfo;
3115         guint32 quad;
3116
3117         /* Move return value to the target register */
3118         /* FIXME: do this in the local reg allocator */
3119         switch (ins->opcode) {
3120         case OP_CALL:
3121         case OP_CALL_REG:
3122         case OP_CALL_MEMBASE:
3123         case OP_LCALL:
3124         case OP_LCALL_REG:
3125         case OP_LCALL_MEMBASE:
3126                 g_assert (ins->dreg == AMD64_RAX);
3127                 break;
3128         case OP_FCALL:
3129         case OP_FCALL_REG:
3130         case OP_FCALL_MEMBASE:
3131                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3132                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3133                 }
3134                 else {
3135                         if (ins->dreg != AMD64_XMM0)
3136                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3137                 }
3138                 break;
3139         case OP_VCALL:
3140         case OP_VCALL_REG:
3141         case OP_VCALL_MEMBASE:
3142         case OP_VCALL2:
3143         case OP_VCALL2_REG:
3144         case OP_VCALL2_MEMBASE:
3145                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3146                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3147                         MonoInst *loc = cfg->arch.vret_addr_loc;
3148
3149                         /* Load the destination address */
3150                         g_assert (loc->opcode == OP_REGOFFSET);
3151                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3152
3153                         for (quad = 0; quad < 2; quad ++) {
3154                                 switch (cinfo->ret.pair_storage [quad]) {
3155                                 case ArgInIReg:
3156                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3157                                         break;
3158                                 case ArgInFloatSSEReg:
3159                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3160                                         break;
3161                                 case ArgInDoubleSSEReg:
3162                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3163                                         break;
3164                                 case ArgNone:
3165                                         break;
3166                                 default:
3167                                         NOT_IMPLEMENTED;
3168                                 }
3169                         }
3170                 }
3171                 break;
3172         }
3173
3174         return code;
3175 }
3176
3177 #endif /* DISABLE_JIT */
3178
3179 /*
3180  * mono_amd64_emit_tls_get:
3181  * @code: buffer to store code to
3182  * @dreg: hard register where to place the result
3183  * @tls_offset: offset info
3184  *
3185  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3186  * the dreg register the item in the thread local storage identified
3187  * by tls_offset.
3188  *
3189  * Returns: a pointer to the end of the stored code
3190  */
3191 guint8*
3192 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3193 {
3194 #ifdef HOST_WIN32
3195         g_assert (tls_offset < 64);
3196         x86_prefix (code, X86_GS_PREFIX);
3197         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3198 #else
3199         if (optimize_for_xen) {
3200                 x86_prefix (code, X86_FS_PREFIX);
3201                 amd64_mov_reg_mem (code, dreg, 0, 8);
3202                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3203         } else {
3204                 x86_prefix (code, X86_FS_PREFIX);
3205                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3206         }
3207 #endif
3208         return code;
3209 }
3210
3211 #define REAL_PRINT_REG(text,reg) \
3212 mono_assert (reg >= 0); \
3213 amd64_push_reg (code, AMD64_RAX); \
3214 amd64_push_reg (code, AMD64_RDX); \
3215 amd64_push_reg (code, AMD64_RCX); \
3216 amd64_push_reg (code, reg); \
3217 amd64_push_imm (code, reg); \
3218 amd64_push_imm (code, text " %d %p\n"); \
3219 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3220 amd64_call_reg (code, AMD64_RAX); \
3221 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3222 amd64_pop_reg (code, AMD64_RCX); \
3223 amd64_pop_reg (code, AMD64_RDX); \
3224 amd64_pop_reg (code, AMD64_RAX);
3225
3226 /* benchmark and set based on cpu */
3227 #define LOOP_ALIGNMENT 8
3228 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3229
3230 #ifndef DISABLE_JIT
3231
3232 void
3233 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3234 {
3235         MonoInst *ins;
3236         MonoCallInst *call;
3237         guint offset;
3238         guint8 *code = cfg->native_code + cfg->code_len;
3239         MonoInst *last_ins = NULL;
3240         guint last_offset = 0;
3241         int max_len;
3242
3243         /* Fix max_offset estimate for each successor bb */
3244         if (cfg->opt & MONO_OPT_BRANCH) {
3245                 int current_offset = cfg->code_len;
3246                 MonoBasicBlock *current_bb;
3247                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3248                         current_bb->max_offset = current_offset;
3249                         current_offset += current_bb->max_length;
3250                 }
3251         }
3252
3253         if (cfg->opt & MONO_OPT_LOOP) {
3254                 int pad, align = LOOP_ALIGNMENT;
3255                 /* set alignment depending on cpu */
3256                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3257                         pad = align - pad;
3258                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3259                         amd64_padding (code, pad);
3260                         cfg->code_len += pad;
3261                         bb->native_offset = cfg->code_len;
3262                 }
3263         }
3264
3265         if (cfg->verbose_level > 2)
3266                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3267
3268         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3269                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3270                 g_assert (!cfg->compile_aot);
3271
3272                 cov->data [bb->dfn].cil_code = bb->cil_code;
3273                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3274                 /* this is not thread save, but good enough */
3275                 amd64_inc_membase (code, AMD64_R11, 0);
3276         }
3277
3278         offset = code - cfg->native_code;
3279
3280         mono_debug_open_block (cfg, bb, offset);
3281
3282     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3283                 x86_breakpoint (code);
3284
3285         MONO_BB_FOR_EACH_INS (bb, ins) {
3286                 offset = code - cfg->native_code;
3287
3288                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3289
3290                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3291                         cfg->code_size *= 2;
3292                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3293                         code = cfg->native_code + offset;
3294                         mono_jit_stats.code_reallocs++;
3295                 }
3296
3297                 if (cfg->debug_info)
3298                         mono_debug_record_line_number (cfg, ins, offset);
3299
3300                 switch (ins->opcode) {
3301                 case OP_BIGMUL:
3302                         amd64_mul_reg (code, ins->sreg2, TRUE);
3303                         break;
3304                 case OP_BIGMUL_UN:
3305                         amd64_mul_reg (code, ins->sreg2, FALSE);
3306                         break;
3307                 case OP_X86_SETEQ_MEMBASE:
3308                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3309                         break;
3310                 case OP_STOREI1_MEMBASE_IMM:
3311                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3312                         break;
3313                 case OP_STOREI2_MEMBASE_IMM:
3314                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3315                         break;
3316                 case OP_STOREI4_MEMBASE_IMM:
3317                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3318                         break;
3319                 case OP_STOREI1_MEMBASE_REG:
3320                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3321                         break;
3322                 case OP_STOREI2_MEMBASE_REG:
3323                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3324                         break;
3325                 case OP_STORE_MEMBASE_REG:
3326                 case OP_STOREI8_MEMBASE_REG:
3327                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3328                         break;
3329                 case OP_STOREI4_MEMBASE_REG:
3330                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3331                         break;
3332                 case OP_STORE_MEMBASE_IMM:
3333                 case OP_STOREI8_MEMBASE_IMM:
3334                         g_assert (amd64_is_imm32 (ins->inst_imm));
3335                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3336                         break;
3337                 case OP_LOAD_MEM:
3338                 case OP_LOADI8_MEM:
3339                         // FIXME: Decompose this earlier
3340                         if (amd64_is_imm32 (ins->inst_imm))
3341                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3342                         else {
3343                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3344                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3345                         }
3346                         break;
3347                 case OP_LOADI4_MEM:
3348                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3349                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3350                         break;
3351                 case OP_LOADU4_MEM:
3352                         // FIXME: Decompose this earlier
3353                         if (amd64_is_imm32 (ins->inst_imm))
3354                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3355                         else {
3356                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3357                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3358                         }
3359                         break;
3360                 case OP_LOADU1_MEM:
3361                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3362                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3363                         break;
3364                 case OP_LOADU2_MEM:
3365                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3366                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3367                         break;
3368                 case OP_LOAD_MEMBASE:
3369                 case OP_LOADI8_MEMBASE:
3370                         g_assert (amd64_is_imm32 (ins->inst_offset));
3371                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3372                         break;
3373                 case OP_LOADI4_MEMBASE:
3374                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3375                         break;
3376                 case OP_LOADU4_MEMBASE:
3377                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3378                         break;
3379                 case OP_LOADU1_MEMBASE:
3380                         /* The cpu zero extends the result into 64 bits */
3381                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3382                         break;
3383                 case OP_LOADI1_MEMBASE:
3384                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3385                         break;
3386                 case OP_LOADU2_MEMBASE:
3387                         /* The cpu zero extends the result into 64 bits */
3388                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3389                         break;
3390                 case OP_LOADI2_MEMBASE:
3391                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3392                         break;
3393                 case OP_AMD64_LOADI8_MEMINDEX:
3394                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3395                         break;
3396                 case OP_LCONV_TO_I1:
3397                 case OP_ICONV_TO_I1:
3398                 case OP_SEXT_I1:
3399                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3400                         break;
3401                 case OP_LCONV_TO_I2:
3402                 case OP_ICONV_TO_I2:
3403                 case OP_SEXT_I2:
3404                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3405                         break;
3406                 case OP_LCONV_TO_U1:
3407                 case OP_ICONV_TO_U1:
3408                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3409                         break;
3410                 case OP_LCONV_TO_U2:
3411                 case OP_ICONV_TO_U2:
3412                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3413                         break;
3414                 case OP_ZEXT_I4:
3415                         /* Clean out the upper word */
3416                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3417                         break;
3418                 case OP_SEXT_I4:
3419                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3420                         break;
3421                 case OP_COMPARE:
3422                 case OP_LCOMPARE:
3423                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3424                         break;
3425                 case OP_COMPARE_IMM:
3426                 case OP_LCOMPARE_IMM:
3427                         g_assert (amd64_is_imm32 (ins->inst_imm));
3428                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3429                         break;
3430                 case OP_X86_COMPARE_REG_MEMBASE:
3431                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3432                         break;
3433                 case OP_X86_TEST_NULL:
3434                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3435                         break;
3436                 case OP_AMD64_TEST_NULL:
3437                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3438                         break;
3439
3440                 case OP_X86_ADD_REG_MEMBASE:
3441                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3442                         break;
3443                 case OP_X86_SUB_REG_MEMBASE:
3444                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3445                         break;
3446                 case OP_X86_AND_REG_MEMBASE:
3447                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3448                         break;
3449                 case OP_X86_OR_REG_MEMBASE:
3450                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3451                         break;
3452                 case OP_X86_XOR_REG_MEMBASE:
3453                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3454                         break;
3455
3456                 case OP_X86_ADD_MEMBASE_IMM:
3457                         /* FIXME: Make a 64 version too */
3458                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3459                         break;
3460                 case OP_X86_SUB_MEMBASE_IMM:
3461                         g_assert (amd64_is_imm32 (ins->inst_imm));
3462                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3463                         break;
3464                 case OP_X86_AND_MEMBASE_IMM:
3465                         g_assert (amd64_is_imm32 (ins->inst_imm));
3466                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3467                         break;
3468                 case OP_X86_OR_MEMBASE_IMM:
3469                         g_assert (amd64_is_imm32 (ins->inst_imm));
3470                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3471                         break;
3472                 case OP_X86_XOR_MEMBASE_IMM:
3473                         g_assert (amd64_is_imm32 (ins->inst_imm));
3474                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3475                         break;
3476                 case OP_X86_ADD_MEMBASE_REG:
3477                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3478                         break;
3479                 case OP_X86_SUB_MEMBASE_REG:
3480                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3481                         break;
3482                 case OP_X86_AND_MEMBASE_REG:
3483                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3484                         break;
3485                 case OP_X86_OR_MEMBASE_REG:
3486                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3487                         break;
3488                 case OP_X86_XOR_MEMBASE_REG:
3489                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3490                         break;
3491                 case OP_X86_INC_MEMBASE:
3492                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3493                         break;
3494                 case OP_X86_INC_REG:
3495                         amd64_inc_reg_size (code, ins->dreg, 4);
3496                         break;
3497                 case OP_X86_DEC_MEMBASE:
3498                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3499                         break;
3500                 case OP_X86_DEC_REG:
3501                         amd64_dec_reg_size (code, ins->dreg, 4);
3502                         break;
3503                 case OP_X86_MUL_REG_MEMBASE:
3504                 case OP_X86_MUL_MEMBASE_REG:
3505                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3506                         break;
3507                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3508                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3509                         break;
3510                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3511                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3512                         break;
3513                 case OP_AMD64_COMPARE_MEMBASE_REG:
3514                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3515                         break;
3516                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3517                         g_assert (amd64_is_imm32 (ins->inst_imm));
3518                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3519                         break;
3520                 case OP_X86_COMPARE_MEMBASE8_IMM:
3521                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3522                         break;
3523                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3524                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3525                         break;
3526                 case OP_AMD64_COMPARE_REG_MEMBASE:
3527                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3528                         break;
3529
3530                 case OP_AMD64_ADD_REG_MEMBASE:
3531                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3532                         break;
3533                 case OP_AMD64_SUB_REG_MEMBASE:
3534                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3535                         break;
3536                 case OP_AMD64_AND_REG_MEMBASE:
3537                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3538                         break;
3539                 case OP_AMD64_OR_REG_MEMBASE:
3540                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3541                         break;
3542                 case OP_AMD64_XOR_REG_MEMBASE:
3543                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3544                         break;
3545
3546                 case OP_AMD64_ADD_MEMBASE_REG:
3547                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3548                         break;
3549                 case OP_AMD64_SUB_MEMBASE_REG:
3550                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3551                         break;
3552                 case OP_AMD64_AND_MEMBASE_REG:
3553                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3554                         break;
3555                 case OP_AMD64_OR_MEMBASE_REG:
3556                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3557                         break;
3558                 case OP_AMD64_XOR_MEMBASE_REG:
3559                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3560                         break;
3561
3562                 case OP_AMD64_ADD_MEMBASE_IMM:
3563                         g_assert (amd64_is_imm32 (ins->inst_imm));
3564                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3565                         break;
3566                 case OP_AMD64_SUB_MEMBASE_IMM:
3567                         g_assert (amd64_is_imm32 (ins->inst_imm));
3568                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3569                         break;
3570                 case OP_AMD64_AND_MEMBASE_IMM:
3571                         g_assert (amd64_is_imm32 (ins->inst_imm));
3572                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3573                         break;
3574                 case OP_AMD64_OR_MEMBASE_IMM:
3575                         g_assert (amd64_is_imm32 (ins->inst_imm));
3576                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3577                         break;
3578                 case OP_AMD64_XOR_MEMBASE_IMM:
3579                         g_assert (amd64_is_imm32 (ins->inst_imm));
3580                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3581                         break;
3582
3583                 case OP_BREAK:
3584                         amd64_breakpoint (code);
3585                         break;
3586                 case OP_RELAXED_NOP:
3587                         x86_prefix (code, X86_REP_PREFIX);
3588                         x86_nop (code);
3589                         break;
3590                 case OP_HARD_NOP:
3591                         x86_nop (code);
3592                         break;
3593                 case OP_NOP:
3594                 case OP_DUMMY_USE:
3595                 case OP_DUMMY_STORE:
3596                 case OP_NOT_REACHED:
3597                 case OP_NOT_NULL:
3598                         break;
3599                 case OP_SEQ_POINT: {
3600                         int i;
3601
3602                         if (cfg->compile_aot)
3603                                 NOT_IMPLEMENTED;
3604
3605                         /*
3606                          * Read from the single stepping trigger page. This will cause a
3607                          * SIGSEGV when single stepping is enabled.
3608                          * We do this _before_ the breakpoint, so single stepping after
3609                          * a breakpoint is hit will step to the next IL offset.
3610                          */
3611                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3612                                 if (((guint64)ss_trigger_page >> 32) == 0)
3613                                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3614                                 else {
3615                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
3616
3617                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
3618                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
3619                                 }
3620                         }
3621
3622                         /*
3623                          * This is the address which is saved in seq points,
3624                          * get_ip_for_single_step () / get_ip_for_breakpoint () needs to compute this
3625                          * from the address of the instruction causing the fault.
3626                          */
3627                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3628
3629                         /*
3630                          * A placeholder for a possible breakpoint inserted by
3631                          * mono_arch_set_breakpoint ().
3632                          */
3633                         for (i = 0; i < breakpoint_size; ++i)
3634                                 x86_nop (code);
3635                         break;
3636                 }
3637                 case OP_ADDCC:
3638                 case OP_LADD:
3639                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3640                         break;
3641                 case OP_ADC:
3642                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3643                         break;
3644                 case OP_ADD_IMM:
3645                 case OP_LADD_IMM:
3646                         g_assert (amd64_is_imm32 (ins->inst_imm));
3647                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3648                         break;
3649                 case OP_ADC_IMM:
3650                         g_assert (amd64_is_imm32 (ins->inst_imm));
3651                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3652                         break;
3653                 case OP_SUBCC:
3654                 case OP_LSUB:
3655                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3656                         break;
3657                 case OP_SBB:
3658                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3659                         break;
3660                 case OP_SUB_IMM:
3661                 case OP_LSUB_IMM:
3662                         g_assert (amd64_is_imm32 (ins->inst_imm));
3663                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3664                         break;
3665                 case OP_SBB_IMM:
3666                         g_assert (amd64_is_imm32 (ins->inst_imm));
3667                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3668                         break;
3669                 case OP_LAND:
3670                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3671                         break;
3672                 case OP_AND_IMM:
3673                 case OP_LAND_IMM:
3674                         g_assert (amd64_is_imm32 (ins->inst_imm));
3675                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3676                         break;
3677                 case OP_LMUL:
3678                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3679                         break;
3680                 case OP_MUL_IMM:
3681                 case OP_LMUL_IMM:
3682                 case OP_IMUL_IMM: {
3683                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3684
3685                         switch (ins->inst_imm) {
3686                         case 2:
3687                                 /* MOV r1, r2 */
3688                                 /* ADD r1, r1 */
3689                                 if (ins->dreg != ins->sreg1)
3690                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3691                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3692                                 break;
3693                         case 3:
3694                                 /* LEA r1, [r2 + r2*2] */
3695                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3696                                 break;
3697                         case 5:
3698                                 /* LEA r1, [r2 + r2*4] */
3699                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3700                                 break;
3701                         case 6:
3702                                 /* LEA r1, [r2 + r2*2] */
3703                                 /* ADD r1, r1          */
3704                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3705                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3706                                 break;
3707                         case 9:
3708                                 /* LEA r1, [r2 + r2*8] */
3709                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3710                                 break;
3711                         case 10:
3712                                 /* LEA r1, [r2 + r2*4] */
3713                                 /* ADD r1, r1          */
3714                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3715                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3716                                 break;
3717                         case 12:
3718                                 /* LEA r1, [r2 + r2*2] */
3719                                 /* SHL r1, 2           */
3720                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3721                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3722                                 break;
3723                         case 25:
3724                                 /* LEA r1, [r2 + r2*4] */
3725                                 /* LEA r1, [r1 + r1*4] */
3726                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3727                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3728                                 break;
3729                         case 100:
3730                                 /* LEA r1, [r2 + r2*4] */
3731                                 /* SHL r1, 2           */
3732                                 /* LEA r1, [r1 + r1*4] */
3733                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3734                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3735                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3736                                 break;
3737                         default:
3738                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3739                                 break;
3740                         }
3741                         break;
3742                 }
3743                 case OP_LDIV:
3744                 case OP_LREM:
3745                         /* Regalloc magic makes the div/rem cases the same */
3746                         if (ins->sreg2 == AMD64_RDX) {
3747                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3748                                 amd64_cdq (code);
3749                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3750                         } else {
3751                                 amd64_cdq (code);
3752                                 amd64_div_reg (code, ins->sreg2, TRUE);
3753                         }
3754                         break;
3755                 case OP_LDIV_UN:
3756                 case OP_LREM_UN:
3757                         if (ins->sreg2 == AMD64_RDX) {
3758                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3759                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3760                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3761                         } else {
3762                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3763                                 amd64_div_reg (code, ins->sreg2, FALSE);
3764                         }
3765                         break;
3766                 case OP_IDIV:
3767                 case OP_IREM:
3768                         if (ins->sreg2 == AMD64_RDX) {
3769                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3770                                 amd64_cdq_size (code, 4);
3771                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3772                         } else {
3773                                 amd64_cdq_size (code, 4);
3774                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3775                         }
3776                         break;
3777                 case OP_IDIV_UN:
3778                 case OP_IREM_UN:
3779                         if (ins->sreg2 == AMD64_RDX) {
3780                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3781                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3782                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3783                         } else {
3784                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3785                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3786                         }
3787                         break;
3788                 case OP_IREM_IMM: {
3789                         int power = mono_is_power_of_two (ins->inst_imm);
3790
3791                         g_assert (ins->sreg1 == X86_EAX);
3792                         g_assert (ins->dreg == X86_EAX);
3793                         g_assert (power >= 0);
3794
3795                         if (power == 0) {
3796                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3797                                 break;
3798                         }
3799
3800                         /* Based on gcc code */
3801
3802                         /* Add compensation for negative dividents */
3803                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3804                         if (power > 1)
3805                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3806                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3807                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3808                         /* Compute remainder */
3809                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3810                         /* Remove compensation */
3811                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3812                         break;
3813                 }
3814                 case OP_LMUL_OVF:
3815                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3816                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3817                         break;
3818                 case OP_LOR:
3819                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3820                         break;
3821                 case OP_OR_IMM:
3822                 case OP_LOR_IMM:
3823                         g_assert (amd64_is_imm32 (ins->inst_imm));
3824                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3825                         break;
3826                 case OP_LXOR:
3827                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3828                         break;
3829                 case OP_XOR_IMM:
3830                 case OP_LXOR_IMM:
3831                         g_assert (amd64_is_imm32 (ins->inst_imm));
3832                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3833                         break;
3834                 case OP_LSHL:
3835                         g_assert (ins->sreg2 == AMD64_RCX);
3836                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3837                         break;
3838                 case OP_LSHR:
3839                         g_assert (ins->sreg2 == AMD64_RCX);
3840                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3841                         break;
3842                 case OP_SHR_IMM:
3843                         g_assert (amd64_is_imm32 (ins->inst_imm));
3844                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3845                         break;
3846                 case OP_LSHR_IMM:
3847                         g_assert (amd64_is_imm32 (ins->inst_imm));
3848                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3849                         break;
3850                 case OP_SHR_UN_IMM:
3851                         g_assert (amd64_is_imm32 (ins->inst_imm));
3852                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3853                         break;
3854                 case OP_LSHR_UN_IMM:
3855                         g_assert (amd64_is_imm32 (ins->inst_imm));
3856                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3857                         break;
3858                 case OP_LSHR_UN:
3859                         g_assert (ins->sreg2 == AMD64_RCX);
3860                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3861                         break;
3862                 case OP_SHL_IMM:
3863                         g_assert (amd64_is_imm32 (ins->inst_imm));
3864                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3865                         break;
3866                 case OP_LSHL_IMM:
3867                         g_assert (amd64_is_imm32 (ins->inst_imm));
3868                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3869                         break;
3870
3871                 case OP_IADDCC:
3872                 case OP_IADD:
3873                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3874                         break;
3875                 case OP_IADC:
3876                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3877                         break;
3878                 case OP_IADD_IMM:
3879                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3880                         break;
3881                 case OP_IADC_IMM:
3882                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3883                         break;
3884                 case OP_ISUBCC:
3885                 case OP_ISUB:
3886                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3887                         break;
3888                 case OP_ISBB:
3889                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3890                         break;
3891                 case OP_ISUB_IMM:
3892                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3893                         break;
3894                 case OP_ISBB_IMM:
3895                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3896                         break;
3897                 case OP_IAND:
3898                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3899                         break;
3900                 case OP_IAND_IMM:
3901                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3902                         break;
3903                 case OP_IOR:
3904                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3905                         break;
3906                 case OP_IOR_IMM:
3907                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3908                         break;
3909                 case OP_IXOR:
3910                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3911                         break;
3912                 case OP_IXOR_IMM:
3913                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3914                         break;
3915                 case OP_INEG:
3916                         amd64_neg_reg_size (code, ins->sreg1, 4);
3917                         break;
3918                 case OP_INOT:
3919                         amd64_not_reg_size (code, ins->sreg1, 4);
3920                         break;
3921                 case OP_ISHL:
3922                         g_assert (ins->sreg2 == AMD64_RCX);
3923                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3924                         break;
3925                 case OP_ISHR:
3926                         g_assert (ins->sreg2 == AMD64_RCX);
3927                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3928                         break;
3929                 case OP_ISHR_IMM:
3930                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3931                         break;
3932                 case OP_ISHR_UN_IMM:
3933                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3934                         break;
3935                 case OP_ISHR_UN:
3936                         g_assert (ins->sreg2 == AMD64_RCX);
3937                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3938                         break;
3939                 case OP_ISHL_IMM:
3940                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3941                         break;
3942                 case OP_IMUL:
3943                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3944                         break;
3945                 case OP_IMUL_OVF:
3946                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3947                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3948                         break;
3949                 case OP_IMUL_OVF_UN:
3950                 case OP_LMUL_OVF_UN: {
3951                         /* the mul operation and the exception check should most likely be split */
3952                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3953                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3954                         /*g_assert (ins->sreg2 == X86_EAX);
3955                         g_assert (ins->dreg == X86_EAX);*/
3956                         if (ins->sreg2 == X86_EAX) {
3957                                 non_eax_reg = ins->sreg1;
3958                         } else if (ins->sreg1 == X86_EAX) {
3959                                 non_eax_reg = ins->sreg2;
3960                         } else {
3961                                 /* no need to save since we're going to store to it anyway */
3962                                 if (ins->dreg != X86_EAX) {
3963                                         saved_eax = TRUE;
3964                                         amd64_push_reg (code, X86_EAX);
3965                                 }
3966                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3967                                 non_eax_reg = ins->sreg2;
3968                         }
3969                         if (ins->dreg == X86_EDX) {
3970                                 if (!saved_eax) {
3971                                         saved_eax = TRUE;
3972                                         amd64_push_reg (code, X86_EAX);
3973                                 }
3974                         } else {
3975                                 saved_edx = TRUE;
3976                                 amd64_push_reg (code, X86_EDX);
3977                         }
3978                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3979                         /* save before the check since pop and mov don't change the flags */
3980                         if (ins->dreg != X86_EAX)
3981                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3982                         if (saved_edx)
3983                                 amd64_pop_reg (code, X86_EDX);
3984                         if (saved_eax)
3985                                 amd64_pop_reg (code, X86_EAX);
3986                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3987                         break;
3988                 }
3989                 case OP_ICOMPARE:
3990                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3991                         break;
3992                 case OP_ICOMPARE_IMM:
3993                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3994                         break;
3995                 case OP_IBEQ:
3996                 case OP_IBLT:
3997                 case OP_IBGT:
3998                 case OP_IBGE:
3999                 case OP_IBLE:
4000                 case OP_LBEQ:
4001                 case OP_LBLT:
4002                 case OP_LBGT:
4003                 case OP_LBGE:
4004                 case OP_LBLE:
4005                 case OP_IBNE_UN:
4006                 case OP_IBLT_UN:
4007                 case OP_IBGT_UN:
4008                 case OP_IBGE_UN:
4009                 case OP_IBLE_UN:
4010                 case OP_LBNE_UN:
4011                 case OP_LBLT_UN:
4012                 case OP_LBGT_UN:
4013                 case OP_LBGE_UN:
4014                 case OP_LBLE_UN:
4015                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4016                         break;
4017
4018                 case OP_CMOV_IEQ:
4019                 case OP_CMOV_IGE:
4020                 case OP_CMOV_IGT:
4021                 case OP_CMOV_ILE:
4022                 case OP_CMOV_ILT:
4023                 case OP_CMOV_INE_UN:
4024                 case OP_CMOV_IGE_UN:
4025                 case OP_CMOV_IGT_UN:
4026                 case OP_CMOV_ILE_UN:
4027                 case OP_CMOV_ILT_UN:
4028                 case OP_CMOV_LEQ:
4029                 case OP_CMOV_LGE:
4030                 case OP_CMOV_LGT:
4031                 case OP_CMOV_LLE:
4032                 case OP_CMOV_LLT:
4033                 case OP_CMOV_LNE_UN:
4034                 case OP_CMOV_LGE_UN:
4035                 case OP_CMOV_LGT_UN:
4036                 case OP_CMOV_LLE_UN:
4037                 case OP_CMOV_LLT_UN:
4038                         g_assert (ins->dreg == ins->sreg1);
4039                         /* This needs to operate on 64 bit values */
4040                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4041                         break;
4042
4043                 case OP_LNOT:
4044                         amd64_not_reg (code, ins->sreg1);
4045                         break;
4046                 case OP_LNEG:
4047                         amd64_neg_reg (code, ins->sreg1);
4048                         break;
4049
4050                 case OP_ICONST:
4051                 case OP_I8CONST:
4052                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4053                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4054                         else
4055                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4056                         break;
4057                 case OP_AOTCONST:
4058                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4059                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
4060                         break;
4061                 case OP_JUMP_TABLE:
4062                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4063                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4064                         break;
4065                 case OP_MOVE:
4066                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4067                         break;
4068                 case OP_AMD64_SET_XMMREG_R4: {
4069                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4070                         break;
4071                 }
4072                 case OP_AMD64_SET_XMMREG_R8: {
4073                         if (ins->dreg != ins->sreg1)
4074                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4075                         break;
4076                 }
4077                 case OP_TAILCALL: {
4078                         MonoCallInst *call = (MonoCallInst*)ins;
4079                         int pos = 0, i;
4080
4081                         /* FIXME: no tracing support... */
4082                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4083                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
4084
4085                         g_assert (!cfg->method->save_lmf);
4086
4087                         if (cfg->arch.omit_fp) {
4088                                 guint32 save_offset = 0;
4089                                 /* Pop callee-saved registers */
4090                                 for (i = 0; i < AMD64_NREG; ++i)
4091                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4092                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4093                                                 save_offset += 8;
4094                                         }
4095                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4096
4097                                 // FIXME:
4098                                 if (call->stack_usage)
4099                                         NOT_IMPLEMENTED;
4100                         }
4101                         else {
4102                                 for (i = 0; i < AMD64_NREG; ++i)
4103                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4104                                                 pos -= sizeof (gpointer);
4105
4106                                 /* Restore callee-saved registers */
4107                                 for (i = AMD64_NREG - 1; i > 0; --i) {
4108                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4109                                                 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4110                                                 pos += 8;
4111                                         }
4112                                 }
4113
4114                                 /* Copy arguments on the stack to our argument area */
4115                                 for (i = 0; i < call->stack_usage; i += 8) {
4116                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, 8);
4117                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, 8);
4118                                 }
4119
4120                                 if (pos)
4121                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4122
4123                                 amd64_leave (code);
4124                         }
4125
4126                         offset = code - cfg->native_code;
4127                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4128                         if (cfg->compile_aot)
4129                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4130                         else
4131                                 amd64_set_reg_template (code, AMD64_R11);
4132                         amd64_jump_reg (code, AMD64_R11);
4133                         break;
4134                 }
4135                 case OP_CHECK_THIS:
4136                         /* ensure ins->sreg1 is not NULL */
4137                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4138                         break;
4139                 case OP_ARGLIST: {
4140                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4141                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4142                         break;
4143                 }
4144                 case OP_CALL:
4145                 case OP_FCALL:
4146                 case OP_LCALL:
4147                 case OP_VCALL:
4148                 case OP_VCALL2:
4149                 case OP_VOIDCALL:
4150                         call = (MonoCallInst*)ins;
4151                         /*
4152                          * The AMD64 ABI forces callers to know about varargs.
4153                          */
4154                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4155                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4156                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4157                                 /*
4158                                  * Since the unmanaged calling convention doesn't contain a
4159                                  * 'vararg' entry, we have to treat every pinvoke call as a
4160                                  * potential vararg call.
4161                                  */
4162                                 guint32 nregs, i;
4163                                 nregs = 0;
4164                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4165                                         if (call->used_fregs & (1 << i))
4166                                                 nregs ++;
4167                                 if (!nregs)
4168                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4169                                 else
4170                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4171                         }
4172
4173                         if (ins->flags & MONO_INST_HAS_METHOD)
4174                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4175                         else
4176                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4177                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4178                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4179                         code = emit_move_return_value (cfg, ins, code);
4180                         break;
4181                 case OP_FCALL_REG:
4182                 case OP_LCALL_REG:
4183                 case OP_VCALL_REG:
4184                 case OP_VCALL2_REG:
4185                 case OP_VOIDCALL_REG:
4186                 case OP_CALL_REG:
4187                         call = (MonoCallInst*)ins;
4188
4189                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4190                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4191                                 ins->sreg1 = AMD64_R11;
4192                         }
4193
4194                         /*
4195                          * The AMD64 ABI forces callers to know about varargs.
4196                          */
4197                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4198                                 if (ins->sreg1 == AMD64_RAX) {
4199                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4200                                         ins->sreg1 = AMD64_R11;
4201                                 }
4202                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4203                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4204                                 /*
4205                                  * Since the unmanaged calling convention doesn't contain a
4206                                  * 'vararg' entry, we have to treat every pinvoke call as a
4207                                  * potential vararg call.
4208                                  */
4209                                 guint32 nregs, i;
4210                                 nregs = 0;
4211                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4212                                         if (call->used_fregs & (1 << i))
4213                                                 nregs ++;
4214                                 if (ins->sreg1 == AMD64_RAX) {
4215                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4216                                         ins->sreg1 = AMD64_R11;
4217                                 }
4218                                 if (!nregs)
4219                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4220                                 else
4221                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4222                         }
4223
4224                         amd64_call_reg (code, ins->sreg1);
4225                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4226                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4227                         code = emit_move_return_value (cfg, ins, code);
4228                         break;
4229                 case OP_FCALL_MEMBASE:
4230                 case OP_LCALL_MEMBASE:
4231                 case OP_VCALL_MEMBASE:
4232                 case OP_VCALL2_MEMBASE:
4233                 case OP_VOIDCALL_MEMBASE:
4234                 case OP_CALL_MEMBASE:
4235                         call = (MonoCallInst*)ins;
4236
4237                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4238                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4239                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4240                         code = emit_move_return_value (cfg, ins, code);
4241                         break;
4242                 case OP_DYN_CALL: {
4243                         int i;
4244                         MonoInst *var = cfg->dyn_call_var;
4245
4246                         g_assert (var->opcode == OP_REGOFFSET);
4247
4248                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4249                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4250                         /* r10 = ftn */
4251                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4252
4253                         /* Save args buffer */
4254                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4255
4256                         /* Set argument registers */
4257                         for (i = 0; i < PARAM_REGS; ++i)
4258                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4259
4260                         /* Make the call */
4261                         amd64_call_reg (code, AMD64_R10);
4262
4263                         /* Save result */
4264                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4265                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4266                         break;
4267                 }
4268                 case OP_AMD64_SAVE_SP_TO_LMF:
4269                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4270                         break;
4271                 case OP_X86_PUSH:
4272                         g_assert (!cfg->arch.no_pushes);
4273                         amd64_push_reg (code, ins->sreg1);
4274                         break;
4275                 case OP_X86_PUSH_IMM:
4276                         g_assert (!cfg->arch.no_pushes);
4277                         g_assert (amd64_is_imm32 (ins->inst_imm));
4278                         amd64_push_imm (code, ins->inst_imm);
4279                         break;
4280                 case OP_X86_PUSH_MEMBASE:
4281                         g_assert (!cfg->arch.no_pushes);
4282                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4283                         break;
4284                 case OP_X86_PUSH_OBJ: {
4285                         int size = ALIGN_TO (ins->inst_imm, 8);
4286
4287                         g_assert (!cfg->arch.no_pushes);
4288
4289                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4290                         amd64_push_reg (code, AMD64_RDI);
4291                         amd64_push_reg (code, AMD64_RSI);
4292                         amd64_push_reg (code, AMD64_RCX);
4293                         if (ins->inst_offset)
4294                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4295                         else
4296                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4297                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4298                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4299                         amd64_cld (code);
4300                         amd64_prefix (code, X86_REP_PREFIX);
4301                         amd64_movsd (code);
4302                         amd64_pop_reg (code, AMD64_RCX);
4303                         amd64_pop_reg (code, AMD64_RSI);
4304                         amd64_pop_reg (code, AMD64_RDI);
4305                         break;
4306                 }
4307                 case OP_X86_LEA:
4308                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4309                         break;
4310                 case OP_X86_LEA_MEMBASE:
4311                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4312                         break;
4313                 case OP_X86_XCHG:
4314                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4315                         break;
4316                 case OP_LOCALLOC:
4317                         /* keep alignment */
4318                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4319                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4320                         code = mono_emit_stack_alloc (cfg, code, ins);
4321                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4322                         if (cfg->param_area && cfg->arch.no_pushes)
4323                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4324                         break;
4325                 case OP_LOCALLOC_IMM: {
4326                         guint32 size = ins->inst_imm;
4327                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4328
4329                         if (ins->flags & MONO_INST_INIT) {
4330                                 if (size < 64) {
4331                                         int i;
4332
4333                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4334                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4335
4336                                         for (i = 0; i < size; i += 8)
4337                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4338                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4339                                 } else {
4340                                         amd64_mov_reg_imm (code, ins->dreg, size);
4341                                         ins->sreg1 = ins->dreg;
4342
4343                                         code = mono_emit_stack_alloc (cfg, code, ins);
4344                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4345                                 }
4346                         } else {
4347                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4348                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4349                         }
4350                         if (cfg->param_area && cfg->arch.no_pushes)
4351                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4352                         break;
4353                 }
4354                 case OP_THROW: {
4355                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4356                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4357                                              (gpointer)"mono_arch_throw_exception", FALSE);
4358                         break;
4359                 }
4360                 case OP_RETHROW: {
4361                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4362                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4363                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4364                         break;
4365                 }
4366                 case OP_CALL_HANDLER:
4367                         /* Align stack */
4368                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4369                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4370                         amd64_call_imm (code, 0);
4371                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4372                         /* Restore stack alignment */
4373                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4374                         break;
4375                 case OP_START_HANDLER: {
4376                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4377                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4378
4379                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4380                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4381                                 cfg->param_area && cfg->arch.no_pushes) {
4382                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4383                         }
4384                         break;
4385                 }
4386                 case OP_ENDFINALLY: {
4387                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4388                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4389                         amd64_ret (code);
4390                         break;
4391                 }
4392                 case OP_ENDFILTER: {
4393                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4394                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4395                         /* The local allocator will put the result into RAX */
4396                         amd64_ret (code);
4397                         break;
4398                 }
4399
4400                 case OP_LABEL:
4401                         ins->inst_c0 = code - cfg->native_code;
4402                         break;
4403                 case OP_BR:
4404                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4405                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4406                         //break;
4407                                 if (ins->inst_target_bb->native_offset) {
4408                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4409                                 } else {
4410                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4411                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4412                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4413                                                 x86_jump8 (code, 0);
4414                                         else
4415                                                 x86_jump32 (code, 0);
4416                         }
4417                         break;
4418                 case OP_BR_REG:
4419                         amd64_jump_reg (code, ins->sreg1);
4420                         break;
4421                 case OP_CEQ:
4422                 case OP_LCEQ:
4423                 case OP_ICEQ:
4424                 case OP_CLT:
4425                 case OP_LCLT:
4426                 case OP_ICLT:
4427                 case OP_CGT:
4428                 case OP_ICGT:
4429                 case OP_LCGT:
4430                 case OP_CLT_UN:
4431                 case OP_LCLT_UN:
4432                 case OP_ICLT_UN:
4433                 case OP_CGT_UN:
4434                 case OP_LCGT_UN:
4435                 case OP_ICGT_UN:
4436                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4437                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4438                         break;
4439                 case OP_COND_EXC_EQ:
4440                 case OP_COND_EXC_NE_UN:
4441                 case OP_COND_EXC_LT:
4442                 case OP_COND_EXC_LT_UN:
4443                 case OP_COND_EXC_GT:
4444                 case OP_COND_EXC_GT_UN:
4445                 case OP_COND_EXC_GE:
4446                 case OP_COND_EXC_GE_UN:
4447                 case OP_COND_EXC_LE:
4448                 case OP_COND_EXC_LE_UN:
4449                 case OP_COND_EXC_IEQ:
4450                 case OP_COND_EXC_INE_UN:
4451                 case OP_COND_EXC_ILT:
4452                 case OP_COND_EXC_ILT_UN:
4453                 case OP_COND_EXC_IGT:
4454                 case OP_COND_EXC_IGT_UN:
4455                 case OP_COND_EXC_IGE:
4456                 case OP_COND_EXC_IGE_UN:
4457                 case OP_COND_EXC_ILE:
4458                 case OP_COND_EXC_ILE_UN:
4459                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4460                         break;
4461                 case OP_COND_EXC_OV:
4462                 case OP_COND_EXC_NO:
4463                 case OP_COND_EXC_C:
4464                 case OP_COND_EXC_NC:
4465                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4466                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4467                         break;
4468                 case OP_COND_EXC_IOV:
4469                 case OP_COND_EXC_INO:
4470                 case OP_COND_EXC_IC:
4471                 case OP_COND_EXC_INC:
4472                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4473                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4474                         break;
4475
4476                 /* floating point opcodes */
4477                 case OP_R8CONST: {
4478                         double d = *(double *)ins->inst_p0;
4479
4480                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4481                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4482                         }
4483                         else {
4484                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4485                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4486                         }
4487                         break;
4488                 }
4489                 case OP_R4CONST: {
4490                         float f = *(float *)ins->inst_p0;
4491
4492                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4493                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4494                         }
4495                         else {
4496                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4497                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4498                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4499                         }
4500                         break;
4501                 }
4502                 case OP_STORER8_MEMBASE_REG:
4503                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4504                         break;
4505                 case OP_LOADR8_MEMBASE:
4506                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4507                         break;
4508                 case OP_STORER4_MEMBASE_REG:
4509                         /* This requires a double->single conversion */
4510                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4511                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4512                         break;
4513                 case OP_LOADR4_MEMBASE:
4514                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4515                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4516                         break;
4517                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4518                 case OP_ICONV_TO_R8:
4519                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4520                         break;
4521                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4522                 case OP_LCONV_TO_R8:
4523                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4524                         break;
4525                 case OP_FCONV_TO_R4:
4526                         /* FIXME: nothing to do ?? */
4527                         break;
4528                 case OP_FCONV_TO_I1:
4529                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4530                         break;
4531                 case OP_FCONV_TO_U1:
4532                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4533                         break;
4534                 case OP_FCONV_TO_I2:
4535                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4536                         break;
4537                 case OP_FCONV_TO_U2:
4538                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4539                         break;
4540                 case OP_FCONV_TO_U4:
4541                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4542                         break;
4543                 case OP_FCONV_TO_I4:
4544                 case OP_FCONV_TO_I:
4545                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4546                         break;
4547                 case OP_FCONV_TO_I8:
4548                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4549                         break;
4550                 case OP_LCONV_TO_R_UN: {
4551                         guint8 *br [2];
4552
4553                         /* Based on gcc code */
4554                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4555                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4556
4557                         /* Positive case */
4558                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4559                         br [1] = code; x86_jump8 (code, 0);
4560                         amd64_patch (br [0], code);
4561
4562                         /* Negative case */
4563                         /* Save to the red zone */
4564                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4565                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4566                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4567                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4568                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4569                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4570                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4571                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4572                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4573                         /* Restore */
4574                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4575                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4576                         amd64_patch (br [1], code);
4577                         break;
4578                 }
4579                 case OP_LCONV_TO_OVF_U4:
4580                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4581                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4582                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4583                         break;
4584                 case OP_LCONV_TO_OVF_I4_UN:
4585                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4586                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4587                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4588                         break;
4589                 case OP_FMOVE:
4590                         if (ins->dreg != ins->sreg1)
4591                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4592                         break;
4593                 case OP_FADD:
4594                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4595                         break;
4596                 case OP_FSUB:
4597                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4598                         break;
4599                 case OP_FMUL:
4600                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4601                         break;
4602                 case OP_FDIV:
4603                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4604                         break;
4605                 case OP_FNEG: {
4606                         static double r8_0 = -0.0;
4607
4608                         g_assert (ins->sreg1 == ins->dreg);
4609
4610                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4611                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4612                         break;
4613                 }
4614                 case OP_SIN:
4615                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4616                         break;
4617                 case OP_COS:
4618                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4619                         break;
4620                 case OP_ABS: {
4621                         static guint64 d = 0x7fffffffffffffffUL;
4622
4623                         g_assert (ins->sreg1 == ins->dreg);
4624
4625                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4626                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4627                         break;
4628                 }
4629                 case OP_SQRT:
4630                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4631                         break;
4632                 case OP_IMIN:
4633                         g_assert (cfg->opt & MONO_OPT_CMOV);
4634                         g_assert (ins->dreg == ins->sreg1);
4635                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4636                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4637                         break;
4638                 case OP_IMIN_UN:
4639                         g_assert (cfg->opt & MONO_OPT_CMOV);
4640                         g_assert (ins->dreg == ins->sreg1);
4641                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4642                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4643                         break;
4644                 case OP_IMAX:
4645                         g_assert (cfg->opt & MONO_OPT_CMOV);
4646                         g_assert (ins->dreg == ins->sreg1);
4647                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4648                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4649                         break;
4650                 case OP_IMAX_UN:
4651                         g_assert (cfg->opt & MONO_OPT_CMOV);
4652                         g_assert (ins->dreg == ins->sreg1);
4653                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4654                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4655                         break;
4656                 case OP_LMIN:
4657                         g_assert (cfg->opt & MONO_OPT_CMOV);
4658                         g_assert (ins->dreg == ins->sreg1);
4659                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4660                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4661                         break;
4662                 case OP_LMIN_UN:
4663                         g_assert (cfg->opt & MONO_OPT_CMOV);
4664                         g_assert (ins->dreg == ins->sreg1);
4665                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4666                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4667                         break;
4668                 case OP_LMAX:
4669                         g_assert (cfg->opt & MONO_OPT_CMOV);
4670                         g_assert (ins->dreg == ins->sreg1);
4671                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4672                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4673                         break;
4674                 case OP_LMAX_UN:
4675                         g_assert (cfg->opt & MONO_OPT_CMOV);
4676                         g_assert (ins->dreg == ins->sreg1);
4677                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4678                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4679                         break;
4680                 case OP_X86_FPOP:
4681                         break;
4682                 case OP_FCOMPARE:
4683                         /*
4684                          * The two arguments are swapped because the fbranch instructions
4685                          * depend on this for the non-sse case to work.
4686                          */
4687                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4688                         break;
4689                 case OP_FCEQ: {
4690                         /* zeroing the register at the start results in
4691                          * shorter and faster code (we can also remove the widening op)
4692                          */
4693                         guchar *unordered_check;
4694                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4695                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4696                         unordered_check = code;
4697                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4698                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4699                         amd64_patch (unordered_check, code);
4700                         break;
4701                 }
4702                 case OP_FCLT:
4703                 case OP_FCLT_UN:
4704                         /* zeroing the register at the start results in
4705                          * shorter and faster code (we can also remove the widening op)
4706                          */
4707                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4708                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4709                         if (ins->opcode == OP_FCLT_UN) {
4710                                 guchar *unordered_check = code;
4711                                 guchar *jump_to_end;
4712                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4713                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4714                                 jump_to_end = code;
4715                                 x86_jump8 (code, 0);
4716                                 amd64_patch (unordered_check, code);
4717                                 amd64_inc_reg (code, ins->dreg);
4718                                 amd64_patch (jump_to_end, code);
4719                         } else {
4720                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4721                         }
4722                         break;
4723                 case OP_FCGT:
4724                 case OP_FCGT_UN: {
4725                         /* zeroing the register at the start results in
4726                          * shorter and faster code (we can also remove the widening op)
4727                          */
4728                         guchar *unordered_check;
4729                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4730                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4731                         if (ins->opcode == OP_FCGT) {
4732                                 unordered_check = code;
4733                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4734                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4735                                 amd64_patch (unordered_check, code);
4736                         } else {
4737                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4738                         }
4739                         break;
4740                 }
4741                 case OP_FCLT_MEMBASE:
4742                 case OP_FCGT_MEMBASE:
4743                 case OP_FCLT_UN_MEMBASE:
4744                 case OP_FCGT_UN_MEMBASE:
4745                 case OP_FCEQ_MEMBASE: {
4746                         guchar *unordered_check, *jump_to_end;
4747                         int x86_cond;
4748
4749                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4750                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4751
4752                         switch (ins->opcode) {
4753                         case OP_FCEQ_MEMBASE:
4754                                 x86_cond = X86_CC_EQ;
4755                                 break;
4756                         case OP_FCLT_MEMBASE:
4757                         case OP_FCLT_UN_MEMBASE:
4758                                 x86_cond = X86_CC_LT;
4759                                 break;
4760                         case OP_FCGT_MEMBASE:
4761                         case OP_FCGT_UN_MEMBASE:
4762                                 x86_cond = X86_CC_GT;
4763                                 break;
4764                         default:
4765                                 g_assert_not_reached ();
4766                         }
4767
4768                         unordered_check = code;
4769                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4770                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4771
4772                         switch (ins->opcode) {
4773                         case OP_FCEQ_MEMBASE:
4774                         case OP_FCLT_MEMBASE:
4775                         case OP_FCGT_MEMBASE:
4776                                 amd64_patch (unordered_check, code);
4777                                 break;
4778                         case OP_FCLT_UN_MEMBASE:
4779                         case OP_FCGT_UN_MEMBASE:
4780                                 jump_to_end = code;
4781                                 x86_jump8 (code, 0);
4782                                 amd64_patch (unordered_check, code);
4783                                 amd64_inc_reg (code, ins->dreg);
4784                                 amd64_patch (jump_to_end, code);
4785                                 break;
4786                         default:
4787                                 break;
4788                         }
4789                         break;
4790                 }
4791                 case OP_FBEQ: {
4792                         guchar *jump = code;
4793                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4794                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4795                         amd64_patch (jump, code);
4796                         break;
4797                 }
4798                 case OP_FBNE_UN:
4799                         /* Branch if C013 != 100 */
4800                         /* branch if !ZF or (PF|CF) */
4801                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4802                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4803                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4804                         break;
4805                 case OP_FBLT:
4806                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4807                         break;
4808                 case OP_FBLT_UN:
4809                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4810                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4811                         break;
4812                 case OP_FBGT:
4813                 case OP_FBGT_UN:
4814                         if (ins->opcode == OP_FBGT) {
4815                                 guchar *br1;
4816
4817                                 /* skip branch if C1=1 */
4818                                 br1 = code;
4819                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4820                                 /* branch if (C0 | C3) = 1 */
4821                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4822                                 amd64_patch (br1, code);
4823                                 break;
4824                         } else {
4825                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4826                         }
4827                         break;
4828                 case OP_FBGE: {
4829                         /* Branch if C013 == 100 or 001 */
4830                         guchar *br1;
4831
4832                         /* skip branch if C1=1 */
4833                         br1 = code;
4834                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4835                         /* branch if (C0 | C3) = 1 */
4836                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4837                         amd64_patch (br1, code);
4838                         break;
4839                 }
4840                 case OP_FBGE_UN:
4841                         /* Branch if C013 == 000 */
4842                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4843                         break;
4844                 case OP_FBLE: {
4845                         /* Branch if C013=000 or 100 */
4846                         guchar *br1;
4847
4848                         /* skip branch if C1=1 */
4849                         br1 = code;
4850                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4851                         /* branch if C0=0 */
4852                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4853                         amd64_patch (br1, code);
4854                         break;
4855                 }
4856                 case OP_FBLE_UN:
4857                         /* Branch if C013 != 001 */
4858                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4859                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4860                         break;
4861                 case OP_CKFINITE:
4862                         /* Transfer value to the fp stack */
4863                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4864                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4865                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4866
4867                         amd64_push_reg (code, AMD64_RAX);
4868                         amd64_fxam (code);
4869                         amd64_fnstsw (code);
4870                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4871                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4872                         amd64_pop_reg (code, AMD64_RAX);
4873                         amd64_fstp (code, 0);
4874                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4875                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4876                         break;
4877                 case OP_TLS_GET: {
4878                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4879                         break;
4880                 }
4881                 case OP_MEMORY_BARRIER: {
4882                         /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4883                         x86_prefix (code, X86_LOCK_PREFIX);
4884                         amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
4885                         break;
4886                 }
4887                 case OP_ATOMIC_ADD_I4:
4888                 case OP_ATOMIC_ADD_I8: {
4889                         int dreg = ins->dreg;
4890                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4891
4892                         if (dreg == ins->inst_basereg)
4893                                 dreg = AMD64_R11;
4894
4895                         if (dreg != ins->sreg2)
4896                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4897
4898                         x86_prefix (code, X86_LOCK_PREFIX);
4899                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4900
4901                         if (dreg != ins->dreg)
4902                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4903
4904                         break;
4905                 }
4906                 case OP_ATOMIC_ADD_NEW_I4:
4907                 case OP_ATOMIC_ADD_NEW_I8: {
4908                         int dreg = ins->dreg;
4909                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4910
4911                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4912                                 dreg = AMD64_R11;
4913
4914                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4915                         amd64_prefix (code, X86_LOCK_PREFIX);
4916                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4917                         /* dreg contains the old value, add with sreg2 value */
4918                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4919
4920                         if (ins->dreg != dreg)
4921                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4922
4923                         break;
4924                 }
4925                 case OP_ATOMIC_EXCHANGE_I4:
4926                 case OP_ATOMIC_EXCHANGE_I8: {
4927                         guchar *br[2];
4928                         int sreg2 = ins->sreg2;
4929                         int breg = ins->inst_basereg;
4930                         guint32 size;
4931                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4932
4933                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4934                                 size = 8;
4935                         else
4936                                 size = 4;
4937
4938                         /*
4939                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4940                          * an explanation of how this works.
4941                          */
4942
4943                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4944                          * hack to overcome limits in x86 reg allocator
4945                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4946                          */
4947                         g_assert (ins->dreg == AMD64_RAX);
4948
4949                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4950                                 /* Highly unlikely, but possible */
4951                                 need_push = TRUE;
4952
4953                         /* The pushes invalidate rsp */
4954                         if ((breg == AMD64_RAX) || need_push) {
4955                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4956                                 breg = AMD64_R11;
4957                         }
4958
4959                         /* We need the EAX reg for the comparand */
4960                         if (ins->sreg2 == AMD64_RAX) {
4961                                 if (breg != AMD64_R11) {
4962                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4963                                         sreg2 = AMD64_R11;
4964                                 } else {
4965                                         g_assert (need_push);
4966                                         amd64_push_reg (code, AMD64_RDX);
4967                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4968                                         sreg2 = AMD64_RDX;
4969                                         rdx_pushed = TRUE;
4970                                 }
4971                         }
4972
4973                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4974
4975                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4976                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4977                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4978                         amd64_patch (br [1], br [0]);
4979
4980                         if (rdx_pushed)
4981                                 amd64_pop_reg (code, AMD64_RDX);
4982
4983                         break;
4984                 }
4985                 case OP_ATOMIC_CAS_I4:
4986                 case OP_ATOMIC_CAS_I8: {
4987                         guint32 size;
4988
4989                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4990                                 size = 8;
4991                         else
4992                                 size = 4;
4993
4994                         /*
4995                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4996                          * an explanation of how this works.
4997                          */
4998                         g_assert (ins->sreg3 == AMD64_RAX);
4999                         g_assert (ins->sreg1 != AMD64_RAX);
5000                         g_assert (ins->sreg1 != ins->sreg2);
5001
5002                         amd64_prefix (code, X86_LOCK_PREFIX);
5003                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5004
5005                         if (ins->dreg != AMD64_RAX)
5006                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5007                         break;
5008                 }
5009                 case OP_CARD_TABLE_WBARRIER: {
5010                         int ptr = ins->sreg1;
5011                         int value = ins->sreg2;
5012                         guchar *br;
5013                         int nursery_shift, card_table_shift;
5014                         gpointer card_table_mask;
5015                         size_t nursery_size;
5016
5017                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5018                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5019
5020                         /*If either point to the stack we can simply avoid the WB. This happens due to
5021                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5022                          */
5023                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5024                                 continue;
5025
5026                         /*
5027                          * We need one register we can clobber, we choose EDX and make sreg1
5028                          * fixed EAX to work around limitations in the local register allocator.
5029                          * sreg2 might get allocated to EDX, but that is not a problem since
5030                          * we use it before clobbering EDX.
5031                          */
5032                         g_assert (ins->sreg1 == AMD64_RAX);
5033
5034                         /*
5035                          * This is the code we produce:
5036                          *
5037                          *   edx = value
5038                          *   edx >>= nursery_shift
5039                          *   cmp edx, (nursery_start >> nursery_shift)
5040                          *   jne done
5041                          *   edx = ptr
5042                          *   edx >>= card_table_shift
5043                          *   edx += cardtable
5044                          *   [edx] = 1
5045                          * done:
5046                          */
5047
5048                         if (value != AMD64_RDX)
5049                                 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5050                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5051                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, nursery_start >> nursery_shift);
5052                         br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5053                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5054                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5055                         if (card_table_mask)
5056                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5057
5058                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5059                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5060
5061                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5062                         x86_patch (br, code);
5063                         break;
5064                 }
5065 #ifdef MONO_ARCH_SIMD_INTRINSICS
5066                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5067                 case OP_ADDPS:
5068                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5069                         break;
5070                 case OP_DIVPS:
5071                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5072                         break;
5073                 case OP_MULPS:
5074                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5075                         break;
5076                 case OP_SUBPS:
5077                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5078                         break;
5079                 case OP_MAXPS:
5080                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5081                         break;
5082                 case OP_MINPS:
5083                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5084                         break;
5085                 case OP_COMPPS:
5086                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5087                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5088                         break;
5089                 case OP_ANDPS:
5090                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5091                         break;
5092                 case OP_ANDNPS:
5093                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5094                         break;
5095                 case OP_ORPS:
5096                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5097                         break;
5098                 case OP_XORPS:
5099                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5100                         break;
5101                 case OP_SQRTPS:
5102                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5103                         break;
5104                 case OP_RSQRTPS:
5105                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5106                         break;
5107                 case OP_RCPPS:
5108                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5109                         break;
5110                 case OP_ADDSUBPS:
5111                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5112                         break;
5113                 case OP_HADDPS:
5114                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5115                         break;
5116                 case OP_HSUBPS:
5117                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5118                         break;
5119                 case OP_DUPPS_HIGH:
5120                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5121                         break;
5122                 case OP_DUPPS_LOW:
5123                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5124                         break;
5125
5126                 case OP_PSHUFLEW_HIGH:
5127                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5128                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5129                         break;
5130                 case OP_PSHUFLEW_LOW:
5131                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5132                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5133                         break;
5134                 case OP_PSHUFLED:
5135                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5136                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5137                         break;
5138
5139                 case OP_ADDPD:
5140                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5141                         break;
5142                 case OP_DIVPD:
5143                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5144                         break;
5145                 case OP_MULPD:
5146                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5147                         break;
5148                 case OP_SUBPD:
5149                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5150                         break;
5151                 case OP_MAXPD:
5152                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5153                         break;
5154                 case OP_MINPD:
5155                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5156                         break;
5157                 case OP_COMPPD:
5158                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5159                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5160                         break;
5161                 case OP_ANDPD:
5162                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5163                         break;
5164                 case OP_ANDNPD:
5165                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5166                         break;
5167                 case OP_ORPD:
5168                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5169                         break;
5170                 case OP_XORPD:
5171                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5172                         break;
5173                 case OP_SQRTPD:
5174                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5175                         break;
5176                 case OP_ADDSUBPD:
5177                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5178                         break;
5179                 case OP_HADDPD:
5180                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5181                         break;
5182                 case OP_HSUBPD:
5183                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5184                         break;
5185                 case OP_DUPPD:
5186                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5187                         break;
5188
5189                 case OP_EXTRACT_MASK:
5190                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5191                         break;
5192
5193                 case OP_PAND:
5194                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5195                         break;
5196                 case OP_POR:
5197                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5198                         break;
5199                 case OP_PXOR:
5200                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5201                         break;
5202
5203                 case OP_PADDB:
5204                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5205                         break;
5206                 case OP_PADDW:
5207                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5208                         break;
5209                 case OP_PADDD:
5210                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5211                         break;
5212                 case OP_PADDQ:
5213                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5214                         break;
5215
5216                 case OP_PSUBB:
5217                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5218                         break;
5219                 case OP_PSUBW:
5220                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5221                         break;
5222                 case OP_PSUBD:
5223                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5224                         break;
5225                 case OP_PSUBQ:
5226                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5227                         break;
5228
5229                 case OP_PMAXB_UN:
5230                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5231                         break;
5232                 case OP_PMAXW_UN:
5233                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5234                         break;
5235                 case OP_PMAXD_UN:
5236                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5237                         break;
5238
5239                 case OP_PMAXB:
5240                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5241                         break;
5242                 case OP_PMAXW:
5243                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5244                         break;
5245                 case OP_PMAXD:
5246                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5247                         break;
5248
5249                 case OP_PAVGB_UN:
5250                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5251                         break;
5252                 case OP_PAVGW_UN:
5253                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5254                         break;
5255
5256                 case OP_PMINB_UN:
5257                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5258                         break;
5259                 case OP_PMINW_UN:
5260                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5261                         break;
5262                 case OP_PMIND_UN:
5263                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5264                         break;
5265
5266                 case OP_PMINB:
5267                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5268                         break;
5269                 case OP_PMINW:
5270                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5271                         break;
5272                 case OP_PMIND:
5273                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5274                         break;
5275
5276                 case OP_PCMPEQB:
5277                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5278                         break;
5279                 case OP_PCMPEQW:
5280                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5281                         break;
5282                 case OP_PCMPEQD:
5283                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5284                         break;
5285                 case OP_PCMPEQQ:
5286                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5287                         break;
5288
5289                 case OP_PCMPGTB:
5290                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5291                         break;
5292                 case OP_PCMPGTW:
5293                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5294                         break;
5295                 case OP_PCMPGTD:
5296                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5297                         break;
5298                 case OP_PCMPGTQ:
5299                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5300                         break;
5301
5302                 case OP_PSUM_ABS_DIFF:
5303                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5304                         break;
5305
5306                 case OP_UNPACK_LOWB:
5307                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5308                         break;
5309                 case OP_UNPACK_LOWW:
5310                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5311                         break;
5312                 case OP_UNPACK_LOWD:
5313                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5314                         break;
5315                 case OP_UNPACK_LOWQ:
5316                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5317                         break;
5318                 case OP_UNPACK_LOWPS:
5319                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5320                         break;
5321                 case OP_UNPACK_LOWPD:
5322                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5323                         break;
5324
5325                 case OP_UNPACK_HIGHB:
5326                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5327                         break;
5328                 case OP_UNPACK_HIGHW:
5329                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5330                         break;
5331                 case OP_UNPACK_HIGHD:
5332                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5333                         break;
5334                 case OP_UNPACK_HIGHQ:
5335                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5336                         break;
5337                 case OP_UNPACK_HIGHPS:
5338                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5339                         break;
5340                 case OP_UNPACK_HIGHPD:
5341                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5342                         break;
5343
5344                 case OP_PACKW:
5345                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5346                         break;
5347                 case OP_PACKD:
5348                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5349                         break;
5350                 case OP_PACKW_UN:
5351                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5352                         break;
5353                 case OP_PACKD_UN:
5354                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5355                         break;
5356
5357                 case OP_PADDB_SAT_UN:
5358                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5359                         break;
5360                 case OP_PSUBB_SAT_UN:
5361                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5362                         break;
5363                 case OP_PADDW_SAT_UN:
5364                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5365                         break;
5366                 case OP_PSUBW_SAT_UN:
5367                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5368                         break;
5369
5370                 case OP_PADDB_SAT:
5371                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5372                         break;
5373                 case OP_PSUBB_SAT:
5374                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5375                         break;
5376                 case OP_PADDW_SAT:
5377                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5378                         break;
5379                 case OP_PSUBW_SAT:
5380                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5381                         break;
5382
5383                 case OP_PMULW:
5384                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5385                         break;
5386                 case OP_PMULD:
5387                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5388                         break;
5389                 case OP_PMULQ:
5390                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5391                         break;
5392                 case OP_PMULW_HIGH_UN:
5393                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5394                         break;
5395                 case OP_PMULW_HIGH:
5396                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5397                         break;
5398
5399                 case OP_PSHRW:
5400                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5401                         break;
5402                 case OP_PSHRW_REG:
5403                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5404                         break;
5405
5406                 case OP_PSARW:
5407                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5408                         break;
5409                 case OP_PSARW_REG:
5410                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5411                         break;
5412
5413                 case OP_PSHLW:
5414                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5415                         break;
5416                 case OP_PSHLW_REG:
5417                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5418                         break;
5419
5420                 case OP_PSHRD:
5421                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5422                         break;
5423                 case OP_PSHRD_REG:
5424                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5425                         break;
5426
5427                 case OP_PSARD:
5428                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5429                         break;
5430                 case OP_PSARD_REG:
5431                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5432                         break;
5433
5434                 case OP_PSHLD:
5435                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5436                         break;
5437                 case OP_PSHLD_REG:
5438                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5439                         break;
5440
5441                 case OP_PSHRQ:
5442                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5443                         break;
5444                 case OP_PSHRQ_REG:
5445                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5446                         break;
5447
5448                 /*TODO: This is appart of the sse spec but not added
5449                 case OP_PSARQ:
5450                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5451                         break;
5452                 case OP_PSARQ_REG:
5453                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5454                         break;
5455                 */
5456
5457                 case OP_PSHLQ:
5458                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5459                         break;
5460                 case OP_PSHLQ_REG:
5461                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5462                         break;
5463
5464                 case OP_ICONV_TO_X:
5465                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5466                         break;
5467                 case OP_EXTRACT_I4:
5468                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5469                         break;
5470                 case OP_EXTRACT_I8:
5471                         if (ins->inst_c0) {
5472                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5473                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5474                         } else {
5475                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5476                         }
5477                         break;
5478                 case OP_EXTRACT_I1:
5479                 case OP_EXTRACT_U1:
5480                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5481                         if (ins->inst_c0)
5482                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5483                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5484                         break;
5485                 case OP_EXTRACT_I2:
5486                 case OP_EXTRACT_U2:
5487                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5488                         if (ins->inst_c0)
5489                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5490                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5491                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5492                         break;
5493                 case OP_EXTRACT_R8:
5494                         if (ins->inst_c0)
5495                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5496                         else
5497                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5498                         break;
5499                 case OP_INSERT_I2:
5500                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5501                         break;
5502                 case OP_EXTRACTX_U2:
5503                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5504                         break;
5505                 case OP_INSERTX_U1_SLOW:
5506                         /*sreg1 is the extracted ireg (scratch)
5507                         /sreg2 is the to be inserted ireg (scratch)
5508                         /dreg is the xreg to receive the value*/
5509
5510                         /*clear the bits from the extracted word*/
5511                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5512                         /*shift the value to insert if needed*/
5513                         if (ins->inst_c0 & 1)
5514                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5515                         /*join them together*/
5516                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5517                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5518                         break;
5519                 case OP_INSERTX_I4_SLOW:
5520                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5521                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5522                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5523                         break;
5524                 case OP_INSERTX_I8_SLOW:
5525                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5526                         if (ins->inst_c0)
5527                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5528                         else
5529                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5530                         break;
5531
5532                 case OP_INSERTX_R4_SLOW:
5533                         switch (ins->inst_c0) {
5534                         case 0:
5535                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5536                                 break;
5537                         case 1:
5538                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5539                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5540                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5541                                 break;
5542                         case 2:
5543                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5544                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5545                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5546                                 break;
5547                         case 3:
5548                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5549                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5550                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5551                                 break;
5552                         }
5553                         break;
5554                 case OP_INSERTX_R8_SLOW:
5555                         if (ins->inst_c0)
5556                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5557                         else
5558                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5559                         break;
5560                 case OP_STOREX_MEMBASE_REG:
5561                 case OP_STOREX_MEMBASE:
5562                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5563                         break;
5564                 case OP_LOADX_MEMBASE:
5565                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5566                         break;
5567                 case OP_LOADX_ALIGNED_MEMBASE:
5568                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5569                         break;
5570                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5571                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5572                         break;
5573                 case OP_STOREX_NTA_MEMBASE_REG:
5574                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5575                         break;
5576                 case OP_PREFETCH_MEMBASE:
5577                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5578                         break;
5579
5580                 case OP_XMOVE:
5581                         /*FIXME the peephole pass should have killed this*/
5582                         if (ins->dreg != ins->sreg1)
5583                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5584                         break;
5585                 case OP_XZERO:
5586                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5587                         break;
5588                 case OP_ICONV_TO_R8_RAW:
5589                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5590                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5591                         break;
5592
5593                 case OP_FCONV_TO_R8_X:
5594                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5595                         break;
5596
5597                 case OP_XCONV_R8_TO_I4:
5598                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5599                         switch (ins->backend.source_opcode) {
5600                         case OP_FCONV_TO_I1:
5601                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5602                                 break;
5603                         case OP_FCONV_TO_U1:
5604                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5605                                 break;
5606                         case OP_FCONV_TO_I2:
5607                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5608                                 break;
5609                         case OP_FCONV_TO_U2:
5610                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5611                                 break;
5612                         }
5613                         break;
5614
5615                 case OP_EXPAND_I2:
5616                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5617                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5618                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5619                         break;
5620                 case OP_EXPAND_I4:
5621                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5622                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5623                         break;
5624                 case OP_EXPAND_I8:
5625                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5626                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5627                         break;
5628                 case OP_EXPAND_R4:
5629                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5630                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5631                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5632                         break;
5633                 case OP_EXPAND_R8:
5634                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5635                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5636                         break;
5637 #endif
5638                 case OP_LIVERANGE_START: {
5639                         if (cfg->verbose_level > 1)
5640                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5641                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5642                         break;
5643                 }
5644                 case OP_LIVERANGE_END: {
5645                         if (cfg->verbose_level > 1)
5646                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5647                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5648                         break;
5649                 }
5650                 default:
5651                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5652                         g_assert_not_reached ();
5653                 }
5654
5655                 if ((code - cfg->native_code - offset) > max_len) {
5656                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5657                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5658                         g_assert_not_reached ();
5659                 }
5660
5661                 last_ins = ins;
5662                 last_offset = offset;
5663         }
5664
5665         cfg->code_len = code - cfg->native_code;
5666 }
5667
5668 #endif /* DISABLE_JIT */
5669
5670 void
5671 mono_arch_register_lowlevel_calls (void)
5672 {
5673         /* The signature doesn't matter */
5674         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5675 }
5676
5677 void
5678 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5679 {
5680         MonoJumpInfo *patch_info;
5681         gboolean compile_aot = !run_cctors;
5682
5683         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5684                 unsigned char *ip = patch_info->ip.i + code;
5685                 unsigned char *target;
5686
5687                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5688
5689                 if (compile_aot) {
5690                         switch (patch_info->type) {
5691                         case MONO_PATCH_INFO_BB:
5692                         case MONO_PATCH_INFO_LABEL:
5693                                 break;
5694                         default:
5695                                 /* No need to patch these */
5696                                 continue;
5697                         }
5698                 }
5699
5700                 switch (patch_info->type) {
5701                 case MONO_PATCH_INFO_NONE:
5702                         continue;
5703                 case MONO_PATCH_INFO_METHOD_REL:
5704                 case MONO_PATCH_INFO_R8:
5705                 case MONO_PATCH_INFO_R4:
5706                         g_assert_not_reached ();
5707                         continue;
5708                 case MONO_PATCH_INFO_BB:
5709                         break;
5710                 default:
5711                         break;
5712                 }
5713
5714                 /*
5715                  * Debug code to help track down problems where the target of a near call is
5716                  * is not valid.
5717                  */
5718                 if (amd64_is_near_call (ip)) {
5719                         gint64 disp = (guint8*)target - (guint8*)ip;
5720
5721                         if (!amd64_is_imm32 (disp)) {
5722                                 printf ("TYPE: %d\n", patch_info->type);
5723                                 switch (patch_info->type) {
5724                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5725                                         printf ("V: %s\n", patch_info->data.name);
5726                                         break;
5727                                 case MONO_PATCH_INFO_METHOD_JUMP:
5728                                 case MONO_PATCH_INFO_METHOD:
5729                                         printf ("V: %s\n", patch_info->data.method->name);
5730                                         break;
5731                                 default:
5732                                         break;
5733                                 }
5734                         }
5735                 }
5736
5737                 amd64_patch (ip, (gpointer)target);
5738         }
5739 }
5740
5741 #ifndef DISABLE_JIT
5742
5743 static int
5744 get_max_epilog_size (MonoCompile *cfg)
5745 {
5746         int max_epilog_size = 16;
5747
5748         if (cfg->method->save_lmf)
5749                 max_epilog_size += 256;
5750
5751         if (mono_jit_trace_calls != NULL)
5752                 max_epilog_size += 50;
5753
5754         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5755                 max_epilog_size += 50;
5756
5757         max_epilog_size += (AMD64_NREG * 2);
5758
5759         return max_epilog_size;
5760 }
5761
5762 /*
5763  * This macro is used for testing whenever the unwinder works correctly at every point
5764  * where an async exception can happen.
5765  */
5766 /* This will generate a SIGSEGV at the given point in the code */
5767 #define async_exc_point(code) do { \
5768     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5769          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5770              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5771          cfg->arch.async_point_count ++; \
5772     } \
5773 } while (0)
5774
5775 guint8 *
5776 mono_arch_emit_prolog (MonoCompile *cfg)
5777 {
5778         MonoMethod *method = cfg->method;
5779         MonoBasicBlock *bb;
5780         MonoMethodSignature *sig;
5781         MonoInst *ins;
5782         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5783         guint8 *code;
5784         CallInfo *cinfo;
5785         gint32 lmf_offset = cfg->arch.lmf_offset;
5786         gboolean args_clobbered = FALSE;
5787         gboolean trace = FALSE;
5788
5789         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
5790
5791         code = cfg->native_code = g_malloc (cfg->code_size);
5792
5793         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5794                 trace = TRUE;
5795
5796         /* Amount of stack space allocated by register saving code */
5797         pos = 0;
5798
5799         /* Offset between RSP and the CFA */
5800         cfa_offset = 0;
5801
5802         /*
5803          * The prolog consists of the following parts:
5804          * FP present:
5805          * - push rbp, mov rbp, rsp
5806          * - save callee saved regs using pushes
5807          * - allocate frame
5808          * - save rgctx if needed
5809          * - save lmf if needed
5810          * FP not present:
5811          * - allocate frame
5812          * - save rgctx if needed
5813          * - save lmf if needed
5814          * - save callee saved regs using moves
5815          */
5816
5817         // CFA = sp + 8
5818         cfa_offset = 8;
5819         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5820         // IP saved at CFA - 8
5821         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5822         async_exc_point (code);
5823
5824         if (!cfg->arch.omit_fp) {
5825                 amd64_push_reg (code, AMD64_RBP);
5826                 cfa_offset += 8;
5827                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5828                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5829                 async_exc_point (code);
5830 #ifdef HOST_WIN32
5831                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5832 #endif
5833
5834                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5835                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5836                 async_exc_point (code);
5837 #ifdef HOST_WIN32
5838                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5839 #endif
5840         }
5841
5842         /* Save callee saved registers */
5843         if (!cfg->arch.omit_fp && !method->save_lmf) {
5844                 int offset = cfa_offset;
5845
5846                 for (i = 0; i < AMD64_NREG; ++i)
5847                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5848                                 amd64_push_reg (code, i);
5849                                 pos += sizeof (gpointer);
5850                                 offset += 8;
5851                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5852                                 async_exc_point (code);
5853                         }
5854         }
5855
5856         /* The param area is always at offset 0 from sp */
5857         /* This needs to be allocated here, since it has to come after the spill area */
5858         if (cfg->arch.no_pushes && cfg->param_area) {
5859                 if (cfg->arch.omit_fp)
5860                         // FIXME:
5861                         g_assert_not_reached ();
5862                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5863         }
5864
5865         if (cfg->arch.omit_fp) {
5866                 /*
5867                  * On enter, the stack is misaligned by the the pushing of the return
5868                  * address. It is either made aligned by the pushing of %rbp, or by
5869                  * this.
5870                  */
5871                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5872                 if ((alloc_size % 16) == 0)
5873                         alloc_size += 8;
5874         } else {
5875                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5876
5877                 alloc_size -= pos;
5878         }
5879
5880         cfg->arch.stack_alloc_size = alloc_size;
5881
5882         /* Allocate stack frame */
5883         if (alloc_size) {
5884                 /* See mono_emit_stack_alloc */
5885 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5886                 guint32 remaining_size = alloc_size;
5887                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5888                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
5889                 guint32 offset = code - cfg->native_code;
5890                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5891                         while (required_code_size >= (cfg->code_size - offset))
5892                                 cfg->code_size *= 2;
5893                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5894                         code = cfg->native_code + offset;
5895                         mono_jit_stats.code_reallocs++;
5896                 }
5897
5898                 while (remaining_size >= 0x1000) {
5899                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5900                         if (cfg->arch.omit_fp) {
5901                                 cfa_offset += 0x1000;
5902                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5903                         }
5904                         async_exc_point (code);
5905 #ifdef HOST_WIN32
5906                         if (cfg->arch.omit_fp)
5907                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5908 #endif
5909
5910                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5911                         remaining_size -= 0x1000;
5912                 }
5913                 if (remaining_size) {
5914                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5915                         if (cfg->arch.omit_fp) {
5916                                 cfa_offset += remaining_size;
5917                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5918                                 async_exc_point (code);
5919                         }
5920 #ifdef HOST_WIN32
5921                         if (cfg->arch.omit_fp)
5922                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5923 #endif
5924                 }
5925 #else
5926                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5927                 if (cfg->arch.omit_fp) {
5928                         cfa_offset += alloc_size;
5929                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5930                         async_exc_point (code);
5931                 }
5932 #endif
5933         }
5934
5935         /* Stack alignment check */
5936 #if 0
5937         {
5938                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5939                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5940                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5941                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5942                 amd64_breakpoint (code);
5943         }
5944 #endif
5945
5946 #ifndef TARGET_WIN32
5947         if (mini_get_debug_options ()->init_stacks) {
5948                 /* Fill the stack frame with a dummy value to force deterministic behavior */
5949
5950                 /* Save registers to the red zone */
5951                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
5952                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5953
5954                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
5955                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
5956                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
5957
5958                 amd64_cld (code);
5959                 amd64_prefix (code, X86_REP_PREFIX);
5960                 amd64_stosl (code);
5961
5962                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
5963                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5964         }
5965 #endif
5966
5967         /* Save LMF */
5968         if (method->save_lmf) {
5969                 /*
5970                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5971                  */
5972                 /*
5973                  * sp is saved right before calls but we need to save it here too so
5974                  * async stack walks would work.
5975                  */
5976                 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5977                 /* Skip method (only needed for trampoline LMF frames) */
5978                 /* Save callee saved regs */
5979                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5980                         int offset;
5981
5982                         switch (i) {
5983                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5984                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5985                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5986                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5987                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5988                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5989 #ifdef HOST_WIN32
5990                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5991                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5992 #endif
5993                         default:
5994                                 offset = -1;
5995                                 break;
5996                         }
5997
5998                         if (offset != -1) {
5999                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
6000                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
6001                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
6002                         }
6003                 }
6004         }
6005
6006         /* Save callee saved registers */
6007         if (cfg->arch.omit_fp && !method->save_lmf) {
6008                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6009
6010                 /* Save caller saved registers after sp is adjusted */
6011                 /* The registers are saved at the bottom of the frame */
6012                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6013                 for (i = 0; i < AMD64_NREG; ++i)
6014                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6015                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
6016                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6017                                 save_area_offset += 8;
6018                                 async_exc_point (code);
6019                         }
6020         }
6021
6022         /* store runtime generic context */
6023         if (cfg->rgctx_var) {
6024                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6025                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6026
6027                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
6028         }
6029
6030         /* compute max_length in order to use short forward jumps */
6031         max_epilog_size = get_max_epilog_size (cfg);
6032         if (cfg->opt & MONO_OPT_BRANCH) {
6033                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6034                         MonoInst *ins;
6035                         int max_length = 0;
6036
6037                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6038                                 max_length += 6;
6039                         /* max alignment for loops */
6040                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6041                                 max_length += LOOP_ALIGNMENT;
6042
6043                         MONO_BB_FOR_EACH_INS (bb, ins) {
6044                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6045                         }
6046
6047                         /* Take prolog and epilog instrumentation into account */
6048                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6049                                 max_length += max_epilog_size;
6050
6051                         bb->max_length = max_length;
6052                 }
6053         }
6054
6055         sig = mono_method_signature (method);
6056         pos = 0;
6057
6058         cinfo = cfg->arch.cinfo;
6059
6060         if (sig->ret->type != MONO_TYPE_VOID) {
6061                 /* Save volatile arguments to the stack */
6062                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6063                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6064         }
6065
6066         /* Keep this in sync with emit_load_volatile_arguments */
6067         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6068                 ArgInfo *ainfo = cinfo->args + i;
6069                 gint32 stack_offset;
6070                 MonoType *arg_type;
6071
6072                 ins = cfg->args [i];
6073
6074                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6075                         /* Unused arguments */
6076                         continue;
6077
6078                 if (sig->hasthis && (i == 0))
6079                         arg_type = &mono_defaults.object_class->byval_arg;
6080                 else
6081                         arg_type = sig->params [i - sig->hasthis];
6082
6083                 stack_offset = ainfo->offset + ARGS_OFFSET;
6084
6085                 if (cfg->globalra) {
6086                         /* All the other moves are done by the register allocator */
6087                         switch (ainfo->storage) {
6088                         case ArgInFloatSSEReg:
6089                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6090                                 break;
6091                         case ArgValuetypeInReg:
6092                                 for (quad = 0; quad < 2; quad ++) {
6093                                         switch (ainfo->pair_storage [quad]) {
6094                                         case ArgInIReg:
6095                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6096                                                 break;
6097                                         case ArgInFloatSSEReg:
6098                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6099                                                 break;
6100                                         case ArgInDoubleSSEReg:
6101                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6102                                                 break;
6103                                         case ArgNone:
6104                                                 break;
6105                                         default:
6106                                                 g_assert_not_reached ();
6107                                         }
6108                                 }
6109                                 break;
6110                         default:
6111                                 break;
6112                         }
6113
6114                         continue;
6115                 }
6116
6117                 /* Save volatile arguments to the stack */
6118                 if (ins->opcode != OP_REGVAR) {
6119                         switch (ainfo->storage) {
6120                         case ArgInIReg: {
6121                                 guint32 size = 8;
6122
6123                                 /* FIXME: I1 etc */
6124                                 /*
6125                                 if (stack_offset & 0x1)
6126                                         size = 1;
6127                                 else if (stack_offset & 0x2)
6128                                         size = 2;
6129                                 else if (stack_offset & 0x4)
6130                                         size = 4;
6131                                 else
6132                                         size = 8;
6133                                 */
6134                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6135                                 break;
6136                         }
6137                         case ArgInFloatSSEReg:
6138                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6139                                 break;
6140                         case ArgInDoubleSSEReg:
6141                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6142                                 break;
6143                         case ArgValuetypeInReg:
6144                                 for (quad = 0; quad < 2; quad ++) {
6145                                         switch (ainfo->pair_storage [quad]) {
6146                                         case ArgInIReg:
6147                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6148                                                 break;
6149                                         case ArgInFloatSSEReg:
6150                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6151                                                 break;
6152                                         case ArgInDoubleSSEReg:
6153                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6154                                                 break;
6155                                         case ArgNone:
6156                                                 break;
6157                                         default:
6158                                                 g_assert_not_reached ();
6159                                         }
6160                                 }
6161                                 break;
6162                         case ArgValuetypeAddrInIReg:
6163                                 if (ainfo->pair_storage [0] == ArgInIReg)
6164                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6165                                 break;
6166                         default:
6167                                 break;
6168                         }
6169                 } else {
6170                         /* Argument allocated to (non-volatile) register */
6171                         switch (ainfo->storage) {
6172                         case ArgInIReg:
6173                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6174                                 break;
6175                         case ArgOnStack:
6176                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6177                                 break;
6178                         default:
6179                                 g_assert_not_reached ();
6180                         }
6181                 }
6182         }
6183
6184         /* Might need to attach the thread to the JIT  or change the domain for the callback */
6185         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6186                 guint64 domain = (guint64)cfg->domain;
6187
6188                 args_clobbered = TRUE;
6189
6190                 /*
6191                  * The call might clobber argument registers, but they are already
6192                  * saved to the stack/global regs.
6193                  */
6194                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6195                         guint8 *buf, *no_domain_branch;
6196
6197                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6198                         if (cfg->compile_aot) {
6199                                 /* AOT code is only used in the root domain */
6200                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6201                         } else {
6202                                 if ((domain >> 32) == 0)
6203                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6204                                 else
6205                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6206                         }
6207                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6208                         no_domain_branch = code;
6209                         x86_branch8 (code, X86_CC_NE, 0, 0);
6210                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6211                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6212                         buf = code;
6213                         x86_branch8 (code, X86_CC_NE, 0, 0);
6214                         amd64_patch (no_domain_branch, code);
6215                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6216                                           (gpointer)"mono_jit_thread_attach", TRUE);
6217                         amd64_patch (buf, code);
6218 #ifdef HOST_WIN32
6219                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6220                         /* FIXME: Add a separate key for LMF to avoid this */
6221                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6222 #endif
6223                 } else {
6224                         g_assert (!cfg->compile_aot);
6225                         if (cfg->compile_aot) {
6226                                 /* AOT code is only used in the root domain */
6227                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6228                         } else {
6229                                 if ((domain >> 32) == 0)
6230                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6231                                 else
6232                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6233                         }
6234                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6235                                           (gpointer)"mono_jit_thread_attach", TRUE);
6236                 }
6237         }
6238
6239         if (method->save_lmf) {
6240                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6241                         /*
6242                          * Optimized version which uses the mono_lmf TLS variable instead of
6243                          * indirection through the mono_lmf_addr TLS variable.
6244                          */
6245                         /* %rax = previous_lmf */
6246                         x86_prefix (code, X86_FS_PREFIX);
6247                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6248
6249                         /* Save previous_lmf */
6250                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6251                         /* Set new lmf */
6252                         if (lmf_offset == 0) {
6253                                 x86_prefix (code, X86_FS_PREFIX);
6254                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6255                         } else {
6256                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6257                                 x86_prefix (code, X86_FS_PREFIX);
6258                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6259                         }
6260                 } else {
6261                         if (lmf_addr_tls_offset != -1) {
6262                                 /* Load lmf quicky using the FS register */
6263                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6264 #ifdef HOST_WIN32
6265                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6266                                 /* FIXME: Add a separate key for LMF to avoid this */
6267                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6268 #endif
6269                         }
6270                         else {
6271                                 /*
6272                                  * The call might clobber argument registers, but they are already
6273                                  * saved to the stack/global regs.
6274                                  */
6275                                 args_clobbered = TRUE;
6276                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6277                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6278                         }
6279
6280                         /* Save lmf_addr */
6281                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6282                         /* Save previous_lmf */
6283                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6284                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6285                         /* Set new lmf */
6286                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6287                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6288                 }
6289         }
6290
6291         if (trace) {
6292                 args_clobbered = TRUE;
6293                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6294         }
6295
6296         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6297                 args_clobbered = TRUE;
6298
6299         /*
6300          * Optimize the common case of the first bblock making a call with the same
6301          * arguments as the method. This works because the arguments are still in their
6302          * original argument registers.
6303          * FIXME: Generalize this
6304          */
6305         if (!args_clobbered) {
6306                 MonoBasicBlock *first_bb = cfg->bb_entry;
6307                 MonoInst *next;
6308
6309                 next = mono_bb_first_ins (first_bb);
6310                 if (!next && first_bb->next_bb) {
6311                         first_bb = first_bb->next_bb;
6312                         next = mono_bb_first_ins (first_bb);
6313                 }
6314
6315                 if (first_bb->in_count > 1)
6316                         next = NULL;
6317
6318                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6319                         ArgInfo *ainfo = cinfo->args + i;
6320                         gboolean match = FALSE;
6321
6322                         ins = cfg->args [i];
6323                         if (ins->opcode != OP_REGVAR) {
6324                                 switch (ainfo->storage) {
6325                                 case ArgInIReg: {
6326                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6327                                                 if (next->dreg == ainfo->reg) {
6328                                                         NULLIFY_INS (next);
6329                                                         match = TRUE;
6330                                                 } else {
6331                                                         next->opcode = OP_MOVE;
6332                                                         next->sreg1 = ainfo->reg;
6333                                                         /* Only continue if the instruction doesn't change argument regs */
6334                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6335                                                                 match = TRUE;
6336                                                 }
6337                                         }
6338                                         break;
6339                                 }
6340                                 default:
6341                                         break;
6342                                 }
6343                         } else {
6344                                 /* Argument allocated to (non-volatile) register */
6345                                 switch (ainfo->storage) {
6346                                 case ArgInIReg:
6347                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6348                                                 NULLIFY_INS (next);
6349                                                 match = TRUE;
6350                                         }
6351                                         break;
6352                                 default:
6353                                         break;
6354                                 }
6355                         }
6356
6357                         if (match) {
6358                                 next = next->next;
6359                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6360                                 if (!next)
6361                                         break;
6362                         }
6363                 }
6364         }
6365
6366         /* Initialize ss_trigger_page_var */
6367         if (cfg->arch.ss_trigger_page_var) {
6368                 MonoInst *var = cfg->arch.ss_trigger_page_var;
6369
6370                 g_assert (!cfg->compile_aot);
6371                 g_assert (var->opcode == OP_REGOFFSET);
6372
6373                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6374                 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
6375         }
6376
6377         cfg->code_len = code - cfg->native_code;
6378
6379         g_assert (cfg->code_len < cfg->code_size);
6380
6381         return code;
6382 }
6383
6384 void
6385 mono_arch_emit_epilog (MonoCompile *cfg)
6386 {
6387         MonoMethod *method = cfg->method;
6388         int quad, pos, i;
6389         guint8 *code;
6390         int max_epilog_size;
6391         CallInfo *cinfo;
6392         gint32 lmf_offset = cfg->arch.lmf_offset;
6393
6394         max_epilog_size = get_max_epilog_size (cfg);
6395
6396         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6397                 cfg->code_size *= 2;
6398                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6399                 mono_jit_stats.code_reallocs++;
6400         }
6401
6402         code = cfg->native_code + cfg->code_len;
6403
6404         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6405                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6406
6407         /* the code restoring the registers must be kept in sync with OP_JMP */
6408         pos = 0;
6409
6410         if (method->save_lmf) {
6411                 /* check if we need to restore protection of the stack after a stack overflow */
6412                 if (mono_get_jit_tls_offset () != -1) {
6413                         guint8 *patch;
6414                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6415                         /* we load the value in a separate instruction: this mechanism may be
6416                          * used later as a safer way to do thread interruption
6417                          */
6418                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6419                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6420                         patch = code;
6421                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6422                         /* note that the call trampoline will preserve eax/edx */
6423                         x86_call_reg (code, X86_ECX);
6424                         x86_patch (patch, code);
6425                 } else {
6426                         /* FIXME: maybe save the jit tls in the prolog */
6427                 }
6428                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6429                         /*
6430                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6431                          * through the mono_lmf_addr TLS variable.
6432                          */
6433                         /* reg = previous_lmf */
6434                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6435                         x86_prefix (code, X86_FS_PREFIX);
6436                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6437                 } else {
6438                         /* Restore previous lmf */
6439                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6440                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6441                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6442                 }
6443
6444                 /* Restore caller saved regs */
6445                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6446                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6447                 }
6448                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6449                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6450                 }
6451                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6452                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6453                 }
6454                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6455                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6456                 }
6457                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6458                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6459                 }
6460                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6461                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6462                 }
6463 #ifdef HOST_WIN32
6464                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6465                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6466                 }
6467                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6468                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6469                 }
6470 #endif
6471         } else {
6472
6473                 if (cfg->arch.omit_fp) {
6474                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6475
6476                         for (i = 0; i < AMD64_NREG; ++i)
6477                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6478                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6479                                         save_area_offset += 8;
6480                                 }
6481                 }
6482                 else {
6483                         for (i = 0; i < AMD64_NREG; ++i)
6484                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6485                                         pos -= sizeof (gpointer);
6486
6487                         if (pos) {
6488                                 if (pos == - sizeof (gpointer)) {
6489                                         /* Only one register, so avoid lea */
6490                                         for (i = AMD64_NREG - 1; i > 0; --i)
6491                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6492                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6493                                                 }
6494                                 }
6495                                 else {
6496                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6497
6498                                         /* Pop registers in reverse order */
6499                                         for (i = AMD64_NREG - 1; i > 0; --i)
6500                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6501                                                         amd64_pop_reg (code, i);
6502                                                 }
6503                                 }
6504                         }
6505                 }
6506         }
6507
6508         /* Load returned vtypes into registers if needed */
6509         cinfo = cfg->arch.cinfo;
6510         if (cinfo->ret.storage == ArgValuetypeInReg) {
6511                 ArgInfo *ainfo = &cinfo->ret;
6512                 MonoInst *inst = cfg->ret;
6513
6514                 for (quad = 0; quad < 2; quad ++) {
6515                         switch (ainfo->pair_storage [quad]) {
6516                         case ArgInIReg:
6517                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6518                                 break;
6519                         case ArgInFloatSSEReg:
6520                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6521                                 break;
6522                         case ArgInDoubleSSEReg:
6523                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6524                                 break;
6525                         case ArgNone:
6526                                 break;
6527                         default:
6528                                 g_assert_not_reached ();
6529                         }
6530                 }
6531         }
6532
6533         if (cfg->arch.omit_fp) {
6534                 if (cfg->arch.stack_alloc_size)
6535                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6536         } else {
6537                 amd64_leave (code);
6538         }
6539         async_exc_point (code);
6540         amd64_ret (code);
6541
6542         cfg->code_len = code - cfg->native_code;
6543
6544         g_assert (cfg->code_len < cfg->code_size);
6545 }
6546
6547 void
6548 mono_arch_emit_exceptions (MonoCompile *cfg)
6549 {
6550         MonoJumpInfo *patch_info;
6551         int nthrows, i;
6552         guint8 *code;
6553         MonoClass *exc_classes [16];
6554         guint8 *exc_throw_start [16], *exc_throw_end [16];
6555         guint32 code_size = 0;
6556
6557         /* Compute needed space */
6558         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6559                 if (patch_info->type == MONO_PATCH_INFO_EXC)
6560                         code_size += 40;
6561                 if (patch_info->type == MONO_PATCH_INFO_R8)
6562                         code_size += 8 + 15; /* sizeof (double) + alignment */
6563                 if (patch_info->type == MONO_PATCH_INFO_R4)
6564                         code_size += 4 + 15; /* sizeof (float) + alignment */
6565                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
6566                         code_size += 8 + 7; /*sizeof (void*) + alignment */
6567         }
6568
6569         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6570                 cfg->code_size *= 2;
6571                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6572                 mono_jit_stats.code_reallocs++;
6573         }
6574
6575         code = cfg->native_code + cfg->code_len;
6576
6577         /* add code to raise exceptions */
6578         nthrows = 0;
6579         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6580                 switch (patch_info->type) {
6581                 case MONO_PATCH_INFO_EXC: {
6582                         MonoClass *exc_class;
6583                         guint8 *buf, *buf2;
6584                         guint32 throw_ip;
6585
6586                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
6587
6588                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6589                         g_assert (exc_class);
6590                         throw_ip = patch_info->ip.i;
6591
6592                         //x86_breakpoint (code);
6593                         /* Find a throw sequence for the same exception class */
6594                         for (i = 0; i < nthrows; ++i)
6595                                 if (exc_classes [i] == exc_class)
6596                                         break;
6597                         if (i < nthrows) {
6598                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6599                                 x86_jump_code (code, exc_throw_start [i]);
6600                                 patch_info->type = MONO_PATCH_INFO_NONE;
6601                         }
6602                         else {
6603                                 buf = code;
6604                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6605                                 buf2 = code;
6606
6607                                 if (nthrows < 16) {
6608                                         exc_classes [nthrows] = exc_class;
6609                                         exc_throw_start [nthrows] = code;
6610                                 }
6611                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
6612
6613                                 patch_info->type = MONO_PATCH_INFO_NONE;
6614
6615                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6616
6617                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6618                                 while (buf < buf2)
6619                                         x86_nop (buf);
6620
6621                                 if (nthrows < 16) {
6622                                         exc_throw_end [nthrows] = code;
6623                                         nthrows ++;
6624                                 }
6625                         }
6626                         break;
6627                 }
6628                 default:
6629                         /* do nothing */
6630                         break;
6631                 }
6632         }
6633
6634         /* Handle relocations with RIP relative addressing */
6635         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6636                 gboolean remove = FALSE;
6637                 guint8 *orig_code = code;
6638
6639                 switch (patch_info->type) {
6640                 case MONO_PATCH_INFO_R8:
6641                 case MONO_PATCH_INFO_R4: {
6642                         guint8 *pos;
6643
6644                         /* The SSE opcodes require a 16 byte alignment */
6645                         code = (guint8*)ALIGN_TO (code, 16);
6646                         memset (orig_code, 0, code - orig_code);
6647
6648                         pos = cfg->native_code + patch_info->ip.i;
6649
6650                         if (IS_REX (pos [1]))
6651                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6652                         else
6653                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6654
6655                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6656                                 *(double*)code = *(double*)patch_info->data.target;
6657                                 code += sizeof (double);
6658                         } else {
6659                                 *(float*)code = *(float*)patch_info->data.target;
6660                                 code += sizeof (float);
6661                         }
6662
6663                         remove = TRUE;
6664                         break;
6665                 }
6666                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
6667                         guint8 *pos;
6668
6669                         if (cfg->compile_aot)
6670                                 continue;
6671
6672                         /*loading is faster against aligned addresses.*/
6673                         code = (guint8*)ALIGN_TO (code, 8);
6674                         memset (orig_code, 0, code - orig_code);
6675
6676                         pos = cfg->native_code + patch_info->ip.i;
6677
6678                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
6679                         if (IS_REX (pos [1]))
6680                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6681                         else
6682                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
6683
6684                         *(gpointer*)code = (gpointer)patch_info->data.target;
6685                         code += sizeof (gpointer);
6686
6687                         remove = TRUE;
6688                         break;
6689                 }
6690                 default:
6691                         break;
6692                 }
6693
6694                 if (remove) {
6695                         if (patch_info == cfg->patch_info)
6696                                 cfg->patch_info = patch_info->next;
6697                         else {
6698                                 MonoJumpInfo *tmp;
6699
6700                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6701                                         ;
6702                                 tmp->next = patch_info->next;
6703                         }
6704                 }
6705         }
6706
6707         cfg->code_len = code - cfg->native_code;
6708
6709         g_assert (cfg->code_len < cfg->code_size);
6710
6711 }
6712
6713 #endif /* DISABLE_JIT */
6714
6715 void*
6716 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6717 {
6718         guchar *code = p;
6719         CallInfo *cinfo = NULL;
6720         MonoMethodSignature *sig;
6721         MonoInst *inst;
6722         int i, n, stack_area = 0;
6723
6724         /* Keep this in sync with mono_arch_get_argument_info */
6725
6726         if (enable_arguments) {
6727                 /* Allocate a new area on the stack and save arguments there */
6728                 sig = mono_method_signature (cfg->method);
6729
6730                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
6731
6732                 n = sig->param_count + sig->hasthis;
6733
6734                 stack_area = ALIGN_TO (n * 8, 16);
6735
6736                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6737
6738                 for (i = 0; i < n; ++i) {
6739                         inst = cfg->args [i];
6740
6741                         if (inst->opcode == OP_REGVAR)
6742                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6743                         else {
6744                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6745                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6746                         }
6747                 }
6748         }
6749
6750         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6751         amd64_set_reg_template (code, AMD64_ARG_REG1);
6752         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6753         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6754
6755         if (enable_arguments)
6756                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6757
6758         return code;
6759 }
6760
6761 enum {
6762         SAVE_NONE,
6763         SAVE_STRUCT,
6764         SAVE_EAX,
6765         SAVE_EAX_EDX,
6766         SAVE_XMM
6767 };
6768
6769 void*
6770 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6771 {
6772         guchar *code = p;
6773         int save_mode = SAVE_NONE;
6774         MonoMethod *method = cfg->method;
6775         MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
6776
6777         switch (ret_type->type) {
6778         case MONO_TYPE_VOID:
6779                 /* special case string .ctor icall */
6780                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6781                         save_mode = SAVE_EAX;
6782                 else
6783                         save_mode = SAVE_NONE;
6784                 break;
6785         case MONO_TYPE_I8:
6786         case MONO_TYPE_U8:
6787                 save_mode = SAVE_EAX;
6788                 break;
6789         case MONO_TYPE_R4:
6790         case MONO_TYPE_R8:
6791                 save_mode = SAVE_XMM;
6792                 break;
6793         case MONO_TYPE_GENERICINST:
6794                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
6795                         save_mode = SAVE_EAX;
6796                         break;
6797                 }
6798                 /* Fall through */
6799         case MONO_TYPE_VALUETYPE:
6800                 save_mode = SAVE_STRUCT;
6801                 break;
6802         default:
6803                 save_mode = SAVE_EAX;
6804                 break;
6805         }
6806
6807         /* Save the result and copy it into the proper argument register */
6808         switch (save_mode) {
6809         case SAVE_EAX:
6810                 amd64_push_reg (code, AMD64_RAX);
6811                 /* Align stack */
6812                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6813                 if (enable_arguments)
6814                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6815                 break;
6816         case SAVE_STRUCT:
6817                 /* FIXME: */
6818                 if (enable_arguments)
6819                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6820                 break;
6821         case SAVE_XMM:
6822                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6823                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6824                 /* Align stack */
6825                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6826                 /*
6827                  * The result is already in the proper argument register so no copying
6828                  * needed.
6829                  */
6830                 break;
6831         case SAVE_NONE:
6832                 break;
6833         default:
6834                 g_assert_not_reached ();
6835         }
6836
6837         /* Set %al since this is a varargs call */
6838         if (save_mode == SAVE_XMM)
6839                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6840         else
6841                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6842
6843         if (preserve_argument_registers) {
6844                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6845                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6846         }
6847
6848         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6849         amd64_set_reg_template (code, AMD64_ARG_REG1);
6850         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6851
6852         if (preserve_argument_registers) {
6853                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6854                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6855         }
6856
6857         /* Restore result */
6858         switch (save_mode) {
6859         case SAVE_EAX:
6860                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6861                 amd64_pop_reg (code, AMD64_RAX);
6862                 break;
6863         case SAVE_STRUCT:
6864                 /* FIXME: */
6865                 break;
6866         case SAVE_XMM:
6867                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6868                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6869                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6870                 break;
6871         case SAVE_NONE:
6872                 break;
6873         default:
6874                 g_assert_not_reached ();
6875         }
6876
6877         return code;
6878 }
6879
6880 void
6881 mono_arch_flush_icache (guint8 *code, gint size)
6882 {
6883         /* Not needed */
6884 }
6885
6886 void
6887 mono_arch_flush_register_windows (void)
6888 {
6889 }
6890
6891 gboolean
6892 mono_arch_is_inst_imm (gint64 imm)
6893 {
6894         return amd64_is_imm32 (imm);
6895 }
6896
6897 /*
6898  * Determine whenever the trap whose info is in SIGINFO is caused by
6899  * integer overflow.
6900  */
6901 gboolean
6902 mono_arch_is_int_overflow (void *sigctx, void *info)
6903 {
6904         MonoContext ctx;
6905         guint8* rip;
6906         int reg;
6907         gint64 value;
6908
6909         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6910
6911         rip = (guint8*)ctx.rip;
6912
6913         if (IS_REX (rip [0])) {
6914                 reg = amd64_rex_b (rip [0]);
6915                 rip ++;
6916         }
6917         else
6918                 reg = 0;
6919
6920         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6921                 /* idiv REG */
6922                 reg += x86_modrm_rm (rip [1]);
6923
6924                 switch (reg) {
6925                 case AMD64_RAX:
6926                         value = ctx.rax;
6927                         break;
6928                 case AMD64_RBX:
6929                         value = ctx.rbx;
6930                         break;
6931                 case AMD64_RCX:
6932                         value = ctx.rcx;
6933                         break;
6934                 case AMD64_RDX:
6935                         value = ctx.rdx;
6936                         break;
6937                 case AMD64_RBP:
6938                         value = ctx.rbp;
6939                         break;
6940                 case AMD64_RSP:
6941                         value = ctx.rsp;
6942                         break;
6943                 case AMD64_RSI:
6944                         value = ctx.rsi;
6945                         break;
6946                 case AMD64_RDI:
6947                         value = ctx.rdi;
6948                         break;
6949                 case AMD64_R12:
6950                         value = ctx.r12;
6951                         break;
6952                 case AMD64_R13:
6953                         value = ctx.r13;
6954                         break;
6955                 case AMD64_R14:
6956                         value = ctx.r14;
6957                         break;
6958                 case AMD64_R15:
6959                         value = ctx.r15;
6960                         break;
6961                 default:
6962                         g_assert_not_reached ();
6963                         reg = -1;
6964                 }
6965
6966                 if (value == -1)
6967                         return TRUE;
6968         }
6969
6970         return FALSE;
6971 }
6972
6973 guint32
6974 mono_arch_get_patch_offset (guint8 *code)
6975 {
6976         return 3;
6977 }
6978
6979 /**
6980  * mono_breakpoint_clean_code:
6981  *
6982  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6983  * breakpoints in the original code, they are removed in the copy.
6984  *
6985  * Returns TRUE if no sw breakpoint was present.
6986  */
6987 gboolean
6988 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6989 {
6990         int i;
6991         gboolean can_write = TRUE;
6992         /*
6993          * If method_start is non-NULL we need to perform bound checks, since we access memory
6994          * at code - offset we could go before the start of the method and end up in a different
6995          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6996          * instead.
6997          */
6998         if (!method_start || code - offset >= method_start) {
6999                 memcpy (buf, code - offset, size);
7000         } else {
7001                 int diff = code - method_start;
7002                 memset (buf, 0, size);
7003                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7004         }
7005         code -= offset;
7006         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7007                 int idx = mono_breakpoint_info_index [i];
7008                 guint8 *ptr;
7009                 if (idx < 1)
7010                         continue;
7011                 ptr = mono_breakpoint_info [idx].address;
7012                 if (ptr >= code && ptr < code + size) {
7013                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7014                         can_write = FALSE;
7015                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7016                         buf [ptr - code] = saved_byte;
7017                 }
7018         }
7019         return can_write;
7020 }
7021
7022 int
7023 mono_arch_get_this_arg_reg (guint8 *code)
7024 {
7025         return AMD64_ARG_REG1;
7026 }
7027
7028 gpointer
7029 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7030 {
7031         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7032 }
7033
7034 #define MAX_ARCH_DELEGATE_PARAMS 10
7035
7036 static gpointer
7037 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7038 {
7039         guint8 *code, *start;
7040         int i;
7041
7042         if (has_target) {
7043                 start = code = mono_global_codeman_reserve (64);
7044
7045                 /* Replace the this argument with the target */
7046                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7047                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7048                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7049
7050                 g_assert ((code - start) < 64);
7051         } else {
7052                 start = code = mono_global_codeman_reserve (64);
7053
7054                 if (param_count == 0) {
7055                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7056                 } else {
7057                         /* We have to shift the arguments left */
7058                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7059                         for (i = 0; i < param_count; ++i) {
7060 #ifdef HOST_WIN32
7061                                 if (i < 3)
7062                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7063                                 else
7064                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7065 #else
7066                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7067 #endif
7068                         }
7069
7070                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7071                 }
7072                 g_assert ((code - start) < 64);
7073         }
7074
7075         mono_debug_add_delegate_trampoline (start, code - start);
7076
7077         if (code_len)
7078                 *code_len = code - start;
7079
7080
7081         if (mono_jit_map_is_enabled ()) {
7082                 char *buff;
7083                 if (has_target)
7084                         buff = (char*)"delegate_invoke_has_target";
7085                 else
7086                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7087                 mono_emit_jit_tramp (start, code - start, buff);
7088                 if (!has_target)
7089                         g_free (buff);
7090         }
7091
7092         return start;
7093 }
7094
7095 /*
7096  * mono_arch_get_delegate_invoke_impls:
7097  *
7098  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7099  * trampolines.
7100  */
7101 GSList*
7102 mono_arch_get_delegate_invoke_impls (void)
7103 {
7104         GSList *res = NULL;
7105         guint8 *code;
7106         guint32 code_len;
7107         int i;
7108
7109         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7110         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7111
7112         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7113                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7114                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7115         }
7116
7117         return res;
7118 }
7119
7120 gpointer
7121 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7122 {
7123         guint8 *code, *start;
7124         int i;
7125
7126         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7127                 return NULL;
7128
7129         /* FIXME: Support more cases */
7130         if (MONO_TYPE_ISSTRUCT (sig->ret))
7131                 return NULL;
7132
7133         if (has_target) {
7134                 static guint8* cached = NULL;
7135
7136                 if (cached)
7137                         return cached;
7138
7139                 if (mono_aot_only)
7140                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7141                 else
7142                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7143
7144                 mono_memory_barrier ();
7145
7146                 cached = start;
7147         } else {
7148                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7149                 for (i = 0; i < sig->param_count; ++i)
7150                         if (!mono_is_regsize_var (sig->params [i]))
7151                                 return NULL;
7152                 if (sig->param_count > 4)
7153                         return NULL;
7154
7155                 code = cache [sig->param_count];
7156                 if (code)
7157                         return code;
7158
7159                 if (mono_aot_only) {
7160                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7161                         start = mono_aot_get_trampoline (name);
7162                         g_free (name);
7163                 } else {
7164                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7165                 }
7166
7167                 mono_memory_barrier ();
7168
7169                 cache [sig->param_count] = start;
7170         }
7171
7172         return start;
7173 }
7174
7175 /*
7176  * Support for fast access to the thread-local lmf structure using the GS
7177  * segment register on NPTL + kernel 2.6.x.
7178  */
7179
7180 static gboolean tls_offset_inited = FALSE;
7181
7182 void
7183 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7184 {
7185         if (!tls_offset_inited) {
7186 #ifdef HOST_WIN32
7187                 /*
7188                  * We need to init this multiple times, since when we are first called, the key might not
7189                  * be initialized yet.
7190                  */
7191                 appdomain_tls_offset = mono_domain_get_tls_key ();
7192                 lmf_tls_offset = mono_get_jit_tls_key ();
7193                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7194
7195                 /* Only 64 tls entries can be accessed using inline code */
7196                 if (appdomain_tls_offset >= 64)
7197                         appdomain_tls_offset = -1;
7198                 if (lmf_tls_offset >= 64)
7199                         lmf_tls_offset = -1;
7200 #else
7201                 tls_offset_inited = TRUE;
7202 #ifdef MONO_XEN_OPT
7203                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7204 #endif
7205                 appdomain_tls_offset = mono_domain_get_tls_offset ();
7206                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7207                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7208 #endif
7209         }
7210 }
7211
7212 void
7213 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7214 {
7215 }
7216
7217 #ifdef MONO_ARCH_HAVE_IMT
7218
7219 #define CMP_SIZE (6 + 1)
7220 #define CMP_REG_REG_SIZE (4 + 1)
7221 #define BR_SMALL_SIZE 2
7222 #define BR_LARGE_SIZE 6
7223 #define MOV_REG_IMM_SIZE 10
7224 #define MOV_REG_IMM_32BIT_SIZE 6
7225 #define JUMP_REG_SIZE (2 + 1)
7226
7227 static int
7228 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7229 {
7230         int i, distance = 0;
7231         for (i = start; i < target; ++i)
7232                 distance += imt_entries [i]->chunk_size;
7233         return distance;
7234 }
7235
7236 /*
7237  * LOCKING: called with the domain lock held
7238  */
7239 gpointer
7240 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7241         gpointer fail_tramp)
7242 {
7243         int i;
7244         int size = 0;
7245         guint8 *code, *start;
7246         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7247
7248         for (i = 0; i < count; ++i) {
7249                 MonoIMTCheckItem *item = imt_entries [i];
7250                 if (item->is_equals) {
7251                         if (item->check_target_idx) {
7252                                 if (!item->compare_done) {
7253                                         if (amd64_is_imm32 (item->key))
7254                                                 item->chunk_size += CMP_SIZE;
7255                                         else
7256                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7257                                 }
7258                                 if (item->has_target_code) {
7259                                         item->chunk_size += MOV_REG_IMM_SIZE;
7260                                 } else {
7261                                         if (vtable_is_32bit)
7262                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7263                                         else
7264                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7265                                 }
7266                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7267                         } else {
7268                                 if (fail_tramp) {
7269                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7270                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7271                                 } else {
7272                                         if (vtable_is_32bit)
7273                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7274                                         else
7275                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7276                                         item->chunk_size += JUMP_REG_SIZE;
7277                                         /* with assert below:
7278                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7279                                          */
7280                                 }
7281                         }
7282                 } else {
7283                         if (amd64_is_imm32 (item->key))
7284                                 item->chunk_size += CMP_SIZE;
7285                         else
7286                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7287                         item->chunk_size += BR_LARGE_SIZE;
7288                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7289                 }
7290                 size += item->chunk_size;
7291         }
7292         if (fail_tramp)
7293                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7294         else
7295                 code = mono_domain_code_reserve (domain, size);
7296         start = code;
7297         for (i = 0; i < count; ++i) {
7298                 MonoIMTCheckItem *item = imt_entries [i];
7299                 item->code_target = code;
7300                 if (item->is_equals) {
7301                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7302
7303                         if (item->check_target_idx || fail_case) {
7304                                 if (!item->compare_done || fail_case) {
7305                                         if (amd64_is_imm32 (item->key))
7306                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7307                                         else {
7308                                                 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7309                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7310                                         }
7311                                 }
7312                                 item->jmp_code = code;
7313                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7314                                 if (item->has_target_code) {
7315                                         amd64_mov_reg_imm (code, AMD64_R11, item->value.target_code);
7316                                         amd64_jump_reg (code, AMD64_R11);
7317                                 } else {
7318                                         amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7319                                         amd64_jump_membase (code, AMD64_R11, 0);
7320                                 }
7321
7322                                 if (fail_case) {
7323                                         amd64_patch (item->jmp_code, code);
7324                                         amd64_mov_reg_imm (code, AMD64_R11, fail_tramp);
7325                                         amd64_jump_reg (code, AMD64_R11);
7326                                         item->jmp_code = NULL;
7327                                 }
7328                         } else {
7329                                 /* enable the commented code to assert on wrong method */
7330 #if 0
7331                                 if (amd64_is_imm32 (item->key))
7332                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7333                                 else {
7334                                         amd64_mov_reg_imm (code, AMD64_R11, item->key);
7335                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7336                                 }
7337                                 item->jmp_code = code;
7338                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7339                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7340                                 amd64_jump_membase (code, AMD64_R11, 0);
7341                                 amd64_patch (item->jmp_code, code);
7342                                 amd64_breakpoint (code);
7343                                 item->jmp_code = NULL;
7344 #else
7345                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7346                                 amd64_jump_membase (code, AMD64_R11, 0);
7347 #endif
7348                         }
7349                 } else {
7350                         if (amd64_is_imm32 (item->key))
7351                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7352                         else {
7353                                 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7354                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7355                         }
7356                         item->jmp_code = code;
7357                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7358                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7359                         else
7360                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7361                 }
7362                 g_assert (code - item->code_target <= item->chunk_size);
7363         }
7364         /* patch the branches to get to the target items */
7365         for (i = 0; i < count; ++i) {
7366                 MonoIMTCheckItem *item = imt_entries [i];
7367                 if (item->jmp_code) {
7368                         if (item->check_target_idx) {
7369                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7370                         }
7371                 }
7372         }
7373
7374         if (!fail_tramp)
7375                 mono_stats.imt_thunks_size += code - start;
7376         g_assert (code - start <= size);
7377
7378         return start;
7379 }
7380
7381 MonoMethod*
7382 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7383 {
7384         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7385 }
7386 #endif
7387
7388 MonoVTable*
7389 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7390 {
7391         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7392 }
7393
7394 GSList*
7395 mono_arch_get_cie_program (void)
7396 {
7397         GSList *l = NULL;
7398
7399         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
7400         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
7401
7402         return l;
7403 }
7404
7405 MonoInst*
7406 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7407 {
7408         MonoInst *ins = NULL;
7409         int opcode = 0;
7410
7411         if (cmethod->klass == mono_defaults.math_class) {
7412                 if (strcmp (cmethod->name, "Sin") == 0) {
7413                         opcode = OP_SIN;
7414                 } else if (strcmp (cmethod->name, "Cos") == 0) {
7415                         opcode = OP_COS;
7416                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7417                         opcode = OP_SQRT;
7418                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7419                         opcode = OP_ABS;
7420                 }
7421
7422                 if (opcode) {
7423                         MONO_INST_NEW (cfg, ins, opcode);
7424                         ins->type = STACK_R8;
7425                         ins->dreg = mono_alloc_freg (cfg);
7426                         ins->sreg1 = args [0]->dreg;
7427                         MONO_ADD_INS (cfg->cbb, ins);
7428                 }
7429
7430                 opcode = 0;
7431                 if (cfg->opt & MONO_OPT_CMOV) {
7432                         if (strcmp (cmethod->name, "Min") == 0) {
7433                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7434                                         opcode = OP_IMIN;
7435                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7436                                         opcode = OP_IMIN_UN;
7437                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7438                                         opcode = OP_LMIN;
7439                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7440                                         opcode = OP_LMIN_UN;
7441                         } else if (strcmp (cmethod->name, "Max") == 0) {
7442                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7443                                         opcode = OP_IMAX;
7444                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7445                                         opcode = OP_IMAX_UN;
7446                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7447                                         opcode = OP_LMAX;
7448                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7449                                         opcode = OP_LMAX_UN;
7450                         }
7451                 }
7452
7453                 if (opcode) {
7454                         MONO_INST_NEW (cfg, ins, opcode);
7455                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7456                         ins->dreg = mono_alloc_ireg (cfg);
7457                         ins->sreg1 = args [0]->dreg;
7458                         ins->sreg2 = args [1]->dreg;
7459                         MONO_ADD_INS (cfg->cbb, ins);
7460                 }
7461
7462 #if 0
7463                 /* OP_FREM is not IEEE compatible */
7464                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7465                         MONO_INST_NEW (cfg, ins, OP_FREM);
7466                         ins->inst_i0 = args [0];
7467                         ins->inst_i1 = args [1];
7468                 }
7469 #endif
7470         }
7471
7472         /*
7473          * Can't implement CompareExchange methods this way since they have
7474          * three arguments.
7475          */
7476
7477         return ins;
7478 }
7479
7480 gboolean
7481 mono_arch_print_tree (MonoInst *tree, int arity)
7482 {
7483         return 0;
7484 }
7485
7486 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7487 {
7488         MonoInst* ins;
7489
7490         if (appdomain_tls_offset == -1)
7491                 return NULL;
7492
7493         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7494         ins->inst_offset = appdomain_tls_offset;
7495         return ins;
7496 }
7497
7498 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7499
7500 gpointer
7501 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7502 {
7503         switch (reg) {
7504         case AMD64_RCX: return (gpointer)ctx->rcx;
7505         case AMD64_RDX: return (gpointer)ctx->rdx;
7506         case AMD64_RBX: return (gpointer)ctx->rbx;
7507         case AMD64_RBP: return (gpointer)ctx->rbp;
7508         case AMD64_RSP: return (gpointer)ctx->rsp;
7509         default:
7510                 if (reg < 8)
7511                         return _CTX_REG (ctx, rax, reg);
7512                 else if (reg >= 12)
7513                         return _CTX_REG (ctx, r12, reg - 12);
7514                 else
7515                         g_assert_not_reached ();
7516         }
7517 }
7518
7519 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
7520 gpointer
7521 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7522 {
7523         int offset;
7524         gpointer *sp, old_value;
7525         char *bp;
7526         const unsigned char *handler;
7527
7528         /*Decode the first instruction to figure out where did we store the spvar*/
7529         /*Our jit MUST generate the following:
7530          mov    %rsp, ?(%rbp)
7531
7532          Which is encoded as: REX.W 0x89 mod_rm
7533          mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
7534                 mod (reg + imm8):  01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
7535                 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
7536
7537         FIXME can we generate frameless methods on this case?
7538
7539         */
7540         handler = clause->handler_start;
7541
7542         /*REX.W*/
7543         if (*handler != 0x48)
7544                 return NULL;
7545         ++handler;
7546
7547         /*mov r, r/m */
7548         if (*handler != 0x89)
7549                 return NULL;
7550         ++handler;
7551
7552         if (*handler == 0x65)
7553                 offset = *(signed char*)(handler + 1);
7554         else if (*handler == 0xA5)
7555                 offset = *(int*)(handler + 1);
7556         else
7557                 return NULL;
7558
7559         /*Load the spvar*/
7560         bp = MONO_CONTEXT_GET_BP (ctx);
7561         sp = *(gpointer*)(bp + offset);
7562
7563         old_value = *sp;
7564         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7565                 return old_value;
7566
7567         *sp = new_value;
7568
7569         return old_value;
7570 }
7571
7572 /*
7573  * mono_arch_emit_load_aotconst:
7574  *
7575  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
7576  * TARGET from the mscorlib GOT in full-aot code.
7577  * On AMD64, the result is placed into R11.
7578  */
7579 guint8*
7580 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
7581 {
7582         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
7583         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
7584
7585         return code;
7586 }
7587
7588 /*
7589  * mono_arch_get_trampolines:
7590  *
7591  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
7592  * for AOT.
7593  */
7594 GSList *
7595 mono_arch_get_trampolines (gboolean aot)
7596 {
7597         MonoTrampInfo *info;
7598         GSList *tramps = NULL;
7599
7600         mono_arch_get_throw_pending_exception (&info, aot);
7601
7602         tramps = g_slist_append (tramps, info);
7603
7604         return tramps;
7605 }
7606
7607 /* Soft Debug support */
7608 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7609
7610 /*
7611  * mono_arch_set_breakpoint:
7612  *
7613  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7614  * The location should contain code emitted by OP_SEQ_POINT.
7615  */
7616 void
7617 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7618 {
7619         guint8 *code = ip;
7620         guint8 *orig_code = code;
7621
7622         /*
7623          * In production, we will use int3 (has to fix the size in the md
7624          * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7625          * instead.
7626          */
7627         g_assert (code [0] == 0x90);
7628         if (breakpoint_size == 8) {
7629                 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7630         } else {
7631                 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
7632                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
7633         }
7634
7635         g_assert (code - orig_code == breakpoint_size);
7636 }
7637
7638 /*
7639  * mono_arch_clear_breakpoint:
7640  *
7641  *   Clear the breakpoint at IP.
7642  */
7643 void
7644 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7645 {
7646         guint8 *code = ip;
7647         int i;
7648
7649         for (i = 0; i < breakpoint_size; ++i)
7650                 x86_nop (code);
7651 }
7652
7653 gboolean
7654 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7655 {
7656 #ifdef HOST_WIN32
7657         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7658         return FALSE;
7659 #else
7660         siginfo_t* sinfo = (siginfo_t*) info;
7661         /* Sometimes the address is off by 4 */
7662         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7663                 return TRUE;
7664         else
7665                 return FALSE;
7666 #endif
7667 }
7668
7669 /*
7670  * mono_arch_get_ip_for_breakpoint:
7671  *
7672  *   Convert the ip in CTX to the address where a breakpoint was placed.
7673  */
7674 guint8*
7675 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7676 {
7677         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7678
7679         /* ip points to the instruction causing the fault */
7680         ip -= (breakpoint_size - breakpoint_fault_size);
7681
7682         return ip;
7683 }
7684
7685 /*
7686  * mono_arch_skip_breakpoint:
7687  *
7688  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
7689  * we resume, the instruction is not executed again.
7690  */
7691 void
7692 mono_arch_skip_breakpoint (MonoContext *ctx)
7693 {
7694         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
7695 }
7696
7697 /*
7698  * mono_arch_start_single_stepping:
7699  *
7700  *   Start single stepping.
7701  */
7702 void
7703 mono_arch_start_single_stepping (void)
7704 {
7705         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7706 }
7707
7708 /*
7709  * mono_arch_stop_single_stepping:
7710  *
7711  *   Stop single stepping.
7712  */
7713 void
7714 mono_arch_stop_single_stepping (void)
7715 {
7716         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7717 }
7718
7719 /*
7720  * mono_arch_is_single_step_event:
7721  *
7722  *   Return whenever the machine state in SIGCTX corresponds to a single
7723  * step event.
7724  */
7725 gboolean
7726 mono_arch_is_single_step_event (void *info, void *sigctx)
7727 {
7728 #ifdef HOST_WIN32
7729         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7730         return FALSE;
7731 #else
7732         siginfo_t* sinfo = (siginfo_t*) info;
7733         /* Sometimes the address is off by 4 */
7734         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7735                 return TRUE;
7736         else
7737                 return FALSE;
7738 #endif
7739 }
7740
7741 /*
7742  * mono_arch_get_ip_for_single_step:
7743  *
7744  *   Convert the ip in CTX to the address stored in seq_points.
7745  */
7746 guint8*
7747 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7748 {
7749         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7750
7751         ip += single_step_fault_size;
7752
7753         return ip;
7754 }
7755
7756 /*
7757  * mono_arch_skip_single_step:
7758  *
7759  *   Modify CTX so the ip is placed after the single step trigger instruction,
7760  * we resume, the instruction is not executed again.
7761  */
7762 void
7763 mono_arch_skip_single_step (MonoContext *ctx)
7764 {
7765         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
7766 }
7767
7768 /*
7769  * mono_arch_create_seq_point_info:
7770  *
7771  *   Return a pointer to a data structure which is used by the sequence
7772  * point implementation in AOTed code.
7773  */
7774 gpointer
7775 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7776 {
7777         NOT_IMPLEMENTED;
7778         return NULL;
7779 }
7780
7781 #endif