mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 /*
  72  * The code generated for sequence points reads from this location, which is
  73  * made read-only when single stepping is enabled.
  74  */
  75 static gpointer ss_trigger_page;
  76
  77 /* Enabled breakpoints read from this trigger page */
  78 static gpointer bp_trigger_page;
  79
  80 /* The size of the breakpoint sequence */
  81 static int breakpoint_size;
  82
  83 /* The size of the breakpoint instruction causing the actual fault */
  84 static int breakpoint_fault_size;
  85
  86 /* The size of the single step instruction causing the actual fault */
  87 static int single_step_fault_size;
  88
  89 /* The single step trampoline */
  90 static gpointer ss_trampoline;
  91
  92 /* Offset between fp and the first argument in the callee */
  93 #define ARGS_OFFSET 16
  94 #define GP_SCRATCH_REG AMD64_R11
  95
  96 /*
  97  * AMD64 register usage:
  98  * - callee saved registers are used for global register allocation
  99  * - %r11 is used for materializing 64 bit constants in opcodes
 100  * - the rest is used for local allocation
 101  */
 102
 103 /*
 104  * Floating point comparison results:
 105  *                  ZF PF CF
 106  * A > B            0  0  0
 107  * A < B            0  0  1
 108  * A = B            1  0  0
 109  * A > B            0  0  0
 110  * UNORDERED        1  1  1
 111  */
 112
 113 const char*
 114 mono_arch_regname (int reg)
 115 {
 116         switch (reg) {
 117         case AMD64_RAX: return "%rax";
 118         case AMD64_RBX: return "%rbx";
 119         case AMD64_RCX: return "%rcx";
 120         case AMD64_RDX: return "%rdx";
 121         case AMD64_RSP: return "%rsp";
 122         case AMD64_RBP: return "%rbp";
 123         case AMD64_RDI: return "%rdi";
 124         case AMD64_RSI: return "%rsi";
 125         case AMD64_R8: return "%r8";
 126         case AMD64_R9: return "%r9";
 127         case AMD64_R10: return "%r10";
 128         case AMD64_R11: return "%r11";
 129         case AMD64_R12: return "%r12";
 130         case AMD64_R13: return "%r13";
 131         case AMD64_R14: return "%r14";
 132         case AMD64_R15: return "%r15";
 133         }
 134         return "unknown";
 135 }
 136
 137 static const char * packed_xmmregs [] = {
 138         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 139         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 140 };
 141
 142 static const char * single_xmmregs [] = {
 143         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 144         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 145 };
 146
 147 const char*
 148 mono_arch_fregname (int reg)
 149 {
 150         if (reg < AMD64_XMM_NREG)
 151                 return single_xmmregs [reg];
 152         else
 153                 return "unknown";
 154 }
 155
 156 const char *
 157 mono_arch_xregname (int reg)
 158 {
 159         if (reg < AMD64_XMM_NREG)
 160                 return packed_xmmregs [reg];
 161         else
 162                 return "unknown";
 163 }
 164
 165 static gboolean
 166 debug_omit_fp (void)
 167 {
 168 #if 0
 169         return mono_debug_count ();
 170 #else
 171         return TRUE;
 172 #endif
 173 }
 174
 175 static inline gboolean
 176 amd64_is_near_call (guint8 *code)
 177 {
 178         /* Skip REX */
 179         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 180                 code += 1;
 181
 182         return code [0] == 0xe8;
 183 }
 184
 185 #ifdef __native_client_codegen__
 186
 187 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 188 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 189 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 190 /* We only want to force bundle alignment for the top level instruction,    */
 191 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 192 static MonoNativeTlsKey nacl_instruction_depth;
 193
 194 static MonoNativeTlsKey nacl_rex_tag;
 195 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 196
 197 void
 198 amd64_nacl_clear_legacy_prefix_tag ()
 199 {
 200         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 201 }
 202
 203 void
 204 amd64_nacl_tag_legacy_prefix (guint8* code)
 205 {
 206         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 207                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 208 }
 209
 210 void
 211 amd64_nacl_tag_rex (guint8* code)
 212 {
 213         mono_native_tls_set_value (nacl_rex_tag, code);
 214 }
 215
 216 guint8*
 217 amd64_nacl_get_legacy_prefix_tag ()
 218 {
 219         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 220 }
 221
 222 guint8*
 223 amd64_nacl_get_rex_tag ()
 224 {
 225         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 226 }
 227
 228 /* Increment the instruction "depth" described above */
 229 void
 230 amd64_nacl_instruction_pre ()
 231 {
 232         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 233         depth++;
 234         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 235 }
 236
 237 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 238 /* alignment if depth == 0 (top level instruction)                          */
 239 /* IN: start, end    pointers to instruction beginning and end              */
 240 /* OUT: start, end   pointers to beginning and end after possible alignment */
 241 /* GLOBALS: nacl_instruction_depth     defined above                        */
 242 void
 243 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 244 {
 245         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 246         depth--;
 247         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 248
 249         g_assert ( depth >= 0 );
 250         if (depth == 0) {
 251                 uintptr_t space_in_block;
 252                 uintptr_t instlen;
 253                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 254                 /* if legacy prefix is present, and if it was emitted before */
 255                 /* the start of the instruction sequence, adjust the start   */
 256                 if (prefix != NULL && prefix < *start) {
 257                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 258                         *start = prefix;
 259                 }
 260                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 261                 instlen = (uintptr_t)(*end - *start);
 262                 /* Only check for instructions which are less than        */
 263                 /* kNaClAlignment. The only instructions that should ever */
 264                 /* be that long are call sequences, which are already     */
 265                 /* padded out to align the return to the next bundle.     */
 266                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 267                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 268                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 269                         const size_t length = (size_t)((*end)-(*start));
 270                         g_assert (length < MAX_NACL_INST_LENGTH);
 271
 272                         memcpy (copy_of_instruction, *start, length);
 273                         *start = mono_arch_nacl_pad (*start, space_in_block);
 274                         memcpy (*start, copy_of_instruction, length);
 275                         *end = *start + length;
 276                 }
 277                 amd64_nacl_clear_legacy_prefix_tag ();
 278                 amd64_nacl_tag_rex (NULL);
 279         }
 280 }
 281
 282 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 283 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 284 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 285 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 286 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 287 /* IN:      code                                                            */
 288 /*             pointer to current instruction stream (in the                */
 289 /*             middle of an instruction, after opcode is emitted)           */
 290 /*          basereg/offset/dreg                                             */
 291 /*             operands of normal membase address                           */
 292 /* OUT:     code                                                            */
 293 /*             pointer to the end of the membase/memindex emit              */
 294 /* GLOBALS: nacl_rex_tag                                                    */
 295 /*             position in instruction stream that rex prefix was emitted   */
 296 /*          nacl_legacy_prefix_tag                                          */
 297 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 298 void
 299 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 300 {
 301         gint8 true_basereg = basereg;
 302
 303         /* Cache these values, they might change  */
 304         /* as new instructions are emitted below. */
 305         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 306         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 307
 308         /* 'basereg' is given masked to 0x7 at this point, so check */
 309         /* the rex prefix to see if this is an extended register.   */
 310         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 311                 true_basereg |= 0x8;
 312         }
 313
 314 #define X86_LEA_OPCODE (0x8D)
 315
 316         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 317                 guint8* old_instruction_start;
 318
 319                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 320                 /* 32-bits of the old base register (new index register)     */
 321                 guint8 buf[32];
 322                 guint8* buf_ptr = buf;
 323                 size_t insert_len;
 324
 325                 g_assert (rex_tag != NULL);
 326
 327                 if (IS_REX(*rex_tag)) {
 328                         /* The old rex.B should be the new rex.X */
 329                         if (*rex_tag & AMD64_REX_B) {
 330                                 *rex_tag |= AMD64_REX_X;
 331                         }
 332                         /* Since our new base is %r15 set rex.B */
 333                         *rex_tag |= AMD64_REX_B;
 334                 } else {
 335                         /* Shift the instruction by one byte  */
 336                         /* so we can insert a rex prefix      */
 337                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 338                         *code += 1;
 339                         /* New rex prefix only needs rex.B for %r15 base */
 340                         *rex_tag = AMD64_REX(AMD64_REX_B);
 341                 }
 342
 343                 if (legacy_prefix_tag) {
 344                         old_instruction_start = legacy_prefix_tag;
 345                 } else {
 346                         old_instruction_start = rex_tag;
 347                 }
 348
 349                 /* Clears the upper 32-bits of the previous base register */
 350                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 351                 insert_len = buf_ptr - buf;
 352
 353                 /* Move the old instruction forward to make */
 354                 /* room for 'mov' stored in 'buf_ptr'       */
 355                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 356                 *code += insert_len;
 357                 memcpy (old_instruction_start, buf, insert_len);
 358
 359                 /* Sandboxed replacement for the normal membase_emit */
 360                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 361
 362         } else {
 363                 /* Normal default behavior, emit membase memory location */
 364                 x86_membase_emit_body (*code, dreg, basereg, offset);
 365         }
 366 }
 367
 368
 369 static inline unsigned char*
 370 amd64_skip_nops (unsigned char* code)
 371 {
 372         guint8 in_nop;
 373         do {
 374                 in_nop = 0;
 375                 if (   code[0] == 0x90) {
 376                         in_nop = 1;
 377                         code += 1;
 378                 }
 379                 if (   code[0] == 0x66 && code[1] == 0x90) {
 380                         in_nop = 1;
 381                         code += 2;
 382                 }
 383                 if (code[0] == 0x0f && code[1] == 0x1f
 384                  && code[2] == 0x00) {
 385                         in_nop = 1;
 386                         code += 3;
 387                 }
 388                 if (code[0] == 0x0f && code[1] == 0x1f
 389                  && code[2] == 0x40 && code[3] == 0x00) {
 390                         in_nop = 1;
 391                         code += 4;
 392                 }
 393                 if (code[0] == 0x0f && code[1] == 0x1f
 394                  && code[2] == 0x44 && code[3] == 0x00
 395                  && code[4] == 0x00) {
 396                         in_nop = 1;
 397                         code += 5;
 398                 }
 399                 if (code[0] == 0x66 && code[1] == 0x0f
 400                  && code[2] == 0x1f && code[3] == 0x44
 401                  && code[4] == 0x00 && code[5] == 0x00) {
 402                         in_nop = 1;
 403                         code += 6;
 404                 }
 405                 if (code[0] == 0x0f && code[1] == 0x1f
 406                  && code[2] == 0x80 && code[3] == 0x00
 407                  && code[4] == 0x00 && code[5] == 0x00
 408                  && code[6] == 0x00) {
 409                         in_nop = 1;
 410                         code += 7;
 411                 }
 412                 if (code[0] == 0x0f && code[1] == 0x1f
 413                  && code[2] == 0x84 && code[3] == 0x00
 414                  && code[4] == 0x00 && code[5] == 0x00
 415                  && code[6] == 0x00 && code[7] == 0x00) {
 416                         in_nop = 1;
 417                         code += 8;
 418                 }
 419         } while ( in_nop );
 420         return code;
 421 }
 422
 423 guint8*
 424 mono_arch_nacl_skip_nops (guint8* code)
 425 {
 426   return amd64_skip_nops(code);
 427 }
 428
 429 #endif /*__native_client_codegen__*/
 430
 431 static inline void
 432 amd64_patch (unsigned char* code, gpointer target)
 433 {
 434         guint8 rex = 0;
 435
 436 #ifdef __native_client_codegen__
 437         code = amd64_skip_nops (code);
 438 #endif
 439 #if defined(__native_client_codegen__) && defined(__native_client__)
 440         if (nacl_is_code_address (code)) {
 441                 /* For tail calls, code is patched after being installed */
 442                 /* but not through the normal "patch callsite" method.   */
 443                 unsigned char buf[kNaClAlignment];
 444                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 445                 int ret;
 446                 memcpy (buf, aligned_code, kNaClAlignment);
 447                 /* Patch a temp buffer of bundle size, */
 448                 /* then install to actual location.    */
 449                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 450                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 451                 g_assert (ret == 0);
 452                 return;
 453         }
 454         target = nacl_modify_patch_target (target);
 455 #endif
 456
 457         /* Skip REX */
 458         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 459                 rex = code [0];
 460                 code += 1;
 461         }
 462
 463         if ((code [0] & 0xf8) == 0xb8) {
 464                 /* amd64_set_reg_template */
 465                 *(guint64*)(code + 1) = (guint64)target;
 466         }
 467         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 468                 /* mov 0(%rip), %dreg */
 469                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 470         }
 471         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 472                 /* call *<OFFSET>(%rip) */
 473                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 474         }
 475         else if (code [0] == 0xe8) {
 476                 /* call <DISP> */
 477                 gint64 disp = (guint8*)target - (guint8*)code;
 478                 g_assert (amd64_is_imm32 (disp));
 479                 x86_patch (code, (unsigned char*)target);
 480         }
 481         else
 482                 x86_patch (code, (unsigned char*)target);
 483 }
 484
 485 void
 486 mono_amd64_patch (unsigned char* code, gpointer target)
 487 {
 488         amd64_patch (code, target);
 489 }
 490
 491 typedef enum {
 492         ArgInIReg,
 493         ArgInFloatSSEReg,
 494         ArgInDoubleSSEReg,
 495         ArgOnStack,
 496         ArgValuetypeInReg,
 497         ArgValuetypeAddrInIReg,
 498         ArgNone /* only in pair_storage */
 499 } ArgStorage;
 500
 501 typedef struct {
 502         gint16 offset;
 503         gint8  reg;
 504         ArgStorage storage;
 505
 506         /* Only if storage == ArgValuetypeInReg */
 507         ArgStorage pair_storage [2];
 508         gint8 pair_regs [2];
 509         /* The size of each pair */
 510         int pair_size [2];
 511         int nregs;
 512 } ArgInfo;
 513
 514 typedef struct {
 515         int nargs;
 516         guint32 stack_usage;
 517         guint32 reg_usage;
 518         guint32 freg_usage;
 519         gboolean need_stack_align;
 520         gboolean vtype_retaddr;
 521         /* The index of the vret arg in the argument list */
 522         int vret_arg_index;
 523         ArgInfo ret;
 524         ArgInfo sig_cookie;
 525         ArgInfo args [1];
 526 } CallInfo;
 527
 528 #define DEBUG(a) if (cfg->verbose_level > 1) a
 529
 530 #ifdef TARGET_WIN32
 531 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 532
 533 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #else
 535 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 536
 537  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 538 #endif
 539
 540 static void inline
 541 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 542 {
 543     ainfo->offset = *stack_size;
 544
 545     if (*gr >= PARAM_REGS) {
 546                 ainfo->storage = ArgOnStack;
 547                 /* Since the same stack slot size is used for all arg */
 548                 /*  types, it needs to be big enough to hold them all */
 549                 (*stack_size) += sizeof(mgreg_t);
 550     }
 551     else {
 552                 ainfo->storage = ArgInIReg;
 553                 ainfo->reg = param_regs [*gr];
 554                 (*gr) ++;
 555     }
 556 }
 557
 558 #ifdef TARGET_WIN32
 559 #define FLOAT_PARAM_REGS 4
 560 #else
 561 #define FLOAT_PARAM_REGS 8
 562 #endif
 563
 564 static void inline
 565 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 566 {
 567     ainfo->offset = *stack_size;
 568
 569     if (*gr >= FLOAT_PARAM_REGS) {
 570                 ainfo->storage = ArgOnStack;
 571                 /* Since the same stack slot size is used for both float */
 572                 /*  types, it needs to be big enough to hold them both */
 573                 (*stack_size) += sizeof(mgreg_t);
 574     }
 575     else {
 576                 /* A double register */
 577                 if (is_double)
 578                         ainfo->storage = ArgInDoubleSSEReg;
 579                 else
 580                         ainfo->storage = ArgInFloatSSEReg;
 581                 ainfo->reg = *gr;
 582                 (*gr) += 1;
 583     }
 584 }
 585
 586 typedef enum ArgumentClass {
 587         ARG_CLASS_NO_CLASS,
 588         ARG_CLASS_MEMORY,
 589         ARG_CLASS_INTEGER,
 590         ARG_CLASS_SSE
 591 } ArgumentClass;
 592
 593 static ArgumentClass
 594 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 595 {
 596         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 597         MonoType *ptype;
 598
 599         ptype = mini_type_get_underlying_type (gsctx, type);
 600         switch (ptype->type) {
 601         case MONO_TYPE_I1:
 602         case MONO_TYPE_U1:
 603         case MONO_TYPE_I2:
 604         case MONO_TYPE_U2:
 605         case MONO_TYPE_I4:
 606         case MONO_TYPE_U4:
 607         case MONO_TYPE_I:
 608         case MONO_TYPE_U:
 609         case MONO_TYPE_STRING:
 610         case MONO_TYPE_OBJECT:
 611         case MONO_TYPE_CLASS:
 612         case MONO_TYPE_SZARRAY:
 613         case MONO_TYPE_PTR:
 614         case MONO_TYPE_FNPTR:
 615         case MONO_TYPE_ARRAY:
 616         case MONO_TYPE_I8:
 617         case MONO_TYPE_U8:
 618                 class2 = ARG_CLASS_INTEGER;
 619                 break;
 620         case MONO_TYPE_R4:
 621         case MONO_TYPE_R8:
 622 #ifdef TARGET_WIN32
 623                 class2 = ARG_CLASS_INTEGER;
 624 #else
 625                 class2 = ARG_CLASS_SSE;
 626 #endif
 627                 break;
 628
 629         case MONO_TYPE_TYPEDBYREF:
 630                 g_assert_not_reached ();
 631
 632         case MONO_TYPE_GENERICINST:
 633                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 634                         class2 = ARG_CLASS_INTEGER;
 635                         break;
 636                 }
 637                 /* fall through */
 638         case MONO_TYPE_VALUETYPE: {
 639                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 640                 int i;
 641
 642                 for (i = 0; i < info->num_fields; ++i) {
 643                         class2 = class1;
 644                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 645                 }
 646                 break;
 647         }
 648         default:
 649                 g_assert_not_reached ();
 650         }
 651
 652         /* Merge */
 653         if (class1 == class2)
 654                 ;
 655         else if (class1 == ARG_CLASS_NO_CLASS)
 656                 class1 = class2;
 657         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 658                 class1 = ARG_CLASS_MEMORY;
 659         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 660                 class1 = ARG_CLASS_INTEGER;
 661         else
 662                 class1 = ARG_CLASS_SSE;
 663
 664         return class1;
 665 }
 666 #ifdef __native_client_codegen__
 667
 668 /* Default alignment for Native Client is 32-byte. */
 669 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 670
 671 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 672 /* Check that alignment doesn't cross an alignment boundary.             */
 673 guint8*
 674 mono_arch_nacl_pad(guint8 *code, int pad)
 675 {
 676         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 677
 678         if (pad == 0) return code;
 679         /* assertion: alignment cannot cross a block boundary */
 680         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 681                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 682         while (pad >= kMaxPadding) {
 683                 amd64_padding (code, kMaxPadding);
 684                 pad -= kMaxPadding;
 685         }
 686         if (pad != 0) amd64_padding (code, pad);
 687         return code;
 688 }
 689 #endif
 690
 691 static int
 692 count_fields_nested (MonoClass *klass)
 693 {
 694         MonoMarshalType *info;
 695         int i, count;
 696
 697         info = mono_marshal_load_type_info (klass);
 698         g_assert(info);
 699         count = 0;
 700         for (i = 0; i < info->num_fields; ++i) {
 701                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 702                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 703                 else
 704                         count ++;
 705         }
 706         return count;
 707 }
 708
 709 static int
 710 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 711 {
 712         MonoMarshalType *info;
 713         int i;
 714
 715         info = mono_marshal_load_type_info (klass);
 716         g_assert(info);
 717         for (i = 0; i < info->num_fields; ++i) {
 718                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 719                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 720                 } else {
 721                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 722                         fields [index].offset += offset;
 723                         index ++;
 724                 }
 725         }
 726         return index;
 727 }
 728
 729 static void
 730 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 731                            gboolean is_return,
 732                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 733 {
 734         guint32 size, quad, nquads, i, nfields;
 735         /* Keep track of the size used in each quad so we can */
 736         /* use the right size when copying args/return vars.  */
 737         guint32 quadsize [2] = {8, 8};
 738         ArgumentClass args [2];
 739         MonoMarshalType *info = NULL;
 740         MonoMarshalField *fields = NULL;
 741         MonoClass *klass;
 742         MonoGenericSharingContext tmp_gsctx;
 743         gboolean pass_on_stack = FALSE;
 744
 745         /*
 746          * The gsctx currently contains no data, it is only used for checking whenever
 747          * open types are allowed, some callers like mono_arch_get_argument_info ()
 748          * don't pass it to us, so work around that.
 749          */
 750         if (!gsctx)
 751                 gsctx = &tmp_gsctx;
 752
 753         klass = mono_class_from_mono_type (type);
 754         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 755 #ifndef TARGET_WIN32
 756         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 757                 /* We pass and return vtypes of size 8 in a register */
 758         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 759                 pass_on_stack = TRUE;
 760         }
 761 #else
 762         if (!sig->pinvoke) {
 763                 pass_on_stack = TRUE;
 764         }
 765 #endif
 766
 767         /* If this struct can't be split up naturally into 8-byte */
 768         /* chunks (registers), pass it on the stack.              */
 769         if (sig->pinvoke && !pass_on_stack) {
 770                 guint32 align;
 771                 guint32 field_size;
 772
 773                 info = mono_marshal_load_type_info (klass);
 774                 g_assert (info);
 775
 776                 /*
 777                  * Collect field information recursively to be able to
 778                  * handle nested structures.
 779                  */
 780                 nfields = count_fields_nested (klass);
 781                 fields = g_new0 (MonoMarshalField, nfields);
 782                 collect_field_info_nested (klass, fields, 0, 0);
 783
 784                 for (i = 0; i < nfields; ++i) {
 785                         field_size = mono_marshal_type_size (fields [i].field->type,
 786                                                            fields [i].mspec,
 787                                                            &align, TRUE, klass->unicode);
 788                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 789                                 pass_on_stack = TRUE;
 790                                 break;
 791                         }
 792                 }
 793         }
 794
 795         if (pass_on_stack) {
 796                 /* Allways pass in memory */
 797                 ainfo->offset = *stack_size;
 798                 *stack_size += ALIGN_TO (size, 8);
 799                 ainfo->storage = ArgOnStack;
 800
 801                 g_free (fields);
 802                 return;
 803         }
 804
 805         /* FIXME: Handle structs smaller than 8 bytes */
 806         //if ((size % 8) != 0)
 807         //      NOT_IMPLEMENTED;
 808
 809         if (size > 8)
 810                 nquads = 2;
 811         else
 812                 nquads = 1;
 813
 814         if (!sig->pinvoke) {
 815                 int n = mono_class_value_size (klass, NULL);
 816
 817                 quadsize [0] = n >= 8 ? 8 : n;
 818                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 819
 820                 /* Always pass in 1 or 2 integer registers */
 821                 args [0] = ARG_CLASS_INTEGER;
 822                 args [1] = ARG_CLASS_INTEGER;
 823                 /* Only the simplest cases are supported */
 824                 if (is_return && nquads != 1) {
 825                         args [0] = ARG_CLASS_MEMORY;
 826                         args [1] = ARG_CLASS_MEMORY;
 827                 }
 828         } else {
 829                 /*
 830                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 831                  * The X87 and SSEUP stuff is left out since there are no such types in
 832                  * the CLR.
 833                  */
 834                 g_assert (info);
 835                 g_assert (fields);
 836
 837 #ifndef TARGET_WIN32
 838                 if (info->native_size > 16) {
 839                         ainfo->offset = *stack_size;
 840                         *stack_size += ALIGN_TO (info->native_size, 8);
 841                         ainfo->storage = ArgOnStack;
 842
 843                         g_free (fields);
 844                         return;
 845                 }
 846 #else
 847                 switch (info->native_size) {
 848                 case 1: case 2: case 4: case 8:
 849                         break;
 850                 default:
 851                         if (is_return) {
 852                                 ainfo->storage = ArgOnStack;
 853                                 ainfo->offset = *stack_size;
 854                                 *stack_size += ALIGN_TO (info->native_size, 8);
 855                         }
 856                         else {
 857                                 ainfo->storage = ArgValuetypeAddrInIReg;
 858
 859                                 if (*gr < PARAM_REGS) {
 860                                         ainfo->pair_storage [0] = ArgInIReg;
 861                                         ainfo->pair_regs [0] = param_regs [*gr];
 862                                         (*gr) ++;
 863                                 }
 864                                 else {
 865                                         ainfo->pair_storage [0] = ArgOnStack;
 866                                         ainfo->offset = *stack_size;
 867                                         *stack_size += 8;
 868                                 }
 869                         }
 870
 871                         g_free (fields);
 872                         return;
 873                 }
 874 #endif
 875
 876                 args [0] = ARG_CLASS_NO_CLASS;
 877                 args [1] = ARG_CLASS_NO_CLASS;
 878                 for (quad = 0; quad < nquads; ++quad) {
 879                         int size;
 880                         guint32 align;
 881                         ArgumentClass class1;
 882
 883                         if (nfields == 0)
 884                                 class1 = ARG_CLASS_MEMORY;
 885                         else
 886                                 class1 = ARG_CLASS_NO_CLASS;
 887                         for (i = 0; i < nfields; ++i) {
 888                                 size = mono_marshal_type_size (fields [i].field->type,
 889                                                                                            fields [i].mspec,
 890                                                                                            &align, TRUE, klass->unicode);
 891                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 892                                         /* Unaligned field */
 893                                         NOT_IMPLEMENTED;
 894                                 }
 895
 896                                 /* Skip fields in other quad */
 897                                 if ((quad == 0) && (fields [i].offset >= 8))
 898                                         continue;
 899                                 if ((quad == 1) && (fields [i].offset < 8))
 900                                         continue;
 901
 902                                 /* How far into this quad this data extends.*/
 903                                 /* (8 is size of quad) */
 904                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 905
 906                                 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
 907                         }
 908                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 909                         args [quad] = class1;
 910                 }
 911         }
 912
 913         g_free (fields);
 914
 915         /* Post merger cleanup */
 916         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 917                 args [0] = args [1] = ARG_CLASS_MEMORY;
 918
 919         /* Allocate registers */
 920         {
 921                 int orig_gr = *gr;
 922                 int orig_fr = *fr;
 923
 924                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 925                         quadsize [0] ++;
 926                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 927                         quadsize [1] ++;
 928
 929                 ainfo->storage = ArgValuetypeInReg;
 930                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 931                 g_assert (quadsize [0] <= 8);
 932                 g_assert (quadsize [1] <= 8);
 933                 ainfo->pair_size [0] = quadsize [0];
 934                 ainfo->pair_size [1] = quadsize [1];
 935                 ainfo->nregs = nquads;
 936                 for (quad = 0; quad < nquads; ++quad) {
 937                         switch (args [quad]) {
 938                         case ARG_CLASS_INTEGER:
 939                                 if (*gr >= PARAM_REGS)
 940                                         args [quad] = ARG_CLASS_MEMORY;
 941                                 else {
 942                                         ainfo->pair_storage [quad] = ArgInIReg;
 943                                         if (is_return)
 944                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 945                                         else
 946                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 947                                         (*gr) ++;
 948                                 }
 949                                 break;
 950                         case ARG_CLASS_SSE:
 951                                 if (*fr >= FLOAT_PARAM_REGS)
 952                                         args [quad] = ARG_CLASS_MEMORY;
 953                                 else {
 954                                         if (quadsize[quad] <= 4)
 955                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 956                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 957                                         ainfo->pair_regs [quad] = *fr;
 958                                         (*fr) ++;
 959                                 }
 960                                 break;
 961                         case ARG_CLASS_MEMORY:
 962                                 break;
 963                         default:
 964                                 g_assert_not_reached ();
 965                         }
 966                 }
 967
 968                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 969                         /* Revert possible register assignments */
 970                         *gr = orig_gr;
 971                         *fr = orig_fr;
 972
 973                         ainfo->offset = *stack_size;
 974                         if (sig->pinvoke)
 975                                 *stack_size += ALIGN_TO (info->native_size, 8);
 976                         else
 977                                 *stack_size += nquads * sizeof(mgreg_t);
 978                         ainfo->storage = ArgOnStack;
 979                 }
 980         }
 981 }
 982
 983 /*
 984  * get_call_info:
 985  *
 986  *  Obtain information about a call according to the calling convention.
 987  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 988  * Draft Version 0.23" document for more information.
 989  */
 990 static CallInfo*
 991 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 992 {
 993         guint32 i, gr, fr, pstart;
 994         MonoType *ret_type;
 995         int n = sig->hasthis + sig->param_count;
 996         guint32 stack_size = 0;
 997         CallInfo *cinfo;
 998         gboolean is_pinvoke = sig->pinvoke;
 999
1000         if (mp)
1001                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1002         else
1003                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1004
1005         cinfo->nargs = n;
1006
1007         gr = 0;
1008         fr = 0;
1009
1010 #ifdef TARGET_WIN32
1011         /* Reserve space where the callee can save the argument registers */
1012         stack_size = 4 * sizeof (mgreg_t);
1013 #endif
1014
1015         /* return value */
1016         ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1017         switch (ret_type->type) {
1018         case MONO_TYPE_I1:
1019         case MONO_TYPE_U1:
1020         case MONO_TYPE_I2:
1021         case MONO_TYPE_U2:
1022         case MONO_TYPE_I4:
1023         case MONO_TYPE_U4:
1024         case MONO_TYPE_I:
1025         case MONO_TYPE_U:
1026         case MONO_TYPE_PTR:
1027         case MONO_TYPE_FNPTR:
1028         case MONO_TYPE_CLASS:
1029         case MONO_TYPE_OBJECT:
1030         case MONO_TYPE_SZARRAY:
1031         case MONO_TYPE_ARRAY:
1032         case MONO_TYPE_STRING:
1033                 cinfo->ret.storage = ArgInIReg;
1034                 cinfo->ret.reg = AMD64_RAX;
1035                 break;
1036         case MONO_TYPE_U8:
1037         case MONO_TYPE_I8:
1038                 cinfo->ret.storage = ArgInIReg;
1039                 cinfo->ret.reg = AMD64_RAX;
1040                 break;
1041         case MONO_TYPE_R4:
1042                 cinfo->ret.storage = ArgInFloatSSEReg;
1043                 cinfo->ret.reg = AMD64_XMM0;
1044                 break;
1045         case MONO_TYPE_R8:
1046                 cinfo->ret.storage = ArgInDoubleSSEReg;
1047                 cinfo->ret.reg = AMD64_XMM0;
1048                 break;
1049         case MONO_TYPE_GENERICINST:
1050                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1051                         cinfo->ret.storage = ArgInIReg;
1052                         cinfo->ret.reg = AMD64_RAX;
1053                         break;
1054                 }
1055                 /* fall through */
1056 #if defined( __native_client_codegen__ )
1057         case MONO_TYPE_TYPEDBYREF:
1058 #endif
1059         case MONO_TYPE_VALUETYPE: {
1060                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1061
1062                 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1063                 if (cinfo->ret.storage == ArgOnStack) {
1064                         cinfo->vtype_retaddr = TRUE;
1065                         /* The caller passes the address where the value is stored */
1066                 }
1067                 break;
1068         }
1069 #if !defined( __native_client_codegen__ )
1070         case MONO_TYPE_TYPEDBYREF:
1071                 /* Same as a valuetype with size 24 */
1072                 cinfo->vtype_retaddr = TRUE;
1073                 break;
1074 #endif
1075         case MONO_TYPE_VOID:
1076                 break;
1077         default:
1078                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1079         }
1080
1081         pstart = 0;
1082         /*
1083          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1084          * the first argument, allowing 'this' to be always passed in the first arg reg.
1085          * Also do this if the first argument is a reference type, since virtual calls
1086          * are sometimes made using calli without sig->hasthis set, like in the delegate
1087          * invoke wrappers.
1088          */
1089         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1090                 if (sig->hasthis) {
1091                         add_general (&gr, &stack_size, cinfo->args + 0);
1092                 } else {
1093                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1094                         pstart = 1;
1095                 }
1096                 add_general (&gr, &stack_size, &cinfo->ret);
1097                 cinfo->vret_arg_index = 1;
1098         } else {
1099                 /* this */
1100                 if (sig->hasthis)
1101                         add_general (&gr, &stack_size, cinfo->args + 0);
1102
1103                 if (cinfo->vtype_retaddr)
1104                         add_general (&gr, &stack_size, &cinfo->ret);
1105         }
1106
1107         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1108                 gr = PARAM_REGS;
1109                 fr = FLOAT_PARAM_REGS;
1110
1111                 /* Emit the signature cookie just before the implicit arguments */
1112                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1113         }
1114
1115         for (i = pstart; i < sig->param_count; ++i) {
1116                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1117                 MonoType *ptype;
1118
1119 #ifdef TARGET_WIN32
1120                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1121                 if (gr > fr)
1122                         fr = gr;
1123                 else if (fr > gr)
1124                         gr = fr;
1125 #endif
1126
1127                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1128                         /* We allways pass the sig cookie on the stack for simplicity */
1129                         /*
1130                          * Prevent implicit arguments + the sig cookie from being passed
1131                          * in registers.
1132                          */
1133                         gr = PARAM_REGS;
1134                         fr = FLOAT_PARAM_REGS;
1135
1136                         /* Emit the signature cookie just before the implicit arguments */
1137                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1138                 }
1139
1140                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1141                 switch (ptype->type) {
1142                 case MONO_TYPE_I1:
1143                 case MONO_TYPE_U1:
1144                         add_general (&gr, &stack_size, ainfo);
1145                         break;
1146                 case MONO_TYPE_I2:
1147                 case MONO_TYPE_U2:
1148                         add_general (&gr, &stack_size, ainfo);
1149                         break;
1150                 case MONO_TYPE_I4:
1151                 case MONO_TYPE_U4:
1152                         add_general (&gr, &stack_size, ainfo);
1153                         break;
1154                 case MONO_TYPE_I:
1155                 case MONO_TYPE_U:
1156                 case MONO_TYPE_PTR:
1157                 case MONO_TYPE_FNPTR:
1158                 case MONO_TYPE_CLASS:
1159                 case MONO_TYPE_OBJECT:
1160                 case MONO_TYPE_STRING:
1161                 case MONO_TYPE_SZARRAY:
1162                 case MONO_TYPE_ARRAY:
1163                         add_general (&gr, &stack_size, ainfo);
1164                         break;
1165                 case MONO_TYPE_GENERICINST:
1166                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1167                                 add_general (&gr, &stack_size, ainfo);
1168                                 break;
1169                         }
1170                         /* fall through */
1171                 case MONO_TYPE_VALUETYPE:
1172                 case MONO_TYPE_TYPEDBYREF:
1173                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1174                         break;
1175                 case MONO_TYPE_U8:
1176
1177                 case MONO_TYPE_I8:
1178                         add_general (&gr, &stack_size, ainfo);
1179                         break;
1180                 case MONO_TYPE_R4:
1181                         add_float (&fr, &stack_size, ainfo, FALSE);
1182                         break;
1183                 case MONO_TYPE_R8:
1184                         add_float (&fr, &stack_size, ainfo, TRUE);
1185                         break;
1186                 default:
1187                         g_assert_not_reached ();
1188                 }
1189         }
1190
1191         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1192                 gr = PARAM_REGS;
1193                 fr = FLOAT_PARAM_REGS;
1194
1195                 /* Emit the signature cookie just before the implicit arguments */
1196                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1197         }
1198
1199         cinfo->stack_usage = stack_size;
1200         cinfo->reg_usage = gr;
1201         cinfo->freg_usage = fr;
1202         return cinfo;
1203 }
1204
1205 /*
1206  * mono_arch_get_argument_info:
1207  * @csig:  a method signature
1208  * @param_count: the number of parameters to consider
1209  * @arg_info: an array to store the result infos
1210  *
1211  * Gathers information on parameters such as size, alignment and
1212  * padding. arg_info should be large enought to hold param_count + 1 entries.
1213  *
1214  * Returns the size of the argument area on the stack.
1215  */
1216 int
1217 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1218 {
1219         int k;
1220         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1221         guint32 args_size = cinfo->stack_usage;
1222
1223         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1224         if (csig->hasthis) {
1225                 arg_info [0].offset = 0;
1226         }
1227
1228         for (k = 0; k < param_count; k++) {
1229                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1230                 /* FIXME: */
1231                 arg_info [k + 1].size = 0;
1232         }
1233
1234         g_free (cinfo);
1235
1236         return args_size;
1237 }
1238
1239 gboolean
1240 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1241 {
1242         CallInfo *c1, *c2;
1243         gboolean res;
1244         MonoType *callee_ret;
1245
1246         c1 = get_call_info (NULL, NULL, caller_sig);
1247         c2 = get_call_info (NULL, NULL, callee_sig);
1248         res = c1->stack_usage >= c2->stack_usage;
1249         callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1250         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1251                 /* An address on the callee's stack is passed as the first argument */
1252                 res = FALSE;
1253
1254         g_free (c1);
1255         g_free (c2);
1256
1257         return res;
1258 }
1259
1260 /*
1261  * Initialize the cpu to execute managed code.
1262  */
1263 void
1264 mono_arch_cpu_init (void)
1265 {
1266 #ifndef _MSC_VER
1267         guint16 fpcw;
1268
1269         /* spec compliance requires running with double precision */
1270         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1271         fpcw &= ~X86_FPCW_PRECC_MASK;
1272         fpcw |= X86_FPCW_PREC_DOUBLE;
1273         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1274         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275 #else
1276         /* TODO: This is crashing on Win64 right now.
1277         * _control87 (_PC_53, MCW_PC);
1278         */
1279 #endif
1280 }
1281
1282 /*
1283  * Initialize architecture specific code.
1284  */
1285 void
1286 mono_arch_init (void)
1287 {
1288         int flags;
1289
1290         mono_mutex_init_recursive (&mini_arch_mutex);
1291 #if defined(__native_client_codegen__)
1292         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1293         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1294         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1295         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1296 #endif
1297
1298 #ifdef MONO_ARCH_NOMAP32BIT
1299         flags = MONO_MMAP_READ;
1300         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1301         breakpoint_size = 13;
1302         breakpoint_fault_size = 3;
1303 #else
1304         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1305         /* amd64_mov_reg_mem () */
1306         breakpoint_size = 8;
1307         breakpoint_fault_size = 8;
1308 #endif
1309
1310         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1311         single_step_fault_size = 4;
1312
1313         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1314         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1315         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1316
1317         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1318         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1319         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1320         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1321 }
1322
1323 /*
1324  * Cleanup architecture specific code.
1325  */
1326 void
1327 mono_arch_cleanup (void)
1328 {
1329         mono_mutex_destroy (&mini_arch_mutex);
1330 #if defined(__native_client_codegen__)
1331         mono_native_tls_free (nacl_instruction_depth);
1332         mono_native_tls_free (nacl_rex_tag);
1333         mono_native_tls_free (nacl_legacy_prefix_tag);
1334 #endif
1335 }
1336
1337 /*
1338  * This function returns the optimizations supported on this cpu.
1339  */
1340 guint32
1341 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1342 {
1343         guint32 opts = 0;
1344
1345         *exclude_mask = 0;
1346
1347         if (mono_hwcap_x86_has_cmov) {
1348                 opts |= MONO_OPT_CMOV;
1349
1350                 if (mono_hwcap_x86_has_fcmov)
1351                         opts |= MONO_OPT_FCMOV;
1352                 else
1353                         *exclude_mask |= MONO_OPT_FCMOV;
1354         } else {
1355                 *exclude_mask |= MONO_OPT_CMOV;
1356         }
1357
1358         return opts;
1359 }
1360
1361 /*
1362  * This function test for all SSE functions supported.
1363  *
1364  * Returns a bitmask corresponding to all supported versions.
1365  *
1366  */
1367 guint32
1368 mono_arch_cpu_enumerate_simd_versions (void)
1369 {
1370         guint32 sse_opts = 0;
1371
1372         if (mono_hwcap_x86_has_sse1)
1373                 sse_opts |= SIMD_VERSION_SSE1;
1374
1375         if (mono_hwcap_x86_has_sse2)
1376                 sse_opts |= SIMD_VERSION_SSE2;
1377
1378         if (mono_hwcap_x86_has_sse3)
1379                 sse_opts |= SIMD_VERSION_SSE3;
1380
1381         if (mono_hwcap_x86_has_ssse3)
1382                 sse_opts |= SIMD_VERSION_SSSE3;
1383
1384         if (mono_hwcap_x86_has_sse41)
1385                 sse_opts |= SIMD_VERSION_SSE41;
1386
1387         if (mono_hwcap_x86_has_sse42)
1388                 sse_opts |= SIMD_VERSION_SSE42;
1389
1390         if (mono_hwcap_x86_has_sse4a)
1391                 sse_opts |= SIMD_VERSION_SSE4a;
1392
1393         return sse_opts;
1394 }
1395
1396 #ifndef DISABLE_JIT
1397
1398 GList *
1399 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1400 {
1401         GList *vars = NULL;
1402         int i;
1403
1404         for (i = 0; i < cfg->num_varinfo; i++) {
1405                 MonoInst *ins = cfg->varinfo [i];
1406                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1407
1408                 /* unused vars */
1409                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1410                         continue;
1411
1412                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1413                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1414                         continue;
1415
1416                 if (mono_is_regsize_var (ins->inst_vtype)) {
1417                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1418                         g_assert (i == vmv->idx);
1419                         vars = g_list_prepend (vars, vmv);
1420                 }
1421         }
1422
1423         vars = mono_varlist_sort (cfg, vars, 0);
1424
1425         return vars;
1426 }
1427
1428 /**
1429  * mono_arch_compute_omit_fp:
1430  *
1431  *   Determine whenever the frame pointer can be eliminated.
1432  */
1433 static void
1434 mono_arch_compute_omit_fp (MonoCompile *cfg)
1435 {
1436         MonoMethodSignature *sig;
1437         MonoMethodHeader *header;
1438         int i, locals_size;
1439         CallInfo *cinfo;
1440
1441         if (cfg->arch.omit_fp_computed)
1442                 return;
1443
1444         header = cfg->header;
1445
1446         sig = mono_method_signature (cfg->method);
1447
1448         if (!cfg->arch.cinfo)
1449                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1450         cinfo = cfg->arch.cinfo;
1451
1452         /*
1453          * FIXME: Remove some of the restrictions.
1454          */
1455         cfg->arch.omit_fp = TRUE;
1456         cfg->arch.omit_fp_computed = TRUE;
1457
1458 #ifdef __native_client_codegen__
1459         /* NaCl modules may not change the value of RBP, so it cannot be */
1460         /* used as a normal register, but it can be used as a frame pointer*/
1461         cfg->disable_omit_fp = TRUE;
1462         cfg->arch.omit_fp = FALSE;
1463 #endif
1464
1465         if (cfg->disable_omit_fp)
1466                 cfg->arch.omit_fp = FALSE;
1467
1468         if (!debug_omit_fp ())
1469                 cfg->arch.omit_fp = FALSE;
1470         /*
1471         if (cfg->method->save_lmf)
1472                 cfg->arch.omit_fp = FALSE;
1473         */
1474         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1475                 cfg->arch.omit_fp = FALSE;
1476         if (header->num_clauses)
1477                 cfg->arch.omit_fp = FALSE;
1478         if (cfg->param_area)
1479                 cfg->arch.omit_fp = FALSE;
1480         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1481                 cfg->arch.omit_fp = FALSE;
1482         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1483                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1484                 cfg->arch.omit_fp = FALSE;
1485         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1486                 ArgInfo *ainfo = &cinfo->args [i];
1487
1488                 if (ainfo->storage == ArgOnStack) {
1489                         /*
1490                          * The stack offset can only be determined when the frame
1491                          * size is known.
1492                          */
1493                         cfg->arch.omit_fp = FALSE;
1494                 }
1495         }
1496
1497         locals_size = 0;
1498         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1499                 MonoInst *ins = cfg->varinfo [i];
1500                 int ialign;
1501
1502                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1503         }
1504 }
1505
1506 GList *
1507 mono_arch_get_global_int_regs (MonoCompile *cfg)
1508 {
1509         GList *regs = NULL;
1510
1511         mono_arch_compute_omit_fp (cfg);
1512
1513         if (cfg->arch.omit_fp)
1514                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1515
1516         /* We use the callee saved registers for global allocation */
1517         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1518         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1519         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1520         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1521 #ifndef __native_client_codegen__
1522         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1523 #endif
1524 #ifdef TARGET_WIN32
1525         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1526         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1527 #endif
1528
1529         return regs;
1530 }
1531
1532 GList*
1533 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1534 {
1535         GList *regs = NULL;
1536         int i;
1537
1538         /* All XMM registers */
1539         for (i = 0; i < 16; ++i)
1540                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1541
1542         return regs;
1543 }
1544
1545 GList*
1546 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1547 {
1548         static GList *r = NULL;
1549
1550         if (r == NULL) {
1551                 GList *regs = NULL;
1552
1553                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1554                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1555                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1556                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1557                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1558 #ifndef __native_client_codegen__
1559                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1560 #endif
1561
1562                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1563                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1564                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1565                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1566                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1567                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1568                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1569                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1570
1571                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1572         }
1573
1574         return r;
1575 }
1576
1577 GList*
1578 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1579 {
1580         int i;
1581         static GList *r = NULL;
1582
1583         if (r == NULL) {
1584                 GList *regs = NULL;
1585
1586                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1587                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1588
1589                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1590         }
1591
1592         return r;
1593 }
1594
1595 /*
1596  * mono_arch_regalloc_cost:
1597  *
1598  *  Return the cost, in number of memory references, of the action of
1599  * allocating the variable VMV into a register during global register
1600  * allocation.
1601  */
1602 guint32
1603 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1604 {
1605         MonoInst *ins = cfg->varinfo [vmv->idx];
1606
1607         if (cfg->method->save_lmf)
1608                 /* The register is already saved */
1609                 /* substract 1 for the invisible store in the prolog */
1610                 return (ins->opcode == OP_ARG) ? 0 : 1;
1611         else
1612                 /* push+pop */
1613                 return (ins->opcode == OP_ARG) ? 1 : 2;
1614 }
1615
1616 /*
1617  * mono_arch_fill_argument_info:
1618  *
1619  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1620  * of the method.
1621  */
1622 void
1623 mono_arch_fill_argument_info (MonoCompile *cfg)
1624 {
1625         MonoType *sig_ret;
1626         MonoMethodSignature *sig;
1627         MonoInst *ins;
1628         int i;
1629         CallInfo *cinfo;
1630
1631         sig = mono_method_signature (cfg->method);
1632
1633         cinfo = cfg->arch.cinfo;
1634         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1635
1636         /*
1637          * Contrary to mono_arch_allocate_vars (), the information should describe
1638          * where the arguments are at the beginning of the method, not where they can be
1639          * accessed during the execution of the method. The later makes no sense for the
1640          * global register allocator, since a variable can be in more than one location.
1641          */
1642         if (sig_ret->type != MONO_TYPE_VOID) {
1643                 switch (cinfo->ret.storage) {
1644                 case ArgInIReg:
1645                 case ArgInFloatSSEReg:
1646                 case ArgInDoubleSSEReg:
1647                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1648                                 cfg->vret_addr->opcode = OP_REGVAR;
1649                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1650                         }
1651                         else {
1652                                 cfg->ret->opcode = OP_REGVAR;
1653                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1654                         }
1655                         break;
1656                 case ArgValuetypeInReg:
1657                         cfg->ret->opcode = OP_REGOFFSET;
1658                         cfg->ret->inst_basereg = -1;
1659                         cfg->ret->inst_offset = -1;
1660                         break;
1661                 default:
1662                         g_assert_not_reached ();
1663                 }
1664         }
1665
1666         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1667                 ArgInfo *ainfo = &cinfo->args [i];
1668
1669                 ins = cfg->args [i];
1670
1671                 switch (ainfo->storage) {
1672                 case ArgInIReg:
1673                 case ArgInFloatSSEReg:
1674                 case ArgInDoubleSSEReg:
1675                         ins->opcode = OP_REGVAR;
1676                         ins->inst_c0 = ainfo->reg;
1677                         break;
1678                 case ArgOnStack:
1679                         ins->opcode = OP_REGOFFSET;
1680                         ins->inst_basereg = -1;
1681                         ins->inst_offset = -1;
1682                         break;
1683                 case ArgValuetypeInReg:
1684                         /* Dummy */
1685                         ins->opcode = OP_NOP;
1686                         break;
1687                 default:
1688                         g_assert_not_reached ();
1689                 }
1690         }
1691 }
1692
1693 void
1694 mono_arch_allocate_vars (MonoCompile *cfg)
1695 {
1696         MonoType *sig_ret;
1697         MonoMethodSignature *sig;
1698         MonoInst *ins;
1699         int i, offset;
1700         guint32 locals_stack_size, locals_stack_align;
1701         gint32 *offsets;
1702         CallInfo *cinfo;
1703
1704         sig = mono_method_signature (cfg->method);
1705
1706         cinfo = cfg->arch.cinfo;
1707         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1708
1709         mono_arch_compute_omit_fp (cfg);
1710
1711         /*
1712          * We use the ABI calling conventions for managed code as well.
1713          * Exception: valuetypes are only sometimes passed or returned in registers.
1714          */
1715
1716         /*
1717          * The stack looks like this:
1718          * <incoming arguments passed on the stack>
1719          * <return value>
1720          * <lmf/caller saved registers>
1721          * <locals>
1722          * <spill area>
1723          * <localloc area>  -> grows dynamically
1724          * <params area>
1725          */
1726
1727         if (cfg->arch.omit_fp) {
1728                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1729                 cfg->frame_reg = AMD64_RSP;
1730                 offset = 0;
1731         } else {
1732                 /* Locals are allocated backwards from %fp */
1733                 cfg->frame_reg = AMD64_RBP;
1734                 offset = 0;
1735         }
1736
1737         cfg->arch.saved_iregs = cfg->used_int_regs;
1738         if (cfg->method->save_lmf)
1739                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1740                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1741
1742         if (cfg->arch.omit_fp)
1743                 cfg->arch.reg_save_area_offset = offset;
1744         /* Reserve space for callee saved registers */
1745         for (i = 0; i < AMD64_NREG; ++i)
1746                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1747                         offset += sizeof(mgreg_t);
1748                 }
1749         if (!cfg->arch.omit_fp)
1750                 cfg->arch.reg_save_area_offset = -offset;
1751
1752         if (sig_ret->type != MONO_TYPE_VOID) {
1753                 switch (cinfo->ret.storage) {
1754                 case ArgInIReg:
1755                 case ArgInFloatSSEReg:
1756                 case ArgInDoubleSSEReg:
1757                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1758                                 /* The register is volatile */
1759                                 cfg->vret_addr->opcode = OP_REGOFFSET;
1760                                 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1761                                 if (cfg->arch.omit_fp) {
1762                                         cfg->vret_addr->inst_offset = offset;
1763                                         offset += 8;
1764                                 } else {
1765                                         offset += 8;
1766                                         cfg->vret_addr->inst_offset = -offset;
1767                                 }
1768                                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1769                                         printf ("vret_addr =");
1770                                         mono_print_ins (cfg->vret_addr);
1771                                 }
1772                         }
1773                         else {
1774                                 cfg->ret->opcode = OP_REGVAR;
1775                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1776                         }
1777                         break;
1778                 case ArgValuetypeInReg:
1779                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1780                         cfg->ret->opcode = OP_REGOFFSET;
1781                         cfg->ret->inst_basereg = cfg->frame_reg;
1782                         if (cfg->arch.omit_fp) {
1783                                 cfg->ret->inst_offset = offset;
1784                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1785                         } else {
1786                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1787                                 cfg->ret->inst_offset = - offset;
1788                         }
1789                         break;
1790                 default:
1791                         g_assert_not_reached ();
1792                 }
1793                 cfg->ret->dreg = cfg->ret->inst_c0;
1794         }
1795
1796         /* Allocate locals */
1797         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1798         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1799                 char *mname = mono_method_full_name (cfg->method, TRUE);
1800                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1801                 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1802                 g_free (mname);
1803                 return;
1804         }
1805
1806         if (locals_stack_align) {
1807                 offset += (locals_stack_align - 1);
1808                 offset &= ~(locals_stack_align - 1);
1809         }
1810         if (cfg->arch.omit_fp) {
1811                 cfg->locals_min_stack_offset = offset;
1812                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1813         } else {
1814                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1815                 cfg->locals_max_stack_offset = - offset;
1816         }
1817
1818         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1819                 if (offsets [i] != -1) {
1820                         MonoInst *ins = cfg->varinfo [i];
1821                         ins->opcode = OP_REGOFFSET;
1822                         ins->inst_basereg = cfg->frame_reg;
1823                         if (cfg->arch.omit_fp)
1824                                 ins->inst_offset = (offset + offsets [i]);
1825                         else
1826                                 ins->inst_offset = - (offset + offsets [i]);
1827                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1828                 }
1829         }
1830         offset += locals_stack_size;
1831
1832         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1833                 g_assert (!cfg->arch.omit_fp);
1834                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1835                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1836         }
1837
1838         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1839                 ins = cfg->args [i];
1840                 if (ins->opcode != OP_REGVAR) {
1841                         ArgInfo *ainfo = &cinfo->args [i];
1842                         gboolean inreg = TRUE;
1843
1844                         /* FIXME: Allocate volatile arguments to registers */
1845                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1846                                 inreg = FALSE;
1847
1848                         /*
1849                          * Under AMD64, all registers used to pass arguments to functions
1850                          * are volatile across calls.
1851                          * FIXME: Optimize this.
1852                          */
1853                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1854                                 inreg = FALSE;
1855
1856                         ins->opcode = OP_REGOFFSET;
1857
1858                         switch (ainfo->storage) {
1859                         case ArgInIReg:
1860                         case ArgInFloatSSEReg:
1861                         case ArgInDoubleSSEReg:
1862                                 if (inreg) {
1863                                         ins->opcode = OP_REGVAR;
1864                                         ins->dreg = ainfo->reg;
1865                                 }
1866                                 break;
1867                         case ArgOnStack:
1868                                 g_assert (!cfg->arch.omit_fp);
1869                                 ins->opcode = OP_REGOFFSET;
1870                                 ins->inst_basereg = cfg->frame_reg;
1871                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1872                                 break;
1873                         case ArgValuetypeInReg:
1874                                 break;
1875                         case ArgValuetypeAddrInIReg: {
1876                                 MonoInst *indir;
1877                                 g_assert (!cfg->arch.omit_fp);
1878
1879                                 MONO_INST_NEW (cfg, indir, 0);
1880                                 indir->opcode = OP_REGOFFSET;
1881                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1882                                         indir->inst_basereg = cfg->frame_reg;
1883                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1884                                         offset += (sizeof (gpointer));
1885                                         indir->inst_offset = - offset;
1886                                 }
1887                                 else {
1888                                         indir->inst_basereg = cfg->frame_reg;
1889                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1890                                 }
1891
1892                                 ins->opcode = OP_VTARG_ADDR;
1893                                 ins->inst_left = indir;
1894
1895                                 break;
1896                         }
1897                         default:
1898                                 NOT_IMPLEMENTED;
1899                         }
1900
1901                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1902                                 ins->opcode = OP_REGOFFSET;
1903                                 ins->inst_basereg = cfg->frame_reg;
1904                                 /* These arguments are saved to the stack in the prolog */
1905                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1906                                 if (cfg->arch.omit_fp) {
1907                                         ins->inst_offset = offset;
1908                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1909                                         // Arguments are yet supported by the stack map creation code
1910                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1911                                 } else {
1912                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1913                                         ins->inst_offset = - offset;
1914                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1915                                 }
1916                         }
1917                 }
1918         }
1919
1920         cfg->stack_offset = offset;
1921 }
1922
1923 void
1924 mono_arch_create_vars (MonoCompile *cfg)
1925 {
1926         MonoMethodSignature *sig;
1927         CallInfo *cinfo;
1928         MonoType *sig_ret;
1929
1930         sig = mono_method_signature (cfg->method);
1931
1932         if (!cfg->arch.cinfo)
1933                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1934         cinfo = cfg->arch.cinfo;
1935
1936         if (cinfo->ret.storage == ArgValuetypeInReg)
1937                 cfg->ret_var_is_local = TRUE;
1938
1939         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1940         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1941                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1942                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1943                         printf ("vret_addr = ");
1944                         mono_print_ins (cfg->vret_addr);
1945                 }
1946         }
1947
1948         if (cfg->gen_sdb_seq_points) {
1949                 MonoInst *ins;
1950
1951                 if (cfg->compile_aot) {
1952                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1953                         ins->flags |= MONO_INST_VOLATILE;
1954                         cfg->arch.seq_point_info_var = ins;
1955
1956                         ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1957                         ins->flags |= MONO_INST_VOLATILE;
1958                         cfg->arch.ss_tramp_var = ins;
1959                 }
1960
1961             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1962                 ins->flags |= MONO_INST_VOLATILE;
1963                 cfg->arch.ss_trigger_page_var = ins;
1964         }
1965
1966         if (cfg->method->save_lmf)
1967                 cfg->create_lmf_var = TRUE;
1968
1969         if (cfg->method->save_lmf) {
1970                 cfg->lmf_ir = TRUE;
1971 #if !defined(TARGET_WIN32)
1972                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1973                         cfg->lmf_ir_mono_lmf = TRUE;
1974 #endif
1975         }
1976 }
1977
1978 static void
1979 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1980 {
1981         MonoInst *ins;
1982
1983         switch (storage) {
1984         case ArgInIReg:
1985                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1986                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1987                 ins->sreg1 = tree->dreg;
1988                 MONO_ADD_INS (cfg->cbb, ins);
1989                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1990                 break;
1991         case ArgInFloatSSEReg:
1992                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1993                 ins->dreg = mono_alloc_freg (cfg);
1994                 ins->sreg1 = tree->dreg;
1995                 MONO_ADD_INS (cfg->cbb, ins);
1996
1997                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1998                 break;
1999         case ArgInDoubleSSEReg:
2000                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2001                 ins->dreg = mono_alloc_freg (cfg);
2002                 ins->sreg1 = tree->dreg;
2003                 MONO_ADD_INS (cfg->cbb, ins);
2004
2005                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2006
2007                 break;
2008         default:
2009                 g_assert_not_reached ();
2010         }
2011 }
2012
2013 static int
2014 arg_storage_to_load_membase (ArgStorage storage)
2015 {
2016         switch (storage) {
2017         case ArgInIReg:
2018 #if defined(__mono_ilp32__)
2019                 return OP_LOADI8_MEMBASE;
2020 #else
2021                 return OP_LOAD_MEMBASE;
2022 #endif
2023         case ArgInDoubleSSEReg:
2024                 return OP_LOADR8_MEMBASE;
2025         case ArgInFloatSSEReg:
2026                 return OP_LOADR4_MEMBASE;
2027         default:
2028                 g_assert_not_reached ();
2029         }
2030
2031         return -1;
2032 }
2033
2034 static void
2035 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2036 {
2037         MonoMethodSignature *tmp_sig;
2038         int sig_reg;
2039
2040         if (call->tail_call)
2041                 NOT_IMPLEMENTED;
2042
2043         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2044
2045         /*
2046          * mono_ArgIterator_Setup assumes the signature cookie is
2047          * passed first and all the arguments which were before it are
2048          * passed on the stack after the signature. So compensate by
2049          * passing a different signature.
2050          */
2051         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2052         tmp_sig->param_count -= call->signature->sentinelpos;
2053         tmp_sig->sentinelpos = 0;
2054         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2055
2056         sig_reg = mono_alloc_ireg (cfg);
2057         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2058
2059         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2060 }
2061
2062 #ifdef ENABLE_LLVM
2063 static inline LLVMArgStorage
2064 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2065 {
2066         switch (storage) {
2067         case ArgInIReg:
2068                 return LLVMArgInIReg;
2069         case ArgNone:
2070                 return LLVMArgNone;
2071         default:
2072                 g_assert_not_reached ();
2073                 return LLVMArgNone;
2074         }
2075 }
2076
2077 LLVMCallInfo*
2078 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2079 {
2080         int i, n;
2081         CallInfo *cinfo;
2082         ArgInfo *ainfo;
2083         int j;
2084         LLVMCallInfo *linfo;
2085         MonoType *t, *sig_ret;
2086
2087         n = sig->param_count + sig->hasthis;
2088         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2089
2090         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2091
2092         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2093
2094         /*
2095          * LLVM always uses the native ABI while we use our own ABI, the
2096          * only difference is the handling of vtypes:
2097          * - we only pass/receive them in registers in some cases, and only
2098          *   in 1 or 2 integer registers.
2099          */
2100         if (cinfo->ret.storage == ArgValuetypeInReg) {
2101                 if (sig->pinvoke) {
2102                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2103                         cfg->disable_llvm = TRUE;
2104                         return linfo;
2105                 }
2106
2107                 linfo->ret.storage = LLVMArgVtypeInReg;
2108                 for (j = 0; j < 2; ++j)
2109                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2110         }
2111
2112         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2113                 /* Vtype returned using a hidden argument */
2114                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2115                 linfo->vret_arg_index = cinfo->vret_arg_index;
2116         }
2117
2118         for (i = 0; i < n; ++i) {
2119                 ainfo = cinfo->args + i;
2120
2121                 if (i >= sig->hasthis)
2122                         t = sig->params [i - sig->hasthis];
2123                 else
2124                         t = &mono_defaults.int_class->byval_arg;
2125
2126                 linfo->args [i].storage = LLVMArgNone;
2127
2128                 switch (ainfo->storage) {
2129                 case ArgInIReg:
2130                         linfo->args [i].storage = LLVMArgInIReg;
2131                         break;
2132                 case ArgInDoubleSSEReg:
2133                 case ArgInFloatSSEReg:
2134                         linfo->args [i].storage = LLVMArgInFPReg;
2135                         break;
2136                 case ArgOnStack:
2137                         if (MONO_TYPE_ISSTRUCT (t)) {
2138                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2139                         } else {
2140                                 linfo->args [i].storage = LLVMArgInIReg;
2141                                 if (!t->byref) {
2142                                         if (t->type == MONO_TYPE_R4)
2143                                                 linfo->args [i].storage = LLVMArgInFPReg;
2144                                         else if (t->type == MONO_TYPE_R8)
2145                                                 linfo->args [i].storage = LLVMArgInFPReg;
2146                                 }
2147                         }
2148                         break;
2149                 case ArgValuetypeInReg:
2150                         if (sig->pinvoke) {
2151                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2152                                 cfg->disable_llvm = TRUE;
2153                                 return linfo;
2154                         }
2155
2156                         linfo->args [i].storage = LLVMArgVtypeInReg;
2157                         for (j = 0; j < 2; ++j)
2158                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2159                         break;
2160                 default:
2161                         cfg->exception_message = g_strdup ("ainfo->storage");
2162                         cfg->disable_llvm = TRUE;
2163                         break;
2164                 }
2165         }
2166
2167         return linfo;
2168 }
2169 #endif
2170
2171 void
2172 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2173 {
2174         MonoInst *arg, *in;
2175         MonoMethodSignature *sig;
2176         MonoType *sig_ret;
2177         int i, n;
2178         CallInfo *cinfo;
2179         ArgInfo *ainfo;
2180
2181         sig = call->signature;
2182         n = sig->param_count + sig->hasthis;
2183
2184         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2185
2186         sig_ret = sig->ret;
2187
2188         if (COMPILE_LLVM (cfg)) {
2189                 /* We shouldn't be called in the llvm case */
2190                 cfg->disable_llvm = TRUE;
2191                 return;
2192         }
2193
2194         /*
2195          * Emit all arguments which are passed on the stack to prevent register
2196          * allocation problems.
2197          */
2198         for (i = 0; i < n; ++i) {
2199                 MonoType *t;
2200                 ainfo = cinfo->args + i;
2201
2202                 in = call->args [i];
2203
2204                 if (sig->hasthis && i == 0)
2205                         t = &mono_defaults.object_class->byval_arg;
2206                 else
2207                         t = sig->params [i - sig->hasthis];
2208
2209                 t = mini_get_underlying_type (cfg, t);
2210                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2211                         if (!t->byref) {
2212                                 if (t->type == MONO_TYPE_R4)
2213                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2214                                 else if (t->type == MONO_TYPE_R8)
2215                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2216                                 else
2217                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2218                         } else {
2219                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2220                         }
2221                         if (cfg->compute_gc_maps) {
2222                                 MonoInst *def;
2223
2224                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2225                         }
2226                 }
2227         }
2228
2229         /*
2230          * Emit all parameters passed in registers in non-reverse order for better readability
2231          * and to help the optimization in emit_prolog ().
2232          */
2233         for (i = 0; i < n; ++i) {
2234                 ainfo = cinfo->args + i;
2235
2236                 in = call->args [i];
2237
2238                 if (ainfo->storage == ArgInIReg)
2239                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2240         }
2241
2242         for (i = n - 1; i >= 0; --i) {
2243                 ainfo = cinfo->args + i;
2244
2245                 in = call->args [i];
2246
2247                 switch (ainfo->storage) {
2248                 case ArgInIReg:
2249                         /* Already done */
2250                         break;
2251                 case ArgInFloatSSEReg:
2252                 case ArgInDoubleSSEReg:
2253                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2254                         break;
2255                 case ArgOnStack:
2256                 case ArgValuetypeInReg:
2257                 case ArgValuetypeAddrInIReg:
2258                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2259                                 MonoInst *call_inst = (MonoInst*)call;
2260                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2261                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2262                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2263                                 guint32 align;
2264                                 guint32 size;
2265
2266                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2267                                         size = sizeof (MonoTypedRef);
2268                                         align = sizeof (gpointer);
2269                                 }
2270                                 else {
2271                                         if (sig->pinvoke)
2272                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2273                                         else {
2274                                                 /*
2275                                                  * Other backends use mono_type_stack_size (), but that
2276                                                  * aligns the size to 8, which is larger than the size of
2277                                                  * the source, leading to reads of invalid memory if the
2278                                                  * source is at the end of address space.
2279                                                  */
2280                                                 size = mono_class_value_size (in->klass, &align);
2281                                         }
2282                                 }
2283                                 g_assert (in->klass);
2284
2285                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2286                                         /* Avoid asserts in emit_memcpy () */
2287                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2288                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2289                                         /* Continue normally */
2290                                 }
2291
2292                                 if (size > 0) {
2293                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2294                                         arg->sreg1 = in->dreg;
2295                                         arg->klass = in->klass;
2296                                         arg->backend.size = size;
2297                                         arg->inst_p0 = call;
2298                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2299                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2300
2301                                         MONO_ADD_INS (cfg->cbb, arg);
2302                                 }
2303                         }
2304                         break;
2305                 default:
2306                         g_assert_not_reached ();
2307                 }
2308
2309                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2310                         /* Emit the signature cookie just before the implicit arguments */
2311                         emit_sig_cookie (cfg, call, cinfo);
2312         }
2313
2314         /* Handle the case where there are no implicit arguments */
2315         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2316                 emit_sig_cookie (cfg, call, cinfo);
2317
2318         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2319         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2320                 MonoInst *vtarg;
2321
2322                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2323                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2324                                 /*
2325                                  * Tell the JIT to use a more efficient calling convention: call using
2326                                  * OP_CALL, compute the result location after the call, and save the
2327                                  * result there.
2328                                  */
2329                                 call->vret_in_reg = TRUE;
2330                                 /*
2331                                  * Nullify the instruction computing the vret addr to enable
2332                                  * future optimizations.
2333                                  */
2334                                 if (call->vret_var)
2335                                         NULLIFY_INS (call->vret_var);
2336                         } else {
2337                                 if (call->tail_call)
2338                                         NOT_IMPLEMENTED;
2339                                 /*
2340                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2341                                  * the stack. Push the address here, so the call instruction can
2342                                  * access it.
2343                                  */
2344                                 if (!cfg->arch.vret_addr_loc) {
2345                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2346                                         /* Prevent it from being register allocated or optimized away */
2347                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2348                                 }
2349
2350                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2351                         }
2352                 }
2353                 else {
2354                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2355                         vtarg->sreg1 = call->vret_var->dreg;
2356                         vtarg->dreg = mono_alloc_preg (cfg);
2357                         MONO_ADD_INS (cfg->cbb, vtarg);
2358
2359                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2360                 }
2361         }
2362
2363         if (cfg->method->save_lmf) {
2364                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2365                 MONO_ADD_INS (cfg->cbb, arg);
2366         }
2367
2368         call->stack_usage = cinfo->stack_usage;
2369 }
2370
2371 void
2372 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2373 {
2374         MonoInst *arg;
2375         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2376         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2377         int size = ins->backend.size;
2378
2379         if (ainfo->storage == ArgValuetypeInReg) {
2380                 MonoInst *load;
2381                 int part;
2382
2383                 for (part = 0; part < 2; ++part) {
2384                         if (ainfo->pair_storage [part] == ArgNone)
2385                                 continue;
2386
2387                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2388                         load->inst_basereg = src->dreg;
2389                         load->inst_offset = part * sizeof(mgreg_t);
2390
2391                         switch (ainfo->pair_storage [part]) {
2392                         case ArgInIReg:
2393                                 load->dreg = mono_alloc_ireg (cfg);
2394                                 break;
2395                         case ArgInDoubleSSEReg:
2396                         case ArgInFloatSSEReg:
2397                                 load->dreg = mono_alloc_freg (cfg);
2398                                 break;
2399                         default:
2400                                 g_assert_not_reached ();
2401                         }
2402                         MONO_ADD_INS (cfg->cbb, load);
2403
2404                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2405                 }
2406         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2407                 MonoInst *vtaddr, *load;
2408                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2409
2410                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2411                 cfg->has_indirection = TRUE;
2412                 load->inst_p0 = vtaddr;
2413                 vtaddr->flags |= MONO_INST_INDIRECT;
2414                 load->type = STACK_MP;
2415                 load->klass = vtaddr->klass;
2416                 load->dreg = mono_alloc_ireg (cfg);
2417                 MONO_ADD_INS (cfg->cbb, load);
2418                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2419
2420                 if (ainfo->pair_storage [0] == ArgInIReg) {
2421                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2422                         arg->dreg = mono_alloc_ireg (cfg);
2423                         arg->sreg1 = load->dreg;
2424                         arg->inst_imm = 0;
2425                         MONO_ADD_INS (cfg->cbb, arg);
2426                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2427                 } else {
2428                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2429                 }
2430         } else {
2431                 if (size == 8) {
2432                         int dreg = mono_alloc_ireg (cfg);
2433
2434                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2435                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2436                 } else if (size <= 40) {
2437                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2438                 } else {
2439                         // FIXME: Code growth
2440                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2441                 }
2442
2443                 if (cfg->compute_gc_maps) {
2444                         MonoInst *def;
2445                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2446                 }
2447         }
2448 }
2449
2450 void
2451 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2452 {
2453         MonoType *ret = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
2454
2455         if (ret->type == MONO_TYPE_R4) {
2456                 if (COMPILE_LLVM (cfg))
2457                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2458                 else
2459                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2460                 return;
2461         } else if (ret->type == MONO_TYPE_R8) {
2462                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2463                 return;
2464         }
2465
2466         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2467 }
2468
2469 #endif /* DISABLE_JIT */
2470
2471 #define EMIT_COND_BRANCH(ins,cond,sign) \
2472         if (ins->inst_true_bb->native_offset) { \
2473                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2474         } else { \
2475                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2476                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2477             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2478                         x86_branch8 (code, cond, 0, sign); \
2479                 else \
2480                         x86_branch32 (code, cond, 0, sign); \
2481 }
2482
2483 typedef struct {
2484         MonoMethodSignature *sig;
2485         CallInfo *cinfo;
2486 } ArchDynCallInfo;
2487
2488 static gboolean
2489 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2490 {
2491         int i;
2492
2493 #ifdef HOST_WIN32
2494         return FALSE;
2495 #endif
2496
2497         switch (cinfo->ret.storage) {
2498         case ArgNone:
2499         case ArgInIReg:
2500                 break;
2501         case ArgValuetypeInReg: {
2502                 ArgInfo *ainfo = &cinfo->ret;
2503
2504                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2505                         return FALSE;
2506                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2507                         return FALSE;
2508                 break;
2509         }
2510         default:
2511                 return FALSE;
2512         }
2513
2514         for (i = 0; i < cinfo->nargs; ++i) {
2515                 ArgInfo *ainfo = &cinfo->args [i];
2516                 switch (ainfo->storage) {
2517                 case ArgInIReg:
2518                         break;
2519                 case ArgValuetypeInReg:
2520                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2521                                 return FALSE;
2522                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2523                                 return FALSE;
2524                         break;
2525                 default:
2526                         return FALSE;
2527                 }
2528         }
2529
2530         return TRUE;
2531 }
2532
2533 /*
2534  * mono_arch_dyn_call_prepare:
2535  *
2536  *   Return a pointer to an arch-specific structure which contains information
2537  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2538  * supported for SIG.
2539  * This function is equivalent to ffi_prep_cif in libffi.
2540  */
2541 MonoDynCallInfo*
2542 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2543 {
2544         ArchDynCallInfo *info;
2545         CallInfo *cinfo;
2546
2547         cinfo = get_call_info (NULL, NULL, sig);
2548
2549         if (!dyn_call_supported (sig, cinfo)) {
2550                 g_free (cinfo);
2551                 return NULL;
2552         }
2553
2554         info = g_new0 (ArchDynCallInfo, 1);
2555         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2556         info->sig = sig;
2557         info->cinfo = cinfo;
2558
2559         return (MonoDynCallInfo*)info;
2560 }
2561
2562 /*
2563  * mono_arch_dyn_call_free:
2564  *
2565  *   Free a MonoDynCallInfo structure.
2566  */
2567 void
2568 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2569 {
2570         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2571
2572         g_free (ainfo->cinfo);
2573         g_free (ainfo);
2574 }
2575
2576 #if !defined(__native_client__)
2577 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2578 #define GREG_TO_PTR(greg) (gpointer)(greg)
2579 #else
2580 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2581 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2582 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2583 #endif
2584
2585 /*
2586  * mono_arch_get_start_dyn_call:
2587  *
2588  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2589  * store the result into BUF.
2590  * ARGS should be an array of pointers pointing to the arguments.
2591  * RET should point to a memory buffer large enought to hold the result of the
2592  * call.
2593  * This function should be as fast as possible, any work which does not depend
2594  * on the actual values of the arguments should be done in
2595  * mono_arch_dyn_call_prepare ().
2596  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2597  * libffi.
2598  */
2599 void
2600 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2601 {
2602         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2603         DynCallArgs *p = (DynCallArgs*)buf;
2604         int arg_index, greg, i, pindex;
2605         MonoMethodSignature *sig = dinfo->sig;
2606
2607         g_assert (buf_len >= sizeof (DynCallArgs));
2608
2609         p->res = 0;
2610         p->ret = ret;
2611
2612         arg_index = 0;
2613         greg = 0;
2614         pindex = 0;
2615
2616         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2617                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2618                 if (!sig->hasthis)
2619                         pindex = 1;
2620         }
2621
2622         if (dinfo->cinfo->vtype_retaddr)
2623                 p->regs [greg ++] = PTR_TO_GREG(ret);
2624
2625         for (i = pindex; i < sig->param_count; i++) {
2626                 MonoType *t = mini_type_get_underlying_type (NULL, sig->params [i]);
2627                 gpointer *arg = args [arg_index ++];
2628
2629                 if (t->byref) {
2630                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2631                         continue;
2632                 }
2633
2634                 switch (t->type) {
2635                 case MONO_TYPE_STRING:
2636                 case MONO_TYPE_CLASS:
2637                 case MONO_TYPE_ARRAY:
2638                 case MONO_TYPE_SZARRAY:
2639                 case MONO_TYPE_OBJECT:
2640                 case MONO_TYPE_PTR:
2641                 case MONO_TYPE_I:
2642                 case MONO_TYPE_U:
2643 #if !defined(__mono_ilp32__)
2644                 case MONO_TYPE_I8:
2645                 case MONO_TYPE_U8:
2646 #endif
2647                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2648                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2649                         break;
2650 #if defined(__mono_ilp32__)
2651                 case MONO_TYPE_I8:
2652                 case MONO_TYPE_U8:
2653                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2654                         p->regs [greg ++] = *(guint64*)(arg);
2655                         break;
2656 #endif
2657                 case MONO_TYPE_U1:
2658                         p->regs [greg ++] = *(guint8*)(arg);
2659                         break;
2660                 case MONO_TYPE_I1:
2661                         p->regs [greg ++] = *(gint8*)(arg);
2662                         break;
2663                 case MONO_TYPE_I2:
2664                         p->regs [greg ++] = *(gint16*)(arg);
2665                         break;
2666                 case MONO_TYPE_U2:
2667                         p->regs [greg ++] = *(guint16*)(arg);
2668                         break;
2669                 case MONO_TYPE_I4:
2670                         p->regs [greg ++] = *(gint32*)(arg);
2671                         break;
2672                 case MONO_TYPE_U4:
2673                         p->regs [greg ++] = *(guint32*)(arg);
2674                         break;
2675                 case MONO_TYPE_GENERICINST:
2676                     if (MONO_TYPE_IS_REFERENCE (t)) {
2677                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2678                                 break;
2679                         } else {
2680                                 /* Fall through */
2681                         }
2682                 case MONO_TYPE_VALUETYPE: {
2683                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2684
2685                         g_assert (ainfo->storage == ArgValuetypeInReg);
2686                         if (ainfo->pair_storage [0] != ArgNone) {
2687                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2688                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2689                         }
2690                         if (ainfo->pair_storage [1] != ArgNone) {
2691                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2692                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2693                         }
2694                         break;
2695                 }
2696                 default:
2697                         g_assert_not_reached ();
2698                 }
2699         }
2700
2701         g_assert (greg <= PARAM_REGS);
2702 }
2703
2704 /*
2705  * mono_arch_finish_dyn_call:
2706  *
2707  *   Store the result of a dyn call into the return value buffer passed to
2708  * start_dyn_call ().
2709  * This function should be as fast as possible, any work which does not depend
2710  * on the actual values of the arguments should be done in
2711  * mono_arch_dyn_call_prepare ().
2712  */
2713 void
2714 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2715 {
2716         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2717         MonoMethodSignature *sig = dinfo->sig;
2718         guint8 *ret = ((DynCallArgs*)buf)->ret;
2719         mgreg_t res = ((DynCallArgs*)buf)->res;
2720         MonoType *sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
2721
2722         switch (sig_ret->type) {
2723         case MONO_TYPE_VOID:
2724                 *(gpointer*)ret = NULL;
2725                 break;
2726         case MONO_TYPE_STRING:
2727         case MONO_TYPE_CLASS:
2728         case MONO_TYPE_ARRAY:
2729         case MONO_TYPE_SZARRAY:
2730         case MONO_TYPE_OBJECT:
2731         case MONO_TYPE_I:
2732         case MONO_TYPE_U:
2733         case MONO_TYPE_PTR:
2734                 *(gpointer*)ret = GREG_TO_PTR(res);
2735                 break;
2736         case MONO_TYPE_I1:
2737                 *(gint8*)ret = res;
2738                 break;
2739         case MONO_TYPE_U1:
2740                 *(guint8*)ret = res;
2741                 break;
2742         case MONO_TYPE_I2:
2743                 *(gint16*)ret = res;
2744                 break;
2745         case MONO_TYPE_U2:
2746                 *(guint16*)ret = res;
2747                 break;
2748         case MONO_TYPE_I4:
2749                 *(gint32*)ret = res;
2750                 break;
2751         case MONO_TYPE_U4:
2752                 *(guint32*)ret = res;
2753                 break;
2754         case MONO_TYPE_I8:
2755                 *(gint64*)ret = res;
2756                 break;
2757         case MONO_TYPE_U8:
2758                 *(guint64*)ret = res;
2759                 break;
2760         case MONO_TYPE_GENERICINST:
2761                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2762                         *(gpointer*)ret = GREG_TO_PTR(res);
2763                         break;
2764                 } else {
2765                         /* Fall through */
2766                 }
2767         case MONO_TYPE_VALUETYPE:
2768                 if (dinfo->cinfo->vtype_retaddr) {
2769                         /* Nothing to do */
2770                 } else {
2771                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2772
2773                         g_assert (ainfo->storage == ArgValuetypeInReg);
2774
2775                         if (ainfo->pair_storage [0] != ArgNone) {
2776                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2777                                 ((mgreg_t*)ret)[0] = res;
2778                         }
2779
2780                         g_assert (ainfo->pair_storage [1] == ArgNone);
2781                 }
2782                 break;
2783         default:
2784                 g_assert_not_reached ();
2785         }
2786 }
2787
2788 /* emit an exception if condition is fail */
2789 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2790         do {                                                        \
2791                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2792                 if (tins == NULL) {                                                                             \
2793                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2794                                         MONO_PATCH_INFO_EXC, exc_name);  \
2795                         x86_branch32 (code, cond, 0, signed);               \
2796                 } else {        \
2797                         EMIT_COND_BRANCH (tins, cond, signed);  \
2798                 }                       \
2799         } while (0);
2800
2801 #define EMIT_FPCOMPARE(code) do { \
2802         amd64_fcompp (code); \
2803         amd64_fnstsw (code); \
2804 } while (0);
2805
2806 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2807     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2808         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2809         amd64_ ##op (code); \
2810         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2811         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2812 } while (0);
2813
2814 static guint8*
2815 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2816 {
2817         gboolean no_patch = FALSE;
2818
2819         /*
2820          * FIXME: Add support for thunks
2821          */
2822         {
2823                 gboolean near_call = FALSE;
2824
2825                 /*
2826                  * Indirect calls are expensive so try to make a near call if possible.
2827                  * The caller memory is allocated by the code manager so it is
2828                  * guaranteed to be at a 32 bit offset.
2829                  */
2830
2831                 if (patch_type != MONO_PATCH_INFO_ABS) {
2832                         /* The target is in memory allocated using the code manager */
2833                         near_call = TRUE;
2834
2835                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2836                                 if (((MonoMethod*)data)->klass->image->aot_module)
2837                                         /* The callee might be an AOT method */
2838                                         near_call = FALSE;
2839                                 if (((MonoMethod*)data)->dynamic)
2840                                         /* The target is in malloc-ed memory */
2841                                         near_call = FALSE;
2842                         }
2843
2844                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2845                                 /*
2846                                  * The call might go directly to a native function without
2847                                  * the wrapper.
2848                                  */
2849                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2850                                 if (mi) {
2851                                         gconstpointer target = mono_icall_get_wrapper (mi);
2852                                         if ((((guint64)target) >> 32) != 0)
2853                                                 near_call = FALSE;
2854                                 }
2855                         }
2856                 }
2857                 else {
2858                         MonoJumpInfo *jinfo = NULL;
2859
2860                         if (cfg->abs_patches)
2861                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2862                         if (jinfo) {
2863                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2864                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2865                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2866                                                 near_call = TRUE;
2867                                         no_patch = TRUE;
2868                                 } else {
2869                                         /*
2870                                          * This is not really an optimization, but required because the
2871                                          * generic class init trampolines use R11 to pass the vtable.
2872                                          */
2873                                         near_call = TRUE;
2874                                 }
2875                         } else {
2876                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2877                                 if (info) {
2878                                         if (info->func == info->wrapper) {
2879                                                 /* No wrapper */
2880                                                 if ((((guint64)info->func) >> 32) == 0)
2881                                                         near_call = TRUE;
2882                                         }
2883                                         else {
2884                                                 /* See the comment in mono_codegen () */
2885                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2886                                                         near_call = TRUE;
2887                                         }
2888                                 }
2889                                 else if ((((guint64)data) >> 32) == 0) {
2890                                         near_call = TRUE;
2891                                         no_patch = TRUE;
2892                                 }
2893                         }
2894                 }
2895
2896                 if (cfg->method->dynamic)
2897                         /* These methods are allocated using malloc */
2898                         near_call = FALSE;
2899
2900 #ifdef MONO_ARCH_NOMAP32BIT
2901                 near_call = FALSE;
2902 #endif
2903 #if defined(__native_client__)
2904                 /* Always use near_call == TRUE for Native Client */
2905                 near_call = TRUE;
2906 #endif
2907                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2908                 if (optimize_for_xen)
2909                         near_call = FALSE;
2910
2911                 if (cfg->compile_aot) {
2912                         near_call = TRUE;
2913                         no_patch = TRUE;
2914                 }
2915
2916                 if (near_call) {
2917                         /*
2918                          * Align the call displacement to an address divisible by 4 so it does
2919                          * not span cache lines. This is required for code patching to work on SMP
2920                          * systems.
2921                          */
2922                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2923                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2924                                 amd64_padding (code, pad_size);
2925                         }
2926                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2927                         amd64_call_code (code, 0);
2928                 }
2929                 else {
2930                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2931                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2932                         amd64_call_reg (code, GP_SCRATCH_REG);
2933                 }
2934         }
2935
2936         return code;
2937 }
2938
2939 static inline guint8*
2940 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2941 {
2942 #ifdef TARGET_WIN32
2943         if (win64_adjust_stack)
2944                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2945 #endif
2946         code = emit_call_body (cfg, code, patch_type, data);
2947 #ifdef TARGET_WIN32
2948         if (win64_adjust_stack)
2949                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2950 #endif
2951
2952         return code;
2953 }
2954
2955 static inline int
2956 store_membase_imm_to_store_membase_reg (int opcode)
2957 {
2958         switch (opcode) {
2959         case OP_STORE_MEMBASE_IMM:
2960                 return OP_STORE_MEMBASE_REG;
2961         case OP_STOREI4_MEMBASE_IMM:
2962                 return OP_STOREI4_MEMBASE_REG;
2963         case OP_STOREI8_MEMBASE_IMM:
2964                 return OP_STOREI8_MEMBASE_REG;
2965         }
2966
2967         return -1;
2968 }
2969
2970 #ifndef DISABLE_JIT
2971
2972 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2973
2974 /*
2975  * mono_arch_peephole_pass_1:
2976  *
2977  *   Perform peephole opts which should/can be performed before local regalloc
2978  */
2979 void
2980 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2981 {
2982         MonoInst *ins, *n;
2983
2984         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2985                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2986
2987                 switch (ins->opcode) {
2988                 case OP_ADD_IMM:
2989                 case OP_IADD_IMM:
2990                 case OP_LADD_IMM:
2991                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2992                                 /*
2993                                  * X86_LEA is like ADD, but doesn't have the
2994                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2995                                  * its operand to 64 bit.
2996                                  */
2997                                 ins->opcode = OP_X86_LEA_MEMBASE;
2998                                 ins->inst_basereg = ins->sreg1;
2999                         }
3000                         break;
3001                 case OP_LXOR:
3002                 case OP_IXOR:
3003                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3004                                 MonoInst *ins2;
3005
3006                                 /*
3007                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3008                                  * the latter has length 2-3 instead of 6 (reverse constant
3009                                  * propagation). These instruction sequences are very common
3010                                  * in the initlocals bblock.
3011                                  */
3012                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3013                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3014                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3015                                                 ins2->sreg1 = ins->dreg;
3016                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3017                                                 /* Continue */
3018                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3019                                                 NULLIFY_INS (ins2);
3020                                                 /* Continue */
3021                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3022                                                 /* Continue */
3023                                         } else {
3024                                                 break;
3025                                         }
3026                                 }
3027                         }
3028                         break;
3029                 case OP_COMPARE_IMM:
3030                 case OP_LCOMPARE_IMM:
3031                         /* OP_COMPARE_IMM (reg, 0)
3032                          * -->
3033                          * OP_AMD64_TEST_NULL (reg)
3034                          */
3035                         if (!ins->inst_imm)
3036                                 ins->opcode = OP_AMD64_TEST_NULL;
3037                         break;
3038                 case OP_ICOMPARE_IMM:
3039                         if (!ins->inst_imm)
3040                                 ins->opcode = OP_X86_TEST_NULL;
3041                         break;
3042                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3043                         /*
3044                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3045                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3046                          * -->
3047                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3048                          * OP_COMPARE_IMM reg, imm
3049                          *
3050                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3051                          */
3052                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3053                             ins->inst_basereg == last_ins->inst_destbasereg &&
3054                             ins->inst_offset == last_ins->inst_offset) {
3055                                         ins->opcode = OP_ICOMPARE_IMM;
3056                                         ins->sreg1 = last_ins->sreg1;
3057
3058                                         /* check if we can remove cmp reg,0 with test null */
3059                                         if (!ins->inst_imm)
3060                                                 ins->opcode = OP_X86_TEST_NULL;
3061                                 }
3062
3063                         break;
3064                 }
3065
3066                 mono_peephole_ins (bb, ins);
3067         }
3068 }
3069
3070 void
3071 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3072 {
3073         MonoInst *ins, *n;
3074
3075         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3076                 switch (ins->opcode) {
3077                 case OP_ICONST:
3078                 case OP_I8CONST: {
3079                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3080                         /* reg = 0 -> XOR (reg, reg) */
3081                         /* XOR sets cflags on x86, so we cant do it always */
3082                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3083                                 ins->opcode = OP_LXOR;
3084                                 ins->sreg1 = ins->dreg;
3085                                 ins->sreg2 = ins->dreg;
3086                                 /* Fall through */
3087                         } else {
3088                                 break;
3089                         }
3090                 }
3091                 case OP_LXOR:
3092                         /*
3093                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3094                          * 0 result into 64 bits.
3095                          */
3096                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3097                                 ins->opcode = OP_IXOR;
3098                         }
3099                         /* Fall through */
3100                 case OP_IXOR:
3101                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3102                                 MonoInst *ins2;
3103
3104                                 /*
3105                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3106                                  * the latter has length 2-3 instead of 6 (reverse constant
3107                                  * propagation). These instruction sequences are very common
3108                                  * in the initlocals bblock.
3109                                  */
3110                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3111                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3112                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3113                                                 ins2->sreg1 = ins->dreg;
3114                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3115                                                 /* Continue */
3116                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3117                                                 NULLIFY_INS (ins2);
3118                                                 /* Continue */
3119                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3120                                                 /* Continue */
3121                                         } else {
3122                                                 break;
3123                                         }
3124                                 }
3125                         }
3126                         break;
3127                 case OP_IADD_IMM:
3128                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3129                                 ins->opcode = OP_X86_INC_REG;
3130                         break;
3131                 case OP_ISUB_IMM:
3132                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3133                                 ins->opcode = OP_X86_DEC_REG;
3134                         break;
3135                 }
3136
3137                 mono_peephole_ins (bb, ins);
3138         }
3139 }
3140
3141 #define NEW_INS(cfg,ins,dest,op) do {   \
3142                 MONO_INST_NEW ((cfg), (dest), (op)); \
3143         (dest)->cil_code = (ins)->cil_code; \
3144         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3145         } while (0)
3146
3147 /*
3148  * mono_arch_lowering_pass:
3149  *
3150  *  Converts complex opcodes into simpler ones so that each IR instruction
3151  * corresponds to one machine instruction.
3152  */
3153 void
3154 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3155 {
3156         MonoInst *ins, *n, *temp;
3157
3158         /*
3159          * FIXME: Need to add more instructions, but the current machine
3160          * description can't model some parts of the composite instructions like
3161          * cdq.
3162          */
3163         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3164                 switch (ins->opcode) {
3165                 case OP_DIV_IMM:
3166                 case OP_REM_IMM:
3167                 case OP_IDIV_IMM:
3168                 case OP_IDIV_UN_IMM:
3169                 case OP_IREM_UN_IMM:
3170                 case OP_LREM_IMM:
3171                 case OP_IREM_IMM:
3172                         mono_decompose_op_imm (cfg, bb, ins);
3173                         break;
3174                 case OP_COMPARE_IMM:
3175                 case OP_LCOMPARE_IMM:
3176                         if (!amd64_is_imm32 (ins->inst_imm)) {
3177                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3178                                 temp->inst_c0 = ins->inst_imm;
3179                                 temp->dreg = mono_alloc_ireg (cfg);
3180                                 ins->opcode = OP_COMPARE;
3181                                 ins->sreg2 = temp->dreg;
3182                         }
3183                         break;
3184 #ifndef __mono_ilp32__
3185                 case OP_LOAD_MEMBASE:
3186 #endif
3187                 case OP_LOADI8_MEMBASE:
3188 #ifndef __native_client_codegen__
3189                 /*  Don't generate memindex opcodes (to simplify */
3190                 /*  read sandboxing) */
3191                         if (!amd64_is_imm32 (ins->inst_offset)) {
3192                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3193                                 temp->inst_c0 = ins->inst_offset;
3194                                 temp->dreg = mono_alloc_ireg (cfg);
3195                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3196                                 ins->inst_indexreg = temp->dreg;
3197                         }
3198 #endif
3199                         break;
3200 #ifndef __mono_ilp32__
3201                 case OP_STORE_MEMBASE_IMM:
3202 #endif
3203                 case OP_STOREI8_MEMBASE_IMM:
3204                         if (!amd64_is_imm32 (ins->inst_imm)) {
3205                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3206                                 temp->inst_c0 = ins->inst_imm;
3207                                 temp->dreg = mono_alloc_ireg (cfg);
3208                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3209                                 ins->sreg1 = temp->dreg;
3210                         }
3211                         break;
3212 #ifdef MONO_ARCH_SIMD_INTRINSICS
3213                 case OP_EXPAND_I1: {
3214                                 int temp_reg1 = mono_alloc_ireg (cfg);
3215                                 int temp_reg2 = mono_alloc_ireg (cfg);
3216                                 int original_reg = ins->sreg1;
3217
3218                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3219                                 temp->sreg1 = original_reg;
3220                                 temp->dreg = temp_reg1;
3221
3222                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3223                                 temp->sreg1 = temp_reg1;
3224                                 temp->dreg = temp_reg2;
3225                                 temp->inst_imm = 8;
3226
3227                                 NEW_INS (cfg, ins, temp, OP_LOR);
3228                                 temp->sreg1 = temp->dreg = temp_reg2;
3229                                 temp->sreg2 = temp_reg1;
3230
3231                                 ins->opcode = OP_EXPAND_I2;
3232                                 ins->sreg1 = temp_reg2;
3233                         }
3234                         break;
3235 #endif
3236                 default:
3237                         break;
3238                 }
3239         }
3240
3241         bb->max_vreg = cfg->next_vreg;
3242 }
3243
3244 static const int
3245 branch_cc_table [] = {
3246         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3247         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3248         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3249 };
3250
3251 /* Maps CMP_... constants to X86_CC_... constants */
3252 static const int
3253 cc_table [] = {
3254         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3255         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3256 };
3257
3258 static const int
3259 cc_signed_table [] = {
3260         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3261         FALSE, FALSE, FALSE, FALSE
3262 };
3263
3264 /*#include "cprop.c"*/
3265
3266 static unsigned char*
3267 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3268 {
3269         if (size == 8)
3270                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3271         else
3272                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3273
3274         if (size == 1)
3275                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3276         else if (size == 2)
3277                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3278         return code;
3279 }
3280
3281 static unsigned char*
3282 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3283 {
3284         int sreg = tree->sreg1;
3285         int need_touch = FALSE;
3286
3287 #if defined(TARGET_WIN32)
3288         need_touch = TRUE;
3289 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3290         if (!tree->flags & MONO_INST_INIT)
3291                 need_touch = TRUE;
3292 #endif
3293
3294         if (need_touch) {
3295                 guint8* br[5];
3296
3297                 /*
3298                  * Under Windows:
3299                  * If requested stack size is larger than one page,
3300                  * perform stack-touch operation
3301                  */
3302                 /*
3303                  * Generate stack probe code.
3304                  * Under Windows, it is necessary to allocate one page at a time,
3305                  * "touching" stack after each successful sub-allocation. This is
3306                  * because of the way stack growth is implemented - there is a
3307                  * guard page before the lowest stack page that is currently commited.
3308                  * Stack normally grows sequentially so OS traps access to the
3309                  * guard page and commits more pages when needed.
3310                  */
3311                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3312                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3313
3314                 br[2] = code; /* loop */
3315                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3316                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3317                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3318                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3319                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3320                 amd64_patch (br[3], br[2]);
3321                 amd64_test_reg_reg (code, sreg, sreg);
3322                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3323                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3324
3325                 br[1] = code; x86_jump8 (code, 0);
3326
3327                 amd64_patch (br[0], code);
3328                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3329                 amd64_patch (br[1], code);
3330                 amd64_patch (br[4], code);
3331         }
3332         else
3333                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3334
3335         if (tree->flags & MONO_INST_INIT) {
3336                 int offset = 0;
3337                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3338                         amd64_push_reg (code, AMD64_RAX);
3339                         offset += 8;
3340                 }
3341                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3342                         amd64_push_reg (code, AMD64_RCX);
3343                         offset += 8;
3344                 }
3345                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3346                         amd64_push_reg (code, AMD64_RDI);
3347                         offset += 8;
3348                 }
3349
3350                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3351                 if (sreg != AMD64_RCX)
3352                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3353                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3354
3355                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3356                 if (cfg->param_area)
3357                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3358                 amd64_cld (code);
3359 #if defined(__default_codegen__)
3360                 amd64_prefix (code, X86_REP_PREFIX);
3361                 amd64_stosl (code);
3362 #elif defined(__native_client_codegen__)
3363                 /* NaCl stos pseudo-instruction */
3364                 amd64_codegen_pre(code);
3365                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3366                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3367                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3368                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3369                 amd64_prefix (code, X86_REP_PREFIX);
3370                 amd64_stosl (code);
3371                 amd64_codegen_post(code);
3372 #endif /* __native_client_codegen__ */
3373
3374                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3375                         amd64_pop_reg (code, AMD64_RDI);
3376                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3377                         amd64_pop_reg (code, AMD64_RCX);
3378                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3379                         amd64_pop_reg (code, AMD64_RAX);
3380         }
3381         return code;
3382 }
3383
3384 static guint8*
3385 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3386 {
3387         CallInfo *cinfo;
3388         guint32 quad;
3389
3390         /* Move return value to the target register */
3391         /* FIXME: do this in the local reg allocator */
3392         switch (ins->opcode) {
3393         case OP_CALL:
3394         case OP_CALL_REG:
3395         case OP_CALL_MEMBASE:
3396         case OP_LCALL:
3397         case OP_LCALL_REG:
3398         case OP_LCALL_MEMBASE:
3399                 g_assert (ins->dreg == AMD64_RAX);
3400                 break;
3401         case OP_FCALL:
3402         case OP_FCALL_REG:
3403         case OP_FCALL_MEMBASE: {
3404                 MonoType *rtype = mini_get_underlying_type (cfg, ((MonoCallInst*)ins)->signature->ret);
3405                 if (rtype->type == MONO_TYPE_R4) {
3406                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3407                 }
3408                 else {
3409                         if (ins->dreg != AMD64_XMM0)
3410                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3411                 }
3412                 break;
3413         }
3414         case OP_RCALL:
3415         case OP_RCALL_REG:
3416         case OP_RCALL_MEMBASE:
3417                 if (ins->dreg != AMD64_XMM0)
3418                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3419                 break;
3420         case OP_VCALL:
3421         case OP_VCALL_REG:
3422         case OP_VCALL_MEMBASE:
3423         case OP_VCALL2:
3424         case OP_VCALL2_REG:
3425         case OP_VCALL2_MEMBASE:
3426                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3427                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3428                         MonoInst *loc = cfg->arch.vret_addr_loc;
3429
3430                         /* Load the destination address */
3431                         g_assert (loc->opcode == OP_REGOFFSET);
3432                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3433
3434                         for (quad = 0; quad < 2; quad ++) {
3435                                 switch (cinfo->ret.pair_storage [quad]) {
3436                                 case ArgInIReg:
3437                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3438                                         break;
3439                                 case ArgInFloatSSEReg:
3440                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3441                                         break;
3442                                 case ArgInDoubleSSEReg:
3443                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3444                                         break;
3445                                 case ArgNone:
3446                                         break;
3447                                 default:
3448                                         NOT_IMPLEMENTED;
3449                                 }
3450                         }
3451                 }
3452                 break;
3453         }
3454
3455         return code;
3456 }
3457
3458 #endif /* DISABLE_JIT */
3459
3460 #ifdef __APPLE__
3461 static int tls_gs_offset;
3462 #endif
3463
3464 gboolean
3465 mono_amd64_have_tls_get (void)
3466 {
3467 #ifdef TARGET_MACH
3468         static gboolean have_tls_get = FALSE;
3469         static gboolean inited = FALSE;
3470         guint8 *ins;
3471
3472         if (inited)
3473                 return have_tls_get;
3474
3475         ins = (guint8*)pthread_getspecific;
3476
3477         /*
3478          * We're looking for these two instructions:
3479          *
3480          * mov    %gs:[offset](,%rdi,8),%rax
3481          * retq
3482          */
3483         have_tls_get = ins [0] == 0x65 &&
3484                        ins [1] == 0x48 &&
3485                        ins [2] == 0x8b &&
3486                        ins [3] == 0x04 &&
3487                        ins [4] == 0xfd &&
3488                        ins [6] == 0x00 &&
3489                        ins [7] == 0x00 &&
3490                        ins [8] == 0x00 &&
3491                        ins [9] == 0xc3;
3492
3493         inited = TRUE;
3494
3495         tls_gs_offset = ins[5];
3496
3497         return have_tls_get;
3498 #elif defined(TARGET_ANDROID)
3499         return FALSE;
3500 #else
3501         return TRUE;
3502 #endif
3503 }
3504
3505 int
3506 mono_amd64_get_tls_gs_offset (void)
3507 {
3508 #ifdef TARGET_OSX
3509         return tls_gs_offset;
3510 #else
3511         g_assert_not_reached ();
3512         return -1;
3513 #endif
3514 }
3515
3516 /*
3517  * mono_amd64_emit_tls_get:
3518  * @code: buffer to store code to
3519  * @dreg: hard register where to place the result
3520  * @tls_offset: offset info
3521  *
3522  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3523  * the dreg register the item in the thread local storage identified
3524  * by tls_offset.
3525  *
3526  * Returns: a pointer to the end of the stored code
3527  */
3528 guint8*
3529 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3530 {
3531 #ifdef TARGET_WIN32
3532         if (tls_offset < 64) {
3533                 x86_prefix (code, X86_GS_PREFIX);
3534                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3535         } else {
3536                 guint8 *buf [16];
3537
3538                 g_assert (tls_offset < 0x440);
3539                 /* Load TEB->TlsExpansionSlots */
3540                 x86_prefix (code, X86_GS_PREFIX);
3541                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3542                 amd64_test_reg_reg (code, dreg, dreg);
3543                 buf [0] = code;
3544                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3545                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3546                 amd64_patch (buf [0], code);
3547         }
3548 #elif defined(__APPLE__)
3549         x86_prefix (code, X86_GS_PREFIX);
3550         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3551 #else
3552         if (optimize_for_xen) {
3553                 x86_prefix (code, X86_FS_PREFIX);
3554                 amd64_mov_reg_mem (code, dreg, 0, 8);
3555                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3556         } else {
3557                 x86_prefix (code, X86_FS_PREFIX);
3558                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3559         }
3560 #endif
3561         return code;
3562 }
3563
3564 static guint8*
3565 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3566 {
3567         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3568 #ifdef TARGET_OSX
3569         if (dreg != offset_reg)
3570                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3571         amd64_prefix (code, X86_GS_PREFIX);
3572         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3573 #elif defined(__linux__)
3574         int tmpreg = -1;
3575
3576         if (dreg == offset_reg) {
3577                 /* Use a temporary reg by saving it to the redzone */
3578                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3579                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3580                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3581                 offset_reg = tmpreg;
3582         }
3583         x86_prefix (code, X86_FS_PREFIX);
3584         amd64_mov_reg_mem (code, dreg, 0, 8);
3585         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3586         if (tmpreg != -1)
3587                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3588 #else
3589         g_assert_not_reached ();
3590 #endif
3591         return code;
3592 }
3593
3594 static guint8*
3595 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3596 {
3597 #ifdef TARGET_WIN32
3598         g_assert_not_reached ();
3599 #elif defined(__APPLE__)
3600         x86_prefix (code, X86_GS_PREFIX);
3601         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3602 #else
3603         g_assert (!optimize_for_xen);
3604         x86_prefix (code, X86_FS_PREFIX);
3605         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3606 #endif
3607         return code;
3608 }
3609
3610 static guint8*
3611 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3612 {
3613         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3614 #ifdef TARGET_WIN32
3615         g_assert_not_reached ();
3616 #elif defined(__APPLE__)
3617         x86_prefix (code, X86_GS_PREFIX);
3618         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3619 #else
3620         x86_prefix (code, X86_FS_PREFIX);
3621         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3622 #endif
3623         return code;
3624 }
3625
3626  /*
3627  * mono_arch_translate_tls_offset:
3628  *
3629  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3630  */
3631 int
3632 mono_arch_translate_tls_offset (int offset)
3633 {
3634 #ifdef __APPLE__
3635         return tls_gs_offset + (offset * 8);
3636 #else
3637         return offset;
3638 #endif
3639 }
3640
3641 /*
3642  * emit_setup_lmf:
3643  *
3644  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3645  */
3646 static guint8*
3647 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3648 {
3649         /*
3650          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3651          */
3652         /*
3653          * sp is saved right before calls but we need to save it here too so
3654          * async stack walks would work.
3655          */
3656         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3657         /* Save rbp */
3658         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3659         if (cfg->arch.omit_fp && cfa_offset != -1)
3660                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3661
3662         /* These can't contain refs */
3663         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3664         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3665         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3666         /* These are handled automatically by the stack marking code */
3667         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3668
3669         return code;
3670 }
3671
3672 #define REAL_PRINT_REG(text,reg) \
3673 mono_assert (reg >= 0); \
3674 amd64_push_reg (code, AMD64_RAX); \
3675 amd64_push_reg (code, AMD64_RDX); \
3676 amd64_push_reg (code, AMD64_RCX); \
3677 amd64_push_reg (code, reg); \
3678 amd64_push_imm (code, reg); \
3679 amd64_push_imm (code, text " %d %p\n"); \
3680 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3681 amd64_call_reg (code, AMD64_RAX); \
3682 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3683 amd64_pop_reg (code, AMD64_RCX); \
3684 amd64_pop_reg (code, AMD64_RDX); \
3685 amd64_pop_reg (code, AMD64_RAX);
3686
3687 /* benchmark and set based on cpu */
3688 #define LOOP_ALIGNMENT 8
3689 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3690
3691 #ifndef DISABLE_JIT
3692 void
3693 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3694 {
3695         MonoInst *ins;
3696         MonoCallInst *call;
3697         guint offset;
3698         guint8 *code = cfg->native_code + cfg->code_len;
3699         int max_len;
3700
3701         /* Fix max_offset estimate for each successor bb */
3702         if (cfg->opt & MONO_OPT_BRANCH) {
3703                 int current_offset = cfg->code_len;
3704                 MonoBasicBlock *current_bb;
3705                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3706                         current_bb->max_offset = current_offset;
3707                         current_offset += current_bb->max_length;
3708                 }
3709         }
3710
3711         if (cfg->opt & MONO_OPT_LOOP) {
3712                 int pad, align = LOOP_ALIGNMENT;
3713                 /* set alignment depending on cpu */
3714                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3715                         pad = align - pad;
3716                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3717                         amd64_padding (code, pad);
3718                         cfg->code_len += pad;
3719                         bb->native_offset = cfg->code_len;
3720                 }
3721         }
3722
3723 #if defined(__native_client_codegen__)
3724         /* For Native Client, all indirect call/jump targets must be */
3725         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3726         /* indirectly as well.                                       */
3727         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3728                                       (bb->flags & BB_EXCEPTION_HANDLER);
3729
3730         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3731                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3732                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3733                 cfg->code_len += pad;
3734                 bb->native_offset = cfg->code_len;
3735         }
3736 #endif  /*__native_client_codegen__*/
3737
3738         if (cfg->verbose_level > 2)
3739                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3740
3741         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3742                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3743                 g_assert (!cfg->compile_aot);
3744
3745                 cov->data [bb->dfn].cil_code = bb->cil_code;
3746                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3747                 /* this is not thread save, but good enough */
3748                 amd64_inc_membase (code, AMD64_R11, 0);
3749         }
3750
3751         offset = code - cfg->native_code;
3752
3753         mono_debug_open_block (cfg, bb, offset);
3754
3755     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3756                 x86_breakpoint (code);
3757
3758         MONO_BB_FOR_EACH_INS (bb, ins) {
3759                 offset = code - cfg->native_code;
3760
3761                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3762
3763 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3764
3765                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3766                         cfg->code_size *= 2;
3767                         cfg->native_code = mono_realloc_native_code(cfg);
3768                         code = cfg->native_code + offset;
3769                         cfg->stat_code_reallocs++;
3770                 }
3771
3772                 if (cfg->debug_info)
3773                         mono_debug_record_line_number (cfg, ins, offset);
3774
3775                 switch (ins->opcode) {
3776                 case OP_BIGMUL:
3777                         amd64_mul_reg (code, ins->sreg2, TRUE);
3778                         break;
3779                 case OP_BIGMUL_UN:
3780                         amd64_mul_reg (code, ins->sreg2, FALSE);
3781                         break;
3782                 case OP_X86_SETEQ_MEMBASE:
3783                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3784                         break;
3785                 case OP_STOREI1_MEMBASE_IMM:
3786                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3787                         break;
3788                 case OP_STOREI2_MEMBASE_IMM:
3789                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3790                         break;
3791                 case OP_STOREI4_MEMBASE_IMM:
3792                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3793                         break;
3794                 case OP_STOREI1_MEMBASE_REG:
3795                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3796                         break;
3797                 case OP_STOREI2_MEMBASE_REG:
3798                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3799                         break;
3800                 /* In AMD64 NaCl, pointers are 4 bytes, */
3801                 /*  so STORE_* != STOREI8_*. Likewise below. */
3802                 case OP_STORE_MEMBASE_REG:
3803                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3804                         break;
3805                 case OP_STOREI8_MEMBASE_REG:
3806                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3807                         break;
3808                 case OP_STOREI4_MEMBASE_REG:
3809                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3810                         break;
3811                 case OP_STORE_MEMBASE_IMM:
3812 #ifndef __native_client_codegen__
3813                         /* In NaCl, this could be a PCONST type, which could */
3814                         /* mean a pointer type was copied directly into the  */
3815                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3816                         /* the value would be 0x00000000FFFFFFFF which is    */
3817                         /* not proper for an imm32 unless you cast it.       */
3818                         g_assert (amd64_is_imm32 (ins->inst_imm));
3819 #endif
3820                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3821                         break;
3822                 case OP_STOREI8_MEMBASE_IMM:
3823                         g_assert (amd64_is_imm32 (ins->inst_imm));
3824                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3825                         break;
3826                 case OP_LOAD_MEM:
3827 #ifdef __mono_ilp32__
3828                         /* In ILP32, pointers are 4 bytes, so separate these */
3829                         /* cases, use literal 8 below where we really want 8 */
3830                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3831                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3832                         break;
3833 #endif
3834                 case OP_LOADI8_MEM:
3835                         // FIXME: Decompose this earlier
3836                         if (amd64_is_imm32 (ins->inst_imm))
3837                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3838                         else {
3839                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3840                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3841                         }
3842                         break;
3843                 case OP_LOADI4_MEM:
3844                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3845                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3846                         break;
3847                 case OP_LOADU4_MEM:
3848                         // FIXME: Decompose this earlier
3849                         if (amd64_is_imm32 (ins->inst_imm))
3850                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3851                         else {
3852                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3853                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3854                         }
3855                         break;
3856                 case OP_LOADU1_MEM:
3857                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3858                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3859                         break;
3860                 case OP_LOADU2_MEM:
3861                         /* For NaCl, pointers are 4 bytes, so separate these */
3862                         /* cases, use literal 8 below where we really want 8 */
3863                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3864                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3865                         break;
3866                 case OP_LOAD_MEMBASE:
3867                         g_assert (amd64_is_imm32 (ins->inst_offset));
3868                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3869                         break;
3870                 case OP_LOADI8_MEMBASE:
3871                         /* Use literal 8 instead of sizeof pointer or */
3872                         /* register, we really want 8 for this opcode */
3873                         g_assert (amd64_is_imm32 (ins->inst_offset));
3874                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3875                         break;
3876                 case OP_LOADI4_MEMBASE:
3877                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3878                         break;
3879                 case OP_LOADU4_MEMBASE:
3880                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3881                         break;
3882                 case OP_LOADU1_MEMBASE:
3883                         /* The cpu zero extends the result into 64 bits */
3884                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3885                         break;
3886                 case OP_LOADI1_MEMBASE:
3887                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3888                         break;
3889                 case OP_LOADU2_MEMBASE:
3890                         /* The cpu zero extends the result into 64 bits */
3891                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3892                         break;
3893                 case OP_LOADI2_MEMBASE:
3894                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3895                         break;
3896                 case OP_AMD64_LOADI8_MEMINDEX:
3897                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3898                         break;
3899                 case OP_LCONV_TO_I1:
3900                 case OP_ICONV_TO_I1:
3901                 case OP_SEXT_I1:
3902                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3903                         break;
3904                 case OP_LCONV_TO_I2:
3905                 case OP_ICONV_TO_I2:
3906                 case OP_SEXT_I2:
3907                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3908                         break;
3909                 case OP_LCONV_TO_U1:
3910                 case OP_ICONV_TO_U1:
3911                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3912                         break;
3913                 case OP_LCONV_TO_U2:
3914                 case OP_ICONV_TO_U2:
3915                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3916                         break;
3917                 case OP_ZEXT_I4:
3918                         /* Clean out the upper word */
3919                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3920                         break;
3921                 case OP_SEXT_I4:
3922                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3923                         break;
3924                 case OP_COMPARE:
3925                 case OP_LCOMPARE:
3926                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3927                         break;
3928                 case OP_COMPARE_IMM:
3929 #if defined(__mono_ilp32__)
3930                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3931                         g_assert (amd64_is_imm32 (ins->inst_imm));
3932                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3933                         break;
3934 #endif
3935                 case OP_LCOMPARE_IMM:
3936                         g_assert (amd64_is_imm32 (ins->inst_imm));
3937                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3938                         break;
3939                 case OP_X86_COMPARE_REG_MEMBASE:
3940                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3941                         break;
3942                 case OP_X86_TEST_NULL:
3943                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3944                         break;
3945                 case OP_AMD64_TEST_NULL:
3946                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3947                         break;
3948
3949                 case OP_X86_ADD_REG_MEMBASE:
3950                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3951                         break;
3952                 case OP_X86_SUB_REG_MEMBASE:
3953                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3954                         break;
3955                 case OP_X86_AND_REG_MEMBASE:
3956                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3957                         break;
3958                 case OP_X86_OR_REG_MEMBASE:
3959                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3960                         break;
3961                 case OP_X86_XOR_REG_MEMBASE:
3962                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3963                         break;
3964
3965                 case OP_X86_ADD_MEMBASE_IMM:
3966                         /* FIXME: Make a 64 version too */
3967                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3968                         break;
3969                 case OP_X86_SUB_MEMBASE_IMM:
3970                         g_assert (amd64_is_imm32 (ins->inst_imm));
3971                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3972                         break;
3973                 case OP_X86_AND_MEMBASE_IMM:
3974                         g_assert (amd64_is_imm32 (ins->inst_imm));
3975                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3976                         break;
3977                 case OP_X86_OR_MEMBASE_IMM:
3978                         g_assert (amd64_is_imm32 (ins->inst_imm));
3979                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3980                         break;
3981                 case OP_X86_XOR_MEMBASE_IMM:
3982                         g_assert (amd64_is_imm32 (ins->inst_imm));
3983                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3984                         break;
3985                 case OP_X86_ADD_MEMBASE_REG:
3986                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3987                         break;
3988                 case OP_X86_SUB_MEMBASE_REG:
3989                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3990                         break;
3991                 case OP_X86_AND_MEMBASE_REG:
3992                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3993                         break;
3994                 case OP_X86_OR_MEMBASE_REG:
3995                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3996                         break;
3997                 case OP_X86_XOR_MEMBASE_REG:
3998                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3999                         break;
4000                 case OP_X86_INC_MEMBASE:
4001                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4002                         break;
4003                 case OP_X86_INC_REG:
4004                         amd64_inc_reg_size (code, ins->dreg, 4);
4005                         break;
4006                 case OP_X86_DEC_MEMBASE:
4007                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4008                         break;
4009                 case OP_X86_DEC_REG:
4010                         amd64_dec_reg_size (code, ins->dreg, 4);
4011                         break;
4012                 case OP_X86_MUL_REG_MEMBASE:
4013                 case OP_X86_MUL_MEMBASE_REG:
4014                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4015                         break;
4016                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4017                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4018                         break;
4019                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4020                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4021                         break;
4022                 case OP_AMD64_COMPARE_MEMBASE_REG:
4023                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4024                         break;
4025                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4026                         g_assert (amd64_is_imm32 (ins->inst_imm));
4027                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4028                         break;
4029                 case OP_X86_COMPARE_MEMBASE8_IMM:
4030                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4031                         break;
4032                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4033                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4034                         break;
4035                 case OP_AMD64_COMPARE_REG_MEMBASE:
4036                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4037                         break;
4038
4039                 case OP_AMD64_ADD_REG_MEMBASE:
4040                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4041                         break;
4042                 case OP_AMD64_SUB_REG_MEMBASE:
4043                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4044                         break;
4045                 case OP_AMD64_AND_REG_MEMBASE:
4046                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4047                         break;
4048                 case OP_AMD64_OR_REG_MEMBASE:
4049                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4050                         break;
4051                 case OP_AMD64_XOR_REG_MEMBASE:
4052                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4053                         break;
4054
4055                 case OP_AMD64_ADD_MEMBASE_REG:
4056                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4057                         break;
4058                 case OP_AMD64_SUB_MEMBASE_REG:
4059                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4060                         break;
4061                 case OP_AMD64_AND_MEMBASE_REG:
4062                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4063                         break;
4064                 case OP_AMD64_OR_MEMBASE_REG:
4065                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4066                         break;
4067                 case OP_AMD64_XOR_MEMBASE_REG:
4068                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4069                         break;
4070
4071                 case OP_AMD64_ADD_MEMBASE_IMM:
4072                         g_assert (amd64_is_imm32 (ins->inst_imm));
4073                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4074                         break;
4075                 case OP_AMD64_SUB_MEMBASE_IMM:
4076                         g_assert (amd64_is_imm32 (ins->inst_imm));
4077                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4078                         break;
4079                 case OP_AMD64_AND_MEMBASE_IMM:
4080                         g_assert (amd64_is_imm32 (ins->inst_imm));
4081                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4082                         break;
4083                 case OP_AMD64_OR_MEMBASE_IMM:
4084                         g_assert (amd64_is_imm32 (ins->inst_imm));
4085                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4086                         break;
4087                 case OP_AMD64_XOR_MEMBASE_IMM:
4088                         g_assert (amd64_is_imm32 (ins->inst_imm));
4089                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4090                         break;
4091
4092                 case OP_BREAK:
4093                         amd64_breakpoint (code);
4094                         break;
4095                 case OP_RELAXED_NOP:
4096                         x86_prefix (code, X86_REP_PREFIX);
4097                         x86_nop (code);
4098                         break;
4099                 case OP_HARD_NOP:
4100                         x86_nop (code);
4101                         break;
4102                 case OP_NOP:
4103                 case OP_DUMMY_USE:
4104                 case OP_DUMMY_STORE:
4105                 case OP_DUMMY_ICONST:
4106                 case OP_DUMMY_R8CONST:
4107                 case OP_NOT_REACHED:
4108                 case OP_NOT_NULL:
4109                         break;
4110                 case OP_IL_SEQ_POINT:
4111                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4112                         break;
4113                 case OP_SEQ_POINT: {
4114                         int i;
4115
4116                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4117                                 if (cfg->compile_aot) {
4118                                         MonoInst *var = cfg->arch.ss_tramp_var;
4119                                         guint8 *label;
4120
4121                                         /* Load ss_tramp_var */
4122                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4123                                         /* Load the trampoline address */
4124                                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4125                                         /* Call it if it is non-null */
4126                                         amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4127                                         label = code;
4128                                         amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4129                                         amd64_call_reg (code, AMD64_R11);
4130                                         amd64_patch (label, code);
4131                                 } else {
4132                                         /*
4133                                          * Read from the single stepping trigger page. This will cause a
4134                                          * SIGSEGV when single stepping is enabled.
4135                                          * We do this _before_ the breakpoint, so single stepping after
4136                                          * a breakpoint is hit will step to the next IL offset.
4137                                          */
4138                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
4139
4140                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4141                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4142                                 }
4143                         }
4144
4145                         /*
4146                          * This is the address which is saved in seq points,
4147                          */
4148                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4149
4150                         if (cfg->compile_aot) {
4151                                 guint32 offset = code - cfg->native_code;
4152                                 guint32 val;
4153                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4154                                 guint8 *label;
4155
4156                                 /* Load info var */
4157                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4158                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4159                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4160                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4161                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4162                                 label = code;
4163                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4164                                 /* Call the trampoline */
4165                                 amd64_call_reg (code, AMD64_R11);
4166                                 amd64_patch (label, code);
4167                         } else {
4168                                 /*
4169                                  * A placeholder for a possible breakpoint inserted by
4170                                  * mono_arch_set_breakpoint ().
4171                                  */
4172                                 for (i = 0; i < breakpoint_size; ++i)
4173                                         x86_nop (code);
4174                         }
4175                         /*
4176                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4177                          * to another IL offset.
4178                          */
4179                         x86_nop (code);
4180                         break;
4181                 }
4182                 case OP_ADDCC:
4183                 case OP_LADDCC:
4184                 case OP_LADD:
4185                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4186                         break;
4187                 case OP_ADC:
4188                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4189                         break;
4190                 case OP_ADD_IMM:
4191                 case OP_LADD_IMM:
4192                         g_assert (amd64_is_imm32 (ins->inst_imm));
4193                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4194                         break;
4195                 case OP_ADC_IMM:
4196                         g_assert (amd64_is_imm32 (ins->inst_imm));
4197                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4198                         break;
4199                 case OP_SUBCC:
4200                 case OP_LSUBCC:
4201                 case OP_LSUB:
4202                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4203                         break;
4204                 case OP_SBB:
4205                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4206                         break;
4207                 case OP_SUB_IMM:
4208                 case OP_LSUB_IMM:
4209                         g_assert (amd64_is_imm32 (ins->inst_imm));
4210                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4211                         break;
4212                 case OP_SBB_IMM:
4213                         g_assert (amd64_is_imm32 (ins->inst_imm));
4214                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4215                         break;
4216                 case OP_LAND:
4217                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4218                         break;
4219                 case OP_AND_IMM:
4220                 case OP_LAND_IMM:
4221                         g_assert (amd64_is_imm32 (ins->inst_imm));
4222                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4223                         break;
4224                 case OP_LMUL:
4225                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4226                         break;
4227                 case OP_MUL_IMM:
4228                 case OP_LMUL_IMM:
4229                 case OP_IMUL_IMM: {
4230                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4231
4232                         switch (ins->inst_imm) {
4233                         case 2:
4234                                 /* MOV r1, r2 */
4235                                 /* ADD r1, r1 */
4236                                 if (ins->dreg != ins->sreg1)
4237                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4238                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4239                                 break;
4240                         case 3:
4241                                 /* LEA r1, [r2 + r2*2] */
4242                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4243                                 break;
4244                         case 5:
4245                                 /* LEA r1, [r2 + r2*4] */
4246                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4247                                 break;
4248                         case 6:
4249                                 /* LEA r1, [r2 + r2*2] */
4250                                 /* ADD r1, r1          */
4251                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4252                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4253                                 break;
4254                         case 9:
4255                                 /* LEA r1, [r2 + r2*8] */
4256                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4257                                 break;
4258                         case 10:
4259                                 /* LEA r1, [r2 + r2*4] */
4260                                 /* ADD r1, r1          */
4261                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4262                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4263                                 break;
4264                         case 12:
4265                                 /* LEA r1, [r2 + r2*2] */
4266                                 /* SHL r1, 2           */
4267                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4268                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4269                                 break;
4270                         case 25:
4271                                 /* LEA r1, [r2 + r2*4] */
4272                                 /* LEA r1, [r1 + r1*4] */
4273                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4274                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4275                                 break;
4276                         case 100:
4277                                 /* LEA r1, [r2 + r2*4] */
4278                                 /* SHL r1, 2           */
4279                                 /* LEA r1, [r1 + r1*4] */
4280                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4281                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4282                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4283                                 break;
4284                         default:
4285                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4286                                 break;
4287                         }
4288                         break;
4289                 }
4290                 case OP_LDIV:
4291                 case OP_LREM:
4292 #if defined( __native_client_codegen__ )
4293                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4294                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4295 #endif
4296                         /* Regalloc magic makes the div/rem cases the same */
4297                         if (ins->sreg2 == AMD64_RDX) {
4298                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4299                                 amd64_cdq (code);
4300                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4301                         } else {
4302                                 amd64_cdq (code);
4303                                 amd64_div_reg (code, ins->sreg2, TRUE);
4304                         }
4305                         break;
4306                 case OP_LDIV_UN:
4307                 case OP_LREM_UN:
4308 #if defined( __native_client_codegen__ )
4309                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4310                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4311 #endif
4312                         if (ins->sreg2 == AMD64_RDX) {
4313                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4314                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4315                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4316                         } else {
4317                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4318                                 amd64_div_reg (code, ins->sreg2, FALSE);
4319                         }
4320                         break;
4321                 case OP_IDIV:
4322                 case OP_IREM:
4323 #if defined( __native_client_codegen__ )
4324                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4325                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4326 #endif
4327                         if (ins->sreg2 == AMD64_RDX) {
4328                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4329                                 amd64_cdq_size (code, 4);
4330                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4331                         } else {
4332                                 amd64_cdq_size (code, 4);
4333                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4334                         }
4335                         break;
4336                 case OP_IDIV_UN:
4337                 case OP_IREM_UN:
4338 #if defined( __native_client_codegen__ )
4339                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4340                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4341 #endif
4342                         if (ins->sreg2 == AMD64_RDX) {
4343                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4344                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4345                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4346                         } else {
4347                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4348                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4349                         }
4350                         break;
4351                 case OP_LMUL_OVF:
4352                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4353                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4354                         break;
4355                 case OP_LOR:
4356                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4357                         break;
4358                 case OP_OR_IMM:
4359                 case OP_LOR_IMM:
4360                         g_assert (amd64_is_imm32 (ins->inst_imm));
4361                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4362                         break;
4363                 case OP_LXOR:
4364                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4365                         break;
4366                 case OP_XOR_IMM:
4367                 case OP_LXOR_IMM:
4368                         g_assert (amd64_is_imm32 (ins->inst_imm));
4369                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4370                         break;
4371                 case OP_LSHL:
4372                         g_assert (ins->sreg2 == AMD64_RCX);
4373                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4374                         break;
4375                 case OP_LSHR:
4376                         g_assert (ins->sreg2 == AMD64_RCX);
4377                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4378                         break;
4379                 case OP_SHR_IMM:
4380                 case OP_LSHR_IMM:
4381                         g_assert (amd64_is_imm32 (ins->inst_imm));
4382                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4383                         break;
4384                 case OP_SHR_UN_IMM:
4385                         g_assert (amd64_is_imm32 (ins->inst_imm));
4386                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4387                         break;
4388                 case OP_LSHR_UN_IMM:
4389                         g_assert (amd64_is_imm32 (ins->inst_imm));
4390                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4391                         break;
4392                 case OP_LSHR_UN:
4393                         g_assert (ins->sreg2 == AMD64_RCX);
4394                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4395                         break;
4396                 case OP_SHL_IMM:
4397                 case OP_LSHL_IMM:
4398                         g_assert (amd64_is_imm32 (ins->inst_imm));
4399                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4400                         break;
4401
4402                 case OP_IADDCC:
4403                 case OP_IADD:
4404                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4405                         break;
4406                 case OP_IADC:
4407                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4408                         break;
4409                 case OP_IADD_IMM:
4410                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4411                         break;
4412                 case OP_IADC_IMM:
4413                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4414                         break;
4415                 case OP_ISUBCC:
4416                 case OP_ISUB:
4417                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4418                         break;
4419                 case OP_ISBB:
4420                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4421                         break;
4422                 case OP_ISUB_IMM:
4423                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4424                         break;
4425                 case OP_ISBB_IMM:
4426                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4427                         break;
4428                 case OP_IAND:
4429                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4430                         break;
4431                 case OP_IAND_IMM:
4432                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4433                         break;
4434                 case OP_IOR:
4435                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4436                         break;
4437                 case OP_IOR_IMM:
4438                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4439                         break;
4440                 case OP_IXOR:
4441                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4442                         break;
4443                 case OP_IXOR_IMM:
4444                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4445                         break;
4446                 case OP_INEG:
4447                         amd64_neg_reg_size (code, ins->sreg1, 4);
4448                         break;
4449                 case OP_INOT:
4450                         amd64_not_reg_size (code, ins->sreg1, 4);
4451                         break;
4452                 case OP_ISHL:
4453                         g_assert (ins->sreg2 == AMD64_RCX);
4454                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4455                         break;
4456                 case OP_ISHR:
4457                         g_assert (ins->sreg2 == AMD64_RCX);
4458                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4459                         break;
4460                 case OP_ISHR_IMM:
4461                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4462                         break;
4463                 case OP_ISHR_UN_IMM:
4464                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4465                         break;
4466                 case OP_ISHR_UN:
4467                         g_assert (ins->sreg2 == AMD64_RCX);
4468                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4469                         break;
4470                 case OP_ISHL_IMM:
4471                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4472                         break;
4473                 case OP_IMUL:
4474                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4475                         break;
4476                 case OP_IMUL_OVF:
4477                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4478                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4479                         break;
4480                 case OP_IMUL_OVF_UN:
4481                 case OP_LMUL_OVF_UN: {
4482                         /* the mul operation and the exception check should most likely be split */
4483                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4484                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4485                         /*g_assert (ins->sreg2 == X86_EAX);
4486                         g_assert (ins->dreg == X86_EAX);*/
4487                         if (ins->sreg2 == X86_EAX) {
4488                                 non_eax_reg = ins->sreg1;
4489                         } else if (ins->sreg1 == X86_EAX) {
4490                                 non_eax_reg = ins->sreg2;
4491                         } else {
4492                                 /* no need to save since we're going to store to it anyway */
4493                                 if (ins->dreg != X86_EAX) {
4494                                         saved_eax = TRUE;
4495                                         amd64_push_reg (code, X86_EAX);
4496                                 }
4497                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4498                                 non_eax_reg = ins->sreg2;
4499                         }
4500                         if (ins->dreg == X86_EDX) {
4501                                 if (!saved_eax) {
4502                                         saved_eax = TRUE;
4503                                         amd64_push_reg (code, X86_EAX);
4504                                 }
4505                         } else {
4506                                 saved_edx = TRUE;
4507                                 amd64_push_reg (code, X86_EDX);
4508                         }
4509                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4510                         /* save before the check since pop and mov don't change the flags */
4511                         if (ins->dreg != X86_EAX)
4512                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4513                         if (saved_edx)
4514                                 amd64_pop_reg (code, X86_EDX);
4515                         if (saved_eax)
4516                                 amd64_pop_reg (code, X86_EAX);
4517                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4518                         break;
4519                 }
4520                 case OP_ICOMPARE:
4521                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4522                         break;
4523                 case OP_ICOMPARE_IMM:
4524                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4525                         break;
4526                 case OP_IBEQ:
4527                 case OP_IBLT:
4528                 case OP_IBGT:
4529                 case OP_IBGE:
4530                 case OP_IBLE:
4531                 case OP_LBEQ:
4532                 case OP_LBLT:
4533                 case OP_LBGT:
4534                 case OP_LBGE:
4535                 case OP_LBLE:
4536                 case OP_IBNE_UN:
4537                 case OP_IBLT_UN:
4538                 case OP_IBGT_UN:
4539                 case OP_IBGE_UN:
4540                 case OP_IBLE_UN:
4541                 case OP_LBNE_UN:
4542                 case OP_LBLT_UN:
4543                 case OP_LBGT_UN:
4544                 case OP_LBGE_UN:
4545                 case OP_LBLE_UN:
4546                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4547                         break;
4548
4549                 case OP_CMOV_IEQ:
4550                 case OP_CMOV_IGE:
4551                 case OP_CMOV_IGT:
4552                 case OP_CMOV_ILE:
4553                 case OP_CMOV_ILT:
4554                 case OP_CMOV_INE_UN:
4555                 case OP_CMOV_IGE_UN:
4556                 case OP_CMOV_IGT_UN:
4557                 case OP_CMOV_ILE_UN:
4558                 case OP_CMOV_ILT_UN:
4559                 case OP_CMOV_LEQ:
4560                 case OP_CMOV_LGE:
4561                 case OP_CMOV_LGT:
4562                 case OP_CMOV_LLE:
4563                 case OP_CMOV_LLT:
4564                 case OP_CMOV_LNE_UN:
4565                 case OP_CMOV_LGE_UN:
4566                 case OP_CMOV_LGT_UN:
4567                 case OP_CMOV_LLE_UN:
4568                 case OP_CMOV_LLT_UN:
4569                         g_assert (ins->dreg == ins->sreg1);
4570                         /* This needs to operate on 64 bit values */
4571                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4572                         break;
4573
4574                 case OP_LNOT:
4575                         amd64_not_reg (code, ins->sreg1);
4576                         break;
4577                 case OP_LNEG:
4578                         amd64_neg_reg (code, ins->sreg1);
4579                         break;
4580
4581                 case OP_ICONST:
4582                 case OP_I8CONST:
4583                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4584                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4585                         else
4586                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4587                         break;
4588                 case OP_AOTCONST:
4589                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4590                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4591                         break;
4592                 case OP_JUMP_TABLE:
4593                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4594                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4595                         break;
4596                 case OP_MOVE:
4597                         if (ins->dreg != ins->sreg1)
4598                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4599                         break;
4600                 case OP_AMD64_SET_XMMREG_R4: {
4601                         if (cfg->r4fp) {
4602                                 if (ins->dreg != ins->sreg1)
4603                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4604                         } else {
4605                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4606                         }
4607                         break;
4608                 }
4609                 case OP_AMD64_SET_XMMREG_R8: {
4610                         if (ins->dreg != ins->sreg1)
4611                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4612                         break;
4613                 }
4614                 case OP_TAILCALL: {
4615                         MonoCallInst *call = (MonoCallInst*)ins;
4616                         int i, save_area_offset;
4617
4618                         g_assert (!cfg->method->save_lmf);
4619
4620                         /* Restore callee saved registers */
4621                         save_area_offset = cfg->arch.reg_save_area_offset;
4622                         for (i = 0; i < AMD64_NREG; ++i)
4623                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4624                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4625                                         save_area_offset += 8;
4626                                 }
4627
4628                         if (cfg->arch.omit_fp) {
4629                                 if (cfg->arch.stack_alloc_size)
4630                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4631                                 // FIXME:
4632                                 if (call->stack_usage)
4633                                         NOT_IMPLEMENTED;
4634                         } else {
4635                                 /* Copy arguments on the stack to our argument area */
4636                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4637                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4638                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4639                                 }
4640
4641                                 amd64_leave (code);
4642                         }
4643
4644                         offset = code - cfg->native_code;
4645                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4646                         if (cfg->compile_aot)
4647                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4648                         else
4649                                 amd64_set_reg_template (code, AMD64_R11);
4650                         amd64_jump_reg (code, AMD64_R11);
4651                         ins->flags |= MONO_INST_GC_CALLSITE;
4652                         ins->backend.pc_offset = code - cfg->native_code;
4653                         break;
4654                 }
4655                 case OP_CHECK_THIS:
4656                         /* ensure ins->sreg1 is not NULL */
4657                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4658                         break;
4659                 case OP_ARGLIST: {
4660                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4661                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4662                         break;
4663                 }
4664                 case OP_CALL:
4665                 case OP_FCALL:
4666                 case OP_RCALL:
4667                 case OP_LCALL:
4668                 case OP_VCALL:
4669                 case OP_VCALL2:
4670                 case OP_VOIDCALL:
4671                         call = (MonoCallInst*)ins;
4672                         /*
4673                          * The AMD64 ABI forces callers to know about varargs.
4674                          */
4675                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4676                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4677                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4678                                 /*
4679                                  * Since the unmanaged calling convention doesn't contain a
4680                                  * 'vararg' entry, we have to treat every pinvoke call as a
4681                                  * potential vararg call.
4682                                  */
4683                                 guint32 nregs, i;
4684                                 nregs = 0;
4685                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4686                                         if (call->used_fregs & (1 << i))
4687                                                 nregs ++;
4688                                 if (!nregs)
4689                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4690                                 else
4691                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4692                         }
4693
4694                         if (ins->flags & MONO_INST_HAS_METHOD)
4695                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4696                         else
4697                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4698                         ins->flags |= MONO_INST_GC_CALLSITE;
4699                         ins->backend.pc_offset = code - cfg->native_code;
4700                         code = emit_move_return_value (cfg, ins, code);
4701                         break;
4702                 case OP_FCALL_REG:
4703                 case OP_RCALL_REG:
4704                 case OP_LCALL_REG:
4705                 case OP_VCALL_REG:
4706                 case OP_VCALL2_REG:
4707                 case OP_VOIDCALL_REG:
4708                 case OP_CALL_REG:
4709                         call = (MonoCallInst*)ins;
4710
4711                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4712                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4713                                 ins->sreg1 = AMD64_R11;
4714                         }
4715
4716                         /*
4717                          * The AMD64 ABI forces callers to know about varargs.
4718                          */
4719                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4720                                 if (ins->sreg1 == AMD64_RAX) {
4721                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4722                                         ins->sreg1 = AMD64_R11;
4723                                 }
4724                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4725                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4726                                 /*
4727                                  * Since the unmanaged calling convention doesn't contain a
4728                                  * 'vararg' entry, we have to treat every pinvoke call as a
4729                                  * potential vararg call.
4730                                  */
4731                                 guint32 nregs, i;
4732                                 nregs = 0;
4733                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4734                                         if (call->used_fregs & (1 << i))
4735                                                 nregs ++;
4736                                 if (ins->sreg1 == AMD64_RAX) {
4737                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4738                                         ins->sreg1 = AMD64_R11;
4739                                 }
4740                                 if (!nregs)
4741                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4742                                 else
4743                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4744                         }
4745
4746                         amd64_call_reg (code, ins->sreg1);
4747                         ins->flags |= MONO_INST_GC_CALLSITE;
4748                         ins->backend.pc_offset = code - cfg->native_code;
4749                         code = emit_move_return_value (cfg, ins, code);
4750                         break;
4751                 case OP_FCALL_MEMBASE:
4752                 case OP_RCALL_MEMBASE:
4753                 case OP_LCALL_MEMBASE:
4754                 case OP_VCALL_MEMBASE:
4755                 case OP_VCALL2_MEMBASE:
4756                 case OP_VOIDCALL_MEMBASE:
4757                 case OP_CALL_MEMBASE:
4758                         call = (MonoCallInst*)ins;
4759
4760                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4761                         ins->flags |= MONO_INST_GC_CALLSITE;
4762                         ins->backend.pc_offset = code - cfg->native_code;
4763                         code = emit_move_return_value (cfg, ins, code);
4764                         break;
4765                 case OP_DYN_CALL: {
4766                         int i;
4767                         MonoInst *var = cfg->dyn_call_var;
4768
4769                         g_assert (var->opcode == OP_REGOFFSET);
4770
4771                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4772                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4773                         /* r10 = ftn */
4774                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4775
4776                         /* Save args buffer */
4777                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4778
4779                         /* Set argument registers */
4780                         for (i = 0; i < PARAM_REGS; ++i)
4781                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4782
4783                         /* Make the call */
4784                         amd64_call_reg (code, AMD64_R10);
4785
4786                         ins->flags |= MONO_INST_GC_CALLSITE;
4787                         ins->backend.pc_offset = code - cfg->native_code;
4788
4789                         /* Save result */
4790                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4791                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4792                         break;
4793                 }
4794                 case OP_AMD64_SAVE_SP_TO_LMF: {
4795                         MonoInst *lmf_var = cfg->lmf_var;
4796                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4797                         break;
4798                 }
4799                 case OP_X86_PUSH:
4800                         g_assert_not_reached ();
4801                         amd64_push_reg (code, ins->sreg1);
4802                         break;
4803                 case OP_X86_PUSH_IMM:
4804                         g_assert_not_reached ();
4805                         g_assert (amd64_is_imm32 (ins->inst_imm));
4806                         amd64_push_imm (code, ins->inst_imm);
4807                         break;
4808                 case OP_X86_PUSH_MEMBASE:
4809                         g_assert_not_reached ();
4810                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4811                         break;
4812                 case OP_X86_PUSH_OBJ: {
4813                         int size = ALIGN_TO (ins->inst_imm, 8);
4814
4815                         g_assert_not_reached ();
4816
4817                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4818                         amd64_push_reg (code, AMD64_RDI);
4819                         amd64_push_reg (code, AMD64_RSI);
4820                         amd64_push_reg (code, AMD64_RCX);
4821                         if (ins->inst_offset)
4822                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4823                         else
4824                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4825                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4826                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4827                         amd64_cld (code);
4828                         amd64_prefix (code, X86_REP_PREFIX);
4829                         amd64_movsd (code);
4830                         amd64_pop_reg (code, AMD64_RCX);
4831                         amd64_pop_reg (code, AMD64_RSI);
4832                         amd64_pop_reg (code, AMD64_RDI);
4833                         break;
4834                 }
4835                 case OP_GENERIC_CLASS_INIT: {
4836                         static int byte_offset = -1;
4837                         static guint8 bitmask;
4838                         guint8 *jump;
4839
4840                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4841
4842                         if (byte_offset < 0)
4843                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4844
4845                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4846                         jump = code;
4847                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4848
4849                         code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ADDR, "specific_trampoline_generic_class_init", FALSE);
4850                         ins->flags |= MONO_INST_GC_CALLSITE;
4851                         ins->backend.pc_offset = code - cfg->native_code;
4852
4853                         x86_patch (jump, code);
4854                         break;
4855                 }
4856
4857                 case OP_X86_LEA:
4858                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4859                         break;
4860                 case OP_X86_LEA_MEMBASE:
4861                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4862                         break;
4863                 case OP_X86_XCHG:
4864                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4865                         break;
4866                 case OP_LOCALLOC:
4867                         /* keep alignment */
4868                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4869                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4870                         code = mono_emit_stack_alloc (cfg, code, ins);
4871                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4872                         if (cfg->param_area)
4873                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4874                         break;
4875                 case OP_LOCALLOC_IMM: {
4876                         guint32 size = ins->inst_imm;
4877                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4878
4879                         if (ins->flags & MONO_INST_INIT) {
4880                                 if (size < 64) {
4881                                         int i;
4882
4883                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4884                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4885
4886                                         for (i = 0; i < size; i += 8)
4887                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4888                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4889                                 } else {
4890                                         amd64_mov_reg_imm (code, ins->dreg, size);
4891                                         ins->sreg1 = ins->dreg;
4892
4893                                         code = mono_emit_stack_alloc (cfg, code, ins);
4894                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4895                                 }
4896                         } else {
4897                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4898                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4899                         }
4900                         if (cfg->param_area)
4901                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4902                         break;
4903                 }
4904                 case OP_THROW: {
4905                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4906                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4907                                              (gpointer)"mono_arch_throw_exception", FALSE);
4908                         ins->flags |= MONO_INST_GC_CALLSITE;
4909                         ins->backend.pc_offset = code - cfg->native_code;
4910                         break;
4911                 }
4912                 case OP_RETHROW: {
4913                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4914                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4915                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4916                         ins->flags |= MONO_INST_GC_CALLSITE;
4917                         ins->backend.pc_offset = code - cfg->native_code;
4918                         break;
4919                 }
4920                 case OP_CALL_HANDLER:
4921                         /* Align stack */
4922                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4923                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4924                         amd64_call_imm (code, 0);
4925                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4926                         /* Restore stack alignment */
4927                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4928                         break;
4929                 case OP_START_HANDLER: {
4930                         /* Even though we're saving RSP, use sizeof */
4931                         /* gpointer because spvar is of type IntPtr */
4932                         /* see: mono_create_spvar_for_region */
4933                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4934                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4935
4936                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4937                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4938                                 cfg->param_area) {
4939                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4940                         }
4941                         break;
4942                 }
4943                 case OP_ENDFINALLY: {
4944                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4945                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4946                         amd64_ret (code);
4947                         break;
4948                 }
4949                 case OP_ENDFILTER: {
4950                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4951                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4952                         /* The local allocator will put the result into RAX */
4953                         amd64_ret (code);
4954                         break;
4955                 }
4956                 case OP_GET_EX_OBJ:
4957                         if (ins->dreg != AMD64_RAX)
4958                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4959                         break;
4960                 case OP_LABEL:
4961                         ins->inst_c0 = code - cfg->native_code;
4962                         break;
4963                 case OP_BR:
4964                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4965                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4966                         //break;
4967                                 if (ins->inst_target_bb->native_offset) {
4968                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4969                                 } else {
4970                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4971                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4972                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4973                                                 x86_jump8 (code, 0);
4974                                         else
4975                                                 x86_jump32 (code, 0);
4976                         }
4977                         break;
4978                 case OP_BR_REG:
4979                         amd64_jump_reg (code, ins->sreg1);
4980                         break;
4981                 case OP_ICNEQ:
4982                 case OP_ICGE:
4983                 case OP_ICLE:
4984                 case OP_ICGE_UN:
4985                 case OP_ICLE_UN:
4986
4987                 case OP_CEQ:
4988                 case OP_LCEQ:
4989                 case OP_ICEQ:
4990                 case OP_CLT:
4991                 case OP_LCLT:
4992                 case OP_ICLT:
4993                 case OP_CGT:
4994                 case OP_ICGT:
4995                 case OP_LCGT:
4996                 case OP_CLT_UN:
4997                 case OP_LCLT_UN:
4998                 case OP_ICLT_UN:
4999                 case OP_CGT_UN:
5000                 case OP_LCGT_UN:
5001                 case OP_ICGT_UN:
5002                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5003                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5004                         break;
5005                 case OP_COND_EXC_EQ:
5006                 case OP_COND_EXC_NE_UN:
5007                 case OP_COND_EXC_LT:
5008                 case OP_COND_EXC_LT_UN:
5009                 case OP_COND_EXC_GT:
5010                 case OP_COND_EXC_GT_UN:
5011                 case OP_COND_EXC_GE:
5012                 case OP_COND_EXC_GE_UN:
5013                 case OP_COND_EXC_LE:
5014                 case OP_COND_EXC_LE_UN:
5015                 case OP_COND_EXC_IEQ:
5016                 case OP_COND_EXC_INE_UN:
5017                 case OP_COND_EXC_ILT:
5018                 case OP_COND_EXC_ILT_UN:
5019                 case OP_COND_EXC_IGT:
5020                 case OP_COND_EXC_IGT_UN:
5021                 case OP_COND_EXC_IGE:
5022                 case OP_COND_EXC_IGE_UN:
5023                 case OP_COND_EXC_ILE:
5024                 case OP_COND_EXC_ILE_UN:
5025                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5026                         break;
5027                 case OP_COND_EXC_OV:
5028                 case OP_COND_EXC_NO:
5029                 case OP_COND_EXC_C:
5030                 case OP_COND_EXC_NC:
5031                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5032                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5033                         break;
5034                 case OP_COND_EXC_IOV:
5035                 case OP_COND_EXC_INO:
5036                 case OP_COND_EXC_IC:
5037                 case OP_COND_EXC_INC:
5038                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5039                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5040                         break;
5041
5042                 /* floating point opcodes */
5043                 case OP_R8CONST: {
5044                         double d = *(double *)ins->inst_p0;
5045
5046                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5047                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5048                         }
5049                         else {
5050                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5051                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5052                         }
5053                         break;
5054                 }
5055                 case OP_R4CONST: {
5056                         float f = *(float *)ins->inst_p0;
5057
5058                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5059                                 if (cfg->r4fp)
5060                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5061                                 else
5062                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5063                         }
5064                         else {
5065                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5066                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5067                                 if (!cfg->r4fp)
5068                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5069                         }
5070                         break;
5071                 }
5072                 case OP_STORER8_MEMBASE_REG:
5073                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5074                         break;
5075                 case OP_LOADR8_MEMBASE:
5076                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5077                         break;
5078                 case OP_STORER4_MEMBASE_REG:
5079                         if (cfg->r4fp) {
5080                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5081                         } else {
5082                                 /* This requires a double->single conversion */
5083                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5084                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5085                         }
5086                         break;
5087                 case OP_LOADR4_MEMBASE:
5088                         if (cfg->r4fp) {
5089                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5090                         } else {
5091                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5092                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5093                         }
5094                         break;
5095                 case OP_ICONV_TO_R4:
5096                         if (cfg->r4fp) {
5097                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5098                         } else {
5099                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5100                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5101                         }
5102                         break;
5103                 case OP_ICONV_TO_R8:
5104                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5105                         break;
5106                 case OP_LCONV_TO_R4:
5107                         if (cfg->r4fp) {
5108                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5109                         } else {
5110                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5111                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5112                         }
5113                         break;
5114                 case OP_LCONV_TO_R8:
5115                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5116                         break;
5117                 case OP_FCONV_TO_R4:
5118                         if (cfg->r4fp) {
5119                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5120                         } else {
5121                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5122                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5123                         }
5124                         break;
5125                 case OP_FCONV_TO_I1:
5126                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5127                         break;
5128                 case OP_FCONV_TO_U1:
5129                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5130                         break;
5131                 case OP_FCONV_TO_I2:
5132                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5133                         break;
5134                 case OP_FCONV_TO_U2:
5135                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5136                         break;
5137                 case OP_FCONV_TO_U4:
5138                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5139                         break;
5140                 case OP_FCONV_TO_I4:
5141                 case OP_FCONV_TO_I:
5142                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5143                         break;
5144                 case OP_FCONV_TO_I8:
5145                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5146                         break;
5147
5148                 case OP_RCONV_TO_I1:
5149                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5150                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5151                         break;
5152                 case OP_RCONV_TO_U1:
5153                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5154                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5155                         break;
5156                 case OP_RCONV_TO_I2:
5157                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5158                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5159                         break;
5160                 case OP_RCONV_TO_U2:
5161                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5162                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5163                         break;
5164                 case OP_RCONV_TO_I4:
5165                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5166                         break;
5167                 case OP_RCONV_TO_U4:
5168                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5169                         break;
5170                 case OP_RCONV_TO_I8:
5171                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5172                         break;
5173                 case OP_RCONV_TO_R8:
5174                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5175                         break;
5176                 case OP_RCONV_TO_R4:
5177                         if (ins->dreg != ins->sreg1)
5178                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5179                         break;
5180
5181                 case OP_LCONV_TO_R_UN: {
5182                         guint8 *br [2];
5183
5184                         /* Based on gcc code */
5185                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5186                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5187
5188                         /* Positive case */
5189                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5190                         br [1] = code; x86_jump8 (code, 0);
5191                         amd64_patch (br [0], code);
5192
5193                         /* Negative case */
5194                         /* Save to the red zone */
5195                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5196                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5197                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5198                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5199                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5200                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5201                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5202                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5203                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5204                         /* Restore */
5205                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5206                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5207                         amd64_patch (br [1], code);
5208                         break;
5209                 }
5210                 case OP_LCONV_TO_OVF_U4:
5211                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5212                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5213                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5214                         break;
5215                 case OP_LCONV_TO_OVF_I4_UN:
5216                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5217                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5218                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5219                         break;
5220                 case OP_FMOVE:
5221                         if (ins->dreg != ins->sreg1)
5222                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5223                         break;
5224                 case OP_RMOVE:
5225                         if (ins->dreg != ins->sreg1)
5226                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5227                         break;
5228                 case OP_MOVE_F_TO_I4:
5229                         if (cfg->r4fp) {
5230                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5231                         } else {
5232                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5233                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5234                         }
5235                         break;
5236                 case OP_MOVE_I4_TO_F:
5237                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5238                         if (!cfg->r4fp)
5239                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5240                         break;
5241                 case OP_MOVE_F_TO_I8:
5242                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5243                         break;
5244                 case OP_MOVE_I8_TO_F:
5245                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5246                         break;
5247                 case OP_FADD:
5248                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5249                         break;
5250                 case OP_FSUB:
5251                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5252                         break;
5253                 case OP_FMUL:
5254                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5255                         break;
5256                 case OP_FDIV:
5257                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5258                         break;
5259                 case OP_FNEG: {
5260                         static double r8_0 = -0.0;
5261
5262                         g_assert (ins->sreg1 == ins->dreg);
5263
5264                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5265                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5266                         break;
5267                 }
5268                 case OP_SIN:
5269                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5270                         break;
5271                 case OP_COS:
5272                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5273                         break;
5274                 case OP_ABS: {
5275                         static guint64 d = 0x7fffffffffffffffUL;
5276
5277                         g_assert (ins->sreg1 == ins->dreg);
5278
5279                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5280                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5281                         break;
5282                 }
5283                 case OP_SQRT:
5284                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5285                         break;
5286
5287                 case OP_RADD:
5288                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5289                         break;
5290                 case OP_RSUB:
5291                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5292                         break;
5293                 case OP_RMUL:
5294                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5295                         break;
5296                 case OP_RDIV:
5297                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5298                         break;
5299                 case OP_RNEG: {
5300                         static float r4_0 = -0.0;
5301
5302                         g_assert (ins->sreg1 == ins->dreg);
5303
5304                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5305                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5306                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5307                         break;
5308                 }
5309
5310                 case OP_IMIN:
5311                         g_assert (cfg->opt & MONO_OPT_CMOV);
5312                         g_assert (ins->dreg == ins->sreg1);
5313                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5314                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5315                         break;
5316                 case OP_IMIN_UN:
5317                         g_assert (cfg->opt & MONO_OPT_CMOV);
5318                         g_assert (ins->dreg == ins->sreg1);
5319                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5320                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5321                         break;
5322                 case OP_IMAX:
5323                         g_assert (cfg->opt & MONO_OPT_CMOV);
5324                         g_assert (ins->dreg == ins->sreg1);
5325                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5326                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5327                         break;
5328                 case OP_IMAX_UN:
5329                         g_assert (cfg->opt & MONO_OPT_CMOV);
5330                         g_assert (ins->dreg == ins->sreg1);
5331                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5332                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5333                         break;
5334                 case OP_LMIN:
5335                         g_assert (cfg->opt & MONO_OPT_CMOV);
5336                         g_assert (ins->dreg == ins->sreg1);
5337                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5338                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5339                         break;
5340                 case OP_LMIN_UN:
5341                         g_assert (cfg->opt & MONO_OPT_CMOV);
5342                         g_assert (ins->dreg == ins->sreg1);
5343                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5344                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5345                         break;
5346                 case OP_LMAX:
5347                         g_assert (cfg->opt & MONO_OPT_CMOV);
5348                         g_assert (ins->dreg == ins->sreg1);
5349                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5350                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5351                         break;
5352                 case OP_LMAX_UN:
5353                         g_assert (cfg->opt & MONO_OPT_CMOV);
5354                         g_assert (ins->dreg == ins->sreg1);
5355                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5356                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5357                         break;
5358                 case OP_X86_FPOP:
5359                         break;
5360                 case OP_FCOMPARE:
5361                         /*
5362                          * The two arguments are swapped because the fbranch instructions
5363                          * depend on this for the non-sse case to work.
5364                          */
5365                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5366                         break;
5367                 case OP_RCOMPARE:
5368                         /*
5369                          * FIXME: Get rid of this.
5370                          * The two arguments are swapped because the fbranch instructions
5371                          * depend on this for the non-sse case to work.
5372                          */
5373                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5374                         break;
5375                 case OP_FCNEQ:
5376                 case OP_FCEQ: {
5377                         /* zeroing the register at the start results in
5378                          * shorter and faster code (we can also remove the widening op)
5379                          */
5380                         guchar *unordered_check;
5381
5382                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5383                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5384                         unordered_check = code;
5385                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5386
5387                         if (ins->opcode == OP_FCEQ) {
5388                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5389                                 amd64_patch (unordered_check, code);
5390                         } else {
5391                                 guchar *jump_to_end;
5392                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5393                                 jump_to_end = code;
5394                                 x86_jump8 (code, 0);
5395                                 amd64_patch (unordered_check, code);
5396                                 amd64_inc_reg (code, ins->dreg);
5397                                 amd64_patch (jump_to_end, code);
5398                         }
5399                         break;
5400                 }
5401                 case OP_FCLT:
5402                 case OP_FCLT_UN: {
5403                         /* zeroing the register at the start results in
5404                          * shorter and faster code (we can also remove the widening op)
5405                          */
5406                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5407                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5408                         if (ins->opcode == OP_FCLT_UN) {
5409                                 guchar *unordered_check = code;
5410                                 guchar *jump_to_end;
5411                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5412                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5413                                 jump_to_end = code;
5414                                 x86_jump8 (code, 0);
5415                                 amd64_patch (unordered_check, code);
5416                                 amd64_inc_reg (code, ins->dreg);
5417                                 amd64_patch (jump_to_end, code);
5418                         } else {
5419                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5420                         }
5421                         break;
5422                 }
5423                 case OP_FCLE: {
5424                         guchar *unordered_check;
5425                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5426                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5427                         unordered_check = code;
5428                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5429                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5430                         amd64_patch (unordered_check, code);
5431                         break;
5432                 }
5433                 case OP_FCGT:
5434                 case OP_FCGT_UN: {
5435                         /* zeroing the register at the start results in
5436                          * shorter and faster code (we can also remove the widening op)
5437                          */
5438                         guchar *unordered_check;
5439
5440                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5441                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5442                         if (ins->opcode == OP_FCGT) {
5443                                 unordered_check = code;
5444                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5445                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5446                                 amd64_patch (unordered_check, code);
5447                         } else {
5448                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5449                         }
5450                         break;
5451                 }
5452                 case OP_FCGE: {
5453                         guchar *unordered_check;
5454                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5455                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5456                         unordered_check = code;
5457                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5458                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5459                         amd64_patch (unordered_check, code);
5460                         break;
5461                 }
5462
5463                 case OP_RCEQ:
5464                 case OP_RCGT:
5465                 case OP_RCLT:
5466                 case OP_RCLT_UN:
5467                 case OP_RCGT_UN: {
5468                         int x86_cond;
5469                         gboolean unordered = FALSE;
5470
5471                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5472                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5473
5474                         switch (ins->opcode) {
5475                         case OP_RCEQ:
5476                                 x86_cond = X86_CC_EQ;
5477                                 break;
5478                         case OP_RCGT:
5479                                 x86_cond = X86_CC_LT;
5480                                 break;
5481                         case OP_RCLT:
5482                                 x86_cond = X86_CC_GT;
5483                                 break;
5484                         case OP_RCLT_UN:
5485                                 x86_cond = X86_CC_GT;
5486                                 unordered = TRUE;
5487                                 break;
5488                         case OP_RCGT_UN:
5489                                 x86_cond = X86_CC_LT;
5490                                 unordered = TRUE;
5491                                 break;
5492                         default:
5493                                 g_assert_not_reached ();
5494                                 break;
5495                         }
5496
5497                         if (unordered) {
5498                                 guchar *unordered_check;
5499                                 guchar *jump_to_end;
5500
5501                                 unordered_check = code;
5502                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5503                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5504                                 jump_to_end = code;
5505                                 x86_jump8 (code, 0);
5506                                 amd64_patch (unordered_check, code);
5507                                 amd64_inc_reg (code, ins->dreg);
5508                                 amd64_patch (jump_to_end, code);
5509                         } else {
5510                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5511                         }
5512                         break;
5513                 }
5514                 case OP_FCLT_MEMBASE:
5515                 case OP_FCGT_MEMBASE:
5516                 case OP_FCLT_UN_MEMBASE:
5517                 case OP_FCGT_UN_MEMBASE:
5518                 case OP_FCEQ_MEMBASE: {
5519                         guchar *unordered_check, *jump_to_end;
5520                         int x86_cond;
5521
5522                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5523                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5524
5525                         switch (ins->opcode) {
5526                         case OP_FCEQ_MEMBASE:
5527                                 x86_cond = X86_CC_EQ;
5528                                 break;
5529                         case OP_FCLT_MEMBASE:
5530                         case OP_FCLT_UN_MEMBASE:
5531                                 x86_cond = X86_CC_LT;
5532                                 break;
5533                         case OP_FCGT_MEMBASE:
5534                         case OP_FCGT_UN_MEMBASE:
5535                                 x86_cond = X86_CC_GT;
5536                                 break;
5537                         default:
5538                                 g_assert_not_reached ();
5539                         }
5540
5541                         unordered_check = code;
5542                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5543                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5544
5545                         switch (ins->opcode) {
5546                         case OP_FCEQ_MEMBASE:
5547                         case OP_FCLT_MEMBASE:
5548                         case OP_FCGT_MEMBASE:
5549                                 amd64_patch (unordered_check, code);
5550                                 break;
5551                         case OP_FCLT_UN_MEMBASE:
5552                         case OP_FCGT_UN_MEMBASE:
5553                                 jump_to_end = code;
5554                                 x86_jump8 (code, 0);
5555                                 amd64_patch (unordered_check, code);
5556                                 amd64_inc_reg (code, ins->dreg);
5557                                 amd64_patch (jump_to_end, code);
5558                                 break;
5559                         default:
5560                                 break;
5561                         }
5562                         break;
5563                 }
5564                 case OP_FBEQ: {
5565                         guchar *jump = code;
5566                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5567                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5568                         amd64_patch (jump, code);
5569                         break;
5570                 }
5571                 case OP_FBNE_UN:
5572                         /* Branch if C013 != 100 */
5573                         /* branch if !ZF or (PF|CF) */
5574                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5575                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5576                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5577                         break;
5578                 case OP_FBLT:
5579                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5580                         break;
5581                 case OP_FBLT_UN:
5582                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5583                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5584                         break;
5585                 case OP_FBGT:
5586                 case OP_FBGT_UN:
5587                         if (ins->opcode == OP_FBGT) {
5588                                 guchar *br1;
5589
5590                                 /* skip branch if C1=1 */
5591                                 br1 = code;
5592                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5593                                 /* branch if (C0 | C3) = 1 */
5594                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5595                                 amd64_patch (br1, code);
5596                                 break;
5597                         } else {
5598                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5599                         }
5600                         break;
5601                 case OP_FBGE: {
5602                         /* Branch if C013 == 100 or 001 */
5603                         guchar *br1;
5604
5605                         /* skip branch if C1=1 */
5606                         br1 = code;
5607                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5608                         /* branch if (C0 | C3) = 1 */
5609                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5610                         amd64_patch (br1, code);
5611                         break;
5612                 }
5613                 case OP_FBGE_UN:
5614                         /* Branch if C013 == 000 */
5615                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5616                         break;
5617                 case OP_FBLE: {
5618                         /* Branch if C013=000 or 100 */
5619                         guchar *br1;
5620
5621                         /* skip branch if C1=1 */
5622                         br1 = code;
5623                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5624                         /* branch if C0=0 */
5625                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5626                         amd64_patch (br1, code);
5627                         break;
5628                 }
5629                 case OP_FBLE_UN:
5630                         /* Branch if C013 != 001 */
5631                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5632                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5633                         break;
5634                 case OP_CKFINITE:
5635                         /* Transfer value to the fp stack */
5636                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5637                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5638                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5639
5640                         amd64_push_reg (code, AMD64_RAX);
5641                         amd64_fxam (code);
5642                         amd64_fnstsw (code);
5643                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5644                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5645                         amd64_pop_reg (code, AMD64_RAX);
5646                         amd64_fstp (code, 0);
5647                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5648                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5649                         break;
5650                 case OP_TLS_GET: {
5651                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5652                         break;
5653                 }
5654                 case OP_TLS_GET_REG:
5655                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5656                         break;
5657                 case OP_TLS_SET: {
5658                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5659                         break;
5660                 }
5661                 case OP_TLS_SET_REG: {
5662                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5663                         break;
5664                 }
5665                 case OP_MEMORY_BARRIER: {
5666                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5667                                 x86_mfence (code);
5668                         break;
5669                 }
5670                 case OP_ATOMIC_ADD_I4:
5671                 case OP_ATOMIC_ADD_I8: {
5672                         int dreg = ins->dreg;
5673                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5674
5675                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5676                                 dreg = AMD64_R11;
5677
5678                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5679                         amd64_prefix (code, X86_LOCK_PREFIX);
5680                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5681                         /* dreg contains the old value, add with sreg2 value */
5682                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5683
5684                         if (ins->dreg != dreg)
5685                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5686
5687                         break;
5688                 }
5689                 case OP_ATOMIC_EXCHANGE_I4:
5690                 case OP_ATOMIC_EXCHANGE_I8: {
5691                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5692
5693                         /* LOCK prefix is implied. */
5694                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5695                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5696                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5697                         break;
5698                 }
5699                 case OP_ATOMIC_CAS_I4:
5700                 case OP_ATOMIC_CAS_I8: {
5701                         guint32 size;
5702
5703                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5704                                 size = 8;
5705                         else
5706                                 size = 4;
5707
5708                         /*
5709                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5710                          * an explanation of how this works.
5711                          */
5712                         g_assert (ins->sreg3 == AMD64_RAX);
5713                         g_assert (ins->sreg1 != AMD64_RAX);
5714                         g_assert (ins->sreg1 != ins->sreg2);
5715
5716                         amd64_prefix (code, X86_LOCK_PREFIX);
5717                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5718
5719                         if (ins->dreg != AMD64_RAX)
5720                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5721                         break;
5722                 }
5723                 case OP_ATOMIC_LOAD_I1: {
5724                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5725                         break;
5726                 }
5727                 case OP_ATOMIC_LOAD_U1: {
5728                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5729                         break;
5730                 }
5731                 case OP_ATOMIC_LOAD_I2: {
5732                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5733                         break;
5734                 }
5735                 case OP_ATOMIC_LOAD_U2: {
5736                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5737                         break;
5738                 }
5739                 case OP_ATOMIC_LOAD_I4: {
5740                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5741                         break;
5742                 }
5743                 case OP_ATOMIC_LOAD_U4:
5744                 case OP_ATOMIC_LOAD_I8:
5745                 case OP_ATOMIC_LOAD_U8: {
5746                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5747                         break;
5748                 }
5749                 case OP_ATOMIC_LOAD_R4: {
5750                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5751                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5752                         break;
5753                 }
5754                 case OP_ATOMIC_LOAD_R8: {
5755                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5756                         break;
5757                 }
5758                 case OP_ATOMIC_STORE_I1:
5759                 case OP_ATOMIC_STORE_U1:
5760                 case OP_ATOMIC_STORE_I2:
5761                 case OP_ATOMIC_STORE_U2:
5762                 case OP_ATOMIC_STORE_I4:
5763                 case OP_ATOMIC_STORE_U4:
5764                 case OP_ATOMIC_STORE_I8:
5765                 case OP_ATOMIC_STORE_U8: {
5766                         int size;
5767
5768                         switch (ins->opcode) {
5769                         case OP_ATOMIC_STORE_I1:
5770                         case OP_ATOMIC_STORE_U1:
5771                                 size = 1;
5772                                 break;
5773                         case OP_ATOMIC_STORE_I2:
5774                         case OP_ATOMIC_STORE_U2:
5775                                 size = 2;
5776                                 break;
5777                         case OP_ATOMIC_STORE_I4:
5778                         case OP_ATOMIC_STORE_U4:
5779                                 size = 4;
5780                                 break;
5781                         case OP_ATOMIC_STORE_I8:
5782                         case OP_ATOMIC_STORE_U8:
5783                                 size = 8;
5784                                 break;
5785                         }
5786
5787                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5788
5789                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5790                                 x86_mfence (code);
5791                         break;
5792                 }
5793                 case OP_ATOMIC_STORE_R4: {
5794                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5795                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5796
5797                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5798                                 x86_mfence (code);
5799                         break;
5800                 }
5801                 case OP_ATOMIC_STORE_R8: {
5802                         x86_nop (code);
5803                         x86_nop (code);
5804                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5805                         x86_nop (code);
5806                         x86_nop (code);
5807
5808                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5809                                 x86_mfence (code);
5810                         break;
5811                 }
5812                 case OP_CARD_TABLE_WBARRIER: {
5813                         int ptr = ins->sreg1;
5814                         int value = ins->sreg2;
5815                         guchar *br = 0;
5816                         int nursery_shift, card_table_shift;
5817                         gpointer card_table_mask;
5818                         size_t nursery_size;
5819
5820                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5821                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5822                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5823
5824                         /*If either point to the stack we can simply avoid the WB. This happens due to
5825                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5826                          */
5827                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5828                                 continue;
5829
5830                         /*
5831                          * We need one register we can clobber, we choose EDX and make sreg1
5832                          * fixed EAX to work around limitations in the local register allocator.
5833                          * sreg2 might get allocated to EDX, but that is not a problem since
5834                          * we use it before clobbering EDX.
5835                          */
5836                         g_assert (ins->sreg1 == AMD64_RAX);
5837
5838                         /*
5839                          * This is the code we produce:
5840                          *
5841                          *   edx = value
5842                          *   edx >>= nursery_shift
5843                          *   cmp edx, (nursery_start >> nursery_shift)
5844                          *   jne done
5845                          *   edx = ptr
5846                          *   edx >>= card_table_shift
5847                          *   edx += cardtable
5848                          *   [edx] = 1
5849                          * done:
5850                          */
5851
5852                         if (mono_gc_card_table_nursery_check ()) {
5853                                 if (value != AMD64_RDX)
5854                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5855                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5856                                 if (shifted_nursery_start >> 31) {
5857                                         /*
5858                                          * The value we need to compare against is 64 bits, so we need
5859                                          * another spare register.  We use RBX, which we save and
5860                                          * restore.
5861                                          */
5862                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5863                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5864                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5865                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5866                                 } else {
5867                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5868                                 }
5869                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5870                         }
5871                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5872                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5873                         if (card_table_mask)
5874                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5875
5876                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5877                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5878
5879                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5880
5881                         if (mono_gc_card_table_nursery_check ())
5882                                 x86_patch (br, code);
5883                         break;
5884                 }
5885 #ifdef MONO_ARCH_SIMD_INTRINSICS
5886                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5887                 case OP_ADDPS:
5888                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5889                         break;
5890                 case OP_DIVPS:
5891                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5892                         break;
5893                 case OP_MULPS:
5894                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5895                         break;
5896                 case OP_SUBPS:
5897                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5898                         break;
5899                 case OP_MAXPS:
5900                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5901                         break;
5902                 case OP_MINPS:
5903                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5904                         break;
5905                 case OP_COMPPS:
5906                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5907                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5908                         break;
5909                 case OP_ANDPS:
5910                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5911                         break;
5912                 case OP_ANDNPS:
5913                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5914                         break;
5915                 case OP_ORPS:
5916                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5917                         break;
5918                 case OP_XORPS:
5919                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5920                         break;
5921                 case OP_SQRTPS:
5922                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5923                         break;
5924                 case OP_RSQRTPS:
5925                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5926                         break;
5927                 case OP_RCPPS:
5928                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5929                         break;
5930                 case OP_ADDSUBPS:
5931                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5932                         break;
5933                 case OP_HADDPS:
5934                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5935                         break;
5936                 case OP_HSUBPS:
5937                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5938                         break;
5939                 case OP_DUPPS_HIGH:
5940                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5941                         break;
5942                 case OP_DUPPS_LOW:
5943                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5944                         break;
5945
5946                 case OP_PSHUFLEW_HIGH:
5947                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5948                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5949                         break;
5950                 case OP_PSHUFLEW_LOW:
5951                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5952                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5953                         break;
5954                 case OP_PSHUFLED:
5955                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5956                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5957                         break;
5958                 case OP_SHUFPS:
5959                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5960                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5961                         break;
5962                 case OP_SHUFPD:
5963                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5964                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5965                         break;
5966
5967                 case OP_ADDPD:
5968                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5969                         break;
5970                 case OP_DIVPD:
5971                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5972                         break;
5973                 case OP_MULPD:
5974                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5975                         break;
5976                 case OP_SUBPD:
5977                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5978                         break;
5979                 case OP_MAXPD:
5980                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5981                         break;
5982                 case OP_MINPD:
5983                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985                 case OP_COMPPD:
5986                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5987                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5988                         break;
5989                 case OP_ANDPD:
5990                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5991                         break;
5992                 case OP_ANDNPD:
5993                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995                 case OP_ORPD:
5996                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5997                         break;
5998                 case OP_XORPD:
5999                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6000                         break;
6001                 case OP_SQRTPD:
6002                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6003                         break;
6004                 case OP_ADDSUBPD:
6005                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6006                         break;
6007                 case OP_HADDPD:
6008                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6009                         break;
6010                 case OP_HSUBPD:
6011                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6012                         break;
6013                 case OP_DUPPD:
6014                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6015                         break;
6016
6017                 case OP_EXTRACT_MASK:
6018                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6019                         break;
6020
6021                 case OP_PAND:
6022                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6023                         break;
6024                 case OP_POR:
6025                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6026                         break;
6027                 case OP_PXOR:
6028                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6029                         break;
6030
6031                 case OP_PADDB:
6032                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034                 case OP_PADDW:
6035                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_PADDD:
6038                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040                 case OP_PADDQ:
6041                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6042                         break;
6043
6044                 case OP_PSUBB:
6045                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047                 case OP_PSUBW:
6048                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6049                         break;
6050                 case OP_PSUBD:
6051                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6052                         break;
6053                 case OP_PSUBQ:
6054                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6055                         break;
6056
6057                 case OP_PMAXB_UN:
6058                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060                 case OP_PMAXW_UN:
6061                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6062                         break;
6063                 case OP_PMAXD_UN:
6064                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6065                         break;
6066
6067                 case OP_PMAXB:
6068                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070                 case OP_PMAXW:
6071                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073                 case OP_PMAXD:
6074                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076
6077                 case OP_PAVGB_UN:
6078                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080                 case OP_PAVGW_UN:
6081                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6082                         break;
6083
6084                 case OP_PMINB_UN:
6085                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6086                         break;
6087                 case OP_PMINW_UN:
6088                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6089                         break;
6090                 case OP_PMIND_UN:
6091                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093
6094                 case OP_PMINB:
6095                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6096                         break;
6097                 case OP_PMINW:
6098                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6099                         break;
6100                 case OP_PMIND:
6101                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6102                         break;
6103
6104                 case OP_PCMPEQB:
6105                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6106                         break;
6107                 case OP_PCMPEQW:
6108                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6109                         break;
6110                 case OP_PCMPEQD:
6111                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6112                         break;
6113                 case OP_PCMPEQQ:
6114                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6115                         break;
6116
6117                 case OP_PCMPGTB:
6118                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6119                         break;
6120                 case OP_PCMPGTW:
6121                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6122                         break;
6123                 case OP_PCMPGTD:
6124                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6125                         break;
6126                 case OP_PCMPGTQ:
6127                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6128                         break;
6129
6130                 case OP_PSUM_ABS_DIFF:
6131                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6132                         break;
6133
6134                 case OP_UNPACK_LOWB:
6135                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6136                         break;
6137                 case OP_UNPACK_LOWW:
6138                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6139                         break;
6140                 case OP_UNPACK_LOWD:
6141                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6142                         break;
6143                 case OP_UNPACK_LOWQ:
6144                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6145                         break;
6146                 case OP_UNPACK_LOWPS:
6147                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6148                         break;
6149                 case OP_UNPACK_LOWPD:
6150                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6151                         break;
6152
6153                 case OP_UNPACK_HIGHB:
6154                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6155                         break;
6156                 case OP_UNPACK_HIGHW:
6157                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6158                         break;
6159                 case OP_UNPACK_HIGHD:
6160                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6161                         break;
6162                 case OP_UNPACK_HIGHQ:
6163                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6164                         break;
6165                 case OP_UNPACK_HIGHPS:
6166                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6167                         break;
6168                 case OP_UNPACK_HIGHPD:
6169                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6170                         break;
6171
6172                 case OP_PACKW:
6173                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6174                         break;
6175                 case OP_PACKD:
6176                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6177                         break;
6178                 case OP_PACKW_UN:
6179                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6180                         break;
6181                 case OP_PACKD_UN:
6182                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6183                         break;
6184
6185                 case OP_PADDB_SAT_UN:
6186                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6187                         break;
6188                 case OP_PSUBB_SAT_UN:
6189                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6190                         break;
6191                 case OP_PADDW_SAT_UN:
6192                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6193                         break;
6194                 case OP_PSUBW_SAT_UN:
6195                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6196                         break;
6197
6198                 case OP_PADDB_SAT:
6199                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6200                         break;
6201                 case OP_PSUBB_SAT:
6202                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6203                         break;
6204                 case OP_PADDW_SAT:
6205                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6206                         break;
6207                 case OP_PSUBW_SAT:
6208                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6209                         break;
6210
6211                 case OP_PMULW:
6212                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6213                         break;
6214                 case OP_PMULD:
6215                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6216                         break;
6217                 case OP_PMULQ:
6218                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6219                         break;
6220                 case OP_PMULW_HIGH_UN:
6221                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6222                         break;
6223                 case OP_PMULW_HIGH:
6224                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6225                         break;
6226
6227                 case OP_PSHRW:
6228                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6229                         break;
6230                 case OP_PSHRW_REG:
6231                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6232                         break;
6233
6234                 case OP_PSARW:
6235                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6236                         break;
6237                 case OP_PSARW_REG:
6238                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6239                         break;
6240
6241                 case OP_PSHLW:
6242                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6243                         break;
6244                 case OP_PSHLW_REG:
6245                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6246                         break;
6247
6248                 case OP_PSHRD:
6249                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6250                         break;
6251                 case OP_PSHRD_REG:
6252                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6253                         break;
6254
6255                 case OP_PSARD:
6256                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6257                         break;
6258                 case OP_PSARD_REG:
6259                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6260                         break;
6261
6262                 case OP_PSHLD:
6263                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6264                         break;
6265                 case OP_PSHLD_REG:
6266                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6267                         break;
6268
6269                 case OP_PSHRQ:
6270                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6271                         break;
6272                 case OP_PSHRQ_REG:
6273                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6274                         break;
6275
6276                 /*TODO: This is appart of the sse spec but not added
6277                 case OP_PSARQ:
6278                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6279                         break;
6280                 case OP_PSARQ_REG:
6281                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6282                         break;
6283                 */
6284
6285                 case OP_PSHLQ:
6286                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6287                         break;
6288                 case OP_PSHLQ_REG:
6289                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6290                         break;
6291                 case OP_CVTDQ2PD:
6292                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6293                         break;
6294                 case OP_CVTDQ2PS:
6295                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6296                         break;
6297                 case OP_CVTPD2DQ:
6298                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6299                         break;
6300                 case OP_CVTPD2PS:
6301                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6302                         break;
6303                 case OP_CVTPS2DQ:
6304                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6305                         break;
6306                 case OP_CVTPS2PD:
6307                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6308                         break;
6309                 case OP_CVTTPD2DQ:
6310                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6311                         break;
6312                 case OP_CVTTPS2DQ:
6313                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6314                         break;
6315
6316                 case OP_ICONV_TO_X:
6317                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6318                         break;
6319                 case OP_EXTRACT_I4:
6320                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6321                         break;
6322                 case OP_EXTRACT_I8:
6323                         if (ins->inst_c0) {
6324                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6325                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6326                         } else {
6327                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6328                         }
6329                         break;
6330                 case OP_EXTRACT_I1:
6331                 case OP_EXTRACT_U1:
6332                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6333                         if (ins->inst_c0)
6334                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6335                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6336                         break;
6337                 case OP_EXTRACT_I2:
6338                 case OP_EXTRACT_U2:
6339                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6340                         if (ins->inst_c0)
6341                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6342                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6343                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6344                         break;
6345                 case OP_EXTRACT_R8:
6346                         if (ins->inst_c0)
6347                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6348                         else
6349                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6350                         break;
6351                 case OP_INSERT_I2:
6352                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6353                         break;
6354                 case OP_EXTRACTX_U2:
6355                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6356                         break;
6357                 case OP_INSERTX_U1_SLOW:
6358                         /*sreg1 is the extracted ireg (scratch)
6359                         /sreg2 is the to be inserted ireg (scratch)
6360                         /dreg is the xreg to receive the value*/
6361
6362                         /*clear the bits from the extracted word*/
6363                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6364                         /*shift the value to insert if needed*/
6365                         if (ins->inst_c0 & 1)
6366                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6367                         /*join them together*/
6368                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6369                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6370                         break;
6371                 case OP_INSERTX_I4_SLOW:
6372                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6373                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6374                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6375                         break;
6376                 case OP_INSERTX_I8_SLOW:
6377                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6378                         if (ins->inst_c0)
6379                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6380                         else
6381                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6382                         break;
6383
6384                 case OP_INSERTX_R4_SLOW:
6385                         switch (ins->inst_c0) {
6386                         case 0:
6387                                 if (cfg->r4fp)
6388                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6389                                 else
6390                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6391                                 break;
6392                         case 1:
6393                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6394                                 if (cfg->r4fp)
6395                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6396                                 else
6397                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6398                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6399                                 break;
6400                         case 2:
6401                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6402                                 if (cfg->r4fp)
6403                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6404                                 else
6405                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6406                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6407                                 break;
6408                         case 3:
6409                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6410                                 if (cfg->r4fp)
6411                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6412                                 else
6413                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6414                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6415                                 break;
6416                         }
6417                         break;
6418                 case OP_INSERTX_R8_SLOW:
6419                         if (ins->inst_c0)
6420                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6421                         else
6422                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6423                         break;
6424                 case OP_STOREX_MEMBASE_REG:
6425                 case OP_STOREX_MEMBASE:
6426                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6427                         break;
6428                 case OP_LOADX_MEMBASE:
6429                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6430                         break;
6431                 case OP_LOADX_ALIGNED_MEMBASE:
6432                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6433                         break;
6434                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6435                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6436                         break;
6437                 case OP_STOREX_NTA_MEMBASE_REG:
6438                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6439                         break;
6440                 case OP_PREFETCH_MEMBASE:
6441                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6442                         break;
6443
6444                 case OP_XMOVE:
6445                         /*FIXME the peephole pass should have killed this*/
6446                         if (ins->dreg != ins->sreg1)
6447                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6448                         break;
6449                 case OP_XZERO:
6450                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6451                         break;
6452                 case OP_ICONV_TO_R4_RAW:
6453                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6454                         break;
6455
6456                 case OP_FCONV_TO_R8_X:
6457                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6458                         break;
6459
6460                 case OP_XCONV_R8_TO_I4:
6461                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6462                         switch (ins->backend.source_opcode) {
6463                         case OP_FCONV_TO_I1:
6464                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6465                                 break;
6466                         case OP_FCONV_TO_U1:
6467                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6468                                 break;
6469                         case OP_FCONV_TO_I2:
6470                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6471                                 break;
6472                         case OP_FCONV_TO_U2:
6473                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6474                                 break;
6475                         }
6476                         break;
6477
6478                 case OP_EXPAND_I2:
6479                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6480                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6481                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6482                         break;
6483                 case OP_EXPAND_I4:
6484                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6485                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6486                         break;
6487                 case OP_EXPAND_I8:
6488                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6489                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6490                         break;
6491                 case OP_EXPAND_R4:
6492                         if (cfg->r4fp) {
6493                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6494                         } else {
6495                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6496                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6497                         }
6498                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6499                         break;
6500                 case OP_EXPAND_R8:
6501                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6502                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6503                         break;
6504 #endif
6505                 case OP_LIVERANGE_START: {
6506                         if (cfg->verbose_level > 1)
6507                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6508                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6509                         break;
6510                 }
6511                 case OP_LIVERANGE_END: {
6512                         if (cfg->verbose_level > 1)
6513                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6514                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6515                         break;
6516                 }
6517                 case OP_GC_SAFE_POINT: {
6518                         const char *polling_func = NULL;
6519                         int compare_val = 0;
6520                         guint8 *br [1];
6521
6522 #if defined (USE_COOP_GC)
6523                         polling_func = "mono_threads_state_poll";
6524                         compare_val = 1;
6525 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
6526                         polling_func = "mono_nacl_gc";
6527                         compare_val = 0xFFFFFFFF;
6528 #endif
6529                         if (!polling_func)
6530                                 break;
6531
6532                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6533                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6534                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6535                         amd64_patch (br[0], code);
6536                         break;
6537                 }
6538
6539                 case OP_GC_LIVENESS_DEF:
6540                 case OP_GC_LIVENESS_USE:
6541                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6542                         ins->backend.pc_offset = code - cfg->native_code;
6543                         break;
6544                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6545                         ins->backend.pc_offset = code - cfg->native_code;
6546                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6547                         break;
6548                 default:
6549                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6550                         g_assert_not_reached ();
6551                 }
6552
6553                 if ((code - cfg->native_code - offset) > max_len) {
6554 #if !defined(__native_client_codegen__)
6555                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6556                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6557                         g_assert_not_reached ();
6558 #endif
6559                 }
6560         }
6561
6562         cfg->code_len = code - cfg->native_code;
6563 }
6564
6565 #endif /* DISABLE_JIT */
6566
6567 void
6568 mono_arch_register_lowlevel_calls (void)
6569 {
6570         /* The signature doesn't matter */
6571         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6572 }
6573
6574 void
6575 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6576 {
6577         unsigned char *ip = ji->ip.i + code;
6578
6579         /*
6580          * Debug code to help track down problems where the target of a near call is
6581          * is not valid.
6582          */
6583         if (amd64_is_near_call (ip)) {
6584                 gint64 disp = (guint8*)target - (guint8*)ip;
6585
6586                 if (!amd64_is_imm32 (disp)) {
6587                         printf ("TYPE: %d\n", ji->type);
6588                         switch (ji->type) {
6589                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6590                                 printf ("V: %s\n", ji->data.name);
6591                                 break;
6592                         case MONO_PATCH_INFO_METHOD_JUMP:
6593                         case MONO_PATCH_INFO_METHOD:
6594                                 printf ("V: %s\n", ji->data.method->name);
6595                                 break;
6596                         default:
6597                                 break;
6598                         }
6599                 }
6600         }
6601
6602         amd64_patch (ip, (gpointer)target);
6603 }
6604
6605 #ifndef DISABLE_JIT
6606
6607 static int
6608 get_max_epilog_size (MonoCompile *cfg)
6609 {
6610         int max_epilog_size = 16;
6611
6612         if (cfg->method->save_lmf)
6613                 max_epilog_size += 256;
6614
6615         if (mono_jit_trace_calls != NULL)
6616                 max_epilog_size += 50;
6617
6618         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6619                 max_epilog_size += 50;
6620
6621         max_epilog_size += (AMD64_NREG * 2);
6622
6623         return max_epilog_size;
6624 }
6625
6626 /*
6627  * This macro is used for testing whenever the unwinder works correctly at every point
6628  * where an async exception can happen.
6629  */
6630 /* This will generate a SIGSEGV at the given point in the code */
6631 #define async_exc_point(code) do { \
6632     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6633          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6634              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6635          cfg->arch.async_point_count ++; \
6636     } \
6637 } while (0)
6638
6639 guint8 *
6640 mono_arch_emit_prolog (MonoCompile *cfg)
6641 {
6642         MonoMethod *method = cfg->method;
6643         MonoBasicBlock *bb;
6644         MonoMethodSignature *sig;
6645         MonoInst *ins;
6646         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6647         guint8 *code;
6648         CallInfo *cinfo;
6649         MonoInst *lmf_var = cfg->lmf_var;
6650         gboolean args_clobbered = FALSE;
6651         gboolean trace = FALSE;
6652 #ifdef __native_client_codegen__
6653         guint alignment_check;
6654 #endif
6655
6656         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6657
6658 #if defined(__default_codegen__)
6659         code = cfg->native_code = g_malloc (cfg->code_size);
6660 #elif defined(__native_client_codegen__)
6661         /* native_code_alloc is not 32-byte aligned, native_code is. */
6662         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6663
6664         /* Align native_code to next nearest kNaclAlignment byte. */
6665         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6666         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6667
6668         code = cfg->native_code;
6669
6670         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6671         g_assert (alignment_check == 0);
6672 #endif
6673
6674         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6675                 trace = TRUE;
6676
6677         /* Amount of stack space allocated by register saving code */
6678         pos = 0;
6679
6680         /* Offset between RSP and the CFA */
6681         cfa_offset = 0;
6682
6683         /*
6684          * The prolog consists of the following parts:
6685          * FP present:
6686          * - push rbp, mov rbp, rsp
6687          * - save callee saved regs using pushes
6688          * - allocate frame
6689          * - save rgctx if needed
6690          * - save lmf if needed
6691          * FP not present:
6692          * - allocate frame
6693          * - save rgctx if needed
6694          * - save lmf if needed
6695          * - save callee saved regs using moves
6696          */
6697
6698         // CFA = sp + 8
6699         cfa_offset = 8;
6700         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6701         // IP saved at CFA - 8
6702         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6703         async_exc_point (code);
6704         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6705
6706         if (!cfg->arch.omit_fp) {
6707                 amd64_push_reg (code, AMD64_RBP);
6708                 cfa_offset += 8;
6709                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6710                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6711                 async_exc_point (code);
6712 #ifdef TARGET_WIN32
6713                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6714 #endif
6715                 /* These are handled automatically by the stack marking code */
6716                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6717
6718                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6719                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6720                 async_exc_point (code);
6721 #ifdef TARGET_WIN32
6722                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6723 #endif
6724         }
6725
6726         /* The param area is always at offset 0 from sp */
6727         /* This needs to be allocated here, since it has to come after the spill area */
6728         if (cfg->param_area) {
6729                 if (cfg->arch.omit_fp)
6730                         // FIXME:
6731                         g_assert_not_reached ();
6732                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6733         }
6734
6735         if (cfg->arch.omit_fp) {
6736                 /*
6737                  * On enter, the stack is misaligned by the pushing of the return
6738                  * address. It is either made aligned by the pushing of %rbp, or by
6739                  * this.
6740                  */
6741                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6742                 if ((alloc_size % 16) == 0) {
6743                         alloc_size += 8;
6744                         /* Mark the padding slot as NOREF */
6745                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6746                 }
6747         } else {
6748                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6749                 if (cfg->stack_offset != alloc_size) {
6750                         /* Mark the padding slot as NOREF */
6751                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6752                 }
6753                 cfg->arch.sp_fp_offset = alloc_size;
6754                 alloc_size -= pos;
6755         }
6756
6757         cfg->arch.stack_alloc_size = alloc_size;
6758
6759         /* Allocate stack frame */
6760         if (alloc_size) {
6761                 /* See mono_emit_stack_alloc */
6762 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6763                 guint32 remaining_size = alloc_size;
6764                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6765                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6766                 guint32 offset = code - cfg->native_code;
6767                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6768                         while (required_code_size >= (cfg->code_size - offset))
6769                                 cfg->code_size *= 2;
6770                         cfg->native_code = mono_realloc_native_code (cfg);
6771                         code = cfg->native_code + offset;
6772                         cfg->stat_code_reallocs++;
6773                 }
6774
6775                 while (remaining_size >= 0x1000) {
6776                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6777                         if (cfg->arch.omit_fp) {
6778                                 cfa_offset += 0x1000;
6779                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6780                         }
6781                         async_exc_point (code);
6782 #ifdef TARGET_WIN32
6783                         if (cfg->arch.omit_fp)
6784                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6785 #endif
6786
6787                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6788                         remaining_size -= 0x1000;
6789                 }
6790                 if (remaining_size) {
6791                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6792                         if (cfg->arch.omit_fp) {
6793                                 cfa_offset += remaining_size;
6794                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6795                                 async_exc_point (code);
6796                         }
6797 #ifdef TARGET_WIN32
6798                         if (cfg->arch.omit_fp)
6799                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6800 #endif
6801                 }
6802 #else
6803                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6804                 if (cfg->arch.omit_fp) {
6805                         cfa_offset += alloc_size;
6806                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6807                         async_exc_point (code);
6808                 }
6809 #endif
6810         }
6811
6812         /* Stack alignment check */
6813 #if 0
6814         {
6815                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6816                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6817                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6818                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6819                 amd64_breakpoint (code);
6820         }
6821 #endif
6822
6823         if (mini_get_debug_options ()->init_stacks) {
6824                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6825
6826                 /* Save registers to the red zone */
6827                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6828                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6829
6830                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6831                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6832                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6833
6834                 amd64_cld (code);
6835 #if defined(__default_codegen__)
6836                 amd64_prefix (code, X86_REP_PREFIX);
6837                 amd64_stosl (code);
6838 #elif defined(__native_client_codegen__)
6839                 /* NaCl stos pseudo-instruction */
6840                 amd64_codegen_pre (code);
6841                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6842                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6843                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6844                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6845                 amd64_prefix (code, X86_REP_PREFIX);
6846                 amd64_stosl (code);
6847                 amd64_codegen_post (code);
6848 #endif /* __native_client_codegen__ */
6849
6850                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6851                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6852         }
6853
6854         /* Save LMF */
6855         if (method->save_lmf)
6856                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6857
6858         /* Save callee saved registers */
6859         if (cfg->arch.omit_fp) {
6860                 save_area_offset = cfg->arch.reg_save_area_offset;
6861                 /* Save caller saved registers after sp is adjusted */
6862                 /* The registers are saved at the bottom of the frame */
6863                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6864         } else {
6865                 /* The registers are saved just below the saved rbp */
6866                 save_area_offset = cfg->arch.reg_save_area_offset;
6867         }
6868
6869         for (i = 0; i < AMD64_NREG; ++i) {
6870                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6871                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6872
6873                         if (cfg->arch.omit_fp) {
6874                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6875                                 /* These are handled automatically by the stack marking code */
6876                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6877                         } else {
6878                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6879                                 // FIXME: GC
6880                         }
6881
6882                         save_area_offset += 8;
6883                         async_exc_point (code);
6884                 }
6885         }
6886
6887         /* store runtime generic context */
6888         if (cfg->rgctx_var) {
6889                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6890                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6891
6892                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6893
6894                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6895                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6896         }
6897
6898         /* compute max_length in order to use short forward jumps */
6899         max_epilog_size = get_max_epilog_size (cfg);
6900         if (cfg->opt & MONO_OPT_BRANCH) {
6901                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6902                         MonoInst *ins;
6903                         int max_length = 0;
6904
6905                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6906                                 max_length += 6;
6907                         /* max alignment for loops */
6908                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6909                                 max_length += LOOP_ALIGNMENT;
6910 #ifdef __native_client_codegen__
6911                         /* max alignment for native client */
6912                         max_length += kNaClAlignment;
6913 #endif
6914
6915                         MONO_BB_FOR_EACH_INS (bb, ins) {
6916 #ifdef __native_client_codegen__
6917                                 {
6918                                         int space_in_block = kNaClAlignment -
6919                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6920                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6921                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6922                                                 max_length += space_in_block;
6923                                         }
6924                                 }
6925 #endif  /*__native_client_codegen__*/
6926                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6927                         }
6928
6929                         /* Take prolog and epilog instrumentation into account */
6930                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6931                                 max_length += max_epilog_size;
6932
6933                         bb->max_length = max_length;
6934                 }
6935         }
6936
6937         sig = mono_method_signature (method);
6938         pos = 0;
6939
6940         cinfo = cfg->arch.cinfo;
6941
6942         if (sig->ret->type != MONO_TYPE_VOID) {
6943                 /* Save volatile arguments to the stack */
6944                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6945                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6946         }
6947
6948         /* Keep this in sync with emit_load_volatile_arguments */
6949         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6950                 ArgInfo *ainfo = cinfo->args + i;
6951
6952                 ins = cfg->args [i];
6953
6954                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6955                         /* Unused arguments */
6956                         continue;
6957
6958                 /* Save volatile arguments to the stack */
6959                 if (ins->opcode != OP_REGVAR) {
6960                         switch (ainfo->storage) {
6961                         case ArgInIReg: {
6962                                 guint32 size = 8;
6963
6964                                 /* FIXME: I1 etc */
6965                                 /*
6966                                 if (stack_offset & 0x1)
6967                                         size = 1;
6968                                 else if (stack_offset & 0x2)
6969                                         size = 2;
6970                                 else if (stack_offset & 0x4)
6971                                         size = 4;
6972                                 else
6973                                         size = 8;
6974                                 */
6975                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6976
6977                                 /*
6978                                  * Save the original location of 'this',
6979                                  * get_generic_info_from_stack_frame () needs this to properly look up
6980                                  * the argument value during the handling of async exceptions.
6981                                  */
6982                                 if (ins == cfg->args [0]) {
6983                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6984                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6985                                 }
6986                                 break;
6987                         }
6988                         case ArgInFloatSSEReg:
6989                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6990                                 break;
6991                         case ArgInDoubleSSEReg:
6992                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6993                                 break;
6994                         case ArgValuetypeInReg:
6995                                 for (quad = 0; quad < 2; quad ++) {
6996                                         switch (ainfo->pair_storage [quad]) {
6997                                         case ArgInIReg:
6998                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6999                                                 break;
7000                                         case ArgInFloatSSEReg:
7001                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7002                                                 break;
7003                                         case ArgInDoubleSSEReg:
7004                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7005                                                 break;
7006                                         case ArgNone:
7007                                                 break;
7008                                         default:
7009                                                 g_assert_not_reached ();
7010                                         }
7011                                 }
7012                                 break;
7013                         case ArgValuetypeAddrInIReg:
7014                                 if (ainfo->pair_storage [0] == ArgInIReg)
7015                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7016                                 break;
7017                         default:
7018                                 break;
7019                         }
7020                 } else {
7021                         /* Argument allocated to (non-volatile) register */
7022                         switch (ainfo->storage) {
7023                         case ArgInIReg:
7024                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7025                                 break;
7026                         case ArgOnStack:
7027                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7028                                 break;
7029                         default:
7030                                 g_assert_not_reached ();
7031                         }
7032
7033                         if (ins == cfg->args [0]) {
7034                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7035                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7036                         }
7037                 }
7038         }
7039
7040         if (cfg->method->save_lmf)
7041                 args_clobbered = TRUE;
7042
7043         if (trace) {
7044                 args_clobbered = TRUE;
7045                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7046         }
7047
7048         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7049                 args_clobbered = TRUE;
7050
7051         /*
7052          * Optimize the common case of the first bblock making a call with the same
7053          * arguments as the method. This works because the arguments are still in their
7054          * original argument registers.
7055          * FIXME: Generalize this
7056          */
7057         if (!args_clobbered) {
7058                 MonoBasicBlock *first_bb = cfg->bb_entry;
7059                 MonoInst *next;
7060                 int filter = FILTER_IL_SEQ_POINT;
7061
7062                 next = mono_bb_first_inst (first_bb, filter);
7063                 if (!next && first_bb->next_bb) {
7064                         first_bb = first_bb->next_bb;
7065                         next = mono_bb_first_inst (first_bb, filter);
7066                 }
7067
7068                 if (first_bb->in_count > 1)
7069                         next = NULL;
7070
7071                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7072                         ArgInfo *ainfo = cinfo->args + i;
7073                         gboolean match = FALSE;
7074
7075                         ins = cfg->args [i];
7076                         if (ins->opcode != OP_REGVAR) {
7077                                 switch (ainfo->storage) {
7078                                 case ArgInIReg: {
7079                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7080                                                 if (next->dreg == ainfo->reg) {
7081                                                         NULLIFY_INS (next);
7082                                                         match = TRUE;
7083                                                 } else {
7084                                                         next->opcode = OP_MOVE;
7085                                                         next->sreg1 = ainfo->reg;
7086                                                         /* Only continue if the instruction doesn't change argument regs */
7087                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7088                                                                 match = TRUE;
7089                                                 }
7090                                         }
7091                                         break;
7092                                 }
7093                                 default:
7094                                         break;
7095                                 }
7096                         } else {
7097                                 /* Argument allocated to (non-volatile) register */
7098                                 switch (ainfo->storage) {
7099                                 case ArgInIReg:
7100                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7101                                                 NULLIFY_INS (next);
7102                                                 match = TRUE;
7103                                         }
7104                                         break;
7105                                 default:
7106                                         break;
7107                                 }
7108                         }
7109
7110                         if (match) {
7111                                 next = mono_inst_next (next, filter);
7112                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7113                                 if (!next)
7114                                         break;
7115                         }
7116                 }
7117         }
7118
7119         if (cfg->gen_sdb_seq_points) {
7120                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7121
7122                 /* Initialize seq_point_info_var */
7123                 if (cfg->compile_aot) {
7124                         /* Initialize the variable from a GOT slot */
7125                         /* Same as OP_AOTCONST */
7126                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7127                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7128                         g_assert (info_var->opcode == OP_REGOFFSET);
7129                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7130                 }
7131
7132                 if (cfg->compile_aot) {
7133                         /* Initialize ss_tramp_var */
7134                         ins = cfg->arch.ss_tramp_var;
7135                         g_assert (ins->opcode == OP_REGOFFSET);
7136
7137                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7138                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7139                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7140                 } else {
7141                         /* Initialize ss_trigger_page_var */
7142                         ins = cfg->arch.ss_trigger_page_var;
7143
7144                         g_assert (ins->opcode == OP_REGOFFSET);
7145
7146                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7147                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7148                 }
7149         }
7150
7151         cfg->code_len = code - cfg->native_code;
7152
7153         g_assert (cfg->code_len < cfg->code_size);
7154
7155         return code;
7156 }
7157
7158 void
7159 mono_arch_emit_epilog (MonoCompile *cfg)
7160 {
7161         MonoMethod *method = cfg->method;
7162         int quad, i;
7163         guint8 *code;
7164         int max_epilog_size;
7165         CallInfo *cinfo;
7166         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7167         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7168
7169         max_epilog_size = get_max_epilog_size (cfg);
7170
7171         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7172                 cfg->code_size *= 2;
7173                 cfg->native_code = mono_realloc_native_code (cfg);
7174                 cfg->stat_code_reallocs++;
7175         }
7176         code = cfg->native_code + cfg->code_len;
7177
7178         cfg->has_unwind_info_for_epilog = TRUE;
7179
7180         /* Mark the start of the epilog */
7181         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7182
7183         /* Save the uwind state which is needed by the out-of-line code */
7184         mono_emit_unwind_op_remember_state (cfg, code);
7185
7186         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7187                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7188
7189         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7190
7191         if (method->save_lmf) {
7192                 /* check if we need to restore protection of the stack after a stack overflow */
7193                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7194                         guint8 *patch;
7195                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7196                         /* we load the value in a separate instruction: this mechanism may be
7197                          * used later as a safer way to do thread interruption
7198                          */
7199                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7200                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7201                         patch = code;
7202                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7203                         /* note that the call trampoline will preserve eax/edx */
7204                         x86_call_reg (code, X86_ECX);
7205                         x86_patch (patch, code);
7206                 } else {
7207                         /* FIXME: maybe save the jit tls in the prolog */
7208                 }
7209                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7210                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7211                 }
7212         }
7213
7214         /* Restore callee saved regs */
7215         for (i = 0; i < AMD64_NREG; ++i) {
7216                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7217                         /* Restore only used_int_regs, not arch.saved_iregs */
7218                         if (cfg->used_int_regs & (1 << i)) {
7219                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7220                                 mono_emit_unwind_op_same_value (cfg, code, i);
7221                                 async_exc_point (code);
7222                         }
7223                         save_area_offset += 8;
7224                 }
7225         }
7226
7227         /* Load returned vtypes into registers if needed */
7228         cinfo = cfg->arch.cinfo;
7229         if (cinfo->ret.storage == ArgValuetypeInReg) {
7230                 ArgInfo *ainfo = &cinfo->ret;
7231                 MonoInst *inst = cfg->ret;
7232
7233                 for (quad = 0; quad < 2; quad ++) {
7234                         switch (ainfo->pair_storage [quad]) {
7235                         case ArgInIReg:
7236                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7237                                 break;
7238                         case ArgInFloatSSEReg:
7239                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7240                                 break;
7241                         case ArgInDoubleSSEReg:
7242                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7243                                 break;
7244                         case ArgNone:
7245                                 break;
7246                         default:
7247                                 g_assert_not_reached ();
7248                         }
7249                 }
7250         }
7251
7252         if (cfg->arch.omit_fp) {
7253                 if (cfg->arch.stack_alloc_size) {
7254                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7255                 }
7256         } else {
7257                 amd64_leave (code);
7258                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7259         }
7260         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7261         async_exc_point (code);
7262         amd64_ret (code);
7263
7264         /* Restore the unwind state to be the same as before the epilog */
7265         mono_emit_unwind_op_restore_state (cfg, code);
7266
7267         cfg->code_len = code - cfg->native_code;
7268
7269         g_assert (cfg->code_len < cfg->code_size);
7270 }
7271
7272 void
7273 mono_arch_emit_exceptions (MonoCompile *cfg)
7274 {
7275         MonoJumpInfo *patch_info;
7276         int nthrows, i;
7277         guint8 *code;
7278         MonoClass *exc_classes [16];
7279         guint8 *exc_throw_start [16], *exc_throw_end [16];
7280         guint32 code_size = 0;
7281
7282         /* Compute needed space */
7283         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7284                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7285                         code_size += 40;
7286                 if (patch_info->type == MONO_PATCH_INFO_R8)
7287                         code_size += 8 + 15; /* sizeof (double) + alignment */
7288                 if (patch_info->type == MONO_PATCH_INFO_R4)
7289                         code_size += 4 + 15; /* sizeof (float) + alignment */
7290                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7291                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7292         }
7293
7294 #ifdef __native_client_codegen__
7295         /* Give us extra room on Native Client.  This could be   */
7296         /* more carefully calculated, but bundle alignment makes */
7297         /* it much trickier, so *2 like other places is good.    */
7298         code_size *= 2;
7299 #endif
7300
7301         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7302                 cfg->code_size *= 2;
7303                 cfg->native_code = mono_realloc_native_code (cfg);
7304                 cfg->stat_code_reallocs++;
7305         }
7306
7307         code = cfg->native_code + cfg->code_len;
7308
7309         /* add code to raise exceptions */
7310         nthrows = 0;
7311         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7312                 switch (patch_info->type) {
7313                 case MONO_PATCH_INFO_EXC: {
7314                         MonoClass *exc_class;
7315                         guint8 *buf, *buf2;
7316                         guint32 throw_ip;
7317
7318                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7319
7320                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7321                         g_assert (exc_class);
7322                         throw_ip = patch_info->ip.i;
7323
7324                         //x86_breakpoint (code);
7325                         /* Find a throw sequence for the same exception class */
7326                         for (i = 0; i < nthrows; ++i)
7327                                 if (exc_classes [i] == exc_class)
7328                                         break;
7329                         if (i < nthrows) {
7330                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7331                                 x86_jump_code (code, exc_throw_start [i]);
7332                                 patch_info->type = MONO_PATCH_INFO_NONE;
7333                         }
7334                         else {
7335                                 buf = code;
7336                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7337                                 buf2 = code;
7338
7339                                 if (nthrows < 16) {
7340                                         exc_classes [nthrows] = exc_class;
7341                                         exc_throw_start [nthrows] = code;
7342                                 }
7343                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7344
7345                                 patch_info->type = MONO_PATCH_INFO_NONE;
7346
7347                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7348
7349                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7350                                 while (buf < buf2)
7351                                         x86_nop (buf);
7352
7353                                 if (nthrows < 16) {
7354                                         exc_throw_end [nthrows] = code;
7355                                         nthrows ++;
7356                                 }
7357                         }
7358                         break;
7359                 }
7360                 default:
7361                         /* do nothing */
7362                         break;
7363                 }
7364                 g_assert(code < cfg->native_code + cfg->code_size);
7365         }
7366
7367         /* Handle relocations with RIP relative addressing */
7368         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7369                 gboolean remove = FALSE;
7370                 guint8 *orig_code = code;
7371
7372                 switch (patch_info->type) {
7373                 case MONO_PATCH_INFO_R8:
7374                 case MONO_PATCH_INFO_R4: {
7375                         guint8 *pos, *patch_pos;
7376                         guint32 target_pos;
7377
7378                         /* The SSE opcodes require a 16 byte alignment */
7379 #if defined(__default_codegen__)
7380                         code = (guint8*)ALIGN_TO (code, 16);
7381 #elif defined(__native_client_codegen__)
7382                         {
7383                                 /* Pad this out with HLT instructions  */
7384                                 /* or we can get garbage bytes emitted */
7385                                 /* which will fail validation          */
7386                                 guint8 *aligned_code;
7387                                 /* extra align to make room for  */
7388                                 /* mov/push below                      */
7389                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7390                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7391                                 /* The technique of hiding data in an  */
7392                                 /* instruction has a problem here: we  */
7393                                 /* need the data aligned to a 16-byte  */
7394                                 /* boundary but the instruction cannot */
7395                                 /* cross the bundle boundary. so only  */
7396                                 /* odd multiples of 16 can be used     */
7397                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7398                                         aligned_code += 16;
7399                                 }
7400                                 while (code < aligned_code) {
7401                                         *(code++) = 0xf4; /* hlt */
7402                                 }
7403                         }
7404 #endif
7405
7406                         pos = cfg->native_code + patch_info->ip.i;
7407                         if (IS_REX (pos [1])) {
7408                                 patch_pos = pos + 5;
7409                                 target_pos = code - pos - 9;
7410                         }
7411                         else {
7412                                 patch_pos = pos + 4;
7413                                 target_pos = code - pos - 8;
7414                         }
7415
7416                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7417 #ifdef __native_client_codegen__
7418                                 /* Hide 64-bit data in a         */
7419                                 /* "mov imm64, r11" instruction. */
7420                                 /* write it before the start of  */
7421                                 /* the data*/
7422                                 *(code-2) = 0x49; /* prefix      */
7423                                 *(code-1) = 0xbb; /* mov X, %r11 */
7424 #endif
7425                                 *(double*)code = *(double*)patch_info->data.target;
7426                                 code += sizeof (double);
7427                         } else {
7428 #ifdef __native_client_codegen__
7429                                 /* Hide 32-bit data in a        */
7430                                 /* "push imm32" instruction.    */
7431                                 *(code-1) = 0x68; /* push */
7432 #endif
7433                                 *(float*)code = *(float*)patch_info->data.target;
7434                                 code += sizeof (float);
7435                         }
7436
7437                         *(guint32*)(patch_pos) = target_pos;
7438
7439                         remove = TRUE;
7440                         break;
7441                 }
7442                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7443                         guint8 *pos;
7444
7445                         if (cfg->compile_aot)
7446                                 continue;
7447
7448                         /*loading is faster against aligned addresses.*/
7449                         code = (guint8*)ALIGN_TO (code, 8);
7450                         memset (orig_code, 0, code - orig_code);
7451
7452                         pos = cfg->native_code + patch_info->ip.i;
7453
7454                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7455                         if (IS_REX (pos [1]))
7456                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7457                         else
7458                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7459
7460                         *(gpointer*)code = (gpointer)patch_info->data.target;
7461                         code += sizeof (gpointer);
7462
7463                         remove = TRUE;
7464                         break;
7465                 }
7466                 default:
7467                         break;
7468                 }
7469
7470                 if (remove) {
7471                         if (patch_info == cfg->patch_info)
7472                                 cfg->patch_info = patch_info->next;
7473                         else {
7474                                 MonoJumpInfo *tmp;
7475
7476                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7477                                         ;
7478                                 tmp->next = patch_info->next;
7479                         }
7480                 }
7481                 g_assert (code < cfg->native_code + cfg->code_size);
7482         }
7483
7484         cfg->code_len = code - cfg->native_code;
7485
7486         g_assert (cfg->code_len < cfg->code_size);
7487
7488 }
7489
7490 #endif /* DISABLE_JIT */
7491
7492 void*
7493 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7494 {
7495         guchar *code = p;
7496         MonoMethodSignature *sig;
7497         MonoInst *inst;
7498         int i, n, stack_area = 0;
7499
7500         /* Keep this in sync with mono_arch_get_argument_info */
7501
7502         if (enable_arguments) {
7503                 /* Allocate a new area on the stack and save arguments there */
7504                 sig = mono_method_signature (cfg->method);
7505
7506                 n = sig->param_count + sig->hasthis;
7507
7508                 stack_area = ALIGN_TO (n * 8, 16);
7509
7510                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7511
7512                 for (i = 0; i < n; ++i) {
7513                         inst = cfg->args [i];
7514
7515                         if (inst->opcode == OP_REGVAR)
7516                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7517                         else {
7518                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7519                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7520                         }
7521                 }
7522         }
7523
7524         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7525         amd64_set_reg_template (code, AMD64_ARG_REG1);
7526         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7527         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7528
7529         if (enable_arguments)
7530                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7531
7532         return code;
7533 }
7534
7535 enum {
7536         SAVE_NONE,
7537         SAVE_STRUCT,
7538         SAVE_EAX,
7539         SAVE_EAX_EDX,
7540         SAVE_XMM
7541 };
7542
7543 void*
7544 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7545 {
7546         guchar *code = p;
7547         int save_mode = SAVE_NONE;
7548         MonoMethod *method = cfg->method;
7549         MonoType *ret_type = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
7550         int i;
7551
7552         switch (ret_type->type) {
7553         case MONO_TYPE_VOID:
7554                 /* special case string .ctor icall */
7555                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7556                         save_mode = SAVE_EAX;
7557                 else
7558                         save_mode = SAVE_NONE;
7559                 break;
7560         case MONO_TYPE_I8:
7561         case MONO_TYPE_U8:
7562                 save_mode = SAVE_EAX;
7563                 break;
7564         case MONO_TYPE_R4:
7565         case MONO_TYPE_R8:
7566                 save_mode = SAVE_XMM;
7567                 break;
7568         case MONO_TYPE_GENERICINST:
7569                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7570                         save_mode = SAVE_EAX;
7571                         break;
7572                 }
7573                 /* Fall through */
7574         case MONO_TYPE_VALUETYPE:
7575                 save_mode = SAVE_STRUCT;
7576                 break;
7577         default:
7578                 save_mode = SAVE_EAX;
7579                 break;
7580         }
7581
7582         /* Save the result and copy it into the proper argument register */
7583         switch (save_mode) {
7584         case SAVE_EAX:
7585                 amd64_push_reg (code, AMD64_RAX);
7586                 /* Align stack */
7587                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7588                 if (enable_arguments)
7589                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7590                 break;
7591         case SAVE_STRUCT:
7592                 /* FIXME: */
7593                 if (enable_arguments)
7594                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7595                 break;
7596         case SAVE_XMM:
7597                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7598                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7599                 /* Align stack */
7600                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7601                 /*
7602                  * The result is already in the proper argument register so no copying
7603                  * needed.
7604                  */
7605                 break;
7606         case SAVE_NONE:
7607                 break;
7608         default:
7609                 g_assert_not_reached ();
7610         }
7611
7612         /* Set %al since this is a varargs call */
7613         if (save_mode == SAVE_XMM)
7614                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7615         else
7616                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7617
7618         if (preserve_argument_registers) {
7619                 for (i = 0; i < PARAM_REGS; ++i)
7620                         amd64_push_reg (code, param_regs [i]);
7621         }
7622
7623         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7624         amd64_set_reg_template (code, AMD64_ARG_REG1);
7625         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7626
7627         if (preserve_argument_registers) {
7628                 for (i = PARAM_REGS - 1; i >= 0; --i)
7629                         amd64_pop_reg (code, param_regs [i]);
7630         }
7631
7632         /* Restore result */
7633         switch (save_mode) {
7634         case SAVE_EAX:
7635                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7636                 amd64_pop_reg (code, AMD64_RAX);
7637                 break;
7638         case SAVE_STRUCT:
7639                 /* FIXME: */
7640                 break;
7641         case SAVE_XMM:
7642                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7643                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7644                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7645                 break;
7646         case SAVE_NONE:
7647                 break;
7648         default:
7649                 g_assert_not_reached ();
7650         }
7651
7652         return code;
7653 }
7654
7655 void
7656 mono_arch_flush_icache (guint8 *code, gint size)
7657 {
7658         /* Not needed */
7659 }
7660
7661 void
7662 mono_arch_flush_register_windows (void)
7663 {
7664 }
7665
7666 gboolean
7667 mono_arch_is_inst_imm (gint64 imm)
7668 {
7669         return amd64_is_imm32 (imm);
7670 }
7671
7672 /*
7673  * Determine whenever the trap whose info is in SIGINFO is caused by
7674  * integer overflow.
7675  */
7676 gboolean
7677 mono_arch_is_int_overflow (void *sigctx, void *info)
7678 {
7679         MonoContext ctx;
7680         guint8* rip;
7681         int reg;
7682         gint64 value;
7683
7684         mono_sigctx_to_monoctx (sigctx, &ctx);
7685
7686         rip = (guint8*)ctx.gregs [AMD64_RIP];
7687
7688         if (IS_REX (rip [0])) {
7689                 reg = amd64_rex_b (rip [0]);
7690                 rip ++;
7691         }
7692         else
7693                 reg = 0;
7694
7695         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7696                 /* idiv REG */
7697                 reg += x86_modrm_rm (rip [1]);
7698
7699                 value = ctx.gregs [reg];
7700
7701                 if (value == -1)
7702                         return TRUE;
7703         }
7704
7705         return FALSE;
7706 }
7707
7708 guint32
7709 mono_arch_get_patch_offset (guint8 *code)
7710 {
7711         return 3;
7712 }
7713
7714 /**
7715  * mono_breakpoint_clean_code:
7716  *
7717  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7718  * breakpoints in the original code, they are removed in the copy.
7719  *
7720  * Returns TRUE if no sw breakpoint was present.
7721  */
7722 gboolean
7723 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7724 {
7725         /*
7726          * If method_start is non-NULL we need to perform bound checks, since we access memory
7727          * at code - offset we could go before the start of the method and end up in a different
7728          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7729          * instead.
7730          */
7731         if (!method_start || code - offset >= method_start) {
7732                 memcpy (buf, code - offset, size);
7733         } else {
7734                 int diff = code - method_start;
7735                 memset (buf, 0, size);
7736                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7737         }
7738         return TRUE;
7739 }
7740
7741 #if defined(__native_client_codegen__)
7742 /* For membase calls, we want the base register. for Native Client,  */
7743 /* all indirect calls have the following sequence with the given sizes: */
7744 /* mov %eXX,%eXX                                [2-3]   */
7745 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7746 /* and $0xffffffffffffffe0,%r11d                [4]     */
7747 /* add %r15,%r11                                [3]     */
7748 /* callq *%r11                                  [3]     */
7749
7750
7751 /* Determine if code points to a NaCl call-through-register sequence, */
7752 /* (i.e., the last 3 instructions listed above) */
7753 int
7754 is_nacl_call_reg_sequence(guint8* code)
7755 {
7756         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7757                                "\x4d\x03\xdf"     /* add */
7758                                "\x41\xff\xd3";   /* call */
7759         return memcmp(code, sequence, 10) == 0;
7760 }
7761
7762 /* Determine if code points to the first opcode of the mov membase component */
7763 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7764 /* (there could be a REX prefix before the opcode but it is ignored) */
7765 static int
7766 is_nacl_indirect_call_membase_sequence(guint8* code)
7767 {
7768                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7769         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7770                /* and that src reg = dest reg */
7771                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7772                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7773                IS_REX(code[2]) &&
7774                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7775                /* and has dst of r11 and base of r15 */
7776                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7777                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7778 }
7779 #endif /* __native_client_codegen__ */
7780
7781 int
7782 mono_arch_get_this_arg_reg (guint8 *code)
7783 {
7784         return AMD64_ARG_REG1;
7785 }
7786
7787 gpointer
7788 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7789 {
7790         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7791 }
7792
7793 #define MAX_ARCH_DELEGATE_PARAMS 10
7794
7795 static gpointer
7796 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7797 {
7798         guint8 *code, *start;
7799         int i;
7800
7801         if (has_target) {
7802                 start = code = mono_global_codeman_reserve (64);
7803
7804                 /* Replace the this argument with the target */
7805                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7806                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7807                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7808
7809                 g_assert ((code - start) < 64);
7810         } else {
7811                 start = code = mono_global_codeman_reserve (64);
7812
7813                 if (param_count == 0) {
7814                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7815                 } else {
7816                         /* We have to shift the arguments left */
7817                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7818                         for (i = 0; i < param_count; ++i) {
7819 #ifdef TARGET_WIN32
7820                                 if (i < 3)
7821                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7822                                 else
7823                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7824 #else
7825                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7826 #endif
7827                         }
7828
7829                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7830                 }
7831                 g_assert ((code - start) < 64);
7832         }
7833
7834         nacl_global_codeman_validate (&start, 64, &code);
7835         mono_arch_flush_icache (start, code - start);
7836
7837         if (code_len)
7838                 *code_len = code - start;
7839
7840         if (mono_jit_map_is_enabled ()) {
7841                 char *buff;
7842                 if (has_target)
7843                         buff = (char*)"delegate_invoke_has_target";
7844                 else
7845                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7846                 mono_emit_jit_tramp (start, code - start, buff);
7847                 if (!has_target)
7848                         g_free (buff);
7849         }
7850         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7851
7852         return start;
7853 }
7854
7855 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7856
7857 static gpointer
7858 get_delegate_virtual_invoke_impl (gboolean load_imt_reg, int offset, guint32 *code_len)
7859 {
7860         guint8 *code, *start;
7861         int size = 20;
7862
7863         if (offset / sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7864                 return NULL;
7865
7866         start = code = mono_global_codeman_reserve (size);
7867
7868         /* Replace the this argument with the target */
7869         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7870         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7871
7872         if (load_imt_reg) {
7873                 /* Load the IMT reg */
7874                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7875         }
7876
7877         /* Load the vtable */
7878         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7879         amd64_jump_membase (code, AMD64_RAX, offset);
7880         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7881
7882         if (code_len)
7883                 *code_len = code - start;
7884
7885         return start;
7886 }
7887
7888 /*
7889  * mono_arch_get_delegate_invoke_impls:
7890  *
7891  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7892  * trampolines.
7893  */
7894 GSList*
7895 mono_arch_get_delegate_invoke_impls (void)
7896 {
7897         GSList *res = NULL;
7898         guint8 *code;
7899         guint32 code_len;
7900         int i;
7901         char *tramp_name;
7902
7903         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7904         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7905
7906         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7907                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7908                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7909                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7910                 g_free (tramp_name);
7911         }
7912
7913         for (i = 0; i < MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7914                 code = get_delegate_virtual_invoke_impl (TRUE, i * SIZEOF_VOID_P, &code_len);
7915                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", i);
7916                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7917                 g_free (tramp_name);
7918
7919                 code = get_delegate_virtual_invoke_impl (FALSE, i * SIZEOF_VOID_P, &code_len);
7920                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", i);
7921                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7922                 g_free (tramp_name);
7923         }
7924
7925         return res;
7926 }
7927
7928 gpointer
7929 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7930 {
7931         guint8 *code, *start;
7932         int i;
7933
7934         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7935                 return NULL;
7936
7937         /* FIXME: Support more cases */
7938         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7939                 return NULL;
7940
7941         if (has_target) {
7942                 static guint8* cached = NULL;
7943
7944                 if (cached)
7945                         return cached;
7946
7947                 if (mono_aot_only)
7948                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7949                 else
7950                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7951
7952                 mono_memory_barrier ();
7953
7954                 cached = start;
7955         } else {
7956                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7957                 for (i = 0; i < sig->param_count; ++i)
7958                         if (!mono_is_regsize_var (sig->params [i]))
7959                                 return NULL;
7960                 if (sig->param_count > 4)
7961                         return NULL;
7962
7963                 code = cache [sig->param_count];
7964                 if (code)
7965                         return code;
7966
7967                 if (mono_aot_only) {
7968                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7969                         start = mono_aot_get_trampoline (name);
7970                         g_free (name);
7971                 } else {
7972                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7973                 }
7974
7975                 mono_memory_barrier ();
7976
7977                 cache [sig->param_count] = start;
7978         }
7979
7980         return start;
7981 }
7982
7983 gpointer
7984 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7985 {
7986         return get_delegate_virtual_invoke_impl (load_imt_reg, offset, NULL);
7987 }
7988
7989 void
7990 mono_arch_finish_init (void)
7991 {
7992 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7993         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7994 #endif
7995 }
7996
7997 void
7998 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7999 {
8000 }
8001
8002 #if defined(__default_codegen__)
8003 #define CMP_SIZE (6 + 1)
8004 #define CMP_REG_REG_SIZE (4 + 1)
8005 #define BR_SMALL_SIZE 2
8006 #define BR_LARGE_SIZE 6
8007 #define MOV_REG_IMM_SIZE 10
8008 #define MOV_REG_IMM_32BIT_SIZE 6
8009 #define JUMP_REG_SIZE (2 + 1)
8010 #elif defined(__native_client_codegen__)
8011 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8012 #define CMP_SIZE ((6 + 1) * 2 - 1)
8013 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8014 #define BR_SMALL_SIZE (2 * 2 - 1)
8015 #define BR_LARGE_SIZE (6 * 2 - 1)
8016 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8017 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8018 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8019 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8020 /* Jump membase's size is large and unpredictable    */
8021 /* in native client, just pad it out a whole bundle. */
8022 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8023 #endif
8024
8025 static int
8026 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8027 {
8028         int i, distance = 0;
8029         for (i = start; i < target; ++i)
8030                 distance += imt_entries [i]->chunk_size;
8031         return distance;
8032 }
8033
8034 /*
8035  * LOCKING: called with the domain lock held
8036  */
8037 gpointer
8038 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8039         gpointer fail_tramp)
8040 {
8041         int i;
8042         int size = 0;
8043         guint8 *code, *start;
8044         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8045
8046         for (i = 0; i < count; ++i) {
8047                 MonoIMTCheckItem *item = imt_entries [i];
8048                 if (item->is_equals) {
8049                         if (item->check_target_idx) {
8050                                 if (!item->compare_done) {
8051                                         if (amd64_is_imm32 (item->key))
8052                                                 item->chunk_size += CMP_SIZE;
8053                                         else
8054                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8055                                 }
8056                                 if (item->has_target_code) {
8057                                         item->chunk_size += MOV_REG_IMM_SIZE;
8058                                 } else {
8059                                         if (vtable_is_32bit)
8060                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8061                                         else
8062                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8063 #ifdef __native_client_codegen__
8064                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8065 #endif
8066                                 }
8067                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8068                         } else {
8069                                 if (fail_tramp) {
8070                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8071                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8072                                 } else {
8073                                         if (vtable_is_32bit)
8074                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8075                                         else
8076                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8077                                         item->chunk_size += JUMP_REG_SIZE;
8078                                         /* with assert below:
8079                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8080                                          */
8081 #ifdef __native_client_codegen__
8082                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8083 #endif
8084                                 }
8085                         }
8086                 } else {
8087                         if (amd64_is_imm32 (item->key))
8088                                 item->chunk_size += CMP_SIZE;
8089                         else
8090                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8091                         item->chunk_size += BR_LARGE_SIZE;
8092                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8093                 }
8094                 size += item->chunk_size;
8095         }
8096 #if defined(__native_client__) && defined(__native_client_codegen__)
8097         /* In Native Client, we don't re-use thunks, allocate from the */
8098         /* normal code manager paths. */
8099         code = mono_domain_code_reserve (domain, size);
8100 #else
8101         if (fail_tramp)
8102                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8103         else
8104                 code = mono_domain_code_reserve (domain, size);
8105 #endif
8106         start = code;
8107         for (i = 0; i < count; ++i) {
8108                 MonoIMTCheckItem *item = imt_entries [i];
8109                 item->code_target = code;
8110                 if (item->is_equals) {
8111                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8112
8113                         if (item->check_target_idx || fail_case) {
8114                                 if (!item->compare_done || fail_case) {
8115                                         if (amd64_is_imm32 (item->key))
8116                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8117                                         else {
8118                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8119                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8120                                         }
8121                                 }
8122                                 item->jmp_code = code;
8123                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8124                                 if (item->has_target_code) {
8125                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8126                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8127                                 } else {
8128                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8129                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8130                                 }
8131
8132                                 if (fail_case) {
8133                                         amd64_patch (item->jmp_code, code);
8134                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8135                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8136                                         item->jmp_code = NULL;
8137                                 }
8138                         } else {
8139                                 /* enable the commented code to assert on wrong method */
8140 #if 0
8141                                 if (amd64_is_imm32 (item->key))
8142                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8143                                 else {
8144                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8145                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8146                                 }
8147                                 item->jmp_code = code;
8148                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8149                                 /* See the comment below about R10 */
8150                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8151                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8152                                 amd64_patch (item->jmp_code, code);
8153                                 amd64_breakpoint (code);
8154                                 item->jmp_code = NULL;
8155 #else
8156                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8157                                    needs to be preserved.  R10 needs
8158                                    to be preserved for calls which
8159                                    require a runtime generic context,
8160                                    but interface calls don't. */
8161                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8162                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8163 #endif
8164                         }
8165                 } else {
8166                         if (amd64_is_imm32 (item->key))
8167                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8168                         else {
8169                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8170                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8171                         }
8172                         item->jmp_code = code;
8173                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8174                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8175                         else
8176                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8177                 }
8178                 g_assert (code - item->code_target <= item->chunk_size);
8179         }
8180         /* patch the branches to get to the target items */
8181         for (i = 0; i < count; ++i) {
8182                 MonoIMTCheckItem *item = imt_entries [i];
8183                 if (item->jmp_code) {
8184                         if (item->check_target_idx) {
8185                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8186                         }
8187                 }
8188         }
8189
8190         if (!fail_tramp)
8191                 mono_stats.imt_thunks_size += code - start;
8192         g_assert (code - start <= size);
8193
8194         nacl_domain_code_validate(domain, &start, size, &code);
8195         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8196
8197         return start;
8198 }
8199
8200 MonoMethod*
8201 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8202 {
8203         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8204 }
8205
8206 MonoVTable*
8207 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8208 {
8209         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8210 }
8211
8212 GSList*
8213 mono_arch_get_cie_program (void)
8214 {
8215         GSList *l = NULL;
8216
8217         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8218         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8219
8220         return l;
8221 }
8222
8223 #ifndef DISABLE_JIT
8224
8225 MonoInst*
8226 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8227 {
8228         MonoInst *ins = NULL;
8229         int opcode = 0;
8230
8231         if (cmethod->klass == mono_defaults.math_class) {
8232                 if (strcmp (cmethod->name, "Sin") == 0) {
8233                         opcode = OP_SIN;
8234                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8235                         opcode = OP_COS;
8236                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8237                         opcode = OP_SQRT;
8238                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8239                         opcode = OP_ABS;
8240                 }
8241
8242                 if (opcode && fsig->param_count == 1) {
8243                         MONO_INST_NEW (cfg, ins, opcode);
8244                         ins->type = STACK_R8;
8245                         ins->dreg = mono_alloc_freg (cfg);
8246                         ins->sreg1 = args [0]->dreg;
8247                         MONO_ADD_INS (cfg->cbb, ins);
8248                 }
8249
8250                 opcode = 0;
8251                 if (cfg->opt & MONO_OPT_CMOV) {
8252                         if (strcmp (cmethod->name, "Min") == 0) {
8253                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8254                                         opcode = OP_IMIN;
8255                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8256                                         opcode = OP_IMIN_UN;
8257                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8258                                         opcode = OP_LMIN;
8259                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8260                                         opcode = OP_LMIN_UN;
8261                         } else if (strcmp (cmethod->name, "Max") == 0) {
8262                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8263                                         opcode = OP_IMAX;
8264                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8265                                         opcode = OP_IMAX_UN;
8266                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8267                                         opcode = OP_LMAX;
8268                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8269                                         opcode = OP_LMAX_UN;
8270                         }
8271                 }
8272
8273                 if (opcode && fsig->param_count == 2) {
8274                         MONO_INST_NEW (cfg, ins, opcode);
8275                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8276                         ins->dreg = mono_alloc_ireg (cfg);
8277                         ins->sreg1 = args [0]->dreg;
8278                         ins->sreg2 = args [1]->dreg;
8279                         MONO_ADD_INS (cfg->cbb, ins);
8280                 }
8281
8282 #if 0
8283                 /* OP_FREM is not IEEE compatible */
8284                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8285                         MONO_INST_NEW (cfg, ins, OP_FREM);
8286                         ins->inst_i0 = args [0];
8287                         ins->inst_i1 = args [1];
8288                 }
8289 #endif
8290         }
8291
8292         return ins;
8293 }
8294 #endif
8295
8296 gboolean
8297 mono_arch_print_tree (MonoInst *tree, int arity)
8298 {
8299         return 0;
8300 }
8301
8302 mgreg_t
8303 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8304 {
8305         return ctx->gregs [reg];
8306 }
8307
8308 void
8309 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8310 {
8311         ctx->gregs [reg] = val;
8312 }
8313
8314 gpointer
8315 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8316 {
8317         gpointer *sp, old_value;
8318         char *bp;
8319
8320         /*Load the spvar*/
8321         bp = MONO_CONTEXT_GET_BP (ctx);
8322         sp = *(gpointer*)(bp + clause->exvar_offset);
8323
8324         old_value = *sp;
8325         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8326                 return old_value;
8327
8328         *sp = new_value;
8329
8330         return old_value;
8331 }
8332
8333 /*
8334  * mono_arch_emit_load_aotconst:
8335  *
8336  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8337  * TARGET from the mscorlib GOT in full-aot code.
8338  * On AMD64, the result is placed into R11.
8339  */
8340 guint8*
8341 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8342 {
8343         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8344         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8345
8346         return code;
8347 }
8348
8349 /*
8350  * mono_arch_get_trampolines:
8351  *
8352  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8353  * for AOT.
8354  */
8355 GSList *
8356 mono_arch_get_trampolines (gboolean aot)
8357 {
8358         return mono_amd64_get_exception_trampolines (aot);
8359 }
8360
8361 /* Soft Debug support */
8362 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8363
8364 /*
8365  * mono_arch_set_breakpoint:
8366  *
8367  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8368  * The location should contain code emitted by OP_SEQ_POINT.
8369  */
8370 void
8371 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8372 {
8373         guint8 *code = ip;
8374         guint8 *orig_code = code;
8375
8376         if (ji->from_aot) {
8377                 guint32 native_offset = ip - (guint8*)ji->code_start;
8378                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8379
8380                 g_assert (info->bp_addrs [native_offset] == 0);
8381                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8382         } else {
8383                 /*
8384                  * In production, we will use int3 (has to fix the size in the md
8385                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8386                  * instead.
8387                  */
8388                 g_assert (code [0] == 0x90);
8389                 if (breakpoint_size == 8) {
8390                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8391                 } else {
8392                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8393                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8394                 }
8395
8396                 g_assert (code - orig_code == breakpoint_size);
8397         }
8398 }
8399
8400 /*
8401  * mono_arch_clear_breakpoint:
8402  *
8403  *   Clear the breakpoint at IP.
8404  */
8405 void
8406 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8407 {
8408         guint8 *code = ip;
8409         int i;
8410
8411         if (ji->from_aot) {
8412                 guint32 native_offset = ip - (guint8*)ji->code_start;
8413                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8414
8415                 info->bp_addrs [native_offset] = NULL;
8416         } else {
8417                 for (i = 0; i < breakpoint_size; ++i)
8418                         x86_nop (code);
8419         }
8420 }
8421
8422 gboolean
8423 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8424 {
8425 #ifdef HOST_WIN32
8426         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8427         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8428                 return TRUE;
8429         else
8430                 return FALSE;
8431 #else
8432         siginfo_t* sinfo = (siginfo_t*) info;
8433         /* Sometimes the address is off by 4 */
8434         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8435                 return TRUE;
8436         else
8437                 return FALSE;
8438 #endif
8439 }
8440
8441 /*
8442  * mono_arch_skip_breakpoint:
8443  *
8444  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8445  * we resume, the instruction is not executed again.
8446  */
8447 void
8448 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8449 {
8450         if (ji->from_aot) {
8451                 /* The breakpoint instruction is a call */
8452         } else {
8453                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8454         }
8455 }
8456
8457 /*
8458  * mono_arch_start_single_stepping:
8459  *
8460  *   Start single stepping.
8461  */
8462 void
8463 mono_arch_start_single_stepping (void)
8464 {
8465         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8466         ss_trampoline = mini_get_single_step_trampoline ();
8467 }
8468
8469 /*
8470  * mono_arch_stop_single_stepping:
8471  *
8472  *   Stop single stepping.
8473  */
8474 void
8475 mono_arch_stop_single_stepping (void)
8476 {
8477         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8478         ss_trampoline = NULL;
8479 }
8480
8481 /*
8482  * mono_arch_is_single_step_event:
8483  *
8484  *   Return whenever the machine state in SIGCTX corresponds to a single
8485  * step event.
8486  */
8487 gboolean
8488 mono_arch_is_single_step_event (void *info, void *sigctx)
8489 {
8490 #ifdef HOST_WIN32
8491         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8492         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8493                 return TRUE;
8494         else
8495                 return FALSE;
8496 #else
8497         siginfo_t* sinfo = (siginfo_t*) info;
8498         /* Sometimes the address is off by 4 */
8499         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8500                 return TRUE;
8501         else
8502                 return FALSE;
8503 #endif
8504 }
8505
8506 /*
8507  * mono_arch_skip_single_step:
8508  *
8509  *   Modify CTX so the ip is placed after the single step trigger instruction,
8510  * we resume, the instruction is not executed again.
8511  */
8512 void
8513 mono_arch_skip_single_step (MonoContext *ctx)
8514 {
8515         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8516 }
8517
8518 /*
8519  * mono_arch_create_seq_point_info:
8520  *
8521  *   Return a pointer to a data structure which is used by the sequence
8522  * point implementation in AOTed code.
8523  */
8524 gpointer
8525 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8526 {
8527         SeqPointInfo *info;
8528         MonoJitInfo *ji;
8529
8530         // FIXME: Add a free function
8531
8532         mono_domain_lock (domain);
8533         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8534                                                                 code);
8535         mono_domain_unlock (domain);
8536
8537         if (!info) {
8538                 ji = mono_jit_info_table_find (domain, (char*)code);
8539                 g_assert (ji);
8540
8541                 // FIXME: Optimize the size
8542                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8543
8544                 info->ss_tramp_addr = &ss_trampoline;
8545
8546                 mono_domain_lock (domain);
8547                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8548                                                          code, info);
8549                 mono_domain_unlock (domain);
8550         }
8551
8552         return info;
8553 }
8554
8555 void
8556 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8557 {
8558         ext->lmf.previous_lmf = prev_lmf;
8559         /* Mark that this is a MonoLMFExt */
8560         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8561         ext->lmf.rsp = (gssize)ext;
8562 }
8563
8564 #endif
8565
8566 gboolean
8567 mono_arch_opcode_supported (int opcode)
8568 {
8569         switch (opcode) {
8570         case OP_ATOMIC_ADD_I4:
8571         case OP_ATOMIC_ADD_I8:
8572         case OP_ATOMIC_EXCHANGE_I4:
8573         case OP_ATOMIC_EXCHANGE_I8:
8574         case OP_ATOMIC_CAS_I4:
8575         case OP_ATOMIC_CAS_I8:
8576         case OP_ATOMIC_LOAD_I1:
8577         case OP_ATOMIC_LOAD_I2:
8578         case OP_ATOMIC_LOAD_I4:
8579         case OP_ATOMIC_LOAD_I8:
8580         case OP_ATOMIC_LOAD_U1:
8581         case OP_ATOMIC_LOAD_U2:
8582         case OP_ATOMIC_LOAD_U4:
8583         case OP_ATOMIC_LOAD_U8:
8584         case OP_ATOMIC_LOAD_R4:
8585         case OP_ATOMIC_LOAD_R8:
8586         case OP_ATOMIC_STORE_I1:
8587         case OP_ATOMIC_STORE_I2:
8588         case OP_ATOMIC_STORE_I4:
8589         case OP_ATOMIC_STORE_I8:
8590         case OP_ATOMIC_STORE_U1:
8591         case OP_ATOMIC_STORE_U2:
8592         case OP_ATOMIC_STORE_U4:
8593         case OP_ATOMIC_STORE_U8:
8594         case OP_ATOMIC_STORE_R4:
8595         case OP_ATOMIC_STORE_R8:
8596                 return TRUE;
8597         default:
8598                 return FALSE;
8599         }
8600 }