mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27 #include <mono/utils/mono-mmap.h>
  28
  29 #include "trace.h"
  30 #include "ir-emit.h"
  31 #include "mini-amd64.h"
  32 #include "cpu-amd64.h"
  33 #include "debugger-agent.h"
  34
  35 /*
  36  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  37  * method-to-ir.c.
  38  */
  39 #define MONO_ARCH_IMT_REG AMD64_R11
  40
  41 static gint lmf_tls_offset = -1;
  42 static gint lmf_addr_tls_offset = -1;
  43 static gint appdomain_tls_offset = -1;
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef HOST_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* amd64_mov_reg_imm () */
  65 #define BREAKPOINT_SIZE 8
  66
  67 /* This mutex protects architecture specific caches */
  68 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  69 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  70 static CRITICAL_SECTION mini_arch_mutex;
  71
  72 MonoBreakpointInfo
  73 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  74
  75 /*
  76  * The code generated for sequence points reads from this location, which is
  77  * made read-only when single stepping is enabled.
  78  */
  79 static gpointer ss_trigger_page;
  80
  81 /* Enabled breakpoints read from this trigger page */
  82 static gpointer bp_trigger_page;
  83
  84 #ifdef HOST_WIN32
  85 /* On Win64 always reserve first 32 bytes for first four arguments */
  86 #define ARGS_OFFSET 48
  87 #else
  88 #define ARGS_OFFSET 16
  89 #endif
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 G_GNUC_UNUSED static void
 162 break_count (void)
 163 {
 164 }
 165
 166 G_GNUC_UNUSED static gboolean
 167 debug_count (void)
 168 {
 169         static int count = 0;
 170         count ++;
 171
 172         if (!getenv ("COUNT"))
 173                 return TRUE;
 174
 175         if (count == atoi (getenv ("COUNT"))) {
 176                 break_count ();
 177         }
 178
 179         if (count > atoi (getenv ("COUNT"))) {
 180                 return FALSE;
 181         }
 182
 183         return TRUE;
 184 }
 185
 186 static gboolean
 187 debug_omit_fp (void)
 188 {
 189 #if 0
 190         return debug_count ();
 191 #else
 192         return TRUE;
 193 #endif
 194 }
 195
 196 static inline gboolean
 197 amd64_is_near_call (guint8 *code)
 198 {
 199         /* Skip REX */
 200         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 201                 code += 1;
 202
 203         return code [0] == 0xe8;
 204 }
 205
 206 static inline void
 207 amd64_patch (unsigned char* code, gpointer target)
 208 {
 209         guint8 rex = 0;
 210
 211         /* Skip REX */
 212         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 213                 rex = code [0];
 214                 code += 1;
 215         }
 216
 217         if ((code [0] & 0xf8) == 0xb8) {
 218                 /* amd64_set_reg_template */
 219                 *(guint64*)(code + 1) = (guint64)target;
 220         }
 221         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 222                 /* mov 0(%rip), %dreg */
 223                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 224         }
 225         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 226                 /* call *<OFFSET>(%rip) */
 227                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 228         }
 229         else if ((code [0] == 0xe8)) {
 230                 /* call <DISP> */
 231                 gint64 disp = (guint8*)target - (guint8*)code;
 232                 g_assert (amd64_is_imm32 (disp));
 233                 x86_patch (code, (unsigned char*)target);
 234         }
 235         else
 236                 x86_patch (code, (unsigned char*)target);
 237 }
 238
 239 void
 240 mono_amd64_patch (unsigned char* code, gpointer target)
 241 {
 242         amd64_patch (code, target);
 243 }
 244
 245 typedef enum {
 246         ArgInIReg,
 247         ArgInFloatSSEReg,
 248         ArgInDoubleSSEReg,
 249         ArgOnStack,
 250         ArgValuetypeInReg,
 251         ArgValuetypeAddrInIReg,
 252         ArgNone /* only in pair_storage */
 253 } ArgStorage;
 254
 255 typedef struct {
 256         gint16 offset;
 257         gint8  reg;
 258         ArgStorage storage;
 259
 260         /* Only if storage == ArgValuetypeInReg */
 261         ArgStorage pair_storage [2];
 262         gint8 pair_regs [2];
 263 } ArgInfo;
 264
 265 typedef struct {
 266         int nargs;
 267         guint32 stack_usage;
 268         guint32 reg_usage;
 269         guint32 freg_usage;
 270         gboolean need_stack_align;
 271         gboolean vtype_retaddr;
 272         ArgInfo ret;
 273         ArgInfo sig_cookie;
 274         ArgInfo args [1];
 275 } CallInfo;
 276
 277 #define DEBUG(a) if (cfg->verbose_level > 1) a
 278
 279 #ifdef HOST_WIN32
 280 #define PARAM_REGS 4
 281
 282 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 283
 284 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 285 #else
 286 #define PARAM_REGS 6
 287
 288 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 289
 290  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 291 #endif
 292
 293 static void inline
 294 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 295 {
 296     ainfo->offset = *stack_size;
 297
 298     if (*gr >= PARAM_REGS) {
 299                 ainfo->storage = ArgOnStack;
 300                 (*stack_size) += sizeof (gpointer);
 301     }
 302     else {
 303                 ainfo->storage = ArgInIReg;
 304                 ainfo->reg = param_regs [*gr];
 305                 (*gr) ++;
 306     }
 307 }
 308
 309 #ifdef HOST_WIN32
 310 #define FLOAT_PARAM_REGS 4
 311 #else
 312 #define FLOAT_PARAM_REGS 8
 313 #endif
 314
 315 static void inline
 316 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 317 {
 318     ainfo->offset = *stack_size;
 319
 320     if (*gr >= FLOAT_PARAM_REGS) {
 321                 ainfo->storage = ArgOnStack;
 322                 (*stack_size) += sizeof (gpointer);
 323     }
 324     else {
 325                 /* A double register */
 326                 if (is_double)
 327                         ainfo->storage = ArgInDoubleSSEReg;
 328                 else
 329                         ainfo->storage = ArgInFloatSSEReg;
 330                 ainfo->reg = *gr;
 331                 (*gr) += 1;
 332     }
 333 }
 334
 335 typedef enum ArgumentClass {
 336         ARG_CLASS_NO_CLASS,
 337         ARG_CLASS_MEMORY,
 338         ARG_CLASS_INTEGER,
 339         ARG_CLASS_SSE
 340 } ArgumentClass;
 341
 342 static ArgumentClass
 343 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 344 {
 345         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 346         MonoType *ptype;
 347
 348         ptype = mini_type_get_underlying_type (NULL, type);
 349         switch (ptype->type) {
 350         case MONO_TYPE_BOOLEAN:
 351         case MONO_TYPE_CHAR:
 352         case MONO_TYPE_I1:
 353         case MONO_TYPE_U1:
 354         case MONO_TYPE_I2:
 355         case MONO_TYPE_U2:
 356         case MONO_TYPE_I4:
 357         case MONO_TYPE_U4:
 358         case MONO_TYPE_I:
 359         case MONO_TYPE_U:
 360         case MONO_TYPE_STRING:
 361         case MONO_TYPE_OBJECT:
 362         case MONO_TYPE_CLASS:
 363         case MONO_TYPE_SZARRAY:
 364         case MONO_TYPE_PTR:
 365         case MONO_TYPE_FNPTR:
 366         case MONO_TYPE_ARRAY:
 367         case MONO_TYPE_I8:
 368         case MONO_TYPE_U8:
 369                 class2 = ARG_CLASS_INTEGER;
 370                 break;
 371         case MONO_TYPE_R4:
 372         case MONO_TYPE_R8:
 373 #ifdef HOST_WIN32
 374                 class2 = ARG_CLASS_INTEGER;
 375 #else
 376                 class2 = ARG_CLASS_SSE;
 377 #endif
 378                 break;
 379
 380         case MONO_TYPE_TYPEDBYREF:
 381                 g_assert_not_reached ();
 382
 383         case MONO_TYPE_GENERICINST:
 384                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 385                         class2 = ARG_CLASS_INTEGER;
 386                         break;
 387                 }
 388                 /* fall through */
 389         case MONO_TYPE_VALUETYPE: {
 390                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 391                 int i;
 392
 393                 for (i = 0; i < info->num_fields; ++i) {
 394                         class2 = class1;
 395                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 396                 }
 397                 break;
 398         }
 399         default:
 400                 g_assert_not_reached ();
 401         }
 402
 403         /* Merge */
 404         if (class1 == class2)
 405                 ;
 406         else if (class1 == ARG_CLASS_NO_CLASS)
 407                 class1 = class2;
 408         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 409                 class1 = ARG_CLASS_MEMORY;
 410         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 411                 class1 = ARG_CLASS_INTEGER;
 412         else
 413                 class1 = ARG_CLASS_SSE;
 414
 415         return class1;
 416 }
 417
 418 static void
 419 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 420                            gboolean is_return,
 421                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 422 {
 423         guint32 size, quad, nquads, i;
 424         ArgumentClass args [2];
 425         MonoMarshalType *info = NULL;
 426         MonoClass *klass;
 427         MonoGenericSharingContext tmp_gsctx;
 428         gboolean pass_on_stack = FALSE;
 429
 430         /*
 431          * The gsctx currently contains no data, it is only used for checking whenever
 432          * open types are allowed, some callers like mono_arch_get_argument_info ()
 433          * don't pass it to us, so work around that.
 434          */
 435         if (!gsctx)
 436                 gsctx = &tmp_gsctx;
 437
 438         klass = mono_class_from_mono_type (type);
 439         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 440 #ifndef HOST_WIN32
 441         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 442                 /* We pass and return vtypes of size 8 in a register */
 443         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 444                 pass_on_stack = TRUE;
 445         }
 446 #else
 447         if (!sig->pinvoke) {
 448                 pass_on_stack = TRUE;
 449         }
 450 #endif
 451
 452         if (pass_on_stack) {
 453                 /* Allways pass in memory */
 454                 ainfo->offset = *stack_size;
 455                 *stack_size += ALIGN_TO (size, 8);
 456                 ainfo->storage = ArgOnStack;
 457
 458                 return;
 459         }
 460
 461         /* FIXME: Handle structs smaller than 8 bytes */
 462         //if ((size % 8) != 0)
 463         //      NOT_IMPLEMENTED;
 464
 465         if (size > 8)
 466                 nquads = 2;
 467         else
 468                 nquads = 1;
 469
 470         if (!sig->pinvoke) {
 471                 /* Always pass in 1 or 2 integer registers */
 472                 args [0] = ARG_CLASS_INTEGER;
 473                 args [1] = ARG_CLASS_INTEGER;
 474                 /* Only the simplest cases are supported */
 475                 if (is_return && nquads != 1) {
 476                         args [0] = ARG_CLASS_MEMORY;
 477                         args [1] = ARG_CLASS_MEMORY;
 478                 }
 479         } else {
 480                 /*
 481                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 482                  * The X87 and SSEUP stuff is left out since there are no such types in
 483                  * the CLR.
 484                  */
 485                 info = mono_marshal_load_type_info (klass);
 486                 g_assert (info);
 487
 488 #ifndef HOST_WIN32
 489                 if (info->native_size > 16) {
 490                         ainfo->offset = *stack_size;
 491                         *stack_size += ALIGN_TO (info->native_size, 8);
 492                         ainfo->storage = ArgOnStack;
 493
 494                         return;
 495                 }
 496 #else
 497                 switch (info->native_size) {
 498                 case 1: case 2: case 4: case 8:
 499                         break;
 500                 default:
 501                         if (is_return) {
 502                                 ainfo->storage = ArgOnStack;
 503                                 ainfo->offset = *stack_size;
 504                                 *stack_size += ALIGN_TO (info->native_size, 8);
 505                         }
 506                         else {
 507                                 ainfo->storage = ArgValuetypeAddrInIReg;
 508
 509                                 if (*gr < PARAM_REGS) {
 510                                         ainfo->pair_storage [0] = ArgInIReg;
 511                                         ainfo->pair_regs [0] = param_regs [*gr];
 512                                         (*gr) ++;
 513                                 }
 514                                 else {
 515                                         ainfo->pair_storage [0] = ArgOnStack;
 516                                         ainfo->offset = *stack_size;
 517                                         *stack_size += 8;
 518                                 }
 519                         }
 520
 521                         return;
 522                 }
 523 #endif
 524
 525                 args [0] = ARG_CLASS_NO_CLASS;
 526                 args [1] = ARG_CLASS_NO_CLASS;
 527                 for (quad = 0; quad < nquads; ++quad) {
 528                         int size;
 529                         guint32 align;
 530                         ArgumentClass class1;
 531
 532                         if (info->num_fields == 0)
 533                                 class1 = ARG_CLASS_MEMORY;
 534                         else
 535                                 class1 = ARG_CLASS_NO_CLASS;
 536                         for (i = 0; i < info->num_fields; ++i) {
 537                                 size = mono_marshal_type_size (info->fields [i].field->type,
 538                                                                                            info->fields [i].mspec,
 539                                                                                            &align, TRUE, klass->unicode);
 540                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 541                                         /* Unaligned field */
 542                                         NOT_IMPLEMENTED;
 543                                 }
 544
 545                                 /* Skip fields in other quad */
 546                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 547                                         continue;
 548                                 if ((quad == 1) && (info->fields [i].offset < 8))
 549                                         continue;
 550
 551                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 552                         }
 553                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 554                         args [quad] = class1;
 555                 }
 556         }
 557
 558         /* Post merger cleanup */
 559         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 560                 args [0] = args [1] = ARG_CLASS_MEMORY;
 561
 562         /* Allocate registers */
 563         {
 564                 int orig_gr = *gr;
 565                 int orig_fr = *fr;
 566
 567                 ainfo->storage = ArgValuetypeInReg;
 568                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 569                 for (quad = 0; quad < nquads; ++quad) {
 570                         switch (args [quad]) {
 571                         case ARG_CLASS_INTEGER:
 572                                 if (*gr >= PARAM_REGS)
 573                                         args [quad] = ARG_CLASS_MEMORY;
 574                                 else {
 575                                         ainfo->pair_storage [quad] = ArgInIReg;
 576                                         if (is_return)
 577                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 578                                         else
 579                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 580                                         (*gr) ++;
 581                                 }
 582                                 break;
 583                         case ARG_CLASS_SSE:
 584                                 if (*fr >= FLOAT_PARAM_REGS)
 585                                         args [quad] = ARG_CLASS_MEMORY;
 586                                 else {
 587                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 588                                         ainfo->pair_regs [quad] = *fr;
 589                                         (*fr) ++;
 590                                 }
 591                                 break;
 592                         case ARG_CLASS_MEMORY:
 593                                 break;
 594                         default:
 595                                 g_assert_not_reached ();
 596                         }
 597                 }
 598
 599                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 600                         /* Revert possible register assignments */
 601                         *gr = orig_gr;
 602                         *fr = orig_fr;
 603
 604                         ainfo->offset = *stack_size;
 605                         if (sig->pinvoke)
 606                                 *stack_size += ALIGN_TO (info->native_size, 8);
 607                         else
 608                                 *stack_size += nquads * sizeof (gpointer);
 609                         ainfo->storage = ArgOnStack;
 610                 }
 611         }
 612 }
 613
 614 /*
 615  * get_call_info:
 616  *
 617  *  Obtain information about a call according to the calling convention.
 618  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 619  * Draft Version 0.23" document for more information.
 620  */
 621 static CallInfo*
 622 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 623 {
 624         guint32 i, gr, fr;
 625         MonoType *ret_type;
 626         int n = sig->hasthis + sig->param_count;
 627         guint32 stack_size = 0;
 628         CallInfo *cinfo;
 629
 630         if (mp)
 631                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 632         else
 633                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 634
 635         cinfo->nargs = n;
 636
 637         gr = 0;
 638         fr = 0;
 639
 640         /* return value */
 641         {
 642                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 643                 switch (ret_type->type) {
 644                 case MONO_TYPE_BOOLEAN:
 645                 case MONO_TYPE_I1:
 646                 case MONO_TYPE_U1:
 647                 case MONO_TYPE_I2:
 648                 case MONO_TYPE_U2:
 649                 case MONO_TYPE_CHAR:
 650                 case MONO_TYPE_I4:
 651                 case MONO_TYPE_U4:
 652                 case MONO_TYPE_I:
 653                 case MONO_TYPE_U:
 654                 case MONO_TYPE_PTR:
 655                 case MONO_TYPE_FNPTR:
 656                 case MONO_TYPE_CLASS:
 657                 case MONO_TYPE_OBJECT:
 658                 case MONO_TYPE_SZARRAY:
 659                 case MONO_TYPE_ARRAY:
 660                 case MONO_TYPE_STRING:
 661                         cinfo->ret.storage = ArgInIReg;
 662                         cinfo->ret.reg = AMD64_RAX;
 663                         break;
 664                 case MONO_TYPE_U8:
 665                 case MONO_TYPE_I8:
 666                         cinfo->ret.storage = ArgInIReg;
 667                         cinfo->ret.reg = AMD64_RAX;
 668                         break;
 669                 case MONO_TYPE_R4:
 670                         cinfo->ret.storage = ArgInFloatSSEReg;
 671                         cinfo->ret.reg = AMD64_XMM0;
 672                         break;
 673                 case MONO_TYPE_R8:
 674                         cinfo->ret.storage = ArgInDoubleSSEReg;
 675                         cinfo->ret.reg = AMD64_XMM0;
 676                         break;
 677                 case MONO_TYPE_GENERICINST:
 678                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 679                                 cinfo->ret.storage = ArgInIReg;
 680                                 cinfo->ret.reg = AMD64_RAX;
 681                                 break;
 682                         }
 683                         /* fall through */
 684                 case MONO_TYPE_VALUETYPE: {
 685                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 686
 687                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 688                         if (cinfo->ret.storage == ArgOnStack) {
 689                                 cinfo->vtype_retaddr = TRUE;
 690                                 /* The caller passes the address where the value is stored */
 691                                 add_general (&gr, &stack_size, &cinfo->ret);
 692                         }
 693                         break;
 694                 }
 695                 case MONO_TYPE_TYPEDBYREF:
 696                         /* Same as a valuetype with size 24 */
 697                         add_general (&gr, &stack_size, &cinfo->ret);
 698                         ;
 699                         break;
 700                 case MONO_TYPE_VOID:
 701                         break;
 702                 default:
 703                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 704                 }
 705         }
 706
 707         /* this */
 708         if (sig->hasthis)
 709                 add_general (&gr, &stack_size, cinfo->args + 0);
 710
 711         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 712                 gr = PARAM_REGS;
 713                 fr = FLOAT_PARAM_REGS;
 714
 715                 /* Emit the signature cookie just before the implicit arguments */
 716                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 717         }
 718
 719         for (i = 0; i < sig->param_count; ++i) {
 720                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 721                 MonoType *ptype;
 722
 723 #ifdef HOST_WIN32
 724                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 725                 if (gr > fr)
 726                         fr = gr;
 727                 else if (fr > gr)
 728                         gr = fr;
 729 #endif
 730
 731                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 732                         /* We allways pass the sig cookie on the stack for simplicity */
 733                         /*
 734                          * Prevent implicit arguments + the sig cookie from being passed
 735                          * in registers.
 736                          */
 737                         gr = PARAM_REGS;
 738                         fr = FLOAT_PARAM_REGS;
 739
 740                         /* Emit the signature cookie just before the implicit arguments */
 741                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 742                 }
 743
 744                 if (sig->params [i]->byref) {
 745                         add_general (&gr, &stack_size, ainfo);
 746                         continue;
 747                 }
 748                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 749                 switch (ptype->type) {
 750                 case MONO_TYPE_BOOLEAN:
 751                 case MONO_TYPE_I1:
 752                 case MONO_TYPE_U1:
 753                         add_general (&gr, &stack_size, ainfo);
 754                         break;
 755                 case MONO_TYPE_I2:
 756                 case MONO_TYPE_U2:
 757                 case MONO_TYPE_CHAR:
 758                         add_general (&gr, &stack_size, ainfo);
 759                         break;
 760                 case MONO_TYPE_I4:
 761                 case MONO_TYPE_U4:
 762                         add_general (&gr, &stack_size, ainfo);
 763                         break;
 764                 case MONO_TYPE_I:
 765                 case MONO_TYPE_U:
 766                 case MONO_TYPE_PTR:
 767                 case MONO_TYPE_FNPTR:
 768                 case MONO_TYPE_CLASS:
 769                 case MONO_TYPE_OBJECT:
 770                 case MONO_TYPE_STRING:
 771                 case MONO_TYPE_SZARRAY:
 772                 case MONO_TYPE_ARRAY:
 773                         add_general (&gr, &stack_size, ainfo);
 774                         break;
 775                 case MONO_TYPE_GENERICINST:
 776                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 777                                 add_general (&gr, &stack_size, ainfo);
 778                                 break;
 779                         }
 780                         /* fall through */
 781                 case MONO_TYPE_VALUETYPE:
 782                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 783                         break;
 784                 case MONO_TYPE_TYPEDBYREF:
 785 #ifdef HOST_WIN32
 786                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 787 #else
 788                         stack_size += sizeof (MonoTypedRef);
 789                         ainfo->storage = ArgOnStack;
 790 #endif
 791                         break;
 792                 case MONO_TYPE_U8:
 793                 case MONO_TYPE_I8:
 794                         add_general (&gr, &stack_size, ainfo);
 795                         break;
 796                 case MONO_TYPE_R4:
 797                         add_float (&fr, &stack_size, ainfo, FALSE);
 798                         break;
 799                 case MONO_TYPE_R8:
 800                         add_float (&fr, &stack_size, ainfo, TRUE);
 801                         break;
 802                 default:
 803                         g_assert_not_reached ();
 804                 }
 805         }
 806
 807         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 808                 gr = PARAM_REGS;
 809                 fr = FLOAT_PARAM_REGS;
 810
 811                 /* Emit the signature cookie just before the implicit arguments */
 812                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 813         }
 814
 815 #ifdef HOST_WIN32
 816         // There always is 32 bytes reserved on the stack when calling on Winx64
 817         stack_size += 0x20;
 818 #endif
 819
 820         if (stack_size & 0x8) {
 821                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 822                 cinfo->need_stack_align = TRUE;
 823                 stack_size += 8;
 824         }
 825
 826         cinfo->stack_usage = stack_size;
 827         cinfo->reg_usage = gr;
 828         cinfo->freg_usage = fr;
 829         return cinfo;
 830 }
 831
 832 /*
 833  * mono_arch_get_argument_info:
 834  * @csig:  a method signature
 835  * @param_count: the number of parameters to consider
 836  * @arg_info: an array to store the result infos
 837  *
 838  * Gathers information on parameters such as size, alignment and
 839  * padding. arg_info should be large enought to hold param_count + 1 entries.
 840  *
 841  * Returns the size of the argument area on the stack.
 842  */
 843 int
 844 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 845 {
 846         int k;
 847         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 848         guint32 args_size = cinfo->stack_usage;
 849
 850         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 851         if (csig->hasthis) {
 852                 arg_info [0].offset = 0;
 853         }
 854
 855         for (k = 0; k < param_count; k++) {
 856                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 857                 /* FIXME: */
 858                 arg_info [k + 1].size = 0;
 859         }
 860
 861         g_free (cinfo);
 862
 863         return args_size;
 864 }
 865
 866 static int
 867 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 868 {
 869 #ifndef _MSC_VER
 870         __asm__ __volatile__ ("cpuid"
 871                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 872                 : "a" (id));
 873 #else
 874         int info[4];
 875         __cpuid(info, id);
 876         *p_eax = info[0];
 877         *p_ebx = info[1];
 878         *p_ecx = info[2];
 879         *p_edx = info[3];
 880 #endif
 881         return 1;
 882 }
 883
 884 /*
 885  * Initialize the cpu to execute managed code.
 886  */
 887 void
 888 mono_arch_cpu_init (void)
 889 {
 890 #ifndef _MSC_VER
 891         guint16 fpcw;
 892
 893         /* spec compliance requires running with double precision */
 894         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 895         fpcw &= ~X86_FPCW_PRECC_MASK;
 896         fpcw |= X86_FPCW_PREC_DOUBLE;
 897         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 898         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 899 #else
 900         /* TODO: This is crashing on Win64 right now.
 901         * _control87 (_PC_53, MCW_PC);
 902         */
 903 #endif
 904 }
 905
 906 /*
 907  * Initialize architecture specific code.
 908  */
 909 void
 910 mono_arch_init (void)
 911 {
 912         InitializeCriticalSection (&mini_arch_mutex);
 913
 914         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 915         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 916         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 917 }
 918
 919 /*
 920  * Cleanup architecture specific code.
 921  */
 922 void
 923 mono_arch_cleanup (void)
 924 {
 925         DeleteCriticalSection (&mini_arch_mutex);
 926 }
 927
 928 /*
 929  * This function returns the optimizations supported on this cpu.
 930  */
 931 guint32
 932 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 933 {
 934         int eax, ebx, ecx, edx;
 935         guint32 opts = 0;
 936
 937         /* FIXME: AMD64 */
 938
 939         *exclude_mask = 0;
 940         /* Feature Flags function, flags returned in EDX. */
 941         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 942                 if (edx & (1 << 15)) {
 943                         opts |= MONO_OPT_CMOV;
 944                         if (edx & 1)
 945                                 opts |= MONO_OPT_FCMOV;
 946                         else
 947                                 *exclude_mask |= MONO_OPT_FCMOV;
 948                 } else
 949                         *exclude_mask |= MONO_OPT_CMOV;
 950         }
 951
 952         return opts;
 953 }
 954
 955 /*
 956  * This function test for all SSE functions supported.
 957  *
 958  * Returns a bitmask corresponding to all supported versions.
 959  *
 960  */
 961 guint32
 962 mono_arch_cpu_enumerate_simd_versions (void)
 963 {
 964         int eax, ebx, ecx, edx;
 965         guint32 sse_opts = 0;
 966
 967         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 968                 if (edx & (1 << 25))
 969                         sse_opts |= 1 << SIMD_VERSION_SSE1;
 970                 if (edx & (1 << 26))
 971                         sse_opts |= 1 << SIMD_VERSION_SSE2;
 972                 if (ecx & (1 << 0))
 973                         sse_opts |= 1 << SIMD_VERSION_SSE3;
 974                 if (ecx & (1 << 9))
 975                         sse_opts |= 1 << SIMD_VERSION_SSSE3;
 976                 if (ecx & (1 << 19))
 977                         sse_opts |= 1 << SIMD_VERSION_SSE41;
 978                 if (ecx & (1 << 20))
 979                         sse_opts |= 1 << SIMD_VERSION_SSE42;
 980         }
 981
 982         /* Yes, all this needs to be done to check for sse4a.
 983            See: "Amd: CPUID Specification"
 984          */
 985         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
 986                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
 987                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
 988                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
 989                         if (ecx & (1 << 6))
 990                                 sse_opts |= 1 << SIMD_VERSION_SSE4a;
 991                 }
 992         }
 993
 994         return sse_opts;
 995 }
 996
 997 GList *
 998 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 999 {
1000         GList *vars = NULL;
1001         int i;
1002
1003         for (i = 0; i < cfg->num_varinfo; i++) {
1004                 MonoInst *ins = cfg->varinfo [i];
1005                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1006
1007                 /* unused vars */
1008                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1009                         continue;
1010
1011                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1012                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1013                         continue;
1014
1015                 if (mono_is_regsize_var (ins->inst_vtype)) {
1016                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1017                         g_assert (i == vmv->idx);
1018                         vars = g_list_prepend (vars, vmv);
1019                 }
1020         }
1021
1022         vars = mono_varlist_sort (cfg, vars, 0);
1023
1024         return vars;
1025 }
1026
1027 /**
1028  * mono_arch_compute_omit_fp:
1029  *
1030  *   Determine whenever the frame pointer can be eliminated.
1031  */
1032 static void
1033 mono_arch_compute_omit_fp (MonoCompile *cfg)
1034 {
1035         MonoMethodSignature *sig;
1036         MonoMethodHeader *header;
1037         int i, locals_size;
1038         CallInfo *cinfo;
1039
1040         if (cfg->arch.omit_fp_computed)
1041                 return;
1042
1043         header = mono_method_get_header (cfg->method);
1044
1045         sig = mono_method_signature (cfg->method);
1046
1047         if (!cfg->arch.cinfo)
1048                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1049         cinfo = cfg->arch.cinfo;
1050
1051         /*
1052          * FIXME: Remove some of the restrictions.
1053          */
1054         cfg->arch.omit_fp = TRUE;
1055         cfg->arch.omit_fp_computed = TRUE;
1056
1057         if (cfg->disable_omit_fp)
1058                 cfg->arch.omit_fp = FALSE;
1059
1060         if (!debug_omit_fp ())
1061                 cfg->arch.omit_fp = FALSE;
1062         /*
1063         if (cfg->method->save_lmf)
1064                 cfg->arch.omit_fp = FALSE;
1065         */
1066         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1067                 cfg->arch.omit_fp = FALSE;
1068         if (header->num_clauses)
1069                 cfg->arch.omit_fp = FALSE;
1070         if (cfg->param_area)
1071                 cfg->arch.omit_fp = FALSE;
1072         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1073                 cfg->arch.omit_fp = FALSE;
1074         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1075                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1076                 cfg->arch.omit_fp = FALSE;
1077         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1078                 ArgInfo *ainfo = &cinfo->args [i];
1079
1080                 if (ainfo->storage == ArgOnStack) {
1081                         /*
1082                          * The stack offset can only be determined when the frame
1083                          * size is known.
1084                          */
1085                         cfg->arch.omit_fp = FALSE;
1086                 }
1087         }
1088
1089         locals_size = 0;
1090         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1091                 MonoInst *ins = cfg->varinfo [i];
1092                 int ialign;
1093
1094                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1095         }
1096 }
1097
1098 GList *
1099 mono_arch_get_global_int_regs (MonoCompile *cfg)
1100 {
1101         GList *regs = NULL;
1102
1103         mono_arch_compute_omit_fp (cfg);
1104
1105         if (cfg->globalra) {
1106                 if (cfg->arch.omit_fp)
1107                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1108
1109                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1110                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1111                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1112                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1113                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1114
1115                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1116                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1117                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1118                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1119                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1120                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1121                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1122                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1123         } else {
1124                 if (cfg->arch.omit_fp)
1125                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1126
1127                 /* We use the callee saved registers for global allocation */
1128                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1129                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1130                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1131                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1132                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1133 #ifdef HOST_WIN32
1134                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1135                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1136 #endif
1137         }
1138
1139         return regs;
1140 }
1141
1142 GList*
1143 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1144 {
1145         GList *regs = NULL;
1146         int i;
1147
1148         /* All XMM registers */
1149         for (i = 0; i < 16; ++i)
1150                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1151
1152         return regs;
1153 }
1154
1155 GList*
1156 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1157 {
1158         static GList *r = NULL;
1159
1160         if (r == NULL) {
1161                 GList *regs = NULL;
1162
1163                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1164                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1165                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1166                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1167                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1168                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1169
1170                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1171                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1172                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1173                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1174                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1175                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1176                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1177                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1178
1179                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1180         }
1181
1182         return r;
1183 }
1184
1185 GList*
1186 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1187 {
1188         int i;
1189         static GList *r = NULL;
1190
1191         if (r == NULL) {
1192                 GList *regs = NULL;
1193
1194                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1195                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1196
1197                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1198         }
1199
1200         return r;
1201 }
1202
1203 /*
1204  * mono_arch_regalloc_cost:
1205  *
1206  *  Return the cost, in number of memory references, of the action of
1207  * allocating the variable VMV into a register during global register
1208  * allocation.
1209  */
1210 guint32
1211 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1212 {
1213         MonoInst *ins = cfg->varinfo [vmv->idx];
1214
1215         if (cfg->method->save_lmf)
1216                 /* The register is already saved */
1217                 /* substract 1 for the invisible store in the prolog */
1218                 return (ins->opcode == OP_ARG) ? 0 : 1;
1219         else
1220                 /* push+pop */
1221                 return (ins->opcode == OP_ARG) ? 1 : 2;
1222 }
1223
1224 /*
1225  * mono_arch_fill_argument_info:
1226  *
1227  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1228  * of the method.
1229  */
1230 void
1231 mono_arch_fill_argument_info (MonoCompile *cfg)
1232 {
1233         MonoMethodSignature *sig;
1234         MonoMethodHeader *header;
1235         MonoInst *ins;
1236         int i;
1237         CallInfo *cinfo;
1238
1239         header = mono_method_get_header (cfg->method);
1240
1241         sig = mono_method_signature (cfg->method);
1242
1243         cinfo = cfg->arch.cinfo;
1244
1245         /*
1246          * Contrary to mono_arch_allocate_vars (), the information should describe
1247          * where the arguments are at the beginning of the method, not where they can be
1248          * accessed during the execution of the method. The later makes no sense for the
1249          * global register allocator, since a variable can be in more than one location.
1250          */
1251         if (sig->ret->type != MONO_TYPE_VOID) {
1252                 switch (cinfo->ret.storage) {
1253                 case ArgInIReg:
1254                 case ArgInFloatSSEReg:
1255                 case ArgInDoubleSSEReg:
1256                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1257                                 cfg->vret_addr->opcode = OP_REGVAR;
1258                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1259                         }
1260                         else {
1261                                 cfg->ret->opcode = OP_REGVAR;
1262                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1263                         }
1264                         break;
1265                 case ArgValuetypeInReg:
1266                         cfg->ret->opcode = OP_REGOFFSET;
1267                         cfg->ret->inst_basereg = -1;
1268                         cfg->ret->inst_offset = -1;
1269                         break;
1270                 default:
1271                         g_assert_not_reached ();
1272                 }
1273         }
1274
1275         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1276                 ArgInfo *ainfo = &cinfo->args [i];
1277                 MonoType *arg_type;
1278
1279                 ins = cfg->args [i];
1280
1281                 if (sig->hasthis && (i == 0))
1282                         arg_type = &mono_defaults.object_class->byval_arg;
1283                 else
1284                         arg_type = sig->params [i - sig->hasthis];
1285
1286                 switch (ainfo->storage) {
1287                 case ArgInIReg:
1288                 case ArgInFloatSSEReg:
1289                 case ArgInDoubleSSEReg:
1290                         ins->opcode = OP_REGVAR;
1291                         ins->inst_c0 = ainfo->reg;
1292                         break;
1293                 case ArgOnStack:
1294                         ins->opcode = OP_REGOFFSET;
1295                         ins->inst_basereg = -1;
1296                         ins->inst_offset = -1;
1297                         break;
1298                 case ArgValuetypeInReg:
1299                         /* Dummy */
1300                         ins->opcode = OP_NOP;
1301                         break;
1302                 default:
1303                         g_assert_not_reached ();
1304                 }
1305         }
1306 }
1307
1308 void
1309 mono_arch_allocate_vars (MonoCompile *cfg)
1310 {
1311         MonoMethodSignature *sig;
1312         MonoMethodHeader *header;
1313         MonoInst *ins;
1314         int i, offset;
1315         guint32 locals_stack_size, locals_stack_align;
1316         gint32 *offsets;
1317         CallInfo *cinfo;
1318
1319         header = mono_method_get_header (cfg->method);
1320
1321         sig = mono_method_signature (cfg->method);
1322
1323         cinfo = cfg->arch.cinfo;
1324
1325         mono_arch_compute_omit_fp (cfg);
1326
1327         /*
1328          * We use the ABI calling conventions for managed code as well.
1329          * Exception: valuetypes are only sometimes passed or returned in registers.
1330          */
1331
1332         /*
1333          * The stack looks like this:
1334          * <incoming arguments passed on the stack>
1335          * <return value>
1336          * <lmf/caller saved registers>
1337          * <locals>
1338          * <spill area>
1339          * <localloc area>  -> grows dynamically
1340          * <params area>
1341          */
1342
1343         if (cfg->arch.omit_fp) {
1344                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1345                 cfg->frame_reg = AMD64_RSP;
1346                 offset = 0;
1347         } else {
1348                 /* Locals are allocated backwards from %fp */
1349                 cfg->frame_reg = AMD64_RBP;
1350                 offset = 0;
1351         }
1352
1353         if (cfg->method->save_lmf) {
1354                 /* Reserve stack space for saving LMF */
1355                 if (cfg->arch.omit_fp) {
1356                         cfg->arch.lmf_offset = offset;
1357                         offset += sizeof (MonoLMF);
1358                 }
1359                 else {
1360                         offset += sizeof (MonoLMF);
1361                         cfg->arch.lmf_offset = -offset;
1362                 }
1363         } else {
1364                 if (cfg->arch.omit_fp)
1365                         cfg->arch.reg_save_area_offset = offset;
1366                 /* Reserve space for caller saved registers */
1367                 for (i = 0; i < AMD64_NREG; ++i)
1368                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1369                                 offset += sizeof (gpointer);
1370                         }
1371         }
1372
1373         if (sig->ret->type != MONO_TYPE_VOID) {
1374                 switch (cinfo->ret.storage) {
1375                 case ArgInIReg:
1376                 case ArgInFloatSSEReg:
1377                 case ArgInDoubleSSEReg:
1378                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1379                                 if (cfg->globalra) {
1380                                         cfg->vret_addr->opcode = OP_REGVAR;
1381                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1382                                 } else {
1383                                         /* The register is volatile */
1384                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1385                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1386                                         if (cfg->arch.omit_fp) {
1387                                                 cfg->vret_addr->inst_offset = offset;
1388                                                 offset += 8;
1389                                         } else {
1390                                                 offset += 8;
1391                                                 cfg->vret_addr->inst_offset = -offset;
1392                                         }
1393                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1394                                                 printf ("vret_addr =");
1395                                                 mono_print_ins (cfg->vret_addr);
1396                                         }
1397                                 }
1398                         }
1399                         else {
1400                                 cfg->ret->opcode = OP_REGVAR;
1401                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1402                         }
1403                         break;
1404                 case ArgValuetypeInReg:
1405                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1406                         cfg->ret->opcode = OP_REGOFFSET;
1407                         cfg->ret->inst_basereg = cfg->frame_reg;
1408                         if (cfg->arch.omit_fp) {
1409                                 cfg->ret->inst_offset = offset;
1410                                 offset += 16;
1411                         } else {
1412                                 offset += 16;
1413                                 cfg->ret->inst_offset = - offset;
1414                         }
1415                         break;
1416                 default:
1417                         g_assert_not_reached ();
1418                 }
1419                 if (!cfg->globalra)
1420                         cfg->ret->dreg = cfg->ret->inst_c0;
1421         }
1422
1423         /* Allocate locals */
1424         if (!cfg->globalra) {
1425                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1426                 if (locals_stack_align) {
1427                         offset += (locals_stack_align - 1);
1428                         offset &= ~(locals_stack_align - 1);
1429                 }
1430                 if (cfg->arch.omit_fp) {
1431                         cfg->locals_min_stack_offset = offset;
1432                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1433                 } else {
1434                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1435                         cfg->locals_max_stack_offset = - offset;
1436                 }
1437
1438                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1439                         if (offsets [i] != -1) {
1440                                 MonoInst *ins = cfg->varinfo [i];
1441                                 ins->opcode = OP_REGOFFSET;
1442                                 ins->inst_basereg = cfg->frame_reg;
1443                                 if (cfg->arch.omit_fp)
1444                                         ins->inst_offset = (offset + offsets [i]);
1445                                 else
1446                                         ins->inst_offset = - (offset + offsets [i]);
1447                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1448                         }
1449                 }
1450                 offset += locals_stack_size;
1451         }
1452
1453         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1454                 g_assert (!cfg->arch.omit_fp);
1455                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1456                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1457         }
1458
1459         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1460                 ins = cfg->args [i];
1461                 if (ins->opcode != OP_REGVAR) {
1462                         ArgInfo *ainfo = &cinfo->args [i];
1463                         gboolean inreg = TRUE;
1464                         MonoType *arg_type;
1465
1466                         if (sig->hasthis && (i == 0))
1467                                 arg_type = &mono_defaults.object_class->byval_arg;
1468                         else
1469                                 arg_type = sig->params [i - sig->hasthis];
1470
1471                         if (cfg->globalra) {
1472                                 /* The new allocator needs info about the original locations of the arguments */
1473                                 switch (ainfo->storage) {
1474                                 case ArgInIReg:
1475                                 case ArgInFloatSSEReg:
1476                                 case ArgInDoubleSSEReg:
1477                                         ins->opcode = OP_REGVAR;
1478                                         ins->inst_c0 = ainfo->reg;
1479                                         break;
1480                                 case ArgOnStack:
1481                                         g_assert (!cfg->arch.omit_fp);
1482                                         ins->opcode = OP_REGOFFSET;
1483                                         ins->inst_basereg = cfg->frame_reg;
1484                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1485                                         break;
1486                                 case ArgValuetypeInReg:
1487                                         ins->opcode = OP_REGOFFSET;
1488                                         ins->inst_basereg = cfg->frame_reg;
1489                                         /* These arguments are saved to the stack in the prolog */
1490                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1491                                         if (cfg->arch.omit_fp) {
1492                                                 ins->inst_offset = offset;
1493                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1494                                         } else {
1495                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1496                                                 ins->inst_offset = - offset;
1497                                         }
1498                                         break;
1499                                 default:
1500                                         g_assert_not_reached ();
1501                                 }
1502
1503                                 continue;
1504                         }
1505
1506                         /* FIXME: Allocate volatile arguments to registers */
1507                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1508                                 inreg = FALSE;
1509
1510                         /*
1511                          * Under AMD64, all registers used to pass arguments to functions
1512                          * are volatile across calls.
1513                          * FIXME: Optimize this.
1514                          */
1515                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1516                                 inreg = FALSE;
1517
1518                         ins->opcode = OP_REGOFFSET;
1519
1520                         switch (ainfo->storage) {
1521                         case ArgInIReg:
1522                         case ArgInFloatSSEReg:
1523                         case ArgInDoubleSSEReg:
1524                                 if (inreg) {
1525                                         ins->opcode = OP_REGVAR;
1526                                         ins->dreg = ainfo->reg;
1527                                 }
1528                                 break;
1529                         case ArgOnStack:
1530                                 g_assert (!cfg->arch.omit_fp);
1531                                 ins->opcode = OP_REGOFFSET;
1532                                 ins->inst_basereg = cfg->frame_reg;
1533                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1534                                 break;
1535                         case ArgValuetypeInReg:
1536                                 break;
1537                         case ArgValuetypeAddrInIReg: {
1538                                 MonoInst *indir;
1539                                 g_assert (!cfg->arch.omit_fp);
1540
1541                                 MONO_INST_NEW (cfg, indir, 0);
1542                                 indir->opcode = OP_REGOFFSET;
1543                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1544                                         indir->inst_basereg = cfg->frame_reg;
1545                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1546                                         offset += (sizeof (gpointer));
1547                                         indir->inst_offset = - offset;
1548                                 }
1549                                 else {
1550                                         indir->inst_basereg = cfg->frame_reg;
1551                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1552                                 }
1553
1554                                 ins->opcode = OP_VTARG_ADDR;
1555                                 ins->inst_left = indir;
1556
1557                                 break;
1558                         }
1559                         default:
1560                                 NOT_IMPLEMENTED;
1561                         }
1562
1563                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1564                                 ins->opcode = OP_REGOFFSET;
1565                                 ins->inst_basereg = cfg->frame_reg;
1566                                 /* These arguments are saved to the stack in the prolog */
1567                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1568                                 if (cfg->arch.omit_fp) {
1569                                         ins->inst_offset = offset;
1570                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1571                                         // Arguments are yet supported by the stack map creation code
1572                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1573                                 } else {
1574                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1575                                         ins->inst_offset = - offset;
1576                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1577                                 }
1578                         }
1579                 }
1580         }
1581
1582         cfg->stack_offset = offset;
1583 }
1584
1585 void
1586 mono_arch_create_vars (MonoCompile *cfg)
1587 {
1588         MonoMethodSignature *sig;
1589         CallInfo *cinfo;
1590
1591         sig = mono_method_signature (cfg->method);
1592
1593         if (!cfg->arch.cinfo)
1594                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1595         cinfo = cfg->arch.cinfo;
1596
1597         if (cinfo->ret.storage == ArgValuetypeInReg)
1598                 cfg->ret_var_is_local = TRUE;
1599
1600         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1601                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1602                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1603                         printf ("vret_addr = ");
1604                         mono_print_ins (cfg->vret_addr);
1605                 }
1606         }
1607
1608 #ifdef MONO_AMD64_NO_PUSHES
1609         /*
1610          * When this is set, we pass arguments on the stack by moves, and by allocating
1611          * a bigger stack frame, instead of pushes.
1612          * Pushes complicate exception handling because the arguments on the stack have
1613          * to be popped each time a frame is unwound. They also make fp elimination
1614          * impossible.
1615          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1616          * on a new frame which doesn't include a param area.
1617          */
1618         cfg->arch.no_pushes = TRUE;
1619 #endif
1620 }
1621
1622 static void
1623 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1624 {
1625         MonoInst *ins;
1626
1627         switch (storage) {
1628         case ArgInIReg:
1629                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1630                 ins->dreg = mono_alloc_ireg (cfg);
1631                 ins->sreg1 = tree->dreg;
1632                 MONO_ADD_INS (cfg->cbb, ins);
1633                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1634                 break;
1635         case ArgInFloatSSEReg:
1636                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1637                 ins->dreg = mono_alloc_freg (cfg);
1638                 ins->sreg1 = tree->dreg;
1639                 MONO_ADD_INS (cfg->cbb, ins);
1640
1641                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1642                 break;
1643         case ArgInDoubleSSEReg:
1644                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1645                 ins->dreg = mono_alloc_freg (cfg);
1646                 ins->sreg1 = tree->dreg;
1647                 MONO_ADD_INS (cfg->cbb, ins);
1648
1649                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1650
1651                 break;
1652         default:
1653                 g_assert_not_reached ();
1654         }
1655 }
1656
1657 static int
1658 arg_storage_to_load_membase (ArgStorage storage)
1659 {
1660         switch (storage) {
1661         case ArgInIReg:
1662                 return OP_LOAD_MEMBASE;
1663         case ArgInDoubleSSEReg:
1664                 return OP_LOADR8_MEMBASE;
1665         case ArgInFloatSSEReg:
1666                 return OP_LOADR4_MEMBASE;
1667         default:
1668                 g_assert_not_reached ();
1669         }
1670
1671         return -1;
1672 }
1673
1674 static void
1675 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1676 {
1677         MonoInst *arg;
1678         MonoMethodSignature *tmp_sig;
1679         MonoInst *sig_arg;
1680
1681         if (call->tail_call)
1682                 NOT_IMPLEMENTED;
1683
1684         /* FIXME: Add support for signature tokens to AOT */
1685         cfg->disable_aot = TRUE;
1686
1687         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1688
1689         /*
1690          * mono_ArgIterator_Setup assumes the signature cookie is
1691          * passed first and all the arguments which were before it are
1692          * passed on the stack after the signature. So compensate by
1693          * passing a different signature.
1694          */
1695         tmp_sig = mono_metadata_signature_dup (call->signature);
1696         tmp_sig->param_count -= call->signature->sentinelpos;
1697         tmp_sig->sentinelpos = 0;
1698         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1699
1700         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1701         sig_arg->dreg = mono_alloc_ireg (cfg);
1702         sig_arg->inst_p0 = tmp_sig;
1703         MONO_ADD_INS (cfg->cbb, sig_arg);
1704
1705         if (cfg->arch.no_pushes) {
1706                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1707         } else {
1708                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1709                 arg->sreg1 = sig_arg->dreg;
1710                 MONO_ADD_INS (cfg->cbb, arg);
1711         }
1712 }
1713
1714 static inline LLVMArgStorage
1715 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1716 {
1717         switch (storage) {
1718         case ArgInIReg:
1719                 return LLVMArgInIReg;
1720         case ArgNone:
1721                 return LLVMArgNone;
1722         default:
1723                 g_assert_not_reached ();
1724                 return LLVMArgNone;
1725         }
1726 }
1727
1728 #ifdef ENABLE_LLVM
1729 LLVMCallInfo*
1730 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1731 {
1732         int i, n;
1733         CallInfo *cinfo;
1734         ArgInfo *ainfo;
1735         int j;
1736         LLVMCallInfo *linfo;
1737
1738         n = sig->param_count + sig->hasthis;
1739
1740         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1741
1742         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1743
1744         /*
1745          * LLVM always uses the native ABI while we use our own ABI, the
1746          * only difference is the handling of vtypes:
1747          * - we only pass/receive them in registers in some cases, and only
1748          *   in 1 or 2 integer registers.
1749          */
1750         if (cinfo->ret.storage == ArgValuetypeInReg) {
1751                 if (sig->pinvoke) {
1752                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1753                         cfg->disable_llvm = TRUE;
1754                         return linfo;
1755                 }
1756
1757                 linfo->ret.storage = LLVMArgVtypeInReg;
1758                 for (j = 0; j < 2; ++j)
1759                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1760         }
1761
1762         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1763                 /* Vtype returned using a hidden argument */
1764                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1765         }
1766
1767         for (i = 0; i < n; ++i) {
1768                 ainfo = cinfo->args + i;
1769
1770                 linfo->args [i].storage = LLVMArgNone;
1771
1772                 switch (ainfo->storage) {
1773                 case ArgInIReg:
1774                         linfo->args [i].storage = LLVMArgInIReg;
1775                         break;
1776                 case ArgInDoubleSSEReg:
1777                 case ArgInFloatSSEReg:
1778                         linfo->args [i].storage = LLVMArgInFPReg;
1779                         break;
1780                 case ArgOnStack:
1781                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1782                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1783                         } else {
1784                                 linfo->args [i].storage = LLVMArgInIReg;
1785                                 if (!sig->params [i - sig->hasthis]->byref) {
1786                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1787                                                 linfo->args [i].storage = LLVMArgInFPReg;
1788                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1789                                                 linfo->args [i].storage = LLVMArgInFPReg;
1790                                         }
1791                                 }
1792                         }
1793                         break;
1794                 case ArgValuetypeInReg:
1795                         if (sig->pinvoke) {
1796                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1797                                 cfg->disable_llvm = TRUE;
1798                                 return linfo;
1799                         }
1800
1801                         linfo->args [i].storage = LLVMArgVtypeInReg;
1802                         for (j = 0; j < 2; ++j)
1803                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1804                         break;
1805                 default:
1806                         cfg->exception_message = g_strdup ("ainfo->storage");
1807                         cfg->disable_llvm = TRUE;
1808                         break;
1809                 }
1810         }
1811
1812         return linfo;
1813 }
1814 #endif
1815
1816 void
1817 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1818 {
1819         MonoInst *arg, *in;
1820         MonoMethodSignature *sig;
1821         int i, n, stack_size;
1822         CallInfo *cinfo;
1823         ArgInfo *ainfo;
1824
1825         stack_size = 0;
1826
1827         sig = call->signature;
1828         n = sig->param_count + sig->hasthis;
1829
1830         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1831
1832         if (COMPILE_LLVM (cfg)) {
1833                 /* We shouldn't be called in the llvm case */
1834                 cfg->disable_llvm = TRUE;
1835                 return;
1836         }
1837
1838         if (cinfo->need_stack_align) {
1839                 if (!cfg->arch.no_pushes)
1840                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1841         }
1842
1843         /*
1844          * Emit all arguments which are passed on the stack to prevent register
1845          * allocation problems.
1846          */
1847         if (cfg->arch.no_pushes) {
1848                 for (i = 0; i < n; ++i) {
1849                         MonoType *t;
1850                         ainfo = cinfo->args + i;
1851
1852                         in = call->args [i];
1853
1854                         if (sig->hasthis && i == 0)
1855                                 t = &mono_defaults.object_class->byval_arg;
1856                         else
1857                                 t = sig->params [i - sig->hasthis];
1858
1859                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1860                                 if (!t->byref) {
1861                                         if (t->type == MONO_TYPE_R4)
1862                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1863                                         else if (t->type == MONO_TYPE_R8)
1864                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1865                                         else
1866                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1867                                 } else {
1868                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1869                                 }
1870                         }
1871                 }
1872         }
1873
1874         /*
1875          * Emit all parameters passed in registers in non-reverse order for better readability
1876          * and to help the optimization in emit_prolog ().
1877          */
1878         for (i = 0; i < n; ++i) {
1879                 ainfo = cinfo->args + i;
1880
1881                 in = call->args [i];
1882
1883                 if (ainfo->storage == ArgInIReg)
1884                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1885         }
1886
1887         for (i = n - 1; i >= 0; --i) {
1888                 ainfo = cinfo->args + i;
1889
1890                 in = call->args [i];
1891
1892                 switch (ainfo->storage) {
1893                 case ArgInIReg:
1894                         /* Already done */
1895                         break;
1896                 case ArgInFloatSSEReg:
1897                 case ArgInDoubleSSEReg:
1898                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1899                         break;
1900                 case ArgOnStack:
1901                 case ArgValuetypeInReg:
1902                 case ArgValuetypeAddrInIReg:
1903                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1904                                 MonoInst *call_inst = (MonoInst*)call;
1905                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1906                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1907                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1908                                 guint32 align;
1909                                 guint32 size;
1910
1911                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1912                                         size = sizeof (MonoTypedRef);
1913                                         align = sizeof (gpointer);
1914                                 }
1915                                 else {
1916                                         if (sig->pinvoke)
1917                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1918                                         else {
1919                                                 /*
1920                                                  * Other backends use mono_type_stack_size (), but that
1921                                                  * aligns the size to 8, which is larger than the size of
1922                                                  * the source, leading to reads of invalid memory if the
1923                                                  * source is at the end of address space.
1924                                                  */
1925                                                 size = mono_class_value_size (in->klass, &align);
1926                                         }
1927                                 }
1928                                 g_assert (in->klass);
1929
1930                                 if (size > 0) {
1931                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1932                                         arg->sreg1 = in->dreg;
1933                                         arg->klass = in->klass;
1934                                         arg->backend.size = size;
1935                                         arg->inst_p0 = call;
1936                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1937                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1938
1939                                         MONO_ADD_INS (cfg->cbb, arg);
1940                                 }
1941                         } else {
1942                                 if (cfg->arch.no_pushes) {
1943                                         /* Already done */
1944                                 } else {
1945                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1946                                         arg->sreg1 = in->dreg;
1947                                         if (!sig->params [i - sig->hasthis]->byref) {
1948                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1949                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1950                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
1951                                                         arg->inst_destbasereg = X86_ESP;
1952                                                         arg->inst_offset = 0;
1953                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1954                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1955                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
1956                                                         arg->inst_destbasereg = X86_ESP;
1957                                                         arg->inst_offset = 0;
1958                                                 }
1959                                         }
1960                                         MONO_ADD_INS (cfg->cbb, arg);
1961                                 }
1962                         }
1963                         break;
1964                 default:
1965                         g_assert_not_reached ();
1966                 }
1967
1968                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1969                         /* Emit the signature cookie just before the implicit arguments */
1970                         emit_sig_cookie (cfg, call, cinfo);
1971         }
1972
1973         /* Handle the case where there are no implicit arguments */
1974         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1975                 emit_sig_cookie (cfg, call, cinfo);
1976
1977         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1978                 MonoInst *vtarg;
1979
1980                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1981                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1982                                 /*
1983                                  * Tell the JIT to use a more efficient calling convention: call using
1984                                  * OP_CALL, compute the result location after the call, and save the
1985                                  * result there.
1986                                  */
1987                                 call->vret_in_reg = TRUE;
1988                                 /*
1989                                  * Nullify the instruction computing the vret addr to enable
1990                                  * future optimizations.
1991                                  */
1992                                 if (call->vret_var)
1993                                         NULLIFY_INS (call->vret_var);
1994                         } else {
1995                                 if (call->tail_call)
1996                                         NOT_IMPLEMENTED;
1997                                 /*
1998                                  * The valuetype is in RAX:RDX after the call, need to be copied to
1999                                  * the stack. Push the address here, so the call instruction can
2000                                  * access it.
2001                                  */
2002                                 if (!cfg->arch.vret_addr_loc) {
2003                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2004                                         /* Prevent it from being register allocated or optimized away */
2005                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2006                                 }
2007
2008                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2009                         }
2010                 }
2011                 else {
2012                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2013                         vtarg->sreg1 = call->vret_var->dreg;
2014                         vtarg->dreg = mono_alloc_preg (cfg);
2015                         MONO_ADD_INS (cfg->cbb, vtarg);
2016
2017                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2018                 }
2019         }
2020
2021 #ifdef HOST_WIN32
2022         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2023                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2024         }
2025 #endif
2026
2027         if (cfg->method->save_lmf) {
2028                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2029                 MONO_ADD_INS (cfg->cbb, arg);
2030         }
2031
2032         call->stack_usage = cinfo->stack_usage;
2033 }
2034
2035 void
2036 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2037 {
2038         MonoInst *arg;
2039         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2040         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2041         int size = ins->backend.size;
2042
2043         if (ainfo->storage == ArgValuetypeInReg) {
2044                 MonoInst *load;
2045                 int part;
2046
2047                 for (part = 0; part < 2; ++part) {
2048                         if (ainfo->pair_storage [part] == ArgNone)
2049                                 continue;
2050
2051                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2052                         load->inst_basereg = src->dreg;
2053                         load->inst_offset = part * sizeof (gpointer);
2054
2055                         switch (ainfo->pair_storage [part]) {
2056                         case ArgInIReg:
2057                                 load->dreg = mono_alloc_ireg (cfg);
2058                                 break;
2059                         case ArgInDoubleSSEReg:
2060                         case ArgInFloatSSEReg:
2061                                 load->dreg = mono_alloc_freg (cfg);
2062                                 break;
2063                         default:
2064                                 g_assert_not_reached ();
2065                         }
2066                         MONO_ADD_INS (cfg->cbb, load);
2067
2068                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2069                 }
2070         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2071                 MonoInst *vtaddr, *load;
2072                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2073
2074                 g_assert (!cfg->arch.no_pushes);
2075
2076                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2077                 load->inst_p0 = vtaddr;
2078                 vtaddr->flags |= MONO_INST_INDIRECT;
2079                 load->type = STACK_MP;
2080                 load->klass = vtaddr->klass;
2081                 load->dreg = mono_alloc_ireg (cfg);
2082                 MONO_ADD_INS (cfg->cbb, load);
2083                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2084
2085                 if (ainfo->pair_storage [0] == ArgInIReg) {
2086                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2087                         arg->dreg = mono_alloc_ireg (cfg);
2088                         arg->sreg1 = load->dreg;
2089                         arg->inst_imm = 0;
2090                         MONO_ADD_INS (cfg->cbb, arg);
2091                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2092                 } else {
2093                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2094                         arg->sreg1 = load->dreg;
2095                         MONO_ADD_INS (cfg->cbb, arg);
2096                 }
2097         } else {
2098                 if (size == 8) {
2099                         if (cfg->arch.no_pushes) {
2100                                 int dreg = mono_alloc_ireg (cfg);
2101
2102                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2103                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2104                         } else {
2105                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2106                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2107                                 arg->inst_basereg = src->dreg;
2108                                 arg->inst_offset = 0;
2109                                 MONO_ADD_INS (cfg->cbb, arg);
2110                         }
2111                 } else if (size <= 40) {
2112                         if (cfg->arch.no_pushes) {
2113                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2114                         } else {
2115                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2116                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2117                         }
2118                 } else {
2119                         if (cfg->arch.no_pushes) {
2120                                 // FIXME: Code growth
2121                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2122                         } else {
2123                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2124                                 arg->inst_basereg = src->dreg;
2125                                 arg->inst_offset = 0;
2126                                 arg->inst_imm = size;
2127                                 MONO_ADD_INS (cfg->cbb, arg);
2128                         }
2129                 }
2130         }
2131 }
2132
2133 void
2134 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2135 {
2136         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2137
2138         if (!ret->byref) {
2139                 if (ret->type == MONO_TYPE_R4) {
2140                         if (COMPILE_LLVM (cfg))
2141                                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2142                         else
2143                                 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2144                         return;
2145                 } else if (ret->type == MONO_TYPE_R8) {
2146                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2147                         return;
2148                 }
2149         }
2150
2151         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2152 }
2153
2154 #define EMIT_COND_BRANCH(ins,cond,sign) \
2155         if (ins->inst_true_bb->native_offset) { \
2156                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2157         } else { \
2158                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2159                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2160             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2161                         x86_branch8 (code, cond, 0, sign); \
2162                 else \
2163                         x86_branch32 (code, cond, 0, sign); \
2164 }
2165
2166 typedef struct {
2167         MonoMethodSignature *sig;
2168         CallInfo *cinfo;
2169 } ArchDynCallInfo;
2170
2171 typedef struct {
2172         mgreg_t regs [PARAM_REGS];
2173         mgreg_t res;
2174         guint8 *ret;
2175 } DynCallArgs;
2176
2177 static gboolean
2178 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2179 {
2180         int i;
2181
2182 #ifdef HOST_WIN32
2183         return FALSE;
2184 #endif
2185
2186         switch (cinfo->ret.storage) {
2187         case ArgNone:
2188         case ArgInIReg:
2189                 break;
2190         case ArgValuetypeInReg: {
2191                 ArgInfo *ainfo = &cinfo->ret;
2192
2193                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2194                         return FALSE;
2195                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2196                         return FALSE;
2197                 break;
2198         }
2199         default:
2200                 return FALSE;
2201         }
2202
2203         for (i = 0; i < cinfo->nargs; ++i) {
2204                 ArgInfo *ainfo = &cinfo->args [i];
2205                 switch (ainfo->storage) {
2206                 case ArgInIReg:
2207                         break;
2208                 case ArgValuetypeInReg:
2209                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2210                                 return FALSE;
2211                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2212                                 return FALSE;
2213                         break;
2214                 default:
2215                         return FALSE;
2216                 }
2217         }
2218
2219         return TRUE;
2220 }
2221
2222 /*
2223  * mono_arch_dyn_call_prepare:
2224  *
2225  *   Return a pointer to an arch-specific structure which contains information
2226  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2227  * supported for SIG.
2228  * This function is equivalent to ffi_prep_cif in libffi.
2229  */
2230 MonoDynCallInfo*
2231 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2232 {
2233         ArchDynCallInfo *info;
2234         CallInfo *cinfo;
2235
2236         cinfo = get_call_info (NULL, NULL, sig, FALSE);
2237
2238         if (!dyn_call_supported (sig, cinfo)) {
2239                 g_free (cinfo);
2240                 return NULL;
2241         }
2242
2243         info = g_new0 (ArchDynCallInfo, 1);
2244         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2245         info->sig = sig;
2246         info->cinfo = cinfo;
2247
2248         return (MonoDynCallInfo*)info;
2249 }
2250
2251 /*
2252  * mono_arch_dyn_call_free:
2253  *
2254  *   Free a MonoDynCallInfo structure.
2255  */
2256 void
2257 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2258 {
2259         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2260
2261         g_free (ainfo->cinfo);
2262         g_free (ainfo);
2263 }
2264
2265 /*
2266  * mono_arch_get_start_dyn_call:
2267  *
2268  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2269  * store the result into BUF.
2270  * ARGS should be an array of pointers pointing to the arguments.
2271  * RET should point to a memory buffer large enought to hold the result of the
2272  * call.
2273  * This function should be as fast as possible, any work which does not depend
2274  * on the actual values of the arguments should be done in
2275  * mono_arch_dyn_call_prepare ().
2276  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2277  * libffi.
2278  */
2279 void
2280 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2281 {
2282         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2283         DynCallArgs *p = (DynCallArgs*)buf;
2284         int arg_index, greg, i;
2285         MonoMethodSignature *sig = dinfo->sig;
2286
2287         g_assert (buf_len >= sizeof (DynCallArgs));
2288
2289         p->res = 0;
2290         p->ret = ret;
2291
2292         arg_index = 0;
2293         greg = 0;
2294
2295         if (dinfo->cinfo->vtype_retaddr)
2296                 p->regs [greg ++] = (mgreg_t)ret;
2297
2298         if (sig->hasthis) {
2299                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2300         }
2301
2302         for (i = 0; i < sig->param_count; i++) {
2303                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2304                 gpointer *arg = args [arg_index ++];
2305
2306                 if (t->byref) {
2307                         p->regs [greg ++] = (mgreg_t)*(arg);
2308                         continue;
2309                 }
2310
2311                 switch (t->type) {
2312                 case MONO_TYPE_STRING:
2313                 case MONO_TYPE_CLASS:
2314                 case MONO_TYPE_ARRAY:
2315                 case MONO_TYPE_SZARRAY:
2316                 case MONO_TYPE_OBJECT:
2317                 case MONO_TYPE_PTR:
2318                 case MONO_TYPE_I:
2319                 case MONO_TYPE_U:
2320                 case MONO_TYPE_I8:
2321                 case MONO_TYPE_U8:
2322                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2323                         p->regs [greg ++] = (mgreg_t)*(arg);
2324                         break;
2325                 case MONO_TYPE_BOOLEAN:
2326                 case MONO_TYPE_U1:
2327                         p->regs [greg ++] = *(guint8*)(arg);
2328                         break;
2329                 case MONO_TYPE_I1:
2330                         p->regs [greg ++] = *(gint8*)(arg);
2331                         break;
2332                 case MONO_TYPE_I2:
2333                         p->regs [greg ++] = *(gint16*)(arg);
2334                         break;
2335                 case MONO_TYPE_U2:
2336                 case MONO_TYPE_CHAR:
2337                         p->regs [greg ++] = *(guint16*)(arg);
2338                         break;
2339                 case MONO_TYPE_I4:
2340                         p->regs [greg ++] = *(gint32*)(arg);
2341                         break;
2342                 case MONO_TYPE_U4:
2343                         p->regs [greg ++] = *(guint32*)(arg);
2344                         break;
2345                 case MONO_TYPE_GENERICINST:
2346                     if (MONO_TYPE_IS_REFERENCE (t)) {
2347                                 p->regs [greg ++] = (mgreg_t)*(arg);
2348                                 break;
2349                         } else {
2350                                 /* Fall through */
2351                         }
2352                 case MONO_TYPE_VALUETYPE: {
2353                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2354
2355                         g_assert (ainfo->storage == ArgValuetypeInReg);
2356                         if (ainfo->pair_storage [0] != ArgNone) {
2357                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2358                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2359                         }
2360                         if (ainfo->pair_storage [1] != ArgNone) {
2361                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2362                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2363                         }
2364                         break;
2365                 }
2366                 default:
2367                         g_assert_not_reached ();
2368                 }
2369         }
2370
2371         g_assert (greg <= PARAM_REGS);
2372 }
2373
2374 /*
2375  * mono_arch_finish_dyn_call:
2376  *
2377  *   Store the result of a dyn call into the return value buffer passed to
2378  * start_dyn_call ().
2379  * This function should be as fast as possible, any work which does not depend
2380  * on the actual values of the arguments should be done in
2381  * mono_arch_dyn_call_prepare ().
2382  */
2383 void
2384 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2385 {
2386         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2387         MonoMethodSignature *sig = dinfo->sig;
2388         guint8 *ret = ((DynCallArgs*)buf)->ret;
2389         mgreg_t res = ((DynCallArgs*)buf)->res;
2390
2391         switch (mono_type_get_underlying_type (sig->ret)->type) {
2392         case MONO_TYPE_VOID:
2393                 *(gpointer*)ret = NULL;
2394                 break;
2395         case MONO_TYPE_STRING:
2396         case MONO_TYPE_CLASS:
2397         case MONO_TYPE_ARRAY:
2398         case MONO_TYPE_SZARRAY:
2399         case MONO_TYPE_OBJECT:
2400         case MONO_TYPE_I:
2401         case MONO_TYPE_U:
2402         case MONO_TYPE_PTR:
2403                 *(gpointer*)ret = (gpointer)res;
2404                 break;
2405         case MONO_TYPE_I1:
2406                 *(gint8*)ret = res;
2407                 break;
2408         case MONO_TYPE_U1:
2409         case MONO_TYPE_BOOLEAN:
2410                 *(guint8*)ret = res;
2411                 break;
2412         case MONO_TYPE_I2:
2413                 *(gint16*)ret = res;
2414                 break;
2415         case MONO_TYPE_U2:
2416         case MONO_TYPE_CHAR:
2417                 *(guint16*)ret = res;
2418                 break;
2419         case MONO_TYPE_I4:
2420                 *(gint32*)ret = res;
2421                 break;
2422         case MONO_TYPE_U4:
2423                 *(guint32*)ret = res;
2424                 break;
2425         case MONO_TYPE_I8:
2426                 *(gint64*)ret = res;
2427                 break;
2428         case MONO_TYPE_U8:
2429                 *(guint64*)ret = res;
2430                 break;
2431         case MONO_TYPE_GENERICINST:
2432                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2433                         *(gpointer*)ret = (gpointer)res;
2434                         break;
2435                 } else {
2436                         /* Fall through */
2437                 }
2438         case MONO_TYPE_VALUETYPE:
2439                 if (dinfo->cinfo->vtype_retaddr) {
2440                         /* Nothing to do */
2441                 } else {
2442                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2443
2444                         g_assert (ainfo->storage == ArgValuetypeInReg);
2445
2446                         if (ainfo->pair_storage [0] != ArgNone) {
2447                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2448                                 ((mgreg_t*)ret)[0] = res;
2449                         }
2450
2451                         g_assert (ainfo->pair_storage [1] == ArgNone);
2452                 }
2453                 break;
2454         default:
2455                 g_assert_not_reached ();
2456         }
2457 }
2458
2459 /* emit an exception if condition is fail */
2460 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2461         do {                                                        \
2462                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2463                 if (tins == NULL) {                                                                             \
2464                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2465                                         MONO_PATCH_INFO_EXC, exc_name);  \
2466                         x86_branch32 (code, cond, 0, signed);               \
2467                 } else {        \
2468                         EMIT_COND_BRANCH (tins, cond, signed);  \
2469                 }                       \
2470         } while (0);
2471
2472 #define EMIT_FPCOMPARE(code) do { \
2473         amd64_fcompp (code); \
2474         amd64_fnstsw (code); \
2475 } while (0);
2476
2477 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2478     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2479         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2480         amd64_ ##op (code); \
2481         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2482         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2483 } while (0);
2484
2485 static guint8*
2486 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2487 {
2488         gboolean no_patch = FALSE;
2489
2490         /*
2491          * FIXME: Add support for thunks
2492          */
2493         {
2494                 gboolean near_call = FALSE;
2495
2496                 /*
2497                  * Indirect calls are expensive so try to make a near call if possible.
2498                  * The caller memory is allocated by the code manager so it is
2499                  * guaranteed to be at a 32 bit offset.
2500                  */
2501
2502                 if (patch_type != MONO_PATCH_INFO_ABS) {
2503                         /* The target is in memory allocated using the code manager */
2504                         near_call = TRUE;
2505
2506                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2507                                 if (((MonoMethod*)data)->klass->image->aot_module)
2508                                         /* The callee might be an AOT method */
2509                                         near_call = FALSE;
2510                                 if (((MonoMethod*)data)->dynamic)
2511                                         /* The target is in malloc-ed memory */
2512                                         near_call = FALSE;
2513                         }
2514
2515                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2516                                 /*
2517                                  * The call might go directly to a native function without
2518                                  * the wrapper.
2519                                  */
2520                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2521                                 if (mi) {
2522                                         gconstpointer target = mono_icall_get_wrapper (mi);
2523                                         if ((((guint64)target) >> 32) != 0)
2524                                                 near_call = FALSE;
2525                                 }
2526                         }
2527                 }
2528                 else {
2529                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2530                                 /*
2531                                  * This is not really an optimization, but required because the
2532                                  * generic class init trampolines use R11 to pass the vtable.
2533                                  */
2534                                 near_call = TRUE;
2535                         } else {
2536                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2537                                 if (info) {
2538                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2539                                                 strstr (cfg->method->name, info->name)) {
2540                                                 /* A call to the wrapped function */
2541                                                 if ((((guint64)data) >> 32) == 0)
2542                                                         near_call = TRUE;
2543                                                 no_patch = TRUE;
2544                                         }
2545                                         else if (info->func == info->wrapper) {
2546                                                 /* No wrapper */
2547                                                 if ((((guint64)info->func) >> 32) == 0)
2548                                                         near_call = TRUE;
2549                                         }
2550                                         else {
2551                                                 /* See the comment in mono_codegen () */
2552                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2553                                                         near_call = TRUE;
2554                                         }
2555                                 }
2556                                 else if ((((guint64)data) >> 32) == 0) {
2557                                         near_call = TRUE;
2558                                         no_patch = TRUE;
2559                                 }
2560                         }
2561                 }
2562
2563                 if (cfg->method->dynamic)
2564                         /* These methods are allocated using malloc */
2565                         near_call = FALSE;
2566
2567                 if (cfg->compile_aot) {
2568                         near_call = TRUE;
2569                         no_patch = TRUE;
2570                 }
2571
2572 #ifdef MONO_ARCH_NOMAP32BIT
2573                 near_call = FALSE;
2574 #endif
2575
2576                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2577                 if (optimize_for_xen)
2578                         near_call = FALSE;
2579
2580                 if (near_call) {
2581                         /*
2582                          * Align the call displacement to an address divisible by 4 so it does
2583                          * not span cache lines. This is required for code patching to work on SMP
2584                          * systems.
2585                          */
2586                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2587                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2588                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2589                         amd64_call_code (code, 0);
2590                 }
2591                 else {
2592                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2593                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2594                         amd64_call_reg (code, GP_SCRATCH_REG);
2595                 }
2596         }
2597
2598         return code;
2599 }
2600
2601 static inline guint8*
2602 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2603 {
2604 #ifdef HOST_WIN32
2605         if (win64_adjust_stack)
2606                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2607 #endif
2608         code = emit_call_body (cfg, code, patch_type, data);
2609 #ifdef HOST_WIN32
2610         if (win64_adjust_stack)
2611                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2612 #endif
2613
2614         return code;
2615 }
2616
2617 static inline int
2618 store_membase_imm_to_store_membase_reg (int opcode)
2619 {
2620         switch (opcode) {
2621         case OP_STORE_MEMBASE_IMM:
2622                 return OP_STORE_MEMBASE_REG;
2623         case OP_STOREI4_MEMBASE_IMM:
2624                 return OP_STOREI4_MEMBASE_REG;
2625         case OP_STOREI8_MEMBASE_IMM:
2626                 return OP_STOREI8_MEMBASE_REG;
2627         }
2628
2629         return -1;
2630 }
2631
2632 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2633
2634 /*
2635  * mono_arch_peephole_pass_1:
2636  *
2637  *   Perform peephole opts which should/can be performed before local regalloc
2638  */
2639 void
2640 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2641 {
2642         MonoInst *ins, *n;
2643
2644         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2645                 MonoInst *last_ins = ins->prev;
2646
2647                 switch (ins->opcode) {
2648                 case OP_ADD_IMM:
2649                 case OP_IADD_IMM:
2650                 case OP_LADD_IMM:
2651                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2652                                 /*
2653                                  * X86_LEA is like ADD, but doesn't have the
2654                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2655                                  * its operand to 64 bit.
2656                                  */
2657                                 ins->opcode = OP_X86_LEA_MEMBASE;
2658                                 ins->inst_basereg = ins->sreg1;
2659                         }
2660                         break;
2661                 case OP_LXOR:
2662                 case OP_IXOR:
2663                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2664                                 MonoInst *ins2;
2665
2666                                 /*
2667                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2668                                  * the latter has length 2-3 instead of 6 (reverse constant
2669                                  * propagation). These instruction sequences are very common
2670                                  * in the initlocals bblock.
2671                                  */
2672                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2673                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2674                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2675                                                 ins2->sreg1 = ins->dreg;
2676                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2677                                                 /* Continue */
2678                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2679                                                 NULLIFY_INS (ins2);
2680                                                 /* Continue */
2681                                         } else {
2682                                                 break;
2683                                         }
2684                                 }
2685                         }
2686                         break;
2687                 case OP_COMPARE_IMM:
2688                 case OP_LCOMPARE_IMM:
2689                         /* OP_COMPARE_IMM (reg, 0)
2690                          * -->
2691                          * OP_AMD64_TEST_NULL (reg)
2692                          */
2693                         if (!ins->inst_imm)
2694                                 ins->opcode = OP_AMD64_TEST_NULL;
2695                         break;
2696                 case OP_ICOMPARE_IMM:
2697                         if (!ins->inst_imm)
2698                                 ins->opcode = OP_X86_TEST_NULL;
2699                         break;
2700                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2701                         /*
2702                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2703                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2704                          * -->
2705                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2706                          * OP_COMPARE_IMM reg, imm
2707                          *
2708                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2709                          */
2710                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2711                             ins->inst_basereg == last_ins->inst_destbasereg &&
2712                             ins->inst_offset == last_ins->inst_offset) {
2713                                         ins->opcode = OP_ICOMPARE_IMM;
2714                                         ins->sreg1 = last_ins->sreg1;
2715
2716                                         /* check if we can remove cmp reg,0 with test null */
2717                                         if (!ins->inst_imm)
2718                                                 ins->opcode = OP_X86_TEST_NULL;
2719                                 }
2720
2721                         break;
2722                 }
2723
2724                 mono_peephole_ins (bb, ins);
2725         }
2726 }
2727
2728 void
2729 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2730 {
2731         MonoInst *ins, *n;
2732
2733         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2734                 switch (ins->opcode) {
2735                 case OP_ICONST:
2736                 case OP_I8CONST: {
2737                         /* reg = 0 -> XOR (reg, reg) */
2738                         /* XOR sets cflags on x86, so we cant do it always */
2739                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2740                                 ins->opcode = OP_LXOR;
2741                                 ins->sreg1 = ins->dreg;
2742                                 ins->sreg2 = ins->dreg;
2743                                 /* Fall through */
2744                         } else {
2745                                 break;
2746                         }
2747                 }
2748                 case OP_LXOR:
2749                         /*
2750                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2751                          * 0 result into 64 bits.
2752                          */
2753                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2754                                 ins->opcode = OP_IXOR;
2755                         }
2756                         /* Fall through */
2757                 case OP_IXOR:
2758                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2759                                 MonoInst *ins2;
2760
2761                                 /*
2762                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2763                                  * the latter has length 2-3 instead of 6 (reverse constant
2764                                  * propagation). These instruction sequences are very common
2765                                  * in the initlocals bblock.
2766                                  */
2767                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2768                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2769                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2770                                                 ins2->sreg1 = ins->dreg;
2771                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2772                                                 /* Continue */
2773                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2774                                                 NULLIFY_INS (ins2);
2775                                                 /* Continue */
2776                                         } else {
2777                                                 break;
2778                                         }
2779                                 }
2780                         }
2781                         break;
2782                 case OP_IADD_IMM:
2783                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2784                                 ins->opcode = OP_X86_INC_REG;
2785                         break;
2786                 case OP_ISUB_IMM:
2787                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2788                                 ins->opcode = OP_X86_DEC_REG;
2789                         break;
2790                 }
2791
2792                 mono_peephole_ins (bb, ins);
2793         }
2794 }
2795
2796 #define NEW_INS(cfg,ins,dest,op) do {   \
2797                 MONO_INST_NEW ((cfg), (dest), (op)); \
2798         (dest)->cil_code = (ins)->cil_code; \
2799         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2800         } while (0)
2801
2802 /*
2803  * mono_arch_lowering_pass:
2804  *
2805  *  Converts complex opcodes into simpler ones so that each IR instruction
2806  * corresponds to one machine instruction.
2807  */
2808 void
2809 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2810 {
2811         MonoInst *ins, *n, *temp;
2812
2813         /*
2814          * FIXME: Need to add more instructions, but the current machine
2815          * description can't model some parts of the composite instructions like
2816          * cdq.
2817          */
2818         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2819                 switch (ins->opcode) {
2820                 case OP_DIV_IMM:
2821                 case OP_REM_IMM:
2822                 case OP_IDIV_IMM:
2823                 case OP_IDIV_UN_IMM:
2824                 case OP_IREM_UN_IMM:
2825                         mono_decompose_op_imm (cfg, bb, ins);
2826                         break;
2827                 case OP_IREM_IMM:
2828                         /* Keep the opcode if we can implement it efficiently */
2829                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2830                                 mono_decompose_op_imm (cfg, bb, ins);
2831                         break;
2832                 case OP_COMPARE_IMM:
2833                 case OP_LCOMPARE_IMM:
2834                         if (!amd64_is_imm32 (ins->inst_imm)) {
2835                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2836                                 temp->inst_c0 = ins->inst_imm;
2837                                 temp->dreg = mono_alloc_ireg (cfg);
2838                                 ins->opcode = OP_COMPARE;
2839                                 ins->sreg2 = temp->dreg;
2840                         }
2841                         break;
2842                 case OP_LOAD_MEMBASE:
2843                 case OP_LOADI8_MEMBASE:
2844                         if (!amd64_is_imm32 (ins->inst_offset)) {
2845                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2846                                 temp->inst_c0 = ins->inst_offset;
2847                                 temp->dreg = mono_alloc_ireg (cfg);
2848                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2849                                 ins->inst_indexreg = temp->dreg;
2850                         }
2851                         break;
2852                 case OP_STORE_MEMBASE_IMM:
2853                 case OP_STOREI8_MEMBASE_IMM:
2854                         if (!amd64_is_imm32 (ins->inst_imm)) {
2855                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2856                                 temp->inst_c0 = ins->inst_imm;
2857                                 temp->dreg = mono_alloc_ireg (cfg);
2858                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2859                                 ins->sreg1 = temp->dreg;
2860                         }
2861                         break;
2862 #ifdef MONO_ARCH_SIMD_INTRINSICS
2863                 case OP_EXPAND_I1: {
2864                                 int temp_reg1 = mono_alloc_ireg (cfg);
2865                                 int temp_reg2 = mono_alloc_ireg (cfg);
2866                                 int original_reg = ins->sreg1;
2867
2868                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2869                                 temp->sreg1 = original_reg;
2870                                 temp->dreg = temp_reg1;
2871
2872                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2873                                 temp->sreg1 = temp_reg1;
2874                                 temp->dreg = temp_reg2;
2875                                 temp->inst_imm = 8;
2876
2877                                 NEW_INS (cfg, ins, temp, OP_LOR);
2878                                 temp->sreg1 = temp->dreg = temp_reg2;
2879                                 temp->sreg2 = temp_reg1;
2880
2881                                 ins->opcode = OP_EXPAND_I2;
2882                                 ins->sreg1 = temp_reg2;
2883                         }
2884                         break;
2885 #endif
2886                 default:
2887                         break;
2888                 }
2889         }
2890
2891         bb->max_vreg = cfg->next_vreg;
2892 }
2893
2894 static const int
2895 branch_cc_table [] = {
2896         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2897         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2898         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2899 };
2900
2901 /* Maps CMP_... constants to X86_CC_... constants */
2902 static const int
2903 cc_table [] = {
2904         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2905         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2906 };
2907
2908 static const int
2909 cc_signed_table [] = {
2910         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2911         FALSE, FALSE, FALSE, FALSE
2912 };
2913
2914 /*#include "cprop.c"*/
2915
2916 static unsigned char*
2917 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2918 {
2919         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2920
2921         if (size == 1)
2922                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2923         else if (size == 2)
2924                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2925         return code;
2926 }
2927
2928 static unsigned char*
2929 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2930 {
2931         int sreg = tree->sreg1;
2932         int need_touch = FALSE;
2933
2934 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2935         if (!tree->flags & MONO_INST_INIT)
2936                 need_touch = TRUE;
2937 #endif
2938
2939         if (need_touch) {
2940                 guint8* br[5];
2941
2942                 /*
2943                  * Under Windows:
2944                  * If requested stack size is larger than one page,
2945                  * perform stack-touch operation
2946                  */
2947                 /*
2948                  * Generate stack probe code.
2949                  * Under Windows, it is necessary to allocate one page at a time,
2950                  * "touching" stack after each successful sub-allocation. This is
2951                  * because of the way stack growth is implemented - there is a
2952                  * guard page before the lowest stack page that is currently commited.
2953                  * Stack normally grows sequentially so OS traps access to the
2954                  * guard page and commits more pages when needed.
2955                  */
2956                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2957                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2958
2959                 br[2] = code; /* loop */
2960                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2961                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2962                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2963                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2964                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2965                 amd64_patch (br[3], br[2]);
2966                 amd64_test_reg_reg (code, sreg, sreg);
2967                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2968                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2969
2970                 br[1] = code; x86_jump8 (code, 0);
2971
2972                 amd64_patch (br[0], code);
2973                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2974                 amd64_patch (br[1], code);
2975                 amd64_patch (br[4], code);
2976         }
2977         else
2978                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2979
2980         if (tree->flags & MONO_INST_INIT) {
2981                 int offset = 0;
2982                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2983                         amd64_push_reg (code, AMD64_RAX);
2984                         offset += 8;
2985                 }
2986                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2987                         amd64_push_reg (code, AMD64_RCX);
2988                         offset += 8;
2989                 }
2990                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2991                         amd64_push_reg (code, AMD64_RDI);
2992                         offset += 8;
2993                 }
2994
2995                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2996                 if (sreg != AMD64_RCX)
2997                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2998                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2999
3000                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3001                 if (cfg->param_area && cfg->arch.no_pushes)
3002                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3003                 amd64_cld (code);
3004                 amd64_prefix (code, X86_REP_PREFIX);
3005                 amd64_stosl (code);
3006
3007                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3008                         amd64_pop_reg (code, AMD64_RDI);
3009                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3010                         amd64_pop_reg (code, AMD64_RCX);
3011                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3012                         amd64_pop_reg (code, AMD64_RAX);
3013         }
3014         return code;
3015 }
3016
3017 static guint8*
3018 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3019 {
3020         CallInfo *cinfo;
3021         guint32 quad;
3022
3023         /* Move return value to the target register */
3024         /* FIXME: do this in the local reg allocator */
3025         switch (ins->opcode) {
3026         case OP_CALL:
3027         case OP_CALL_REG:
3028         case OP_CALL_MEMBASE:
3029         case OP_LCALL:
3030         case OP_LCALL_REG:
3031         case OP_LCALL_MEMBASE:
3032                 g_assert (ins->dreg == AMD64_RAX);
3033                 break;
3034         case OP_FCALL:
3035         case OP_FCALL_REG:
3036         case OP_FCALL_MEMBASE:
3037                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3038                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3039                 }
3040                 else {
3041                         if (ins->dreg != AMD64_XMM0)
3042                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3043                 }
3044                 break;
3045         case OP_VCALL:
3046         case OP_VCALL_REG:
3047         case OP_VCALL_MEMBASE:
3048         case OP_VCALL2:
3049         case OP_VCALL2_REG:
3050         case OP_VCALL2_MEMBASE:
3051                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3052                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3053                         MonoInst *loc = cfg->arch.vret_addr_loc;
3054
3055                         /* Load the destination address */
3056                         g_assert (loc->opcode == OP_REGOFFSET);
3057                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3058
3059                         for (quad = 0; quad < 2; quad ++) {
3060                                 switch (cinfo->ret.pair_storage [quad]) {
3061                                 case ArgInIReg:
3062                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3063                                         break;
3064                                 case ArgInFloatSSEReg:
3065                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3066                                         break;
3067                                 case ArgInDoubleSSEReg:
3068                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3069                                         break;
3070                                 case ArgNone:
3071                                         break;
3072                                 default:
3073                                         NOT_IMPLEMENTED;
3074                                 }
3075                         }
3076                 }
3077                 break;
3078         }
3079
3080         return code;
3081 }
3082
3083 /*
3084  * mono_amd64_emit_tls_get:
3085  * @code: buffer to store code to
3086  * @dreg: hard register where to place the result
3087  * @tls_offset: offset info
3088  *
3089  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3090  * the dreg register the item in the thread local storage identified
3091  * by tls_offset.
3092  *
3093  * Returns: a pointer to the end of the stored code
3094  */
3095 guint8*
3096 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3097 {
3098 #ifdef HOST_WIN32
3099         g_assert (tls_offset < 64);
3100         x86_prefix (code, X86_GS_PREFIX);
3101         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3102 #else
3103         if (optimize_for_xen) {
3104                 x86_prefix (code, X86_FS_PREFIX);
3105                 amd64_mov_reg_mem (code, dreg, 0, 8);
3106                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3107         } else {
3108                 x86_prefix (code, X86_FS_PREFIX);
3109                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3110         }
3111 #endif
3112         return code;
3113 }
3114
3115 #define REAL_PRINT_REG(text,reg) \
3116 mono_assert (reg >= 0); \
3117 amd64_push_reg (code, AMD64_RAX); \
3118 amd64_push_reg (code, AMD64_RDX); \
3119 amd64_push_reg (code, AMD64_RCX); \
3120 amd64_push_reg (code, reg); \
3121 amd64_push_imm (code, reg); \
3122 amd64_push_imm (code, text " %d %p\n"); \
3123 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3124 amd64_call_reg (code, AMD64_RAX); \
3125 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3126 amd64_pop_reg (code, AMD64_RCX); \
3127 amd64_pop_reg (code, AMD64_RDX); \
3128 amd64_pop_reg (code, AMD64_RAX);
3129
3130 /* benchmark and set based on cpu */
3131 #define LOOP_ALIGNMENT 8
3132 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3133
3134 #ifndef DISABLE_JIT
3135
3136 void
3137 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3138 {
3139         MonoInst *ins;
3140         MonoCallInst *call;
3141         guint offset;
3142         guint8 *code = cfg->native_code + cfg->code_len;
3143         MonoInst *last_ins = NULL;
3144         guint last_offset = 0;
3145         int max_len;
3146
3147         /* Fix max_offset estimate for each successor bb */
3148         if (cfg->opt & MONO_OPT_BRANCH) {
3149                 int current_offset = cfg->code_len;
3150                 MonoBasicBlock *current_bb;
3151                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3152                         current_bb->max_offset = current_offset;
3153                         current_offset += current_bb->max_length;
3154                 }
3155         }
3156
3157         if (cfg->opt & MONO_OPT_LOOP) {
3158                 int pad, align = LOOP_ALIGNMENT;
3159                 /* set alignment depending on cpu */
3160                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3161                         pad = align - pad;
3162                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3163                         amd64_padding (code, pad);
3164                         cfg->code_len += pad;
3165                         bb->native_offset = cfg->code_len;
3166                 }
3167         }
3168
3169         if (cfg->verbose_level > 2)
3170                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3171
3172         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3173                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3174                 g_assert (!cfg->compile_aot);
3175
3176                 cov->data [bb->dfn].cil_code = bb->cil_code;
3177                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3178                 /* this is not thread save, but good enough */
3179                 amd64_inc_membase (code, AMD64_R11, 0);
3180         }
3181
3182         offset = code - cfg->native_code;
3183
3184         mono_debug_open_block (cfg, bb, offset);
3185
3186     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3187                 x86_breakpoint (code);
3188
3189         MONO_BB_FOR_EACH_INS (bb, ins) {
3190                 offset = code - cfg->native_code;
3191
3192                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3193
3194                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3195                         cfg->code_size *= 2;
3196                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3197                         code = cfg->native_code + offset;
3198                         mono_jit_stats.code_reallocs++;
3199                 }
3200
3201                 if (cfg->debug_info)
3202                         mono_debug_record_line_number (cfg, ins, offset);
3203
3204                 switch (ins->opcode) {
3205                 case OP_BIGMUL:
3206                         amd64_mul_reg (code, ins->sreg2, TRUE);
3207                         break;
3208                 case OP_BIGMUL_UN:
3209                         amd64_mul_reg (code, ins->sreg2, FALSE);
3210                         break;
3211                 case OP_X86_SETEQ_MEMBASE:
3212                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3213                         break;
3214                 case OP_STOREI1_MEMBASE_IMM:
3215                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3216                         break;
3217                 case OP_STOREI2_MEMBASE_IMM:
3218                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3219                         break;
3220                 case OP_STOREI4_MEMBASE_IMM:
3221                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3222                         break;
3223                 case OP_STOREI1_MEMBASE_REG:
3224                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3225                         break;
3226                 case OP_STOREI2_MEMBASE_REG:
3227                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3228                         break;
3229                 case OP_STORE_MEMBASE_REG:
3230                 case OP_STOREI8_MEMBASE_REG:
3231                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3232                         break;
3233                 case OP_STOREI4_MEMBASE_REG:
3234                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3235                         break;
3236                 case OP_STORE_MEMBASE_IMM:
3237                 case OP_STOREI8_MEMBASE_IMM:
3238                         g_assert (amd64_is_imm32 (ins->inst_imm));
3239                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3240                         break;
3241                 case OP_LOAD_MEM:
3242                 case OP_LOADI8_MEM:
3243                         // FIXME: Decompose this earlier
3244                         if (amd64_is_imm32 (ins->inst_imm))
3245                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3246                         else {
3247                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3248                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3249                         }
3250                         break;
3251                 case OP_LOADI4_MEM:
3252                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3253                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3254                         break;
3255                 case OP_LOADU4_MEM:
3256                         // FIXME: Decompose this earlier
3257                         if (amd64_is_imm32 (ins->inst_imm))
3258                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3259                         else {
3260                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3261                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3262                         }
3263                         break;
3264                 case OP_LOADU1_MEM:
3265                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3266                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3267                         break;
3268                 case OP_LOADU2_MEM:
3269                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3270                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3271                         break;
3272                 case OP_LOAD_MEMBASE:
3273                 case OP_LOADI8_MEMBASE:
3274                         g_assert (amd64_is_imm32 (ins->inst_offset));
3275                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3276                         break;
3277                 case OP_LOADI4_MEMBASE:
3278                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3279                         break;
3280                 case OP_LOADU4_MEMBASE:
3281                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3282                         break;
3283                 case OP_LOADU1_MEMBASE:
3284                         /* The cpu zero extends the result into 64 bits */
3285                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3286                         break;
3287                 case OP_LOADI1_MEMBASE:
3288                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3289                         break;
3290                 case OP_LOADU2_MEMBASE:
3291                         /* The cpu zero extends the result into 64 bits */
3292                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3293                         break;
3294                 case OP_LOADI2_MEMBASE:
3295                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3296                         break;
3297                 case OP_AMD64_LOADI8_MEMINDEX:
3298                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3299                         break;
3300                 case OP_LCONV_TO_I1:
3301                 case OP_ICONV_TO_I1:
3302                 case OP_SEXT_I1:
3303                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3304                         break;
3305                 case OP_LCONV_TO_I2:
3306                 case OP_ICONV_TO_I2:
3307                 case OP_SEXT_I2:
3308                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3309                         break;
3310                 case OP_LCONV_TO_U1:
3311                 case OP_ICONV_TO_U1:
3312                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3313                         break;
3314                 case OP_LCONV_TO_U2:
3315                 case OP_ICONV_TO_U2:
3316                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3317                         break;
3318                 case OP_ZEXT_I4:
3319                         /* Clean out the upper word */
3320                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3321                         break;
3322                 case OP_SEXT_I4:
3323                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3324                         break;
3325                 case OP_COMPARE:
3326                 case OP_LCOMPARE:
3327                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3328                         break;
3329                 case OP_COMPARE_IMM:
3330                 case OP_LCOMPARE_IMM:
3331                         g_assert (amd64_is_imm32 (ins->inst_imm));
3332                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3333                         break;
3334                 case OP_X86_COMPARE_REG_MEMBASE:
3335                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3336                         break;
3337                 case OP_X86_TEST_NULL:
3338                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3339                         break;
3340                 case OP_AMD64_TEST_NULL:
3341                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3342                         break;
3343
3344                 case OP_X86_ADD_REG_MEMBASE:
3345                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3346                         break;
3347                 case OP_X86_SUB_REG_MEMBASE:
3348                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3349                         break;
3350                 case OP_X86_AND_REG_MEMBASE:
3351                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3352                         break;
3353                 case OP_X86_OR_REG_MEMBASE:
3354                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3355                         break;
3356                 case OP_X86_XOR_REG_MEMBASE:
3357                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3358                         break;
3359
3360                 case OP_X86_ADD_MEMBASE_IMM:
3361                         /* FIXME: Make a 64 version too */
3362                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3363                         break;
3364                 case OP_X86_SUB_MEMBASE_IMM:
3365                         g_assert (amd64_is_imm32 (ins->inst_imm));
3366                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3367                         break;
3368                 case OP_X86_AND_MEMBASE_IMM:
3369                         g_assert (amd64_is_imm32 (ins->inst_imm));
3370                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3371                         break;
3372                 case OP_X86_OR_MEMBASE_IMM:
3373                         g_assert (amd64_is_imm32 (ins->inst_imm));
3374                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3375                         break;
3376                 case OP_X86_XOR_MEMBASE_IMM:
3377                         g_assert (amd64_is_imm32 (ins->inst_imm));
3378                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3379                         break;
3380                 case OP_X86_ADD_MEMBASE_REG:
3381                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3382                         break;
3383                 case OP_X86_SUB_MEMBASE_REG:
3384                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3385                         break;
3386                 case OP_X86_AND_MEMBASE_REG:
3387                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3388                         break;
3389                 case OP_X86_OR_MEMBASE_REG:
3390                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3391                         break;
3392                 case OP_X86_XOR_MEMBASE_REG:
3393                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3394                         break;
3395                 case OP_X86_INC_MEMBASE:
3396                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3397                         break;
3398                 case OP_X86_INC_REG:
3399                         amd64_inc_reg_size (code, ins->dreg, 4);
3400                         break;
3401                 case OP_X86_DEC_MEMBASE:
3402                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3403                         break;
3404                 case OP_X86_DEC_REG:
3405                         amd64_dec_reg_size (code, ins->dreg, 4);
3406                         break;
3407                 case OP_X86_MUL_REG_MEMBASE:
3408                 case OP_X86_MUL_MEMBASE_REG:
3409                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3410                         break;
3411                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3412                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3413                         break;
3414                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3415                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3416                         break;
3417                 case OP_AMD64_COMPARE_MEMBASE_REG:
3418                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3419                         break;
3420                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3421                         g_assert (amd64_is_imm32 (ins->inst_imm));
3422                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3423                         break;
3424                 case OP_X86_COMPARE_MEMBASE8_IMM:
3425                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3426                         break;
3427                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3428                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3429                         break;
3430                 case OP_AMD64_COMPARE_REG_MEMBASE:
3431                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3432                         break;
3433
3434                 case OP_AMD64_ADD_REG_MEMBASE:
3435                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3436                         break;
3437                 case OP_AMD64_SUB_REG_MEMBASE:
3438                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3439                         break;
3440                 case OP_AMD64_AND_REG_MEMBASE:
3441                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3442                         break;
3443                 case OP_AMD64_OR_REG_MEMBASE:
3444                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3445                         break;
3446                 case OP_AMD64_XOR_REG_MEMBASE:
3447                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3448                         break;
3449
3450                 case OP_AMD64_ADD_MEMBASE_REG:
3451                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3452                         break;
3453                 case OP_AMD64_SUB_MEMBASE_REG:
3454                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3455                         break;
3456                 case OP_AMD64_AND_MEMBASE_REG:
3457                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3458                         break;
3459                 case OP_AMD64_OR_MEMBASE_REG:
3460                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3461                         break;
3462                 case OP_AMD64_XOR_MEMBASE_REG:
3463                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3464                         break;
3465
3466                 case OP_AMD64_ADD_MEMBASE_IMM:
3467                         g_assert (amd64_is_imm32 (ins->inst_imm));
3468                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3469                         break;
3470                 case OP_AMD64_SUB_MEMBASE_IMM:
3471                         g_assert (amd64_is_imm32 (ins->inst_imm));
3472                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3473                         break;
3474                 case OP_AMD64_AND_MEMBASE_IMM:
3475                         g_assert (amd64_is_imm32 (ins->inst_imm));
3476                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3477                         break;
3478                 case OP_AMD64_OR_MEMBASE_IMM:
3479                         g_assert (amd64_is_imm32 (ins->inst_imm));
3480                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3481                         break;
3482                 case OP_AMD64_XOR_MEMBASE_IMM:
3483                         g_assert (amd64_is_imm32 (ins->inst_imm));
3484                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3485                         break;
3486
3487                 case OP_BREAK:
3488                         amd64_breakpoint (code);
3489                         break;
3490                 case OP_RELAXED_NOP:
3491                         x86_prefix (code, X86_REP_PREFIX);
3492                         x86_nop (code);
3493                         break;
3494                 case OP_HARD_NOP:
3495                         x86_nop (code);
3496                         break;
3497                 case OP_NOP:
3498                 case OP_DUMMY_USE:
3499                 case OP_DUMMY_STORE:
3500                 case OP_NOT_REACHED:
3501                 case OP_NOT_NULL:
3502                         break;
3503                 case OP_SEQ_POINT: {
3504                         int i, il_offset;
3505
3506                         if (cfg->compile_aot)
3507                                 NOT_IMPLEMENTED;
3508
3509                         /*
3510                          * Read from the single stepping trigger page. This will cause a
3511                          * SIGSEGV when single stepping is enabled.
3512                          * We do this _before_ the breakpoint, so single stepping after
3513                          * a breakpoint is hit will step to the next IL offset.
3514                          */
3515                         g_assert (((guint64)ss_trigger_page >> 32) == 0);
3516
3517                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
3518                                 amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3519
3520                         il_offset = ins->inst_imm;
3521
3522                         if (!cfg->seq_points)
3523                                 cfg->seq_points = g_ptr_array_new ();
3524                         g_ptr_array_add (cfg->seq_points, GUINT_TO_POINTER (il_offset));
3525                         g_ptr_array_add (cfg->seq_points, GUINT_TO_POINTER (code - cfg->native_code));
3526                         /*
3527                          * A placeholder for a possible breakpoint inserted by
3528                          * mono_arch_set_breakpoint ().
3529                          */
3530                         for (i = 0; i < BREAKPOINT_SIZE; ++i)
3531                                 x86_nop (code);
3532                         break;
3533                 }
3534                 case OP_ADDCC:
3535                 case OP_LADD:
3536                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3537                         break;
3538                 case OP_ADC:
3539                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3540                         break;
3541                 case OP_ADD_IMM:
3542                 case OP_LADD_IMM:
3543                         g_assert (amd64_is_imm32 (ins->inst_imm));
3544                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3545                         break;
3546                 case OP_ADC_IMM:
3547                         g_assert (amd64_is_imm32 (ins->inst_imm));
3548                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3549                         break;
3550                 case OP_SUBCC:
3551                 case OP_LSUB:
3552                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3553                         break;
3554                 case OP_SBB:
3555                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3556                         break;
3557                 case OP_SUB_IMM:
3558                 case OP_LSUB_IMM:
3559                         g_assert (amd64_is_imm32 (ins->inst_imm));
3560                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3561                         break;
3562                 case OP_SBB_IMM:
3563                         g_assert (amd64_is_imm32 (ins->inst_imm));
3564                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3565                         break;
3566                 case OP_LAND:
3567                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3568                         break;
3569                 case OP_AND_IMM:
3570                 case OP_LAND_IMM:
3571                         g_assert (amd64_is_imm32 (ins->inst_imm));
3572                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3573                         break;
3574                 case OP_LMUL:
3575                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3576                         break;
3577                 case OP_MUL_IMM:
3578                 case OP_LMUL_IMM:
3579                 case OP_IMUL_IMM: {
3580                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3581
3582                         switch (ins->inst_imm) {
3583                         case 2:
3584                                 /* MOV r1, r2 */
3585                                 /* ADD r1, r1 */
3586                                 if (ins->dreg != ins->sreg1)
3587                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3588                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3589                                 break;
3590                         case 3:
3591                                 /* LEA r1, [r2 + r2*2] */
3592                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3593                                 break;
3594                         case 5:
3595                                 /* LEA r1, [r2 + r2*4] */
3596                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3597                                 break;
3598                         case 6:
3599                                 /* LEA r1, [r2 + r2*2] */
3600                                 /* ADD r1, r1          */
3601                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3602                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3603                                 break;
3604                         case 9:
3605                                 /* LEA r1, [r2 + r2*8] */
3606                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3607                                 break;
3608                         case 10:
3609                                 /* LEA r1, [r2 + r2*4] */
3610                                 /* ADD r1, r1          */
3611                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3612                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3613                                 break;
3614                         case 12:
3615                                 /* LEA r1, [r2 + r2*2] */
3616                                 /* SHL r1, 2           */
3617                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3618                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3619                                 break;
3620                         case 25:
3621                                 /* LEA r1, [r2 + r2*4] */
3622                                 /* LEA r1, [r1 + r1*4] */
3623                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3624                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3625                                 break;
3626                         case 100:
3627                                 /* LEA r1, [r2 + r2*4] */
3628                                 /* SHL r1, 2           */
3629                                 /* LEA r1, [r1 + r1*4] */
3630                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3631                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3632                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3633                                 break;
3634                         default:
3635                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3636                                 break;
3637                         }
3638                         break;
3639                 }
3640                 case OP_LDIV:
3641                 case OP_LREM:
3642                         /* Regalloc magic makes the div/rem cases the same */
3643                         if (ins->sreg2 == AMD64_RDX) {
3644                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3645                                 amd64_cdq (code);
3646                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3647                         } else {
3648                                 amd64_cdq (code);
3649                                 amd64_div_reg (code, ins->sreg2, TRUE);
3650                         }
3651                         break;
3652                 case OP_LDIV_UN:
3653                 case OP_LREM_UN:
3654                         if (ins->sreg2 == AMD64_RDX) {
3655                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3656                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3657                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3658                         } else {
3659                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3660                                 amd64_div_reg (code, ins->sreg2, FALSE);
3661                         }
3662                         break;
3663                 case OP_IDIV:
3664                 case OP_IREM:
3665                         if (ins->sreg2 == AMD64_RDX) {
3666                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3667                                 amd64_cdq_size (code, 4);
3668                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3669                         } else {
3670                                 amd64_cdq_size (code, 4);
3671                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3672                         }
3673                         break;
3674                 case OP_IDIV_UN:
3675                 case OP_IREM_UN:
3676                         if (ins->sreg2 == AMD64_RDX) {
3677                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3678                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3679                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3680                         } else {
3681                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3682                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3683                         }
3684                         break;
3685                 case OP_IREM_IMM: {
3686                         int power = mono_is_power_of_two (ins->inst_imm);
3687
3688                         g_assert (ins->sreg1 == X86_EAX);
3689                         g_assert (ins->dreg == X86_EAX);
3690                         g_assert (power >= 0);
3691
3692                         if (power == 0) {
3693                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3694                                 break;
3695                         }
3696
3697                         /* Based on gcc code */
3698
3699                         /* Add compensation for negative dividents */
3700                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3701                         if (power > 1)
3702                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3703                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3704                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3705                         /* Compute remainder */
3706                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3707                         /* Remove compensation */
3708                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3709                         break;
3710                 }
3711                 case OP_LMUL_OVF:
3712                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3713                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3714                         break;
3715                 case OP_LOR:
3716                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3717                         break;
3718                 case OP_OR_IMM:
3719                 case OP_LOR_IMM:
3720                         g_assert (amd64_is_imm32 (ins->inst_imm));
3721                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3722                         break;
3723                 case OP_LXOR:
3724                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3725                         break;
3726                 case OP_XOR_IMM:
3727                 case OP_LXOR_IMM:
3728                         g_assert (amd64_is_imm32 (ins->inst_imm));
3729                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3730                         break;
3731                 case OP_LSHL:
3732                         g_assert (ins->sreg2 == AMD64_RCX);
3733                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3734                         break;
3735                 case OP_LSHR:
3736                         g_assert (ins->sreg2 == AMD64_RCX);
3737                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3738                         break;
3739                 case OP_SHR_IMM:
3740                         g_assert (amd64_is_imm32 (ins->inst_imm));
3741                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3742                         break;
3743                 case OP_LSHR_IMM:
3744                         g_assert (amd64_is_imm32 (ins->inst_imm));
3745                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3746                         break;
3747                 case OP_SHR_UN_IMM:
3748                         g_assert (amd64_is_imm32 (ins->inst_imm));
3749                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3750                         break;
3751                 case OP_LSHR_UN_IMM:
3752                         g_assert (amd64_is_imm32 (ins->inst_imm));
3753                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3754                         break;
3755                 case OP_LSHR_UN:
3756                         g_assert (ins->sreg2 == AMD64_RCX);
3757                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3758                         break;
3759                 case OP_SHL_IMM:
3760                         g_assert (amd64_is_imm32 (ins->inst_imm));
3761                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3762                         break;
3763                 case OP_LSHL_IMM:
3764                         g_assert (amd64_is_imm32 (ins->inst_imm));
3765                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3766                         break;
3767
3768                 case OP_IADDCC:
3769                 case OP_IADD:
3770                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3771                         break;
3772                 case OP_IADC:
3773                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3774                         break;
3775                 case OP_IADD_IMM:
3776                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3777                         break;
3778                 case OP_IADC_IMM:
3779                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3780                         break;
3781                 case OP_ISUBCC:
3782                 case OP_ISUB:
3783                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3784                         break;
3785                 case OP_ISBB:
3786                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3787                         break;
3788                 case OP_ISUB_IMM:
3789                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3790                         break;
3791                 case OP_ISBB_IMM:
3792                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3793                         break;
3794                 case OP_IAND:
3795                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3796                         break;
3797                 case OP_IAND_IMM:
3798                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3799                         break;
3800                 case OP_IOR:
3801                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3802                         break;
3803                 case OP_IOR_IMM:
3804                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3805                         break;
3806                 case OP_IXOR:
3807                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3808                         break;
3809                 case OP_IXOR_IMM:
3810                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3811                         break;
3812                 case OP_INEG:
3813                         amd64_neg_reg_size (code, ins->sreg1, 4);
3814                         break;
3815                 case OP_INOT:
3816                         amd64_not_reg_size (code, ins->sreg1, 4);
3817                         break;
3818                 case OP_ISHL:
3819                         g_assert (ins->sreg2 == AMD64_RCX);
3820                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3821                         break;
3822                 case OP_ISHR:
3823                         g_assert (ins->sreg2 == AMD64_RCX);
3824                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3825                         break;
3826                 case OP_ISHR_IMM:
3827                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3828                         break;
3829                 case OP_ISHR_UN_IMM:
3830                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3831                         break;
3832                 case OP_ISHR_UN:
3833                         g_assert (ins->sreg2 == AMD64_RCX);
3834                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3835                         break;
3836                 case OP_ISHL_IMM:
3837                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3838                         break;
3839                 case OP_IMUL:
3840                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3841                         break;
3842                 case OP_IMUL_OVF:
3843                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3844                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3845                         break;
3846                 case OP_IMUL_OVF_UN:
3847                 case OP_LMUL_OVF_UN: {
3848                         /* the mul operation and the exception check should most likely be split */
3849                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3850                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3851                         /*g_assert (ins->sreg2 == X86_EAX);
3852                         g_assert (ins->dreg == X86_EAX);*/
3853                         if (ins->sreg2 == X86_EAX) {
3854                                 non_eax_reg = ins->sreg1;
3855                         } else if (ins->sreg1 == X86_EAX) {
3856                                 non_eax_reg = ins->sreg2;
3857                         } else {
3858                                 /* no need to save since we're going to store to it anyway */
3859                                 if (ins->dreg != X86_EAX) {
3860                                         saved_eax = TRUE;
3861                                         amd64_push_reg (code, X86_EAX);
3862                                 }
3863                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3864                                 non_eax_reg = ins->sreg2;
3865                         }
3866                         if (ins->dreg == X86_EDX) {
3867                                 if (!saved_eax) {
3868                                         saved_eax = TRUE;
3869                                         amd64_push_reg (code, X86_EAX);
3870                                 }
3871                         } else {
3872                                 saved_edx = TRUE;
3873                                 amd64_push_reg (code, X86_EDX);
3874                         }
3875                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3876                         /* save before the check since pop and mov don't change the flags */
3877                         if (ins->dreg != X86_EAX)
3878                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3879                         if (saved_edx)
3880                                 amd64_pop_reg (code, X86_EDX);
3881                         if (saved_eax)
3882                                 amd64_pop_reg (code, X86_EAX);
3883                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3884                         break;
3885                 }
3886                 case OP_ICOMPARE:
3887                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3888                         break;
3889                 case OP_ICOMPARE_IMM:
3890                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3891                         break;
3892                 case OP_IBEQ:
3893                 case OP_IBLT:
3894                 case OP_IBGT:
3895                 case OP_IBGE:
3896                 case OP_IBLE:
3897                 case OP_LBEQ:
3898                 case OP_LBLT:
3899                 case OP_LBGT:
3900                 case OP_LBGE:
3901                 case OP_LBLE:
3902                 case OP_IBNE_UN:
3903                 case OP_IBLT_UN:
3904                 case OP_IBGT_UN:
3905                 case OP_IBGE_UN:
3906                 case OP_IBLE_UN:
3907                 case OP_LBNE_UN:
3908                 case OP_LBLT_UN:
3909                 case OP_LBGT_UN:
3910                 case OP_LBGE_UN:
3911                 case OP_LBLE_UN:
3912                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3913                         break;
3914
3915                 case OP_CMOV_IEQ:
3916                 case OP_CMOV_IGE:
3917                 case OP_CMOV_IGT:
3918                 case OP_CMOV_ILE:
3919                 case OP_CMOV_ILT:
3920                 case OP_CMOV_INE_UN:
3921                 case OP_CMOV_IGE_UN:
3922                 case OP_CMOV_IGT_UN:
3923                 case OP_CMOV_ILE_UN:
3924                 case OP_CMOV_ILT_UN:
3925                 case OP_CMOV_LEQ:
3926                 case OP_CMOV_LGE:
3927                 case OP_CMOV_LGT:
3928                 case OP_CMOV_LLE:
3929                 case OP_CMOV_LLT:
3930                 case OP_CMOV_LNE_UN:
3931                 case OP_CMOV_LGE_UN:
3932                 case OP_CMOV_LGT_UN:
3933                 case OP_CMOV_LLE_UN:
3934                 case OP_CMOV_LLT_UN:
3935                         g_assert (ins->dreg == ins->sreg1);
3936                         /* This needs to operate on 64 bit values */
3937                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3938                         break;
3939
3940                 case OP_LNOT:
3941                         amd64_not_reg (code, ins->sreg1);
3942                         break;
3943                 case OP_LNEG:
3944                         amd64_neg_reg (code, ins->sreg1);
3945                         break;
3946
3947                 case OP_ICONST:
3948                 case OP_I8CONST:
3949                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3950                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3951                         else
3952                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3953                         break;
3954                 case OP_AOTCONST:
3955                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3956                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3957                         break;
3958                 case OP_JUMP_TABLE:
3959                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3960                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3961                         break;
3962                 case OP_MOVE:
3963                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3964                         break;
3965                 case OP_AMD64_SET_XMMREG_R4: {
3966                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3967                         break;
3968                 }
3969                 case OP_AMD64_SET_XMMREG_R8: {
3970                         if (ins->dreg != ins->sreg1)
3971                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3972                         break;
3973                 }
3974                 case OP_TAILCALL: {
3975                         /*
3976                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3977                          * Keep in sync with the code in emit_epilog.
3978                          */
3979                         int pos = 0, i;
3980
3981                         /* FIXME: no tracing support... */
3982                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3983                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
3984
3985                         g_assert (!cfg->method->save_lmf);
3986
3987                         if (cfg->arch.omit_fp) {
3988                                 guint32 save_offset = 0;
3989                                 /* Pop callee-saved registers */
3990                                 for (i = 0; i < AMD64_NREG; ++i)
3991                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3992                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3993                                                 save_offset += 8;
3994                                         }
3995                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3996                         }
3997                         else {
3998                                 for (i = 0; i < AMD64_NREG; ++i)
3999                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4000                                                 pos -= sizeof (gpointer);
4001
4002                                 if (pos)
4003                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4004
4005                                 /* Pop registers in reverse order */
4006                                 for (i = AMD64_NREG - 1; i > 0; --i)
4007                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4008                                                 amd64_pop_reg (code, i);
4009                                         }
4010
4011                                 amd64_leave (code);
4012                         }
4013
4014                         offset = code - cfg->native_code;
4015                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4016                         if (cfg->compile_aot)
4017                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4018                         else
4019                                 amd64_set_reg_template (code, AMD64_R11);
4020                         amd64_jump_reg (code, AMD64_R11);
4021                         break;
4022                 }
4023                 case OP_CHECK_THIS:
4024                         /* ensure ins->sreg1 is not NULL */
4025                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4026                         break;
4027                 case OP_ARGLIST: {
4028                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4029                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4030                         break;
4031                 }
4032                 case OP_CALL:
4033                 case OP_FCALL:
4034                 case OP_LCALL:
4035                 case OP_VCALL:
4036                 case OP_VCALL2:
4037                 case OP_VOIDCALL:
4038                         call = (MonoCallInst*)ins;
4039                         /*
4040                          * The AMD64 ABI forces callers to know about varargs.
4041                          */
4042                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4043                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4044                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4045                                 /*
4046                                  * Since the unmanaged calling convention doesn't contain a
4047                                  * 'vararg' entry, we have to treat every pinvoke call as a
4048                                  * potential vararg call.
4049                                  */
4050                                 guint32 nregs, i;
4051                                 nregs = 0;
4052                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4053                                         if (call->used_fregs & (1 << i))
4054                                                 nregs ++;
4055                                 if (!nregs)
4056                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4057                                 else
4058                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4059                         }
4060
4061                         if (ins->flags & MONO_INST_HAS_METHOD)
4062                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4063                         else
4064                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4065                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4066                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4067                         code = emit_move_return_value (cfg, ins, code);
4068                         break;
4069                 case OP_FCALL_REG:
4070                 case OP_LCALL_REG:
4071                 case OP_VCALL_REG:
4072                 case OP_VCALL2_REG:
4073                 case OP_VOIDCALL_REG:
4074                 case OP_CALL_REG:
4075                         call = (MonoCallInst*)ins;
4076
4077                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4078                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4079                                 ins->sreg1 = AMD64_R11;
4080                         }
4081
4082                         /*
4083                          * The AMD64 ABI forces callers to know about varargs.
4084                          */
4085                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4086                                 if (ins->sreg1 == AMD64_RAX) {
4087                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4088                                         ins->sreg1 = AMD64_R11;
4089                                 }
4090                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4091                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4092                                 /*
4093                                  * Since the unmanaged calling convention doesn't contain a
4094                                  * 'vararg' entry, we have to treat every pinvoke call as a
4095                                  * potential vararg call.
4096                                  */
4097                                 guint32 nregs, i;
4098                                 nregs = 0;
4099                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4100                                         if (call->used_fregs & (1 << i))
4101                                                 nregs ++;
4102                                 if (ins->sreg1 == AMD64_RAX) {
4103                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4104                                         ins->sreg1 = AMD64_R11;
4105                                 }
4106                                 if (!nregs)
4107                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4108                                 else
4109                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4110                         }
4111
4112                         amd64_call_reg (code, ins->sreg1);
4113                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4114                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4115                         code = emit_move_return_value (cfg, ins, code);
4116                         break;
4117                 case OP_FCALL_MEMBASE:
4118                 case OP_LCALL_MEMBASE:
4119                 case OP_VCALL_MEMBASE:
4120                 case OP_VCALL2_MEMBASE:
4121                 case OP_VOIDCALL_MEMBASE:
4122                 case OP_CALL_MEMBASE:
4123                         call = (MonoCallInst*)ins;
4124
4125                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4126                                 /*
4127                                  * Can't use R11 because it is clobbered by the trampoline
4128                                  * code, and the reg value is needed by get_vcall_slot_addr.
4129                                  */
4130                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4131                                 ins->sreg1 = AMD64_RAX;
4132                         }
4133
4134                         /*
4135                          * Emit a few nops to simplify get_vcall_slot ().
4136                          */
4137                         amd64_nop (code);
4138                         amd64_nop (code);
4139                         amd64_nop (code);
4140
4141                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4142                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4143                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4144                         code = emit_move_return_value (cfg, ins, code);
4145                         break;
4146                 case OP_DYN_CALL: {
4147                         int i;
4148                         MonoInst *var = cfg->dyn_call_var;
4149
4150                         g_assert (var->opcode == OP_REGOFFSET);
4151
4152                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4153                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4154                         /* r10 = ftn */
4155                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4156
4157                         /* Save args buffer */
4158                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4159
4160                         /* Set argument registers */
4161                         for (i = 0; i < PARAM_REGS; ++i)
4162                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4163
4164                         /* Make the call */
4165                         amd64_call_reg (code, AMD64_R10);
4166
4167                         /* Save result */
4168                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4169                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4170                         break;
4171                 }
4172                 case OP_AMD64_SAVE_SP_TO_LMF:
4173                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4174                         break;
4175                 case OP_X86_PUSH:
4176                         g_assert (!cfg->arch.no_pushes);
4177                         amd64_push_reg (code, ins->sreg1);
4178                         break;
4179                 case OP_X86_PUSH_IMM:
4180                         g_assert (!cfg->arch.no_pushes);
4181                         g_assert (amd64_is_imm32 (ins->inst_imm));
4182                         amd64_push_imm (code, ins->inst_imm);
4183                         break;
4184                 case OP_X86_PUSH_MEMBASE:
4185                         g_assert (!cfg->arch.no_pushes);
4186                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4187                         break;
4188                 case OP_X86_PUSH_OBJ: {
4189                         int size = ALIGN_TO (ins->inst_imm, 8);
4190
4191                         g_assert (!cfg->arch.no_pushes);
4192
4193                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4194                         amd64_push_reg (code, AMD64_RDI);
4195                         amd64_push_reg (code, AMD64_RSI);
4196                         amd64_push_reg (code, AMD64_RCX);
4197                         if (ins->inst_offset)
4198                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4199                         else
4200                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4201                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4202                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4203                         amd64_cld (code);
4204                         amd64_prefix (code, X86_REP_PREFIX);
4205                         amd64_movsd (code);
4206                         amd64_pop_reg (code, AMD64_RCX);
4207                         amd64_pop_reg (code, AMD64_RSI);
4208                         amd64_pop_reg (code, AMD64_RDI);
4209                         break;
4210                 }
4211                 case OP_X86_LEA:
4212                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4213                         break;
4214                 case OP_X86_LEA_MEMBASE:
4215                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4216                         break;
4217                 case OP_X86_XCHG:
4218                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4219                         break;
4220                 case OP_LOCALLOC:
4221                         /* keep alignment */
4222                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4223                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4224                         code = mono_emit_stack_alloc (cfg, code, ins);
4225                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4226                         if (cfg->param_area && cfg->arch.no_pushes)
4227                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4228                         break;
4229                 case OP_LOCALLOC_IMM: {
4230                         guint32 size = ins->inst_imm;
4231                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4232
4233                         if (ins->flags & MONO_INST_INIT) {
4234                                 if (size < 64) {
4235                                         int i;
4236
4237                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4238                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4239
4240                                         for (i = 0; i < size; i += 8)
4241                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4242                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4243                                 } else {
4244                                         amd64_mov_reg_imm (code, ins->dreg, size);
4245                                         ins->sreg1 = ins->dreg;
4246
4247                                         code = mono_emit_stack_alloc (cfg, code, ins);
4248                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4249                                 }
4250                         } else {
4251                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4252                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4253                         }
4254                         if (cfg->param_area && cfg->arch.no_pushes)
4255                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4256                         break;
4257                 }
4258                 case OP_THROW: {
4259                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4260                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4261                                              (gpointer)"mono_arch_throw_exception", FALSE);
4262                         break;
4263                 }
4264                 case OP_RETHROW: {
4265                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4266                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4267                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4268                         break;
4269                 }
4270                 case OP_CALL_HANDLER:
4271                         /* Align stack */
4272                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4273                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4274                         amd64_call_imm (code, 0);
4275                         /* Restore stack alignment */
4276                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4277                         break;
4278                 case OP_START_HANDLER: {
4279                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4280                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4281
4282                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4283                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4284                                 cfg->param_area && cfg->arch.no_pushes) {
4285                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4286                         }
4287                         break;
4288                 }
4289                 case OP_ENDFINALLY: {
4290                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4291                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4292                         amd64_ret (code);
4293                         break;
4294                 }
4295                 case OP_ENDFILTER: {
4296                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4297                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4298                         /* The local allocator will put the result into RAX */
4299                         amd64_ret (code);
4300                         break;
4301                 }
4302
4303                 case OP_LABEL:
4304                         ins->inst_c0 = code - cfg->native_code;
4305                         break;
4306                 case OP_BR:
4307                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4308                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4309                         //break;
4310                                 if (ins->inst_target_bb->native_offset) {
4311                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4312                                 } else {
4313                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4314                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4315                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4316                                                 x86_jump8 (code, 0);
4317                                         else
4318                                                 x86_jump32 (code, 0);
4319                         }
4320                         break;
4321                 case OP_BR_REG:
4322                         amd64_jump_reg (code, ins->sreg1);
4323                         break;
4324                 case OP_CEQ:
4325                 case OP_LCEQ:
4326                 case OP_ICEQ:
4327                 case OP_CLT:
4328                 case OP_LCLT:
4329                 case OP_ICLT:
4330                 case OP_CGT:
4331                 case OP_ICGT:
4332                 case OP_LCGT:
4333                 case OP_CLT_UN:
4334                 case OP_LCLT_UN:
4335                 case OP_ICLT_UN:
4336                 case OP_CGT_UN:
4337                 case OP_LCGT_UN:
4338                 case OP_ICGT_UN:
4339                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4340                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4341                         break;
4342                 case OP_COND_EXC_EQ:
4343                 case OP_COND_EXC_NE_UN:
4344                 case OP_COND_EXC_LT:
4345                 case OP_COND_EXC_LT_UN:
4346                 case OP_COND_EXC_GT:
4347                 case OP_COND_EXC_GT_UN:
4348                 case OP_COND_EXC_GE:
4349                 case OP_COND_EXC_GE_UN:
4350                 case OP_COND_EXC_LE:
4351                 case OP_COND_EXC_LE_UN:
4352                 case OP_COND_EXC_IEQ:
4353                 case OP_COND_EXC_INE_UN:
4354                 case OP_COND_EXC_ILT:
4355                 case OP_COND_EXC_ILT_UN:
4356                 case OP_COND_EXC_IGT:
4357                 case OP_COND_EXC_IGT_UN:
4358                 case OP_COND_EXC_IGE:
4359                 case OP_COND_EXC_IGE_UN:
4360                 case OP_COND_EXC_ILE:
4361                 case OP_COND_EXC_ILE_UN:
4362                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4363                         break;
4364                 case OP_COND_EXC_OV:
4365                 case OP_COND_EXC_NO:
4366                 case OP_COND_EXC_C:
4367                 case OP_COND_EXC_NC:
4368                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4369                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4370                         break;
4371                 case OP_COND_EXC_IOV:
4372                 case OP_COND_EXC_INO:
4373                 case OP_COND_EXC_IC:
4374                 case OP_COND_EXC_INC:
4375                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4376                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4377                         break;
4378
4379                 /* floating point opcodes */
4380                 case OP_R8CONST: {
4381                         double d = *(double *)ins->inst_p0;
4382
4383                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4384                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4385                         }
4386                         else {
4387                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4388                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4389                         }
4390                         break;
4391                 }
4392                 case OP_R4CONST: {
4393                         float f = *(float *)ins->inst_p0;
4394
4395                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4396                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4397                         }
4398                         else {
4399                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4400                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4401                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4402                         }
4403                         break;
4404                 }
4405                 case OP_STORER8_MEMBASE_REG:
4406                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4407                         break;
4408                 case OP_LOADR8_MEMBASE:
4409                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4410                         break;
4411                 case OP_STORER4_MEMBASE_REG:
4412                         /* This requires a double->single conversion */
4413                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4414                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4415                         break;
4416                 case OP_LOADR4_MEMBASE:
4417                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4418                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4419                         break;
4420                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4421                 case OP_ICONV_TO_R8:
4422                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4423                         break;
4424                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4425                 case OP_LCONV_TO_R8:
4426                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4427                         break;
4428                 case OP_FCONV_TO_R4:
4429                         /* FIXME: nothing to do ?? */
4430                         break;
4431                 case OP_FCONV_TO_I1:
4432                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4433                         break;
4434                 case OP_FCONV_TO_U1:
4435                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4436                         break;
4437                 case OP_FCONV_TO_I2:
4438                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4439                         break;
4440                 case OP_FCONV_TO_U2:
4441                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4442                         break;
4443                 case OP_FCONV_TO_U4:
4444                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4445                         break;
4446                 case OP_FCONV_TO_I4:
4447                 case OP_FCONV_TO_I:
4448                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4449                         break;
4450                 case OP_FCONV_TO_I8:
4451                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4452                         break;
4453                 case OP_LCONV_TO_R_UN: {
4454                         guint8 *br [2];
4455
4456                         /* Based on gcc code */
4457                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4458                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4459
4460                         /* Positive case */
4461                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4462                         br [1] = code; x86_jump8 (code, 0);
4463                         amd64_patch (br [0], code);
4464
4465                         /* Negative case */
4466                         /* Save to the red zone */
4467                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4468                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4469                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4470                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4471                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4472                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4473                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4474                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4475                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4476                         /* Restore */
4477                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4478                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4479                         amd64_patch (br [1], code);
4480                         break;
4481                 }
4482                 case OP_LCONV_TO_OVF_U4:
4483                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4484                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4485                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4486                         break;
4487                 case OP_LCONV_TO_OVF_I4_UN:
4488                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4489                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4490                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4491                         break;
4492                 case OP_FMOVE:
4493                         if (ins->dreg != ins->sreg1)
4494                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4495                         break;
4496                 case OP_FADD:
4497                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4498                         break;
4499                 case OP_FSUB:
4500                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4501                         break;
4502                 case OP_FMUL:
4503                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4504                         break;
4505                 case OP_FDIV:
4506                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4507                         break;
4508                 case OP_FNEG: {
4509                         static double r8_0 = -0.0;
4510
4511                         g_assert (ins->sreg1 == ins->dreg);
4512
4513                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4514                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4515                         break;
4516                 }
4517                 case OP_SIN:
4518                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4519                         break;
4520                 case OP_COS:
4521                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4522                         break;
4523                 case OP_ABS: {
4524                         static guint64 d = 0x7fffffffffffffffUL;
4525
4526                         g_assert (ins->sreg1 == ins->dreg);
4527
4528                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4529                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4530                         break;
4531                 }
4532                 case OP_SQRT:
4533                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4534                         break;
4535                 case OP_IMIN:
4536                         g_assert (cfg->opt & MONO_OPT_CMOV);
4537                         g_assert (ins->dreg == ins->sreg1);
4538                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4539                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4540                         break;
4541                 case OP_IMIN_UN:
4542                         g_assert (cfg->opt & MONO_OPT_CMOV);
4543                         g_assert (ins->dreg == ins->sreg1);
4544                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4545                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4546                         break;
4547                 case OP_IMAX:
4548                         g_assert (cfg->opt & MONO_OPT_CMOV);
4549                         g_assert (ins->dreg == ins->sreg1);
4550                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4551                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4552                         break;
4553                 case OP_IMAX_UN:
4554                         g_assert (cfg->opt & MONO_OPT_CMOV);
4555                         g_assert (ins->dreg == ins->sreg1);
4556                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4557                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4558                         break;
4559                 case OP_LMIN:
4560                         g_assert (cfg->opt & MONO_OPT_CMOV);
4561                         g_assert (ins->dreg == ins->sreg1);
4562                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4563                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4564                         break;
4565                 case OP_LMIN_UN:
4566                         g_assert (cfg->opt & MONO_OPT_CMOV);
4567                         g_assert (ins->dreg == ins->sreg1);
4568                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4569                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4570                         break;
4571                 case OP_LMAX:
4572                         g_assert (cfg->opt & MONO_OPT_CMOV);
4573                         g_assert (ins->dreg == ins->sreg1);
4574                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4575                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4576                         break;
4577                 case OP_LMAX_UN:
4578                         g_assert (cfg->opt & MONO_OPT_CMOV);
4579                         g_assert (ins->dreg == ins->sreg1);
4580                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4581                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4582                         break;
4583                 case OP_X86_FPOP:
4584                         break;
4585                 case OP_FCOMPARE:
4586                         /*
4587                          * The two arguments are swapped because the fbranch instructions
4588                          * depend on this for the non-sse case to work.
4589                          */
4590                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4591                         break;
4592                 case OP_FCEQ: {
4593                         /* zeroing the register at the start results in
4594                          * shorter and faster code (we can also remove the widening op)
4595                          */
4596                         guchar *unordered_check;
4597                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4598                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4599                         unordered_check = code;
4600                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4601                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4602                         amd64_patch (unordered_check, code);
4603                         break;
4604                 }
4605                 case OP_FCLT:
4606                 case OP_FCLT_UN:
4607                         /* zeroing the register at the start results in
4608                          * shorter and faster code (we can also remove the widening op)
4609                          */
4610                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4611                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4612                         if (ins->opcode == OP_FCLT_UN) {
4613                                 guchar *unordered_check = code;
4614                                 guchar *jump_to_end;
4615                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4616                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4617                                 jump_to_end = code;
4618                                 x86_jump8 (code, 0);
4619                                 amd64_patch (unordered_check, code);
4620                                 amd64_inc_reg (code, ins->dreg);
4621                                 amd64_patch (jump_to_end, code);
4622                         } else {
4623                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4624                         }
4625                         break;
4626                 case OP_FCGT:
4627                 case OP_FCGT_UN: {
4628                         /* zeroing the register at the start results in
4629                          * shorter and faster code (we can also remove the widening op)
4630                          */
4631                         guchar *unordered_check;
4632                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4633                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4634                         if (ins->opcode == OP_FCGT) {
4635                                 unordered_check = code;
4636                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4637                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4638                                 amd64_patch (unordered_check, code);
4639                         } else {
4640                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4641                         }
4642                         break;
4643                 }
4644                 case OP_FCLT_MEMBASE:
4645                 case OP_FCGT_MEMBASE:
4646                 case OP_FCLT_UN_MEMBASE:
4647                 case OP_FCGT_UN_MEMBASE:
4648                 case OP_FCEQ_MEMBASE: {
4649                         guchar *unordered_check, *jump_to_end;
4650                         int x86_cond;
4651
4652                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4653                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4654
4655                         switch (ins->opcode) {
4656                         case OP_FCEQ_MEMBASE:
4657                                 x86_cond = X86_CC_EQ;
4658                                 break;
4659                         case OP_FCLT_MEMBASE:
4660                         case OP_FCLT_UN_MEMBASE:
4661                                 x86_cond = X86_CC_LT;
4662                                 break;
4663                         case OP_FCGT_MEMBASE:
4664                         case OP_FCGT_UN_MEMBASE:
4665                                 x86_cond = X86_CC_GT;
4666                                 break;
4667                         default:
4668                                 g_assert_not_reached ();
4669                         }
4670
4671                         unordered_check = code;
4672                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4673                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4674
4675                         switch (ins->opcode) {
4676                         case OP_FCEQ_MEMBASE:
4677                         case OP_FCLT_MEMBASE:
4678                         case OP_FCGT_MEMBASE:
4679                                 amd64_patch (unordered_check, code);
4680                                 break;
4681                         case OP_FCLT_UN_MEMBASE:
4682                         case OP_FCGT_UN_MEMBASE:
4683                                 jump_to_end = code;
4684                                 x86_jump8 (code, 0);
4685                                 amd64_patch (unordered_check, code);
4686                                 amd64_inc_reg (code, ins->dreg);
4687                                 amd64_patch (jump_to_end, code);
4688                                 break;
4689                         default:
4690                                 break;
4691                         }
4692                         break;
4693                 }
4694                 case OP_FBEQ: {
4695                         guchar *jump = code;
4696                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4697                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4698                         amd64_patch (jump, code);
4699                         break;
4700                 }
4701                 case OP_FBNE_UN:
4702                         /* Branch if C013 != 100 */
4703                         /* branch if !ZF or (PF|CF) */
4704                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4705                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4706                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4707                         break;
4708                 case OP_FBLT:
4709                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4710                         break;
4711                 case OP_FBLT_UN:
4712                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4713                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4714                         break;
4715                 case OP_FBGT:
4716                 case OP_FBGT_UN:
4717                         if (ins->opcode == OP_FBGT) {
4718                                 guchar *br1;
4719
4720                                 /* skip branch if C1=1 */
4721                                 br1 = code;
4722                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4723                                 /* branch if (C0 | C3) = 1 */
4724                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4725                                 amd64_patch (br1, code);
4726                                 break;
4727                         } else {
4728                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4729                         }
4730                         break;
4731                 case OP_FBGE: {
4732                         /* Branch if C013 == 100 or 001 */
4733                         guchar *br1;
4734
4735                         /* skip branch if C1=1 */
4736                         br1 = code;
4737                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4738                         /* branch if (C0 | C3) = 1 */
4739                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4740                         amd64_patch (br1, code);
4741                         break;
4742                 }
4743                 case OP_FBGE_UN:
4744                         /* Branch if C013 == 000 */
4745                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4746                         break;
4747                 case OP_FBLE: {
4748                         /* Branch if C013=000 or 100 */
4749                         guchar *br1;
4750
4751                         /* skip branch if C1=1 */
4752                         br1 = code;
4753                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4754                         /* branch if C0=0 */
4755                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4756                         amd64_patch (br1, code);
4757                         break;
4758                 }
4759                 case OP_FBLE_UN:
4760                         /* Branch if C013 != 001 */
4761                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4762                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4763                         break;
4764                 case OP_CKFINITE:
4765                         /* Transfer value to the fp stack */
4766                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4767                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4768                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4769
4770                         amd64_push_reg (code, AMD64_RAX);
4771                         amd64_fxam (code);
4772                         amd64_fnstsw (code);
4773                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4774                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4775                         amd64_pop_reg (code, AMD64_RAX);
4776                         amd64_fstp (code, 0);
4777                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4778                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4779                         break;
4780                 case OP_TLS_GET: {
4781                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4782                         break;
4783                 }
4784                 case OP_MEMORY_BARRIER: {
4785                         /* Not needed on amd64 */
4786                         break;
4787                 }
4788                 case OP_ATOMIC_ADD_I4:
4789                 case OP_ATOMIC_ADD_I8: {
4790                         int dreg = ins->dreg;
4791                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4792
4793                         if (dreg == ins->inst_basereg)
4794                                 dreg = AMD64_R11;
4795
4796                         if (dreg != ins->sreg2)
4797                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4798
4799                         x86_prefix (code, X86_LOCK_PREFIX);
4800                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4801
4802                         if (dreg != ins->dreg)
4803                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4804
4805                         break;
4806                 }
4807                 case OP_ATOMIC_ADD_NEW_I4:
4808                 case OP_ATOMIC_ADD_NEW_I8: {
4809                         int dreg = ins->dreg;
4810                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4811
4812                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4813                                 dreg = AMD64_R11;
4814
4815                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4816                         amd64_prefix (code, X86_LOCK_PREFIX);
4817                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4818                         /* dreg contains the old value, add with sreg2 value */
4819                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4820
4821                         if (ins->dreg != dreg)
4822                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4823
4824                         break;
4825                 }
4826                 case OP_ATOMIC_EXCHANGE_I4:
4827                 case OP_ATOMIC_EXCHANGE_I8: {
4828                         guchar *br[2];
4829                         int sreg2 = ins->sreg2;
4830                         int breg = ins->inst_basereg;
4831                         guint32 size;
4832                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4833
4834                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4835                                 size = 8;
4836                         else
4837                                 size = 4;
4838
4839                         /*
4840                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4841                          * an explanation of how this works.
4842                          */
4843
4844                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4845                          * hack to overcome limits in x86 reg allocator
4846                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4847                          */
4848                         g_assert (ins->dreg == AMD64_RAX);
4849
4850                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4851                                 /* Highly unlikely, but possible */
4852                                 need_push = TRUE;
4853
4854                         /* The pushes invalidate rsp */
4855                         if ((breg == AMD64_RAX) || need_push) {
4856                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4857                                 breg = AMD64_R11;
4858                         }
4859
4860                         /* We need the EAX reg for the comparand */
4861                         if (ins->sreg2 == AMD64_RAX) {
4862                                 if (breg != AMD64_R11) {
4863                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4864                                         sreg2 = AMD64_R11;
4865                                 } else {
4866                                         g_assert (need_push);
4867                                         amd64_push_reg (code, AMD64_RDX);
4868                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4869                                         sreg2 = AMD64_RDX;
4870                                         rdx_pushed = TRUE;
4871                                 }
4872                         }
4873
4874                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4875
4876                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4877                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4878                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4879                         amd64_patch (br [1], br [0]);
4880
4881                         if (rdx_pushed)
4882                                 amd64_pop_reg (code, AMD64_RDX);
4883
4884                         break;
4885                 }
4886                 case OP_ATOMIC_CAS_I4:
4887                 case OP_ATOMIC_CAS_I8: {
4888                         guint32 size;
4889
4890                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4891                                 size = 8;
4892                         else
4893                                 size = 4;
4894
4895                         /*
4896                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4897                          * an explanation of how this works.
4898                          */
4899                         g_assert (ins->sreg3 == AMD64_RAX);
4900                         g_assert (ins->sreg1 != AMD64_RAX);
4901                         g_assert (ins->sreg1 != ins->sreg2);
4902
4903                         amd64_prefix (code, X86_LOCK_PREFIX);
4904                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4905
4906                         if (ins->dreg != AMD64_RAX)
4907                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4908                         break;
4909                 }
4910 #ifdef MONO_ARCH_SIMD_INTRINSICS
4911                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
4912                 case OP_ADDPS:
4913                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
4914                         break;
4915                 case OP_DIVPS:
4916                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
4917                         break;
4918                 case OP_MULPS:
4919                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
4920                         break;
4921                 case OP_SUBPS:
4922                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
4923                         break;
4924                 case OP_MAXPS:
4925                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
4926                         break;
4927                 case OP_MINPS:
4928                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
4929                         break;
4930                 case OP_COMPPS:
4931                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4932                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4933                         break;
4934                 case OP_ANDPS:
4935                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
4936                         break;
4937                 case OP_ANDNPS:
4938                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
4939                         break;
4940                 case OP_ORPS:
4941                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
4942                         break;
4943                 case OP_XORPS:
4944                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
4945                         break;
4946                 case OP_SQRTPS:
4947                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4948                         break;
4949                 case OP_RSQRTPS:
4950                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4951                         break;
4952                 case OP_RCPPS:
4953                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
4954                         break;
4955                 case OP_ADDSUBPS:
4956                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
4957                         break;
4958                 case OP_HADDPS:
4959                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
4960                         break;
4961                 case OP_HSUBPS:
4962                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
4963                         break;
4964                 case OP_DUPPS_HIGH:
4965                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
4966                         break;
4967                 case OP_DUPPS_LOW:
4968                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
4969                         break;
4970
4971                 case OP_PSHUFLEW_HIGH:
4972                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4973                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4974                         break;
4975                 case OP_PSHUFLEW_LOW:
4976                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4977                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4978                         break;
4979                 case OP_PSHUFLED:
4980                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4981                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4982                         break;
4983
4984                 case OP_ADDPD:
4985                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
4986                         break;
4987                 case OP_DIVPD:
4988                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
4989                         break;
4990                 case OP_MULPD:
4991                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
4992                         break;
4993                 case OP_SUBPD:
4994                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
4995                         break;
4996                 case OP_MAXPD:
4997                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
4998                         break;
4999                 case OP_MINPD:
5000                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5001                         break;
5002                 case OP_COMPPD:
5003                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5004                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5005                         break;
5006                 case OP_ANDPD:
5007                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5008                         break;
5009                 case OP_ANDNPD:
5010                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5011                         break;
5012                 case OP_ORPD:
5013                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5014                         break;
5015                 case OP_XORPD:
5016                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5017                         break;
5018                 case OP_SQRTPD:
5019                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5020                         break;
5021                 case OP_ADDSUBPD:
5022                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5023                         break;
5024                 case OP_HADDPD:
5025                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5026                         break;
5027                 case OP_HSUBPD:
5028                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5029                         break;
5030                 case OP_DUPPD:
5031                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5032                         break;
5033
5034                 case OP_EXTRACT_MASK:
5035                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5036                         break;
5037
5038                 case OP_PAND:
5039                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5040                         break;
5041                 case OP_POR:
5042                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5043                         break;
5044                 case OP_PXOR:
5045                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5046                         break;
5047
5048                 case OP_PADDB:
5049                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5050                         break;
5051                 case OP_PADDW:
5052                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5053                         break;
5054                 case OP_PADDD:
5055                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5056                         break;
5057                 case OP_PADDQ:
5058                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5059                         break;
5060
5061                 case OP_PSUBB:
5062                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5063                         break;
5064                 case OP_PSUBW:
5065                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5066                         break;
5067                 case OP_PSUBD:
5068                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5069                         break;
5070                 case OP_PSUBQ:
5071                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5072                         break;
5073
5074                 case OP_PMAXB_UN:
5075                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5076                         break;
5077                 case OP_PMAXW_UN:
5078                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5079                         break;
5080                 case OP_PMAXD_UN:
5081                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5082                         break;
5083
5084                 case OP_PMAXB:
5085                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5086                         break;
5087                 case OP_PMAXW:
5088                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5089                         break;
5090                 case OP_PMAXD:
5091                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5092                         break;
5093
5094                 case OP_PAVGB_UN:
5095                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5096                         break;
5097                 case OP_PAVGW_UN:
5098                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5099                         break;
5100
5101                 case OP_PMINB_UN:
5102                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5103                         break;
5104                 case OP_PMINW_UN:
5105                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5106                         break;
5107                 case OP_PMIND_UN:
5108                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5109                         break;
5110
5111                 case OP_PMINB:
5112                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5113                         break;
5114                 case OP_PMINW:
5115                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5116                         break;
5117                 case OP_PMIND:
5118                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5119                         break;
5120
5121                 case OP_PCMPEQB:
5122                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5123                         break;
5124                 case OP_PCMPEQW:
5125                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5126                         break;
5127                 case OP_PCMPEQD:
5128                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5129                         break;
5130                 case OP_PCMPEQQ:
5131                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5132                         break;
5133
5134                 case OP_PCMPGTB:
5135                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5136                         break;
5137                 case OP_PCMPGTW:
5138                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5139                         break;
5140                 case OP_PCMPGTD:
5141                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5142                         break;
5143                 case OP_PCMPGTQ:
5144                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5145                         break;
5146
5147                 case OP_PSUM_ABS_DIFF:
5148                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5149                         break;
5150
5151                 case OP_UNPACK_LOWB:
5152                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5153                         break;
5154                 case OP_UNPACK_LOWW:
5155                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5156                         break;
5157                 case OP_UNPACK_LOWD:
5158                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5159                         break;
5160                 case OP_UNPACK_LOWQ:
5161                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5162                         break;
5163                 case OP_UNPACK_LOWPS:
5164                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5165                         break;
5166                 case OP_UNPACK_LOWPD:
5167                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5168                         break;
5169
5170                 case OP_UNPACK_HIGHB:
5171                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5172                         break;
5173                 case OP_UNPACK_HIGHW:
5174                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5175                         break;
5176                 case OP_UNPACK_HIGHD:
5177                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5178                         break;
5179                 case OP_UNPACK_HIGHQ:
5180                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5181                         break;
5182                 case OP_UNPACK_HIGHPS:
5183                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5184                         break;
5185                 case OP_UNPACK_HIGHPD:
5186                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5187                         break;
5188
5189                 case OP_PACKW:
5190                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5191                         break;
5192                 case OP_PACKD:
5193                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5194                         break;
5195                 case OP_PACKW_UN:
5196                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5197                         break;
5198                 case OP_PACKD_UN:
5199                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5200                         break;
5201
5202                 case OP_PADDB_SAT_UN:
5203                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5204                         break;
5205                 case OP_PSUBB_SAT_UN:
5206                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5207                         break;
5208                 case OP_PADDW_SAT_UN:
5209                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5210                         break;
5211                 case OP_PSUBW_SAT_UN:
5212                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5213                         break;
5214
5215                 case OP_PADDB_SAT:
5216                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5217                         break;
5218                 case OP_PSUBB_SAT:
5219                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5220                         break;
5221                 case OP_PADDW_SAT:
5222                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5223                         break;
5224                 case OP_PSUBW_SAT:
5225                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5226                         break;
5227
5228                 case OP_PMULW:
5229                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5230                         break;
5231                 case OP_PMULD:
5232                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5233                         break;
5234                 case OP_PMULQ:
5235                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5236                         break;
5237                 case OP_PMULW_HIGH_UN:
5238                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5239                         break;
5240                 case OP_PMULW_HIGH:
5241                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5242                         break;
5243
5244                 case OP_PSHRW:
5245                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5246                         break;
5247                 case OP_PSHRW_REG:
5248                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5249                         break;
5250
5251                 case OP_PSARW:
5252                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5253                         break;
5254                 case OP_PSARW_REG:
5255                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5256                         break;
5257
5258                 case OP_PSHLW:
5259                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5260                         break;
5261                 case OP_PSHLW_REG:
5262                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5263                         break;
5264
5265                 case OP_PSHRD:
5266                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5267                         break;
5268                 case OP_PSHRD_REG:
5269                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5270                         break;
5271
5272                 case OP_PSARD:
5273                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5274                         break;
5275                 case OP_PSARD_REG:
5276                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5277                         break;
5278
5279                 case OP_PSHLD:
5280                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5281                         break;
5282                 case OP_PSHLD_REG:
5283                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5284                         break;
5285
5286                 case OP_PSHRQ:
5287                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5288                         break;
5289                 case OP_PSHRQ_REG:
5290                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5291                         break;
5292
5293                 /*TODO: This is appart of the sse spec but not added
5294                 case OP_PSARQ:
5295                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5296                         break;
5297                 case OP_PSARQ_REG:
5298                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5299                         break;
5300                 */
5301
5302                 case OP_PSHLQ:
5303                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5304                         break;
5305                 case OP_PSHLQ_REG:
5306                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5307                         break;
5308
5309                 case OP_ICONV_TO_X:
5310                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5311                         break;
5312                 case OP_EXTRACT_I4:
5313                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5314                         break;
5315                 case OP_EXTRACT_I8:
5316                         if (ins->inst_c0) {
5317                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5318                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5319                         } else {
5320                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5321                         }
5322                         break;
5323                 case OP_EXTRACT_I1:
5324                 case OP_EXTRACT_U1:
5325                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5326                         if (ins->inst_c0)
5327                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5328                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5329                         break;
5330                 case OP_EXTRACT_I2:
5331                 case OP_EXTRACT_U2:
5332                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5333                         if (ins->inst_c0)
5334                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5335                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5336                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5337                         break;
5338                 case OP_EXTRACT_R8:
5339                         if (ins->inst_c0)
5340                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5341                         else
5342                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5343                         break;
5344                 case OP_INSERT_I2:
5345                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5346                         break;
5347                 case OP_EXTRACTX_U2:
5348                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5349                         break;
5350                 case OP_INSERTX_U1_SLOW:
5351                         /*sreg1 is the extracted ireg (scratch)
5352                         /sreg2 is the to be inserted ireg (scratch)
5353                         /dreg is the xreg to receive the value*/
5354
5355                         /*clear the bits from the extracted word*/
5356                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5357                         /*shift the value to insert if needed*/
5358                         if (ins->inst_c0 & 1)
5359                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5360                         /*join them together*/
5361                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5362                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5363                         break;
5364                 case OP_INSERTX_I4_SLOW:
5365                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5366                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5367                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5368                         break;
5369                 case OP_INSERTX_I8_SLOW:
5370                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5371                         if (ins->inst_c0)
5372                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5373                         else
5374                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5375                         break;
5376
5377                 case OP_INSERTX_R4_SLOW:
5378                         switch (ins->inst_c0) {
5379                         case 0:
5380                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5381                                 break;
5382                         case 1:
5383                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5384                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5385                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5386                                 break;
5387                         case 2:
5388                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5389                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5390                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5391                                 break;
5392                         case 3:
5393                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5394                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5395                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5396                                 break;
5397                         }
5398                         break;
5399                 case OP_INSERTX_R8_SLOW:
5400                         if (ins->inst_c0)
5401                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5402                         else
5403                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5404                         break;
5405                 case OP_STOREX_MEMBASE_REG:
5406                 case OP_STOREX_MEMBASE:
5407                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5408                         break;
5409                 case OP_LOADX_MEMBASE:
5410                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5411                         break;
5412                 case OP_LOADX_ALIGNED_MEMBASE:
5413                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5414                         break;
5415                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5416                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5417                         break;
5418                 case OP_STOREX_NTA_MEMBASE_REG:
5419                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5420                         break;
5421                 case OP_PREFETCH_MEMBASE:
5422                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5423                         break;
5424
5425                 case OP_XMOVE:
5426                         /*FIXME the peephole pass should have killed this*/
5427                         if (ins->dreg != ins->sreg1)
5428                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5429                         break;
5430                 case OP_XZERO:
5431                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5432                         break;
5433                 case OP_ICONV_TO_R8_RAW:
5434                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5435                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5436                         break;
5437
5438                 case OP_FCONV_TO_R8_X:
5439                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5440                         break;
5441
5442                 case OP_XCONV_R8_TO_I4:
5443                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5444                         switch (ins->backend.source_opcode) {
5445                         case OP_FCONV_TO_I1:
5446                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5447                                 break;
5448                         case OP_FCONV_TO_U1:
5449                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5450                                 break;
5451                         case OP_FCONV_TO_I2:
5452                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5453                                 break;
5454                         case OP_FCONV_TO_U2:
5455                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5456                                 break;
5457                         }
5458                         break;
5459
5460                 case OP_EXPAND_I2:
5461                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5462                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5463                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5464                         break;
5465                 case OP_EXPAND_I4:
5466                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5467                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5468                         break;
5469                 case OP_EXPAND_I8:
5470                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5471                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5472                         break;
5473                 case OP_EXPAND_R4:
5474                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5475                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5476                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5477                         break;
5478                 case OP_EXPAND_R8:
5479                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5480                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5481                         break;
5482 #endif
5483                 case OP_LIVERANGE_START: {
5484                         if (cfg->verbose_level > 1)
5485                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5486                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5487                         break;
5488                 }
5489                 case OP_LIVERANGE_END: {
5490                         if (cfg->verbose_level > 1)
5491                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5492                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5493                         break;
5494                 }
5495                 default:
5496                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5497                         g_assert_not_reached ();
5498                 }
5499
5500                 if ((code - cfg->native_code - offset) > max_len) {
5501                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5502                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5503                         g_assert_not_reached ();
5504                 }
5505
5506                 last_ins = ins;
5507                 last_offset = offset;
5508         }
5509
5510         cfg->code_len = code - cfg->native_code;
5511 }
5512
5513 #endif /* DISABLE_JIT */
5514
5515 void
5516 mono_arch_register_lowlevel_calls (void)
5517 {
5518         /* The signature doesn't matter */
5519         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5520 }
5521
5522 void
5523 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5524 {
5525         MonoJumpInfo *patch_info;
5526         gboolean compile_aot = !run_cctors;
5527
5528         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5529                 unsigned char *ip = patch_info->ip.i + code;
5530                 unsigned char *target;
5531
5532                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5533
5534                 if (compile_aot) {
5535                         switch (patch_info->type) {
5536                         case MONO_PATCH_INFO_BB:
5537                         case MONO_PATCH_INFO_LABEL:
5538                                 break;
5539                         default:
5540                                 /* No need to patch these */
5541                                 continue;
5542                         }
5543                 }
5544
5545                 switch (patch_info->type) {
5546                 case MONO_PATCH_INFO_NONE:
5547                         continue;
5548                 case MONO_PATCH_INFO_METHOD_REL:
5549                 case MONO_PATCH_INFO_R8:
5550                 case MONO_PATCH_INFO_R4:
5551                         g_assert_not_reached ();
5552                         continue;
5553                 case MONO_PATCH_INFO_BB:
5554                         break;
5555                 default:
5556                         break;
5557                 }
5558
5559                 /*
5560                  * Debug code to help track down problems where the target of a near call is
5561                  * is not valid.
5562                  */
5563                 if (amd64_is_near_call (ip)) {
5564                         gint64 disp = (guint8*)target - (guint8*)ip;
5565
5566                         if (!amd64_is_imm32 (disp)) {
5567                                 printf ("TYPE: %d\n", patch_info->type);
5568                                 switch (patch_info->type) {
5569                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5570                                         printf ("V: %s\n", patch_info->data.name);
5571                                         break;
5572                                 case MONO_PATCH_INFO_METHOD_JUMP:
5573                                 case MONO_PATCH_INFO_METHOD:
5574                                         printf ("V: %s\n", patch_info->data.method->name);
5575                                         break;
5576                                 default:
5577                                         break;
5578                                 }
5579                         }
5580                 }
5581
5582                 amd64_patch (ip, (gpointer)target);
5583         }
5584 }
5585
5586 static int
5587 get_max_epilog_size (MonoCompile *cfg)
5588 {
5589         int max_epilog_size = 16;
5590
5591         if (cfg->method->save_lmf)
5592                 max_epilog_size += 256;
5593
5594         if (mono_jit_trace_calls != NULL)
5595                 max_epilog_size += 50;
5596
5597         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5598                 max_epilog_size += 50;
5599
5600         max_epilog_size += (AMD64_NREG * 2);
5601
5602         return max_epilog_size;
5603 }
5604
5605 /*
5606  * This macro is used for testing whenever the unwinder works correctly at every point
5607  * where an async exception can happen.
5608  */
5609 /* This will generate a SIGSEGV at the given point in the code */
5610 #define async_exc_point(code) do { \
5611     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5612          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5613              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5614          cfg->arch.async_point_count ++; \
5615     } \
5616 } while (0)
5617
5618 guint8 *
5619 mono_arch_emit_prolog (MonoCompile *cfg)
5620 {
5621         MonoMethod *method = cfg->method;
5622         MonoBasicBlock *bb;
5623         MonoMethodSignature *sig;
5624         MonoInst *ins;
5625         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5626         guint8 *code;
5627         CallInfo *cinfo;
5628         gint32 lmf_offset = cfg->arch.lmf_offset;
5629         gboolean args_clobbered = FALSE;
5630         gboolean trace = FALSE;
5631
5632         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
5633
5634         code = cfg->native_code = g_malloc (cfg->code_size);
5635
5636         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5637                 trace = TRUE;
5638
5639         /* Amount of stack space allocated by register saving code */
5640         pos = 0;
5641
5642         /* Offset between RSP and the CFA */
5643         cfa_offset = 0;
5644
5645         /*
5646          * The prolog consists of the following parts:
5647          * FP present:
5648          * - push rbp, mov rbp, rsp
5649          * - save callee saved regs using pushes
5650          * - allocate frame
5651          * - save rgctx if needed
5652          * - save lmf if needed
5653          * FP not present:
5654          * - allocate frame
5655          * - save rgctx if needed
5656          * - save lmf if needed
5657          * - save callee saved regs using moves
5658          */
5659
5660         // CFA = sp + 8
5661         cfa_offset = 8;
5662         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5663         // IP saved at CFA - 8
5664         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5665         async_exc_point (code);
5666
5667         if (!cfg->arch.omit_fp) {
5668                 amd64_push_reg (code, AMD64_RBP);
5669                 cfa_offset += 8;
5670                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5671                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5672                 async_exc_point (code);
5673 #ifdef HOST_WIN32
5674                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5675 #endif
5676
5677                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5678                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5679                 async_exc_point (code);
5680 #ifdef HOST_WIN32
5681                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5682 #endif
5683         }
5684
5685         /* Save callee saved registers */
5686         if (!cfg->arch.omit_fp && !method->save_lmf) {
5687                 int offset = cfa_offset;
5688
5689                 for (i = 0; i < AMD64_NREG; ++i)
5690                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5691                                 amd64_push_reg (code, i);
5692                                 pos += sizeof (gpointer);
5693                                 offset += 8;
5694                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5695                                 async_exc_point (code);
5696                         }
5697         }
5698
5699         /* The param area is always at offset 0 from sp */
5700         /* This needs to be allocated here, since it has to come after the spill area */
5701         if (cfg->arch.no_pushes && cfg->param_area) {
5702                 if (cfg->arch.omit_fp)
5703                         // FIXME:
5704                         g_assert_not_reached ();
5705                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5706         }
5707
5708         if (cfg->arch.omit_fp) {
5709                 /*
5710                  * On enter, the stack is misaligned by the the pushing of the return
5711                  * address. It is either made aligned by the pushing of %rbp, or by
5712                  * this.
5713                  */
5714                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5715                 if ((alloc_size % 16) == 0)
5716                         alloc_size += 8;
5717         } else {
5718                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5719
5720                 alloc_size -= pos;
5721         }
5722
5723         cfg->arch.stack_alloc_size = alloc_size;
5724
5725         /* Allocate stack frame */
5726         if (alloc_size) {
5727                 /* See mono_emit_stack_alloc */
5728 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5729                 guint32 remaining_size = alloc_size;
5730                 while (remaining_size >= 0x1000) {
5731                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5732                         if (cfg->arch.omit_fp) {
5733                                 cfa_offset += 0x1000;
5734                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5735                         }
5736                         async_exc_point (code);
5737 #ifdef HOST_WIN32
5738                         if (cfg->arch.omit_fp)
5739                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5740 #endif
5741
5742                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5743                         remaining_size -= 0x1000;
5744                 }
5745                 if (remaining_size) {
5746                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5747                         if (cfg->arch.omit_fp) {
5748                                 cfa_offset += remaining_size;
5749                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5750                                 async_exc_point (code);
5751                         }
5752 #ifdef HOST_WIN32
5753                         if (cfg->arch.omit_fp)
5754                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5755 #endif
5756                 }
5757 #else
5758                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5759                 if (cfg->arch.omit_fp) {
5760                         cfa_offset += alloc_size;
5761                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5762                         async_exc_point (code);
5763                 }
5764 #endif
5765         }
5766
5767         /* Stack alignment check */
5768 #if 0
5769         {
5770                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5771                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5772                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5773                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5774                 amd64_breakpoint (code);
5775         }
5776 #endif
5777
5778         /* Save LMF */
5779         if (method->save_lmf) {
5780                 /*
5781                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5782                  */
5783                 /* sp is saved right before calls */
5784                 /* Skip method (only needed for trampoline LMF frames) */
5785                 /* Save callee saved regs */
5786                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5787                         int offset;
5788
5789                         switch (i) {
5790                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5791                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5792                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5793                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5794                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5795                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5796 #ifdef HOST_WIN32
5797                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5798                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5799 #endif
5800                         default:
5801                                 offset = -1;
5802                                 break;
5803                         }
5804
5805                         if (offset != -1) {
5806                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5807                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
5808                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
5809                         }
5810                 }
5811         }
5812
5813         /* Save callee saved registers */
5814         if (cfg->arch.omit_fp && !method->save_lmf) {
5815                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5816
5817                 /* Save caller saved registers after sp is adjusted */
5818                 /* The registers are saved at the bottom of the frame */
5819                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5820                 for (i = 0; i < AMD64_NREG; ++i)
5821                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5822                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5823                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5824                                 save_area_offset += 8;
5825                                 async_exc_point (code);
5826                         }
5827         }
5828
5829         /* store runtime generic context */
5830         if (cfg->rgctx_var) {
5831                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5832                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5833
5834                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5835         }
5836
5837         /* compute max_length in order to use short forward jumps */
5838         max_epilog_size = get_max_epilog_size (cfg);
5839         if (cfg->opt & MONO_OPT_BRANCH) {
5840                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5841                         MonoInst *ins;
5842                         int max_length = 0;
5843
5844                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5845                                 max_length += 6;
5846                         /* max alignment for loops */
5847                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5848                                 max_length += LOOP_ALIGNMENT;
5849
5850                         MONO_BB_FOR_EACH_INS (bb, ins) {
5851                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5852                         }
5853
5854                         /* Take prolog and epilog instrumentation into account */
5855                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
5856                                 max_length += max_epilog_size;
5857
5858                         bb->max_length = max_length;
5859                 }
5860         }
5861
5862         sig = mono_method_signature (method);
5863         pos = 0;
5864
5865         cinfo = cfg->arch.cinfo;
5866
5867         if (sig->ret->type != MONO_TYPE_VOID) {
5868                 /* Save volatile arguments to the stack */
5869                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5870                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5871         }
5872
5873         /* Keep this in sync with emit_load_volatile_arguments */
5874         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5875                 ArgInfo *ainfo = cinfo->args + i;
5876                 gint32 stack_offset;
5877                 MonoType *arg_type;
5878
5879                 ins = cfg->args [i];
5880
5881                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5882                         /* Unused arguments */
5883                         continue;
5884
5885                 if (sig->hasthis && (i == 0))
5886                         arg_type = &mono_defaults.object_class->byval_arg;
5887                 else
5888                         arg_type = sig->params [i - sig->hasthis];
5889
5890                 stack_offset = ainfo->offset + ARGS_OFFSET;
5891
5892                 if (cfg->globalra) {
5893                         /* All the other moves are done by the register allocator */
5894                         switch (ainfo->storage) {
5895                         case ArgInFloatSSEReg:
5896                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5897                                 break;
5898                         case ArgValuetypeInReg:
5899                                 for (quad = 0; quad < 2; quad ++) {
5900                                         switch (ainfo->pair_storage [quad]) {
5901                                         case ArgInIReg:
5902                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5903                                                 break;
5904                                         case ArgInFloatSSEReg:
5905                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5906                                                 break;
5907                                         case ArgInDoubleSSEReg:
5908                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5909                                                 break;
5910                                         case ArgNone:
5911                                                 break;
5912                                         default:
5913                                                 g_assert_not_reached ();
5914                                         }
5915                                 }
5916                                 break;
5917                         default:
5918                                 break;
5919                         }
5920
5921                         continue;
5922                 }
5923
5924                 /* Save volatile arguments to the stack */
5925                 if (ins->opcode != OP_REGVAR) {
5926                         switch (ainfo->storage) {
5927                         case ArgInIReg: {
5928                                 guint32 size = 8;
5929
5930                                 /* FIXME: I1 etc */
5931                                 /*
5932                                 if (stack_offset & 0x1)
5933                                         size = 1;
5934                                 else if (stack_offset & 0x2)
5935                                         size = 2;
5936                                 else if (stack_offset & 0x4)
5937                                         size = 4;
5938                                 else
5939                                         size = 8;
5940                                 */
5941                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5942                                 break;
5943                         }
5944                         case ArgInFloatSSEReg:
5945                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5946                                 break;
5947                         case ArgInDoubleSSEReg:
5948                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5949                                 break;
5950                         case ArgValuetypeInReg:
5951                                 for (quad = 0; quad < 2; quad ++) {
5952                                         switch (ainfo->pair_storage [quad]) {
5953                                         case ArgInIReg:
5954                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5955                                                 break;
5956                                         case ArgInFloatSSEReg:
5957                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5958                                                 break;
5959                                         case ArgInDoubleSSEReg:
5960                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5961                                                 break;
5962                                         case ArgNone:
5963                                                 break;
5964                                         default:
5965                                                 g_assert_not_reached ();
5966                                         }
5967                                 }
5968                                 break;
5969                         case ArgValuetypeAddrInIReg:
5970                                 if (ainfo->pair_storage [0] == ArgInIReg)
5971                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
5972                                 break;
5973                         default:
5974                                 break;
5975                         }
5976                 } else {
5977                         /* Argument allocated to (non-volatile) register */
5978                         switch (ainfo->storage) {
5979                         case ArgInIReg:
5980                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
5981                                 break;
5982                         case ArgOnStack:
5983                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5984                                 break;
5985                         default:
5986                                 g_assert_not_reached ();
5987                         }
5988                 }
5989         }
5990
5991         /* Might need to attach the thread to the JIT  or change the domain for the callback */
5992         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5993                 guint64 domain = (guint64)cfg->domain;
5994
5995                 args_clobbered = TRUE;
5996
5997                 /*
5998                  * The call might clobber argument registers, but they are already
5999                  * saved to the stack/global regs.
6000                  */
6001                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6002                         guint8 *buf, *no_domain_branch;
6003
6004                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6005                         if (cfg->compile_aot) {
6006                                 /* AOT code is only used in the root domain */
6007                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6008                         } else {
6009                                 if ((domain >> 32) == 0)
6010                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6011                                 else
6012                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6013                         }
6014                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6015                         no_domain_branch = code;
6016                         x86_branch8 (code, X86_CC_NE, 0, 0);
6017                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6018                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6019                         buf = code;
6020                         x86_branch8 (code, X86_CC_NE, 0, 0);
6021                         amd64_patch (no_domain_branch, code);
6022                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6023                                           (gpointer)"mono_jit_thread_attach", TRUE);
6024                         amd64_patch (buf, code);
6025 #ifdef HOST_WIN32
6026                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6027                         /* FIXME: Add a separate key for LMF to avoid this */
6028                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6029 #endif
6030                 } else {
6031                         g_assert (!cfg->compile_aot);
6032                         if (cfg->compile_aot) {
6033                                 /* AOT code is only used in the root domain */
6034                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6035                         } else {
6036                                 if ((domain >> 32) == 0)
6037                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6038                                 else
6039                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6040                         }
6041                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6042                                           (gpointer)"mono_jit_thread_attach", TRUE);
6043                 }
6044         }
6045
6046         if (method->save_lmf) {
6047                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6048                         /*
6049                          * Optimized version which uses the mono_lmf TLS variable instead of
6050                          * indirection through the mono_lmf_addr TLS variable.
6051                          */
6052                         /* %rax = previous_lmf */
6053                         x86_prefix (code, X86_FS_PREFIX);
6054                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6055
6056                         /* Save previous_lmf */
6057                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6058                         /* Set new lmf */
6059                         if (lmf_offset == 0) {
6060                                 x86_prefix (code, X86_FS_PREFIX);
6061                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6062                         } else {
6063                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6064                                 x86_prefix (code, X86_FS_PREFIX);
6065                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6066                         }
6067                 } else {
6068                         if (lmf_addr_tls_offset != -1) {
6069                                 /* Load lmf quicky using the FS register */
6070                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6071 #ifdef HOST_WIN32
6072                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6073                                 /* FIXME: Add a separate key for LMF to avoid this */
6074                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6075 #endif
6076                         }
6077                         else {
6078                                 /*
6079                                  * The call might clobber argument registers, but they are already
6080                                  * saved to the stack/global regs.
6081                                  */
6082                                 args_clobbered = TRUE;
6083                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6084                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6085                         }
6086
6087                         /* Save lmf_addr */
6088                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6089                         /* Save previous_lmf */
6090                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6091                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6092                         /* Set new lmf */
6093                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6094                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6095                 }
6096         }
6097
6098         if (trace) {
6099                 args_clobbered = TRUE;
6100                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6101         }
6102
6103         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6104                 args_clobbered = TRUE;
6105
6106         /*
6107          * Optimize the common case of the first bblock making a call with the same
6108          * arguments as the method. This works because the arguments are still in their
6109          * original argument registers.
6110          * FIXME: Generalize this
6111          */
6112         if (!args_clobbered) {
6113                 MonoBasicBlock *first_bb = cfg->bb_entry;
6114                 MonoInst *next;
6115
6116                 next = mono_bb_first_ins (first_bb);
6117                 if (!next && first_bb->next_bb) {
6118                         first_bb = first_bb->next_bb;
6119                         next = mono_bb_first_ins (first_bb);
6120                 }
6121
6122                 if (first_bb->in_count > 1)
6123                         next = NULL;
6124
6125                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6126                         ArgInfo *ainfo = cinfo->args + i;
6127                         gboolean match = FALSE;
6128
6129                         ins = cfg->args [i];
6130                         if (ins->opcode != OP_REGVAR) {
6131                                 switch (ainfo->storage) {
6132                                 case ArgInIReg: {
6133                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6134                                                 if (next->dreg == ainfo->reg) {
6135                                                         NULLIFY_INS (next);
6136                                                         match = TRUE;
6137                                                 } else {
6138                                                         next->opcode = OP_MOVE;
6139                                                         next->sreg1 = ainfo->reg;
6140                                                         /* Only continue if the instruction doesn't change argument regs */
6141                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6142                                                                 match = TRUE;
6143                                                 }
6144                                         }
6145                                         break;
6146                                 }
6147                                 default:
6148                                         break;
6149                                 }
6150                         } else {
6151                                 /* Argument allocated to (non-volatile) register */
6152                                 switch (ainfo->storage) {
6153                                 case ArgInIReg:
6154                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6155                                                 NULLIFY_INS (next);
6156                                                 match = TRUE;
6157                                         }
6158                                         break;
6159                                 default:
6160                                         break;
6161                                 }
6162                         }
6163
6164                         if (match) {
6165                                 next = next->next;
6166                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6167                                 if (!next)
6168                                         break;
6169                         }
6170                 }
6171         }
6172
6173         cfg->code_len = code - cfg->native_code;
6174
6175         g_assert (cfg->code_len < cfg->code_size);
6176
6177         return code;
6178 }
6179
6180 void
6181 mono_arch_emit_epilog (MonoCompile *cfg)
6182 {
6183         MonoMethod *method = cfg->method;
6184         int quad, pos, i;
6185         guint8 *code;
6186         int max_epilog_size;
6187         CallInfo *cinfo;
6188         gint32 lmf_offset = cfg->arch.lmf_offset;
6189
6190         max_epilog_size = get_max_epilog_size (cfg);
6191
6192         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6193                 cfg->code_size *= 2;
6194                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6195                 mono_jit_stats.code_reallocs++;
6196         }
6197
6198         code = cfg->native_code + cfg->code_len;
6199
6200         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6201                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6202
6203         /* the code restoring the registers must be kept in sync with OP_JMP */
6204         pos = 0;
6205
6206         if (method->save_lmf) {
6207                 /* check if we need to restore protection of the stack after a stack overflow */
6208                 if (mono_get_jit_tls_offset () != -1) {
6209                         guint8 *patch;
6210                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6211                         /* we load the value in a separate instruction: this mechanism may be
6212                          * used later as a safer way to do thread interruption
6213                          */
6214                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6215                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6216                         patch = code;
6217                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6218                         /* note that the call trampoline will preserve eax/edx */
6219                         x86_call_reg (code, X86_ECX);
6220                         x86_patch (patch, code);
6221                 } else {
6222                         /* FIXME: maybe save the jit tls in the prolog */
6223                 }
6224                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6225                         /*
6226                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6227                          * through the mono_lmf_addr TLS variable.
6228                          */
6229                         /* reg = previous_lmf */
6230                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6231                         x86_prefix (code, X86_FS_PREFIX);
6232                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6233                 } else {
6234                         /* Restore previous lmf */
6235                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6236                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6237                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6238                 }
6239
6240                 /* Restore caller saved regs */
6241                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6242                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6243                 }
6244                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6245                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6246                 }
6247                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6248                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6249                 }
6250                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6251                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6252                 }
6253                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6254                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6255                 }
6256                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6257                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6258                 }
6259 #ifdef HOST_WIN32
6260                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6261                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6262                 }
6263                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6264                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6265                 }
6266 #endif
6267         } else {
6268
6269                 if (cfg->arch.omit_fp) {
6270                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6271
6272                         for (i = 0; i < AMD64_NREG; ++i)
6273                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6274                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6275                                         save_area_offset += 8;
6276                                 }
6277                 }
6278                 else {
6279                         for (i = 0; i < AMD64_NREG; ++i)
6280                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6281                                         pos -= sizeof (gpointer);
6282
6283                         if (pos) {
6284                                 if (pos == - sizeof (gpointer)) {
6285                                         /* Only one register, so avoid lea */
6286                                         for (i = AMD64_NREG - 1; i > 0; --i)
6287                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6288                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6289                                                 }
6290                                 }
6291                                 else {
6292                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6293
6294                                         /* Pop registers in reverse order */
6295                                         for (i = AMD64_NREG - 1; i > 0; --i)
6296                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6297                                                         amd64_pop_reg (code, i);
6298                                                 }
6299                                 }
6300                         }
6301                 }
6302         }
6303
6304         /* Load returned vtypes into registers if needed */
6305         cinfo = cfg->arch.cinfo;
6306         if (cinfo->ret.storage == ArgValuetypeInReg) {
6307                 ArgInfo *ainfo = &cinfo->ret;
6308                 MonoInst *inst = cfg->ret;
6309
6310                 for (quad = 0; quad < 2; quad ++) {
6311                         switch (ainfo->pair_storage [quad]) {
6312                         case ArgInIReg:
6313                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6314                                 break;
6315                         case ArgInFloatSSEReg:
6316                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6317                                 break;
6318                         case ArgInDoubleSSEReg:
6319                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6320                                 break;
6321                         case ArgNone:
6322                                 break;
6323                         default:
6324                                 g_assert_not_reached ();
6325                         }
6326                 }
6327         }
6328
6329         if (cfg->arch.omit_fp) {
6330                 if (cfg->arch.stack_alloc_size)
6331                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6332         } else {
6333                 amd64_leave (code);
6334         }
6335         async_exc_point (code);
6336         amd64_ret (code);
6337
6338         cfg->code_len = code - cfg->native_code;
6339
6340         g_assert (cfg->code_len < cfg->code_size);
6341 }
6342
6343 void
6344 mono_arch_emit_exceptions (MonoCompile *cfg)
6345 {
6346         MonoJumpInfo *patch_info;
6347         int nthrows, i;
6348         guint8 *code;
6349         MonoClass *exc_classes [16];
6350         guint8 *exc_throw_start [16], *exc_throw_end [16];
6351         guint32 code_size = 0;
6352
6353         /* Compute needed space */
6354         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6355                 if (patch_info->type == MONO_PATCH_INFO_EXC)
6356                         code_size += 40;
6357                 if (patch_info->type == MONO_PATCH_INFO_R8)
6358                         code_size += 8 + 15; /* sizeof (double) + alignment */
6359                 if (patch_info->type == MONO_PATCH_INFO_R4)
6360                         code_size += 4 + 15; /* sizeof (float) + alignment */
6361         }
6362
6363         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6364                 cfg->code_size *= 2;
6365                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6366                 mono_jit_stats.code_reallocs++;
6367         }
6368
6369         code = cfg->native_code + cfg->code_len;
6370
6371         /* add code to raise exceptions */
6372         nthrows = 0;
6373         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6374                 switch (patch_info->type) {
6375                 case MONO_PATCH_INFO_EXC: {
6376                         MonoClass *exc_class;
6377                         guint8 *buf, *buf2;
6378                         guint32 throw_ip;
6379
6380                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
6381
6382                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6383                         g_assert (exc_class);
6384                         throw_ip = patch_info->ip.i;
6385
6386                         //x86_breakpoint (code);
6387                         /* Find a throw sequence for the same exception class */
6388                         for (i = 0; i < nthrows; ++i)
6389                                 if (exc_classes [i] == exc_class)
6390                                         break;
6391                         if (i < nthrows) {
6392                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6393                                 x86_jump_code (code, exc_throw_start [i]);
6394                                 patch_info->type = MONO_PATCH_INFO_NONE;
6395                         }
6396                         else {
6397                                 buf = code;
6398                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6399                                 buf2 = code;
6400
6401                                 if (nthrows < 16) {
6402                                         exc_classes [nthrows] = exc_class;
6403                                         exc_throw_start [nthrows] = code;
6404                                 }
6405                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
6406
6407                                 patch_info->type = MONO_PATCH_INFO_NONE;
6408
6409                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6410
6411                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6412                                 while (buf < buf2)
6413                                         x86_nop (buf);
6414
6415                                 if (nthrows < 16) {
6416                                         exc_throw_end [nthrows] = code;
6417                                         nthrows ++;
6418                                 }
6419                         }
6420                         break;
6421                 }
6422                 default:
6423                         /* do nothing */
6424                         break;
6425                 }
6426         }
6427
6428         /* Handle relocations with RIP relative addressing */
6429         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6430                 gboolean remove = FALSE;
6431
6432                 switch (patch_info->type) {
6433                 case MONO_PATCH_INFO_R8:
6434                 case MONO_PATCH_INFO_R4: {
6435                         guint8 *pos;
6436
6437                         /* The SSE opcodes require a 16 byte alignment */
6438                         code = (guint8*)ALIGN_TO (code, 16);
6439
6440                         pos = cfg->native_code + patch_info->ip.i;
6441
6442                         if (IS_REX (pos [1]))
6443                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6444                         else
6445                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6446
6447                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6448                                 *(double*)code = *(double*)patch_info->data.target;
6449                                 code += sizeof (double);
6450                         } else {
6451                                 *(float*)code = *(float*)patch_info->data.target;
6452                                 code += sizeof (float);
6453                         }
6454
6455                         remove = TRUE;
6456                         break;
6457                 }
6458                 default:
6459                         break;
6460                 }
6461
6462                 if (remove) {
6463                         if (patch_info == cfg->patch_info)
6464                                 cfg->patch_info = patch_info->next;
6465                         else {
6466                                 MonoJumpInfo *tmp;
6467
6468                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6469                                         ;
6470                                 tmp->next = patch_info->next;
6471                         }
6472                 }
6473         }
6474
6475         cfg->code_len = code - cfg->native_code;
6476
6477         g_assert (cfg->code_len < cfg->code_size);
6478
6479 }
6480
6481 void*
6482 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6483 {
6484         guchar *code = p;
6485         CallInfo *cinfo = NULL;
6486         MonoMethodSignature *sig;
6487         MonoInst *inst;
6488         int i, n, stack_area = 0;
6489
6490         /* Keep this in sync with mono_arch_get_argument_info */
6491
6492         if (enable_arguments) {
6493                 /* Allocate a new area on the stack and save arguments there */
6494                 sig = mono_method_signature (cfg->method);
6495
6496                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6497
6498                 n = sig->param_count + sig->hasthis;
6499
6500                 stack_area = ALIGN_TO (n * 8, 16);
6501
6502                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6503
6504                 for (i = 0; i < n; ++i) {
6505                         inst = cfg->args [i];
6506
6507                         if (inst->opcode == OP_REGVAR)
6508                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6509                         else {
6510                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6511                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6512                         }
6513                 }
6514         }
6515
6516         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6517         amd64_set_reg_template (code, AMD64_ARG_REG1);
6518         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6519         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6520
6521         if (enable_arguments)
6522                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6523
6524         return code;
6525 }
6526
6527 enum {
6528         SAVE_NONE,
6529         SAVE_STRUCT,
6530         SAVE_EAX,
6531         SAVE_EAX_EDX,
6532         SAVE_XMM
6533 };
6534
6535 void*
6536 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6537 {
6538         guchar *code = p;
6539         int save_mode = SAVE_NONE;
6540         MonoMethod *method = cfg->method;
6541         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
6542
6543         switch (rtype) {
6544         case MONO_TYPE_VOID:
6545                 /* special case string .ctor icall */
6546                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6547                         save_mode = SAVE_EAX;
6548                 else
6549                         save_mode = SAVE_NONE;
6550                 break;
6551         case MONO_TYPE_I8:
6552         case MONO_TYPE_U8:
6553                 save_mode = SAVE_EAX;
6554                 break;
6555         case MONO_TYPE_R4:
6556         case MONO_TYPE_R8:
6557                 save_mode = SAVE_XMM;
6558                 break;
6559         case MONO_TYPE_GENERICINST:
6560                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
6561                         save_mode = SAVE_EAX;
6562                         break;
6563                 }
6564                 /* Fall through */
6565         case MONO_TYPE_VALUETYPE:
6566                 save_mode = SAVE_STRUCT;
6567                 break;
6568         default:
6569                 save_mode = SAVE_EAX;
6570                 break;
6571         }
6572
6573         /* Save the result and copy it into the proper argument register */
6574         switch (save_mode) {
6575         case SAVE_EAX:
6576                 amd64_push_reg (code, AMD64_RAX);
6577                 /* Align stack */
6578                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6579                 if (enable_arguments)
6580                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6581                 break;
6582         case SAVE_STRUCT:
6583                 /* FIXME: */
6584                 if (enable_arguments)
6585                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6586                 break;
6587         case SAVE_XMM:
6588                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6589                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6590                 /* Align stack */
6591                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6592                 /*
6593                  * The result is already in the proper argument register so no copying
6594                  * needed.
6595                  */
6596                 break;
6597         case SAVE_NONE:
6598                 break;
6599         default:
6600                 g_assert_not_reached ();
6601         }
6602
6603         /* Set %al since this is a varargs call */
6604         if (save_mode == SAVE_XMM)
6605                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6606         else
6607                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6608
6609         if (preserve_argument_registers) {
6610                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6611                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6612         }
6613
6614         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6615         amd64_set_reg_template (code, AMD64_ARG_REG1);
6616         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6617
6618         if (preserve_argument_registers) {
6619                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6620                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6621         }
6622
6623         /* Restore result */
6624         switch (save_mode) {
6625         case SAVE_EAX:
6626                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6627                 amd64_pop_reg (code, AMD64_RAX);
6628                 break;
6629         case SAVE_STRUCT:
6630                 /* FIXME: */
6631                 break;
6632         case SAVE_XMM:
6633                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6634                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6635                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6636                 break;
6637         case SAVE_NONE:
6638                 break;
6639         default:
6640                 g_assert_not_reached ();
6641         }
6642
6643         return code;
6644 }
6645
6646 void
6647 mono_arch_flush_icache (guint8 *code, gint size)
6648 {
6649         /* Not needed */
6650 }
6651
6652 void
6653 mono_arch_flush_register_windows (void)
6654 {
6655 }
6656
6657 gboolean
6658 mono_arch_is_inst_imm (gint64 imm)
6659 {
6660         return amd64_is_imm32 (imm);
6661 }
6662
6663 /*
6664  * Determine whenever the trap whose info is in SIGINFO is caused by
6665  * integer overflow.
6666  */
6667 gboolean
6668 mono_arch_is_int_overflow (void *sigctx, void *info)
6669 {
6670         MonoContext ctx;
6671         guint8* rip;
6672         int reg;
6673         gint64 value;
6674
6675         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6676
6677         rip = (guint8*)ctx.rip;
6678
6679         if (IS_REX (rip [0])) {
6680                 reg = amd64_rex_b (rip [0]);
6681                 rip ++;
6682         }
6683         else
6684                 reg = 0;
6685
6686         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6687                 /* idiv REG */
6688                 reg += x86_modrm_rm (rip [1]);
6689
6690                 switch (reg) {
6691                 case AMD64_RAX:
6692                         value = ctx.rax;
6693                         break;
6694                 case AMD64_RBX:
6695                         value = ctx.rbx;
6696                         break;
6697                 case AMD64_RCX:
6698                         value = ctx.rcx;
6699                         break;
6700                 case AMD64_RDX:
6701                         value = ctx.rdx;
6702                         break;
6703                 case AMD64_RBP:
6704                         value = ctx.rbp;
6705                         break;
6706                 case AMD64_RSP:
6707                         value = ctx.rsp;
6708                         break;
6709                 case AMD64_RSI:
6710                         value = ctx.rsi;
6711                         break;
6712                 case AMD64_RDI:
6713                         value = ctx.rdi;
6714                         break;
6715                 case AMD64_R12:
6716                         value = ctx.r12;
6717                         break;
6718                 case AMD64_R13:
6719                         value = ctx.r13;
6720                         break;
6721                 case AMD64_R14:
6722                         value = ctx.r14;
6723                         break;
6724                 case AMD64_R15:
6725                         value = ctx.r15;
6726                         break;
6727                 default:
6728                         g_assert_not_reached ();
6729                         reg = -1;
6730                 }
6731
6732                 if (value == -1)
6733                         return TRUE;
6734         }
6735
6736         return FALSE;
6737 }
6738
6739 guint32
6740 mono_arch_get_patch_offset (guint8 *code)
6741 {
6742         return 3;
6743 }
6744
6745 /**
6746  * mono_breakpoint_clean_code:
6747  *
6748  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6749  * breakpoints in the original code, they are removed in the copy.
6750  *
6751  * Returns TRUE if no sw breakpoint was present.
6752  */
6753 gboolean
6754 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6755 {
6756         int i;
6757         gboolean can_write = TRUE;
6758         /*
6759          * If method_start is non-NULL we need to perform bound checks, since we access memory
6760          * at code - offset we could go before the start of the method and end up in a different
6761          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6762          * instead.
6763          */
6764         if (!method_start || code - offset >= method_start) {
6765                 memcpy (buf, code - offset, size);
6766         } else {
6767                 int diff = code - method_start;
6768                 memset (buf, 0, size);
6769                 memcpy (buf + offset - diff, method_start, diff + size - offset);
6770         }
6771         code -= offset;
6772         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6773                 int idx = mono_breakpoint_info_index [i];
6774                 guint8 *ptr;
6775                 if (idx < 1)
6776                         continue;
6777                 ptr = mono_breakpoint_info [idx].address;
6778                 if (ptr >= code && ptr < code + size) {
6779                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6780                         can_write = FALSE;
6781                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6782                         buf [ptr - code] = saved_byte;
6783                 }
6784         }
6785         return can_write;
6786 }
6787
6788 gpointer
6789 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
6790 {
6791         guint8 buf [10];
6792         guint32 reg;
6793         gint32 disp;
6794         guint8 rex = 0;
6795         MonoJitInfo *ji = NULL;
6796
6797 #ifdef ENABLE_LLVM
6798         /* code - 9 might be before the start of the method */
6799         /* FIXME: Avoid this expensive call somehow */
6800         ji = mono_jit_info_table_find (mono_domain_get (), (char*)code);
6801 #endif
6802
6803         mono_breakpoint_clean_code (ji ? ji->code_start : NULL, code, 9, buf, sizeof (buf));
6804         code = buf + 9;
6805
6806         *displacement = 0;
6807
6808         code -= 7;
6809
6810         /*
6811          * A given byte sequence can match more than case here, so we have to be
6812          * really careful about the ordering of the cases. Longer sequences
6813          * come first.
6814          * There are two types of calls:
6815          * - direct calls: 0xff address_byte 8/32 bits displacement
6816          * - indirect calls: nop nop nop <call>
6817          * The nops make sure we don't confuse the instruction preceeding an indirect
6818          * call with a direct call.
6819          */
6820         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
6821                 /* call OFFSET(%rip) */
6822                 disp = *(guint32*)(code + 3);
6823                 return (gpointer*)(code + disp + 7);
6824         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
6825                 /* call *[reg+disp32] using indexed addressing */
6826                 /* The LLVM JIT emits this, and we emit it too for %r12 */
6827                 if (IS_REX (code [-1])) {
6828                         rex = code [-1];
6829                         g_assert (amd64_rex_x (rex) == 0);
6830                 }
6831                 reg = amd64_sib_base (code [2]);
6832                 disp = *(gint32*)(code + 3);
6833         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
6834                 /* call *[reg+disp32] */
6835                 if (IS_REX (code [0]))
6836                         rex = code [0];
6837                 reg = amd64_modrm_rm (code [2]);
6838                 disp = *(gint32*)(code + 3);
6839                 /* R10 is clobbered by the IMT thunk code */
6840                 g_assert (reg != AMD64_R10);
6841         } else if (code [2] == 0xe8) {
6842                 /* call <ADDR> */
6843                 return NULL;
6844         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
6845                 /* call *[r12+disp8] using indexed addressing */
6846                 if (IS_REX (code [2]))
6847                         rex = code [2];
6848                 reg = amd64_sib_base (code [5]);
6849                 disp = *(gint8*)(code + 6);
6850         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
6851                 /* call *%reg */
6852                 return NULL;
6853         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
6854                 /* call *[reg+disp8] */
6855                 if (IS_REX (code [3]))
6856                         rex = code [3];
6857                 reg = amd64_modrm_rm (code [5]);
6858                 disp = *(gint8*)(code + 6);
6859                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6860         }
6861         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6862                 /* call *%reg */
6863                 if (IS_REX (code [4]))
6864                         rex = code [4];
6865                 reg = amd64_modrm_rm (code [6]);
6866                 disp = 0;
6867         }
6868         else
6869                 g_assert_not_reached ();
6870
6871         reg += amd64_rex_b (rex);
6872
6873         /* R11 is clobbered by the trampoline code */
6874         g_assert (reg != AMD64_R11);
6875
6876         *displacement = disp;
6877         return (gpointer)regs [reg];
6878 }
6879
6880 int
6881 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6882 {
6883         int this_reg = AMD64_ARG_REG1;
6884
6885         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6886                 CallInfo *cinfo;
6887
6888                 if (!gsctx && code)
6889                         gsctx = mono_get_generic_context_from_code (code);
6890
6891                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6892
6893                 if (cinfo->ret.storage != ArgValuetypeInReg)
6894                         this_reg = AMD64_ARG_REG2;
6895                 g_free (cinfo);
6896         }
6897
6898         return this_reg;
6899 }
6900
6901 gpointer
6902 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
6903 {
6904         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6905 }
6906
6907 #define MAX_ARCH_DELEGATE_PARAMS 10
6908
6909 static gpointer
6910 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6911 {
6912         guint8 *code, *start;
6913         int i;
6914
6915         if (has_target) {
6916                 start = code = mono_global_codeman_reserve (64);
6917
6918                 /* Replace the this argument with the target */
6919                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6920                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6921                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6922
6923                 g_assert ((code - start) < 64);
6924         } else {
6925                 start = code = mono_global_codeman_reserve (64);
6926
6927                 if (param_count == 0) {
6928                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6929                 } else {
6930                         /* We have to shift the arguments left */
6931                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6932                         for (i = 0; i < param_count; ++i) {
6933 #ifdef HOST_WIN32
6934                                 if (i < 3)
6935                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6936                                 else
6937                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
6938 #else
6939                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6940 #endif
6941                         }
6942
6943                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6944                 }
6945                 g_assert ((code - start) < 64);
6946         }
6947
6948         mono_debug_add_delegate_trampoline (start, code - start);
6949
6950         if (code_len)
6951                 *code_len = code - start;
6952
6953         return start;
6954 }
6955
6956 /*
6957  * mono_arch_get_delegate_invoke_impls:
6958  *
6959  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
6960  * trampolines.
6961  */
6962 GSList*
6963 mono_arch_get_delegate_invoke_impls (void)
6964 {
6965         GSList *res = NULL;
6966         guint8 *code;
6967         guint32 code_len;
6968         int i;
6969
6970         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6971         res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len));
6972
6973         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6974                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6975                 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len));
6976         }
6977
6978         return res;
6979 }
6980
6981 gpointer
6982 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6983 {
6984         guint8 *code, *start;
6985         int i;
6986
6987         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6988                 return NULL;
6989
6990         /* FIXME: Support more cases */
6991         if (MONO_TYPE_ISSTRUCT (sig->ret))
6992                 return NULL;
6993
6994         if (has_target) {
6995                 static guint8* cached = NULL;
6996
6997                 if (cached)
6998                         return cached;
6999
7000                 if (mono_aot_only)
7001                         start = mono_aot_get_named_code ("delegate_invoke_impl_has_target");
7002                 else
7003                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7004
7005                 mono_memory_barrier ();
7006
7007                 cached = start;
7008         } else {
7009                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7010                 for (i = 0; i < sig->param_count; ++i)
7011                         if (!mono_is_regsize_var (sig->params [i]))
7012                                 return NULL;
7013                 if (sig->param_count > 4)
7014                         return NULL;
7015
7016                 code = cache [sig->param_count];
7017                 if (code)
7018                         return code;
7019
7020                 if (mono_aot_only) {
7021                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7022                         start = mono_aot_get_named_code (name);
7023                         g_free (name);
7024                 } else {
7025                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7026                 }
7027
7028                 mono_memory_barrier ();
7029
7030                 cache [sig->param_count] = start;
7031         }
7032
7033         return start;
7034 }
7035
7036 /*
7037  * Support for fast access to the thread-local lmf structure using the GS
7038  * segment register on NPTL + kernel 2.6.x.
7039  */
7040
7041 static gboolean tls_offset_inited = FALSE;
7042
7043 void
7044 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7045 {
7046         if (!tls_offset_inited) {
7047 #ifdef HOST_WIN32
7048                 /*
7049                  * We need to init this multiple times, since when we are first called, the key might not
7050                  * be initialized yet.
7051                  */
7052                 appdomain_tls_offset = mono_domain_get_tls_key ();
7053                 lmf_tls_offset = mono_get_jit_tls_key ();
7054                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7055
7056                 /* Only 64 tls entries can be accessed using inline code */
7057                 if (appdomain_tls_offset >= 64)
7058                         appdomain_tls_offset = -1;
7059                 if (lmf_tls_offset >= 64)
7060                         lmf_tls_offset = -1;
7061 #else
7062                 tls_offset_inited = TRUE;
7063 #ifdef MONO_XEN_OPT
7064                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7065 #endif
7066                 appdomain_tls_offset = mono_domain_get_tls_offset ();
7067                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7068                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7069 #endif
7070         }
7071 }
7072
7073 void
7074 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7075 {
7076 }
7077
7078 #ifdef MONO_ARCH_HAVE_IMT
7079
7080 #define CMP_SIZE (6 + 1)
7081 #define CMP_REG_REG_SIZE (4 + 1)
7082 #define BR_SMALL_SIZE 2
7083 #define BR_LARGE_SIZE 6
7084 #define MOV_REG_IMM_SIZE 10
7085 #define MOV_REG_IMM_32BIT_SIZE 6
7086 #define JUMP_REG_SIZE (2 + 1)
7087
7088 static int
7089 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7090 {
7091         int i, distance = 0;
7092         for (i = start; i < target; ++i)
7093                 distance += imt_entries [i]->chunk_size;
7094         return distance;
7095 }
7096
7097 /*
7098  * LOCKING: called with the domain lock held
7099  */
7100 gpointer
7101 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7102         gpointer fail_tramp)
7103 {
7104         int i;
7105         int size = 0;
7106         guint8 *code, *start;
7107         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7108
7109         for (i = 0; i < count; ++i) {
7110                 MonoIMTCheckItem *item = imt_entries [i];
7111                 if (item->is_equals) {
7112                         if (item->check_target_idx) {
7113                                 if (!item->compare_done) {
7114                                         if (amd64_is_imm32 (item->key))
7115                                                 item->chunk_size += CMP_SIZE;
7116                                         else
7117                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7118                                 }
7119                                 if (item->has_target_code) {
7120                                         item->chunk_size += MOV_REG_IMM_SIZE;
7121                                 } else {
7122                                         if (vtable_is_32bit)
7123                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7124                                         else
7125                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7126                                 }
7127                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7128                         } else {
7129                                 if (fail_tramp) {
7130                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7131                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7132                                 } else {
7133                                         if (vtable_is_32bit)
7134                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7135                                         else
7136                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7137                                         item->chunk_size += JUMP_REG_SIZE;
7138                                         /* with assert below:
7139                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7140                                          */
7141                                 }
7142                         }
7143                 } else {
7144                         if (amd64_is_imm32 (item->key))
7145                                 item->chunk_size += CMP_SIZE;
7146                         else
7147                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7148                         item->chunk_size += BR_LARGE_SIZE;
7149                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7150                 }
7151                 size += item->chunk_size;
7152         }
7153         if (fail_tramp)
7154                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7155         else
7156                 code = mono_domain_code_reserve (domain, size);
7157         start = code;
7158         for (i = 0; i < count; ++i) {
7159                 MonoIMTCheckItem *item = imt_entries [i];
7160                 item->code_target = code;
7161                 if (item->is_equals) {
7162                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7163
7164                         if (item->check_target_idx || fail_case) {
7165                                 if (!item->compare_done || fail_case) {
7166                                         if (amd64_is_imm32 (item->key))
7167                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7168                                         else {
7169                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7170                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7171                                         }
7172                                 }
7173                                 item->jmp_code = code;
7174                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7175                                 /* See the comment below about R10 */
7176                                 if (item->has_target_code) {
7177                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
7178                                         amd64_jump_reg (code, AMD64_R10);
7179                                 } else {
7180                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7181                                         amd64_jump_membase (code, AMD64_R10, 0);
7182                                 }
7183
7184                                 if (fail_case) {
7185                                         amd64_patch (item->jmp_code, code);
7186                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
7187                                         amd64_jump_reg (code, AMD64_R10);
7188                                         item->jmp_code = NULL;
7189                                 }
7190                         } else {
7191                                 /* enable the commented code to assert on wrong method */
7192 #if 0
7193                                 if (amd64_is_imm32 (item->key))
7194                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7195                                 else {
7196                                         amd64_mov_reg_imm (code, AMD64_R10, item->key);
7197                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7198                                 }
7199                                 item->jmp_code = code;
7200                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7201                                 /* See the comment below about R10 */
7202                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7203                                 amd64_jump_membase (code, AMD64_R10, 0);
7204                                 amd64_patch (item->jmp_code, code);
7205                                 amd64_breakpoint (code);
7206                                 item->jmp_code = NULL;
7207 #else
7208                                 /* We're using R10 here because R11
7209                                    needs to be preserved.  R10 needs
7210                                    to be preserved for calls which
7211                                    require a runtime generic context,
7212                                    but interface calls don't. */
7213                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7214                                 amd64_jump_membase (code, AMD64_R10, 0);
7215 #endif
7216                         }
7217                 } else {
7218                         if (amd64_is_imm32 (item->key))
7219                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7220                         else {
7221                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7222                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7223                         }
7224                         item->jmp_code = code;
7225                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7226                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7227                         else
7228                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7229                 }
7230                 g_assert (code - item->code_target <= item->chunk_size);
7231         }
7232         /* patch the branches to get to the target items */
7233         for (i = 0; i < count; ++i) {
7234                 MonoIMTCheckItem *item = imt_entries [i];
7235                 if (item->jmp_code) {
7236                         if (item->check_target_idx) {
7237                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7238                         }
7239                 }
7240         }
7241
7242         if (!fail_tramp)
7243                 mono_stats.imt_thunks_size += code - start;
7244         g_assert (code - start <= size);
7245
7246         return start;
7247 }
7248
7249 MonoMethod*
7250 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7251 {
7252         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7253 }
7254
7255 MonoObject*
7256 mono_arch_find_this_argument (mgreg_t *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
7257 {
7258         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), regs, NULL);
7259 }
7260 #endif
7261
7262 MonoVTable*
7263 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7264 {
7265         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7266 }
7267
7268 MonoInst*
7269 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7270 {
7271         MonoInst *ins = NULL;
7272         int opcode = 0;
7273
7274         if (cmethod->klass == mono_defaults.math_class) {
7275                 if (strcmp (cmethod->name, "Sin") == 0) {
7276                         opcode = OP_SIN;
7277                 } else if (strcmp (cmethod->name, "Cos") == 0) {
7278                         opcode = OP_COS;
7279                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7280                         opcode = OP_SQRT;
7281                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7282                         opcode = OP_ABS;
7283                 }
7284
7285                 if (opcode) {
7286                         MONO_INST_NEW (cfg, ins, opcode);
7287                         ins->type = STACK_R8;
7288                         ins->dreg = mono_alloc_freg (cfg);
7289                         ins->sreg1 = args [0]->dreg;
7290                         MONO_ADD_INS (cfg->cbb, ins);
7291                 }
7292
7293                 opcode = 0;
7294                 if (cfg->opt & MONO_OPT_CMOV) {
7295                         if (strcmp (cmethod->name, "Min") == 0) {
7296                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7297                                         opcode = OP_IMIN;
7298                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7299                                         opcode = OP_IMIN_UN;
7300                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7301                                         opcode = OP_LMIN;
7302                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7303                                         opcode = OP_LMIN_UN;
7304                         } else if (strcmp (cmethod->name, "Max") == 0) {
7305                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7306                                         opcode = OP_IMAX;
7307                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7308                                         opcode = OP_IMAX_UN;
7309                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7310                                         opcode = OP_LMAX;
7311                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7312                                         opcode = OP_LMAX_UN;
7313                         }
7314                 }
7315
7316                 if (opcode) {
7317                         MONO_INST_NEW (cfg, ins, opcode);
7318                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7319                         ins->dreg = mono_alloc_ireg (cfg);
7320                         ins->sreg1 = args [0]->dreg;
7321                         ins->sreg2 = args [1]->dreg;
7322                         MONO_ADD_INS (cfg->cbb, ins);
7323                 }
7324
7325 #if 0
7326                 /* OP_FREM is not IEEE compatible */
7327                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7328                         MONO_INST_NEW (cfg, ins, OP_FREM);
7329                         ins->inst_i0 = args [0];
7330                         ins->inst_i1 = args [1];
7331                 }
7332 #endif
7333         }
7334
7335         /*
7336          * Can't implement CompareExchange methods this way since they have
7337          * three arguments.
7338          */
7339
7340         return ins;
7341 }
7342
7343 gboolean
7344 mono_arch_print_tree (MonoInst *tree, int arity)
7345 {
7346         return 0;
7347 }
7348
7349 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7350 {
7351         MonoInst* ins;
7352
7353         if (appdomain_tls_offset == -1)
7354                 return NULL;
7355
7356         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7357         ins->inst_offset = appdomain_tls_offset;
7358         return ins;
7359 }
7360
7361 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7362
7363 gpointer
7364 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7365 {
7366         switch (reg) {
7367         case AMD64_RCX: return (gpointer)ctx->rcx;
7368         case AMD64_RDX: return (gpointer)ctx->rdx;
7369         case AMD64_RBX: return (gpointer)ctx->rbx;
7370         case AMD64_RBP: return (gpointer)ctx->rbp;
7371         case AMD64_RSP: return (gpointer)ctx->rsp;
7372         default:
7373                 if (reg < 8)
7374                         return _CTX_REG (ctx, rax, reg);
7375                 else if (reg >= 12)
7376                         return _CTX_REG (ctx, r12, reg - 12);
7377                 else
7378                         g_assert_not_reached ();
7379         }
7380 }
7381
7382 /* Soft Debug support */
7383 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7384
7385 /*
7386  * mono_arch_set_breakpoint:
7387  *
7388  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7389  * The location should contain code emitted by OP_SEQ_POINT.
7390  */
7391 void
7392 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7393 {
7394         guint8 *code = ip;
7395         guint8 *orig_code = code;
7396
7397         /*
7398          * In production, we will use int3 (has to fix the size in the md
7399          * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7400          * instead.
7401          */
7402         g_assert (code [0] == 0x90);
7403
7404         g_assert (((guint64)bp_trigger_page >> 32) == 0);
7405
7406         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7407         g_assert (code - orig_code == BREAKPOINT_SIZE);
7408 }
7409
7410 /*
7411  * mono_arch_clear_breakpoint:
7412  *
7413  *   Clear the breakpoint at IP.
7414  */
7415 void
7416 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7417 {
7418         guint8 *code = ip;
7419         int i;
7420
7421         for (i = 0; i < BREAKPOINT_SIZE; ++i)
7422                 x86_nop (code);
7423 }
7424
7425 /*
7426  * mono_arch_start_single_stepping:
7427  *
7428  *   Start single stepping.
7429  */
7430 void
7431 mono_arch_start_single_stepping (void)
7432 {
7433         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7434 }
7435
7436 /*
7437  * mono_arch_stop_single_stepping:
7438  *
7439  *   Stop single stepping.
7440  */
7441 void
7442 mono_arch_stop_single_stepping (void)
7443 {
7444         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7445 }
7446
7447 /*
7448  * mono_arch_is_single_step_event:
7449  *
7450  *   Return whenever the machine state in SIGCTX corresponds to a single
7451  * step event.
7452  */
7453 gboolean
7454 mono_arch_is_single_step_event (void *info, void *sigctx)
7455 {
7456 #ifdef HOST_WIN32
7457         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7458         return FALSE;
7459 #else
7460         siginfo_t* sinfo = (siginfo_t*) info;
7461         /* Sometimes the address is off by 4 */
7462         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7463                 return TRUE;
7464         else
7465                 return FALSE;
7466 #endif
7467 }
7468
7469 gboolean
7470 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7471 {
7472 #ifdef HOST_WIN32
7473         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7474         return FALSE;
7475 #else
7476         siginfo_t* sinfo = (siginfo_t*) info;
7477         /* Sometimes the address is off by 4 */
7478         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7479                 return TRUE;
7480         else
7481                 return FALSE;
7482 #endif
7483 }
7484
7485 /*
7486  * mono_arch_get_ip_for_breakpoint:
7487  *
7488  *   Convert the ip in CTX to the address where a breakpoint was placed.
7489  */
7490 guint8*
7491 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7492 {
7493         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7494
7495         /* size of xor r11, r11 */
7496         ip -= 0;
7497
7498         return ip;
7499 }
7500
7501 /*
7502  * mono_arch_get_ip_for_single_step:
7503  *
7504  *   Convert the ip in CTX to the address stored in seq_points.
7505  */
7506 guint8*
7507 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7508 {
7509         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7510
7511         /* Size of amd64_mov_reg_mem (r11) */
7512         ip += 8;
7513
7514         return ip;
7515 }
7516
7517 /*
7518  * mono_arch_skip_breakpoint:
7519  *
7520  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
7521  * we resume, the instruction is not executed again.
7522  */
7523 void
7524 mono_arch_skip_breakpoint (MonoContext *ctx)
7525 {
7526         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
7527 }
7528
7529 /*
7530  * mono_arch_skip_single_step:
7531  *
7532  *   Modify CTX so the ip is placed after the single step trigger instruction,
7533  * we resume, the instruction is not executed again.
7534  */
7535 void
7536 mono_arch_skip_single_step (MonoContext *ctx)
7537 {
7538         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 8);
7539 }
7540
7541 /*
7542  * mono_arch_create_seq_point_info:
7543  *
7544  *   Return a pointer to a data structure which is used by the sequence
7545  * point implementation in AOTed code.
7546  */
7547 gpointer
7548 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7549 {
7550         NOT_IMPLEMENTED;
7551         return NULL;
7552 }
7553
7554 #endif