mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35
  36 #include "trace.h"
  37 #include "ir-emit.h"
  38 #include "mini-amd64.h"
  39 #include "cpu-amd64.h"
  40 #include "debugger-agent.h"
  41 #include "mini-gc.h"
  42
  43 #ifdef MONO_XEN_OPT
  44 static gboolean optimize_for_xen = TRUE;
  45 #else
  46 #define optimize_for_xen 0
  47 #endif
  48
  49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  50
  51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  52
  53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  54
  55 #ifdef HOST_WIN32
  56 /* Under windows, the calling convention is never stdcall */
  57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  58 #else
  59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  60 #endif
  61
  62 /* This mutex protects architecture specific caches */
  63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  65 static mono_mutex_t mini_arch_mutex;
  66
  67 MonoBreakpointInfo
  68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  69
  70 /*
  71  * The code generated for sequence points reads from this location, which is
  72  * made read-only when single stepping is enabled.
  73  */
  74 static gpointer ss_trigger_page;
  75
  76 /* Enabled breakpoints read from this trigger page */
  77 static gpointer bp_trigger_page;
  78
  79 /* The size of the breakpoint sequence */
  80 static int breakpoint_size;
  81
  82 /* The size of the breakpoint instruction causing the actual fault */
  83 static int breakpoint_fault_size;
  84
  85 /* The size of the single step instruction causing the actual fault */
  86 static int single_step_fault_size;
  87
  88 /* Offset between fp and the first argument in the callee */
  89 #define ARGS_OFFSET 16
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return mono_debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 #ifdef __native_client_codegen__
 182
 183 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 184 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 185 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 186 /* We only want to force bundle alignment for the top level instruction,    */
 187 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 188 static MonoNativeTlsKey nacl_instruction_depth;
 189
 190 static MonoNativeTlsKey nacl_rex_tag;
 191 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 192
 193 void
 194 amd64_nacl_clear_legacy_prefix_tag ()
 195 {
 196         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 197 }
 198
 199 void
 200 amd64_nacl_tag_legacy_prefix (guint8* code)
 201 {
 202         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 203                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 204 }
 205
 206 void
 207 amd64_nacl_tag_rex (guint8* code)
 208 {
 209         mono_native_tls_set_value (nacl_rex_tag, code);
 210 }
 211
 212 guint8*
 213 amd64_nacl_get_legacy_prefix_tag ()
 214 {
 215         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 216 }
 217
 218 guint8*
 219 amd64_nacl_get_rex_tag ()
 220 {
 221         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 222 }
 223
 224 /* Increment the instruction "depth" described above */
 225 void
 226 amd64_nacl_instruction_pre ()
 227 {
 228         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 229         depth++;
 230         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 231 }
 232
 233 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 234 /* alignment if depth == 0 (top level instruction)                          */
 235 /* IN: start, end    pointers to instruction beginning and end              */
 236 /* OUT: start, end   pointers to beginning and end after possible alignment */
 237 /* GLOBALS: nacl_instruction_depth     defined above                        */
 238 void
 239 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 240 {
 241         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 242         depth--;
 243         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 244
 245         g_assert ( depth >= 0 );
 246         if (depth == 0) {
 247                 uintptr_t space_in_block;
 248                 uintptr_t instlen;
 249                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 250                 /* if legacy prefix is present, and if it was emitted before */
 251                 /* the start of the instruction sequence, adjust the start   */
 252                 if (prefix != NULL && prefix < *start) {
 253                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 254                         *start = prefix;
 255                 }
 256                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 257                 instlen = (uintptr_t)(*end - *start);
 258                 /* Only check for instructions which are less than        */
 259                 /* kNaClAlignment. The only instructions that should ever */
 260                 /* be that long are call sequences, which are already     */
 261                 /* padded out to align the return to the next bundle.     */
 262                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 263                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 264                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 265                         const size_t length = (size_t)((*end)-(*start));
 266                         g_assert (length < MAX_NACL_INST_LENGTH);
 267
 268                         memcpy (copy_of_instruction, *start, length);
 269                         *start = mono_arch_nacl_pad (*start, space_in_block);
 270                         memcpy (*start, copy_of_instruction, length);
 271                         *end = *start + length;
 272                 }
 273                 amd64_nacl_clear_legacy_prefix_tag ();
 274                 amd64_nacl_tag_rex (NULL);
 275         }
 276 }
 277
 278 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 279 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 280 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 281 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 282 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 283 /* IN:      code                                                            */
 284 /*             pointer to current instruction stream (in the                */
 285 /*             middle of an instruction, after opcode is emitted)           */
 286 /*          basereg/offset/dreg                                             */
 287 /*             operands of normal membase address                           */
 288 /* OUT:     code                                                            */
 289 /*             pointer to the end of the membase/memindex emit              */
 290 /* GLOBALS: nacl_rex_tag                                                    */
 291 /*             position in instruction stream that rex prefix was emitted   */
 292 /*          nacl_legacy_prefix_tag                                          */
 293 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 294 void
 295 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 296 {
 297         gint8 true_basereg = basereg;
 298
 299         /* Cache these values, they might change  */
 300         /* as new instructions are emitted below. */
 301         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 302         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 303
 304         /* 'basereg' is given masked to 0x7 at this point, so check */
 305         /* the rex prefix to see if this is an extended register.   */
 306         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 307                 true_basereg |= 0x8;
 308         }
 309
 310 #define X86_LEA_OPCODE (0x8D)
 311
 312         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 313                 guint8* old_instruction_start;
 314
 315                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 316                 /* 32-bits of the old base register (new index register)     */
 317                 guint8 buf[32];
 318                 guint8* buf_ptr = buf;
 319                 size_t insert_len;
 320
 321                 g_assert (rex_tag != NULL);
 322
 323                 if (IS_REX(*rex_tag)) {
 324                         /* The old rex.B should be the new rex.X */
 325                         if (*rex_tag & AMD64_REX_B) {
 326                                 *rex_tag |= AMD64_REX_X;
 327                         }
 328                         /* Since our new base is %r15 set rex.B */
 329                         *rex_tag |= AMD64_REX_B;
 330                 } else {
 331                         /* Shift the instruction by one byte  */
 332                         /* so we can insert a rex prefix      */
 333                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 334                         *code += 1;
 335                         /* New rex prefix only needs rex.B for %r15 base */
 336                         *rex_tag = AMD64_REX(AMD64_REX_B);
 337                 }
 338
 339                 if (legacy_prefix_tag) {
 340                         old_instruction_start = legacy_prefix_tag;
 341                 } else {
 342                         old_instruction_start = rex_tag;
 343                 }
 344
 345                 /* Clears the upper 32-bits of the previous base register */
 346                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 347                 insert_len = buf_ptr - buf;
 348
 349                 /* Move the old instruction forward to make */
 350                 /* room for 'mov' stored in 'buf_ptr'       */
 351                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 352                 *code += insert_len;
 353                 memcpy (old_instruction_start, buf, insert_len);
 354
 355                 /* Sandboxed replacement for the normal membase_emit */
 356                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 357
 358         } else {
 359                 /* Normal default behavior, emit membase memory location */
 360                 x86_membase_emit_body (*code, dreg, basereg, offset);
 361         }
 362 }
 363
 364
 365 static inline unsigned char*
 366 amd64_skip_nops (unsigned char* code)
 367 {
 368         guint8 in_nop;
 369         do {
 370                 in_nop = 0;
 371                 if (   code[0] == 0x90) {
 372                         in_nop = 1;
 373                         code += 1;
 374                 }
 375                 if (   code[0] == 0x66 && code[1] == 0x90) {
 376                         in_nop = 1;
 377                         code += 2;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x00) {
 381                         in_nop = 1;
 382                         code += 3;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x40 && code[3] == 0x00) {
 386                         in_nop = 1;
 387                         code += 4;
 388                 }
 389                 if (code[0] == 0x0f && code[1] == 0x1f
 390                  && code[2] == 0x44 && code[3] == 0x00
 391                  && code[4] == 0x00) {
 392                         in_nop = 1;
 393                         code += 5;
 394                 }
 395                 if (code[0] == 0x66 && code[1] == 0x0f
 396                  && code[2] == 0x1f && code[3] == 0x44
 397                  && code[4] == 0x00 && code[5] == 0x00) {
 398                         in_nop = 1;
 399                         code += 6;
 400                 }
 401                 if (code[0] == 0x0f && code[1] == 0x1f
 402                  && code[2] == 0x80 && code[3] == 0x00
 403                  && code[4] == 0x00 && code[5] == 0x00
 404                  && code[6] == 0x00) {
 405                         in_nop = 1;
 406                         code += 7;
 407                 }
 408                 if (code[0] == 0x0f && code[1] == 0x1f
 409                  && code[2] == 0x84 && code[3] == 0x00
 410                  && code[4] == 0x00 && code[5] == 0x00
 411                  && code[6] == 0x00 && code[7] == 0x00) {
 412                         in_nop = 1;
 413                         code += 8;
 414                 }
 415         } while ( in_nop );
 416         return code;
 417 }
 418
 419 guint8*
 420 mono_arch_nacl_skip_nops (guint8* code)
 421 {
 422   return amd64_skip_nops(code);
 423 }
 424
 425 #endif /*__native_client_codegen__*/
 426
 427 static inline void
 428 amd64_patch (unsigned char* code, gpointer target)
 429 {
 430         guint8 rex = 0;
 431
 432 #ifdef __native_client_codegen__
 433         code = amd64_skip_nops (code);
 434 #endif
 435 #if defined(__native_client_codegen__) && defined(__native_client__)
 436         if (nacl_is_code_address (code)) {
 437                 /* For tail calls, code is patched after being installed */
 438                 /* but not through the normal "patch callsite" method.   */
 439                 unsigned char buf[kNaClAlignment];
 440                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 441                 int ret;
 442                 memcpy (buf, aligned_code, kNaClAlignment);
 443                 /* Patch a temp buffer of bundle size, */
 444                 /* then install to actual location.    */
 445                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 446                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 447                 g_assert (ret == 0);
 448                 return;
 449         }
 450         target = nacl_modify_patch_target (target);
 451 #endif
 452
 453         /* Skip REX */
 454         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 455                 rex = code [0];
 456                 code += 1;
 457         }
 458
 459         if ((code [0] & 0xf8) == 0xb8) {
 460                 /* amd64_set_reg_template */
 461                 *(guint64*)(code + 1) = (guint64)target;
 462         }
 463         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 464                 /* mov 0(%rip), %dreg */
 465                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 466         }
 467         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 468                 /* call *<OFFSET>(%rip) */
 469                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 470         }
 471         else if (code [0] == 0xe8) {
 472                 /* call <DISP> */
 473                 gint64 disp = (guint8*)target - (guint8*)code;
 474                 g_assert (amd64_is_imm32 (disp));
 475                 x86_patch (code, (unsigned char*)target);
 476         }
 477         else
 478                 x86_patch (code, (unsigned char*)target);
 479 }
 480
 481 void
 482 mono_amd64_patch (unsigned char* code, gpointer target)
 483 {
 484         amd64_patch (code, target);
 485 }
 486
 487 typedef enum {
 488         ArgInIReg,
 489         ArgInFloatSSEReg,
 490         ArgInDoubleSSEReg,
 491         ArgOnStack,
 492         ArgValuetypeInReg,
 493         ArgValuetypeAddrInIReg,
 494         ArgNone /* only in pair_storage */
 495 } ArgStorage;
 496
 497 typedef struct {
 498         gint16 offset;
 499         gint8  reg;
 500         ArgStorage storage;
 501
 502         /* Only if storage == ArgValuetypeInReg */
 503         ArgStorage pair_storage [2];
 504         gint8 pair_regs [2];
 505         int nregs;
 506 } ArgInfo;
 507
 508 typedef struct {
 509         int nargs;
 510         guint32 stack_usage;
 511         guint32 reg_usage;
 512         guint32 freg_usage;
 513         gboolean need_stack_align;
 514         gboolean vtype_retaddr;
 515         /* The index of the vret arg in the argument list */
 516         int vret_arg_index;
 517         ArgInfo ret;
 518         ArgInfo sig_cookie;
 519         ArgInfo args [1];
 520 } CallInfo;
 521
 522 #define DEBUG(a) if (cfg->verbose_level > 1) a
 523
 524 #ifdef HOST_WIN32
 525 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 526
 527 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 528 #else
 529 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 530
 531  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 532 #endif
 533
 534 static void inline
 535 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 536 {
 537     ainfo->offset = *stack_size;
 538
 539     if (*gr >= PARAM_REGS) {
 540                 ainfo->storage = ArgOnStack;
 541                 /* Since the same stack slot size is used for all arg */
 542                 /*  types, it needs to be big enough to hold them all */
 543                 (*stack_size) += sizeof(mgreg_t);
 544     }
 545     else {
 546                 ainfo->storage = ArgInIReg;
 547                 ainfo->reg = param_regs [*gr];
 548                 (*gr) ++;
 549     }
 550 }
 551
 552 #ifdef HOST_WIN32
 553 #define FLOAT_PARAM_REGS 4
 554 #else
 555 #define FLOAT_PARAM_REGS 8
 556 #endif
 557
 558 static void inline
 559 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 560 {
 561     ainfo->offset = *stack_size;
 562
 563     if (*gr >= FLOAT_PARAM_REGS) {
 564                 ainfo->storage = ArgOnStack;
 565                 /* Since the same stack slot size is used for both float */
 566                 /*  types, it needs to be big enough to hold them both */
 567                 (*stack_size) += sizeof(mgreg_t);
 568     }
 569     else {
 570                 /* A double register */
 571                 if (is_double)
 572                         ainfo->storage = ArgInDoubleSSEReg;
 573                 else
 574                         ainfo->storage = ArgInFloatSSEReg;
 575                 ainfo->reg = *gr;
 576                 (*gr) += 1;
 577     }
 578 }
 579
 580 typedef enum ArgumentClass {
 581         ARG_CLASS_NO_CLASS,
 582         ARG_CLASS_MEMORY,
 583         ARG_CLASS_INTEGER,
 584         ARG_CLASS_SSE
 585 } ArgumentClass;
 586
 587 static ArgumentClass
 588 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 589 {
 590         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 591         MonoType *ptype;
 592
 593         ptype = mini_type_get_underlying_type (gsctx, type);
 594         switch (ptype->type) {
 595         case MONO_TYPE_BOOLEAN:
 596         case MONO_TYPE_CHAR:
 597         case MONO_TYPE_I1:
 598         case MONO_TYPE_U1:
 599         case MONO_TYPE_I2:
 600         case MONO_TYPE_U2:
 601         case MONO_TYPE_I4:
 602         case MONO_TYPE_U4:
 603         case MONO_TYPE_I:
 604         case MONO_TYPE_U:
 605         case MONO_TYPE_STRING:
 606         case MONO_TYPE_OBJECT:
 607         case MONO_TYPE_CLASS:
 608         case MONO_TYPE_SZARRAY:
 609         case MONO_TYPE_PTR:
 610         case MONO_TYPE_FNPTR:
 611         case MONO_TYPE_ARRAY:
 612         case MONO_TYPE_I8:
 613         case MONO_TYPE_U8:
 614                 class2 = ARG_CLASS_INTEGER;
 615                 break;
 616         case MONO_TYPE_R4:
 617         case MONO_TYPE_R8:
 618 #ifdef HOST_WIN32
 619                 class2 = ARG_CLASS_INTEGER;
 620 #else
 621                 class2 = ARG_CLASS_SSE;
 622 #endif
 623                 break;
 624
 625         case MONO_TYPE_TYPEDBYREF:
 626                 g_assert_not_reached ();
 627
 628         case MONO_TYPE_GENERICINST:
 629                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 630                         class2 = ARG_CLASS_INTEGER;
 631                         break;
 632                 }
 633                 /* fall through */
 634         case MONO_TYPE_VALUETYPE: {
 635                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 636                 int i;
 637
 638                 for (i = 0; i < info->num_fields; ++i) {
 639                         class2 = class1;
 640                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 641                 }
 642                 break;
 643         }
 644         default:
 645                 g_assert_not_reached ();
 646         }
 647
 648         /* Merge */
 649         if (class1 == class2)
 650                 ;
 651         else if (class1 == ARG_CLASS_NO_CLASS)
 652                 class1 = class2;
 653         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 654                 class1 = ARG_CLASS_MEMORY;
 655         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 656                 class1 = ARG_CLASS_INTEGER;
 657         else
 658                 class1 = ARG_CLASS_SSE;
 659
 660         return class1;
 661 }
 662 #ifdef __native_client_codegen__
 663
 664 /* Default alignment for Native Client is 32-byte. */
 665 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 666
 667 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 668 /* Check that alignment doesn't cross an alignment boundary.             */
 669 guint8*
 670 mono_arch_nacl_pad(guint8 *code, int pad)
 671 {
 672         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 673
 674         if (pad == 0) return code;
 675         /* assertion: alignment cannot cross a block boundary */
 676         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 677                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 678         while (pad >= kMaxPadding) {
 679                 amd64_padding (code, kMaxPadding);
 680                 pad -= kMaxPadding;
 681         }
 682         if (pad != 0) amd64_padding (code, pad);
 683         return code;
 684 }
 685 #endif
 686
 687 static void
 688 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 689                            gboolean is_return,
 690                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 691 {
 692         guint32 size, quad, nquads, i;
 693         /* Keep track of the size used in each quad so we can */
 694         /* use the right size when copying args/return vars.  */
 695         guint32 quadsize [2] = {8, 8};
 696         ArgumentClass args [2];
 697         MonoMarshalType *info = NULL;
 698         MonoClass *klass;
 699         MonoGenericSharingContext tmp_gsctx;
 700         gboolean pass_on_stack = FALSE;
 701
 702         /*
 703          * The gsctx currently contains no data, it is only used for checking whenever
 704          * open types are allowed, some callers like mono_arch_get_argument_info ()
 705          * don't pass it to us, so work around that.
 706          */
 707         if (!gsctx)
 708                 gsctx = &tmp_gsctx;
 709
 710         klass = mono_class_from_mono_type (type);
 711         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 712 #ifndef HOST_WIN32
 713         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 714                 /* We pass and return vtypes of size 8 in a register */
 715         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 716                 pass_on_stack = TRUE;
 717         }
 718 #else
 719         if (!sig->pinvoke) {
 720                 pass_on_stack = TRUE;
 721         }
 722 #endif
 723
 724         /* If this struct can't be split up naturally into 8-byte */
 725         /* chunks (registers), pass it on the stack.              */
 726         if (sig->pinvoke && !pass_on_stack) {
 727                 guint32 align;
 728                 guint32 field_size;
 729
 730                 info = mono_marshal_load_type_info (klass);
 731                 g_assert(info);
 732                 for (i = 0; i < info->num_fields; ++i) {
 733                         field_size = mono_marshal_type_size (info->fields [i].field->type,
 734                                                            info->fields [i].mspec,
 735                                                            &align, TRUE, klass->unicode);
 736                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
 737                                 pass_on_stack = TRUE;
 738                                 break;
 739                         }
 740                 }
 741         }
 742
 743         if (pass_on_stack) {
 744                 /* Allways pass in memory */
 745                 ainfo->offset = *stack_size;
 746                 *stack_size += ALIGN_TO (size, 8);
 747                 ainfo->storage = ArgOnStack;
 748
 749                 return;
 750         }
 751
 752         /* FIXME: Handle structs smaller than 8 bytes */
 753         //if ((size % 8) != 0)
 754         //      NOT_IMPLEMENTED;
 755
 756         if (size > 8)
 757                 nquads = 2;
 758         else
 759                 nquads = 1;
 760
 761         if (!sig->pinvoke) {
 762                 /* Always pass in 1 or 2 integer registers */
 763                 args [0] = ARG_CLASS_INTEGER;
 764                 args [1] = ARG_CLASS_INTEGER;
 765                 /* Only the simplest cases are supported */
 766                 if (is_return && nquads != 1) {
 767                         args [0] = ARG_CLASS_MEMORY;
 768                         args [1] = ARG_CLASS_MEMORY;
 769                 }
 770         } else {
 771                 /*
 772                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 773                  * The X87 and SSEUP stuff is left out since there are no such types in
 774                  * the CLR.
 775                  */
 776                 info = mono_marshal_load_type_info (klass);
 777                 g_assert (info);
 778
 779 #ifndef HOST_WIN32
 780                 if (info->native_size > 16) {
 781                         ainfo->offset = *stack_size;
 782                         *stack_size += ALIGN_TO (info->native_size, 8);
 783                         ainfo->storage = ArgOnStack;
 784
 785                         return;
 786                 }
 787 #else
 788                 switch (info->native_size) {
 789                 case 1: case 2: case 4: case 8:
 790                         break;
 791                 default:
 792                         if (is_return) {
 793                                 ainfo->storage = ArgOnStack;
 794                                 ainfo->offset = *stack_size;
 795                                 *stack_size += ALIGN_TO (info->native_size, 8);
 796                         }
 797                         else {
 798                                 ainfo->storage = ArgValuetypeAddrInIReg;
 799
 800                                 if (*gr < PARAM_REGS) {
 801                                         ainfo->pair_storage [0] = ArgInIReg;
 802                                         ainfo->pair_regs [0] = param_regs [*gr];
 803                                         (*gr) ++;
 804                                 }
 805                                 else {
 806                                         ainfo->pair_storage [0] = ArgOnStack;
 807                                         ainfo->offset = *stack_size;
 808                                         *stack_size += 8;
 809                                 }
 810                         }
 811
 812                         return;
 813                 }
 814 #endif
 815
 816                 args [0] = ARG_CLASS_NO_CLASS;
 817                 args [1] = ARG_CLASS_NO_CLASS;
 818                 for (quad = 0; quad < nquads; ++quad) {
 819                         int size;
 820                         guint32 align;
 821                         ArgumentClass class1;
 822
 823                         if (info->num_fields == 0)
 824                                 class1 = ARG_CLASS_MEMORY;
 825                         else
 826                                 class1 = ARG_CLASS_NO_CLASS;
 827                         for (i = 0; i < info->num_fields; ++i) {
 828                                 size = mono_marshal_type_size (info->fields [i].field->type,
 829                                                                                            info->fields [i].mspec,
 830                                                                                            &align, TRUE, klass->unicode);
 831                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 832                                         /* Unaligned field */
 833                                         NOT_IMPLEMENTED;
 834                                 }
 835
 836                                 /* Skip fields in other quad */
 837                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 838                                         continue;
 839                                 if ((quad == 1) && (info->fields [i].offset < 8))
 840                                         continue;
 841
 842                                 /* How far into this quad this data extends.*/
 843                                 /* (8 is size of quad) */
 844                                 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
 845
 846                                 class1 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class1);
 847                         }
 848                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 849                         args [quad] = class1;
 850                 }
 851         }
 852
 853         /* Post merger cleanup */
 854         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 855                 args [0] = args [1] = ARG_CLASS_MEMORY;
 856
 857         /* Allocate registers */
 858         {
 859                 int orig_gr = *gr;
 860                 int orig_fr = *fr;
 861
 862                 ainfo->storage = ArgValuetypeInReg;
 863                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 864                 ainfo->nregs = nquads;
 865                 for (quad = 0; quad < nquads; ++quad) {
 866                         switch (args [quad]) {
 867                         case ARG_CLASS_INTEGER:
 868                                 if (*gr >= PARAM_REGS)
 869                                         args [quad] = ARG_CLASS_MEMORY;
 870                                 else {
 871                                         ainfo->pair_storage [quad] = ArgInIReg;
 872                                         if (is_return)
 873                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 874                                         else
 875                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 876                                         (*gr) ++;
 877                                 }
 878                                 break;
 879                         case ARG_CLASS_SSE:
 880                                 if (*fr >= FLOAT_PARAM_REGS)
 881                                         args [quad] = ARG_CLASS_MEMORY;
 882                                 else {
 883                                         if (quadsize[quad] <= 4)
 884                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 885                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 886                                         ainfo->pair_regs [quad] = *fr;
 887                                         (*fr) ++;
 888                                 }
 889                                 break;
 890                         case ARG_CLASS_MEMORY:
 891                                 break;
 892                         default:
 893                                 g_assert_not_reached ();
 894                         }
 895                 }
 896
 897                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 898                         /* Revert possible register assignments */
 899                         *gr = orig_gr;
 900                         *fr = orig_fr;
 901
 902                         ainfo->offset = *stack_size;
 903                         if (sig->pinvoke)
 904                                 *stack_size += ALIGN_TO (info->native_size, 8);
 905                         else
 906                                 *stack_size += nquads * sizeof(mgreg_t);
 907                         ainfo->storage = ArgOnStack;
 908                 }
 909         }
 910 }
 911
 912 /*
 913  * get_call_info:
 914  *
 915  *  Obtain information about a call according to the calling convention.
 916  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 917  * Draft Version 0.23" document for more information.
 918  */
 919 static CallInfo*
 920 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 921 {
 922         guint32 i, gr, fr, pstart;
 923         MonoType *ret_type;
 924         int n = sig->hasthis + sig->param_count;
 925         guint32 stack_size = 0;
 926         CallInfo *cinfo;
 927         gboolean is_pinvoke = sig->pinvoke;
 928
 929         if (mp)
 930                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 931         else
 932                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 933
 934         cinfo->nargs = n;
 935
 936         gr = 0;
 937         fr = 0;
 938
 939 #ifdef HOST_WIN32
 940         /* Reserve space where the callee can save the argument registers */
 941         stack_size = 4 * sizeof (mgreg_t);
 942 #endif
 943
 944         /* return value */
 945         {
 946                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 947                 switch (ret_type->type) {
 948                 case MONO_TYPE_BOOLEAN:
 949                 case MONO_TYPE_I1:
 950                 case MONO_TYPE_U1:
 951                 case MONO_TYPE_I2:
 952                 case MONO_TYPE_U2:
 953                 case MONO_TYPE_CHAR:
 954                 case MONO_TYPE_I4:
 955                 case MONO_TYPE_U4:
 956                 case MONO_TYPE_I:
 957                 case MONO_TYPE_U:
 958                 case MONO_TYPE_PTR:
 959                 case MONO_TYPE_FNPTR:
 960                 case MONO_TYPE_CLASS:
 961                 case MONO_TYPE_OBJECT:
 962                 case MONO_TYPE_SZARRAY:
 963                 case MONO_TYPE_ARRAY:
 964                 case MONO_TYPE_STRING:
 965                         cinfo->ret.storage = ArgInIReg;
 966                         cinfo->ret.reg = AMD64_RAX;
 967                         break;
 968                 case MONO_TYPE_U8:
 969                 case MONO_TYPE_I8:
 970                         cinfo->ret.storage = ArgInIReg;
 971                         cinfo->ret.reg = AMD64_RAX;
 972                         break;
 973                 case MONO_TYPE_R4:
 974                         cinfo->ret.storage = ArgInFloatSSEReg;
 975                         cinfo->ret.reg = AMD64_XMM0;
 976                         break;
 977                 case MONO_TYPE_R8:
 978                         cinfo->ret.storage = ArgInDoubleSSEReg;
 979                         cinfo->ret.reg = AMD64_XMM0;
 980                         break;
 981                 case MONO_TYPE_GENERICINST:
 982                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 983                                 cinfo->ret.storage = ArgInIReg;
 984                                 cinfo->ret.reg = AMD64_RAX;
 985                                 break;
 986                         }
 987                         /* fall through */
 988 #if defined( __native_client_codegen__ )
 989                 case MONO_TYPE_TYPEDBYREF:
 990 #endif
 991                 case MONO_TYPE_VALUETYPE: {
 992                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 993
 994                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 995                         if (cinfo->ret.storage == ArgOnStack) {
 996                                 cinfo->vtype_retaddr = TRUE;
 997                                 /* The caller passes the address where the value is stored */
 998                         }
 999                         break;
1000                 }
1001 #if !defined( __native_client_codegen__ )
1002                 case MONO_TYPE_TYPEDBYREF:
1003                         /* Same as a valuetype with size 24 */
1004                         cinfo->vtype_retaddr = TRUE;
1005                         break;
1006 #endif
1007                 case MONO_TYPE_VOID:
1008                         break;
1009                 default:
1010                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1011                 }
1012         }
1013
1014         pstart = 0;
1015         /*
1016          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1017          * the first argument, allowing 'this' to be always passed in the first arg reg.
1018          * Also do this if the first argument is a reference type, since virtual calls
1019          * are sometimes made using calli without sig->hasthis set, like in the delegate
1020          * invoke wrappers.
1021          */
1022         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1023                 if (sig->hasthis) {
1024                         add_general (&gr, &stack_size, cinfo->args + 0);
1025                 } else {
1026                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1027                         pstart = 1;
1028                 }
1029                 add_general (&gr, &stack_size, &cinfo->ret);
1030                 cinfo->vret_arg_index = 1;
1031         } else {
1032                 /* this */
1033                 if (sig->hasthis)
1034                         add_general (&gr, &stack_size, cinfo->args + 0);
1035
1036                 if (cinfo->vtype_retaddr)
1037                         add_general (&gr, &stack_size, &cinfo->ret);
1038         }
1039
1040         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1041                 gr = PARAM_REGS;
1042                 fr = FLOAT_PARAM_REGS;
1043
1044                 /* Emit the signature cookie just before the implicit arguments */
1045                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1046         }
1047
1048         for (i = pstart; i < sig->param_count; ++i) {
1049                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1050                 MonoType *ptype;
1051
1052 #ifdef HOST_WIN32
1053                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1054                 if (gr > fr)
1055                         fr = gr;
1056                 else if (fr > gr)
1057                         gr = fr;
1058 #endif
1059
1060                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1061                         /* We allways pass the sig cookie on the stack for simplicity */
1062                         /*
1063                          * Prevent implicit arguments + the sig cookie from being passed
1064                          * in registers.
1065                          */
1066                         gr = PARAM_REGS;
1067                         fr = FLOAT_PARAM_REGS;
1068
1069                         /* Emit the signature cookie just before the implicit arguments */
1070                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1071                 }
1072
1073                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1074                 switch (ptype->type) {
1075                 case MONO_TYPE_BOOLEAN:
1076                 case MONO_TYPE_I1:
1077                 case MONO_TYPE_U1:
1078                         add_general (&gr, &stack_size, ainfo);
1079                         break;
1080                 case MONO_TYPE_I2:
1081                 case MONO_TYPE_U2:
1082                 case MONO_TYPE_CHAR:
1083                         add_general (&gr, &stack_size, ainfo);
1084                         break;
1085                 case MONO_TYPE_I4:
1086                 case MONO_TYPE_U4:
1087                         add_general (&gr, &stack_size, ainfo);
1088                         break;
1089                 case MONO_TYPE_I:
1090                 case MONO_TYPE_U:
1091                 case MONO_TYPE_PTR:
1092                 case MONO_TYPE_FNPTR:
1093                 case MONO_TYPE_CLASS:
1094                 case MONO_TYPE_OBJECT:
1095                 case MONO_TYPE_STRING:
1096                 case MONO_TYPE_SZARRAY:
1097                 case MONO_TYPE_ARRAY:
1098                         add_general (&gr, &stack_size, ainfo);
1099                         break;
1100                 case MONO_TYPE_GENERICINST:
1101                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1102                                 add_general (&gr, &stack_size, ainfo);
1103                                 break;
1104                         }
1105                         /* fall through */
1106                 case MONO_TYPE_VALUETYPE:
1107                 case MONO_TYPE_TYPEDBYREF:
1108                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1109                         break;
1110                 case MONO_TYPE_U8:
1111
1112                 case MONO_TYPE_I8:
1113                         add_general (&gr, &stack_size, ainfo);
1114                         break;
1115                 case MONO_TYPE_R4:
1116                         add_float (&fr, &stack_size, ainfo, FALSE);
1117                         break;
1118                 case MONO_TYPE_R8:
1119                         add_float (&fr, &stack_size, ainfo, TRUE);
1120                         break;
1121                 default:
1122                         g_assert_not_reached ();
1123                 }
1124         }
1125
1126         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1127                 gr = PARAM_REGS;
1128                 fr = FLOAT_PARAM_REGS;
1129
1130                 /* Emit the signature cookie just before the implicit arguments */
1131                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1132         }
1133
1134         cinfo->stack_usage = stack_size;
1135         cinfo->reg_usage = gr;
1136         cinfo->freg_usage = fr;
1137         return cinfo;
1138 }
1139
1140 /*
1141  * mono_arch_get_argument_info:
1142  * @csig:  a method signature
1143  * @param_count: the number of parameters to consider
1144  * @arg_info: an array to store the result infos
1145  *
1146  * Gathers information on parameters such as size, alignment and
1147  * padding. arg_info should be large enought to hold param_count + 1 entries.
1148  *
1149  * Returns the size of the argument area on the stack.
1150  */
1151 int
1152 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1153 {
1154         int k;
1155         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1156         guint32 args_size = cinfo->stack_usage;
1157
1158         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1159         if (csig->hasthis) {
1160                 arg_info [0].offset = 0;
1161         }
1162
1163         for (k = 0; k < param_count; k++) {
1164                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1165                 /* FIXME: */
1166                 arg_info [k + 1].size = 0;
1167         }
1168
1169         g_free (cinfo);
1170
1171         return args_size;
1172 }
1173
1174 gboolean
1175 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1176 {
1177         CallInfo *c1, *c2;
1178         gboolean res;
1179         MonoType *callee_ret;
1180
1181         c1 = get_call_info (NULL, NULL, caller_sig);
1182         c2 = get_call_info (NULL, NULL, callee_sig);
1183         res = c1->stack_usage >= c2->stack_usage;
1184         callee_ret = mini_replace_type (callee_sig->ret);
1185         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1186                 /* An address on the callee's stack is passed as the first argument */
1187                 res = FALSE;
1188
1189         g_free (c1);
1190         g_free (c2);
1191
1192         return res;
1193 }
1194
1195 /*
1196  * Initialize the cpu to execute managed code.
1197  */
1198 void
1199 mono_arch_cpu_init (void)
1200 {
1201 #ifndef _MSC_VER
1202         guint16 fpcw;
1203
1204         /* spec compliance requires running with double precision */
1205         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1206         fpcw &= ~X86_FPCW_PRECC_MASK;
1207         fpcw |= X86_FPCW_PREC_DOUBLE;
1208         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1209         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1210 #else
1211         /* TODO: This is crashing on Win64 right now.
1212         * _control87 (_PC_53, MCW_PC);
1213         */
1214 #endif
1215 }
1216
1217 /*
1218  * Initialize architecture specific code.
1219  */
1220 void
1221 mono_arch_init (void)
1222 {
1223         int flags;
1224
1225         mono_mutex_init_recursive (&mini_arch_mutex);
1226 #if defined(__native_client_codegen__)
1227         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1228         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1229         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1230         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1231 #endif
1232
1233 #ifdef MONO_ARCH_NOMAP32BIT
1234         flags = MONO_MMAP_READ;
1235         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1236         breakpoint_size = 13;
1237         breakpoint_fault_size = 3;
1238 #else
1239         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1240         /* amd64_mov_reg_mem () */
1241         breakpoint_size = 8;
1242         breakpoint_fault_size = 8;
1243 #endif
1244
1245         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1246         single_step_fault_size = 4;
1247
1248         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1249         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1250         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1251
1252         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1253         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1254         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1255 }
1256
1257 /*
1258  * Cleanup architecture specific code.
1259  */
1260 void
1261 mono_arch_cleanup (void)
1262 {
1263         mono_mutex_destroy (&mini_arch_mutex);
1264 #if defined(__native_client_codegen__)
1265         mono_native_tls_free (nacl_instruction_depth);
1266         mono_native_tls_free (nacl_rex_tag);
1267         mono_native_tls_free (nacl_legacy_prefix_tag);
1268 #endif
1269 }
1270
1271 /*
1272  * This function returns the optimizations supported on this cpu.
1273  */
1274 guint32
1275 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1276 {
1277         guint32 opts = 0;
1278
1279         *exclude_mask = 0;
1280
1281         if (mono_hwcap_x86_has_cmov) {
1282                 opts |= MONO_OPT_CMOV;
1283
1284                 if (mono_hwcap_x86_has_fcmov)
1285                         opts |= MONO_OPT_FCMOV;
1286                 else
1287                         *exclude_mask |= MONO_OPT_FCMOV;
1288         } else {
1289                 *exclude_mask |= MONO_OPT_CMOV;
1290         }
1291
1292         return opts;
1293 }
1294
1295 /*
1296  * This function test for all SSE functions supported.
1297  *
1298  * Returns a bitmask corresponding to all supported versions.
1299  *
1300  */
1301 guint32
1302 mono_arch_cpu_enumerate_simd_versions (void)
1303 {
1304         guint32 sse_opts = 0;
1305
1306         if (mono_hwcap_x86_has_sse1)
1307                 sse_opts |= SIMD_VERSION_SSE1;
1308
1309         if (mono_hwcap_x86_has_sse2)
1310                 sse_opts |= SIMD_VERSION_SSE2;
1311
1312         if (mono_hwcap_x86_has_sse3)
1313                 sse_opts |= SIMD_VERSION_SSE3;
1314
1315         if (mono_hwcap_x86_has_ssse3)
1316                 sse_opts |= SIMD_VERSION_SSSE3;
1317
1318         if (mono_hwcap_x86_has_sse41)
1319                 sse_opts |= SIMD_VERSION_SSE41;
1320
1321         if (mono_hwcap_x86_has_sse42)
1322                 sse_opts |= SIMD_VERSION_SSE42;
1323
1324         if (mono_hwcap_x86_has_sse4a)
1325                 sse_opts |= SIMD_VERSION_SSE4a;
1326
1327         return sse_opts;
1328 }
1329
1330 #ifndef DISABLE_JIT
1331
1332 GList *
1333 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1334 {
1335         GList *vars = NULL;
1336         int i;
1337
1338         for (i = 0; i < cfg->num_varinfo; i++) {
1339                 MonoInst *ins = cfg->varinfo [i];
1340                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1341
1342                 /* unused vars */
1343                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1344                         continue;
1345
1346                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1347                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1348                         continue;
1349
1350                 if (mono_is_regsize_var (ins->inst_vtype)) {
1351                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1352                         g_assert (i == vmv->idx);
1353                         vars = g_list_prepend (vars, vmv);
1354                 }
1355         }
1356
1357         vars = mono_varlist_sort (cfg, vars, 0);
1358
1359         return vars;
1360 }
1361
1362 /**
1363  * mono_arch_compute_omit_fp:
1364  *
1365  *   Determine whenever the frame pointer can be eliminated.
1366  */
1367 static void
1368 mono_arch_compute_omit_fp (MonoCompile *cfg)
1369 {
1370         MonoMethodSignature *sig;
1371         MonoMethodHeader *header;
1372         int i, locals_size;
1373         CallInfo *cinfo;
1374
1375         if (cfg->arch.omit_fp_computed)
1376                 return;
1377
1378         header = cfg->header;
1379
1380         sig = mono_method_signature (cfg->method);
1381
1382         if (!cfg->arch.cinfo)
1383                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1384         cinfo = cfg->arch.cinfo;
1385
1386         /*
1387          * FIXME: Remove some of the restrictions.
1388          */
1389         cfg->arch.omit_fp = TRUE;
1390         cfg->arch.omit_fp_computed = TRUE;
1391
1392 #ifdef __native_client_codegen__
1393         /* NaCl modules may not change the value of RBP, so it cannot be */
1394         /* used as a normal register, but it can be used as a frame pointer*/
1395         cfg->disable_omit_fp = TRUE;
1396         cfg->arch.omit_fp = FALSE;
1397 #endif
1398
1399 #ifdef HOST_WIN32
1400         cfg->arch.omit_fp = FALSE;
1401 #endif
1402
1403         if (cfg->disable_omit_fp)
1404                 cfg->arch.omit_fp = FALSE;
1405
1406         if (!debug_omit_fp ())
1407                 cfg->arch.omit_fp = FALSE;
1408         /*
1409         if (cfg->method->save_lmf)
1410                 cfg->arch.omit_fp = FALSE;
1411         */
1412         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1413                 cfg->arch.omit_fp = FALSE;
1414         if (header->num_clauses)
1415                 cfg->arch.omit_fp = FALSE;
1416         if (cfg->param_area)
1417                 cfg->arch.omit_fp = FALSE;
1418         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1419                 cfg->arch.omit_fp = FALSE;
1420         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1421                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1422                 cfg->arch.omit_fp = FALSE;
1423         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1424                 ArgInfo *ainfo = &cinfo->args [i];
1425
1426                 if (ainfo->storage == ArgOnStack) {
1427                         /*
1428                          * The stack offset can only be determined when the frame
1429                          * size is known.
1430                          */
1431                         cfg->arch.omit_fp = FALSE;
1432                 }
1433         }
1434
1435         locals_size = 0;
1436         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1437                 MonoInst *ins = cfg->varinfo [i];
1438                 int ialign;
1439
1440                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1441         }
1442 }
1443
1444 GList *
1445 mono_arch_get_global_int_regs (MonoCompile *cfg)
1446 {
1447         GList *regs = NULL;
1448
1449         mono_arch_compute_omit_fp (cfg);
1450
1451         if (cfg->globalra) {
1452                 if (cfg->arch.omit_fp)
1453                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1454
1455                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1456                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1457                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1458                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1459 #ifndef __native_client_codegen__
1460                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1461 #endif
1462
1463                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1464                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1465                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1466                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1467                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1468                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1469                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1470                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1471         } else {
1472                 if (cfg->arch.omit_fp)
1473                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1474
1475                 /* We use the callee saved registers for global allocation */
1476                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1477                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1478                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1479                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1480 #ifndef __native_client_codegen__
1481                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1482 #endif
1483 #ifdef HOST_WIN32
1484                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1485                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1486 #endif
1487         }
1488
1489         return regs;
1490 }
1491
1492 GList*
1493 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1494 {
1495         GList *regs = NULL;
1496         int i;
1497
1498         /* All XMM registers */
1499         for (i = 0; i < 16; ++i)
1500                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1501
1502         return regs;
1503 }
1504
1505 GList*
1506 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1507 {
1508         static GList *r = NULL;
1509
1510         if (r == NULL) {
1511                 GList *regs = NULL;
1512
1513                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1514                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1515                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1516                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1517                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1518 #ifndef __native_client_codegen__
1519                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1520 #endif
1521
1522                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1523                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1524                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1525                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1526                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1527                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1528                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1529                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1530
1531                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1532         }
1533
1534         return r;
1535 }
1536
1537 GList*
1538 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1539 {
1540         int i;
1541         static GList *r = NULL;
1542
1543         if (r == NULL) {
1544                 GList *regs = NULL;
1545
1546                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1547                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1548
1549                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1550         }
1551
1552         return r;
1553 }
1554
1555 /*
1556  * mono_arch_regalloc_cost:
1557  *
1558  *  Return the cost, in number of memory references, of the action of
1559  * allocating the variable VMV into a register during global register
1560  * allocation.
1561  */
1562 guint32
1563 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1564 {
1565         MonoInst *ins = cfg->varinfo [vmv->idx];
1566
1567         if (cfg->method->save_lmf)
1568                 /* The register is already saved */
1569                 /* substract 1 for the invisible store in the prolog */
1570                 return (ins->opcode == OP_ARG) ? 0 : 1;
1571         else
1572                 /* push+pop */
1573                 return (ins->opcode == OP_ARG) ? 1 : 2;
1574 }
1575
1576 /*
1577  * mono_arch_fill_argument_info:
1578  *
1579  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1580  * of the method.
1581  */
1582 void
1583 mono_arch_fill_argument_info (MonoCompile *cfg)
1584 {
1585         MonoType *sig_ret;
1586         MonoMethodSignature *sig;
1587         MonoMethodHeader *header;
1588         MonoInst *ins;
1589         int i;
1590         CallInfo *cinfo;
1591
1592         header = cfg->header;
1593
1594         sig = mono_method_signature (cfg->method);
1595
1596         cinfo = cfg->arch.cinfo;
1597         sig_ret = mini_replace_type (sig->ret);
1598
1599         /*
1600          * Contrary to mono_arch_allocate_vars (), the information should describe
1601          * where the arguments are at the beginning of the method, not where they can be
1602          * accessed during the execution of the method. The later makes no sense for the
1603          * global register allocator, since a variable can be in more than one location.
1604          */
1605         if (sig_ret->type != MONO_TYPE_VOID) {
1606                 switch (cinfo->ret.storage) {
1607                 case ArgInIReg:
1608                 case ArgInFloatSSEReg:
1609                 case ArgInDoubleSSEReg:
1610                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1611                                 cfg->vret_addr->opcode = OP_REGVAR;
1612                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1613                         }
1614                         else {
1615                                 cfg->ret->opcode = OP_REGVAR;
1616                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1617                         }
1618                         break;
1619                 case ArgValuetypeInReg:
1620                         cfg->ret->opcode = OP_REGOFFSET;
1621                         cfg->ret->inst_basereg = -1;
1622                         cfg->ret->inst_offset = -1;
1623                         break;
1624                 default:
1625                         g_assert_not_reached ();
1626                 }
1627         }
1628
1629         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1630                 ArgInfo *ainfo = &cinfo->args [i];
1631                 MonoType *arg_type;
1632
1633                 ins = cfg->args [i];
1634
1635                 if (sig->hasthis && (i == 0))
1636                         arg_type = &mono_defaults.object_class->byval_arg;
1637                 else
1638                         arg_type = sig->params [i - sig->hasthis];
1639
1640                 switch (ainfo->storage) {
1641                 case ArgInIReg:
1642                 case ArgInFloatSSEReg:
1643                 case ArgInDoubleSSEReg:
1644                         ins->opcode = OP_REGVAR;
1645                         ins->inst_c0 = ainfo->reg;
1646                         break;
1647                 case ArgOnStack:
1648                         ins->opcode = OP_REGOFFSET;
1649                         ins->inst_basereg = -1;
1650                         ins->inst_offset = -1;
1651                         break;
1652                 case ArgValuetypeInReg:
1653                         /* Dummy */
1654                         ins->opcode = OP_NOP;
1655                         break;
1656                 default:
1657                         g_assert_not_reached ();
1658                 }
1659         }
1660 }
1661
1662 void
1663 mono_arch_allocate_vars (MonoCompile *cfg)
1664 {
1665         MonoType *sig_ret;
1666         MonoMethodSignature *sig;
1667         MonoMethodHeader *header;
1668         MonoInst *ins;
1669         int i, offset;
1670         guint32 locals_stack_size, locals_stack_align;
1671         gint32 *offsets;
1672         CallInfo *cinfo;
1673
1674         header = cfg->header;
1675
1676         sig = mono_method_signature (cfg->method);
1677
1678         cinfo = cfg->arch.cinfo;
1679         sig_ret = mini_replace_type (sig->ret);
1680
1681         mono_arch_compute_omit_fp (cfg);
1682
1683         /*
1684          * We use the ABI calling conventions for managed code as well.
1685          * Exception: valuetypes are only sometimes passed or returned in registers.
1686          */
1687
1688         /*
1689          * The stack looks like this:
1690          * <incoming arguments passed on the stack>
1691          * <return value>
1692          * <lmf/caller saved registers>
1693          * <locals>
1694          * <spill area>
1695          * <localloc area>  -> grows dynamically
1696          * <params area>
1697          */
1698
1699         if (cfg->arch.omit_fp) {
1700                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1701                 cfg->frame_reg = AMD64_RSP;
1702                 offset = 0;
1703         } else {
1704                 /* Locals are allocated backwards from %fp */
1705                 cfg->frame_reg = AMD64_RBP;
1706                 offset = 0;
1707         }
1708
1709         cfg->arch.saved_iregs = cfg->used_int_regs;
1710         if (cfg->method->save_lmf)
1711                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1712                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1713
1714         if (cfg->arch.omit_fp)
1715                 cfg->arch.reg_save_area_offset = offset;
1716         /* Reserve space for callee saved registers */
1717         for (i = 0; i < AMD64_NREG; ++i)
1718                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1719                         offset += sizeof(mgreg_t);
1720                 }
1721         if (!cfg->arch.omit_fp)
1722                 cfg->arch.reg_save_area_offset = -offset;
1723
1724         if (sig_ret->type != MONO_TYPE_VOID) {
1725                 switch (cinfo->ret.storage) {
1726                 case ArgInIReg:
1727                 case ArgInFloatSSEReg:
1728                 case ArgInDoubleSSEReg:
1729                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1730                                 if (cfg->globalra) {
1731                                         cfg->vret_addr->opcode = OP_REGVAR;
1732                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1733                                 } else {
1734                                         /* The register is volatile */
1735                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1736                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1737                                         if (cfg->arch.omit_fp) {
1738                                                 cfg->vret_addr->inst_offset = offset;
1739                                                 offset += 8;
1740                                         } else {
1741                                                 offset += 8;
1742                                                 cfg->vret_addr->inst_offset = -offset;
1743                                         }
1744                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1745                                                 printf ("vret_addr =");
1746                                                 mono_print_ins (cfg->vret_addr);
1747                                         }
1748                                 }
1749                         }
1750                         else {
1751                                 cfg->ret->opcode = OP_REGVAR;
1752                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1753                         }
1754                         break;
1755                 case ArgValuetypeInReg:
1756                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1757                         cfg->ret->opcode = OP_REGOFFSET;
1758                         cfg->ret->inst_basereg = cfg->frame_reg;
1759                         if (cfg->arch.omit_fp) {
1760                                 cfg->ret->inst_offset = offset;
1761                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1762                         } else {
1763                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1764                                 cfg->ret->inst_offset = - offset;
1765                         }
1766                         break;
1767                 default:
1768                         g_assert_not_reached ();
1769                 }
1770                 if (!cfg->globalra)
1771                         cfg->ret->dreg = cfg->ret->inst_c0;
1772         }
1773
1774         /* Allocate locals */
1775         if (!cfg->globalra) {
1776                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1777                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1778                         char *mname = mono_method_full_name (cfg->method, TRUE);
1779                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1780                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1781                         g_free (mname);
1782                         return;
1783                 }
1784
1785                 if (locals_stack_align) {
1786                         offset += (locals_stack_align - 1);
1787                         offset &= ~(locals_stack_align - 1);
1788                 }
1789                 if (cfg->arch.omit_fp) {
1790                         cfg->locals_min_stack_offset = offset;
1791                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1792                 } else {
1793                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1794                         cfg->locals_max_stack_offset = - offset;
1795                 }
1796
1797                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1798                         if (offsets [i] != -1) {
1799                                 MonoInst *ins = cfg->varinfo [i];
1800                                 ins->opcode = OP_REGOFFSET;
1801                                 ins->inst_basereg = cfg->frame_reg;
1802                                 if (cfg->arch.omit_fp)
1803                                         ins->inst_offset = (offset + offsets [i]);
1804                                 else
1805                                         ins->inst_offset = - (offset + offsets [i]);
1806                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1807                         }
1808                 }
1809                 offset += locals_stack_size;
1810         }
1811
1812         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1813                 g_assert (!cfg->arch.omit_fp);
1814                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1815                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1816         }
1817
1818         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1819                 ins = cfg->args [i];
1820                 if (ins->opcode != OP_REGVAR) {
1821                         ArgInfo *ainfo = &cinfo->args [i];
1822                         gboolean inreg = TRUE;
1823                         MonoType *arg_type;
1824
1825                         if (sig->hasthis && (i == 0))
1826                                 arg_type = &mono_defaults.object_class->byval_arg;
1827                         else
1828                                 arg_type = sig->params [i - sig->hasthis];
1829
1830                         if (cfg->globalra) {
1831                                 /* The new allocator needs info about the original locations of the arguments */
1832                                 switch (ainfo->storage) {
1833                                 case ArgInIReg:
1834                                 case ArgInFloatSSEReg:
1835                                 case ArgInDoubleSSEReg:
1836                                         ins->opcode = OP_REGVAR;
1837                                         ins->inst_c0 = ainfo->reg;
1838                                         break;
1839                                 case ArgOnStack:
1840                                         g_assert (!cfg->arch.omit_fp);
1841                                         ins->opcode = OP_REGOFFSET;
1842                                         ins->inst_basereg = cfg->frame_reg;
1843                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1844                                         break;
1845                                 case ArgValuetypeInReg:
1846                                         ins->opcode = OP_REGOFFSET;
1847                                         ins->inst_basereg = cfg->frame_reg;
1848                                         /* These arguments are saved to the stack in the prolog */
1849                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1850                                         if (cfg->arch.omit_fp) {
1851                                                 ins->inst_offset = offset;
1852                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1853                                         } else {
1854                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1855                                                 ins->inst_offset = - offset;
1856                                         }
1857                                         break;
1858                                 default:
1859                                         g_assert_not_reached ();
1860                                 }
1861
1862                                 continue;
1863                         }
1864
1865                         /* FIXME: Allocate volatile arguments to registers */
1866                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1867                                 inreg = FALSE;
1868
1869                         /*
1870                          * Under AMD64, all registers used to pass arguments to functions
1871                          * are volatile across calls.
1872                          * FIXME: Optimize this.
1873                          */
1874                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1875                                 inreg = FALSE;
1876
1877                         ins->opcode = OP_REGOFFSET;
1878
1879                         switch (ainfo->storage) {
1880                         case ArgInIReg:
1881                         case ArgInFloatSSEReg:
1882                         case ArgInDoubleSSEReg:
1883                                 if (inreg) {
1884                                         ins->opcode = OP_REGVAR;
1885                                         ins->dreg = ainfo->reg;
1886                                 }
1887                                 break;
1888                         case ArgOnStack:
1889                                 g_assert (!cfg->arch.omit_fp);
1890                                 ins->opcode = OP_REGOFFSET;
1891                                 ins->inst_basereg = cfg->frame_reg;
1892                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1893                                 break;
1894                         case ArgValuetypeInReg:
1895                                 break;
1896                         case ArgValuetypeAddrInIReg: {
1897                                 MonoInst *indir;
1898                                 g_assert (!cfg->arch.omit_fp);
1899
1900                                 MONO_INST_NEW (cfg, indir, 0);
1901                                 indir->opcode = OP_REGOFFSET;
1902                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1903                                         indir->inst_basereg = cfg->frame_reg;
1904                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1905                                         offset += (sizeof (gpointer));
1906                                         indir->inst_offset = - offset;
1907                                 }
1908                                 else {
1909                                         indir->inst_basereg = cfg->frame_reg;
1910                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1911                                 }
1912
1913                                 ins->opcode = OP_VTARG_ADDR;
1914                                 ins->inst_left = indir;
1915
1916                                 break;
1917                         }
1918                         default:
1919                                 NOT_IMPLEMENTED;
1920                         }
1921
1922                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1923                                 ins->opcode = OP_REGOFFSET;
1924                                 ins->inst_basereg = cfg->frame_reg;
1925                                 /* These arguments are saved to the stack in the prolog */
1926                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1927                                 if (cfg->arch.omit_fp) {
1928                                         ins->inst_offset = offset;
1929                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1930                                         // Arguments are yet supported by the stack map creation code
1931                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1932                                 } else {
1933                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1934                                         ins->inst_offset = - offset;
1935                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1936                                 }
1937                         }
1938                 }
1939         }
1940
1941         cfg->stack_offset = offset;
1942 }
1943
1944 void
1945 mono_arch_create_vars (MonoCompile *cfg)
1946 {
1947         MonoMethodSignature *sig;
1948         CallInfo *cinfo;
1949         MonoType *sig_ret;
1950
1951         sig = mono_method_signature (cfg->method);
1952
1953         if (!cfg->arch.cinfo)
1954                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1955         cinfo = cfg->arch.cinfo;
1956
1957         if (cinfo->ret.storage == ArgValuetypeInReg)
1958                 cfg->ret_var_is_local = TRUE;
1959
1960         sig_ret = mini_replace_type (sig->ret);
1961         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1962                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1963                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1964                         printf ("vret_addr = ");
1965                         mono_print_ins (cfg->vret_addr);
1966                 }
1967         }
1968
1969         if (cfg->gen_seq_points) {
1970                 MonoInst *ins;
1971
1972                 if (cfg->compile_aot) {
1973                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1974                         ins->flags |= MONO_INST_VOLATILE;
1975                         cfg->arch.seq_point_info_var = ins;
1976                 }
1977
1978             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1979                 ins->flags |= MONO_INST_VOLATILE;
1980                 cfg->arch.ss_trigger_page_var = ins;
1981         }
1982
1983         if (cfg->method->save_lmf)
1984                 cfg->create_lmf_var = TRUE;
1985
1986         if (cfg->method->save_lmf) {
1987                 cfg->lmf_ir = TRUE;
1988 #if !defined(HOST_WIN32)
1989                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1990                         cfg->lmf_ir_mono_lmf = TRUE;
1991 #endif
1992         }
1993
1994 #ifndef HOST_WIN32
1995         cfg->arch_eh_jit_info = 1;
1996 #endif
1997 }
1998
1999 static void
2000 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2001 {
2002         MonoInst *ins;
2003
2004         switch (storage) {
2005         case ArgInIReg:
2006                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2007                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2008                 ins->sreg1 = tree->dreg;
2009                 MONO_ADD_INS (cfg->cbb, ins);
2010                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2011                 break;
2012         case ArgInFloatSSEReg:
2013                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2014                 ins->dreg = mono_alloc_freg (cfg);
2015                 ins->sreg1 = tree->dreg;
2016                 MONO_ADD_INS (cfg->cbb, ins);
2017
2018                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2019                 break;
2020         case ArgInDoubleSSEReg:
2021                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2022                 ins->dreg = mono_alloc_freg (cfg);
2023                 ins->sreg1 = tree->dreg;
2024                 MONO_ADD_INS (cfg->cbb, ins);
2025
2026                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2027
2028                 break;
2029         default:
2030                 g_assert_not_reached ();
2031         }
2032 }
2033
2034 static int
2035 arg_storage_to_load_membase (ArgStorage storage)
2036 {
2037         switch (storage) {
2038         case ArgInIReg:
2039 #if defined(__mono_ilp32__)
2040                 return OP_LOADI8_MEMBASE;
2041 #else
2042                 return OP_LOAD_MEMBASE;
2043 #endif
2044         case ArgInDoubleSSEReg:
2045                 return OP_LOADR8_MEMBASE;
2046         case ArgInFloatSSEReg:
2047                 return OP_LOADR4_MEMBASE;
2048         default:
2049                 g_assert_not_reached ();
2050         }
2051
2052         return -1;
2053 }
2054
2055 static void
2056 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2057 {
2058         MonoInst *arg;
2059         MonoMethodSignature *tmp_sig;
2060         int sig_reg;
2061
2062         if (call->tail_call)
2063                 NOT_IMPLEMENTED;
2064
2065         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2066
2067         /*
2068          * mono_ArgIterator_Setup assumes the signature cookie is
2069          * passed first and all the arguments which were before it are
2070          * passed on the stack after the signature. So compensate by
2071          * passing a different signature.
2072          */
2073         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2074         tmp_sig->param_count -= call->signature->sentinelpos;
2075         tmp_sig->sentinelpos = 0;
2076         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2077
2078         sig_reg = mono_alloc_ireg (cfg);
2079         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2080
2081         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2082 }
2083
2084 static inline LLVMArgStorage
2085 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2086 {
2087         switch (storage) {
2088         case ArgInIReg:
2089                 return LLVMArgInIReg;
2090         case ArgNone:
2091                 return LLVMArgNone;
2092         default:
2093                 g_assert_not_reached ();
2094                 return LLVMArgNone;
2095         }
2096 }
2097
2098 #ifdef ENABLE_LLVM
2099 LLVMCallInfo*
2100 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2101 {
2102         int i, n;
2103         CallInfo *cinfo;
2104         ArgInfo *ainfo;
2105         int j;
2106         LLVMCallInfo *linfo;
2107         MonoType *t, *sig_ret;
2108
2109         n = sig->param_count + sig->hasthis;
2110         sig_ret = mini_replace_type (sig->ret);
2111
2112         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2113
2114         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2115
2116         /*
2117          * LLVM always uses the native ABI while we use our own ABI, the
2118          * only difference is the handling of vtypes:
2119          * - we only pass/receive them in registers in some cases, and only
2120          *   in 1 or 2 integer registers.
2121          */
2122         if (cinfo->ret.storage == ArgValuetypeInReg) {
2123                 if (sig->pinvoke) {
2124                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2125                         cfg->disable_llvm = TRUE;
2126                         return linfo;
2127                 }
2128
2129                 linfo->ret.storage = LLVMArgVtypeInReg;
2130                 for (j = 0; j < 2; ++j)
2131                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2132         }
2133
2134         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2135                 /* Vtype returned using a hidden argument */
2136                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2137                 linfo->vret_arg_index = cinfo->vret_arg_index;
2138         }
2139
2140         for (i = 0; i < n; ++i) {
2141                 ainfo = cinfo->args + i;
2142
2143                 if (i >= sig->hasthis)
2144                         t = sig->params [i - sig->hasthis];
2145                 else
2146                         t = &mono_defaults.int_class->byval_arg;
2147
2148                 linfo->args [i].storage = LLVMArgNone;
2149
2150                 switch (ainfo->storage) {
2151                 case ArgInIReg:
2152                         linfo->args [i].storage = LLVMArgInIReg;
2153                         break;
2154                 case ArgInDoubleSSEReg:
2155                 case ArgInFloatSSEReg:
2156                         linfo->args [i].storage = LLVMArgInFPReg;
2157                         break;
2158                 case ArgOnStack:
2159                         if (MONO_TYPE_ISSTRUCT (t)) {
2160                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2161                         } else {
2162                                 linfo->args [i].storage = LLVMArgInIReg;
2163                                 if (!t->byref) {
2164                                         if (t->type == MONO_TYPE_R4)
2165                                                 linfo->args [i].storage = LLVMArgInFPReg;
2166                                         else if (t->type == MONO_TYPE_R8)
2167                                                 linfo->args [i].storage = LLVMArgInFPReg;
2168                                 }
2169                         }
2170                         break;
2171                 case ArgValuetypeInReg:
2172                         if (sig->pinvoke) {
2173                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2174                                 cfg->disable_llvm = TRUE;
2175                                 return linfo;
2176                         }
2177
2178                         linfo->args [i].storage = LLVMArgVtypeInReg;
2179                         for (j = 0; j < 2; ++j)
2180                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2181                         break;
2182                 default:
2183                         cfg->exception_message = g_strdup ("ainfo->storage");
2184                         cfg->disable_llvm = TRUE;
2185                         break;
2186                 }
2187         }
2188
2189         return linfo;
2190 }
2191 #endif
2192
2193 void
2194 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2195 {
2196         MonoInst *arg, *in;
2197         MonoMethodSignature *sig;
2198         MonoType *sig_ret;
2199         int i, n, stack_size;
2200         CallInfo *cinfo;
2201         ArgInfo *ainfo;
2202
2203         stack_size = 0;
2204
2205         sig = call->signature;
2206         n = sig->param_count + sig->hasthis;
2207
2208         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2209
2210         sig_ret = sig->ret;
2211
2212         if (COMPILE_LLVM (cfg)) {
2213                 /* We shouldn't be called in the llvm case */
2214                 cfg->disable_llvm = TRUE;
2215                 return;
2216         }
2217
2218         /*
2219          * Emit all arguments which are passed on the stack to prevent register
2220          * allocation problems.
2221          */
2222         for (i = 0; i < n; ++i) {
2223                 MonoType *t;
2224                 ainfo = cinfo->args + i;
2225
2226                 in = call->args [i];
2227
2228                 if (sig->hasthis && i == 0)
2229                         t = &mono_defaults.object_class->byval_arg;
2230                 else
2231                         t = sig->params [i - sig->hasthis];
2232
2233                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2234                         if (!t->byref) {
2235                                 if (t->type == MONO_TYPE_R4)
2236                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2237                                 else if (t->type == MONO_TYPE_R8)
2238                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2239                                 else
2240                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2241                         } else {
2242                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2243                         }
2244                         if (cfg->compute_gc_maps) {
2245                                 MonoInst *def;
2246
2247                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2248                         }
2249                 }
2250         }
2251
2252         /*
2253          * Emit all parameters passed in registers in non-reverse order for better readability
2254          * and to help the optimization in emit_prolog ().
2255          */
2256         for (i = 0; i < n; ++i) {
2257                 ainfo = cinfo->args + i;
2258
2259                 in = call->args [i];
2260
2261                 if (ainfo->storage == ArgInIReg)
2262                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2263         }
2264
2265         for (i = n - 1; i >= 0; --i) {
2266                 ainfo = cinfo->args + i;
2267
2268                 in = call->args [i];
2269
2270                 switch (ainfo->storage) {
2271                 case ArgInIReg:
2272                         /* Already done */
2273                         break;
2274                 case ArgInFloatSSEReg:
2275                 case ArgInDoubleSSEReg:
2276                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2277                         break;
2278                 case ArgOnStack:
2279                 case ArgValuetypeInReg:
2280                 case ArgValuetypeAddrInIReg:
2281                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2282                                 MonoInst *call_inst = (MonoInst*)call;
2283                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2284                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2285                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2286                                 guint32 align;
2287                                 guint32 size;
2288
2289                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2290                                         size = sizeof (MonoTypedRef);
2291                                         align = sizeof (gpointer);
2292                                 }
2293                                 else {
2294                                         if (sig->pinvoke)
2295                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2296                                         else {
2297                                                 /*
2298                                                  * Other backends use mono_type_stack_size (), but that
2299                                                  * aligns the size to 8, which is larger than the size of
2300                                                  * the source, leading to reads of invalid memory if the
2301                                                  * source is at the end of address space.
2302                                                  */
2303                                                 size = mono_class_value_size (in->klass, &align);
2304                                         }
2305                                 }
2306                                 g_assert (in->klass);
2307
2308                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2309                                         /* Avoid asserts in emit_memcpy () */
2310                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2311                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2312                                         /* Continue normally */
2313                                 }
2314
2315                                 if (size > 0) {
2316                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2317                                         arg->sreg1 = in->dreg;
2318                                         arg->klass = in->klass;
2319                                         arg->backend.size = size;
2320                                         arg->inst_p0 = call;
2321                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2322                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2323
2324                                         MONO_ADD_INS (cfg->cbb, arg);
2325                                 }
2326                         }
2327                         break;
2328                 default:
2329                         g_assert_not_reached ();
2330                 }
2331
2332                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2333                         /* Emit the signature cookie just before the implicit arguments */
2334                         emit_sig_cookie (cfg, call, cinfo);
2335         }
2336
2337         /* Handle the case where there are no implicit arguments */
2338         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2339                 emit_sig_cookie (cfg, call, cinfo);
2340
2341         sig_ret = mini_replace_type (sig->ret);
2342         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2343                 MonoInst *vtarg;
2344
2345                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2346                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2347                                 /*
2348                                  * Tell the JIT to use a more efficient calling convention: call using
2349                                  * OP_CALL, compute the result location after the call, and save the
2350                                  * result there.
2351                                  */
2352                                 call->vret_in_reg = TRUE;
2353                                 /*
2354                                  * Nullify the instruction computing the vret addr to enable
2355                                  * future optimizations.
2356                                  */
2357                                 if (call->vret_var)
2358                                         NULLIFY_INS (call->vret_var);
2359                         } else {
2360                                 if (call->tail_call)
2361                                         NOT_IMPLEMENTED;
2362                                 /*
2363                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2364                                  * the stack. Push the address here, so the call instruction can
2365                                  * access it.
2366                                  */
2367                                 if (!cfg->arch.vret_addr_loc) {
2368                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2369                                         /* Prevent it from being register allocated or optimized away */
2370                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2371                                 }
2372
2373                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2374                         }
2375                 }
2376                 else {
2377                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2378                         vtarg->sreg1 = call->vret_var->dreg;
2379                         vtarg->dreg = mono_alloc_preg (cfg);
2380                         MONO_ADD_INS (cfg->cbb, vtarg);
2381
2382                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2383                 }
2384         }
2385
2386         if (cfg->method->save_lmf) {
2387                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2388                 MONO_ADD_INS (cfg->cbb, arg);
2389         }
2390
2391         call->stack_usage = cinfo->stack_usage;
2392 }
2393
2394 void
2395 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2396 {
2397         MonoInst *arg;
2398         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2399         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2400         int size = ins->backend.size;
2401
2402         if (ainfo->storage == ArgValuetypeInReg) {
2403                 MonoInst *load;
2404                 int part;
2405
2406                 for (part = 0; part < 2; ++part) {
2407                         if (ainfo->pair_storage [part] == ArgNone)
2408                                 continue;
2409
2410                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2411                         load->inst_basereg = src->dreg;
2412                         load->inst_offset = part * sizeof(mgreg_t);
2413
2414                         switch (ainfo->pair_storage [part]) {
2415                         case ArgInIReg:
2416                                 load->dreg = mono_alloc_ireg (cfg);
2417                                 break;
2418                         case ArgInDoubleSSEReg:
2419                         case ArgInFloatSSEReg:
2420                                 load->dreg = mono_alloc_freg (cfg);
2421                                 break;
2422                         default:
2423                                 g_assert_not_reached ();
2424                         }
2425                         MONO_ADD_INS (cfg->cbb, load);
2426
2427                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2428                 }
2429         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2430                 MonoInst *vtaddr, *load;
2431                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2432
2433                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2434                 cfg->has_indirection = TRUE;
2435                 load->inst_p0 = vtaddr;
2436                 vtaddr->flags |= MONO_INST_INDIRECT;
2437                 load->type = STACK_MP;
2438                 load->klass = vtaddr->klass;
2439                 load->dreg = mono_alloc_ireg (cfg);
2440                 MONO_ADD_INS (cfg->cbb, load);
2441                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2442
2443                 if (ainfo->pair_storage [0] == ArgInIReg) {
2444                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2445                         arg->dreg = mono_alloc_ireg (cfg);
2446                         arg->sreg1 = load->dreg;
2447                         arg->inst_imm = 0;
2448                         MONO_ADD_INS (cfg->cbb, arg);
2449                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2450                 } else {
2451                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2452                 }
2453         } else {
2454                 if (size == 8) {
2455                         int dreg = mono_alloc_ireg (cfg);
2456
2457                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2458                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2459                 } else if (size <= 40) {
2460                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2461                 } else {
2462                         // FIXME: Code growth
2463                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2464                 }
2465
2466                 if (cfg->compute_gc_maps) {
2467                         MonoInst *def;
2468                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2469                 }
2470         }
2471 }
2472
2473 void
2474 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2475 {
2476         MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2477
2478         if (ret->type == MONO_TYPE_R4) {
2479                 if (COMPILE_LLVM (cfg))
2480                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2481                 else
2482                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2483                 return;
2484         } else if (ret->type == MONO_TYPE_R8) {
2485                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2486                 return;
2487         }
2488
2489         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2490 }
2491
2492 #endif /* DISABLE_JIT */
2493
2494 #define EMIT_COND_BRANCH(ins,cond,sign) \
2495         if (ins->inst_true_bb->native_offset) { \
2496                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2497         } else { \
2498                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2499                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2500             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2501                         x86_branch8 (code, cond, 0, sign); \
2502                 else \
2503                         x86_branch32 (code, cond, 0, sign); \
2504 }
2505
2506 typedef struct {
2507         MonoMethodSignature *sig;
2508         CallInfo *cinfo;
2509 } ArchDynCallInfo;
2510
2511 static gboolean
2512 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2513 {
2514         int i;
2515
2516 #ifdef HOST_WIN32
2517         return FALSE;
2518 #endif
2519
2520         switch (cinfo->ret.storage) {
2521         case ArgNone:
2522         case ArgInIReg:
2523                 break;
2524         case ArgValuetypeInReg: {
2525                 ArgInfo *ainfo = &cinfo->ret;
2526
2527                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2528                         return FALSE;
2529                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2530                         return FALSE;
2531                 break;
2532         }
2533         default:
2534                 return FALSE;
2535         }
2536
2537         for (i = 0; i < cinfo->nargs; ++i) {
2538                 ArgInfo *ainfo = &cinfo->args [i];
2539                 switch (ainfo->storage) {
2540                 case ArgInIReg:
2541                         break;
2542                 case ArgValuetypeInReg:
2543                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2544                                 return FALSE;
2545                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2546                                 return FALSE;
2547                         break;
2548                 default:
2549                         return FALSE;
2550                 }
2551         }
2552
2553         return TRUE;
2554 }
2555
2556 /*
2557  * mono_arch_dyn_call_prepare:
2558  *
2559  *   Return a pointer to an arch-specific structure which contains information
2560  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2561  * supported for SIG.
2562  * This function is equivalent to ffi_prep_cif in libffi.
2563  */
2564 MonoDynCallInfo*
2565 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2566 {
2567         ArchDynCallInfo *info;
2568         CallInfo *cinfo;
2569
2570         cinfo = get_call_info (NULL, NULL, sig);
2571
2572         if (!dyn_call_supported (sig, cinfo)) {
2573                 g_free (cinfo);
2574                 return NULL;
2575         }
2576
2577         info = g_new0 (ArchDynCallInfo, 1);
2578         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2579         info->sig = sig;
2580         info->cinfo = cinfo;
2581
2582         return (MonoDynCallInfo*)info;
2583 }
2584
2585 /*
2586  * mono_arch_dyn_call_free:
2587  *
2588  *   Free a MonoDynCallInfo structure.
2589  */
2590 void
2591 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2592 {
2593         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2594
2595         g_free (ainfo->cinfo);
2596         g_free (ainfo);
2597 }
2598
2599 #if !defined(__native_client__)
2600 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2601 #define GREG_TO_PTR(greg) (gpointer)(greg)
2602 #else
2603 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2604 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2605 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2606 #endif
2607
2608 /*
2609  * mono_arch_get_start_dyn_call:
2610  *
2611  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2612  * store the result into BUF.
2613  * ARGS should be an array of pointers pointing to the arguments.
2614  * RET should point to a memory buffer large enought to hold the result of the
2615  * call.
2616  * This function should be as fast as possible, any work which does not depend
2617  * on the actual values of the arguments should be done in
2618  * mono_arch_dyn_call_prepare ().
2619  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2620  * libffi.
2621  */
2622 void
2623 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2624 {
2625         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2626         DynCallArgs *p = (DynCallArgs*)buf;
2627         int arg_index, greg, i, pindex;
2628         MonoMethodSignature *sig = dinfo->sig;
2629
2630         g_assert (buf_len >= sizeof (DynCallArgs));
2631
2632         p->res = 0;
2633         p->ret = ret;
2634
2635         arg_index = 0;
2636         greg = 0;
2637         pindex = 0;
2638
2639         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2640                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2641                 if (!sig->hasthis)
2642                         pindex = 1;
2643         }
2644
2645         if (dinfo->cinfo->vtype_retaddr)
2646                 p->regs [greg ++] = PTR_TO_GREG(ret);
2647
2648         for (i = pindex; i < sig->param_count; i++) {
2649                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2650                 gpointer *arg = args [arg_index ++];
2651
2652                 if (t->byref) {
2653                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2654                         continue;
2655                 }
2656
2657                 switch (t->type) {
2658                 case MONO_TYPE_STRING:
2659                 case MONO_TYPE_CLASS:
2660                 case MONO_TYPE_ARRAY:
2661                 case MONO_TYPE_SZARRAY:
2662                 case MONO_TYPE_OBJECT:
2663                 case MONO_TYPE_PTR:
2664                 case MONO_TYPE_I:
2665                 case MONO_TYPE_U:
2666 #if !defined(__mono_ilp32__)
2667                 case MONO_TYPE_I8:
2668                 case MONO_TYPE_U8:
2669 #endif
2670                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2671                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2672                         break;
2673 #if defined(__mono_ilp32__)
2674                 case MONO_TYPE_I8:
2675                 case MONO_TYPE_U8:
2676                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2677                         p->regs [greg ++] = *(guint64*)(arg);
2678                         break;
2679 #endif
2680                 case MONO_TYPE_BOOLEAN:
2681                 case MONO_TYPE_U1:
2682                         p->regs [greg ++] = *(guint8*)(arg);
2683                         break;
2684                 case MONO_TYPE_I1:
2685                         p->regs [greg ++] = *(gint8*)(arg);
2686                         break;
2687                 case MONO_TYPE_I2:
2688                         p->regs [greg ++] = *(gint16*)(arg);
2689                         break;
2690                 case MONO_TYPE_U2:
2691                 case MONO_TYPE_CHAR:
2692                         p->regs [greg ++] = *(guint16*)(arg);
2693                         break;
2694                 case MONO_TYPE_I4:
2695                         p->regs [greg ++] = *(gint32*)(arg);
2696                         break;
2697                 case MONO_TYPE_U4:
2698                         p->regs [greg ++] = *(guint32*)(arg);
2699                         break;
2700                 case MONO_TYPE_GENERICINST:
2701                     if (MONO_TYPE_IS_REFERENCE (t)) {
2702                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2703                                 break;
2704                         } else {
2705                                 /* Fall through */
2706                         }
2707                 case MONO_TYPE_VALUETYPE: {
2708                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2709
2710                         g_assert (ainfo->storage == ArgValuetypeInReg);
2711                         if (ainfo->pair_storage [0] != ArgNone) {
2712                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2713                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2714                         }
2715                         if (ainfo->pair_storage [1] != ArgNone) {
2716                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2717                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2718                         }
2719                         break;
2720                 }
2721                 default:
2722                         g_assert_not_reached ();
2723                 }
2724         }
2725
2726         g_assert (greg <= PARAM_REGS);
2727 }
2728
2729 /*
2730  * mono_arch_finish_dyn_call:
2731  *
2732  *   Store the result of a dyn call into the return value buffer passed to
2733  * start_dyn_call ().
2734  * This function should be as fast as possible, any work which does not depend
2735  * on the actual values of the arguments should be done in
2736  * mono_arch_dyn_call_prepare ().
2737  */
2738 void
2739 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2740 {
2741         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2742         MonoMethodSignature *sig = dinfo->sig;
2743         guint8 *ret = ((DynCallArgs*)buf)->ret;
2744         mgreg_t res = ((DynCallArgs*)buf)->res;
2745         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2746
2747         switch (sig_ret->type) {
2748         case MONO_TYPE_VOID:
2749                 *(gpointer*)ret = NULL;
2750                 break;
2751         case MONO_TYPE_STRING:
2752         case MONO_TYPE_CLASS:
2753         case MONO_TYPE_ARRAY:
2754         case MONO_TYPE_SZARRAY:
2755         case MONO_TYPE_OBJECT:
2756         case MONO_TYPE_I:
2757         case MONO_TYPE_U:
2758         case MONO_TYPE_PTR:
2759                 *(gpointer*)ret = GREG_TO_PTR(res);
2760                 break;
2761         case MONO_TYPE_I1:
2762                 *(gint8*)ret = res;
2763                 break;
2764         case MONO_TYPE_U1:
2765         case MONO_TYPE_BOOLEAN:
2766                 *(guint8*)ret = res;
2767                 break;
2768         case MONO_TYPE_I2:
2769                 *(gint16*)ret = res;
2770                 break;
2771         case MONO_TYPE_U2:
2772         case MONO_TYPE_CHAR:
2773                 *(guint16*)ret = res;
2774                 break;
2775         case MONO_TYPE_I4:
2776                 *(gint32*)ret = res;
2777                 break;
2778         case MONO_TYPE_U4:
2779                 *(guint32*)ret = res;
2780                 break;
2781         case MONO_TYPE_I8:
2782                 *(gint64*)ret = res;
2783                 break;
2784         case MONO_TYPE_U8:
2785                 *(guint64*)ret = res;
2786                 break;
2787         case MONO_TYPE_GENERICINST:
2788                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2789                         *(gpointer*)ret = GREG_TO_PTR(res);
2790                         break;
2791                 } else {
2792                         /* Fall through */
2793                 }
2794         case MONO_TYPE_VALUETYPE:
2795                 if (dinfo->cinfo->vtype_retaddr) {
2796                         /* Nothing to do */
2797                 } else {
2798                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2799
2800                         g_assert (ainfo->storage == ArgValuetypeInReg);
2801
2802                         if (ainfo->pair_storage [0] != ArgNone) {
2803                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2804                                 ((mgreg_t*)ret)[0] = res;
2805                         }
2806
2807                         g_assert (ainfo->pair_storage [1] == ArgNone);
2808                 }
2809                 break;
2810         default:
2811                 g_assert_not_reached ();
2812         }
2813 }
2814
2815 /* emit an exception if condition is fail */
2816 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2817         do {                                                        \
2818                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2819                 if (tins == NULL) {                                                                             \
2820                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2821                                         MONO_PATCH_INFO_EXC, exc_name);  \
2822                         x86_branch32 (code, cond, 0, signed);               \
2823                 } else {        \
2824                         EMIT_COND_BRANCH (tins, cond, signed);  \
2825                 }                       \
2826         } while (0);
2827
2828 #define EMIT_FPCOMPARE(code) do { \
2829         amd64_fcompp (code); \
2830         amd64_fnstsw (code); \
2831 } while (0);
2832
2833 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2834     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2835         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2836         amd64_ ##op (code); \
2837         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2838         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2839 } while (0);
2840
2841 static guint8*
2842 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2843 {
2844         gboolean no_patch = FALSE;
2845
2846         /*
2847          * FIXME: Add support for thunks
2848          */
2849         {
2850                 gboolean near_call = FALSE;
2851
2852                 /*
2853                  * Indirect calls are expensive so try to make a near call if possible.
2854                  * The caller memory is allocated by the code manager so it is
2855                  * guaranteed to be at a 32 bit offset.
2856                  */
2857
2858                 if (patch_type != MONO_PATCH_INFO_ABS) {
2859                         /* The target is in memory allocated using the code manager */
2860                         near_call = TRUE;
2861
2862                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2863                                 if (((MonoMethod*)data)->klass->image->aot_module)
2864                                         /* The callee might be an AOT method */
2865                                         near_call = FALSE;
2866                                 if (((MonoMethod*)data)->dynamic)
2867                                         /* The target is in malloc-ed memory */
2868                                         near_call = FALSE;
2869                         }
2870
2871                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2872                                 /*
2873                                  * The call might go directly to a native function without
2874                                  * the wrapper.
2875                                  */
2876                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2877                                 if (mi) {
2878                                         gconstpointer target = mono_icall_get_wrapper (mi);
2879                                         if ((((guint64)target) >> 32) != 0)
2880                                                 near_call = FALSE;
2881                                 }
2882                         }
2883                 }
2884                 else {
2885                         MonoJumpInfo *jinfo = NULL;
2886
2887                         if (cfg->abs_patches)
2888                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2889                         if (jinfo) {
2890                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2891                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2892                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2893                                                 near_call = TRUE;
2894                                         no_patch = TRUE;
2895                                 } else {
2896                                         /*
2897                                          * This is not really an optimization, but required because the
2898                                          * generic class init trampolines use R11 to pass the vtable.
2899                                          */
2900                                         near_call = TRUE;
2901                                 }
2902                         } else {
2903                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2904                                 if (info) {
2905                                         if (info->func == info->wrapper) {
2906                                                 /* No wrapper */
2907                                                 if ((((guint64)info->func) >> 32) == 0)
2908                                                         near_call = TRUE;
2909                                         }
2910                                         else {
2911                                                 /* See the comment in mono_codegen () */
2912                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2913                                                         near_call = TRUE;
2914                                         }
2915                                 }
2916                                 else if ((((guint64)data) >> 32) == 0) {
2917                                         near_call = TRUE;
2918                                         no_patch = TRUE;
2919                                 }
2920                         }
2921                 }
2922
2923                 if (cfg->method->dynamic)
2924                         /* These methods are allocated using malloc */
2925                         near_call = FALSE;
2926
2927 #ifdef MONO_ARCH_NOMAP32BIT
2928                 near_call = FALSE;
2929 #endif
2930 #if defined(__native_client__)
2931                 /* Always use near_call == TRUE for Native Client */
2932                 near_call = TRUE;
2933 #endif
2934                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2935                 if (optimize_for_xen)
2936                         near_call = FALSE;
2937
2938                 if (cfg->compile_aot) {
2939                         near_call = TRUE;
2940                         no_patch = TRUE;
2941                 }
2942
2943                 if (near_call) {
2944                         /*
2945                          * Align the call displacement to an address divisible by 4 so it does
2946                          * not span cache lines. This is required for code patching to work on SMP
2947                          * systems.
2948                          */
2949                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2950                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2951                                 amd64_padding (code, pad_size);
2952                         }
2953                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2954                         amd64_call_code (code, 0);
2955                 }
2956                 else {
2957                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2958                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2959                         amd64_call_reg (code, GP_SCRATCH_REG);
2960                 }
2961         }
2962
2963         return code;
2964 }
2965
2966 static inline guint8*
2967 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2968 {
2969 #ifdef HOST_WIN32
2970         if (win64_adjust_stack)
2971                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2972 #endif
2973         code = emit_call_body (cfg, code, patch_type, data);
2974 #ifdef HOST_WIN32
2975         if (win64_adjust_stack)
2976                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2977 #endif
2978
2979         return code;
2980 }
2981
2982 static inline int
2983 store_membase_imm_to_store_membase_reg (int opcode)
2984 {
2985         switch (opcode) {
2986         case OP_STORE_MEMBASE_IMM:
2987                 return OP_STORE_MEMBASE_REG;
2988         case OP_STOREI4_MEMBASE_IMM:
2989                 return OP_STOREI4_MEMBASE_REG;
2990         case OP_STOREI8_MEMBASE_IMM:
2991                 return OP_STOREI8_MEMBASE_REG;
2992         }
2993
2994         return -1;
2995 }
2996
2997 #ifndef DISABLE_JIT
2998
2999 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3000
3001 /*
3002  * mono_arch_peephole_pass_1:
3003  *
3004  *   Perform peephole opts which should/can be performed before local regalloc
3005  */
3006 void
3007 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3008 {
3009         MonoInst *ins, *n;
3010
3011         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3012                 MonoInst *last_ins = ins->prev;
3013
3014                 switch (ins->opcode) {
3015                 case OP_ADD_IMM:
3016                 case OP_IADD_IMM:
3017                 case OP_LADD_IMM:
3018                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3019                                 /*
3020                                  * X86_LEA is like ADD, but doesn't have the
3021                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3022                                  * its operand to 64 bit.
3023                                  */
3024                                 ins->opcode = OP_X86_LEA_MEMBASE;
3025                                 ins->inst_basereg = ins->sreg1;
3026                         }
3027                         break;
3028                 case OP_LXOR:
3029                 case OP_IXOR:
3030                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3031                                 MonoInst *ins2;
3032
3033                                 /*
3034                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3035                                  * the latter has length 2-3 instead of 6 (reverse constant
3036                                  * propagation). These instruction sequences are very common
3037                                  * in the initlocals bblock.
3038                                  */
3039                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3040                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3041                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3042                                                 ins2->sreg1 = ins->dreg;
3043                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3044                                                 /* Continue */
3045                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3046                                                 NULLIFY_INS (ins2);
3047                                                 /* Continue */
3048                                         } else {
3049                                                 break;
3050                                         }
3051                                 }
3052                         }
3053                         break;
3054                 case OP_COMPARE_IMM:
3055                 case OP_LCOMPARE_IMM:
3056                         /* OP_COMPARE_IMM (reg, 0)
3057                          * -->
3058                          * OP_AMD64_TEST_NULL (reg)
3059                          */
3060                         if (!ins->inst_imm)
3061                                 ins->opcode = OP_AMD64_TEST_NULL;
3062                         break;
3063                 case OP_ICOMPARE_IMM:
3064                         if (!ins->inst_imm)
3065                                 ins->opcode = OP_X86_TEST_NULL;
3066                         break;
3067                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3068                         /*
3069                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3070                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3071                          * -->
3072                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3073                          * OP_COMPARE_IMM reg, imm
3074                          *
3075                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3076                          */
3077                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3078                             ins->inst_basereg == last_ins->inst_destbasereg &&
3079                             ins->inst_offset == last_ins->inst_offset) {
3080                                         ins->opcode = OP_ICOMPARE_IMM;
3081                                         ins->sreg1 = last_ins->sreg1;
3082
3083                                         /* check if we can remove cmp reg,0 with test null */
3084                                         if (!ins->inst_imm)
3085                                                 ins->opcode = OP_X86_TEST_NULL;
3086                                 }
3087
3088                         break;
3089                 }
3090
3091                 mono_peephole_ins (bb, ins);
3092         }
3093 }
3094
3095 void
3096 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3097 {
3098         MonoInst *ins, *n;
3099
3100         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3101                 switch (ins->opcode) {
3102                 case OP_ICONST:
3103                 case OP_I8CONST: {
3104                         /* reg = 0 -> XOR (reg, reg) */
3105                         /* XOR sets cflags on x86, so we cant do it always */
3106                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3107                                 ins->opcode = OP_LXOR;
3108                                 ins->sreg1 = ins->dreg;
3109                                 ins->sreg2 = ins->dreg;
3110                                 /* Fall through */
3111                         } else {
3112                                 break;
3113                         }
3114                 }
3115                 case OP_LXOR:
3116                         /*
3117                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3118                          * 0 result into 64 bits.
3119                          */
3120                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3121                                 ins->opcode = OP_IXOR;
3122                         }
3123                         /* Fall through */
3124                 case OP_IXOR:
3125                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3126                                 MonoInst *ins2;
3127
3128                                 /*
3129                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3130                                  * the latter has length 2-3 instead of 6 (reverse constant
3131                                  * propagation). These instruction sequences are very common
3132                                  * in the initlocals bblock.
3133                                  */
3134                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3135                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3136                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3137                                                 ins2->sreg1 = ins->dreg;
3138                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3139                                                 /* Continue */
3140                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3141                                                 NULLIFY_INS (ins2);
3142                                                 /* Continue */
3143                                         } else {
3144                                                 break;
3145                                         }
3146                                 }
3147                         }
3148                         break;
3149                 case OP_IADD_IMM:
3150                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3151                                 ins->opcode = OP_X86_INC_REG;
3152                         break;
3153                 case OP_ISUB_IMM:
3154                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3155                                 ins->opcode = OP_X86_DEC_REG;
3156                         break;
3157                 }
3158
3159                 mono_peephole_ins (bb, ins);
3160         }
3161 }
3162
3163 #define NEW_INS(cfg,ins,dest,op) do {   \
3164                 MONO_INST_NEW ((cfg), (dest), (op)); \
3165         (dest)->cil_code = (ins)->cil_code; \
3166         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3167         } while (0)
3168
3169 /*
3170  * mono_arch_lowering_pass:
3171  *
3172  *  Converts complex opcodes into simpler ones so that each IR instruction
3173  * corresponds to one machine instruction.
3174  */
3175 void
3176 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3177 {
3178         MonoInst *ins, *n, *temp;
3179
3180         /*
3181          * FIXME: Need to add more instructions, but the current machine
3182          * description can't model some parts of the composite instructions like
3183          * cdq.
3184          */
3185         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3186                 switch (ins->opcode) {
3187                 case OP_DIV_IMM:
3188                 case OP_REM_IMM:
3189                 case OP_IDIV_IMM:
3190                 case OP_IDIV_UN_IMM:
3191                 case OP_IREM_UN_IMM:
3192                 case OP_LREM_IMM:
3193                 case OP_IREM_IMM:
3194                         mono_decompose_op_imm (cfg, bb, ins);
3195                         break;
3196                 case OP_COMPARE_IMM:
3197                 case OP_LCOMPARE_IMM:
3198                         if (!amd64_is_imm32 (ins->inst_imm)) {
3199                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3200                                 temp->inst_c0 = ins->inst_imm;
3201                                 temp->dreg = mono_alloc_ireg (cfg);
3202                                 ins->opcode = OP_COMPARE;
3203                                 ins->sreg2 = temp->dreg;
3204                         }
3205                         break;
3206 #ifndef __mono_ilp32__
3207                 case OP_LOAD_MEMBASE:
3208 #endif
3209                 case OP_LOADI8_MEMBASE:
3210 #ifndef __native_client_codegen__
3211                 /*  Don't generate memindex opcodes (to simplify */
3212                 /*  read sandboxing) */
3213                         if (!amd64_is_imm32 (ins->inst_offset)) {
3214                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3215                                 temp->inst_c0 = ins->inst_offset;
3216                                 temp->dreg = mono_alloc_ireg (cfg);
3217                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3218                                 ins->inst_indexreg = temp->dreg;
3219                         }
3220 #endif
3221                         break;
3222 #ifndef __mono_ilp32__
3223                 case OP_STORE_MEMBASE_IMM:
3224 #endif
3225                 case OP_STOREI8_MEMBASE_IMM:
3226                         if (!amd64_is_imm32 (ins->inst_imm)) {
3227                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3228                                 temp->inst_c0 = ins->inst_imm;
3229                                 temp->dreg = mono_alloc_ireg (cfg);
3230                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3231                                 ins->sreg1 = temp->dreg;
3232                         }
3233                         break;
3234 #ifdef MONO_ARCH_SIMD_INTRINSICS
3235                 case OP_EXPAND_I1: {
3236                                 int temp_reg1 = mono_alloc_ireg (cfg);
3237                                 int temp_reg2 = mono_alloc_ireg (cfg);
3238                                 int original_reg = ins->sreg1;
3239
3240                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3241                                 temp->sreg1 = original_reg;
3242                                 temp->dreg = temp_reg1;
3243
3244                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3245                                 temp->sreg1 = temp_reg1;
3246                                 temp->dreg = temp_reg2;
3247                                 temp->inst_imm = 8;
3248
3249                                 NEW_INS (cfg, ins, temp, OP_LOR);
3250                                 temp->sreg1 = temp->dreg = temp_reg2;
3251                                 temp->sreg2 = temp_reg1;
3252
3253                                 ins->opcode = OP_EXPAND_I2;
3254                                 ins->sreg1 = temp_reg2;
3255                         }
3256                         break;
3257 #endif
3258                 default:
3259                         break;
3260                 }
3261         }
3262
3263         bb->max_vreg = cfg->next_vreg;
3264 }
3265
3266 static const int
3267 branch_cc_table [] = {
3268         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3269         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3270         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3271 };
3272
3273 /* Maps CMP_... constants to X86_CC_... constants */
3274 static const int
3275 cc_table [] = {
3276         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3277         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3278 };
3279
3280 static const int
3281 cc_signed_table [] = {
3282         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3283         FALSE, FALSE, FALSE, FALSE
3284 };
3285
3286 /*#include "cprop.c"*/
3287
3288 static unsigned char*
3289 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3290 {
3291         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3292
3293         if (size == 1)
3294                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3295         else if (size == 2)
3296                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3297         return code;
3298 }
3299
3300 static unsigned char*
3301 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3302 {
3303         int sreg = tree->sreg1;
3304         int need_touch = FALSE;
3305
3306 #if defined(HOST_WIN32)
3307         need_touch = TRUE;
3308 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3309         if (!tree->flags & MONO_INST_INIT)
3310                 need_touch = TRUE;
3311 #endif
3312
3313         if (need_touch) {
3314                 guint8* br[5];
3315
3316                 /*
3317                  * Under Windows:
3318                  * If requested stack size is larger than one page,
3319                  * perform stack-touch operation
3320                  */
3321                 /*
3322                  * Generate stack probe code.
3323                  * Under Windows, it is necessary to allocate one page at a time,
3324                  * "touching" stack after each successful sub-allocation. This is
3325                  * because of the way stack growth is implemented - there is a
3326                  * guard page before the lowest stack page that is currently commited.
3327                  * Stack normally grows sequentially so OS traps access to the
3328                  * guard page and commits more pages when needed.
3329                  */
3330                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3331                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3332
3333                 br[2] = code; /* loop */
3334                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3335                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3336                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3337                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3338                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3339                 amd64_patch (br[3], br[2]);
3340                 amd64_test_reg_reg (code, sreg, sreg);
3341                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3342                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3343
3344                 br[1] = code; x86_jump8 (code, 0);
3345
3346                 amd64_patch (br[0], code);
3347                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3348                 amd64_patch (br[1], code);
3349                 amd64_patch (br[4], code);
3350         }
3351         else
3352                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3353
3354         if (tree->flags & MONO_INST_INIT) {
3355                 int offset = 0;
3356                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3357                         amd64_push_reg (code, AMD64_RAX);
3358                         offset += 8;
3359                 }
3360                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3361                         amd64_push_reg (code, AMD64_RCX);
3362                         offset += 8;
3363                 }
3364                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3365                         amd64_push_reg (code, AMD64_RDI);
3366                         offset += 8;
3367                 }
3368
3369                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3370                 if (sreg != AMD64_RCX)
3371                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3372                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3373
3374                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3375                 if (cfg->param_area)
3376                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3377                 amd64_cld (code);
3378 #if defined(__default_codegen__)
3379                 amd64_prefix (code, X86_REP_PREFIX);
3380                 amd64_stosl (code);
3381 #elif defined(__native_client_codegen__)
3382                 /* NaCl stos pseudo-instruction */
3383                 amd64_codegen_pre(code);
3384                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3385                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3386                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3387                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3388                 amd64_prefix (code, X86_REP_PREFIX);
3389                 amd64_stosl (code);
3390                 amd64_codegen_post(code);
3391 #endif /* __native_client_codegen__ */
3392
3393                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3394                         amd64_pop_reg (code, AMD64_RDI);
3395                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3396                         amd64_pop_reg (code, AMD64_RCX);
3397                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3398                         amd64_pop_reg (code, AMD64_RAX);
3399         }
3400         return code;
3401 }
3402
3403 static guint8*
3404 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3405 {
3406         CallInfo *cinfo;
3407         guint32 quad;
3408
3409         /* Move return value to the target register */
3410         /* FIXME: do this in the local reg allocator */
3411         switch (ins->opcode) {
3412         case OP_CALL:
3413         case OP_CALL_REG:
3414         case OP_CALL_MEMBASE:
3415         case OP_LCALL:
3416         case OP_LCALL_REG:
3417         case OP_LCALL_MEMBASE:
3418                 g_assert (ins->dreg == AMD64_RAX);
3419                 break;
3420         case OP_FCALL:
3421         case OP_FCALL_REG:
3422         case OP_FCALL_MEMBASE:
3423                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3424                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3425                 }
3426                 else {
3427                         if (ins->dreg != AMD64_XMM0)
3428                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3429                 }
3430                 break;
3431         case OP_VCALL:
3432         case OP_VCALL_REG:
3433         case OP_VCALL_MEMBASE:
3434         case OP_VCALL2:
3435         case OP_VCALL2_REG:
3436         case OP_VCALL2_MEMBASE:
3437                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3438                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3439                         MonoInst *loc = cfg->arch.vret_addr_loc;
3440
3441                         /* Load the destination address */
3442                         g_assert (loc->opcode == OP_REGOFFSET);
3443                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3444
3445                         for (quad = 0; quad < 2; quad ++) {
3446                                 switch (cinfo->ret.pair_storage [quad]) {
3447                                 case ArgInIReg:
3448                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3449                                         break;
3450                                 case ArgInFloatSSEReg:
3451                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3452                                         break;
3453                                 case ArgInDoubleSSEReg:
3454                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3455                                         break;
3456                                 case ArgNone:
3457                                         break;
3458                                 default:
3459                                         NOT_IMPLEMENTED;
3460                                 }
3461                         }
3462                 }
3463                 break;
3464         }
3465
3466         return code;
3467 }
3468
3469 #endif /* DISABLE_JIT */
3470
3471 #ifdef __APPLE__
3472 static int tls_gs_offset;
3473 #endif
3474
3475 gboolean
3476 mono_amd64_have_tls_get (void)
3477 {
3478 #ifdef __APPLE__
3479         static gboolean have_tls_get = FALSE;
3480         static gboolean inited = FALSE;
3481         guint8 *ins;
3482
3483         if (inited)
3484                 return have_tls_get;
3485
3486         ins = (guint8*)pthread_getspecific;
3487
3488         /*
3489          * We're looking for these two instructions:
3490          *
3491          * mov    %gs:[offset](,%rdi,8),%rax
3492          * retq
3493          */
3494         have_tls_get = ins [0] == 0x65 &&
3495                        ins [1] == 0x48 &&
3496                        ins [2] == 0x8b &&
3497                        ins [3] == 0x04 &&
3498                        ins [4] == 0xfd &&
3499                        ins [6] == 0x00 &&
3500                        ins [7] == 0x00 &&
3501                        ins [8] == 0x00 &&
3502                        ins [9] == 0xc3;
3503
3504         inited = TRUE;
3505
3506         tls_gs_offset = ins[5];
3507
3508         return have_tls_get;
3509 #else
3510         return TRUE;
3511 #endif
3512 }
3513
3514 int
3515 mono_amd64_get_tls_gs_offset (void)
3516 {
3517 #ifdef TARGET_OSX
3518         return tls_gs_offset;
3519 #else
3520         g_assert_not_reached ();
3521         return -1;
3522 #endif
3523 }
3524
3525 /*
3526  * mono_amd64_emit_tls_get:
3527  * @code: buffer to store code to
3528  * @dreg: hard register where to place the result
3529  * @tls_offset: offset info
3530  *
3531  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3532  * the dreg register the item in the thread local storage identified
3533  * by tls_offset.
3534  *
3535  * Returns: a pointer to the end of the stored code
3536  */
3537 guint8*
3538 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3539 {
3540 #ifdef HOST_WIN32
3541         if (tls_offset < 64) {
3542                 x86_prefix (code, X86_GS_PREFIX);
3543                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3544         } else {
3545                 guint8 *buf [16];
3546
3547                 g_assert (tls_offset < 0x440);
3548                 /* Load TEB->TlsExpansionSlots */
3549                 x86_prefix (code, X86_GS_PREFIX);
3550                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3551                 amd64_test_reg_reg (code, dreg, dreg);
3552                 buf [0] = code;
3553                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3554                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3555                 amd64_patch (buf [0], code);
3556         }
3557 #elif defined(__APPLE__)
3558         x86_prefix (code, X86_GS_PREFIX);
3559         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3560 #else
3561         if (optimize_for_xen) {
3562                 x86_prefix (code, X86_FS_PREFIX);
3563                 amd64_mov_reg_mem (code, dreg, 0, 8);
3564                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3565         } else {
3566                 x86_prefix (code, X86_FS_PREFIX);
3567                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3568         }
3569 #endif
3570         return code;
3571 }
3572
3573 static guint8*
3574 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3575 {
3576         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3577 #ifdef TARGET_OSX
3578         if (dreg != offset_reg)
3579                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3580         amd64_prefix (code, X86_GS_PREFIX);
3581         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3582 #elif defined(__linux__)
3583         int tmpreg = -1;
3584
3585         if (dreg == offset_reg) {
3586                 /* Use a temporary reg by saving it to the redzone */
3587                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3588                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3589                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3590                 offset_reg = tmpreg;
3591         }
3592         x86_prefix (code, X86_FS_PREFIX);
3593         amd64_mov_reg_mem (code, dreg, 0, 8);
3594         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3595         if (tmpreg != -1)
3596                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3597 #else
3598         g_assert_not_reached ();
3599 #endif
3600         return code;
3601 }
3602
3603 static guint8*
3604 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3605 {
3606 #ifdef HOST_WIN32
3607         g_assert_not_reached ();
3608 #elif defined(__APPLE__)
3609         x86_prefix (code, X86_GS_PREFIX);
3610         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3611 #else
3612         g_assert (!optimize_for_xen);
3613         x86_prefix (code, X86_FS_PREFIX);
3614         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3615 #endif
3616         return code;
3617 }
3618
3619 static guint8*
3620 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3621 {
3622         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3623 #ifdef HOST_WIN32
3624         g_assert_not_reached ();
3625 #elif defined(__APPLE__)
3626         x86_prefix (code, X86_GS_PREFIX);
3627         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3628 #else
3629         x86_prefix (code, X86_FS_PREFIX);
3630         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3631 #endif
3632         return code;
3633 }
3634
3635  /*
3636  * mono_arch_translate_tls_offset:
3637  *
3638  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3639  */
3640 int
3641 mono_arch_translate_tls_offset (int offset)
3642 {
3643 #ifdef __APPLE__
3644         return tls_gs_offset + (offset * 8);
3645 #else
3646         return offset;
3647 #endif
3648 }
3649
3650 /*
3651  * emit_setup_lmf:
3652  *
3653  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3654  */
3655 static guint8*
3656 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3657 {
3658         /*
3659          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3660          */
3661         /*
3662          * sp is saved right before calls but we need to save it here too so
3663          * async stack walks would work.
3664          */
3665         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3666         /* Save rbp */
3667         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3668         if (cfg->arch.omit_fp && cfa_offset != -1)
3669                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3670
3671         /* These can't contain refs */
3672         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3673         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3674         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3675         /* These are handled automatically by the stack marking code */
3676         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3677
3678         return code;
3679 }
3680
3681 #define REAL_PRINT_REG(text,reg) \
3682 mono_assert (reg >= 0); \
3683 amd64_push_reg (code, AMD64_RAX); \
3684 amd64_push_reg (code, AMD64_RDX); \
3685 amd64_push_reg (code, AMD64_RCX); \
3686 amd64_push_reg (code, reg); \
3687 amd64_push_imm (code, reg); \
3688 amd64_push_imm (code, text " %d %p\n"); \
3689 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3690 amd64_call_reg (code, AMD64_RAX); \
3691 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3692 amd64_pop_reg (code, AMD64_RCX); \
3693 amd64_pop_reg (code, AMD64_RDX); \
3694 amd64_pop_reg (code, AMD64_RAX);
3695
3696 /* benchmark and set based on cpu */
3697 #define LOOP_ALIGNMENT 8
3698 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3699
3700 #ifndef DISABLE_JIT
3701 void
3702 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3703 {
3704         MonoInst *ins;
3705         MonoCallInst *call;
3706         guint offset;
3707         guint8 *code = cfg->native_code + cfg->code_len;
3708         MonoInst *last_ins = NULL;
3709         guint last_offset = 0;
3710         int max_len;
3711
3712         /* Fix max_offset estimate for each successor bb */
3713         if (cfg->opt & MONO_OPT_BRANCH) {
3714                 int current_offset = cfg->code_len;
3715                 MonoBasicBlock *current_bb;
3716                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3717                         current_bb->max_offset = current_offset;
3718                         current_offset += current_bb->max_length;
3719                 }
3720         }
3721
3722         if (cfg->opt & MONO_OPT_LOOP) {
3723                 int pad, align = LOOP_ALIGNMENT;
3724                 /* set alignment depending on cpu */
3725                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3726                         pad = align - pad;
3727                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3728                         amd64_padding (code, pad);
3729                         cfg->code_len += pad;
3730                         bb->native_offset = cfg->code_len;
3731                 }
3732         }
3733
3734 #if defined(__native_client_codegen__)
3735         /* For Native Client, all indirect call/jump targets must be */
3736         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3737         /* indirectly as well.                                       */
3738         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3739                                       (bb->flags & BB_EXCEPTION_HANDLER);
3740
3741         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3742                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3743                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3744                 cfg->code_len += pad;
3745                 bb->native_offset = cfg->code_len;
3746         }
3747 #endif  /*__native_client_codegen__*/
3748
3749         if (cfg->verbose_level > 2)
3750                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3751
3752         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3753                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3754                 g_assert (!cfg->compile_aot);
3755
3756                 cov->data [bb->dfn].cil_code = bb->cil_code;
3757                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3758                 /* this is not thread save, but good enough */
3759                 amd64_inc_membase (code, AMD64_R11, 0);
3760         }
3761
3762         offset = code - cfg->native_code;
3763
3764         mono_debug_open_block (cfg, bb, offset);
3765
3766     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3767                 x86_breakpoint (code);
3768
3769         MONO_BB_FOR_EACH_INS (bb, ins) {
3770                 offset = code - cfg->native_code;
3771
3772                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3773
3774 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3775
3776                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3777                         cfg->code_size *= 2;
3778                         cfg->native_code = mono_realloc_native_code(cfg);
3779                         code = cfg->native_code + offset;
3780                         cfg->stat_code_reallocs++;
3781                 }
3782
3783                 if (cfg->debug_info)
3784                         mono_debug_record_line_number (cfg, ins, offset);
3785
3786                 switch (ins->opcode) {
3787                 case OP_BIGMUL:
3788                         amd64_mul_reg (code, ins->sreg2, TRUE);
3789                         break;
3790                 case OP_BIGMUL_UN:
3791                         amd64_mul_reg (code, ins->sreg2, FALSE);
3792                         break;
3793                 case OP_X86_SETEQ_MEMBASE:
3794                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3795                         break;
3796                 case OP_STOREI1_MEMBASE_IMM:
3797                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3798                         break;
3799                 case OP_STOREI2_MEMBASE_IMM:
3800                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3801                         break;
3802                 case OP_STOREI4_MEMBASE_IMM:
3803                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3804                         break;
3805                 case OP_STOREI1_MEMBASE_REG:
3806                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3807                         break;
3808                 case OP_STOREI2_MEMBASE_REG:
3809                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3810                         break;
3811                 /* In AMD64 NaCl, pointers are 4 bytes, */
3812                 /*  so STORE_* != STOREI8_*. Likewise below. */
3813                 case OP_STORE_MEMBASE_REG:
3814                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3815                         break;
3816                 case OP_STOREI8_MEMBASE_REG:
3817                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3818                         break;
3819                 case OP_STOREI4_MEMBASE_REG:
3820                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3821                         break;
3822                 case OP_STORE_MEMBASE_IMM:
3823 #ifndef __native_client_codegen__
3824                         /* In NaCl, this could be a PCONST type, which could */
3825                         /* mean a pointer type was copied directly into the  */
3826                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3827                         /* the value would be 0x00000000FFFFFFFF which is    */
3828                         /* not proper for an imm32 unless you cast it.       */
3829                         g_assert (amd64_is_imm32 (ins->inst_imm));
3830 #endif
3831                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3832                         break;
3833                 case OP_STOREI8_MEMBASE_IMM:
3834                         g_assert (amd64_is_imm32 (ins->inst_imm));
3835                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3836                         break;
3837                 case OP_LOAD_MEM:
3838 #ifdef __mono_ilp32__
3839                         /* In ILP32, pointers are 4 bytes, so separate these */
3840                         /* cases, use literal 8 below where we really want 8 */
3841                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3842                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3843                         break;
3844 #endif
3845                 case OP_LOADI8_MEM:
3846                         // FIXME: Decompose this earlier
3847                         if (amd64_is_imm32 (ins->inst_imm))
3848                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3849                         else {
3850                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3851                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3852                         }
3853                         break;
3854                 case OP_LOADI4_MEM:
3855                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3856                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3857                         break;
3858                 case OP_LOADU4_MEM:
3859                         // FIXME: Decompose this earlier
3860                         if (amd64_is_imm32 (ins->inst_imm))
3861                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3862                         else {
3863                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3864                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3865                         }
3866                         break;
3867                 case OP_LOADU1_MEM:
3868                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3869                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3870                         break;
3871                 case OP_LOADU2_MEM:
3872                         /* For NaCl, pointers are 4 bytes, so separate these */
3873                         /* cases, use literal 8 below where we really want 8 */
3874                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3875                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3876                         break;
3877                 case OP_LOAD_MEMBASE:
3878                         g_assert (amd64_is_imm32 (ins->inst_offset));
3879                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3880                         break;
3881                 case OP_LOADI8_MEMBASE:
3882                         /* Use literal 8 instead of sizeof pointer or */
3883                         /* register, we really want 8 for this opcode */
3884                         g_assert (amd64_is_imm32 (ins->inst_offset));
3885                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3886                         break;
3887                 case OP_LOADI4_MEMBASE:
3888                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3889                         break;
3890                 case OP_LOADU4_MEMBASE:
3891                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3892                         break;
3893                 case OP_LOADU1_MEMBASE:
3894                         /* The cpu zero extends the result into 64 bits */
3895                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3896                         break;
3897                 case OP_LOADI1_MEMBASE:
3898                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3899                         break;
3900                 case OP_LOADU2_MEMBASE:
3901                         /* The cpu zero extends the result into 64 bits */
3902                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3903                         break;
3904                 case OP_LOADI2_MEMBASE:
3905                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3906                         break;
3907                 case OP_AMD64_LOADI8_MEMINDEX:
3908                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3909                         break;
3910                 case OP_LCONV_TO_I1:
3911                 case OP_ICONV_TO_I1:
3912                 case OP_SEXT_I1:
3913                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3914                         break;
3915                 case OP_LCONV_TO_I2:
3916                 case OP_ICONV_TO_I2:
3917                 case OP_SEXT_I2:
3918                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3919                         break;
3920                 case OP_LCONV_TO_U1:
3921                 case OP_ICONV_TO_U1:
3922                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3923                         break;
3924                 case OP_LCONV_TO_U2:
3925                 case OP_ICONV_TO_U2:
3926                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3927                         break;
3928                 case OP_ZEXT_I4:
3929                         /* Clean out the upper word */
3930                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3931                         break;
3932                 case OP_SEXT_I4:
3933                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3934                         break;
3935                 case OP_COMPARE:
3936                 case OP_LCOMPARE:
3937                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3938                         break;
3939                 case OP_COMPARE_IMM:
3940 #if defined(__mono_ilp32__)
3941                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3942                         g_assert (amd64_is_imm32 (ins->inst_imm));
3943                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3944                         break;
3945 #endif
3946                 case OP_LCOMPARE_IMM:
3947                         g_assert (amd64_is_imm32 (ins->inst_imm));
3948                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3949                         break;
3950                 case OP_X86_COMPARE_REG_MEMBASE:
3951                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3952                         break;
3953                 case OP_X86_TEST_NULL:
3954                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3955                         break;
3956                 case OP_AMD64_TEST_NULL:
3957                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3958                         break;
3959
3960                 case OP_X86_ADD_REG_MEMBASE:
3961                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3962                         break;
3963                 case OP_X86_SUB_REG_MEMBASE:
3964                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3965                         break;
3966                 case OP_X86_AND_REG_MEMBASE:
3967                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3968                         break;
3969                 case OP_X86_OR_REG_MEMBASE:
3970                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3971                         break;
3972                 case OP_X86_XOR_REG_MEMBASE:
3973                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3974                         break;
3975
3976                 case OP_X86_ADD_MEMBASE_IMM:
3977                         /* FIXME: Make a 64 version too */
3978                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3979                         break;
3980                 case OP_X86_SUB_MEMBASE_IMM:
3981                         g_assert (amd64_is_imm32 (ins->inst_imm));
3982                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3983                         break;
3984                 case OP_X86_AND_MEMBASE_IMM:
3985                         g_assert (amd64_is_imm32 (ins->inst_imm));
3986                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3987                         break;
3988                 case OP_X86_OR_MEMBASE_IMM:
3989                         g_assert (amd64_is_imm32 (ins->inst_imm));
3990                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3991                         break;
3992                 case OP_X86_XOR_MEMBASE_IMM:
3993                         g_assert (amd64_is_imm32 (ins->inst_imm));
3994                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3995                         break;
3996                 case OP_X86_ADD_MEMBASE_REG:
3997                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3998                         break;
3999                 case OP_X86_SUB_MEMBASE_REG:
4000                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4001                         break;
4002                 case OP_X86_AND_MEMBASE_REG:
4003                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4004                         break;
4005                 case OP_X86_OR_MEMBASE_REG:
4006                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4007                         break;
4008                 case OP_X86_XOR_MEMBASE_REG:
4009                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4010                         break;
4011                 case OP_X86_INC_MEMBASE:
4012                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4013                         break;
4014                 case OP_X86_INC_REG:
4015                         amd64_inc_reg_size (code, ins->dreg, 4);
4016                         break;
4017                 case OP_X86_DEC_MEMBASE:
4018                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4019                         break;
4020                 case OP_X86_DEC_REG:
4021                         amd64_dec_reg_size (code, ins->dreg, 4);
4022                         break;
4023                 case OP_X86_MUL_REG_MEMBASE:
4024                 case OP_X86_MUL_MEMBASE_REG:
4025                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4026                         break;
4027                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4028                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4029                         break;
4030                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4031                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4032                         break;
4033                 case OP_AMD64_COMPARE_MEMBASE_REG:
4034                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4035                         break;
4036                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4037                         g_assert (amd64_is_imm32 (ins->inst_imm));
4038                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4039                         break;
4040                 case OP_X86_COMPARE_MEMBASE8_IMM:
4041                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4042                         break;
4043                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4044                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4045                         break;
4046                 case OP_AMD64_COMPARE_REG_MEMBASE:
4047                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4048                         break;
4049
4050                 case OP_AMD64_ADD_REG_MEMBASE:
4051                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4052                         break;
4053                 case OP_AMD64_SUB_REG_MEMBASE:
4054                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4055                         break;
4056                 case OP_AMD64_AND_REG_MEMBASE:
4057                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4058                         break;
4059                 case OP_AMD64_OR_REG_MEMBASE:
4060                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4061                         break;
4062                 case OP_AMD64_XOR_REG_MEMBASE:
4063                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4064                         break;
4065
4066                 case OP_AMD64_ADD_MEMBASE_REG:
4067                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4068                         break;
4069                 case OP_AMD64_SUB_MEMBASE_REG:
4070                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4071                         break;
4072                 case OP_AMD64_AND_MEMBASE_REG:
4073                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4074                         break;
4075                 case OP_AMD64_OR_MEMBASE_REG:
4076                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4077                         break;
4078                 case OP_AMD64_XOR_MEMBASE_REG:
4079                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4080                         break;
4081
4082                 case OP_AMD64_ADD_MEMBASE_IMM:
4083                         g_assert (amd64_is_imm32 (ins->inst_imm));
4084                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4085                         break;
4086                 case OP_AMD64_SUB_MEMBASE_IMM:
4087                         g_assert (amd64_is_imm32 (ins->inst_imm));
4088                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4089                         break;
4090                 case OP_AMD64_AND_MEMBASE_IMM:
4091                         g_assert (amd64_is_imm32 (ins->inst_imm));
4092                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4093                         break;
4094                 case OP_AMD64_OR_MEMBASE_IMM:
4095                         g_assert (amd64_is_imm32 (ins->inst_imm));
4096                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4097                         break;
4098                 case OP_AMD64_XOR_MEMBASE_IMM:
4099                         g_assert (amd64_is_imm32 (ins->inst_imm));
4100                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4101                         break;
4102
4103                 case OP_BREAK:
4104                         amd64_breakpoint (code);
4105                         break;
4106                 case OP_RELAXED_NOP:
4107                         x86_prefix (code, X86_REP_PREFIX);
4108                         x86_nop (code);
4109                         break;
4110                 case OP_HARD_NOP:
4111                         x86_nop (code);
4112                         break;
4113                 case OP_NOP:
4114                 case OP_DUMMY_USE:
4115                 case OP_DUMMY_STORE:
4116                 case OP_DUMMY_ICONST:
4117                 case OP_DUMMY_R8CONST:
4118                 case OP_NOT_REACHED:
4119                 case OP_NOT_NULL:
4120                         break;
4121                 case OP_SEQ_POINT: {
4122                         int i;
4123
4124                         /*
4125                          * Read from the single stepping trigger page. This will cause a
4126                          * SIGSEGV when single stepping is enabled.
4127                          * We do this _before_ the breakpoint, so single stepping after
4128                          * a breakpoint is hit will step to the next IL offset.
4129                          */
4130                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4131                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4132
4133                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4134                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4135                         }
4136
4137                         /*
4138                          * This is the address which is saved in seq points,
4139                          */
4140                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4141
4142                         if (cfg->compile_aot) {
4143                                 guint32 offset = code - cfg->native_code;
4144                                 guint32 val;
4145                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4146
4147                                 /* Load info var */
4148                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4149                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4150                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4151                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4152                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4153                         } else {
4154                                 /*
4155                                  * A placeholder for a possible breakpoint inserted by
4156                                  * mono_arch_set_breakpoint ().
4157                                  */
4158                                 for (i = 0; i < breakpoint_size; ++i)
4159                                         x86_nop (code);
4160                         }
4161                         /*
4162                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4163                          * to another IL offset.
4164                          */
4165                         x86_nop (code);
4166                         break;
4167                 }
4168                 case OP_ADDCC:
4169                 case OP_LADDCC:
4170                 case OP_LADD:
4171                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4172                         break;
4173                 case OP_ADC:
4174                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4175                         break;
4176                 case OP_ADD_IMM:
4177                 case OP_LADD_IMM:
4178                         g_assert (amd64_is_imm32 (ins->inst_imm));
4179                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4180                         break;
4181                 case OP_ADC_IMM:
4182                         g_assert (amd64_is_imm32 (ins->inst_imm));
4183                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4184                         break;
4185                 case OP_SUBCC:
4186                 case OP_LSUBCC:
4187                 case OP_LSUB:
4188                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4189                         break;
4190                 case OP_SBB:
4191                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4192                         break;
4193                 case OP_SUB_IMM:
4194                 case OP_LSUB_IMM:
4195                         g_assert (amd64_is_imm32 (ins->inst_imm));
4196                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4197                         break;
4198                 case OP_SBB_IMM:
4199                         g_assert (amd64_is_imm32 (ins->inst_imm));
4200                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4201                         break;
4202                 case OP_LAND:
4203                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4204                         break;
4205                 case OP_AND_IMM:
4206                 case OP_LAND_IMM:
4207                         g_assert (amd64_is_imm32 (ins->inst_imm));
4208                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4209                         break;
4210                 case OP_LMUL:
4211                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4212                         break;
4213                 case OP_MUL_IMM:
4214                 case OP_LMUL_IMM:
4215                 case OP_IMUL_IMM: {
4216                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4217
4218                         switch (ins->inst_imm) {
4219                         case 2:
4220                                 /* MOV r1, r2 */
4221                                 /* ADD r1, r1 */
4222                                 if (ins->dreg != ins->sreg1)
4223                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4224                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4225                                 break;
4226                         case 3:
4227                                 /* LEA r1, [r2 + r2*2] */
4228                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4229                                 break;
4230                         case 5:
4231                                 /* LEA r1, [r2 + r2*4] */
4232                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4233                                 break;
4234                         case 6:
4235                                 /* LEA r1, [r2 + r2*2] */
4236                                 /* ADD r1, r1          */
4237                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4238                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4239                                 break;
4240                         case 9:
4241                                 /* LEA r1, [r2 + r2*8] */
4242                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4243                                 break;
4244                         case 10:
4245                                 /* LEA r1, [r2 + r2*4] */
4246                                 /* ADD r1, r1          */
4247                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4248                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4249                                 break;
4250                         case 12:
4251                                 /* LEA r1, [r2 + r2*2] */
4252                                 /* SHL r1, 2           */
4253                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4254                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4255                                 break;
4256                         case 25:
4257                                 /* LEA r1, [r2 + r2*4] */
4258                                 /* LEA r1, [r1 + r1*4] */
4259                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4260                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4261                                 break;
4262                         case 100:
4263                                 /* LEA r1, [r2 + r2*4] */
4264                                 /* SHL r1, 2           */
4265                                 /* LEA r1, [r1 + r1*4] */
4266                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4267                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4268                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4269                                 break;
4270                         default:
4271                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4272                                 break;
4273                         }
4274                         break;
4275                 }
4276                 case OP_LDIV:
4277                 case OP_LREM:
4278 #if defined( __native_client_codegen__ )
4279                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4280                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4281 #endif
4282                         /* Regalloc magic makes the div/rem cases the same */
4283                         if (ins->sreg2 == AMD64_RDX) {
4284                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4285                                 amd64_cdq (code);
4286                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4287                         } else {
4288                                 amd64_cdq (code);
4289                                 amd64_div_reg (code, ins->sreg2, TRUE);
4290                         }
4291                         break;
4292                 case OP_LDIV_UN:
4293                 case OP_LREM_UN:
4294 #if defined( __native_client_codegen__ )
4295                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4296                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4297 #endif
4298                         if (ins->sreg2 == AMD64_RDX) {
4299                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4300                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4301                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4302                         } else {
4303                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4304                                 amd64_div_reg (code, ins->sreg2, FALSE);
4305                         }
4306                         break;
4307                 case OP_IDIV:
4308                 case OP_IREM:
4309 #if defined( __native_client_codegen__ )
4310                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4311                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4312 #endif
4313                         if (ins->sreg2 == AMD64_RDX) {
4314                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4315                                 amd64_cdq_size (code, 4);
4316                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4317                         } else {
4318                                 amd64_cdq_size (code, 4);
4319                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4320                         }
4321                         break;
4322                 case OP_IDIV_UN:
4323                 case OP_IREM_UN:
4324 #if defined( __native_client_codegen__ )
4325                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4326                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4327 #endif
4328                         if (ins->sreg2 == AMD64_RDX) {
4329                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4330                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4331                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4332                         } else {
4333                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4334                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4335                         }
4336                         break;
4337                 case OP_LMUL_OVF:
4338                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4339                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4340                         break;
4341                 case OP_LOR:
4342                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4343                         break;
4344                 case OP_OR_IMM:
4345                 case OP_LOR_IMM:
4346                         g_assert (amd64_is_imm32 (ins->inst_imm));
4347                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4348                         break;
4349                 case OP_LXOR:
4350                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4351                         break;
4352                 case OP_XOR_IMM:
4353                 case OP_LXOR_IMM:
4354                         g_assert (amd64_is_imm32 (ins->inst_imm));
4355                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4356                         break;
4357                 case OP_LSHL:
4358                         g_assert (ins->sreg2 == AMD64_RCX);
4359                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4360                         break;
4361                 case OP_LSHR:
4362                         g_assert (ins->sreg2 == AMD64_RCX);
4363                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4364                         break;
4365                 case OP_SHR_IMM:
4366                         g_assert (amd64_is_imm32 (ins->inst_imm));
4367                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4368                         break;
4369                 case OP_LSHR_IMM:
4370                         g_assert (amd64_is_imm32 (ins->inst_imm));
4371                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4372                         break;
4373                 case OP_SHR_UN_IMM:
4374                         g_assert (amd64_is_imm32 (ins->inst_imm));
4375                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4376                         break;
4377                 case OP_LSHR_UN_IMM:
4378                         g_assert (amd64_is_imm32 (ins->inst_imm));
4379                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4380                         break;
4381                 case OP_LSHR_UN:
4382                         g_assert (ins->sreg2 == AMD64_RCX);
4383                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4384                         break;
4385                 case OP_SHL_IMM:
4386                         g_assert (amd64_is_imm32 (ins->inst_imm));
4387                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4388                         break;
4389                 case OP_LSHL_IMM:
4390                         g_assert (amd64_is_imm32 (ins->inst_imm));
4391                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4392                         break;
4393
4394                 case OP_IADDCC:
4395                 case OP_IADD:
4396                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4397                         break;
4398                 case OP_IADC:
4399                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4400                         break;
4401                 case OP_IADD_IMM:
4402                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4403                         break;
4404                 case OP_IADC_IMM:
4405                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4406                         break;
4407                 case OP_ISUBCC:
4408                 case OP_ISUB:
4409                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4410                         break;
4411                 case OP_ISBB:
4412                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4413                         break;
4414                 case OP_ISUB_IMM:
4415                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4416                         break;
4417                 case OP_ISBB_IMM:
4418                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4419                         break;
4420                 case OP_IAND:
4421                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4422                         break;
4423                 case OP_IAND_IMM:
4424                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4425                         break;
4426                 case OP_IOR:
4427                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4428                         break;
4429                 case OP_IOR_IMM:
4430                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4431                         break;
4432                 case OP_IXOR:
4433                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4434                         break;
4435                 case OP_IXOR_IMM:
4436                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4437                         break;
4438                 case OP_INEG:
4439                         amd64_neg_reg_size (code, ins->sreg1, 4);
4440                         break;
4441                 case OP_INOT:
4442                         amd64_not_reg_size (code, ins->sreg1, 4);
4443                         break;
4444                 case OP_ISHL:
4445                         g_assert (ins->sreg2 == AMD64_RCX);
4446                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4447                         break;
4448                 case OP_ISHR:
4449                         g_assert (ins->sreg2 == AMD64_RCX);
4450                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4451                         break;
4452                 case OP_ISHR_IMM:
4453                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4454                         break;
4455                 case OP_ISHR_UN_IMM:
4456                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4457                         break;
4458                 case OP_ISHR_UN:
4459                         g_assert (ins->sreg2 == AMD64_RCX);
4460                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4461                         break;
4462                 case OP_ISHL_IMM:
4463                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4464                         break;
4465                 case OP_IMUL:
4466                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4467                         break;
4468                 case OP_IMUL_OVF:
4469                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4470                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4471                         break;
4472                 case OP_IMUL_OVF_UN:
4473                 case OP_LMUL_OVF_UN: {
4474                         /* the mul operation and the exception check should most likely be split */
4475                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4476                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4477                         /*g_assert (ins->sreg2 == X86_EAX);
4478                         g_assert (ins->dreg == X86_EAX);*/
4479                         if (ins->sreg2 == X86_EAX) {
4480                                 non_eax_reg = ins->sreg1;
4481                         } else if (ins->sreg1 == X86_EAX) {
4482                                 non_eax_reg = ins->sreg2;
4483                         } else {
4484                                 /* no need to save since we're going to store to it anyway */
4485                                 if (ins->dreg != X86_EAX) {
4486                                         saved_eax = TRUE;
4487                                         amd64_push_reg (code, X86_EAX);
4488                                 }
4489                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4490                                 non_eax_reg = ins->sreg2;
4491                         }
4492                         if (ins->dreg == X86_EDX) {
4493                                 if (!saved_eax) {
4494                                         saved_eax = TRUE;
4495                                         amd64_push_reg (code, X86_EAX);
4496                                 }
4497                         } else {
4498                                 saved_edx = TRUE;
4499                                 amd64_push_reg (code, X86_EDX);
4500                         }
4501                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4502                         /* save before the check since pop and mov don't change the flags */
4503                         if (ins->dreg != X86_EAX)
4504                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4505                         if (saved_edx)
4506                                 amd64_pop_reg (code, X86_EDX);
4507                         if (saved_eax)
4508                                 amd64_pop_reg (code, X86_EAX);
4509                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4510                         break;
4511                 }
4512                 case OP_ICOMPARE:
4513                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4514                         break;
4515                 case OP_ICOMPARE_IMM:
4516                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4517                         break;
4518                 case OP_IBEQ:
4519                 case OP_IBLT:
4520                 case OP_IBGT:
4521                 case OP_IBGE:
4522                 case OP_IBLE:
4523                 case OP_LBEQ:
4524                 case OP_LBLT:
4525                 case OP_LBGT:
4526                 case OP_LBGE:
4527                 case OP_LBLE:
4528                 case OP_IBNE_UN:
4529                 case OP_IBLT_UN:
4530                 case OP_IBGT_UN:
4531                 case OP_IBGE_UN:
4532                 case OP_IBLE_UN:
4533                 case OP_LBNE_UN:
4534                 case OP_LBLT_UN:
4535                 case OP_LBGT_UN:
4536                 case OP_LBGE_UN:
4537                 case OP_LBLE_UN:
4538                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4539                         break;
4540
4541                 case OP_CMOV_IEQ:
4542                 case OP_CMOV_IGE:
4543                 case OP_CMOV_IGT:
4544                 case OP_CMOV_ILE:
4545                 case OP_CMOV_ILT:
4546                 case OP_CMOV_INE_UN:
4547                 case OP_CMOV_IGE_UN:
4548                 case OP_CMOV_IGT_UN:
4549                 case OP_CMOV_ILE_UN:
4550                 case OP_CMOV_ILT_UN:
4551                 case OP_CMOV_LEQ:
4552                 case OP_CMOV_LGE:
4553                 case OP_CMOV_LGT:
4554                 case OP_CMOV_LLE:
4555                 case OP_CMOV_LLT:
4556                 case OP_CMOV_LNE_UN:
4557                 case OP_CMOV_LGE_UN:
4558                 case OP_CMOV_LGT_UN:
4559                 case OP_CMOV_LLE_UN:
4560                 case OP_CMOV_LLT_UN:
4561                         g_assert (ins->dreg == ins->sreg1);
4562                         /* This needs to operate on 64 bit values */
4563                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4564                         break;
4565
4566                 case OP_LNOT:
4567                         amd64_not_reg (code, ins->sreg1);
4568                         break;
4569                 case OP_LNEG:
4570                         amd64_neg_reg (code, ins->sreg1);
4571                         break;
4572
4573                 case OP_ICONST:
4574                 case OP_I8CONST:
4575                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4576                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4577                         else
4578                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4579                         break;
4580                 case OP_AOTCONST:
4581                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4582                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4583                         break;
4584                 case OP_JUMP_TABLE:
4585                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4586                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4587                         break;
4588                 case OP_MOVE:
4589                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4590                         break;
4591                 case OP_AMD64_SET_XMMREG_R4: {
4592                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4593                         break;
4594                 }
4595                 case OP_AMD64_SET_XMMREG_R8: {
4596                         if (ins->dreg != ins->sreg1)
4597                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4598                         break;
4599                 }
4600                 case OP_TAILCALL: {
4601                         MonoCallInst *call = (MonoCallInst*)ins;
4602                         int i, save_area_offset;
4603
4604                         g_assert (!cfg->method->save_lmf);
4605
4606                         /* Restore callee saved registers */
4607                         save_area_offset = cfg->arch.reg_save_area_offset;
4608                         for (i = 0; i < AMD64_NREG; ++i)
4609                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4610                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4611                                         save_area_offset += 8;
4612                                 }
4613
4614                         if (cfg->arch.omit_fp) {
4615                                 if (cfg->arch.stack_alloc_size)
4616                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4617                                 // FIXME:
4618                                 if (call->stack_usage)
4619                                         NOT_IMPLEMENTED;
4620                         } else {
4621                                 /* Copy arguments on the stack to our argument area */
4622                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4623                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4624                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4625                                 }
4626
4627                                 amd64_leave (code);
4628                         }
4629
4630                         offset = code - cfg->native_code;
4631                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4632                         if (cfg->compile_aot)
4633                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4634                         else
4635                                 amd64_set_reg_template (code, AMD64_R11);
4636                         amd64_jump_reg (code, AMD64_R11);
4637                         ins->flags |= MONO_INST_GC_CALLSITE;
4638                         ins->backend.pc_offset = code - cfg->native_code;
4639                         break;
4640                 }
4641                 case OP_CHECK_THIS:
4642                         /* ensure ins->sreg1 is not NULL */
4643                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4644                         break;
4645                 case OP_ARGLIST: {
4646                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4647                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4648                         break;
4649                 }
4650                 case OP_CALL:
4651                 case OP_FCALL:
4652                 case OP_LCALL:
4653                 case OP_VCALL:
4654                 case OP_VCALL2:
4655                 case OP_VOIDCALL:
4656                         call = (MonoCallInst*)ins;
4657                         /*
4658                          * The AMD64 ABI forces callers to know about varargs.
4659                          */
4660                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4661                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4662                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4663                                 /*
4664                                  * Since the unmanaged calling convention doesn't contain a
4665                                  * 'vararg' entry, we have to treat every pinvoke call as a
4666                                  * potential vararg call.
4667                                  */
4668                                 guint32 nregs, i;
4669                                 nregs = 0;
4670                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4671                                         if (call->used_fregs & (1 << i))
4672                                                 nregs ++;
4673                                 if (!nregs)
4674                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4675                                 else
4676                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4677                         }
4678
4679                         if (ins->flags & MONO_INST_HAS_METHOD)
4680                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4681                         else
4682                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4683                         ins->flags |= MONO_INST_GC_CALLSITE;
4684                         ins->backend.pc_offset = code - cfg->native_code;
4685                         code = emit_move_return_value (cfg, ins, code);
4686                         break;
4687                 case OP_FCALL_REG:
4688                 case OP_LCALL_REG:
4689                 case OP_VCALL_REG:
4690                 case OP_VCALL2_REG:
4691                 case OP_VOIDCALL_REG:
4692                 case OP_CALL_REG:
4693                         call = (MonoCallInst*)ins;
4694
4695                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4696                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4697                                 ins->sreg1 = AMD64_R11;
4698                         }
4699
4700                         /*
4701                          * The AMD64 ABI forces callers to know about varargs.
4702                          */
4703                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4704                                 if (ins->sreg1 == AMD64_RAX) {
4705                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4706                                         ins->sreg1 = AMD64_R11;
4707                                 }
4708                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4709                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4710                                 /*
4711                                  * Since the unmanaged calling convention doesn't contain a
4712                                  * 'vararg' entry, we have to treat every pinvoke call as a
4713                                  * potential vararg call.
4714                                  */
4715                                 guint32 nregs, i;
4716                                 nregs = 0;
4717                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4718                                         if (call->used_fregs & (1 << i))
4719                                                 nregs ++;
4720                                 if (ins->sreg1 == AMD64_RAX) {
4721                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4722                                         ins->sreg1 = AMD64_R11;
4723                                 }
4724                                 if (!nregs)
4725                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4726                                 else
4727                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4728                         }
4729
4730                         amd64_call_reg (code, ins->sreg1);
4731                         ins->flags |= MONO_INST_GC_CALLSITE;
4732                         ins->backend.pc_offset = code - cfg->native_code;
4733                         code = emit_move_return_value (cfg, ins, code);
4734                         break;
4735                 case OP_FCALL_MEMBASE:
4736                 case OP_LCALL_MEMBASE:
4737                 case OP_VCALL_MEMBASE:
4738                 case OP_VCALL2_MEMBASE:
4739                 case OP_VOIDCALL_MEMBASE:
4740                 case OP_CALL_MEMBASE:
4741                         call = (MonoCallInst*)ins;
4742
4743                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4744                         ins->flags |= MONO_INST_GC_CALLSITE;
4745                         ins->backend.pc_offset = code - cfg->native_code;
4746                         code = emit_move_return_value (cfg, ins, code);
4747                         break;
4748                 case OP_DYN_CALL: {
4749                         int i;
4750                         MonoInst *var = cfg->dyn_call_var;
4751
4752                         g_assert (var->opcode == OP_REGOFFSET);
4753
4754                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4755                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4756                         /* r10 = ftn */
4757                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4758
4759                         /* Save args buffer */
4760                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4761
4762                         /* Set argument registers */
4763                         for (i = 0; i < PARAM_REGS; ++i)
4764                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4765
4766                         /* Make the call */
4767                         amd64_call_reg (code, AMD64_R10);
4768
4769                         ins->flags |= MONO_INST_GC_CALLSITE;
4770                         ins->backend.pc_offset = code - cfg->native_code;
4771
4772                         /* Save result */
4773                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4774                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4775                         break;
4776                 }
4777                 case OP_AMD64_SAVE_SP_TO_LMF: {
4778                         MonoInst *lmf_var = cfg->lmf_var;
4779                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4780                         break;
4781                 }
4782                 case OP_X86_PUSH:
4783                         g_assert_not_reached ();
4784                         amd64_push_reg (code, ins->sreg1);
4785                         break;
4786                 case OP_X86_PUSH_IMM:
4787                         g_assert_not_reached ();
4788                         g_assert (amd64_is_imm32 (ins->inst_imm));
4789                         amd64_push_imm (code, ins->inst_imm);
4790                         break;
4791                 case OP_X86_PUSH_MEMBASE:
4792                         g_assert_not_reached ();
4793                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4794                         break;
4795                 case OP_X86_PUSH_OBJ: {
4796                         int size = ALIGN_TO (ins->inst_imm, 8);
4797
4798                         g_assert_not_reached ();
4799
4800                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4801                         amd64_push_reg (code, AMD64_RDI);
4802                         amd64_push_reg (code, AMD64_RSI);
4803                         amd64_push_reg (code, AMD64_RCX);
4804                         if (ins->inst_offset)
4805                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4806                         else
4807                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4808                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4809                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4810                         amd64_cld (code);
4811                         amd64_prefix (code, X86_REP_PREFIX);
4812                         amd64_movsd (code);
4813                         amd64_pop_reg (code, AMD64_RCX);
4814                         amd64_pop_reg (code, AMD64_RSI);
4815                         amd64_pop_reg (code, AMD64_RDI);
4816                         break;
4817                 }
4818                 case OP_X86_LEA:
4819                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4820                         break;
4821                 case OP_X86_LEA_MEMBASE:
4822                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4823                         break;
4824                 case OP_X86_XCHG:
4825                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4826                         break;
4827                 case OP_LOCALLOC:
4828                         /* keep alignment */
4829                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4830                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4831                         code = mono_emit_stack_alloc (cfg, code, ins);
4832                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4833                         if (cfg->param_area)
4834                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4835                         break;
4836                 case OP_LOCALLOC_IMM: {
4837                         guint32 size = ins->inst_imm;
4838                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4839
4840                         if (ins->flags & MONO_INST_INIT) {
4841                                 if (size < 64) {
4842                                         int i;
4843
4844                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4845                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4846
4847                                         for (i = 0; i < size; i += 8)
4848                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4849                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4850                                 } else {
4851                                         amd64_mov_reg_imm (code, ins->dreg, size);
4852                                         ins->sreg1 = ins->dreg;
4853
4854                                         code = mono_emit_stack_alloc (cfg, code, ins);
4855                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4856                                 }
4857                         } else {
4858                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4859                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4860                         }
4861                         if (cfg->param_area)
4862                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4863                         break;
4864                 }
4865                 case OP_THROW: {
4866                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4867                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4868                                              (gpointer)"mono_arch_throw_exception", FALSE);
4869                         ins->flags |= MONO_INST_GC_CALLSITE;
4870                         ins->backend.pc_offset = code - cfg->native_code;
4871                         break;
4872                 }
4873                 case OP_RETHROW: {
4874                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4875                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4876                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4877                         ins->flags |= MONO_INST_GC_CALLSITE;
4878                         ins->backend.pc_offset = code - cfg->native_code;
4879                         break;
4880                 }
4881                 case OP_CALL_HANDLER:
4882                         /* Align stack */
4883                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4884                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4885                         amd64_call_imm (code, 0);
4886                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4887                         /* Restore stack alignment */
4888                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4889                         break;
4890                 case OP_START_HANDLER: {
4891                         /* Even though we're saving RSP, use sizeof */
4892                         /* gpointer because spvar is of type IntPtr */
4893                         /* see: mono_create_spvar_for_region */
4894                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4895                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4896
4897                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4898                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4899                                 cfg->param_area) {
4900                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4901                         }
4902                         break;
4903                 }
4904                 case OP_ENDFINALLY: {
4905                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4906                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4907                         amd64_ret (code);
4908                         break;
4909                 }
4910                 case OP_ENDFILTER: {
4911                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4912                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4913                         /* The local allocator will put the result into RAX */
4914                         amd64_ret (code);
4915                         break;
4916                 }
4917
4918                 case OP_LABEL:
4919                         ins->inst_c0 = code - cfg->native_code;
4920                         break;
4921                 case OP_BR:
4922                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4923                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4924                         //break;
4925                                 if (ins->inst_target_bb->native_offset) {
4926                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4927                                 } else {
4928                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4929                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4930                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4931                                                 x86_jump8 (code, 0);
4932                                         else
4933                                                 x86_jump32 (code, 0);
4934                         }
4935                         break;
4936                 case OP_BR_REG:
4937                         amd64_jump_reg (code, ins->sreg1);
4938                         break;
4939                 case OP_ICNEQ:
4940                 case OP_ICGE:
4941                 case OP_ICLE:
4942                 case OP_ICGE_UN:
4943                 case OP_ICLE_UN:
4944
4945                 case OP_CEQ:
4946                 case OP_LCEQ:
4947                 case OP_ICEQ:
4948                 case OP_CLT:
4949                 case OP_LCLT:
4950                 case OP_ICLT:
4951                 case OP_CGT:
4952                 case OP_ICGT:
4953                 case OP_LCGT:
4954                 case OP_CLT_UN:
4955                 case OP_LCLT_UN:
4956                 case OP_ICLT_UN:
4957                 case OP_CGT_UN:
4958                 case OP_LCGT_UN:
4959                 case OP_ICGT_UN:
4960                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4961                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4962                         break;
4963                 case OP_COND_EXC_EQ:
4964                 case OP_COND_EXC_NE_UN:
4965                 case OP_COND_EXC_LT:
4966                 case OP_COND_EXC_LT_UN:
4967                 case OP_COND_EXC_GT:
4968                 case OP_COND_EXC_GT_UN:
4969                 case OP_COND_EXC_GE:
4970                 case OP_COND_EXC_GE_UN:
4971                 case OP_COND_EXC_LE:
4972                 case OP_COND_EXC_LE_UN:
4973                 case OP_COND_EXC_IEQ:
4974                 case OP_COND_EXC_INE_UN:
4975                 case OP_COND_EXC_ILT:
4976                 case OP_COND_EXC_ILT_UN:
4977                 case OP_COND_EXC_IGT:
4978                 case OP_COND_EXC_IGT_UN:
4979                 case OP_COND_EXC_IGE:
4980                 case OP_COND_EXC_IGE_UN:
4981                 case OP_COND_EXC_ILE:
4982                 case OP_COND_EXC_ILE_UN:
4983                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4984                         break;
4985                 case OP_COND_EXC_OV:
4986                 case OP_COND_EXC_NO:
4987                 case OP_COND_EXC_C:
4988                 case OP_COND_EXC_NC:
4989                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4990                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4991                         break;
4992                 case OP_COND_EXC_IOV:
4993                 case OP_COND_EXC_INO:
4994                 case OP_COND_EXC_IC:
4995                 case OP_COND_EXC_INC:
4996                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4997                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4998                         break;
4999
5000                 /* floating point opcodes */
5001                 case OP_R8CONST: {
5002                         double d = *(double *)ins->inst_p0;
5003
5004                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5005                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5006                         }
5007                         else {
5008                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5009                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5010                         }
5011                         break;
5012                 }
5013                 case OP_R4CONST: {
5014                         float f = *(float *)ins->inst_p0;
5015
5016                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5017                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5018                         }
5019                         else {
5020                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5021                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5022                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5023                         }
5024                         break;
5025                 }
5026                 case OP_STORER8_MEMBASE_REG:
5027                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5028                         break;
5029                 case OP_LOADR8_MEMBASE:
5030                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5031                         break;
5032                 case OP_STORER4_MEMBASE_REG:
5033                         /* This requires a double->single conversion */
5034                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5035                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5036                         break;
5037                 case OP_LOADR4_MEMBASE:
5038                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5039                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5040                         break;
5041                 case OP_ICONV_TO_R4:
5042                         amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5043                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5044                         break;
5045                 case OP_ICONV_TO_R8:
5046                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5047                         break;
5048                 case OP_LCONV_TO_R4:
5049                         amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5050                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5051                         break;
5052                 case OP_LCONV_TO_R8:
5053                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5054                         break;
5055                 case OP_FCONV_TO_R4:
5056                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5057                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5058                         break;
5059                 case OP_FCONV_TO_I1:
5060                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5061                         break;
5062                 case OP_FCONV_TO_U1:
5063                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5064                         break;
5065                 case OP_FCONV_TO_I2:
5066                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5067                         break;
5068                 case OP_FCONV_TO_U2:
5069                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5070                         break;
5071                 case OP_FCONV_TO_U4:
5072                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5073                         break;
5074                 case OP_FCONV_TO_I4:
5075                 case OP_FCONV_TO_I:
5076                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5077                         break;
5078                 case OP_FCONV_TO_I8:
5079                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5080                         break;
5081                 case OP_LCONV_TO_R_UN: {
5082                         guint8 *br [2];
5083
5084                         /* Based on gcc code */
5085                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5086                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5087
5088                         /* Positive case */
5089                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5090                         br [1] = code; x86_jump8 (code, 0);
5091                         amd64_patch (br [0], code);
5092
5093                         /* Negative case */
5094                         /* Save to the red zone */
5095                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5096                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5097                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5098                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5099                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5100                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5101                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5102                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5103                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5104                         /* Restore */
5105                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5106                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5107                         amd64_patch (br [1], code);
5108                         break;
5109                 }
5110                 case OP_LCONV_TO_OVF_U4:
5111                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5112                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5113                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5114                         break;
5115                 case OP_LCONV_TO_OVF_I4_UN:
5116                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5117                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5118                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5119                         break;
5120                 case OP_FMOVE:
5121                         if (ins->dreg != ins->sreg1)
5122                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5123                         break;
5124                 case OP_FADD:
5125                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5126                         break;
5127                 case OP_FSUB:
5128                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5129                         break;
5130                 case OP_FMUL:
5131                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5132                         break;
5133                 case OP_FDIV:
5134                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5135                         break;
5136                 case OP_FNEG: {
5137                         static double r8_0 = -0.0;
5138
5139                         g_assert (ins->sreg1 == ins->dreg);
5140
5141                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5142                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5143                         break;
5144                 }
5145                 case OP_SIN:
5146                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5147                         break;
5148                 case OP_COS:
5149                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5150                         break;
5151                 case OP_ABS: {
5152                         static guint64 d = 0x7fffffffffffffffUL;
5153
5154                         g_assert (ins->sreg1 == ins->dreg);
5155
5156                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5157                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5158                         break;
5159                 }
5160                 case OP_SQRT:
5161                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5162                         break;
5163                 case OP_IMIN:
5164                         g_assert (cfg->opt & MONO_OPT_CMOV);
5165                         g_assert (ins->dreg == ins->sreg1);
5166                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5167                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5168                         break;
5169                 case OP_IMIN_UN:
5170                         g_assert (cfg->opt & MONO_OPT_CMOV);
5171                         g_assert (ins->dreg == ins->sreg1);
5172                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5173                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5174                         break;
5175                 case OP_IMAX:
5176                         g_assert (cfg->opt & MONO_OPT_CMOV);
5177                         g_assert (ins->dreg == ins->sreg1);
5178                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5179                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5180                         break;
5181                 case OP_IMAX_UN:
5182                         g_assert (cfg->opt & MONO_OPT_CMOV);
5183                         g_assert (ins->dreg == ins->sreg1);
5184                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5185                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5186                         break;
5187                 case OP_LMIN:
5188                         g_assert (cfg->opt & MONO_OPT_CMOV);
5189                         g_assert (ins->dreg == ins->sreg1);
5190                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5191                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5192                         break;
5193                 case OP_LMIN_UN:
5194                         g_assert (cfg->opt & MONO_OPT_CMOV);
5195                         g_assert (ins->dreg == ins->sreg1);
5196                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5197                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5198                         break;
5199                 case OP_LMAX:
5200                         g_assert (cfg->opt & MONO_OPT_CMOV);
5201                         g_assert (ins->dreg == ins->sreg1);
5202                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5203                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5204                         break;
5205                 case OP_LMAX_UN:
5206                         g_assert (cfg->opt & MONO_OPT_CMOV);
5207                         g_assert (ins->dreg == ins->sreg1);
5208                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5209                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5210                         break;
5211                 case OP_X86_FPOP:
5212                         break;
5213                 case OP_FCOMPARE:
5214                         /*
5215                          * The two arguments are swapped because the fbranch instructions
5216                          * depend on this for the non-sse case to work.
5217                          */
5218                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5219                         break;
5220                 case OP_FCNEQ:
5221                 case OP_FCEQ: {
5222                         /* zeroing the register at the start results in
5223                          * shorter and faster code (we can also remove the widening op)
5224                          */
5225                         guchar *unordered_check;
5226                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5227                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5228                         unordered_check = code;
5229                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5230
5231                         if (ins->opcode == OP_FCEQ) {
5232                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5233                                 amd64_patch (unordered_check, code);
5234                         } else {
5235                                 guchar *jump_to_end;
5236                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5237                                 jump_to_end = code;
5238                                 x86_jump8 (code, 0);
5239                                 amd64_patch (unordered_check, code);
5240                                 amd64_inc_reg (code, ins->dreg);
5241                                 amd64_patch (jump_to_end, code);
5242                         }
5243                         break;
5244                 }
5245                 case OP_FCLT:
5246                 case OP_FCLT_UN:
5247                         /* zeroing the register at the start results in
5248                          * shorter and faster code (we can also remove the widening op)
5249                          */
5250                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5251                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5252                         if (ins->opcode == OP_FCLT_UN) {
5253                                 guchar *unordered_check = code;
5254                                 guchar *jump_to_end;
5255                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5256                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5257                                 jump_to_end = code;
5258                                 x86_jump8 (code, 0);
5259                                 amd64_patch (unordered_check, code);
5260                                 amd64_inc_reg (code, ins->dreg);
5261                                 amd64_patch (jump_to_end, code);
5262                         } else {
5263                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5264                         }
5265                         break;
5266                 case OP_FCLE: {
5267                         guchar *unordered_check;
5268                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5269                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5270                         unordered_check = code;
5271                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5272                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5273                         amd64_patch (unordered_check, code);
5274                         break;
5275                 }
5276                 case OP_FCGT:
5277                 case OP_FCGT_UN: {
5278                         /* zeroing the register at the start results in
5279                          * shorter and faster code (we can also remove the widening op)
5280                          */
5281                         guchar *unordered_check;
5282                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5283                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5284                         if (ins->opcode == OP_FCGT) {
5285                                 unordered_check = code;
5286                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5287                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5288                                 amd64_patch (unordered_check, code);
5289                         } else {
5290                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5291                         }
5292                         break;
5293                 }
5294                 case OP_FCGE: {
5295                         guchar *unordered_check;
5296                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5297                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5298                         unordered_check = code;
5299                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5300                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5301                         amd64_patch (unordered_check, code);
5302                         break;
5303                 }
5304
5305                 case OP_FCLT_MEMBASE:
5306                 case OP_FCGT_MEMBASE:
5307                 case OP_FCLT_UN_MEMBASE:
5308                 case OP_FCGT_UN_MEMBASE:
5309                 case OP_FCEQ_MEMBASE: {
5310                         guchar *unordered_check, *jump_to_end;
5311                         int x86_cond;
5312
5313                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5314                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5315
5316                         switch (ins->opcode) {
5317                         case OP_FCEQ_MEMBASE:
5318                                 x86_cond = X86_CC_EQ;
5319                                 break;
5320                         case OP_FCLT_MEMBASE:
5321                         case OP_FCLT_UN_MEMBASE:
5322                                 x86_cond = X86_CC_LT;
5323                                 break;
5324                         case OP_FCGT_MEMBASE:
5325                         case OP_FCGT_UN_MEMBASE:
5326                                 x86_cond = X86_CC_GT;
5327                                 break;
5328                         default:
5329                                 g_assert_not_reached ();
5330                         }
5331
5332                         unordered_check = code;
5333                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5334                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5335
5336                         switch (ins->opcode) {
5337                         case OP_FCEQ_MEMBASE:
5338                         case OP_FCLT_MEMBASE:
5339                         case OP_FCGT_MEMBASE:
5340                                 amd64_patch (unordered_check, code);
5341                                 break;
5342                         case OP_FCLT_UN_MEMBASE:
5343                         case OP_FCGT_UN_MEMBASE:
5344                                 jump_to_end = code;
5345                                 x86_jump8 (code, 0);
5346                                 amd64_patch (unordered_check, code);
5347                                 amd64_inc_reg (code, ins->dreg);
5348                                 amd64_patch (jump_to_end, code);
5349                                 break;
5350                         default:
5351                                 break;
5352                         }
5353                         break;
5354                 }
5355                 case OP_FBEQ: {
5356                         guchar *jump = code;
5357                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5358                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5359                         amd64_patch (jump, code);
5360                         break;
5361                 }
5362                 case OP_FBNE_UN:
5363                         /* Branch if C013 != 100 */
5364                         /* branch if !ZF or (PF|CF) */
5365                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5366                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5367                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5368                         break;
5369                 case OP_FBLT:
5370                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5371                         break;
5372                 case OP_FBLT_UN:
5373                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5374                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5375                         break;
5376                 case OP_FBGT:
5377                 case OP_FBGT_UN:
5378                         if (ins->opcode == OP_FBGT) {
5379                                 guchar *br1;
5380
5381                                 /* skip branch if C1=1 */
5382                                 br1 = code;
5383                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5384                                 /* branch if (C0 | C3) = 1 */
5385                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5386                                 amd64_patch (br1, code);
5387                                 break;
5388                         } else {
5389                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5390                         }
5391                         break;
5392                 case OP_FBGE: {
5393                         /* Branch if C013 == 100 or 001 */
5394                         guchar *br1;
5395
5396                         /* skip branch if C1=1 */
5397                         br1 = code;
5398                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5399                         /* branch if (C0 | C3) = 1 */
5400                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5401                         amd64_patch (br1, code);
5402                         break;
5403                 }
5404                 case OP_FBGE_UN:
5405                         /* Branch if C013 == 000 */
5406                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5407                         break;
5408                 case OP_FBLE: {
5409                         /* Branch if C013=000 or 100 */
5410                         guchar *br1;
5411
5412                         /* skip branch if C1=1 */
5413                         br1 = code;
5414                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5415                         /* branch if C0=0 */
5416                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5417                         amd64_patch (br1, code);
5418                         break;
5419                 }
5420                 case OP_FBLE_UN:
5421                         /* Branch if C013 != 001 */
5422                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5423                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5424                         break;
5425                 case OP_CKFINITE:
5426                         /* Transfer value to the fp stack */
5427                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5428                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5429                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5430
5431                         amd64_push_reg (code, AMD64_RAX);
5432                         amd64_fxam (code);
5433                         amd64_fnstsw (code);
5434                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5435                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5436                         amd64_pop_reg (code, AMD64_RAX);
5437                         amd64_fstp (code, 0);
5438                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5439                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5440                         break;
5441                 case OP_TLS_GET: {
5442                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5443                         break;
5444                 }
5445                 case OP_TLS_GET_REG:
5446                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5447                         break;
5448                 case OP_TLS_SET: {
5449                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5450                         break;
5451                 }
5452                 case OP_TLS_SET_REG: {
5453                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5454                         break;
5455                 }
5456                 case OP_MEMORY_BARRIER: {
5457                         switch (ins->backend.memory_barrier_kind) {
5458                         case StoreLoadBarrier:
5459                         case FullBarrier:
5460                                 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5461                                 x86_prefix (code, X86_LOCK_PREFIX);
5462                                 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5463                                 break;
5464                         }
5465                         break;
5466                 }
5467                 case OP_ATOMIC_ADD_I4:
5468                 case OP_ATOMIC_ADD_I8: {
5469                         int dreg = ins->dreg;
5470                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5471
5472                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5473                                 dreg = AMD64_R11;
5474
5475                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5476                         amd64_prefix (code, X86_LOCK_PREFIX);
5477                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5478                         /* dreg contains the old value, add with sreg2 value */
5479                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5480
5481                         if (ins->dreg != dreg)
5482                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5483
5484                         break;
5485                 }
5486                 case OP_ATOMIC_EXCHANGE_I4:
5487                 case OP_ATOMIC_EXCHANGE_I8: {
5488                         guchar *br[2];
5489                         int sreg2 = ins->sreg2;
5490                         int breg = ins->inst_basereg;
5491                         guint32 size;
5492                         gboolean need_push = FALSE, rdx_pushed = FALSE;
5493
5494                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5495                                 size = 8;
5496                         else
5497                                 size = 4;
5498
5499                         /*
5500                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5501                          * an explanation of how this works.
5502                          */
5503
5504                         /* cmpxchg uses eax as comperand, need to make sure we can use it
5505                          * hack to overcome limits in x86 reg allocator
5506                          * (req: dreg == eax and sreg2 != eax and breg != eax)
5507                          */
5508                         g_assert (ins->dreg == AMD64_RAX);
5509
5510                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5511                                 /* Highly unlikely, but possible */
5512                                 need_push = TRUE;
5513
5514                         /* The pushes invalidate rsp */
5515                         if ((breg == AMD64_RAX) || need_push) {
5516                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5517                                 breg = AMD64_R11;
5518                         }
5519
5520                         /* We need the EAX reg for the comparand */
5521                         if (ins->sreg2 == AMD64_RAX) {
5522                                 if (breg != AMD64_R11) {
5523                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5524                                         sreg2 = AMD64_R11;
5525                                 } else {
5526                                         g_assert (need_push);
5527                                         amd64_push_reg (code, AMD64_RDX);
5528                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5529                                         sreg2 = AMD64_RDX;
5530                                         rdx_pushed = TRUE;
5531                                 }
5532                         }
5533
5534                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5535
5536                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5537                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5538                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5539                         amd64_patch (br [1], br [0]);
5540
5541                         if (rdx_pushed)
5542                                 amd64_pop_reg (code, AMD64_RDX);
5543
5544                         break;
5545                 }
5546                 case OP_ATOMIC_CAS_I4:
5547                 case OP_ATOMIC_CAS_I8: {
5548                         guint32 size;
5549
5550                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5551                                 size = 8;
5552                         else
5553                                 size = 4;
5554
5555                         /*
5556                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5557                          * an explanation of how this works.
5558                          */
5559                         g_assert (ins->sreg3 == AMD64_RAX);
5560                         g_assert (ins->sreg1 != AMD64_RAX);
5561                         g_assert (ins->sreg1 != ins->sreg2);
5562
5563                         amd64_prefix (code, X86_LOCK_PREFIX);
5564                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5565
5566                         if (ins->dreg != AMD64_RAX)
5567                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5568                         break;
5569                 }
5570                 case OP_CARD_TABLE_WBARRIER: {
5571                         int ptr = ins->sreg1;
5572                         int value = ins->sreg2;
5573                         guchar *br = 0;
5574                         int nursery_shift, card_table_shift;
5575                         gpointer card_table_mask;
5576                         size_t nursery_size;
5577
5578                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5579                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5580                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5581
5582                         /*If either point to the stack we can simply avoid the WB. This happens due to
5583                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5584                          */
5585                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5586                                 continue;
5587
5588                         /*
5589                          * We need one register we can clobber, we choose EDX and make sreg1
5590                          * fixed EAX to work around limitations in the local register allocator.
5591                          * sreg2 might get allocated to EDX, but that is not a problem since
5592                          * we use it before clobbering EDX.
5593                          */
5594                         g_assert (ins->sreg1 == AMD64_RAX);
5595
5596                         /*
5597                          * This is the code we produce:
5598                          *
5599                          *   edx = value
5600                          *   edx >>= nursery_shift
5601                          *   cmp edx, (nursery_start >> nursery_shift)
5602                          *   jne done
5603                          *   edx = ptr
5604                          *   edx >>= card_table_shift
5605                          *   edx += cardtable
5606                          *   [edx] = 1
5607                          * done:
5608                          */
5609
5610                         if (mono_gc_card_table_nursery_check ()) {
5611                                 if (value != AMD64_RDX)
5612                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5613                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5614                                 if (shifted_nursery_start >> 31) {
5615                                         /*
5616                                          * The value we need to compare against is 64 bits, so we need
5617                                          * another spare register.  We use RBX, which we save and
5618                                          * restore.
5619                                          */
5620                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5621                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5622                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5623                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5624                                 } else {
5625                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5626                                 }
5627                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5628                         }
5629                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5630                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5631                         if (card_table_mask)
5632                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5633
5634                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5635                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5636
5637                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5638
5639                         if (mono_gc_card_table_nursery_check ())
5640                                 x86_patch (br, code);
5641                         break;
5642                 }
5643 #ifdef MONO_ARCH_SIMD_INTRINSICS
5644                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5645                 case OP_ADDPS:
5646                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5647                         break;
5648                 case OP_DIVPS:
5649                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5650                         break;
5651                 case OP_MULPS:
5652                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5653                         break;
5654                 case OP_SUBPS:
5655                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5656                         break;
5657                 case OP_MAXPS:
5658                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5659                         break;
5660                 case OP_MINPS:
5661                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5662                         break;
5663                 case OP_COMPPS:
5664                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5665                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5666                         break;
5667                 case OP_ANDPS:
5668                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5669                         break;
5670                 case OP_ANDNPS:
5671                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5672                         break;
5673                 case OP_ORPS:
5674                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5675                         break;
5676                 case OP_XORPS:
5677                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5678                         break;
5679                 case OP_SQRTPS:
5680                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5681                         break;
5682                 case OP_RSQRTPS:
5683                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5684                         break;
5685                 case OP_RCPPS:
5686                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5687                         break;
5688                 case OP_ADDSUBPS:
5689                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5690                         break;
5691                 case OP_HADDPS:
5692                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5693                         break;
5694                 case OP_HSUBPS:
5695                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5696                         break;
5697                 case OP_DUPPS_HIGH:
5698                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5699                         break;
5700                 case OP_DUPPS_LOW:
5701                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5702                         break;
5703
5704                 case OP_PSHUFLEW_HIGH:
5705                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5706                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5707                         break;
5708                 case OP_PSHUFLEW_LOW:
5709                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5710                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5711                         break;
5712                 case OP_PSHUFLED:
5713                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5714                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5715                         break;
5716                 case OP_SHUFPS:
5717                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5718                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5719                         break;
5720                 case OP_SHUFPD:
5721                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5722                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5723                         break;
5724
5725                 case OP_ADDPD:
5726                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5727                         break;
5728                 case OP_DIVPD:
5729                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5730                         break;
5731                 case OP_MULPD:
5732                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5733                         break;
5734                 case OP_SUBPD:
5735                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5736                         break;
5737                 case OP_MAXPD:
5738                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5739                         break;
5740                 case OP_MINPD:
5741                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5742                         break;
5743                 case OP_COMPPD:
5744                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5745                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5746                         break;
5747                 case OP_ANDPD:
5748                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5749                         break;
5750                 case OP_ANDNPD:
5751                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5752                         break;
5753                 case OP_ORPD:
5754                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5755                         break;
5756                 case OP_XORPD:
5757                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5758                         break;
5759                 case OP_SQRTPD:
5760                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5761                         break;
5762                 case OP_ADDSUBPD:
5763                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5764                         break;
5765                 case OP_HADDPD:
5766                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5767                         break;
5768                 case OP_HSUBPD:
5769                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5770                         break;
5771                 case OP_DUPPD:
5772                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5773                         break;
5774
5775                 case OP_EXTRACT_MASK:
5776                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5777                         break;
5778
5779                 case OP_PAND:
5780                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5781                         break;
5782                 case OP_POR:
5783                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5784                         break;
5785                 case OP_PXOR:
5786                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5787                         break;
5788
5789                 case OP_PADDB:
5790                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5791                         break;
5792                 case OP_PADDW:
5793                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5794                         break;
5795                 case OP_PADDD:
5796                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5797                         break;
5798                 case OP_PADDQ:
5799                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5800                         break;
5801
5802                 case OP_PSUBB:
5803                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5804                         break;
5805                 case OP_PSUBW:
5806                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5807                         break;
5808                 case OP_PSUBD:
5809                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5810                         break;
5811                 case OP_PSUBQ:
5812                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5813                         break;
5814
5815                 case OP_PMAXB_UN:
5816                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5817                         break;
5818                 case OP_PMAXW_UN:
5819                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5820                         break;
5821                 case OP_PMAXD_UN:
5822                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5823                         break;
5824
5825                 case OP_PMAXB:
5826                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5827                         break;
5828                 case OP_PMAXW:
5829                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5830                         break;
5831                 case OP_PMAXD:
5832                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5833                         break;
5834
5835                 case OP_PAVGB_UN:
5836                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5837                         break;
5838                 case OP_PAVGW_UN:
5839                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5840                         break;
5841
5842                 case OP_PMINB_UN:
5843                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5844                         break;
5845                 case OP_PMINW_UN:
5846                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5847                         break;
5848                 case OP_PMIND_UN:
5849                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5850                         break;
5851
5852                 case OP_PMINB:
5853                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5854                         break;
5855                 case OP_PMINW:
5856                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5857                         break;
5858                 case OP_PMIND:
5859                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5860                         break;
5861
5862                 case OP_PCMPEQB:
5863                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5864                         break;
5865                 case OP_PCMPEQW:
5866                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5867                         break;
5868                 case OP_PCMPEQD:
5869                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5870                         break;
5871                 case OP_PCMPEQQ:
5872                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5873                         break;
5874
5875                 case OP_PCMPGTB:
5876                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5877                         break;
5878                 case OP_PCMPGTW:
5879                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5880                         break;
5881                 case OP_PCMPGTD:
5882                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5883                         break;
5884                 case OP_PCMPGTQ:
5885                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5886                         break;
5887
5888                 case OP_PSUM_ABS_DIFF:
5889                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5890                         break;
5891
5892                 case OP_UNPACK_LOWB:
5893                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5894                         break;
5895                 case OP_UNPACK_LOWW:
5896                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5897                         break;
5898                 case OP_UNPACK_LOWD:
5899                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5900                         break;
5901                 case OP_UNPACK_LOWQ:
5902                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5903                         break;
5904                 case OP_UNPACK_LOWPS:
5905                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5906                         break;
5907                 case OP_UNPACK_LOWPD:
5908                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5909                         break;
5910
5911                 case OP_UNPACK_HIGHB:
5912                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5913                         break;
5914                 case OP_UNPACK_HIGHW:
5915                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5916                         break;
5917                 case OP_UNPACK_HIGHD:
5918                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5919                         break;
5920                 case OP_UNPACK_HIGHQ:
5921                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5922                         break;
5923                 case OP_UNPACK_HIGHPS:
5924                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5925                         break;
5926                 case OP_UNPACK_HIGHPD:
5927                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5928                         break;
5929
5930                 case OP_PACKW:
5931                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5932                         break;
5933                 case OP_PACKD:
5934                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5935                         break;
5936                 case OP_PACKW_UN:
5937                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5938                         break;
5939                 case OP_PACKD_UN:
5940                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5941                         break;
5942
5943                 case OP_PADDB_SAT_UN:
5944                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5945                         break;
5946                 case OP_PSUBB_SAT_UN:
5947                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5948                         break;
5949                 case OP_PADDW_SAT_UN:
5950                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5951                         break;
5952                 case OP_PSUBW_SAT_UN:
5953                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5954                         break;
5955
5956                 case OP_PADDB_SAT:
5957                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5958                         break;
5959                 case OP_PSUBB_SAT:
5960                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5961                         break;
5962                 case OP_PADDW_SAT:
5963                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5964                         break;
5965                 case OP_PSUBW_SAT:
5966                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5967                         break;
5968
5969                 case OP_PMULW:
5970                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5971                         break;
5972                 case OP_PMULD:
5973                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_PMULQ:
5976                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978                 case OP_PMULW_HIGH_UN:
5979                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5980                         break;
5981                 case OP_PMULW_HIGH:
5982                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5983                         break;
5984
5985                 case OP_PSHRW:
5986                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5987                         break;
5988                 case OP_PSHRW_REG:
5989                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5990                         break;
5991
5992                 case OP_PSARW:
5993                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5994                         break;
5995                 case OP_PSARW_REG:
5996                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5997                         break;
5998
5999                 case OP_PSHLW:
6000                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6001                         break;
6002                 case OP_PSHLW_REG:
6003                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6004                         break;
6005
6006                 case OP_PSHRD:
6007                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6008                         break;
6009                 case OP_PSHRD_REG:
6010                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6011                         break;
6012
6013                 case OP_PSARD:
6014                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6015                         break;
6016                 case OP_PSARD_REG:
6017                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6018                         break;
6019
6020                 case OP_PSHLD:
6021                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6022                         break;
6023                 case OP_PSHLD_REG:
6024                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6025                         break;
6026
6027                 case OP_PSHRQ:
6028                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6029                         break;
6030                 case OP_PSHRQ_REG:
6031                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6032                         break;
6033
6034                 /*TODO: This is appart of the sse spec but not added
6035                 case OP_PSARQ:
6036                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6037                         break;
6038                 case OP_PSARQ_REG:
6039                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6040                         break;
6041                 */
6042
6043                 case OP_PSHLQ:
6044                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6045                         break;
6046                 case OP_PSHLQ_REG:
6047                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6048                         break;
6049                 case OP_CVTDQ2PD:
6050                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6051                         break;
6052                 case OP_CVTDQ2PS:
6053                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6054                         break;
6055                 case OP_CVTPD2DQ:
6056                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6057                         break;
6058                 case OP_CVTPD2PS:
6059                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6060                         break;
6061                 case OP_CVTPS2DQ:
6062                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6063                         break;
6064                 case OP_CVTPS2PD:
6065                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6066                         break;
6067                 case OP_CVTTPD2DQ:
6068                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6069                         break;
6070                 case OP_CVTTPS2DQ:
6071                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6072                         break;
6073
6074                 case OP_ICONV_TO_X:
6075                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6076                         break;
6077                 case OP_EXTRACT_I4:
6078                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6079                         break;
6080                 case OP_EXTRACT_I8:
6081                         if (ins->inst_c0) {
6082                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6083                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6084                         } else {
6085                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6086                         }
6087                         break;
6088                 case OP_EXTRACT_I1:
6089                 case OP_EXTRACT_U1:
6090                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6091                         if (ins->inst_c0)
6092                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6093                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6094                         break;
6095                 case OP_EXTRACT_I2:
6096                 case OP_EXTRACT_U2:
6097                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6098                         if (ins->inst_c0)
6099                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6100                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6101                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6102                         break;
6103                 case OP_EXTRACT_R8:
6104                         if (ins->inst_c0)
6105                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6106                         else
6107                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6108                         break;
6109                 case OP_INSERT_I2:
6110                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6111                         break;
6112                 case OP_EXTRACTX_U2:
6113                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6114                         break;
6115                 case OP_INSERTX_U1_SLOW:
6116                         /*sreg1 is the extracted ireg (scratch)
6117                         /sreg2 is the to be inserted ireg (scratch)
6118                         /dreg is the xreg to receive the value*/
6119
6120                         /*clear the bits from the extracted word*/
6121                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6122                         /*shift the value to insert if needed*/
6123                         if (ins->inst_c0 & 1)
6124                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6125                         /*join them together*/
6126                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6127                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6128                         break;
6129                 case OP_INSERTX_I4_SLOW:
6130                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6131                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6132                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6133                         break;
6134                 case OP_INSERTX_I8_SLOW:
6135                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6136                         if (ins->inst_c0)
6137                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6138                         else
6139                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6140                         break;
6141
6142                 case OP_INSERTX_R4_SLOW:
6143                         switch (ins->inst_c0) {
6144                         case 0:
6145                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6146                                 break;
6147                         case 1:
6148                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6149                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6150                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6151                                 break;
6152                         case 2:
6153                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6154                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6155                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6156                                 break;
6157                         case 3:
6158                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6159                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6160                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6161                                 break;
6162                         }
6163                         break;
6164                 case OP_INSERTX_R8_SLOW:
6165                         if (ins->inst_c0)
6166                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6167                         else
6168                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6169                         break;
6170                 case OP_STOREX_MEMBASE_REG:
6171                 case OP_STOREX_MEMBASE:
6172                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6173                         break;
6174                 case OP_LOADX_MEMBASE:
6175                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6176                         break;
6177                 case OP_LOADX_ALIGNED_MEMBASE:
6178                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6179                         break;
6180                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6181                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6182                         break;
6183                 case OP_STOREX_NTA_MEMBASE_REG:
6184                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6185                         break;
6186                 case OP_PREFETCH_MEMBASE:
6187                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6188                         break;
6189
6190                 case OP_XMOVE:
6191                         /*FIXME the peephole pass should have killed this*/
6192                         if (ins->dreg != ins->sreg1)
6193                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6194                         break;
6195                 case OP_XZERO:
6196                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6197                         break;
6198                 case OP_ICONV_TO_R8_RAW:
6199                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6200                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6201                         break;
6202
6203                 case OP_FCONV_TO_R8_X:
6204                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6205                         break;
6206
6207                 case OP_XCONV_R8_TO_I4:
6208                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6209                         switch (ins->backend.source_opcode) {
6210                         case OP_FCONV_TO_I1:
6211                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6212                                 break;
6213                         case OP_FCONV_TO_U1:
6214                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6215                                 break;
6216                         case OP_FCONV_TO_I2:
6217                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6218                                 break;
6219                         case OP_FCONV_TO_U2:
6220                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6221                                 break;
6222                         }
6223                         break;
6224
6225                 case OP_EXPAND_I2:
6226                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6227                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6228                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6229                         break;
6230                 case OP_EXPAND_I4:
6231                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6232                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6233                         break;
6234                 case OP_EXPAND_I8:
6235                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6236                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6237                         break;
6238                 case OP_EXPAND_R4:
6239                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6240                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6241                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6242                         break;
6243                 case OP_EXPAND_R8:
6244                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6245                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6246                         break;
6247 #endif
6248                 case OP_LIVERANGE_START: {
6249                         if (cfg->verbose_level > 1)
6250                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6251                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6252                         break;
6253                 }
6254                 case OP_LIVERANGE_END: {
6255                         if (cfg->verbose_level > 1)
6256                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6257                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6258                         break;
6259                 }
6260                 case OP_NACL_GC_SAFE_POINT: {
6261 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6262                         if (cfg->compile_aot)
6263                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6264                         else {
6265                                 guint8 *br [1];
6266
6267                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6268                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6269                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6270                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6271                                 amd64_patch (br[0], code);
6272                         }
6273 #endif
6274                         break;
6275                 }
6276                 case OP_GC_LIVENESS_DEF:
6277                 case OP_GC_LIVENESS_USE:
6278                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6279                         ins->backend.pc_offset = code - cfg->native_code;
6280                         break;
6281                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6282                         ins->backend.pc_offset = code - cfg->native_code;
6283                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6284                         break;
6285                 default:
6286                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6287                         g_assert_not_reached ();
6288                 }
6289
6290                 if ((code - cfg->native_code - offset) > max_len) {
6291 #if !defined(__native_client_codegen__)
6292                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6293                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6294                         g_assert_not_reached ();
6295 #endif
6296                 }
6297
6298                 last_ins = ins;
6299                 last_offset = offset;
6300         }
6301
6302         cfg->code_len = code - cfg->native_code;
6303 }
6304
6305 #endif /* DISABLE_JIT */
6306
6307 void
6308 mono_arch_register_lowlevel_calls (void)
6309 {
6310         /* The signature doesn't matter */
6311         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6312 }
6313
6314 void
6315 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6316 {
6317         MonoJumpInfo *patch_info;
6318         gboolean compile_aot = !run_cctors;
6319
6320         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6321                 unsigned char *ip = patch_info->ip.i + code;
6322                 unsigned char *target;
6323
6324                 if (compile_aot) {
6325                         switch (patch_info->type) {
6326                         case MONO_PATCH_INFO_BB:
6327                         case MONO_PATCH_INFO_LABEL:
6328                                 break;
6329                         default:
6330                                 /* No need to patch these */
6331                                 continue;
6332                         }
6333                 }
6334
6335                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6336
6337                 switch (patch_info->type) {
6338                 case MONO_PATCH_INFO_NONE:
6339                         continue;
6340                 case MONO_PATCH_INFO_METHOD_REL:
6341                 case MONO_PATCH_INFO_R8:
6342                 case MONO_PATCH_INFO_R4:
6343                         g_assert_not_reached ();
6344                         continue;
6345                 case MONO_PATCH_INFO_BB:
6346                         break;
6347                 default:
6348                         break;
6349                 }
6350
6351                 /*
6352                  * Debug code to help track down problems where the target of a near call is
6353                  * is not valid.
6354                  */
6355                 if (amd64_is_near_call (ip)) {
6356                         gint64 disp = (guint8*)target - (guint8*)ip;
6357
6358                         if (!amd64_is_imm32 (disp)) {
6359                                 printf ("TYPE: %d\n", patch_info->type);
6360                                 switch (patch_info->type) {
6361                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6362                                         printf ("V: %s\n", patch_info->data.name);
6363                                         break;
6364                                 case MONO_PATCH_INFO_METHOD_JUMP:
6365                                 case MONO_PATCH_INFO_METHOD:
6366                                         printf ("V: %s\n", patch_info->data.method->name);
6367                                         break;
6368                                 default:
6369                                         break;
6370                                 }
6371                         }
6372                 }
6373
6374                 amd64_patch (ip, (gpointer)target);
6375         }
6376 }
6377
6378 #ifndef DISABLE_JIT
6379
6380 static int
6381 get_max_epilog_size (MonoCompile *cfg)
6382 {
6383         int max_epilog_size = 16;
6384
6385         if (cfg->method->save_lmf)
6386                 max_epilog_size += 256;
6387
6388         if (mono_jit_trace_calls != NULL)
6389                 max_epilog_size += 50;
6390
6391         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6392                 max_epilog_size += 50;
6393
6394         max_epilog_size += (AMD64_NREG * 2);
6395
6396         return max_epilog_size;
6397 }
6398
6399 /*
6400  * This macro is used for testing whenever the unwinder works correctly at every point
6401  * where an async exception can happen.
6402  */
6403 /* This will generate a SIGSEGV at the given point in the code */
6404 #define async_exc_point(code) do { \
6405     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6406          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6407              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6408          cfg->arch.async_point_count ++; \
6409     } \
6410 } while (0)
6411
6412 guint8 *
6413 mono_arch_emit_prolog (MonoCompile *cfg)
6414 {
6415         MonoMethod *method = cfg->method;
6416         MonoBasicBlock *bb;
6417         MonoMethodSignature *sig;
6418         MonoInst *ins;
6419         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6420         guint8 *code;
6421         CallInfo *cinfo;
6422         MonoInst *lmf_var = cfg->lmf_var;
6423         gboolean args_clobbered = FALSE;
6424         gboolean trace = FALSE;
6425 #ifdef __native_client_codegen__
6426         guint alignment_check;
6427 #endif
6428
6429         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
6430
6431 #if defined(__default_codegen__)
6432         code = cfg->native_code = g_malloc (cfg->code_size);
6433 #elif defined(__native_client_codegen__)
6434         /* native_code_alloc is not 32-byte aligned, native_code is. */
6435         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6436
6437         /* Align native_code to next nearest kNaclAlignment byte. */
6438         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6439         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6440
6441         code = cfg->native_code;
6442
6443         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6444         g_assert (alignment_check == 0);
6445 #endif
6446
6447         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6448                 trace = TRUE;
6449
6450         /* Amount of stack space allocated by register saving code */
6451         pos = 0;
6452
6453         /* Offset between RSP and the CFA */
6454         cfa_offset = 0;
6455
6456         /*
6457          * The prolog consists of the following parts:
6458          * FP present:
6459          * - push rbp, mov rbp, rsp
6460          * - save callee saved regs using pushes
6461          * - allocate frame
6462          * - save rgctx if needed
6463          * - save lmf if needed
6464          * FP not present:
6465          * - allocate frame
6466          * - save rgctx if needed
6467          * - save lmf if needed
6468          * - save callee saved regs using moves
6469          */
6470
6471         // CFA = sp + 8
6472         cfa_offset = 8;
6473         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6474         // IP saved at CFA - 8
6475         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6476         async_exc_point (code);
6477         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6478
6479         if (!cfg->arch.omit_fp) {
6480                 amd64_push_reg (code, AMD64_RBP);
6481                 cfa_offset += 8;
6482                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6483                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6484                 async_exc_point (code);
6485 #ifdef HOST_WIN32
6486                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6487 #endif
6488                 /* These are handled automatically by the stack marking code */
6489                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6490
6491                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6492                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6493                 async_exc_point (code);
6494 #ifdef HOST_WIN32
6495                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6496 #endif
6497         }
6498
6499         /* The param area is always at offset 0 from sp */
6500         /* This needs to be allocated here, since it has to come after the spill area */
6501         if (cfg->param_area) {
6502                 if (cfg->arch.omit_fp)
6503                         // FIXME:
6504                         g_assert_not_reached ();
6505                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6506         }
6507
6508         if (cfg->arch.omit_fp) {
6509                 /*
6510                  * On enter, the stack is misaligned by the pushing of the return
6511                  * address. It is either made aligned by the pushing of %rbp, or by
6512                  * this.
6513                  */
6514                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6515                 if ((alloc_size % 16) == 0) {
6516                         alloc_size += 8;
6517                         /* Mark the padding slot as NOREF */
6518                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6519                 }
6520         } else {
6521                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6522                 if (cfg->stack_offset != alloc_size) {
6523                         /* Mark the padding slot as NOREF */
6524                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6525                 }
6526                 cfg->arch.sp_fp_offset = alloc_size;
6527                 alloc_size -= pos;
6528         }
6529
6530         cfg->arch.stack_alloc_size = alloc_size;
6531
6532         /* Allocate stack frame */
6533         if (alloc_size) {
6534                 /* See mono_emit_stack_alloc */
6535 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6536                 guint32 remaining_size = alloc_size;
6537                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6538                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6539                 guint32 offset = code - cfg->native_code;
6540                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6541                         while (required_code_size >= (cfg->code_size - offset))
6542                                 cfg->code_size *= 2;
6543                         cfg->native_code = mono_realloc_native_code (cfg);
6544                         code = cfg->native_code + offset;
6545                         cfg->stat_code_reallocs++;
6546                 }
6547
6548                 while (remaining_size >= 0x1000) {
6549                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6550                         if (cfg->arch.omit_fp) {
6551                                 cfa_offset += 0x1000;
6552                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6553                         }
6554                         async_exc_point (code);
6555 #ifdef HOST_WIN32
6556                         if (cfg->arch.omit_fp)
6557                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6558 #endif
6559
6560                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6561                         remaining_size -= 0x1000;
6562                 }
6563                 if (remaining_size) {
6564                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6565                         if (cfg->arch.omit_fp) {
6566                                 cfa_offset += remaining_size;
6567                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6568                                 async_exc_point (code);
6569                         }
6570 #ifdef HOST_WIN32
6571                         if (cfg->arch.omit_fp)
6572                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6573 #endif
6574                 }
6575 #else
6576                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6577                 if (cfg->arch.omit_fp) {
6578                         cfa_offset += alloc_size;
6579                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6580                         async_exc_point (code);
6581                 }
6582 #endif
6583         }
6584
6585         /* Stack alignment check */
6586 #if 0
6587         {
6588                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6589                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6590                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6591                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6592                 amd64_breakpoint (code);
6593         }
6594 #endif
6595
6596         if (mini_get_debug_options ()->init_stacks) {
6597                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6598
6599                 /* Save registers to the red zone */
6600                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6601                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6602
6603                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6604                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6605                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6606
6607                 amd64_cld (code);
6608 #if defined(__default_codegen__)
6609                 amd64_prefix (code, X86_REP_PREFIX);
6610                 amd64_stosl (code);
6611 #elif defined(__native_client_codegen__)
6612                 /* NaCl stos pseudo-instruction */
6613                 amd64_codegen_pre (code);
6614                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6615                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6616                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6617                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6618                 amd64_prefix (code, X86_REP_PREFIX);
6619                 amd64_stosl (code);
6620                 amd64_codegen_post (code);
6621 #endif /* __native_client_codegen__ */
6622
6623                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6624                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6625         }
6626
6627         /* Save LMF */
6628         if (method->save_lmf)
6629                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6630
6631         /* Save callee saved registers */
6632         if (cfg->arch.omit_fp) {
6633                 save_area_offset = cfg->arch.reg_save_area_offset;
6634                 /* Save caller saved registers after sp is adjusted */
6635                 /* The registers are saved at the bottom of the frame */
6636                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6637         } else {
6638                 /* The registers are saved just below the saved rbp */
6639                 save_area_offset = cfg->arch.reg_save_area_offset;
6640         }
6641
6642         for (i = 0; i < AMD64_NREG; ++i) {
6643                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6644                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6645
6646                         if (cfg->arch.omit_fp) {
6647                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6648                                 /* These are handled automatically by the stack marking code */
6649                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6650                         } else {
6651                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6652                                 // FIXME: GC
6653                         }
6654
6655                         save_area_offset += 8;
6656                         async_exc_point (code);
6657                 }
6658         }
6659
6660         /* store runtime generic context */
6661         if (cfg->rgctx_var) {
6662                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6663                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6664
6665                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6666
6667                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6668                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6669         }
6670
6671         /* compute max_length in order to use short forward jumps */
6672         max_epilog_size = get_max_epilog_size (cfg);
6673         if (cfg->opt & MONO_OPT_BRANCH) {
6674                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6675                         MonoInst *ins;
6676                         int max_length = 0;
6677
6678                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6679                                 max_length += 6;
6680                         /* max alignment for loops */
6681                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6682                                 max_length += LOOP_ALIGNMENT;
6683 #ifdef __native_client_codegen__
6684                         /* max alignment for native client */
6685                         max_length += kNaClAlignment;
6686 #endif
6687
6688                         MONO_BB_FOR_EACH_INS (bb, ins) {
6689 #ifdef __native_client_codegen__
6690                                 {
6691                                         int space_in_block = kNaClAlignment -
6692                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6693                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6694                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6695                                                 max_length += space_in_block;
6696                                         }
6697                                 }
6698 #endif  /*__native_client_codegen__*/
6699                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6700                         }
6701
6702                         /* Take prolog and epilog instrumentation into account */
6703                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6704                                 max_length += max_epilog_size;
6705
6706                         bb->max_length = max_length;
6707                 }
6708         }
6709
6710         sig = mono_method_signature (method);
6711         pos = 0;
6712
6713         cinfo = cfg->arch.cinfo;
6714
6715         if (sig->ret->type != MONO_TYPE_VOID) {
6716                 /* Save volatile arguments to the stack */
6717                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6718                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6719         }
6720
6721         /* Keep this in sync with emit_load_volatile_arguments */
6722         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6723                 ArgInfo *ainfo = cinfo->args + i;
6724                 gint32 stack_offset;
6725                 MonoType *arg_type;
6726
6727                 ins = cfg->args [i];
6728
6729                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6730                         /* Unused arguments */
6731                         continue;
6732
6733                 if (sig->hasthis && (i == 0))
6734                         arg_type = &mono_defaults.object_class->byval_arg;
6735                 else
6736                         arg_type = sig->params [i - sig->hasthis];
6737
6738                 stack_offset = ainfo->offset + ARGS_OFFSET;
6739
6740                 if (cfg->globalra) {
6741                         /* All the other moves are done by the register allocator */
6742                         switch (ainfo->storage) {
6743                         case ArgInFloatSSEReg:
6744                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6745                                 break;
6746                         case ArgValuetypeInReg:
6747                                 for (quad = 0; quad < 2; quad ++) {
6748                                         switch (ainfo->pair_storage [quad]) {
6749                                         case ArgInIReg:
6750                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6751                                                 break;
6752                                         case ArgInFloatSSEReg:
6753                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6754                                                 break;
6755                                         case ArgInDoubleSSEReg:
6756                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6757                                                 break;
6758                                         case ArgNone:
6759                                                 break;
6760                                         default:
6761                                                 g_assert_not_reached ();
6762                                         }
6763                                 }
6764                                 break;
6765                         default:
6766                                 break;
6767                         }
6768
6769                         continue;
6770                 }
6771
6772                 /* Save volatile arguments to the stack */
6773                 if (ins->opcode != OP_REGVAR) {
6774                         switch (ainfo->storage) {
6775                         case ArgInIReg: {
6776                                 guint32 size = 8;
6777
6778                                 /* FIXME: I1 etc */
6779                                 /*
6780                                 if (stack_offset & 0x1)
6781                                         size = 1;
6782                                 else if (stack_offset & 0x2)
6783                                         size = 2;
6784                                 else if (stack_offset & 0x4)
6785                                         size = 4;
6786                                 else
6787                                         size = 8;
6788                                 */
6789                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6790
6791                                 /*
6792                                  * Save the original location of 'this',
6793                                  * get_generic_info_from_stack_frame () needs this to properly look up
6794                                  * the argument value during the handling of async exceptions.
6795                                  */
6796                                 if (ins == cfg->args [0]) {
6797                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6798                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6799                                 }
6800                                 break;
6801                         }
6802                         case ArgInFloatSSEReg:
6803                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6804                                 break;
6805                         case ArgInDoubleSSEReg:
6806                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6807                                 break;
6808                         case ArgValuetypeInReg:
6809                                 for (quad = 0; quad < 2; quad ++) {
6810                                         switch (ainfo->pair_storage [quad]) {
6811                                         case ArgInIReg:
6812                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6813                                                 break;
6814                                         case ArgInFloatSSEReg:
6815                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6816                                                 break;
6817                                         case ArgInDoubleSSEReg:
6818                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6819                                                 break;
6820                                         case ArgNone:
6821                                                 break;
6822                                         default:
6823                                                 g_assert_not_reached ();
6824                                         }
6825                                 }
6826                                 break;
6827                         case ArgValuetypeAddrInIReg:
6828                                 if (ainfo->pair_storage [0] == ArgInIReg)
6829                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6830                                 break;
6831                         default:
6832                                 break;
6833                         }
6834                 } else {
6835                         /* Argument allocated to (non-volatile) register */
6836                         switch (ainfo->storage) {
6837                         case ArgInIReg:
6838                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6839                                 break;
6840                         case ArgOnStack:
6841                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6842                                 break;
6843                         default:
6844                                 g_assert_not_reached ();
6845                         }
6846
6847                         if (ins == cfg->args [0]) {
6848                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6849                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6850                         }
6851                 }
6852         }
6853
6854         if (cfg->method->save_lmf)
6855                 args_clobbered = TRUE;
6856
6857         if (trace) {
6858                 args_clobbered = TRUE;
6859                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6860         }
6861
6862         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6863                 args_clobbered = TRUE;
6864
6865         /*
6866          * Optimize the common case of the first bblock making a call with the same
6867          * arguments as the method. This works because the arguments are still in their
6868          * original argument registers.
6869          * FIXME: Generalize this
6870          */
6871         if (!args_clobbered) {
6872                 MonoBasicBlock *first_bb = cfg->bb_entry;
6873                 MonoInst *next;
6874
6875                 next = mono_bb_first_ins (first_bb);
6876                 if (!next && first_bb->next_bb) {
6877                         first_bb = first_bb->next_bb;
6878                         next = mono_bb_first_ins (first_bb);
6879                 }
6880
6881                 if (first_bb->in_count > 1)
6882                         next = NULL;
6883
6884                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6885                         ArgInfo *ainfo = cinfo->args + i;
6886                         gboolean match = FALSE;
6887
6888                         ins = cfg->args [i];
6889                         if (ins->opcode != OP_REGVAR) {
6890                                 switch (ainfo->storage) {
6891                                 case ArgInIReg: {
6892                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6893                                                 if (next->dreg == ainfo->reg) {
6894                                                         NULLIFY_INS (next);
6895                                                         match = TRUE;
6896                                                 } else {
6897                                                         next->opcode = OP_MOVE;
6898                                                         next->sreg1 = ainfo->reg;
6899                                                         /* Only continue if the instruction doesn't change argument regs */
6900                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6901                                                                 match = TRUE;
6902                                                 }
6903                                         }
6904                                         break;
6905                                 }
6906                                 default:
6907                                         break;
6908                                 }
6909                         } else {
6910                                 /* Argument allocated to (non-volatile) register */
6911                                 switch (ainfo->storage) {
6912                                 case ArgInIReg:
6913                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6914                                                 NULLIFY_INS (next);
6915                                                 match = TRUE;
6916                                         }
6917                                         break;
6918                                 default:
6919                                         break;
6920                                 }
6921                         }
6922
6923                         if (match) {
6924                                 next = next->next;
6925                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6926                                 if (!next)
6927                                         break;
6928                         }
6929                 }
6930         }
6931
6932         if (cfg->gen_seq_points) {
6933                 MonoInst *info_var = cfg->arch.seq_point_info_var;
6934
6935                 /* Initialize seq_point_info_var */
6936                 if (cfg->compile_aot) {
6937                         /* Initialize the variable from a GOT slot */
6938                         /* Same as OP_AOTCONST */
6939                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6940                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
6941                         g_assert (info_var->opcode == OP_REGOFFSET);
6942                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
6943                 }
6944
6945                 /* Initialize ss_trigger_page_var */
6946                 ins = cfg->arch.ss_trigger_page_var;
6947
6948                 g_assert (ins->opcode == OP_REGOFFSET);
6949
6950                 if (cfg->compile_aot) {
6951                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
6952                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
6953                 } else {
6954                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6955                 }
6956                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
6957         }
6958
6959         cfg->code_len = code - cfg->native_code;
6960
6961         g_assert (cfg->code_len < cfg->code_size);
6962
6963         return code;
6964 }
6965
6966 void
6967 mono_arch_emit_epilog (MonoCompile *cfg)
6968 {
6969         MonoMethod *method = cfg->method;
6970         int quad, pos, i;
6971         guint8 *code;
6972         int max_epilog_size;
6973         CallInfo *cinfo;
6974         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
6975         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6976
6977         max_epilog_size = get_max_epilog_size (cfg);
6978
6979         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6980                 cfg->code_size *= 2;
6981                 cfg->native_code = mono_realloc_native_code (cfg);
6982                 cfg->stat_code_reallocs++;
6983         }
6984
6985         code = cfg->native_code + cfg->code_len;
6986
6987         cfg->has_unwind_info_for_epilog = TRUE;
6988
6989         /* Mark the start of the epilog */
6990         mono_emit_unwind_op_mark_loc (cfg, code, 0);
6991
6992         /* Save the uwind state which is needed by the out-of-line code */
6993         mono_emit_unwind_op_remember_state (cfg, code);
6994
6995         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6996                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6997
6998         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
6999         pos = 0;
7000
7001         if (method->save_lmf) {
7002                 /* check if we need to restore protection of the stack after a stack overflow */
7003                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7004                         guint8 *patch;
7005                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7006                         /* we load the value in a separate instruction: this mechanism may be
7007                          * used later as a safer way to do thread interruption
7008                          */
7009                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7010                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7011                         patch = code;
7012                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7013                         /* note that the call trampoline will preserve eax/edx */
7014                         x86_call_reg (code, X86_ECX);
7015                         x86_patch (patch, code);
7016                 } else {
7017                         /* FIXME: maybe save the jit tls in the prolog */
7018                 }
7019                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7020                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7021                 }
7022         }
7023
7024         /* Restore callee saved regs */
7025         for (i = 0; i < AMD64_NREG; ++i) {
7026                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7027                         /* Restore only used_int_regs, not arch.saved_iregs */
7028                         if (cfg->used_int_regs & (1 << i)) {
7029                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7030                                 mono_emit_unwind_op_same_value (cfg, code, i);
7031                                 async_exc_point (code);
7032                         }
7033                         save_area_offset += 8;
7034                 }
7035         }
7036
7037         /* Load returned vtypes into registers if needed */
7038         cinfo = cfg->arch.cinfo;
7039         if (cinfo->ret.storage == ArgValuetypeInReg) {
7040                 ArgInfo *ainfo = &cinfo->ret;
7041                 MonoInst *inst = cfg->ret;
7042
7043                 for (quad = 0; quad < 2; quad ++) {
7044                         switch (ainfo->pair_storage [quad]) {
7045                         case ArgInIReg:
7046                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7047                                 break;
7048                         case ArgInFloatSSEReg:
7049                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7050                                 break;
7051                         case ArgInDoubleSSEReg:
7052                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7053                                 break;
7054                         case ArgNone:
7055                                 break;
7056                         default:
7057                                 g_assert_not_reached ();
7058                         }
7059                 }
7060         }
7061
7062         if (cfg->arch.omit_fp) {
7063                 if (cfg->arch.stack_alloc_size) {
7064                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7065                 }
7066         } else {
7067                 amd64_leave (code);
7068                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7069         }
7070         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7071         async_exc_point (code);
7072         amd64_ret (code);
7073
7074         /* Restore the unwind state to be the same as before the epilog */
7075         mono_emit_unwind_op_restore_state (cfg, code);
7076
7077         cfg->code_len = code - cfg->native_code;
7078
7079         g_assert (cfg->code_len < cfg->code_size);
7080 }
7081
7082 void
7083 mono_arch_emit_exceptions (MonoCompile *cfg)
7084 {
7085         MonoJumpInfo *patch_info;
7086         int nthrows, i;
7087         guint8 *code;
7088         MonoClass *exc_classes [16];
7089         guint8 *exc_throw_start [16], *exc_throw_end [16];
7090         guint32 code_size = 0;
7091
7092         /* Compute needed space */
7093         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7094                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7095                         code_size += 40;
7096                 if (patch_info->type == MONO_PATCH_INFO_R8)
7097                         code_size += 8 + 15; /* sizeof (double) + alignment */
7098                 if (patch_info->type == MONO_PATCH_INFO_R4)
7099                         code_size += 4 + 15; /* sizeof (float) + alignment */
7100                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7101                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7102         }
7103
7104 #ifdef __native_client_codegen__
7105         /* Give us extra room on Native Client.  This could be   */
7106         /* more carefully calculated, but bundle alignment makes */
7107         /* it much trickier, so *2 like other places is good.    */
7108         code_size *= 2;
7109 #endif
7110
7111         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7112                 cfg->code_size *= 2;
7113                 cfg->native_code = mono_realloc_native_code (cfg);
7114                 cfg->stat_code_reallocs++;
7115         }
7116
7117         code = cfg->native_code + cfg->code_len;
7118
7119         /* add code to raise exceptions */
7120         nthrows = 0;
7121         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7122                 switch (patch_info->type) {
7123                 case MONO_PATCH_INFO_EXC: {
7124                         MonoClass *exc_class;
7125                         guint8 *buf, *buf2;
7126                         guint32 throw_ip;
7127
7128                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7129
7130                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7131                         g_assert (exc_class);
7132                         throw_ip = patch_info->ip.i;
7133
7134                         //x86_breakpoint (code);
7135                         /* Find a throw sequence for the same exception class */
7136                         for (i = 0; i < nthrows; ++i)
7137                                 if (exc_classes [i] == exc_class)
7138                                         break;
7139                         if (i < nthrows) {
7140                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7141                                 x86_jump_code (code, exc_throw_start [i]);
7142                                 patch_info->type = MONO_PATCH_INFO_NONE;
7143                         }
7144                         else {
7145                                 buf = code;
7146                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7147                                 buf2 = code;
7148
7149                                 if (nthrows < 16) {
7150                                         exc_classes [nthrows] = exc_class;
7151                                         exc_throw_start [nthrows] = code;
7152                                 }
7153                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7154
7155                                 patch_info->type = MONO_PATCH_INFO_NONE;
7156
7157                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7158
7159                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7160                                 while (buf < buf2)
7161                                         x86_nop (buf);
7162
7163                                 if (nthrows < 16) {
7164                                         exc_throw_end [nthrows] = code;
7165                                         nthrows ++;
7166                                 }
7167                         }
7168                         break;
7169                 }
7170                 default:
7171                         /* do nothing */
7172                         break;
7173                 }
7174                 g_assert(code < cfg->native_code + cfg->code_size);
7175         }
7176
7177         /* Handle relocations with RIP relative addressing */
7178         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7179                 gboolean remove = FALSE;
7180                 guint8 *orig_code = code;
7181
7182                 switch (patch_info->type) {
7183                 case MONO_PATCH_INFO_R8:
7184                 case MONO_PATCH_INFO_R4: {
7185                         guint8 *pos, *patch_pos;
7186                         guint32 target_pos;
7187
7188                         /* The SSE opcodes require a 16 byte alignment */
7189 #if defined(__default_codegen__)
7190                         code = (guint8*)ALIGN_TO (code, 16);
7191 #elif defined(__native_client_codegen__)
7192                         {
7193                                 /* Pad this out with HLT instructions  */
7194                                 /* or we can get garbage bytes emitted */
7195                                 /* which will fail validation          */
7196                                 guint8 *aligned_code;
7197                                 /* extra align to make room for  */
7198                                 /* mov/push below                      */
7199                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7200                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7201                                 /* The technique of hiding data in an  */
7202                                 /* instruction has a problem here: we  */
7203                                 /* need the data aligned to a 16-byte  */
7204                                 /* boundary but the instruction cannot */
7205                                 /* cross the bundle boundary. so only  */
7206                                 /* odd multiples of 16 can be used     */
7207                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7208                                         aligned_code += 16;
7209                                 }
7210                                 while (code < aligned_code) {
7211                                         *(code++) = 0xf4; /* hlt */
7212                                 }
7213                         }
7214 #endif
7215
7216                         pos = cfg->native_code + patch_info->ip.i;
7217                         if (IS_REX (pos [1])) {
7218                                 patch_pos = pos + 5;
7219                                 target_pos = code - pos - 9;
7220                         }
7221                         else {
7222                                 patch_pos = pos + 4;
7223                                 target_pos = code - pos - 8;
7224                         }
7225
7226                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7227 #ifdef __native_client_codegen__
7228                                 /* Hide 64-bit data in a         */
7229                                 /* "mov imm64, r11" instruction. */
7230                                 /* write it before the start of  */
7231                                 /* the data*/
7232                                 *(code-2) = 0x49; /* prefix      */
7233                                 *(code-1) = 0xbb; /* mov X, %r11 */
7234 #endif
7235                                 *(double*)code = *(double*)patch_info->data.target;
7236                                 code += sizeof (double);
7237                         } else {
7238 #ifdef __native_client_codegen__
7239                                 /* Hide 32-bit data in a        */
7240                                 /* "push imm32" instruction.    */
7241                                 *(code-1) = 0x68; /* push */
7242 #endif
7243                                 *(float*)code = *(float*)patch_info->data.target;
7244                                 code += sizeof (float);
7245                         }
7246
7247                         *(guint32*)(patch_pos) = target_pos;
7248
7249                         remove = TRUE;
7250                         break;
7251                 }
7252                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7253                         guint8 *pos;
7254
7255                         if (cfg->compile_aot)
7256                                 continue;
7257
7258                         /*loading is faster against aligned addresses.*/
7259                         code = (guint8*)ALIGN_TO (code, 8);
7260                         memset (orig_code, 0, code - orig_code);
7261
7262                         pos = cfg->native_code + patch_info->ip.i;
7263
7264                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7265                         if (IS_REX (pos [1]))
7266                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7267                         else
7268                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7269
7270                         *(gpointer*)code = (gpointer)patch_info->data.target;
7271                         code += sizeof (gpointer);
7272
7273                         remove = TRUE;
7274                         break;
7275                 }
7276                 default:
7277                         break;
7278                 }
7279
7280                 if (remove) {
7281                         if (patch_info == cfg->patch_info)
7282                                 cfg->patch_info = patch_info->next;
7283                         else {
7284                                 MonoJumpInfo *tmp;
7285
7286                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7287                                         ;
7288                                 tmp->next = patch_info->next;
7289                         }
7290                 }
7291                 g_assert (code < cfg->native_code + cfg->code_size);
7292         }
7293
7294         cfg->code_len = code - cfg->native_code;
7295
7296         g_assert (cfg->code_len < cfg->code_size);
7297
7298 }
7299
7300 #endif /* DISABLE_JIT */
7301
7302 void*
7303 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7304 {
7305         guchar *code = p;
7306         CallInfo *cinfo = NULL;
7307         MonoMethodSignature *sig;
7308         MonoInst *inst;
7309         int i, n, stack_area = 0;
7310
7311         /* Keep this in sync with mono_arch_get_argument_info */
7312
7313         if (enable_arguments) {
7314                 /* Allocate a new area on the stack and save arguments there */
7315                 sig = mono_method_signature (cfg->method);
7316
7317                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7318
7319                 n = sig->param_count + sig->hasthis;
7320
7321                 stack_area = ALIGN_TO (n * 8, 16);
7322
7323                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7324
7325                 for (i = 0; i < n; ++i) {
7326                         inst = cfg->args [i];
7327
7328                         if (inst->opcode == OP_REGVAR)
7329                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7330                         else {
7331                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7332                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7333                         }
7334                 }
7335         }
7336
7337         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7338         amd64_set_reg_template (code, AMD64_ARG_REG1);
7339         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7340         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7341
7342         if (enable_arguments)
7343                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7344
7345         return code;
7346 }
7347
7348 enum {
7349         SAVE_NONE,
7350         SAVE_STRUCT,
7351         SAVE_EAX,
7352         SAVE_EAX_EDX,
7353         SAVE_XMM
7354 };
7355
7356 void*
7357 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7358 {
7359         guchar *code = p;
7360         int save_mode = SAVE_NONE;
7361         MonoMethod *method = cfg->method;
7362         MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7363         int i;
7364
7365         switch (ret_type->type) {
7366         case MONO_TYPE_VOID:
7367                 /* special case string .ctor icall */
7368                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7369                         save_mode = SAVE_EAX;
7370                 else
7371                         save_mode = SAVE_NONE;
7372                 break;
7373         case MONO_TYPE_I8:
7374         case MONO_TYPE_U8:
7375                 save_mode = SAVE_EAX;
7376                 break;
7377         case MONO_TYPE_R4:
7378         case MONO_TYPE_R8:
7379                 save_mode = SAVE_XMM;
7380                 break;
7381         case MONO_TYPE_GENERICINST:
7382                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7383                         save_mode = SAVE_EAX;
7384                         break;
7385                 }
7386                 /* Fall through */
7387         case MONO_TYPE_VALUETYPE:
7388                 save_mode = SAVE_STRUCT;
7389                 break;
7390         default:
7391                 save_mode = SAVE_EAX;
7392                 break;
7393         }
7394
7395         /* Save the result and copy it into the proper argument register */
7396         switch (save_mode) {
7397         case SAVE_EAX:
7398                 amd64_push_reg (code, AMD64_RAX);
7399                 /* Align stack */
7400                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7401                 if (enable_arguments)
7402                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7403                 break;
7404         case SAVE_STRUCT:
7405                 /* FIXME: */
7406                 if (enable_arguments)
7407                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7408                 break;
7409         case SAVE_XMM:
7410                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7411                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7412                 /* Align stack */
7413                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7414                 /*
7415                  * The result is already in the proper argument register so no copying
7416                  * needed.
7417                  */
7418                 break;
7419         case SAVE_NONE:
7420                 break;
7421         default:
7422                 g_assert_not_reached ();
7423         }
7424
7425         /* Set %al since this is a varargs call */
7426         if (save_mode == SAVE_XMM)
7427                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7428         else
7429                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7430
7431         if (preserve_argument_registers) {
7432                 for (i = 0; i < PARAM_REGS; ++i)
7433                         amd64_push_reg (code, param_regs [i]);
7434         }
7435
7436         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7437         amd64_set_reg_template (code, AMD64_ARG_REG1);
7438         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7439
7440         if (preserve_argument_registers) {
7441                 for (i = PARAM_REGS - 1; i >= 0; --i)
7442                         amd64_pop_reg (code, param_regs [i]);
7443         }
7444
7445         /* Restore result */
7446         switch (save_mode) {
7447         case SAVE_EAX:
7448                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7449                 amd64_pop_reg (code, AMD64_RAX);
7450                 break;
7451         case SAVE_STRUCT:
7452                 /* FIXME: */
7453                 break;
7454         case SAVE_XMM:
7455                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7456                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7457                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7458                 break;
7459         case SAVE_NONE:
7460                 break;
7461         default:
7462                 g_assert_not_reached ();
7463         }
7464
7465         return code;
7466 }
7467
7468 void
7469 mono_arch_flush_icache (guint8 *code, gint size)
7470 {
7471         /* Not needed */
7472 }
7473
7474 void
7475 mono_arch_flush_register_windows (void)
7476 {
7477 }
7478
7479 gboolean
7480 mono_arch_is_inst_imm (gint64 imm)
7481 {
7482         return amd64_is_imm32 (imm);
7483 }
7484
7485 /*
7486  * Determine whenever the trap whose info is in SIGINFO is caused by
7487  * integer overflow.
7488  */
7489 gboolean
7490 mono_arch_is_int_overflow (void *sigctx, void *info)
7491 {
7492         MonoContext ctx;
7493         guint8* rip;
7494         int reg;
7495         gint64 value;
7496
7497         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7498
7499         rip = (guint8*)ctx.rip;
7500
7501         if (IS_REX (rip [0])) {
7502                 reg = amd64_rex_b (rip [0]);
7503                 rip ++;
7504         }
7505         else
7506                 reg = 0;
7507
7508         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7509                 /* idiv REG */
7510                 reg += x86_modrm_rm (rip [1]);
7511
7512                 switch (reg) {
7513                 case AMD64_RAX:
7514                         value = ctx.rax;
7515                         break;
7516                 case AMD64_RBX:
7517                         value = ctx.rbx;
7518                         break;
7519                 case AMD64_RCX:
7520                         value = ctx.rcx;
7521                         break;
7522                 case AMD64_RDX:
7523                         value = ctx.rdx;
7524                         break;
7525                 case AMD64_RBP:
7526                         value = ctx.rbp;
7527                         break;
7528                 case AMD64_RSP:
7529                         value = ctx.rsp;
7530                         break;
7531                 case AMD64_RSI:
7532                         value = ctx.rsi;
7533                         break;
7534                 case AMD64_RDI:
7535                         value = ctx.rdi;
7536                         break;
7537                 case AMD64_R12:
7538                         value = ctx.r12;
7539                         break;
7540                 case AMD64_R13:
7541                         value = ctx.r13;
7542                         break;
7543                 case AMD64_R14:
7544                         value = ctx.r14;
7545                         break;
7546                 case AMD64_R15:
7547                         value = ctx.r15;
7548                         break;
7549                 default:
7550                         g_assert_not_reached ();
7551                         reg = -1;
7552                 }
7553
7554                 if (value == -1)
7555                         return TRUE;
7556         }
7557
7558         return FALSE;
7559 }
7560
7561 guint32
7562 mono_arch_get_patch_offset (guint8 *code)
7563 {
7564         return 3;
7565 }
7566
7567 /**
7568  * mono_breakpoint_clean_code:
7569  *
7570  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7571  * breakpoints in the original code, they are removed in the copy.
7572  *
7573  * Returns TRUE if no sw breakpoint was present.
7574  */
7575 gboolean
7576 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7577 {
7578         int i;
7579         gboolean can_write = TRUE;
7580         /*
7581          * If method_start is non-NULL we need to perform bound checks, since we access memory
7582          * at code - offset we could go before the start of the method and end up in a different
7583          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7584          * instead.
7585          */
7586         if (!method_start || code - offset >= method_start) {
7587                 memcpy (buf, code - offset, size);
7588         } else {
7589                 int diff = code - method_start;
7590                 memset (buf, 0, size);
7591                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7592         }
7593         code -= offset;
7594         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7595                 int idx = mono_breakpoint_info_index [i];
7596                 guint8 *ptr;
7597                 if (idx < 1)
7598                         continue;
7599                 ptr = mono_breakpoint_info [idx].address;
7600                 if (ptr >= code && ptr < code + size) {
7601                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7602                         can_write = FALSE;
7603                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7604                         buf [ptr - code] = saved_byte;
7605                 }
7606         }
7607         return can_write;
7608 }
7609
7610 #if defined(__native_client_codegen__)
7611 /* For membase calls, we want the base register. for Native Client,  */
7612 /* all indirect calls have the following sequence with the given sizes: */
7613 /* mov %eXX,%eXX                                [2-3]   */
7614 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7615 /* and $0xffffffffffffffe0,%r11d                [4]     */
7616 /* add %r15,%r11                                [3]     */
7617 /* callq *%r11                                  [3]     */
7618
7619
7620 /* Determine if code points to a NaCl call-through-register sequence, */
7621 /* (i.e., the last 3 instructions listed above) */
7622 int
7623 is_nacl_call_reg_sequence(guint8* code)
7624 {
7625         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7626                                "\x4d\x03\xdf"     /* add */
7627                                "\x41\xff\xd3";   /* call */
7628         return memcmp(code, sequence, 10) == 0;
7629 }
7630
7631 /* Determine if code points to the first opcode of the mov membase component */
7632 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7633 /* (there could be a REX prefix before the opcode but it is ignored) */
7634 static int
7635 is_nacl_indirect_call_membase_sequence(guint8* code)
7636 {
7637                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7638         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7639                /* and that src reg = dest reg */
7640                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7641                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7642                IS_REX(code[2]) &&
7643                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7644                /* and has dst of r11 and base of r15 */
7645                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7646                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7647 }
7648 #endif /* __native_client_codegen__ */
7649
7650 int
7651 mono_arch_get_this_arg_reg (guint8 *code)
7652 {
7653         return AMD64_ARG_REG1;
7654 }
7655
7656 gpointer
7657 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7658 {
7659         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7660 }
7661
7662 #define MAX_ARCH_DELEGATE_PARAMS 10
7663
7664 static gpointer
7665 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7666 {
7667         guint8 *code, *start;
7668         int i;
7669
7670         if (has_target) {
7671                 start = code = mono_global_codeman_reserve (64);
7672
7673                 /* Replace the this argument with the target */
7674                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7675                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7676                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7677
7678                 g_assert ((code - start) < 64);
7679         } else {
7680                 start = code = mono_global_codeman_reserve (64);
7681
7682                 if (param_count == 0) {
7683                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7684                 } else {
7685                         /* We have to shift the arguments left */
7686                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7687                         for (i = 0; i < param_count; ++i) {
7688 #ifdef HOST_WIN32
7689                                 if (i < 3)
7690                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7691                                 else
7692                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7693 #else
7694                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7695 #endif
7696                         }
7697
7698                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7699                 }
7700                 g_assert ((code - start) < 64);
7701         }
7702
7703         nacl_global_codeman_validate(&start, 64, &code);
7704
7705         mono_debug_add_delegate_trampoline (start, code - start);
7706
7707         if (code_len)
7708                 *code_len = code - start;
7709
7710
7711         if (mono_jit_map_is_enabled ()) {
7712                 char *buff;
7713                 if (has_target)
7714                         buff = (char*)"delegate_invoke_has_target";
7715                 else
7716                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7717                 mono_emit_jit_tramp (start, code - start, buff);
7718                 if (!has_target)
7719                         g_free (buff);
7720         }
7721
7722         return start;
7723 }
7724
7725 /*
7726  * mono_arch_get_delegate_invoke_impls:
7727  *
7728  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7729  * trampolines.
7730  */
7731 GSList*
7732 mono_arch_get_delegate_invoke_impls (void)
7733 {
7734         GSList *res = NULL;
7735         guint8 *code;
7736         guint32 code_len;
7737         int i;
7738         char *tramp_name;
7739
7740         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7741         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7742
7743         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7744                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7745                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7746                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7747                 g_free (tramp_name);
7748         }
7749
7750         return res;
7751 }
7752
7753 gpointer
7754 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7755 {
7756         guint8 *code, *start;
7757         int i;
7758
7759         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7760                 return NULL;
7761
7762         /* FIXME: Support more cases */
7763         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7764                 return NULL;
7765
7766         if (has_target) {
7767                 static guint8* cached = NULL;
7768
7769                 if (cached)
7770                         return cached;
7771
7772                 if (mono_aot_only)
7773                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7774                 else
7775                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7776
7777                 mono_memory_barrier ();
7778
7779                 cached = start;
7780         } else {
7781                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7782                 for (i = 0; i < sig->param_count; ++i)
7783                         if (!mono_is_regsize_var (sig->params [i]))
7784                                 return NULL;
7785                 if (sig->param_count > 4)
7786                         return NULL;
7787
7788                 code = cache [sig->param_count];
7789                 if (code)
7790                         return code;
7791
7792                 if (mono_aot_only) {
7793                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7794                         start = mono_aot_get_trampoline (name);
7795                         g_free (name);
7796                 } else {
7797                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7798                 }
7799
7800                 mono_memory_barrier ();
7801
7802                 cache [sig->param_count] = start;
7803         }
7804
7805         return start;
7806 }
7807
7808 gpointer
7809 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7810 {
7811         guint8 *code, *start;
7812         int size = 20;
7813
7814         start = code = mono_global_codeman_reserve (size);
7815
7816         /* Replace the this argument with the target */
7817         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7818         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7819
7820         if (load_imt_reg) {
7821                 /* Load the IMT reg */
7822                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7823         }
7824
7825         /* Load the vtable */
7826         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7827         amd64_jump_membase (code, AMD64_RAX, offset);
7828
7829         return start;
7830 }
7831
7832 void
7833 mono_arch_finish_init (void)
7834 {
7835 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7836         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7837 #endif
7838 }
7839
7840 void
7841 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7842 {
7843 }
7844
7845 #if defined(__default_codegen__)
7846 #define CMP_SIZE (6 + 1)
7847 #define CMP_REG_REG_SIZE (4 + 1)
7848 #define BR_SMALL_SIZE 2
7849 #define BR_LARGE_SIZE 6
7850 #define MOV_REG_IMM_SIZE 10
7851 #define MOV_REG_IMM_32BIT_SIZE 6
7852 #define JUMP_REG_SIZE (2 + 1)
7853 #elif defined(__native_client_codegen__)
7854 /* NaCl N-byte instructions can be padded up to N-1 bytes */
7855 #define CMP_SIZE ((6 + 1) * 2 - 1)
7856 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
7857 #define BR_SMALL_SIZE (2 * 2 - 1)
7858 #define BR_LARGE_SIZE (6 * 2 - 1)
7859 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
7860 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
7861 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
7862 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
7863 /* Jump membase's size is large and unpredictable    */
7864 /* in native client, just pad it out a whole bundle. */
7865 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
7866 #endif
7867
7868 static int
7869 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7870 {
7871         int i, distance = 0;
7872         for (i = start; i < target; ++i)
7873                 distance += imt_entries [i]->chunk_size;
7874         return distance;
7875 }
7876
7877 /*
7878  * LOCKING: called with the domain lock held
7879  */
7880 gpointer
7881 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7882         gpointer fail_tramp)
7883 {
7884         int i;
7885         int size = 0;
7886         guint8 *code, *start;
7887         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7888
7889         for (i = 0; i < count; ++i) {
7890                 MonoIMTCheckItem *item = imt_entries [i];
7891                 if (item->is_equals) {
7892                         if (item->check_target_idx) {
7893                                 if (!item->compare_done) {
7894                                         if (amd64_is_imm32 (item->key))
7895                                                 item->chunk_size += CMP_SIZE;
7896                                         else
7897                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7898                                 }
7899                                 if (item->has_target_code) {
7900                                         item->chunk_size += MOV_REG_IMM_SIZE;
7901                                 } else {
7902                                         if (vtable_is_32bit)
7903                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7904                                         else
7905                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7906 #ifdef __native_client_codegen__
7907                                         item->chunk_size += JUMP_MEMBASE_SIZE;
7908 #endif
7909                                 }
7910                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7911                         } else {
7912                                 if (fail_tramp) {
7913                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7914                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7915                                 } else {
7916                                         if (vtable_is_32bit)
7917                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7918                                         else
7919                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7920                                         item->chunk_size += JUMP_REG_SIZE;
7921                                         /* with assert below:
7922                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7923                                          */
7924 #ifdef __native_client_codegen__
7925                                         item->chunk_size += JUMP_MEMBASE_SIZE;
7926 #endif
7927                                 }
7928                         }
7929                 } else {
7930                         if (amd64_is_imm32 (item->key))
7931                                 item->chunk_size += CMP_SIZE;
7932                         else
7933                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7934                         item->chunk_size += BR_LARGE_SIZE;
7935                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7936                 }
7937                 size += item->chunk_size;
7938         }
7939 #if defined(__native_client__) && defined(__native_client_codegen__)
7940         /* In Native Client, we don't re-use thunks, allocate from the */
7941         /* normal code manager paths. */
7942         code = mono_domain_code_reserve (domain, size);
7943 #else
7944         if (fail_tramp)
7945                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7946         else
7947                 code = mono_domain_code_reserve (domain, size);
7948 #endif
7949         start = code;
7950         for (i = 0; i < count; ++i) {
7951                 MonoIMTCheckItem *item = imt_entries [i];
7952                 item->code_target = code;
7953                 if (item->is_equals) {
7954                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7955
7956                         if (item->check_target_idx || fail_case) {
7957                                 if (!item->compare_done || fail_case) {
7958                                         if (amd64_is_imm32 (item->key))
7959                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7960                                         else {
7961                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7962                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7963                                         }
7964                                 }
7965                                 item->jmp_code = code;
7966                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7967                                 if (item->has_target_code) {
7968                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7969                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7970                                 } else {
7971                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7972                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7973                                 }
7974
7975                                 if (fail_case) {
7976                                         amd64_patch (item->jmp_code, code);
7977                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7978                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7979                                         item->jmp_code = NULL;
7980                                 }
7981                         } else {
7982                                 /* enable the commented code to assert on wrong method */
7983 #if 0
7984                                 if (amd64_is_imm32 (item->key))
7985                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7986                                 else {
7987                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7988                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7989                                 }
7990                                 item->jmp_code = code;
7991                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7992                                 /* See the comment below about R10 */
7993                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7994                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7995                                 amd64_patch (item->jmp_code, code);
7996                                 amd64_breakpoint (code);
7997                                 item->jmp_code = NULL;
7998 #else
7999                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8000                                    needs to be preserved.  R10 needs
8001                                    to be preserved for calls which
8002                                    require a runtime generic context,
8003                                    but interface calls don't. */
8004                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8005                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8006 #endif
8007                         }
8008                 } else {
8009                         if (amd64_is_imm32 (item->key))
8010                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8011                         else {
8012                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8013                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8014                         }
8015                         item->jmp_code = code;
8016                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8017                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8018                         else
8019                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8020                 }
8021                 g_assert (code - item->code_target <= item->chunk_size);
8022         }
8023         /* patch the branches to get to the target items */
8024         for (i = 0; i < count; ++i) {
8025                 MonoIMTCheckItem *item = imt_entries [i];
8026                 if (item->jmp_code) {
8027                         if (item->check_target_idx) {
8028                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8029                         }
8030                 }
8031         }
8032
8033         if (!fail_tramp)
8034                 mono_stats.imt_thunks_size += code - start;
8035         g_assert (code - start <= size);
8036
8037         nacl_domain_code_validate(domain, &start, size, &code);
8038
8039         return start;
8040 }
8041
8042 MonoMethod*
8043 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8044 {
8045         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8046 }
8047
8048 MonoVTable*
8049 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8050 {
8051         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8052 }
8053
8054 GSList*
8055 mono_arch_get_cie_program (void)
8056 {
8057         GSList *l = NULL;
8058
8059         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8060         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8061
8062         return l;
8063 }
8064
8065 MonoInst*
8066 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8067 {
8068         MonoInst *ins = NULL;
8069         int opcode = 0;
8070
8071         if (cmethod->klass == mono_defaults.math_class) {
8072                 if (strcmp (cmethod->name, "Sin") == 0) {
8073                         opcode = OP_SIN;
8074                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8075                         opcode = OP_COS;
8076                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8077                         opcode = OP_SQRT;
8078                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8079                         opcode = OP_ABS;
8080                 }
8081
8082                 if (opcode) {
8083                         MONO_INST_NEW (cfg, ins, opcode);
8084                         ins->type = STACK_R8;
8085                         ins->dreg = mono_alloc_freg (cfg);
8086                         ins->sreg1 = args [0]->dreg;
8087                         MONO_ADD_INS (cfg->cbb, ins);
8088                 }
8089
8090                 opcode = 0;
8091                 if (cfg->opt & MONO_OPT_CMOV) {
8092                         if (strcmp (cmethod->name, "Min") == 0) {
8093                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8094                                         opcode = OP_IMIN;
8095                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8096                                         opcode = OP_IMIN_UN;
8097                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8098                                         opcode = OP_LMIN;
8099                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8100                                         opcode = OP_LMIN_UN;
8101                         } else if (strcmp (cmethod->name, "Max") == 0) {
8102                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8103                                         opcode = OP_IMAX;
8104                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8105                                         opcode = OP_IMAX_UN;
8106                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8107                                         opcode = OP_LMAX;
8108                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8109                                         opcode = OP_LMAX_UN;
8110                         }
8111                 }
8112
8113                 if (opcode) {
8114                         MONO_INST_NEW (cfg, ins, opcode);
8115                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8116                         ins->dreg = mono_alloc_ireg (cfg);
8117                         ins->sreg1 = args [0]->dreg;
8118                         ins->sreg2 = args [1]->dreg;
8119                         MONO_ADD_INS (cfg->cbb, ins);
8120                 }
8121
8122 #if 0
8123                 /* OP_FREM is not IEEE compatible */
8124                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8125                         MONO_INST_NEW (cfg, ins, OP_FREM);
8126                         ins->inst_i0 = args [0];
8127                         ins->inst_i1 = args [1];
8128                 }
8129 #endif
8130         }
8131
8132         /*
8133          * Can't implement CompareExchange methods this way since they have
8134          * three arguments.
8135          */
8136
8137         return ins;
8138 }
8139
8140 gboolean
8141 mono_arch_print_tree (MonoInst *tree, int arity)
8142 {
8143         return 0;
8144 }
8145
8146 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8147
8148 mgreg_t
8149 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8150 {
8151         switch (reg) {
8152         case AMD64_RCX: return ctx->rcx;
8153         case AMD64_RDX: return ctx->rdx;
8154         case AMD64_RBX: return ctx->rbx;
8155         case AMD64_RBP: return ctx->rbp;
8156         case AMD64_RSP: return ctx->rsp;
8157         default:
8158                 return _CTX_REG (ctx, rax, reg);
8159         }
8160 }
8161
8162 void
8163 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8164 {
8165         switch (reg) {
8166         case AMD64_RCX:
8167                 ctx->rcx = val;
8168                 break;
8169         case AMD64_RDX:
8170                 ctx->rdx = val;
8171                 break;
8172         case AMD64_RBX:
8173                 ctx->rbx = val;
8174                 break;
8175         case AMD64_RBP:
8176                 ctx->rbp = val;
8177                 break;
8178         case AMD64_RSP:
8179                 ctx->rsp = val;
8180                 break;
8181         default:
8182                 _CTX_REG (ctx, rax, reg) = val;
8183         }
8184 }
8185
8186 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8187 gpointer
8188 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8189 {
8190         int offset;
8191         gpointer *sp, old_value;
8192         char *bp;
8193         const unsigned char *handler;
8194
8195         /*Decode the first instruction to figure out where did we store the spvar*/
8196         /*Our jit MUST generate the following:
8197          mov    %rsp, ?(%rbp)
8198
8199          Which is encoded as: REX.W 0x89 mod_rm
8200          mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8201                 mod (reg + imm8):  01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8202                 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8203
8204         FIXME can we generate frameless methods on this case?
8205
8206         */
8207         handler = clause->handler_start;
8208
8209         /*REX.W*/
8210         if (*handler != 0x48)
8211                 return NULL;
8212         ++handler;
8213
8214         /*mov r, r/m */
8215         if (*handler != 0x89)
8216                 return NULL;
8217         ++handler;
8218
8219         if (*handler == 0x65)
8220                 offset = *(signed char*)(handler + 1);
8221         else if (*handler == 0xA5)
8222                 offset = *(int*)(handler + 1);
8223         else
8224                 return NULL;
8225
8226         /*Load the spvar*/
8227         bp = MONO_CONTEXT_GET_BP (ctx);
8228         sp = *(gpointer*)(bp + offset);
8229
8230         old_value = *sp;
8231         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8232                 return old_value;
8233
8234         *sp = new_value;
8235
8236         return old_value;
8237 }
8238
8239 /*
8240  * mono_arch_emit_load_aotconst:
8241  *
8242  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8243  * TARGET from the mscorlib GOT in full-aot code.
8244  * On AMD64, the result is placed into R11.
8245  */
8246 guint8*
8247 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8248 {
8249         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8250         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8251
8252         return code;
8253 }
8254
8255 /*
8256  * mono_arch_get_trampolines:
8257  *
8258  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8259  * for AOT.
8260  */
8261 GSList *
8262 mono_arch_get_trampolines (gboolean aot)
8263 {
8264         return mono_amd64_get_exception_trampolines (aot);
8265 }
8266
8267 /* Soft Debug support */
8268 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8269
8270 /*
8271  * mono_arch_set_breakpoint:
8272  *
8273  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8274  * The location should contain code emitted by OP_SEQ_POINT.
8275  */
8276 void
8277 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8278 {
8279         guint8 *code = ip;
8280         guint8 *orig_code = code;
8281
8282         if (ji->from_aot) {
8283                 guint32 native_offset = ip - (guint8*)ji->code_start;
8284                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8285
8286                 g_assert (info->bp_addrs [native_offset] == 0);
8287                 info->bp_addrs [native_offset] = bp_trigger_page;
8288         } else {
8289                 /*
8290                  * In production, we will use int3 (has to fix the size in the md
8291                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8292                  * instead.
8293                  */
8294                 g_assert (code [0] == 0x90);
8295                 if (breakpoint_size == 8) {
8296                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8297                 } else {
8298                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8299                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8300                 }
8301
8302                 g_assert (code - orig_code == breakpoint_size);
8303         }
8304 }
8305
8306 /*
8307  * mono_arch_clear_breakpoint:
8308  *
8309  *   Clear the breakpoint at IP.
8310  */
8311 void
8312 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8313 {
8314         guint8 *code = ip;
8315         int i;
8316
8317         if (ji->from_aot) {
8318                 guint32 native_offset = ip - (guint8*)ji->code_start;
8319                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8320
8321                 g_assert (info->bp_addrs [native_offset] == 0);
8322                 info->bp_addrs [native_offset] = info;
8323         } else {
8324                 for (i = 0; i < breakpoint_size; ++i)
8325                         x86_nop (code);
8326         }
8327 }
8328
8329 gboolean
8330 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8331 {
8332 #ifdef HOST_WIN32
8333         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8334         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8335                 return TRUE;
8336         else
8337                 return FALSE;
8338 #else
8339         siginfo_t* sinfo = (siginfo_t*) info;
8340         /* Sometimes the address is off by 4 */
8341         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8342                 return TRUE;
8343         else
8344                 return FALSE;
8345 #endif
8346 }
8347
8348 /*
8349  * mono_arch_skip_breakpoint:
8350  *
8351  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8352  * we resume, the instruction is not executed again.
8353  */
8354 void
8355 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8356 {
8357         if (ji->from_aot) {
8358                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8359                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8360         } else {
8361                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8362         }
8363 }
8364
8365 /*
8366  * mono_arch_start_single_stepping:
8367  *
8368  *   Start single stepping.
8369  */
8370 void
8371 mono_arch_start_single_stepping (void)
8372 {
8373         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8374 }
8375
8376 /*
8377  * mono_arch_stop_single_stepping:
8378  *
8379  *   Stop single stepping.
8380  */
8381 void
8382 mono_arch_stop_single_stepping (void)
8383 {
8384         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8385 }
8386
8387 /*
8388  * mono_arch_is_single_step_event:
8389  *
8390  *   Return whenever the machine state in SIGCTX corresponds to a single
8391  * step event.
8392  */
8393 gboolean
8394 mono_arch_is_single_step_event (void *info, void *sigctx)
8395 {
8396 #ifdef HOST_WIN32
8397         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8398         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8399                 return TRUE;
8400         else
8401                 return FALSE;
8402 #else
8403         siginfo_t* sinfo = (siginfo_t*) info;
8404         /* Sometimes the address is off by 4 */
8405         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8406                 return TRUE;
8407         else
8408                 return FALSE;
8409 #endif
8410 }
8411
8412 /*
8413  * mono_arch_skip_single_step:
8414  *
8415  *   Modify CTX so the ip is placed after the single step trigger instruction,
8416  * we resume, the instruction is not executed again.
8417  */
8418 void
8419 mono_arch_skip_single_step (MonoContext *ctx)
8420 {
8421         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8422 }
8423
8424 /*
8425  * mono_arch_create_seq_point_info:
8426  *
8427  *   Return a pointer to a data structure which is used by the sequence
8428  * point implementation in AOTed code.
8429  */
8430 gpointer
8431 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8432 {
8433         SeqPointInfo *info;
8434         MonoJitInfo *ji;
8435         int i;
8436
8437         // FIXME: Add a free function
8438
8439         mono_domain_lock (domain);
8440         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8441                                                                 code);
8442         mono_domain_unlock (domain);
8443
8444         if (!info) {
8445                 ji = mono_jit_info_table_find (domain, (char*)code);
8446                 g_assert (ji);
8447
8448                 // FIXME: Optimize the size
8449                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8450
8451                 info->ss_trigger_page = ss_trigger_page;
8452                 info->bp_trigger_page = bp_trigger_page;
8453                 /* Initialize to a valid address */
8454                 for (i = 0; i < ji->code_size; ++i)
8455                         info->bp_addrs [i] = info;
8456
8457                 mono_domain_lock (domain);
8458                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8459                                                          code, info);
8460                 mono_domain_unlock (domain);
8461         }
8462
8463         return info;
8464 }
8465
8466 void
8467 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8468 {
8469         ext->lmf.previous_lmf = prev_lmf;
8470         /* Mark that this is a MonoLMFExt */
8471         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8472         ext->lmf.rsp = (gssize)ext;
8473 }
8474
8475 #endif
8476
8477 gboolean
8478 mono_arch_opcode_supported (int opcode)
8479 {
8480         switch (opcode) {
8481         case OP_ATOMIC_ADD_I4:
8482         case OP_ATOMIC_ADD_I8:
8483         case OP_ATOMIC_EXCHANGE_I4:
8484         case OP_ATOMIC_EXCHANGE_I8:
8485         case OP_ATOMIC_CAS_I4:
8486         case OP_ATOMIC_CAS_I8:
8487                 return TRUE;
8488         default:
8489                 return FALSE;
8490         }
8491 }