2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/abi-details.h>
24 #include <mono/metadata/appdomain.h>
25 #include <mono/metadata/debug-helpers.h>
26 #include <mono/metadata/threads.h>
27 #include <mono/metadata/profiler-private.h>
28 #include <mono/metadata/mono-debug.h>
29 #include <mono/metadata/gc-internal.h>
30 #include <mono/utils/mono-math.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-tls.h>
34 #include <mono/utils/mono-hwcap-x86.h>
38 #include "mini-amd64.h"
39 #include "cpu-amd64.h"
40 #include "debugger-agent.h"
44 static gboolean optimize_for_xen = TRUE;
46 #define optimize_for_xen 0
49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
56 /* Under windows, the calling convention is never stdcall */
57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
62 /* This mutex protects architecture specific caches */
63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
65 static mono_mutex_t mini_arch_mutex;
68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
71 * The code generated for sequence points reads from this location, which is
72 * made read-only when single stepping is enabled.
74 static gpointer ss_trigger_page;
76 /* Enabled breakpoints read from this trigger page */
77 static gpointer bp_trigger_page;
79 /* The size of the breakpoint sequence */
80 static int breakpoint_size;
82 /* The size of the breakpoint instruction causing the actual fault */
83 static int breakpoint_fault_size;
85 /* The size of the single step instruction causing the actual fault */
86 static int single_step_fault_size;
89 /* On Win64 always reserve first 32 bytes for first four arguments */
90 #define ARGS_OFFSET 48
92 #define ARGS_OFFSET 16
94 #define GP_SCRATCH_REG AMD64_R11
97 * AMD64 register usage:
98 * - callee saved registers are used for global register allocation
99 * - %r11 is used for materializing 64 bit constants in opcodes
100 * - the rest is used for local allocation
104 * Floating point comparison results:
114 mono_arch_regname (int reg)
117 case AMD64_RAX: return "%rax";
118 case AMD64_RBX: return "%rbx";
119 case AMD64_RCX: return "%rcx";
120 case AMD64_RDX: return "%rdx";
121 case AMD64_RSP: return "%rsp";
122 case AMD64_RBP: return "%rbp";
123 case AMD64_RDI: return "%rdi";
124 case AMD64_RSI: return "%rsi";
125 case AMD64_R8: return "%r8";
126 case AMD64_R9: return "%r9";
127 case AMD64_R10: return "%r10";
128 case AMD64_R11: return "%r11";
129 case AMD64_R12: return "%r12";
130 case AMD64_R13: return "%r13";
131 case AMD64_R14: return "%r14";
132 case AMD64_R15: return "%r15";
137 static const char * packed_xmmregs [] = {
138 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
139 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
142 static const char * single_xmmregs [] = {
143 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
144 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
148 mono_arch_fregname (int reg)
150 if (reg < AMD64_XMM_NREG)
151 return single_xmmregs [reg];
157 mono_arch_xregname (int reg)
159 if (reg < AMD64_XMM_NREG)
160 return packed_xmmregs [reg];
169 return mono_debug_count ();
175 static inline gboolean
176 amd64_is_near_call (guint8 *code)
179 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
182 return code [0] == 0xe8;
185 #ifdef __native_client_codegen__
187 /* Keep track of instruction "depth", that is, the level of sub-instruction */
188 /* for any given instruction. For instance, amd64_call_reg resolves to */
189 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
190 /* We only want to force bundle alignment for the top level instruction, */
191 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
192 static MonoNativeTlsKey nacl_instruction_depth;
194 static MonoNativeTlsKey nacl_rex_tag;
195 static MonoNativeTlsKey nacl_legacy_prefix_tag;
198 amd64_nacl_clear_legacy_prefix_tag ()
200 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
204 amd64_nacl_tag_legacy_prefix (guint8* code)
206 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
207 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
211 amd64_nacl_tag_rex (guint8* code)
213 mono_native_tls_set_value (nacl_rex_tag, code);
217 amd64_nacl_get_legacy_prefix_tag ()
219 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
223 amd64_nacl_get_rex_tag ()
225 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
228 /* Increment the instruction "depth" described above */
230 amd64_nacl_instruction_pre ()
232 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
234 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
237 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
238 /* alignment if depth == 0 (top level instruction) */
239 /* IN: start, end pointers to instruction beginning and end */
240 /* OUT: start, end pointers to beginning and end after possible alignment */
241 /* GLOBALS: nacl_instruction_depth defined above */
243 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
245 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
247 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
249 g_assert ( depth >= 0 );
251 uintptr_t space_in_block;
253 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
254 /* if legacy prefix is present, and if it was emitted before */
255 /* the start of the instruction sequence, adjust the start */
256 if (prefix != NULL && prefix < *start) {
257 g_assert (*start - prefix <= 3);/* only 3 are allowed */
260 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
261 instlen = (uintptr_t)(*end - *start);
262 /* Only check for instructions which are less than */
263 /* kNaClAlignment. The only instructions that should ever */
264 /* be that long are call sequences, which are already */
265 /* padded out to align the return to the next bundle. */
266 if (instlen > space_in_block && instlen < kNaClAlignment) {
267 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
268 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
269 const size_t length = (size_t)((*end)-(*start));
270 g_assert (length < MAX_NACL_INST_LENGTH);
272 memcpy (copy_of_instruction, *start, length);
273 *start = mono_arch_nacl_pad (*start, space_in_block);
274 memcpy (*start, copy_of_instruction, length);
275 *end = *start + length;
277 amd64_nacl_clear_legacy_prefix_tag ();
278 amd64_nacl_tag_rex (NULL);
282 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
283 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
284 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
285 /* make sure the upper 32-bits are cleared, and use that register in the */
286 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
288 /* pointer to current instruction stream (in the */
289 /* middle of an instruction, after opcode is emitted) */
290 /* basereg/offset/dreg */
291 /* operands of normal membase address */
293 /* pointer to the end of the membase/memindex emit */
294 /* GLOBALS: nacl_rex_tag */
295 /* position in instruction stream that rex prefix was emitted */
296 /* nacl_legacy_prefix_tag */
297 /* (possibly NULL) position in instruction of legacy x86 prefix */
299 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
301 gint8 true_basereg = basereg;
303 /* Cache these values, they might change */
304 /* as new instructions are emitted below. */
305 guint8* rex_tag = amd64_nacl_get_rex_tag ();
306 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
308 /* 'basereg' is given masked to 0x7 at this point, so check */
309 /* the rex prefix to see if this is an extended register. */
310 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
314 #define X86_LEA_OPCODE (0x8D)
316 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
317 guint8* old_instruction_start;
319 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
320 /* 32-bits of the old base register (new index register) */
322 guint8* buf_ptr = buf;
325 g_assert (rex_tag != NULL);
327 if (IS_REX(*rex_tag)) {
328 /* The old rex.B should be the new rex.X */
329 if (*rex_tag & AMD64_REX_B) {
330 *rex_tag |= AMD64_REX_X;
332 /* Since our new base is %r15 set rex.B */
333 *rex_tag |= AMD64_REX_B;
335 /* Shift the instruction by one byte */
336 /* so we can insert a rex prefix */
337 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
339 /* New rex prefix only needs rex.B for %r15 base */
340 *rex_tag = AMD64_REX(AMD64_REX_B);
343 if (legacy_prefix_tag) {
344 old_instruction_start = legacy_prefix_tag;
346 old_instruction_start = rex_tag;
349 /* Clears the upper 32-bits of the previous base register */
350 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
351 insert_len = buf_ptr - buf;
353 /* Move the old instruction forward to make */
354 /* room for 'mov' stored in 'buf_ptr' */
355 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
357 memcpy (old_instruction_start, buf, insert_len);
359 /* Sandboxed replacement for the normal membase_emit */
360 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
363 /* Normal default behavior, emit membase memory location */
364 x86_membase_emit_body (*code, dreg, basereg, offset);
369 static inline unsigned char*
370 amd64_skip_nops (unsigned char* code)
375 if ( code[0] == 0x90) {
379 if ( code[0] == 0x66 && code[1] == 0x90) {
383 if (code[0] == 0x0f && code[1] == 0x1f
384 && code[2] == 0x00) {
388 if (code[0] == 0x0f && code[1] == 0x1f
389 && code[2] == 0x40 && code[3] == 0x00) {
393 if (code[0] == 0x0f && code[1] == 0x1f
394 && code[2] == 0x44 && code[3] == 0x00
395 && code[4] == 0x00) {
399 if (code[0] == 0x66 && code[1] == 0x0f
400 && code[2] == 0x1f && code[3] == 0x44
401 && code[4] == 0x00 && code[5] == 0x00) {
405 if (code[0] == 0x0f && code[1] == 0x1f
406 && code[2] == 0x80 && code[3] == 0x00
407 && code[4] == 0x00 && code[5] == 0x00
408 && code[6] == 0x00) {
412 if (code[0] == 0x0f && code[1] == 0x1f
413 && code[2] == 0x84 && code[3] == 0x00
414 && code[4] == 0x00 && code[5] == 0x00
415 && code[6] == 0x00 && code[7] == 0x00) {
424 mono_arch_nacl_skip_nops (guint8* code)
426 return amd64_skip_nops(code);
429 #endif /*__native_client_codegen__*/
432 amd64_patch (unsigned char* code, gpointer target)
436 #ifdef __native_client_codegen__
437 code = amd64_skip_nops (code);
439 #if defined(__native_client_codegen__) && defined(__native_client__)
440 if (nacl_is_code_address (code)) {
441 /* For tail calls, code is patched after being installed */
442 /* but not through the normal "patch callsite" method. */
443 unsigned char buf[kNaClAlignment];
444 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
446 memcpy (buf, aligned_code, kNaClAlignment);
447 /* Patch a temp buffer of bundle size, */
448 /* then install to actual location. */
449 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
450 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
454 target = nacl_modify_patch_target (target);
458 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
463 if ((code [0] & 0xf8) == 0xb8) {
464 /* amd64_set_reg_template */
465 *(guint64*)(code + 1) = (guint64)target;
467 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
468 /* mov 0(%rip), %dreg */
469 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
471 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
472 /* call *<OFFSET>(%rip) */
473 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
475 else if (code [0] == 0xe8) {
477 gint64 disp = (guint8*)target - (guint8*)code;
478 g_assert (amd64_is_imm32 (disp));
479 x86_patch (code, (unsigned char*)target);
482 x86_patch (code, (unsigned char*)target);
486 mono_amd64_patch (unsigned char* code, gpointer target)
488 amd64_patch (code, target);
497 ArgValuetypeAddrInIReg,
498 ArgNone /* only in pair_storage */
506 /* Only if storage == ArgValuetypeInReg */
507 ArgStorage pair_storage [2];
517 gboolean need_stack_align;
518 gboolean vtype_retaddr;
519 /* The index of the vret arg in the argument list */
526 #define DEBUG(a) if (cfg->verbose_level > 1) a
529 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
531 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
533 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
535 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
539 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
541 ainfo->offset = *stack_size;
543 if (*gr >= PARAM_REGS) {
544 ainfo->storage = ArgOnStack;
545 /* Since the same stack slot size is used for all arg */
546 /* types, it needs to be big enough to hold them all */
547 (*stack_size) += sizeof(mgreg_t);
550 ainfo->storage = ArgInIReg;
551 ainfo->reg = param_regs [*gr];
557 #define FLOAT_PARAM_REGS 4
559 #define FLOAT_PARAM_REGS 8
563 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
565 ainfo->offset = *stack_size;
567 if (*gr >= FLOAT_PARAM_REGS) {
568 ainfo->storage = ArgOnStack;
569 /* Since the same stack slot size is used for both float */
570 /* types, it needs to be big enough to hold them both */
571 (*stack_size) += sizeof(mgreg_t);
574 /* A double register */
576 ainfo->storage = ArgInDoubleSSEReg;
578 ainfo->storage = ArgInFloatSSEReg;
584 typedef enum ArgumentClass {
592 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
594 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
597 ptype = mini_type_get_underlying_type (gsctx, type);
598 switch (ptype->type) {
599 case MONO_TYPE_BOOLEAN:
609 case MONO_TYPE_STRING:
610 case MONO_TYPE_OBJECT:
611 case MONO_TYPE_CLASS:
612 case MONO_TYPE_SZARRAY:
614 case MONO_TYPE_FNPTR:
615 case MONO_TYPE_ARRAY:
618 class2 = ARG_CLASS_INTEGER;
623 class2 = ARG_CLASS_INTEGER;
625 class2 = ARG_CLASS_SSE;
629 case MONO_TYPE_TYPEDBYREF:
630 g_assert_not_reached ();
632 case MONO_TYPE_GENERICINST:
633 if (!mono_type_generic_inst_is_valuetype (ptype)) {
634 class2 = ARG_CLASS_INTEGER;
638 case MONO_TYPE_VALUETYPE: {
639 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
642 for (i = 0; i < info->num_fields; ++i) {
644 class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
649 g_assert_not_reached ();
653 if (class1 == class2)
655 else if (class1 == ARG_CLASS_NO_CLASS)
657 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
658 class1 = ARG_CLASS_MEMORY;
659 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
660 class1 = ARG_CLASS_INTEGER;
662 class1 = ARG_CLASS_SSE;
666 #ifdef __native_client_codegen__
668 /* Default alignment for Native Client is 32-byte. */
669 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
671 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
672 /* Check that alignment doesn't cross an alignment boundary. */
674 mono_arch_nacl_pad(guint8 *code, int pad)
676 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
678 if (pad == 0) return code;
679 /* assertion: alignment cannot cross a block boundary */
680 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
681 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
682 while (pad >= kMaxPadding) {
683 amd64_padding (code, kMaxPadding);
686 if (pad != 0) amd64_padding (code, pad);
692 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
694 guint32 *gr, guint32 *fr, guint32 *stack_size)
696 guint32 size, quad, nquads, i;
697 /* Keep track of the size used in each quad so we can */
698 /* use the right size when copying args/return vars. */
699 guint32 quadsize [2] = {8, 8};
700 ArgumentClass args [2];
701 MonoMarshalType *info = NULL;
703 MonoGenericSharingContext tmp_gsctx;
704 gboolean pass_on_stack = FALSE;
707 * The gsctx currently contains no data, it is only used for checking whenever
708 * open types are allowed, some callers like mono_arch_get_argument_info ()
709 * don't pass it to us, so work around that.
714 klass = mono_class_from_mono_type (type);
715 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
717 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
718 /* We pass and return vtypes of size 8 in a register */
719 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
720 pass_on_stack = TRUE;
724 pass_on_stack = TRUE;
728 /* If this struct can't be split up naturally into 8-byte */
729 /* chunks (registers), pass it on the stack. */
730 if (sig->pinvoke && !pass_on_stack) {
734 info = mono_marshal_load_type_info (klass);
736 for (i = 0; i < info->num_fields; ++i) {
737 field_size = mono_marshal_type_size (info->fields [i].field->type,
738 info->fields [i].mspec,
739 &align, TRUE, klass->unicode);
740 if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
741 pass_on_stack = TRUE;
748 /* Allways pass in memory */
749 ainfo->offset = *stack_size;
750 *stack_size += ALIGN_TO (size, 8);
751 ainfo->storage = ArgOnStack;
756 /* FIXME: Handle structs smaller than 8 bytes */
757 //if ((size % 8) != 0)
766 /* Always pass in 1 or 2 integer registers */
767 args [0] = ARG_CLASS_INTEGER;
768 args [1] = ARG_CLASS_INTEGER;
769 /* Only the simplest cases are supported */
770 if (is_return && nquads != 1) {
771 args [0] = ARG_CLASS_MEMORY;
772 args [1] = ARG_CLASS_MEMORY;
776 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
777 * The X87 and SSEUP stuff is left out since there are no such types in
780 info = mono_marshal_load_type_info (klass);
784 if (info->native_size > 16) {
785 ainfo->offset = *stack_size;
786 *stack_size += ALIGN_TO (info->native_size, 8);
787 ainfo->storage = ArgOnStack;
792 switch (info->native_size) {
793 case 1: case 2: case 4: case 8:
797 ainfo->storage = ArgOnStack;
798 ainfo->offset = *stack_size;
799 *stack_size += ALIGN_TO (info->native_size, 8);
802 ainfo->storage = ArgValuetypeAddrInIReg;
804 if (*gr < PARAM_REGS) {
805 ainfo->pair_storage [0] = ArgInIReg;
806 ainfo->pair_regs [0] = param_regs [*gr];
810 ainfo->pair_storage [0] = ArgOnStack;
811 ainfo->offset = *stack_size;
820 args [0] = ARG_CLASS_NO_CLASS;
821 args [1] = ARG_CLASS_NO_CLASS;
822 for (quad = 0; quad < nquads; ++quad) {
825 ArgumentClass class1;
827 if (info->num_fields == 0)
828 class1 = ARG_CLASS_MEMORY;
830 class1 = ARG_CLASS_NO_CLASS;
831 for (i = 0; i < info->num_fields; ++i) {
832 size = mono_marshal_type_size (info->fields [i].field->type,
833 info->fields [i].mspec,
834 &align, TRUE, klass->unicode);
835 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
836 /* Unaligned field */
840 /* Skip fields in other quad */
841 if ((quad == 0) && (info->fields [i].offset >= 8))
843 if ((quad == 1) && (info->fields [i].offset < 8))
846 /* How far into this quad this data extends.*/
847 /* (8 is size of quad) */
848 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
850 class1 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class1);
852 g_assert (class1 != ARG_CLASS_NO_CLASS);
853 args [quad] = class1;
857 /* Post merger cleanup */
858 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
859 args [0] = args [1] = ARG_CLASS_MEMORY;
861 /* Allocate registers */
866 ainfo->storage = ArgValuetypeInReg;
867 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
868 ainfo->nregs = nquads;
869 for (quad = 0; quad < nquads; ++quad) {
870 switch (args [quad]) {
871 case ARG_CLASS_INTEGER:
872 if (*gr >= PARAM_REGS)
873 args [quad] = ARG_CLASS_MEMORY;
875 ainfo->pair_storage [quad] = ArgInIReg;
877 ainfo->pair_regs [quad] = return_regs [*gr];
879 ainfo->pair_regs [quad] = param_regs [*gr];
884 if (*fr >= FLOAT_PARAM_REGS)
885 args [quad] = ARG_CLASS_MEMORY;
887 if (quadsize[quad] <= 4)
888 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
889 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
890 ainfo->pair_regs [quad] = *fr;
894 case ARG_CLASS_MEMORY:
897 g_assert_not_reached ();
901 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
902 /* Revert possible register assignments */
906 ainfo->offset = *stack_size;
908 *stack_size += ALIGN_TO (info->native_size, 8);
910 *stack_size += nquads * sizeof(mgreg_t);
911 ainfo->storage = ArgOnStack;
919 * Obtain information about a call according to the calling convention.
920 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
921 * Draft Version 0.23" document for more information.
924 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
926 guint32 i, gr, fr, pstart;
928 int n = sig->hasthis + sig->param_count;
929 guint32 stack_size = 0;
931 gboolean is_pinvoke = sig->pinvoke;
934 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
936 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
945 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
946 switch (ret_type->type) {
947 case MONO_TYPE_BOOLEAN:
958 case MONO_TYPE_FNPTR:
959 case MONO_TYPE_CLASS:
960 case MONO_TYPE_OBJECT:
961 case MONO_TYPE_SZARRAY:
962 case MONO_TYPE_ARRAY:
963 case MONO_TYPE_STRING:
964 cinfo->ret.storage = ArgInIReg;
965 cinfo->ret.reg = AMD64_RAX;
969 cinfo->ret.storage = ArgInIReg;
970 cinfo->ret.reg = AMD64_RAX;
973 cinfo->ret.storage = ArgInFloatSSEReg;
974 cinfo->ret.reg = AMD64_XMM0;
977 cinfo->ret.storage = ArgInDoubleSSEReg;
978 cinfo->ret.reg = AMD64_XMM0;
980 case MONO_TYPE_GENERICINST:
981 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
982 cinfo->ret.storage = ArgInIReg;
983 cinfo->ret.reg = AMD64_RAX;
987 #if defined( __native_client_codegen__ )
988 case MONO_TYPE_TYPEDBYREF:
990 case MONO_TYPE_VALUETYPE: {
991 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
993 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
994 if (cinfo->ret.storage == ArgOnStack) {
995 cinfo->vtype_retaddr = TRUE;
996 /* The caller passes the address where the value is stored */
1000 #if !defined( __native_client_codegen__ )
1001 case MONO_TYPE_TYPEDBYREF:
1002 /* Same as a valuetype with size 24 */
1003 cinfo->vtype_retaddr = TRUE;
1006 case MONO_TYPE_VOID:
1009 g_error ("Can't handle as return value 0x%x", ret_type->type);
1015 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1016 * the first argument, allowing 'this' to be always passed in the first arg reg.
1017 * Also do this if the first argument is a reference type, since virtual calls
1018 * are sometimes made using calli without sig->hasthis set, like in the delegate
1021 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1023 add_general (&gr, &stack_size, cinfo->args + 0);
1025 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1028 add_general (&gr, &stack_size, &cinfo->ret);
1029 cinfo->vret_arg_index = 1;
1033 add_general (&gr, &stack_size, cinfo->args + 0);
1035 if (cinfo->vtype_retaddr)
1036 add_general (&gr, &stack_size, &cinfo->ret);
1039 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1041 fr = FLOAT_PARAM_REGS;
1043 /* Emit the signature cookie just before the implicit arguments */
1044 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1047 for (i = pstart; i < sig->param_count; ++i) {
1048 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1052 /* The float param registers and other param registers must be the same index on Windows x64.*/
1059 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1060 /* We allways pass the sig cookie on the stack for simplicity */
1062 * Prevent implicit arguments + the sig cookie from being passed
1066 fr = FLOAT_PARAM_REGS;
1068 /* Emit the signature cookie just before the implicit arguments */
1069 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1072 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1073 switch (ptype->type) {
1074 case MONO_TYPE_BOOLEAN:
1077 add_general (&gr, &stack_size, ainfo);
1081 case MONO_TYPE_CHAR:
1082 add_general (&gr, &stack_size, ainfo);
1086 add_general (&gr, &stack_size, ainfo);
1091 case MONO_TYPE_FNPTR:
1092 case MONO_TYPE_CLASS:
1093 case MONO_TYPE_OBJECT:
1094 case MONO_TYPE_STRING:
1095 case MONO_TYPE_SZARRAY:
1096 case MONO_TYPE_ARRAY:
1097 add_general (&gr, &stack_size, ainfo);
1099 case MONO_TYPE_GENERICINST:
1100 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1101 add_general (&gr, &stack_size, ainfo);
1105 case MONO_TYPE_VALUETYPE:
1106 case MONO_TYPE_TYPEDBYREF:
1107 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1111 add_general (&gr, &stack_size, ainfo);
1114 add_float (&fr, &stack_size, ainfo, FALSE);
1117 add_float (&fr, &stack_size, ainfo, TRUE);
1120 g_assert_not_reached ();
1124 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1126 fr = FLOAT_PARAM_REGS;
1128 /* Emit the signature cookie just before the implicit arguments */
1129 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1133 // There always is 32 bytes reserved on the stack when calling on Winx64
1137 #ifndef MONO_AMD64_NO_PUSHES
1138 if (stack_size & 0x8) {
1139 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1140 cinfo->need_stack_align = TRUE;
1145 cinfo->stack_usage = stack_size;
1146 cinfo->reg_usage = gr;
1147 cinfo->freg_usage = fr;
1152 * mono_arch_get_argument_info:
1153 * @csig: a method signature
1154 * @param_count: the number of parameters to consider
1155 * @arg_info: an array to store the result infos
1157 * Gathers information on parameters such as size, alignment and
1158 * padding. arg_info should be large enought to hold param_count + 1 entries.
1160 * Returns the size of the argument area on the stack.
1163 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1166 CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1167 guint32 args_size = cinfo->stack_usage;
1169 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1170 if (csig->hasthis) {
1171 arg_info [0].offset = 0;
1174 for (k = 0; k < param_count; k++) {
1175 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1177 arg_info [k + 1].size = 0;
1186 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1190 MonoType *callee_ret;
1192 c1 = get_call_info (NULL, NULL, caller_sig);
1193 c2 = get_call_info (NULL, NULL, callee_sig);
1194 res = c1->stack_usage >= c2->stack_usage;
1195 callee_ret = mini_replace_type (callee_sig->ret);
1196 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1197 /* An address on the callee's stack is passed as the first argument */
1207 * Initialize the cpu to execute managed code.
1210 mono_arch_cpu_init (void)
1215 /* spec compliance requires running with double precision */
1216 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1217 fpcw &= ~X86_FPCW_PRECC_MASK;
1218 fpcw |= X86_FPCW_PREC_DOUBLE;
1219 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1220 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1222 /* TODO: This is crashing on Win64 right now.
1223 * _control87 (_PC_53, MCW_PC);
1229 * Initialize architecture specific code.
1232 mono_arch_init (void)
1236 mono_mutex_init_recursive (&mini_arch_mutex);
1237 #if defined(__native_client_codegen__)
1238 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1239 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1240 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1241 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1244 #ifdef MONO_ARCH_NOMAP32BIT
1245 flags = MONO_MMAP_READ;
1246 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1247 breakpoint_size = 13;
1248 breakpoint_fault_size = 3;
1250 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1251 /* amd64_mov_reg_mem () */
1252 breakpoint_size = 8;
1253 breakpoint_fault_size = 8;
1256 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1257 single_step_fault_size = 4;
1259 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1260 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1261 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1263 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1264 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1265 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1269 * Cleanup architecture specific code.
1272 mono_arch_cleanup (void)
1274 mono_mutex_destroy (&mini_arch_mutex);
1275 #if defined(__native_client_codegen__)
1276 mono_native_tls_free (nacl_instruction_depth);
1277 mono_native_tls_free (nacl_rex_tag);
1278 mono_native_tls_free (nacl_legacy_prefix_tag);
1283 * This function returns the optimizations supported on this cpu.
1286 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1292 if (mono_hwcap_x86_has_cmov) {
1293 opts |= MONO_OPT_CMOV;
1295 if (mono_hwcap_x86_has_fcmov)
1296 opts |= MONO_OPT_FCMOV;
1298 *exclude_mask |= MONO_OPT_FCMOV;
1300 *exclude_mask |= MONO_OPT_CMOV;
1307 * This function test for all SSE functions supported.
1309 * Returns a bitmask corresponding to all supported versions.
1313 mono_arch_cpu_enumerate_simd_versions (void)
1315 guint32 sse_opts = 0;
1317 if (mono_hwcap_x86_has_sse1)
1318 sse_opts |= SIMD_VERSION_SSE1;
1320 if (mono_hwcap_x86_has_sse2)
1321 sse_opts |= SIMD_VERSION_SSE2;
1323 if (mono_hwcap_x86_has_sse3)
1324 sse_opts |= SIMD_VERSION_SSE3;
1326 if (mono_hwcap_x86_has_ssse3)
1327 sse_opts |= SIMD_VERSION_SSSE3;
1329 if (mono_hwcap_x86_has_sse41)
1330 sse_opts |= SIMD_VERSION_SSE41;
1332 if (mono_hwcap_x86_has_sse42)
1333 sse_opts |= SIMD_VERSION_SSE42;
1335 if (mono_hwcap_x86_has_sse4a)
1336 sse_opts |= SIMD_VERSION_SSE4a;
1344 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1349 for (i = 0; i < cfg->num_varinfo; i++) {
1350 MonoInst *ins = cfg->varinfo [i];
1351 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1354 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1357 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1358 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1361 if (mono_is_regsize_var (ins->inst_vtype)) {
1362 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1363 g_assert (i == vmv->idx);
1364 vars = g_list_prepend (vars, vmv);
1368 vars = mono_varlist_sort (cfg, vars, 0);
1374 * mono_arch_compute_omit_fp:
1376 * Determine whenever the frame pointer can be eliminated.
1379 mono_arch_compute_omit_fp (MonoCompile *cfg)
1381 MonoMethodSignature *sig;
1382 MonoMethodHeader *header;
1386 if (cfg->arch.omit_fp_computed)
1389 header = cfg->header;
1391 sig = mono_method_signature (cfg->method);
1393 if (!cfg->arch.cinfo)
1394 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1395 cinfo = cfg->arch.cinfo;
1398 * FIXME: Remove some of the restrictions.
1400 cfg->arch.omit_fp = TRUE;
1401 cfg->arch.omit_fp_computed = TRUE;
1403 #ifdef __native_client_codegen__
1404 /* NaCl modules may not change the value of RBP, so it cannot be */
1405 /* used as a normal register, but it can be used as a frame pointer*/
1406 cfg->disable_omit_fp = TRUE;
1407 cfg->arch.omit_fp = FALSE;
1411 cfg->arch.omit_fp = FALSE;
1414 if (cfg->disable_omit_fp)
1415 cfg->arch.omit_fp = FALSE;
1417 if (!debug_omit_fp ())
1418 cfg->arch.omit_fp = FALSE;
1420 if (cfg->method->save_lmf)
1421 cfg->arch.omit_fp = FALSE;
1423 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1424 cfg->arch.omit_fp = FALSE;
1425 if (header->num_clauses)
1426 cfg->arch.omit_fp = FALSE;
1427 if (cfg->param_area)
1428 cfg->arch.omit_fp = FALSE;
1429 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1430 cfg->arch.omit_fp = FALSE;
1431 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1432 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1433 cfg->arch.omit_fp = FALSE;
1434 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1435 ArgInfo *ainfo = &cinfo->args [i];
1437 if (ainfo->storage == ArgOnStack) {
1439 * The stack offset can only be determined when the frame
1442 cfg->arch.omit_fp = FALSE;
1447 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1448 MonoInst *ins = cfg->varinfo [i];
1451 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1456 mono_arch_get_global_int_regs (MonoCompile *cfg)
1460 mono_arch_compute_omit_fp (cfg);
1462 if (cfg->globalra) {
1463 if (cfg->arch.omit_fp)
1464 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1466 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1467 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1468 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1469 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1470 #ifndef __native_client_codegen__
1471 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1474 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1475 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1476 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1477 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1478 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1479 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1480 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1481 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1483 if (cfg->arch.omit_fp)
1484 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1486 /* We use the callee saved registers for global allocation */
1487 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1488 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1489 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1490 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1491 #ifndef __native_client_codegen__
1492 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1495 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1496 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1504 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1509 /* All XMM registers */
1510 for (i = 0; i < 16; ++i)
1511 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1517 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1519 static GList *r = NULL;
1524 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1525 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1526 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1527 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1528 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1529 #ifndef __native_client_codegen__
1530 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1533 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1534 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1535 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1536 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1537 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1538 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1539 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1540 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1542 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1549 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1552 static GList *r = NULL;
1557 for (i = 0; i < AMD64_XMM_NREG; ++i)
1558 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1560 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1567 * mono_arch_regalloc_cost:
1569 * Return the cost, in number of memory references, of the action of
1570 * allocating the variable VMV into a register during global register
1574 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1576 MonoInst *ins = cfg->varinfo [vmv->idx];
1578 if (cfg->method->save_lmf)
1579 /* The register is already saved */
1580 /* substract 1 for the invisible store in the prolog */
1581 return (ins->opcode == OP_ARG) ? 0 : 1;
1584 return (ins->opcode == OP_ARG) ? 1 : 2;
1588 * mono_arch_fill_argument_info:
1590 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1594 mono_arch_fill_argument_info (MonoCompile *cfg)
1597 MonoMethodSignature *sig;
1598 MonoMethodHeader *header;
1603 header = cfg->header;
1605 sig = mono_method_signature (cfg->method);
1607 cinfo = cfg->arch.cinfo;
1608 sig_ret = mini_replace_type (sig->ret);
1611 * Contrary to mono_arch_allocate_vars (), the information should describe
1612 * where the arguments are at the beginning of the method, not where they can be
1613 * accessed during the execution of the method. The later makes no sense for the
1614 * global register allocator, since a variable can be in more than one location.
1616 if (sig_ret->type != MONO_TYPE_VOID) {
1617 switch (cinfo->ret.storage) {
1619 case ArgInFloatSSEReg:
1620 case ArgInDoubleSSEReg:
1621 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1622 cfg->vret_addr->opcode = OP_REGVAR;
1623 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1626 cfg->ret->opcode = OP_REGVAR;
1627 cfg->ret->inst_c0 = cinfo->ret.reg;
1630 case ArgValuetypeInReg:
1631 cfg->ret->opcode = OP_REGOFFSET;
1632 cfg->ret->inst_basereg = -1;
1633 cfg->ret->inst_offset = -1;
1636 g_assert_not_reached ();
1640 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1641 ArgInfo *ainfo = &cinfo->args [i];
1644 ins = cfg->args [i];
1646 if (sig->hasthis && (i == 0))
1647 arg_type = &mono_defaults.object_class->byval_arg;
1649 arg_type = sig->params [i - sig->hasthis];
1651 switch (ainfo->storage) {
1653 case ArgInFloatSSEReg:
1654 case ArgInDoubleSSEReg:
1655 ins->opcode = OP_REGVAR;
1656 ins->inst_c0 = ainfo->reg;
1659 ins->opcode = OP_REGOFFSET;
1660 ins->inst_basereg = -1;
1661 ins->inst_offset = -1;
1663 case ArgValuetypeInReg:
1665 ins->opcode = OP_NOP;
1668 g_assert_not_reached ();
1674 mono_arch_allocate_vars (MonoCompile *cfg)
1677 MonoMethodSignature *sig;
1678 MonoMethodHeader *header;
1681 guint32 locals_stack_size, locals_stack_align;
1685 header = cfg->header;
1687 sig = mono_method_signature (cfg->method);
1689 cinfo = cfg->arch.cinfo;
1690 sig_ret = mini_replace_type (sig->ret);
1692 mono_arch_compute_omit_fp (cfg);
1695 * We use the ABI calling conventions for managed code as well.
1696 * Exception: valuetypes are only sometimes passed or returned in registers.
1700 * The stack looks like this:
1701 * <incoming arguments passed on the stack>
1703 * <lmf/caller saved registers>
1706 * <localloc area> -> grows dynamically
1710 if (cfg->arch.omit_fp) {
1711 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1712 cfg->frame_reg = AMD64_RSP;
1715 /* Locals are allocated backwards from %fp */
1716 cfg->frame_reg = AMD64_RBP;
1720 cfg->arch.saved_iregs = cfg->used_int_regs;
1721 if (cfg->method->save_lmf)
1722 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1723 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1725 if (cfg->arch.omit_fp)
1726 cfg->arch.reg_save_area_offset = offset;
1727 /* Reserve space for callee saved registers */
1728 for (i = 0; i < AMD64_NREG; ++i)
1729 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1730 offset += sizeof(mgreg_t);
1732 if (!cfg->arch.omit_fp)
1733 cfg->arch.reg_save_area_offset = -offset;
1735 if (sig_ret->type != MONO_TYPE_VOID) {
1736 switch (cinfo->ret.storage) {
1738 case ArgInFloatSSEReg:
1739 case ArgInDoubleSSEReg:
1740 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1741 if (cfg->globalra) {
1742 cfg->vret_addr->opcode = OP_REGVAR;
1743 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1745 /* The register is volatile */
1746 cfg->vret_addr->opcode = OP_REGOFFSET;
1747 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1748 if (cfg->arch.omit_fp) {
1749 cfg->vret_addr->inst_offset = offset;
1753 cfg->vret_addr->inst_offset = -offset;
1755 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1756 printf ("vret_addr =");
1757 mono_print_ins (cfg->vret_addr);
1762 cfg->ret->opcode = OP_REGVAR;
1763 cfg->ret->inst_c0 = cinfo->ret.reg;
1766 case ArgValuetypeInReg:
1767 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1768 cfg->ret->opcode = OP_REGOFFSET;
1769 cfg->ret->inst_basereg = cfg->frame_reg;
1770 if (cfg->arch.omit_fp) {
1771 cfg->ret->inst_offset = offset;
1772 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1774 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1775 cfg->ret->inst_offset = - offset;
1779 g_assert_not_reached ();
1782 cfg->ret->dreg = cfg->ret->inst_c0;
1785 /* Allocate locals */
1786 if (!cfg->globalra) {
1787 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1788 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1789 char *mname = mono_method_full_name (cfg->method, TRUE);
1790 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1791 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1796 if (locals_stack_align) {
1797 offset += (locals_stack_align - 1);
1798 offset &= ~(locals_stack_align - 1);
1800 if (cfg->arch.omit_fp) {
1801 cfg->locals_min_stack_offset = offset;
1802 cfg->locals_max_stack_offset = offset + locals_stack_size;
1804 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1805 cfg->locals_max_stack_offset = - offset;
1808 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1809 if (offsets [i] != -1) {
1810 MonoInst *ins = cfg->varinfo [i];
1811 ins->opcode = OP_REGOFFSET;
1812 ins->inst_basereg = cfg->frame_reg;
1813 if (cfg->arch.omit_fp)
1814 ins->inst_offset = (offset + offsets [i]);
1816 ins->inst_offset = - (offset + offsets [i]);
1817 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1820 offset += locals_stack_size;
1823 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1824 g_assert (!cfg->arch.omit_fp);
1825 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1826 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1829 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1830 ins = cfg->args [i];
1831 if (ins->opcode != OP_REGVAR) {
1832 ArgInfo *ainfo = &cinfo->args [i];
1833 gboolean inreg = TRUE;
1836 if (sig->hasthis && (i == 0))
1837 arg_type = &mono_defaults.object_class->byval_arg;
1839 arg_type = sig->params [i - sig->hasthis];
1841 if (cfg->globalra) {
1842 /* The new allocator needs info about the original locations of the arguments */
1843 switch (ainfo->storage) {
1845 case ArgInFloatSSEReg:
1846 case ArgInDoubleSSEReg:
1847 ins->opcode = OP_REGVAR;
1848 ins->inst_c0 = ainfo->reg;
1851 g_assert (!cfg->arch.omit_fp);
1852 ins->opcode = OP_REGOFFSET;
1853 ins->inst_basereg = cfg->frame_reg;
1854 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1856 case ArgValuetypeInReg:
1857 ins->opcode = OP_REGOFFSET;
1858 ins->inst_basereg = cfg->frame_reg;
1859 /* These arguments are saved to the stack in the prolog */
1860 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1861 if (cfg->arch.omit_fp) {
1862 ins->inst_offset = offset;
1863 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1865 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1866 ins->inst_offset = - offset;
1870 g_assert_not_reached ();
1876 /* FIXME: Allocate volatile arguments to registers */
1877 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1881 * Under AMD64, all registers used to pass arguments to functions
1882 * are volatile across calls.
1883 * FIXME: Optimize this.
1885 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1888 ins->opcode = OP_REGOFFSET;
1890 switch (ainfo->storage) {
1892 case ArgInFloatSSEReg:
1893 case ArgInDoubleSSEReg:
1895 ins->opcode = OP_REGVAR;
1896 ins->dreg = ainfo->reg;
1900 g_assert (!cfg->arch.omit_fp);
1901 ins->opcode = OP_REGOFFSET;
1902 ins->inst_basereg = cfg->frame_reg;
1903 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1905 case ArgValuetypeInReg:
1907 case ArgValuetypeAddrInIReg: {
1909 g_assert (!cfg->arch.omit_fp);
1911 MONO_INST_NEW (cfg, indir, 0);
1912 indir->opcode = OP_REGOFFSET;
1913 if (ainfo->pair_storage [0] == ArgInIReg) {
1914 indir->inst_basereg = cfg->frame_reg;
1915 offset = ALIGN_TO (offset, sizeof (gpointer));
1916 offset += (sizeof (gpointer));
1917 indir->inst_offset = - offset;
1920 indir->inst_basereg = cfg->frame_reg;
1921 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1924 ins->opcode = OP_VTARG_ADDR;
1925 ins->inst_left = indir;
1933 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1934 ins->opcode = OP_REGOFFSET;
1935 ins->inst_basereg = cfg->frame_reg;
1936 /* These arguments are saved to the stack in the prolog */
1937 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1938 if (cfg->arch.omit_fp) {
1939 ins->inst_offset = offset;
1940 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1941 // Arguments are yet supported by the stack map creation code
1942 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1944 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1945 ins->inst_offset = - offset;
1946 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1952 cfg->stack_offset = offset;
1956 mono_arch_create_vars (MonoCompile *cfg)
1958 MonoMethodSignature *sig;
1962 sig = mono_method_signature (cfg->method);
1964 if (!cfg->arch.cinfo)
1965 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1966 cinfo = cfg->arch.cinfo;
1968 if (cinfo->ret.storage == ArgValuetypeInReg)
1969 cfg->ret_var_is_local = TRUE;
1971 sig_ret = mini_replace_type (sig->ret);
1972 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1973 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1974 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1975 printf ("vret_addr = ");
1976 mono_print_ins (cfg->vret_addr);
1980 if (cfg->gen_seq_points) {
1983 if (cfg->compile_aot) {
1984 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1985 ins->flags |= MONO_INST_VOLATILE;
1986 cfg->arch.seq_point_info_var = ins;
1989 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1990 ins->flags |= MONO_INST_VOLATILE;
1991 cfg->arch.ss_trigger_page_var = ins;
1994 #ifdef MONO_AMD64_NO_PUSHES
1996 * When this is set, we pass arguments on the stack by moves, and by allocating
1997 * a bigger stack frame, instead of pushes.
1998 * Pushes complicate exception handling because the arguments on the stack have
1999 * to be popped each time a frame is unwound. They also make fp elimination
2001 * FIXME: This doesn't work inside filter/finally clauses, since those execute
2002 * on a new frame which doesn't include a param area.
2004 cfg->arch.no_pushes = TRUE;
2007 if (cfg->method->save_lmf)
2008 cfg->create_lmf_var = TRUE;
2010 if (cfg->method->save_lmf) {
2012 #if !defined(HOST_WIN32)
2013 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2014 cfg->lmf_ir_mono_lmf = TRUE;
2018 #ifndef MONO_AMD64_NO_PUSHES
2019 cfg->arch_eh_jit_info = 1;
2024 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2030 MONO_INST_NEW (cfg, ins, OP_MOVE);
2031 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2032 ins->sreg1 = tree->dreg;
2033 MONO_ADD_INS (cfg->cbb, ins);
2034 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2036 case ArgInFloatSSEReg:
2037 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2038 ins->dreg = mono_alloc_freg (cfg);
2039 ins->sreg1 = tree->dreg;
2040 MONO_ADD_INS (cfg->cbb, ins);
2042 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2044 case ArgInDoubleSSEReg:
2045 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2046 ins->dreg = mono_alloc_freg (cfg);
2047 ins->sreg1 = tree->dreg;
2048 MONO_ADD_INS (cfg->cbb, ins);
2050 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2054 g_assert_not_reached ();
2059 arg_storage_to_load_membase (ArgStorage storage)
2063 #if defined(__mono_ilp32__)
2064 return OP_LOADI8_MEMBASE;
2066 return OP_LOAD_MEMBASE;
2068 case ArgInDoubleSSEReg:
2069 return OP_LOADR8_MEMBASE;
2070 case ArgInFloatSSEReg:
2071 return OP_LOADR4_MEMBASE;
2073 g_assert_not_reached ();
2080 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2083 MonoMethodSignature *tmp_sig;
2086 if (call->tail_call)
2089 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2092 * mono_ArgIterator_Setup assumes the signature cookie is
2093 * passed first and all the arguments which were before it are
2094 * passed on the stack after the signature. So compensate by
2095 * passing a different signature.
2097 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2098 tmp_sig->param_count -= call->signature->sentinelpos;
2099 tmp_sig->sentinelpos = 0;
2100 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2102 sig_reg = mono_alloc_ireg (cfg);
2103 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2105 if (cfg->arch.no_pushes) {
2106 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2108 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2109 arg->sreg1 = sig_reg;
2110 MONO_ADD_INS (cfg->cbb, arg);
2114 static inline LLVMArgStorage
2115 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2119 return LLVMArgInIReg;
2123 g_assert_not_reached ();
2130 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2136 LLVMCallInfo *linfo;
2137 MonoType *t, *sig_ret;
2139 n = sig->param_count + sig->hasthis;
2140 sig_ret = mini_replace_type (sig->ret);
2142 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2144 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2147 * LLVM always uses the native ABI while we use our own ABI, the
2148 * only difference is the handling of vtypes:
2149 * - we only pass/receive them in registers in some cases, and only
2150 * in 1 or 2 integer registers.
2152 if (cinfo->ret.storage == ArgValuetypeInReg) {
2154 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2155 cfg->disable_llvm = TRUE;
2159 linfo->ret.storage = LLVMArgVtypeInReg;
2160 for (j = 0; j < 2; ++j)
2161 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2164 if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2165 /* Vtype returned using a hidden argument */
2166 linfo->ret.storage = LLVMArgVtypeRetAddr;
2167 linfo->vret_arg_index = cinfo->vret_arg_index;
2170 for (i = 0; i < n; ++i) {
2171 ainfo = cinfo->args + i;
2173 if (i >= sig->hasthis)
2174 t = sig->params [i - sig->hasthis];
2176 t = &mono_defaults.int_class->byval_arg;
2178 linfo->args [i].storage = LLVMArgNone;
2180 switch (ainfo->storage) {
2182 linfo->args [i].storage = LLVMArgInIReg;
2184 case ArgInDoubleSSEReg:
2185 case ArgInFloatSSEReg:
2186 linfo->args [i].storage = LLVMArgInFPReg;
2189 if (MONO_TYPE_ISSTRUCT (t)) {
2190 linfo->args [i].storage = LLVMArgVtypeByVal;
2192 linfo->args [i].storage = LLVMArgInIReg;
2194 if (t->type == MONO_TYPE_R4)
2195 linfo->args [i].storage = LLVMArgInFPReg;
2196 else if (t->type == MONO_TYPE_R8)
2197 linfo->args [i].storage = LLVMArgInFPReg;
2201 case ArgValuetypeInReg:
2203 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2204 cfg->disable_llvm = TRUE;
2208 linfo->args [i].storage = LLVMArgVtypeInReg;
2209 for (j = 0; j < 2; ++j)
2210 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2213 cfg->exception_message = g_strdup ("ainfo->storage");
2214 cfg->disable_llvm = TRUE;
2224 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2227 MonoMethodSignature *sig;
2229 int i, n, stack_size;
2235 sig = call->signature;
2236 n = sig->param_count + sig->hasthis;
2238 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2242 if (COMPILE_LLVM (cfg)) {
2243 /* We shouldn't be called in the llvm case */
2244 cfg->disable_llvm = TRUE;
2248 if (cinfo->need_stack_align) {
2249 if (!cfg->arch.no_pushes)
2250 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2254 * Emit all arguments which are passed on the stack to prevent register
2255 * allocation problems.
2257 if (cfg->arch.no_pushes) {
2258 for (i = 0; i < n; ++i) {
2260 ainfo = cinfo->args + i;
2262 in = call->args [i];
2264 if (sig->hasthis && i == 0)
2265 t = &mono_defaults.object_class->byval_arg;
2267 t = sig->params [i - sig->hasthis];
2269 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2271 if (t->type == MONO_TYPE_R4)
2272 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2273 else if (t->type == MONO_TYPE_R8)
2274 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2276 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2278 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2280 if (cfg->compute_gc_maps) {
2283 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2290 * Emit all parameters passed in registers in non-reverse order for better readability
2291 * and to help the optimization in emit_prolog ().
2293 for (i = 0; i < n; ++i) {
2294 ainfo = cinfo->args + i;
2296 in = call->args [i];
2298 if (ainfo->storage == ArgInIReg)
2299 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2302 for (i = n - 1; i >= 0; --i) {
2303 ainfo = cinfo->args + i;
2305 in = call->args [i];
2307 switch (ainfo->storage) {
2311 case ArgInFloatSSEReg:
2312 case ArgInDoubleSSEReg:
2313 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2316 case ArgValuetypeInReg:
2317 case ArgValuetypeAddrInIReg:
2318 if (ainfo->storage == ArgOnStack && call->tail_call) {
2319 MonoInst *call_inst = (MonoInst*)call;
2320 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2321 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2322 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2326 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2327 size = sizeof (MonoTypedRef);
2328 align = sizeof (gpointer);
2332 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2335 * Other backends use mono_type_stack_size (), but that
2336 * aligns the size to 8, which is larger than the size of
2337 * the source, leading to reads of invalid memory if the
2338 * source is at the end of address space.
2340 size = mono_class_value_size (in->klass, &align);
2343 g_assert (in->klass);
2345 if (ainfo->storage == ArgOnStack && size >= 10000) {
2346 /* Avoid asserts in emit_memcpy () */
2347 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2348 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2349 /* Continue normally */
2353 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2354 arg->sreg1 = in->dreg;
2355 arg->klass = in->klass;
2356 arg->backend.size = size;
2357 arg->inst_p0 = call;
2358 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2359 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2361 MONO_ADD_INS (cfg->cbb, arg);
2364 if (cfg->arch.no_pushes) {
2367 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2368 arg->sreg1 = in->dreg;
2369 if (!sig->params [i - sig->hasthis]->byref) {
2370 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2371 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2372 arg->opcode = OP_STORER4_MEMBASE_REG;
2373 arg->inst_destbasereg = X86_ESP;
2374 arg->inst_offset = 0;
2375 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2376 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2377 arg->opcode = OP_STORER8_MEMBASE_REG;
2378 arg->inst_destbasereg = X86_ESP;
2379 arg->inst_offset = 0;
2382 MONO_ADD_INS (cfg->cbb, arg);
2387 g_assert_not_reached ();
2390 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2391 /* Emit the signature cookie just before the implicit arguments */
2392 emit_sig_cookie (cfg, call, cinfo);
2395 /* Handle the case where there are no implicit arguments */
2396 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2397 emit_sig_cookie (cfg, call, cinfo);
2399 sig_ret = mini_replace_type (sig->ret);
2400 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2403 if (cinfo->ret.storage == ArgValuetypeInReg) {
2404 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2406 * Tell the JIT to use a more efficient calling convention: call using
2407 * OP_CALL, compute the result location after the call, and save the
2410 call->vret_in_reg = TRUE;
2412 * Nullify the instruction computing the vret addr to enable
2413 * future optimizations.
2416 NULLIFY_INS (call->vret_var);
2418 if (call->tail_call)
2421 * The valuetype is in RAX:RDX after the call, need to be copied to
2422 * the stack. Push the address here, so the call instruction can
2425 if (!cfg->arch.vret_addr_loc) {
2426 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2427 /* Prevent it from being register allocated or optimized away */
2428 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2431 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2435 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2436 vtarg->sreg1 = call->vret_var->dreg;
2437 vtarg->dreg = mono_alloc_preg (cfg);
2438 MONO_ADD_INS (cfg->cbb, vtarg);
2440 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2445 if (call->inst.opcode != OP_TAILCALL) {
2446 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2450 if (cfg->method->save_lmf) {
2451 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2452 MONO_ADD_INS (cfg->cbb, arg);
2455 call->stack_usage = cinfo->stack_usage;
2459 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2462 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2463 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2464 int size = ins->backend.size;
2466 if (ainfo->storage == ArgValuetypeInReg) {
2470 for (part = 0; part < 2; ++part) {
2471 if (ainfo->pair_storage [part] == ArgNone)
2474 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2475 load->inst_basereg = src->dreg;
2476 load->inst_offset = part * sizeof(mgreg_t);
2478 switch (ainfo->pair_storage [part]) {
2480 load->dreg = mono_alloc_ireg (cfg);
2482 case ArgInDoubleSSEReg:
2483 case ArgInFloatSSEReg:
2484 load->dreg = mono_alloc_freg (cfg);
2487 g_assert_not_reached ();
2489 MONO_ADD_INS (cfg->cbb, load);
2491 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2493 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2494 MonoInst *vtaddr, *load;
2495 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2497 g_assert (!cfg->arch.no_pushes);
2499 MONO_INST_NEW (cfg, load, OP_LDADDR);
2500 cfg->has_indirection = TRUE;
2501 load->inst_p0 = vtaddr;
2502 vtaddr->flags |= MONO_INST_INDIRECT;
2503 load->type = STACK_MP;
2504 load->klass = vtaddr->klass;
2505 load->dreg = mono_alloc_ireg (cfg);
2506 MONO_ADD_INS (cfg->cbb, load);
2507 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2509 if (ainfo->pair_storage [0] == ArgInIReg) {
2510 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2511 arg->dreg = mono_alloc_ireg (cfg);
2512 arg->sreg1 = load->dreg;
2514 MONO_ADD_INS (cfg->cbb, arg);
2515 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2517 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2518 arg->sreg1 = load->dreg;
2519 MONO_ADD_INS (cfg->cbb, arg);
2523 if (cfg->arch.no_pushes) {
2524 int dreg = mono_alloc_ireg (cfg);
2526 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2527 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2529 /* Can't use this for < 8 since it does an 8 byte memory load */
2530 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2531 arg->inst_basereg = src->dreg;
2532 arg->inst_offset = 0;
2533 MONO_ADD_INS (cfg->cbb, arg);
2535 } else if (size <= 40) {
2536 if (cfg->arch.no_pushes) {
2537 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2539 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2540 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2543 if (cfg->arch.no_pushes) {
2544 // FIXME: Code growth
2545 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2547 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2548 arg->inst_basereg = src->dreg;
2549 arg->inst_offset = 0;
2550 arg->inst_imm = size;
2551 MONO_ADD_INS (cfg->cbb, arg);
2555 if (cfg->compute_gc_maps) {
2557 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2563 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2565 MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2567 if (ret->type == MONO_TYPE_R4) {
2568 if (COMPILE_LLVM (cfg))
2569 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2571 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2573 } else if (ret->type == MONO_TYPE_R8) {
2574 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2578 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2581 #endif /* DISABLE_JIT */
2583 #define EMIT_COND_BRANCH(ins,cond,sign) \
2584 if (ins->inst_true_bb->native_offset) { \
2585 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2587 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2588 if ((cfg->opt & MONO_OPT_BRANCH) && \
2589 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2590 x86_branch8 (code, cond, 0, sign); \
2592 x86_branch32 (code, cond, 0, sign); \
2596 MonoMethodSignature *sig;
2601 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2609 switch (cinfo->ret.storage) {
2613 case ArgValuetypeInReg: {
2614 ArgInfo *ainfo = &cinfo->ret;
2616 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2618 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2626 for (i = 0; i < cinfo->nargs; ++i) {
2627 ArgInfo *ainfo = &cinfo->args [i];
2628 switch (ainfo->storage) {
2631 case ArgValuetypeInReg:
2632 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2634 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2646 * mono_arch_dyn_call_prepare:
2648 * Return a pointer to an arch-specific structure which contains information
2649 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2650 * supported for SIG.
2651 * This function is equivalent to ffi_prep_cif in libffi.
2654 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2656 ArchDynCallInfo *info;
2659 cinfo = get_call_info (NULL, NULL, sig);
2661 if (!dyn_call_supported (sig, cinfo)) {
2666 info = g_new0 (ArchDynCallInfo, 1);
2667 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2669 info->cinfo = cinfo;
2671 return (MonoDynCallInfo*)info;
2675 * mono_arch_dyn_call_free:
2677 * Free a MonoDynCallInfo structure.
2680 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2682 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2684 g_free (ainfo->cinfo);
2688 #if !defined(__native_client__)
2689 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2690 #define GREG_TO_PTR(greg) (gpointer)(greg)
2692 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2693 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2694 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2698 * mono_arch_get_start_dyn_call:
2700 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2701 * store the result into BUF.
2702 * ARGS should be an array of pointers pointing to the arguments.
2703 * RET should point to a memory buffer large enought to hold the result of the
2705 * This function should be as fast as possible, any work which does not depend
2706 * on the actual values of the arguments should be done in
2707 * mono_arch_dyn_call_prepare ().
2708 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2712 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2714 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2715 DynCallArgs *p = (DynCallArgs*)buf;
2716 int arg_index, greg, i, pindex;
2717 MonoMethodSignature *sig = dinfo->sig;
2719 g_assert (buf_len >= sizeof (DynCallArgs));
2728 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2729 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2734 if (dinfo->cinfo->vtype_retaddr)
2735 p->regs [greg ++] = PTR_TO_GREG(ret);
2737 for (i = pindex; i < sig->param_count; i++) {
2738 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2739 gpointer *arg = args [arg_index ++];
2742 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2747 case MONO_TYPE_STRING:
2748 case MONO_TYPE_CLASS:
2749 case MONO_TYPE_ARRAY:
2750 case MONO_TYPE_SZARRAY:
2751 case MONO_TYPE_OBJECT:
2755 #if !defined(__mono_ilp32__)
2759 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2760 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2762 #if defined(__mono_ilp32__)
2765 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2766 p->regs [greg ++] = *(guint64*)(arg);
2769 case MONO_TYPE_BOOLEAN:
2771 p->regs [greg ++] = *(guint8*)(arg);
2774 p->regs [greg ++] = *(gint8*)(arg);
2777 p->regs [greg ++] = *(gint16*)(arg);
2780 case MONO_TYPE_CHAR:
2781 p->regs [greg ++] = *(guint16*)(arg);
2784 p->regs [greg ++] = *(gint32*)(arg);
2787 p->regs [greg ++] = *(guint32*)(arg);
2789 case MONO_TYPE_GENERICINST:
2790 if (MONO_TYPE_IS_REFERENCE (t)) {
2791 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2796 case MONO_TYPE_VALUETYPE: {
2797 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2799 g_assert (ainfo->storage == ArgValuetypeInReg);
2800 if (ainfo->pair_storage [0] != ArgNone) {
2801 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2802 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2804 if (ainfo->pair_storage [1] != ArgNone) {
2805 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2806 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2811 g_assert_not_reached ();
2815 g_assert (greg <= PARAM_REGS);
2819 * mono_arch_finish_dyn_call:
2821 * Store the result of a dyn call into the return value buffer passed to
2822 * start_dyn_call ().
2823 * This function should be as fast as possible, any work which does not depend
2824 * on the actual values of the arguments should be done in
2825 * mono_arch_dyn_call_prepare ().
2828 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2830 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2831 MonoMethodSignature *sig = dinfo->sig;
2832 guint8 *ret = ((DynCallArgs*)buf)->ret;
2833 mgreg_t res = ((DynCallArgs*)buf)->res;
2834 MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2836 switch (sig_ret->type) {
2837 case MONO_TYPE_VOID:
2838 *(gpointer*)ret = NULL;
2840 case MONO_TYPE_STRING:
2841 case MONO_TYPE_CLASS:
2842 case MONO_TYPE_ARRAY:
2843 case MONO_TYPE_SZARRAY:
2844 case MONO_TYPE_OBJECT:
2848 *(gpointer*)ret = GREG_TO_PTR(res);
2854 case MONO_TYPE_BOOLEAN:
2855 *(guint8*)ret = res;
2858 *(gint16*)ret = res;
2861 case MONO_TYPE_CHAR:
2862 *(guint16*)ret = res;
2865 *(gint32*)ret = res;
2868 *(guint32*)ret = res;
2871 *(gint64*)ret = res;
2874 *(guint64*)ret = res;
2876 case MONO_TYPE_GENERICINST:
2877 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2878 *(gpointer*)ret = GREG_TO_PTR(res);
2883 case MONO_TYPE_VALUETYPE:
2884 if (dinfo->cinfo->vtype_retaddr) {
2887 ArgInfo *ainfo = &dinfo->cinfo->ret;
2889 g_assert (ainfo->storage == ArgValuetypeInReg);
2891 if (ainfo->pair_storage [0] != ArgNone) {
2892 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2893 ((mgreg_t*)ret)[0] = res;
2896 g_assert (ainfo->pair_storage [1] == ArgNone);
2900 g_assert_not_reached ();
2904 /* emit an exception if condition is fail */
2905 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2907 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2908 if (tins == NULL) { \
2909 mono_add_patch_info (cfg, code - cfg->native_code, \
2910 MONO_PATCH_INFO_EXC, exc_name); \
2911 x86_branch32 (code, cond, 0, signed); \
2913 EMIT_COND_BRANCH (tins, cond, signed); \
2917 #define EMIT_FPCOMPARE(code) do { \
2918 amd64_fcompp (code); \
2919 amd64_fnstsw (code); \
2922 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2923 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2924 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2925 amd64_ ##op (code); \
2926 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2927 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2931 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2933 gboolean no_patch = FALSE;
2936 * FIXME: Add support for thunks
2939 gboolean near_call = FALSE;
2942 * Indirect calls are expensive so try to make a near call if possible.
2943 * The caller memory is allocated by the code manager so it is
2944 * guaranteed to be at a 32 bit offset.
2947 if (patch_type != MONO_PATCH_INFO_ABS) {
2948 /* The target is in memory allocated using the code manager */
2951 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2952 if (((MonoMethod*)data)->klass->image->aot_module)
2953 /* The callee might be an AOT method */
2955 if (((MonoMethod*)data)->dynamic)
2956 /* The target is in malloc-ed memory */
2960 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2962 * The call might go directly to a native function without
2965 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2967 gconstpointer target = mono_icall_get_wrapper (mi);
2968 if ((((guint64)target) >> 32) != 0)
2974 MonoJumpInfo *jinfo = NULL;
2976 if (cfg->abs_patches)
2977 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2979 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2980 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2981 if (mi && (((guint64)mi->func) >> 32) == 0)
2986 * This is not really an optimization, but required because the
2987 * generic class init trampolines use R11 to pass the vtable.
2992 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2994 if (info->func == info->wrapper) {
2996 if ((((guint64)info->func) >> 32) == 0)
3000 /* See the comment in mono_codegen () */
3001 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3005 else if ((((guint64)data) >> 32) == 0) {
3012 if (cfg->method->dynamic)
3013 /* These methods are allocated using malloc */
3016 #ifdef MONO_ARCH_NOMAP32BIT
3019 #if defined(__native_client__)
3020 /* Always use near_call == TRUE for Native Client */
3023 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3024 if (optimize_for_xen)
3027 if (cfg->compile_aot) {
3034 * Align the call displacement to an address divisible by 4 so it does
3035 * not span cache lines. This is required for code patching to work on SMP
3038 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3039 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3040 amd64_padding (code, pad_size);
3042 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3043 amd64_call_code (code, 0);
3046 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3047 amd64_set_reg_template (code, GP_SCRATCH_REG);
3048 amd64_call_reg (code, GP_SCRATCH_REG);
3055 static inline guint8*
3056 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3059 if (win64_adjust_stack)
3060 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3062 code = emit_call_body (cfg, code, patch_type, data);
3064 if (win64_adjust_stack)
3065 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3072 store_membase_imm_to_store_membase_reg (int opcode)
3075 case OP_STORE_MEMBASE_IMM:
3076 return OP_STORE_MEMBASE_REG;
3077 case OP_STOREI4_MEMBASE_IMM:
3078 return OP_STOREI4_MEMBASE_REG;
3079 case OP_STOREI8_MEMBASE_IMM:
3080 return OP_STOREI8_MEMBASE_REG;
3088 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3091 * mono_arch_peephole_pass_1:
3093 * Perform peephole opts which should/can be performed before local regalloc
3096 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3100 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3101 MonoInst *last_ins = ins->prev;
3103 switch (ins->opcode) {
3107 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3109 * X86_LEA is like ADD, but doesn't have the
3110 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3111 * its operand to 64 bit.
3113 ins->opcode = OP_X86_LEA_MEMBASE;
3114 ins->inst_basereg = ins->sreg1;
3119 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3123 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3124 * the latter has length 2-3 instead of 6 (reverse constant
3125 * propagation). These instruction sequences are very common
3126 * in the initlocals bblock.
3128 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3129 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3130 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3131 ins2->sreg1 = ins->dreg;
3132 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3134 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3143 case OP_COMPARE_IMM:
3144 case OP_LCOMPARE_IMM:
3145 /* OP_COMPARE_IMM (reg, 0)
3147 * OP_AMD64_TEST_NULL (reg)
3150 ins->opcode = OP_AMD64_TEST_NULL;
3152 case OP_ICOMPARE_IMM:
3154 ins->opcode = OP_X86_TEST_NULL;
3156 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3158 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3159 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3161 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3162 * OP_COMPARE_IMM reg, imm
3164 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3166 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3167 ins->inst_basereg == last_ins->inst_destbasereg &&
3168 ins->inst_offset == last_ins->inst_offset) {
3169 ins->opcode = OP_ICOMPARE_IMM;
3170 ins->sreg1 = last_ins->sreg1;
3172 /* check if we can remove cmp reg,0 with test null */
3174 ins->opcode = OP_X86_TEST_NULL;
3180 mono_peephole_ins (bb, ins);
3185 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3189 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3190 switch (ins->opcode) {
3193 /* reg = 0 -> XOR (reg, reg) */
3194 /* XOR sets cflags on x86, so we cant do it always */
3195 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3196 ins->opcode = OP_LXOR;
3197 ins->sreg1 = ins->dreg;
3198 ins->sreg2 = ins->dreg;
3206 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3207 * 0 result into 64 bits.
3209 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3210 ins->opcode = OP_IXOR;
3214 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3218 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3219 * the latter has length 2-3 instead of 6 (reverse constant
3220 * propagation). These instruction sequences are very common
3221 * in the initlocals bblock.
3223 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3224 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3225 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3226 ins2->sreg1 = ins->dreg;
3227 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3229 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3239 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3240 ins->opcode = OP_X86_INC_REG;
3243 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3244 ins->opcode = OP_X86_DEC_REG;
3248 mono_peephole_ins (bb, ins);
3252 #define NEW_INS(cfg,ins,dest,op) do { \
3253 MONO_INST_NEW ((cfg), (dest), (op)); \
3254 (dest)->cil_code = (ins)->cil_code; \
3255 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3259 * mono_arch_lowering_pass:
3261 * Converts complex opcodes into simpler ones so that each IR instruction
3262 * corresponds to one machine instruction.
3265 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3267 MonoInst *ins, *n, *temp;
3270 * FIXME: Need to add more instructions, but the current machine
3271 * description can't model some parts of the composite instructions like
3274 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3275 switch (ins->opcode) {
3279 case OP_IDIV_UN_IMM:
3280 case OP_IREM_UN_IMM:
3283 mono_decompose_op_imm (cfg, bb, ins);
3285 case OP_COMPARE_IMM:
3286 case OP_LCOMPARE_IMM:
3287 if (!amd64_is_imm32 (ins->inst_imm)) {
3288 NEW_INS (cfg, ins, temp, OP_I8CONST);
3289 temp->inst_c0 = ins->inst_imm;
3290 temp->dreg = mono_alloc_ireg (cfg);
3291 ins->opcode = OP_COMPARE;
3292 ins->sreg2 = temp->dreg;
3295 #ifndef __mono_ilp32__
3296 case OP_LOAD_MEMBASE:
3298 case OP_LOADI8_MEMBASE:
3299 #ifndef __native_client_codegen__
3300 /* Don't generate memindex opcodes (to simplify */
3301 /* read sandboxing) */
3302 if (!amd64_is_imm32 (ins->inst_offset)) {
3303 NEW_INS (cfg, ins, temp, OP_I8CONST);
3304 temp->inst_c0 = ins->inst_offset;
3305 temp->dreg = mono_alloc_ireg (cfg);
3306 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3307 ins->inst_indexreg = temp->dreg;
3311 #ifndef __mono_ilp32__
3312 case OP_STORE_MEMBASE_IMM:
3314 case OP_STOREI8_MEMBASE_IMM:
3315 if (!amd64_is_imm32 (ins->inst_imm)) {
3316 NEW_INS (cfg, ins, temp, OP_I8CONST);
3317 temp->inst_c0 = ins->inst_imm;
3318 temp->dreg = mono_alloc_ireg (cfg);
3319 ins->opcode = OP_STOREI8_MEMBASE_REG;
3320 ins->sreg1 = temp->dreg;
3323 #ifdef MONO_ARCH_SIMD_INTRINSICS
3324 case OP_EXPAND_I1: {
3325 int temp_reg1 = mono_alloc_ireg (cfg);
3326 int temp_reg2 = mono_alloc_ireg (cfg);
3327 int original_reg = ins->sreg1;
3329 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3330 temp->sreg1 = original_reg;
3331 temp->dreg = temp_reg1;
3333 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3334 temp->sreg1 = temp_reg1;
3335 temp->dreg = temp_reg2;
3338 NEW_INS (cfg, ins, temp, OP_LOR);
3339 temp->sreg1 = temp->dreg = temp_reg2;
3340 temp->sreg2 = temp_reg1;
3342 ins->opcode = OP_EXPAND_I2;
3343 ins->sreg1 = temp_reg2;
3352 bb->max_vreg = cfg->next_vreg;
3356 branch_cc_table [] = {
3357 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3358 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3359 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3362 /* Maps CMP_... constants to X86_CC_... constants */
3365 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3366 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3370 cc_signed_table [] = {
3371 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3372 FALSE, FALSE, FALSE, FALSE
3375 /*#include "cprop.c"*/
3377 static unsigned char*
3378 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3380 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3383 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3385 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3389 static unsigned char*
3390 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3392 int sreg = tree->sreg1;
3393 int need_touch = FALSE;
3395 #if defined(HOST_WIN32)
3397 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3398 if (!tree->flags & MONO_INST_INIT)
3407 * If requested stack size is larger than one page,
3408 * perform stack-touch operation
3411 * Generate stack probe code.
3412 * Under Windows, it is necessary to allocate one page at a time,
3413 * "touching" stack after each successful sub-allocation. This is
3414 * because of the way stack growth is implemented - there is a
3415 * guard page before the lowest stack page that is currently commited.
3416 * Stack normally grows sequentially so OS traps access to the
3417 * guard page and commits more pages when needed.
3419 amd64_test_reg_imm (code, sreg, ~0xFFF);
3420 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3422 br[2] = code; /* loop */
3423 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3424 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3425 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3426 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3427 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3428 amd64_patch (br[3], br[2]);
3429 amd64_test_reg_reg (code, sreg, sreg);
3430 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3431 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3433 br[1] = code; x86_jump8 (code, 0);
3435 amd64_patch (br[0], code);
3436 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3437 amd64_patch (br[1], code);
3438 amd64_patch (br[4], code);
3441 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3443 if (tree->flags & MONO_INST_INIT) {
3445 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3446 amd64_push_reg (code, AMD64_RAX);
3449 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3450 amd64_push_reg (code, AMD64_RCX);
3453 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3454 amd64_push_reg (code, AMD64_RDI);
3458 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3459 if (sreg != AMD64_RCX)
3460 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3461 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3463 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3464 if (cfg->param_area && cfg->arch.no_pushes)
3465 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3467 #if defined(__default_codegen__)
3468 amd64_prefix (code, X86_REP_PREFIX);
3470 #elif defined(__native_client_codegen__)
3471 /* NaCl stos pseudo-instruction */
3472 amd64_codegen_pre(code);
3473 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3474 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3475 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3476 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3477 amd64_prefix (code, X86_REP_PREFIX);
3479 amd64_codegen_post(code);
3480 #endif /* __native_client_codegen__ */
3482 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3483 amd64_pop_reg (code, AMD64_RDI);
3484 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3485 amd64_pop_reg (code, AMD64_RCX);
3486 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3487 amd64_pop_reg (code, AMD64_RAX);
3493 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3498 /* Move return value to the target register */
3499 /* FIXME: do this in the local reg allocator */
3500 switch (ins->opcode) {
3503 case OP_CALL_MEMBASE:
3506 case OP_LCALL_MEMBASE:
3507 g_assert (ins->dreg == AMD64_RAX);
3511 case OP_FCALL_MEMBASE:
3512 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3513 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3516 if (ins->dreg != AMD64_XMM0)
3517 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3522 case OP_VCALL_MEMBASE:
3525 case OP_VCALL2_MEMBASE:
3526 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3527 if (cinfo->ret.storage == ArgValuetypeInReg) {
3528 MonoInst *loc = cfg->arch.vret_addr_loc;
3530 /* Load the destination address */
3531 g_assert (loc->opcode == OP_REGOFFSET);
3532 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3534 for (quad = 0; quad < 2; quad ++) {
3535 switch (cinfo->ret.pair_storage [quad]) {
3537 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3539 case ArgInFloatSSEReg:
3540 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3542 case ArgInDoubleSSEReg:
3543 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3558 #endif /* DISABLE_JIT */
3561 static int tls_gs_offset;
3565 mono_amd64_have_tls_get (void)
3568 static gboolean have_tls_get = FALSE;
3569 static gboolean inited = FALSE;
3573 return have_tls_get;
3575 ins = (guint8*)pthread_getspecific;
3578 * We're looking for these two instructions:
3580 * mov %gs:[offset](,%rdi,8),%rax
3583 have_tls_get = ins [0] == 0x65 &&
3595 tls_gs_offset = ins[5];
3597 return have_tls_get;
3604 mono_amd64_get_tls_gs_offset (void)
3607 return tls_gs_offset;
3609 g_assert_not_reached ();
3615 * mono_amd64_emit_tls_get:
3616 * @code: buffer to store code to
3617 * @dreg: hard register where to place the result
3618 * @tls_offset: offset info
3620 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3621 * the dreg register the item in the thread local storage identified
3624 * Returns: a pointer to the end of the stored code
3627 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3630 if (tls_offset < 64) {
3631 x86_prefix (code, X86_GS_PREFIX);
3632 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3636 g_assert (tls_offset < 0x440);
3637 /* Load TEB->TlsExpansionSlots */
3638 x86_prefix (code, X86_GS_PREFIX);
3639 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3640 amd64_test_reg_reg (code, dreg, dreg);
3642 amd64_branch (code, X86_CC_EQ, code, TRUE);
3643 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3644 amd64_patch (buf [0], code);
3646 #elif defined(__APPLE__)
3647 x86_prefix (code, X86_GS_PREFIX);
3648 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3650 if (optimize_for_xen) {
3651 x86_prefix (code, X86_FS_PREFIX);
3652 amd64_mov_reg_mem (code, dreg, 0, 8);
3653 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3655 x86_prefix (code, X86_FS_PREFIX);
3656 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3663 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3665 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3667 if (dreg != offset_reg)
3668 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3669 amd64_prefix (code, X86_GS_PREFIX);
3670 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3671 #elif defined(__linux__)
3674 if (dreg == offset_reg) {
3675 /* Use a temporary reg by saving it to the redzone */
3676 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3677 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3678 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3679 offset_reg = tmpreg;
3681 x86_prefix (code, X86_FS_PREFIX);
3682 amd64_mov_reg_mem (code, dreg, 0, 8);
3683 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3685 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3687 g_assert_not_reached ();
3693 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3696 g_assert_not_reached ();
3697 #elif defined(__APPLE__)
3698 x86_prefix (code, X86_GS_PREFIX);
3699 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3701 g_assert (!optimize_for_xen);
3702 x86_prefix (code, X86_FS_PREFIX);
3703 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3709 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3711 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3713 g_assert_not_reached ();
3714 #elif defined(__APPLE__)
3715 x86_prefix (code, X86_GS_PREFIX);
3716 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3718 x86_prefix (code, X86_FS_PREFIX);
3719 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3725 * mono_arch_translate_tls_offset:
3727 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3730 mono_arch_translate_tls_offset (int offset)
3733 return tls_gs_offset + (offset * 8);
3742 * Emit code to initialize an LMF structure at LMF_OFFSET.
3745 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3748 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3751 * sp is saved right before calls but we need to save it here too so
3752 * async stack walks would work.
3754 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3756 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3757 if (cfg->arch.omit_fp && cfa_offset != -1)
3758 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3760 /* These can't contain refs */
3761 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3762 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3763 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3764 /* These are handled automatically by the stack marking code */
3765 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3770 #define REAL_PRINT_REG(text,reg) \
3771 mono_assert (reg >= 0); \
3772 amd64_push_reg (code, AMD64_RAX); \
3773 amd64_push_reg (code, AMD64_RDX); \
3774 amd64_push_reg (code, AMD64_RCX); \
3775 amd64_push_reg (code, reg); \
3776 amd64_push_imm (code, reg); \
3777 amd64_push_imm (code, text " %d %p\n"); \
3778 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3779 amd64_call_reg (code, AMD64_RAX); \
3780 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3781 amd64_pop_reg (code, AMD64_RCX); \
3782 amd64_pop_reg (code, AMD64_RDX); \
3783 amd64_pop_reg (code, AMD64_RAX);
3785 /* benchmark and set based on cpu */
3786 #define LOOP_ALIGNMENT 8
3787 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3791 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3796 guint8 *code = cfg->native_code + cfg->code_len;
3797 MonoInst *last_ins = NULL;
3798 guint last_offset = 0;
3801 /* Fix max_offset estimate for each successor bb */
3802 if (cfg->opt & MONO_OPT_BRANCH) {
3803 int current_offset = cfg->code_len;
3804 MonoBasicBlock *current_bb;
3805 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3806 current_bb->max_offset = current_offset;
3807 current_offset += current_bb->max_length;
3811 if (cfg->opt & MONO_OPT_LOOP) {
3812 int pad, align = LOOP_ALIGNMENT;
3813 /* set alignment depending on cpu */
3814 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3816 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3817 amd64_padding (code, pad);
3818 cfg->code_len += pad;
3819 bb->native_offset = cfg->code_len;
3823 #if defined(__native_client_codegen__)
3824 /* For Native Client, all indirect call/jump targets must be */
3825 /* 32-byte aligned. Exception handler blocks are jumped to */
3826 /* indirectly as well. */
3827 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3828 (bb->flags & BB_EXCEPTION_HANDLER);
3830 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3831 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3832 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3833 cfg->code_len += pad;
3834 bb->native_offset = cfg->code_len;
3836 #endif /*__native_client_codegen__*/
3838 if (cfg->verbose_level > 2)
3839 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3841 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3842 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3843 g_assert (!cfg->compile_aot);
3845 cov->data [bb->dfn].cil_code = bb->cil_code;
3846 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3847 /* this is not thread save, but good enough */
3848 amd64_inc_membase (code, AMD64_R11, 0);
3851 offset = code - cfg->native_code;
3853 mono_debug_open_block (cfg, bb, offset);
3855 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3856 x86_breakpoint (code);
3858 MONO_BB_FOR_EACH_INS (bb, ins) {
3859 offset = code - cfg->native_code;
3861 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3863 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3865 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3866 cfg->code_size *= 2;
3867 cfg->native_code = mono_realloc_native_code(cfg);
3868 code = cfg->native_code + offset;
3869 cfg->stat_code_reallocs++;
3872 if (cfg->debug_info)
3873 mono_debug_record_line_number (cfg, ins, offset);
3875 switch (ins->opcode) {
3877 amd64_mul_reg (code, ins->sreg2, TRUE);
3880 amd64_mul_reg (code, ins->sreg2, FALSE);
3882 case OP_X86_SETEQ_MEMBASE:
3883 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3885 case OP_STOREI1_MEMBASE_IMM:
3886 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3888 case OP_STOREI2_MEMBASE_IMM:
3889 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3891 case OP_STOREI4_MEMBASE_IMM:
3892 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3894 case OP_STOREI1_MEMBASE_REG:
3895 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3897 case OP_STOREI2_MEMBASE_REG:
3898 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3900 /* In AMD64 NaCl, pointers are 4 bytes, */
3901 /* so STORE_* != STOREI8_*. Likewise below. */
3902 case OP_STORE_MEMBASE_REG:
3903 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3905 case OP_STOREI8_MEMBASE_REG:
3906 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3908 case OP_STOREI4_MEMBASE_REG:
3909 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3911 case OP_STORE_MEMBASE_IMM:
3912 #ifndef __native_client_codegen__
3913 /* In NaCl, this could be a PCONST type, which could */
3914 /* mean a pointer type was copied directly into the */
3915 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3916 /* the value would be 0x00000000FFFFFFFF which is */
3917 /* not proper for an imm32 unless you cast it. */
3918 g_assert (amd64_is_imm32 (ins->inst_imm));
3920 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3922 case OP_STOREI8_MEMBASE_IMM:
3923 g_assert (amd64_is_imm32 (ins->inst_imm));
3924 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3927 #ifdef __mono_ilp32__
3928 /* In ILP32, pointers are 4 bytes, so separate these */
3929 /* cases, use literal 8 below where we really want 8 */
3930 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3931 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3935 // FIXME: Decompose this earlier
3936 if (amd64_is_imm32 (ins->inst_imm))
3937 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3939 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3940 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3944 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3945 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3948 // FIXME: Decompose this earlier
3949 if (amd64_is_imm32 (ins->inst_imm))
3950 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3952 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3953 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3957 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3958 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3961 /* For NaCl, pointers are 4 bytes, so separate these */
3962 /* cases, use literal 8 below where we really want 8 */
3963 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3964 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3966 case OP_LOAD_MEMBASE:
3967 g_assert (amd64_is_imm32 (ins->inst_offset));
3968 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3970 case OP_LOADI8_MEMBASE:
3971 /* Use literal 8 instead of sizeof pointer or */
3972 /* register, we really want 8 for this opcode */
3973 g_assert (amd64_is_imm32 (ins->inst_offset));
3974 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3976 case OP_LOADI4_MEMBASE:
3977 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3979 case OP_LOADU4_MEMBASE:
3980 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3982 case OP_LOADU1_MEMBASE:
3983 /* The cpu zero extends the result into 64 bits */
3984 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3986 case OP_LOADI1_MEMBASE:
3987 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3989 case OP_LOADU2_MEMBASE:
3990 /* The cpu zero extends the result into 64 bits */
3991 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3993 case OP_LOADI2_MEMBASE:
3994 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3996 case OP_AMD64_LOADI8_MEMINDEX:
3997 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3999 case OP_LCONV_TO_I1:
4000 case OP_ICONV_TO_I1:
4002 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4004 case OP_LCONV_TO_I2:
4005 case OP_ICONV_TO_I2:
4007 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4009 case OP_LCONV_TO_U1:
4010 case OP_ICONV_TO_U1:
4011 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4013 case OP_LCONV_TO_U2:
4014 case OP_ICONV_TO_U2:
4015 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4018 /* Clean out the upper word */
4019 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4022 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4026 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4028 case OP_COMPARE_IMM:
4029 #if defined(__mono_ilp32__)
4030 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4031 g_assert (amd64_is_imm32 (ins->inst_imm));
4032 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4035 case OP_LCOMPARE_IMM:
4036 g_assert (amd64_is_imm32 (ins->inst_imm));
4037 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4039 case OP_X86_COMPARE_REG_MEMBASE:
4040 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4042 case OP_X86_TEST_NULL:
4043 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4045 case OP_AMD64_TEST_NULL:
4046 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4049 case OP_X86_ADD_REG_MEMBASE:
4050 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4052 case OP_X86_SUB_REG_MEMBASE:
4053 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4055 case OP_X86_AND_REG_MEMBASE:
4056 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4058 case OP_X86_OR_REG_MEMBASE:
4059 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4061 case OP_X86_XOR_REG_MEMBASE:
4062 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4065 case OP_X86_ADD_MEMBASE_IMM:
4066 /* FIXME: Make a 64 version too */
4067 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4069 case OP_X86_SUB_MEMBASE_IMM:
4070 g_assert (amd64_is_imm32 (ins->inst_imm));
4071 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4073 case OP_X86_AND_MEMBASE_IMM:
4074 g_assert (amd64_is_imm32 (ins->inst_imm));
4075 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4077 case OP_X86_OR_MEMBASE_IMM:
4078 g_assert (amd64_is_imm32 (ins->inst_imm));
4079 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4081 case OP_X86_XOR_MEMBASE_IMM:
4082 g_assert (amd64_is_imm32 (ins->inst_imm));
4083 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4085 case OP_X86_ADD_MEMBASE_REG:
4086 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4088 case OP_X86_SUB_MEMBASE_REG:
4089 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4091 case OP_X86_AND_MEMBASE_REG:
4092 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4094 case OP_X86_OR_MEMBASE_REG:
4095 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4097 case OP_X86_XOR_MEMBASE_REG:
4098 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4100 case OP_X86_INC_MEMBASE:
4101 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4103 case OP_X86_INC_REG:
4104 amd64_inc_reg_size (code, ins->dreg, 4);
4106 case OP_X86_DEC_MEMBASE:
4107 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4109 case OP_X86_DEC_REG:
4110 amd64_dec_reg_size (code, ins->dreg, 4);
4112 case OP_X86_MUL_REG_MEMBASE:
4113 case OP_X86_MUL_MEMBASE_REG:
4114 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4116 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4117 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4119 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4120 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4122 case OP_AMD64_COMPARE_MEMBASE_REG:
4123 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4125 case OP_AMD64_COMPARE_MEMBASE_IMM:
4126 g_assert (amd64_is_imm32 (ins->inst_imm));
4127 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4129 case OP_X86_COMPARE_MEMBASE8_IMM:
4130 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4132 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4133 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4135 case OP_AMD64_COMPARE_REG_MEMBASE:
4136 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4139 case OP_AMD64_ADD_REG_MEMBASE:
4140 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4142 case OP_AMD64_SUB_REG_MEMBASE:
4143 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4145 case OP_AMD64_AND_REG_MEMBASE:
4146 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4148 case OP_AMD64_OR_REG_MEMBASE:
4149 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4151 case OP_AMD64_XOR_REG_MEMBASE:
4152 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4155 case OP_AMD64_ADD_MEMBASE_REG:
4156 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4158 case OP_AMD64_SUB_MEMBASE_REG:
4159 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4161 case OP_AMD64_AND_MEMBASE_REG:
4162 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4164 case OP_AMD64_OR_MEMBASE_REG:
4165 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4167 case OP_AMD64_XOR_MEMBASE_REG:
4168 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4171 case OP_AMD64_ADD_MEMBASE_IMM:
4172 g_assert (amd64_is_imm32 (ins->inst_imm));
4173 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4175 case OP_AMD64_SUB_MEMBASE_IMM:
4176 g_assert (amd64_is_imm32 (ins->inst_imm));
4177 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4179 case OP_AMD64_AND_MEMBASE_IMM:
4180 g_assert (amd64_is_imm32 (ins->inst_imm));
4181 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4183 case OP_AMD64_OR_MEMBASE_IMM:
4184 g_assert (amd64_is_imm32 (ins->inst_imm));
4185 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4187 case OP_AMD64_XOR_MEMBASE_IMM:
4188 g_assert (amd64_is_imm32 (ins->inst_imm));
4189 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4193 amd64_breakpoint (code);
4195 case OP_RELAXED_NOP:
4196 x86_prefix (code, X86_REP_PREFIX);
4204 case OP_DUMMY_STORE:
4205 case OP_DUMMY_ICONST:
4206 case OP_DUMMY_R8CONST:
4207 case OP_NOT_REACHED:
4210 case OP_SEQ_POINT: {
4214 * Read from the single stepping trigger page. This will cause a
4215 * SIGSEGV when single stepping is enabled.
4216 * We do this _before_ the breakpoint, so single stepping after
4217 * a breakpoint is hit will step to the next IL offset.
4219 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4220 MonoInst *var = cfg->arch.ss_trigger_page_var;
4222 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4223 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4227 * This is the address which is saved in seq points,
4229 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4231 if (cfg->compile_aot) {
4232 guint32 offset = code - cfg->native_code;
4234 MonoInst *info_var = cfg->arch.seq_point_info_var;
4237 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4238 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4239 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4240 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4241 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4244 * A placeholder for a possible breakpoint inserted by
4245 * mono_arch_set_breakpoint ().
4247 for (i = 0; i < breakpoint_size; ++i)
4251 * Add an additional nop so skipping the bp doesn't cause the ip to point
4252 * to another IL offset.
4260 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4263 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4267 g_assert (amd64_is_imm32 (ins->inst_imm));
4268 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4271 g_assert (amd64_is_imm32 (ins->inst_imm));
4272 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4277 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4280 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4284 g_assert (amd64_is_imm32 (ins->inst_imm));
4285 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4288 g_assert (amd64_is_imm32 (ins->inst_imm));
4289 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4292 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4296 g_assert (amd64_is_imm32 (ins->inst_imm));
4297 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4300 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4305 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4307 switch (ins->inst_imm) {
4311 if (ins->dreg != ins->sreg1)
4312 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4313 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4316 /* LEA r1, [r2 + r2*2] */
4317 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4320 /* LEA r1, [r2 + r2*4] */
4321 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4324 /* LEA r1, [r2 + r2*2] */
4326 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4327 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4330 /* LEA r1, [r2 + r2*8] */
4331 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4334 /* LEA r1, [r2 + r2*4] */
4336 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4337 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4340 /* LEA r1, [r2 + r2*2] */
4342 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4343 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4346 /* LEA r1, [r2 + r2*4] */
4347 /* LEA r1, [r1 + r1*4] */
4348 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4349 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4352 /* LEA r1, [r2 + r2*4] */
4354 /* LEA r1, [r1 + r1*4] */
4355 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4356 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4357 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4360 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4367 #if defined( __native_client_codegen__ )
4368 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4369 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4371 /* Regalloc magic makes the div/rem cases the same */
4372 if (ins->sreg2 == AMD64_RDX) {
4373 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4375 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4378 amd64_div_reg (code, ins->sreg2, TRUE);
4383 #if defined( __native_client_codegen__ )
4384 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4385 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4387 if (ins->sreg2 == AMD64_RDX) {
4388 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4389 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4390 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4392 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4393 amd64_div_reg (code, ins->sreg2, FALSE);
4398 #if defined( __native_client_codegen__ )
4399 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4400 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4402 if (ins->sreg2 == AMD64_RDX) {
4403 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4404 amd64_cdq_size (code, 4);
4405 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4407 amd64_cdq_size (code, 4);
4408 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4413 #if defined( __native_client_codegen__ )
4414 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4415 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4417 if (ins->sreg2 == AMD64_RDX) {
4418 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4419 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4420 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4422 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4423 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4427 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4428 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4431 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4435 g_assert (amd64_is_imm32 (ins->inst_imm));
4436 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4439 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4443 g_assert (amd64_is_imm32 (ins->inst_imm));
4444 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4447 g_assert (ins->sreg2 == AMD64_RCX);
4448 amd64_shift_reg (code, X86_SHL, ins->dreg);
4451 g_assert (ins->sreg2 == AMD64_RCX);
4452 amd64_shift_reg (code, X86_SAR, ins->dreg);
4455 g_assert (amd64_is_imm32 (ins->inst_imm));
4456 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4459 g_assert (amd64_is_imm32 (ins->inst_imm));
4460 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4463 g_assert (amd64_is_imm32 (ins->inst_imm));
4464 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4466 case OP_LSHR_UN_IMM:
4467 g_assert (amd64_is_imm32 (ins->inst_imm));
4468 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4471 g_assert (ins->sreg2 == AMD64_RCX);
4472 amd64_shift_reg (code, X86_SHR, ins->dreg);
4475 g_assert (amd64_is_imm32 (ins->inst_imm));
4476 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4479 g_assert (amd64_is_imm32 (ins->inst_imm));
4480 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4485 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4488 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4491 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4494 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4498 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4501 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4504 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4507 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4510 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4513 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4516 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4519 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4522 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4525 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4528 amd64_neg_reg_size (code, ins->sreg1, 4);
4531 amd64_not_reg_size (code, ins->sreg1, 4);
4534 g_assert (ins->sreg2 == AMD64_RCX);
4535 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4538 g_assert (ins->sreg2 == AMD64_RCX);
4539 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4542 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4544 case OP_ISHR_UN_IMM:
4545 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4548 g_assert (ins->sreg2 == AMD64_RCX);
4549 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4552 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4555 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4558 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4559 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4561 case OP_IMUL_OVF_UN:
4562 case OP_LMUL_OVF_UN: {
4563 /* the mul operation and the exception check should most likely be split */
4564 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4565 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4566 /*g_assert (ins->sreg2 == X86_EAX);
4567 g_assert (ins->dreg == X86_EAX);*/
4568 if (ins->sreg2 == X86_EAX) {
4569 non_eax_reg = ins->sreg1;
4570 } else if (ins->sreg1 == X86_EAX) {
4571 non_eax_reg = ins->sreg2;
4573 /* no need to save since we're going to store to it anyway */
4574 if (ins->dreg != X86_EAX) {
4576 amd64_push_reg (code, X86_EAX);
4578 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4579 non_eax_reg = ins->sreg2;
4581 if (ins->dreg == X86_EDX) {
4584 amd64_push_reg (code, X86_EAX);
4588 amd64_push_reg (code, X86_EDX);
4590 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4591 /* save before the check since pop and mov don't change the flags */
4592 if (ins->dreg != X86_EAX)
4593 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4595 amd64_pop_reg (code, X86_EDX);
4597 amd64_pop_reg (code, X86_EAX);
4598 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4602 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4604 case OP_ICOMPARE_IMM:
4605 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4627 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4635 case OP_CMOV_INE_UN:
4636 case OP_CMOV_IGE_UN:
4637 case OP_CMOV_IGT_UN:
4638 case OP_CMOV_ILE_UN:
4639 case OP_CMOV_ILT_UN:
4645 case OP_CMOV_LNE_UN:
4646 case OP_CMOV_LGE_UN:
4647 case OP_CMOV_LGT_UN:
4648 case OP_CMOV_LLE_UN:
4649 case OP_CMOV_LLT_UN:
4650 g_assert (ins->dreg == ins->sreg1);
4651 /* This needs to operate on 64 bit values */
4652 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4656 amd64_not_reg (code, ins->sreg1);
4659 amd64_neg_reg (code, ins->sreg1);
4664 if ((((guint64)ins->inst_c0) >> 32) == 0)
4665 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4667 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4670 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4671 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4674 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4675 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4678 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4680 case OP_AMD64_SET_XMMREG_R4: {
4681 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4684 case OP_AMD64_SET_XMMREG_R8: {
4685 if (ins->dreg != ins->sreg1)
4686 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4690 MonoCallInst *call = (MonoCallInst*)ins;
4691 int i, save_area_offset;
4693 g_assert (!cfg->method->save_lmf);
4695 /* Restore callee saved registers */
4696 save_area_offset = cfg->arch.reg_save_area_offset;
4697 for (i = 0; i < AMD64_NREG; ++i)
4698 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4699 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4700 save_area_offset += 8;
4703 if (cfg->arch.omit_fp) {
4704 if (cfg->arch.stack_alloc_size)
4705 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4707 if (call->stack_usage)
4710 /* Copy arguments on the stack to our argument area */
4711 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4712 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4713 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4719 offset = code - cfg->native_code;
4720 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4721 if (cfg->compile_aot)
4722 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4724 amd64_set_reg_template (code, AMD64_R11);
4725 amd64_jump_reg (code, AMD64_R11);
4726 ins->flags |= MONO_INST_GC_CALLSITE;
4727 ins->backend.pc_offset = code - cfg->native_code;
4731 /* ensure ins->sreg1 is not NULL */
4732 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4735 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4736 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4745 call = (MonoCallInst*)ins;
4747 * The AMD64 ABI forces callers to know about varargs.
4749 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4750 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4751 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4753 * Since the unmanaged calling convention doesn't contain a
4754 * 'vararg' entry, we have to treat every pinvoke call as a
4755 * potential vararg call.
4759 for (i = 0; i < AMD64_XMM_NREG; ++i)
4760 if (call->used_fregs & (1 << i))
4763 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4765 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4768 if (ins->flags & MONO_INST_HAS_METHOD)
4769 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4771 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4772 ins->flags |= MONO_INST_GC_CALLSITE;
4773 ins->backend.pc_offset = code - cfg->native_code;
4774 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4775 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4776 code = emit_move_return_value (cfg, ins, code);
4782 case OP_VOIDCALL_REG:
4784 call = (MonoCallInst*)ins;
4786 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4787 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4788 ins->sreg1 = AMD64_R11;
4792 * The AMD64 ABI forces callers to know about varargs.
4794 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4795 if (ins->sreg1 == AMD64_RAX) {
4796 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4797 ins->sreg1 = AMD64_R11;
4799 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4800 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4802 * Since the unmanaged calling convention doesn't contain a
4803 * 'vararg' entry, we have to treat every pinvoke call as a
4804 * potential vararg call.
4808 for (i = 0; i < AMD64_XMM_NREG; ++i)
4809 if (call->used_fregs & (1 << i))
4811 if (ins->sreg1 == AMD64_RAX) {
4812 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4813 ins->sreg1 = AMD64_R11;
4816 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4818 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4821 amd64_call_reg (code, ins->sreg1);
4822 ins->flags |= MONO_INST_GC_CALLSITE;
4823 ins->backend.pc_offset = code - cfg->native_code;
4824 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4825 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4826 code = emit_move_return_value (cfg, ins, code);
4828 case OP_FCALL_MEMBASE:
4829 case OP_LCALL_MEMBASE:
4830 case OP_VCALL_MEMBASE:
4831 case OP_VCALL2_MEMBASE:
4832 case OP_VOIDCALL_MEMBASE:
4833 case OP_CALL_MEMBASE:
4834 call = (MonoCallInst*)ins;
4836 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4837 ins->flags |= MONO_INST_GC_CALLSITE;
4838 ins->backend.pc_offset = code - cfg->native_code;
4839 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4840 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4841 code = emit_move_return_value (cfg, ins, code);
4845 MonoInst *var = cfg->dyn_call_var;
4847 g_assert (var->opcode == OP_REGOFFSET);
4849 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4850 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4852 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4854 /* Save args buffer */
4855 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4857 /* Set argument registers */
4858 for (i = 0; i < PARAM_REGS; ++i)
4859 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4862 amd64_call_reg (code, AMD64_R10);
4864 ins->flags |= MONO_INST_GC_CALLSITE;
4865 ins->backend.pc_offset = code - cfg->native_code;
4868 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4869 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4872 case OP_AMD64_SAVE_SP_TO_LMF: {
4873 MonoInst *lmf_var = cfg->lmf_var;
4874 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4878 g_assert (!cfg->arch.no_pushes);
4879 amd64_push_reg (code, ins->sreg1);
4881 case OP_X86_PUSH_IMM:
4882 g_assert (!cfg->arch.no_pushes);
4883 g_assert (amd64_is_imm32 (ins->inst_imm));
4884 amd64_push_imm (code, ins->inst_imm);
4886 case OP_X86_PUSH_MEMBASE:
4887 g_assert (!cfg->arch.no_pushes);
4888 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4890 case OP_X86_PUSH_OBJ: {
4891 int size = ALIGN_TO (ins->inst_imm, 8);
4893 g_assert (!cfg->arch.no_pushes);
4895 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4896 amd64_push_reg (code, AMD64_RDI);
4897 amd64_push_reg (code, AMD64_RSI);
4898 amd64_push_reg (code, AMD64_RCX);
4899 if (ins->inst_offset)
4900 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4902 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4903 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4904 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4906 amd64_prefix (code, X86_REP_PREFIX);
4908 amd64_pop_reg (code, AMD64_RCX);
4909 amd64_pop_reg (code, AMD64_RSI);
4910 amd64_pop_reg (code, AMD64_RDI);
4914 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4916 case OP_X86_LEA_MEMBASE:
4917 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4920 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4923 /* keep alignment */
4924 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4925 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4926 code = mono_emit_stack_alloc (cfg, code, ins);
4927 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4928 if (cfg->param_area && cfg->arch.no_pushes)
4929 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4931 case OP_LOCALLOC_IMM: {
4932 guint32 size = ins->inst_imm;
4933 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4935 if (ins->flags & MONO_INST_INIT) {
4939 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4940 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4942 for (i = 0; i < size; i += 8)
4943 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4944 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4946 amd64_mov_reg_imm (code, ins->dreg, size);
4947 ins->sreg1 = ins->dreg;
4949 code = mono_emit_stack_alloc (cfg, code, ins);
4950 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4953 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4954 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4956 if (cfg->param_area && cfg->arch.no_pushes)
4957 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4961 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4962 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4963 (gpointer)"mono_arch_throw_exception", FALSE);
4964 ins->flags |= MONO_INST_GC_CALLSITE;
4965 ins->backend.pc_offset = code - cfg->native_code;
4969 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4970 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4971 (gpointer)"mono_arch_rethrow_exception", FALSE);
4972 ins->flags |= MONO_INST_GC_CALLSITE;
4973 ins->backend.pc_offset = code - cfg->native_code;
4976 case OP_CALL_HANDLER:
4978 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4979 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4980 amd64_call_imm (code, 0);
4981 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4982 /* Restore stack alignment */
4983 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4985 case OP_START_HANDLER: {
4986 /* Even though we're saving RSP, use sizeof */
4987 /* gpointer because spvar is of type IntPtr */
4988 /* see: mono_create_spvar_for_region */
4989 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4990 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4992 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4993 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4994 cfg->param_area && cfg->arch.no_pushes) {
4995 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4999 case OP_ENDFINALLY: {
5000 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5001 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5005 case OP_ENDFILTER: {
5006 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5007 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5008 /* The local allocator will put the result into RAX */
5014 ins->inst_c0 = code - cfg->native_code;
5017 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5018 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5020 if (ins->inst_target_bb->native_offset) {
5021 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5023 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5024 if ((cfg->opt & MONO_OPT_BRANCH) &&
5025 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5026 x86_jump8 (code, 0);
5028 x86_jump32 (code, 0);
5032 amd64_jump_reg (code, ins->sreg1);
5055 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5056 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5058 case OP_COND_EXC_EQ:
5059 case OP_COND_EXC_NE_UN:
5060 case OP_COND_EXC_LT:
5061 case OP_COND_EXC_LT_UN:
5062 case OP_COND_EXC_GT:
5063 case OP_COND_EXC_GT_UN:
5064 case OP_COND_EXC_GE:
5065 case OP_COND_EXC_GE_UN:
5066 case OP_COND_EXC_LE:
5067 case OP_COND_EXC_LE_UN:
5068 case OP_COND_EXC_IEQ:
5069 case OP_COND_EXC_INE_UN:
5070 case OP_COND_EXC_ILT:
5071 case OP_COND_EXC_ILT_UN:
5072 case OP_COND_EXC_IGT:
5073 case OP_COND_EXC_IGT_UN:
5074 case OP_COND_EXC_IGE:
5075 case OP_COND_EXC_IGE_UN:
5076 case OP_COND_EXC_ILE:
5077 case OP_COND_EXC_ILE_UN:
5078 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5080 case OP_COND_EXC_OV:
5081 case OP_COND_EXC_NO:
5083 case OP_COND_EXC_NC:
5084 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5085 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5087 case OP_COND_EXC_IOV:
5088 case OP_COND_EXC_INO:
5089 case OP_COND_EXC_IC:
5090 case OP_COND_EXC_INC:
5091 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5092 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5095 /* floating point opcodes */
5097 double d = *(double *)ins->inst_p0;
5099 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5100 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5103 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5104 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5109 float f = *(float *)ins->inst_p0;
5111 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5112 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5115 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5116 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5117 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5121 case OP_STORER8_MEMBASE_REG:
5122 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5124 case OP_LOADR8_MEMBASE:
5125 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5127 case OP_STORER4_MEMBASE_REG:
5128 /* This requires a double->single conversion */
5129 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5130 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5132 case OP_LOADR4_MEMBASE:
5133 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5134 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5136 case OP_ICONV_TO_R4:
5137 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5138 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5140 case OP_ICONV_TO_R8:
5141 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5143 case OP_LCONV_TO_R4:
5144 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5145 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5147 case OP_LCONV_TO_R8:
5148 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5150 case OP_FCONV_TO_R4:
5151 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5152 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5154 case OP_FCONV_TO_I1:
5155 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5157 case OP_FCONV_TO_U1:
5158 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5160 case OP_FCONV_TO_I2:
5161 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5163 case OP_FCONV_TO_U2:
5164 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5166 case OP_FCONV_TO_U4:
5167 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5169 case OP_FCONV_TO_I4:
5171 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5173 case OP_FCONV_TO_I8:
5174 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5176 case OP_LCONV_TO_R_UN: {
5179 /* Based on gcc code */
5180 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5181 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5184 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5185 br [1] = code; x86_jump8 (code, 0);
5186 amd64_patch (br [0], code);
5189 /* Save to the red zone */
5190 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5191 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5192 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5193 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5194 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5195 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5196 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5197 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5198 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5200 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5201 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5202 amd64_patch (br [1], code);
5205 case OP_LCONV_TO_OVF_U4:
5206 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5207 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5208 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5210 case OP_LCONV_TO_OVF_I4_UN:
5211 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5212 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5213 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5216 if (ins->dreg != ins->sreg1)
5217 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5220 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5223 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5226 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5229 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5232 static double r8_0 = -0.0;
5234 g_assert (ins->sreg1 == ins->dreg);
5236 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5237 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5241 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5244 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5247 static guint64 d = 0x7fffffffffffffffUL;
5249 g_assert (ins->sreg1 == ins->dreg);
5251 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5252 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5256 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5259 g_assert (cfg->opt & MONO_OPT_CMOV);
5260 g_assert (ins->dreg == ins->sreg1);
5261 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5262 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5265 g_assert (cfg->opt & MONO_OPT_CMOV);
5266 g_assert (ins->dreg == ins->sreg1);
5267 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5268 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5271 g_assert (cfg->opt & MONO_OPT_CMOV);
5272 g_assert (ins->dreg == ins->sreg1);
5273 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5274 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5277 g_assert (cfg->opt & MONO_OPT_CMOV);
5278 g_assert (ins->dreg == ins->sreg1);
5279 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5280 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5283 g_assert (cfg->opt & MONO_OPT_CMOV);
5284 g_assert (ins->dreg == ins->sreg1);
5285 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5286 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5289 g_assert (cfg->opt & MONO_OPT_CMOV);
5290 g_assert (ins->dreg == ins->sreg1);
5291 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5292 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5295 g_assert (cfg->opt & MONO_OPT_CMOV);
5296 g_assert (ins->dreg == ins->sreg1);
5297 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5298 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5301 g_assert (cfg->opt & MONO_OPT_CMOV);
5302 g_assert (ins->dreg == ins->sreg1);
5303 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5304 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5310 * The two arguments are swapped because the fbranch instructions
5311 * depend on this for the non-sse case to work.
5313 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5317 /* zeroing the register at the start results in
5318 * shorter and faster code (we can also remove the widening op)
5320 guchar *unordered_check;
5321 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5322 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5323 unordered_check = code;
5324 x86_branch8 (code, X86_CC_P, 0, FALSE);
5326 if (ins->opcode == OP_FCEQ) {
5327 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5328 amd64_patch (unordered_check, code);
5330 guchar *jump_to_end;
5331 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5333 x86_jump8 (code, 0);
5334 amd64_patch (unordered_check, code);
5335 amd64_inc_reg (code, ins->dreg);
5336 amd64_patch (jump_to_end, code);
5342 /* zeroing the register at the start results in
5343 * shorter and faster code (we can also remove the widening op)
5345 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5346 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5347 if (ins->opcode == OP_FCLT_UN) {
5348 guchar *unordered_check = code;
5349 guchar *jump_to_end;
5350 x86_branch8 (code, X86_CC_P, 0, FALSE);
5351 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5353 x86_jump8 (code, 0);
5354 amd64_patch (unordered_check, code);
5355 amd64_inc_reg (code, ins->dreg);
5356 amd64_patch (jump_to_end, code);
5358 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5362 guchar *unordered_check;
5363 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5364 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5365 unordered_check = code;
5366 x86_branch8 (code, X86_CC_P, 0, FALSE);
5367 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5368 amd64_patch (unordered_check, code);
5373 /* zeroing the register at the start results in
5374 * shorter and faster code (we can also remove the widening op)
5376 guchar *unordered_check;
5377 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5378 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5379 if (ins->opcode == OP_FCGT) {
5380 unordered_check = code;
5381 x86_branch8 (code, X86_CC_P, 0, FALSE);
5382 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5383 amd64_patch (unordered_check, code);
5385 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5390 guchar *unordered_check;
5391 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5392 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5393 unordered_check = code;
5394 x86_branch8 (code, X86_CC_P, 0, FALSE);
5395 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5396 amd64_patch (unordered_check, code);
5400 case OP_FCLT_MEMBASE:
5401 case OP_FCGT_MEMBASE:
5402 case OP_FCLT_UN_MEMBASE:
5403 case OP_FCGT_UN_MEMBASE:
5404 case OP_FCEQ_MEMBASE: {
5405 guchar *unordered_check, *jump_to_end;
5408 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5409 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5411 switch (ins->opcode) {
5412 case OP_FCEQ_MEMBASE:
5413 x86_cond = X86_CC_EQ;
5415 case OP_FCLT_MEMBASE:
5416 case OP_FCLT_UN_MEMBASE:
5417 x86_cond = X86_CC_LT;
5419 case OP_FCGT_MEMBASE:
5420 case OP_FCGT_UN_MEMBASE:
5421 x86_cond = X86_CC_GT;
5424 g_assert_not_reached ();
5427 unordered_check = code;
5428 x86_branch8 (code, X86_CC_P, 0, FALSE);
5429 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5431 switch (ins->opcode) {
5432 case OP_FCEQ_MEMBASE:
5433 case OP_FCLT_MEMBASE:
5434 case OP_FCGT_MEMBASE:
5435 amd64_patch (unordered_check, code);
5437 case OP_FCLT_UN_MEMBASE:
5438 case OP_FCGT_UN_MEMBASE:
5440 x86_jump8 (code, 0);
5441 amd64_patch (unordered_check, code);
5442 amd64_inc_reg (code, ins->dreg);
5443 amd64_patch (jump_to_end, code);
5451 guchar *jump = code;
5452 x86_branch8 (code, X86_CC_P, 0, TRUE);
5453 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5454 amd64_patch (jump, code);
5458 /* Branch if C013 != 100 */
5459 /* branch if !ZF or (PF|CF) */
5460 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5461 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5462 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5465 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5468 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5469 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5473 if (ins->opcode == OP_FBGT) {
5476 /* skip branch if C1=1 */
5478 x86_branch8 (code, X86_CC_P, 0, FALSE);
5479 /* branch if (C0 | C3) = 1 */
5480 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5481 amd64_patch (br1, code);
5484 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5488 /* Branch if C013 == 100 or 001 */
5491 /* skip branch if C1=1 */
5493 x86_branch8 (code, X86_CC_P, 0, FALSE);
5494 /* branch if (C0 | C3) = 1 */
5495 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5496 amd64_patch (br1, code);
5500 /* Branch if C013 == 000 */
5501 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5504 /* Branch if C013=000 or 100 */
5507 /* skip branch if C1=1 */
5509 x86_branch8 (code, X86_CC_P, 0, FALSE);
5510 /* branch if C0=0 */
5511 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5512 amd64_patch (br1, code);
5516 /* Branch if C013 != 001 */
5517 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5518 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5521 /* Transfer value to the fp stack */
5522 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5523 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5524 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5526 amd64_push_reg (code, AMD64_RAX);
5528 amd64_fnstsw (code);
5529 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5530 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5531 amd64_pop_reg (code, AMD64_RAX);
5532 amd64_fstp (code, 0);
5533 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5534 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5537 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5540 case OP_TLS_GET_REG:
5541 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5544 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5547 case OP_TLS_SET_REG: {
5548 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5551 case OP_MEMORY_BARRIER: {
5552 switch (ins->backend.memory_barrier_kind) {
5553 case StoreLoadBarrier:
5555 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5556 x86_prefix (code, X86_LOCK_PREFIX);
5557 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5562 case OP_ATOMIC_ADD_I4:
5563 case OP_ATOMIC_ADD_I8: {
5564 int dreg = ins->dreg;
5565 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5567 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5570 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5571 amd64_prefix (code, X86_LOCK_PREFIX);
5572 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5573 /* dreg contains the old value, add with sreg2 value */
5574 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5576 if (ins->dreg != dreg)
5577 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5581 case OP_ATOMIC_EXCHANGE_I4:
5582 case OP_ATOMIC_EXCHANGE_I8: {
5584 int sreg2 = ins->sreg2;
5585 int breg = ins->inst_basereg;
5587 gboolean need_push = FALSE, rdx_pushed = FALSE;
5589 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5595 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5596 * an explanation of how this works.
5599 /* cmpxchg uses eax as comperand, need to make sure we can use it
5600 * hack to overcome limits in x86 reg allocator
5601 * (req: dreg == eax and sreg2 != eax and breg != eax)
5603 g_assert (ins->dreg == AMD64_RAX);
5605 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5606 /* Highly unlikely, but possible */
5609 /* The pushes invalidate rsp */
5610 if ((breg == AMD64_RAX) || need_push) {
5611 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5615 /* We need the EAX reg for the comparand */
5616 if (ins->sreg2 == AMD64_RAX) {
5617 if (breg != AMD64_R11) {
5618 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5621 g_assert (need_push);
5622 amd64_push_reg (code, AMD64_RDX);
5623 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5629 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5631 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5632 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5633 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5634 amd64_patch (br [1], br [0]);
5637 amd64_pop_reg (code, AMD64_RDX);
5641 case OP_ATOMIC_CAS_I4:
5642 case OP_ATOMIC_CAS_I8: {
5645 if (ins->opcode == OP_ATOMIC_CAS_I8)
5651 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5652 * an explanation of how this works.
5654 g_assert (ins->sreg3 == AMD64_RAX);
5655 g_assert (ins->sreg1 != AMD64_RAX);
5656 g_assert (ins->sreg1 != ins->sreg2);
5658 amd64_prefix (code, X86_LOCK_PREFIX);
5659 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5661 if (ins->dreg != AMD64_RAX)
5662 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5665 case OP_CARD_TABLE_WBARRIER: {
5666 int ptr = ins->sreg1;
5667 int value = ins->sreg2;
5669 int nursery_shift, card_table_shift;
5670 gpointer card_table_mask;
5671 size_t nursery_size;
5673 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5674 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5675 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5677 /*If either point to the stack we can simply avoid the WB. This happens due to
5678 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5680 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5684 * We need one register we can clobber, we choose EDX and make sreg1
5685 * fixed EAX to work around limitations in the local register allocator.
5686 * sreg2 might get allocated to EDX, but that is not a problem since
5687 * we use it before clobbering EDX.
5689 g_assert (ins->sreg1 == AMD64_RAX);
5692 * This is the code we produce:
5695 * edx >>= nursery_shift
5696 * cmp edx, (nursery_start >> nursery_shift)
5699 * edx >>= card_table_shift
5705 if (mono_gc_card_table_nursery_check ()) {
5706 if (value != AMD64_RDX)
5707 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5708 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5709 if (shifted_nursery_start >> 31) {
5711 * The value we need to compare against is 64 bits, so we need
5712 * another spare register. We use RBX, which we save and
5715 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5716 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5717 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5718 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5720 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5722 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5724 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5725 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5726 if (card_table_mask)
5727 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5729 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5730 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5732 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5734 if (mono_gc_card_table_nursery_check ())
5735 x86_patch (br, code);
5738 #ifdef MONO_ARCH_SIMD_INTRINSICS
5739 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5741 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5744 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5747 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5750 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5753 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5756 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5759 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5760 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5763 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5766 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5769 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5772 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5775 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5778 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5781 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5784 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5787 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5790 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5793 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5796 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5799 case OP_PSHUFLEW_HIGH:
5800 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5801 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5803 case OP_PSHUFLEW_LOW:
5804 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5805 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5808 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5809 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5812 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5813 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5816 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5817 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5821 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5824 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5827 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5830 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5833 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5836 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5839 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5840 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5843 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5846 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5849 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5852 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5855 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5858 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5861 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5864 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5867 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5870 case OP_EXTRACT_MASK:
5871 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5875 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5878 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5881 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5885 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5888 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5891 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5894 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5898 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5901 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5904 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5907 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5911 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5914 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5917 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5921 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5924 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5927 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5931 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5934 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5938 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5941 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5944 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5948 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5951 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5954 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5958 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5961 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5964 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5967 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5971 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5974 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5977 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5980 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5983 case OP_PSUM_ABS_DIFF:
5984 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5987 case OP_UNPACK_LOWB:
5988 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5990 case OP_UNPACK_LOWW:
5991 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5993 case OP_UNPACK_LOWD:
5994 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5996 case OP_UNPACK_LOWQ:
5997 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5999 case OP_UNPACK_LOWPS:
6000 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6002 case OP_UNPACK_LOWPD:
6003 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6006 case OP_UNPACK_HIGHB:
6007 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6009 case OP_UNPACK_HIGHW:
6010 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6012 case OP_UNPACK_HIGHD:
6013 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6015 case OP_UNPACK_HIGHQ:
6016 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6018 case OP_UNPACK_HIGHPS:
6019 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6021 case OP_UNPACK_HIGHPD:
6022 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6026 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6029 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6032 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6035 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6038 case OP_PADDB_SAT_UN:
6039 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6041 case OP_PSUBB_SAT_UN:
6042 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6044 case OP_PADDW_SAT_UN:
6045 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6047 case OP_PSUBW_SAT_UN:
6048 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6052 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6055 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6058 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6061 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6065 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6068 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6071 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6073 case OP_PMULW_HIGH_UN:
6074 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6077 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6081 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6084 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6088 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6091 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6095 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6098 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6102 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6105 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6109 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6112 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6116 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6119 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6123 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6126 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6129 /*TODO: This is appart of the sse spec but not added
6131 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6134 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6139 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6142 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6145 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6148 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6151 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6154 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6157 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6160 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6163 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6166 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6170 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6173 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6177 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6178 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6180 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6185 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6187 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6188 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6192 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6194 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6195 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6196 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6200 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6202 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6205 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6207 case OP_EXTRACTX_U2:
6208 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6210 case OP_INSERTX_U1_SLOW:
6211 /*sreg1 is the extracted ireg (scratch)
6212 /sreg2 is the to be inserted ireg (scratch)
6213 /dreg is the xreg to receive the value*/
6215 /*clear the bits from the extracted word*/
6216 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6217 /*shift the value to insert if needed*/
6218 if (ins->inst_c0 & 1)
6219 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6220 /*join them together*/
6221 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6222 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6224 case OP_INSERTX_I4_SLOW:
6225 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6226 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6227 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6229 case OP_INSERTX_I8_SLOW:
6230 amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6232 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6234 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6237 case OP_INSERTX_R4_SLOW:
6238 switch (ins->inst_c0) {
6240 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6243 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6244 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6245 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6248 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6249 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6250 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6253 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6254 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6255 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6259 case OP_INSERTX_R8_SLOW:
6261 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6263 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6265 case OP_STOREX_MEMBASE_REG:
6266 case OP_STOREX_MEMBASE:
6267 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6269 case OP_LOADX_MEMBASE:
6270 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6272 case OP_LOADX_ALIGNED_MEMBASE:
6273 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6275 case OP_STOREX_ALIGNED_MEMBASE_REG:
6276 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6278 case OP_STOREX_NTA_MEMBASE_REG:
6279 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6281 case OP_PREFETCH_MEMBASE:
6282 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6286 /*FIXME the peephole pass should have killed this*/
6287 if (ins->dreg != ins->sreg1)
6288 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6291 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6293 case OP_ICONV_TO_R8_RAW:
6294 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6295 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6298 case OP_FCONV_TO_R8_X:
6299 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6302 case OP_XCONV_R8_TO_I4:
6303 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6304 switch (ins->backend.source_opcode) {
6305 case OP_FCONV_TO_I1:
6306 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6308 case OP_FCONV_TO_U1:
6309 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6311 case OP_FCONV_TO_I2:
6312 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6314 case OP_FCONV_TO_U2:
6315 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6321 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6322 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6323 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6326 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6327 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6330 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6331 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6334 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6335 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6336 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6339 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6340 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6343 case OP_LIVERANGE_START: {
6344 if (cfg->verbose_level > 1)
6345 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6346 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6349 case OP_LIVERANGE_END: {
6350 if (cfg->verbose_level > 1)
6351 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6352 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6355 case OP_NACL_GC_SAFE_POINT: {
6356 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6357 if (cfg->compile_aot)
6358 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6362 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6363 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6364 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6365 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6366 amd64_patch (br[0], code);
6371 case OP_GC_LIVENESS_DEF:
6372 case OP_GC_LIVENESS_USE:
6373 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6374 ins->backend.pc_offset = code - cfg->native_code;
6376 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6377 ins->backend.pc_offset = code - cfg->native_code;
6378 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6381 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6382 g_assert_not_reached ();
6385 if ((code - cfg->native_code - offset) > max_len) {
6386 #if !defined(__native_client_codegen__)
6387 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6388 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6389 g_assert_not_reached ();
6394 last_offset = offset;
6397 cfg->code_len = code - cfg->native_code;
6400 #endif /* DISABLE_JIT */
6403 mono_arch_register_lowlevel_calls (void)
6405 /* The signature doesn't matter */
6406 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6410 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6412 MonoJumpInfo *patch_info;
6413 gboolean compile_aot = !run_cctors;
6415 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6416 unsigned char *ip = patch_info->ip.i + code;
6417 unsigned char *target;
6420 switch (patch_info->type) {
6421 case MONO_PATCH_INFO_BB:
6422 case MONO_PATCH_INFO_LABEL:
6425 /* No need to patch these */
6430 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6432 switch (patch_info->type) {
6433 case MONO_PATCH_INFO_NONE:
6435 case MONO_PATCH_INFO_METHOD_REL:
6436 case MONO_PATCH_INFO_R8:
6437 case MONO_PATCH_INFO_R4:
6438 g_assert_not_reached ();
6440 case MONO_PATCH_INFO_BB:
6447 * Debug code to help track down problems where the target of a near call is
6450 if (amd64_is_near_call (ip)) {
6451 gint64 disp = (guint8*)target - (guint8*)ip;
6453 if (!amd64_is_imm32 (disp)) {
6454 printf ("TYPE: %d\n", patch_info->type);
6455 switch (patch_info->type) {
6456 case MONO_PATCH_INFO_INTERNAL_METHOD:
6457 printf ("V: %s\n", patch_info->data.name);
6459 case MONO_PATCH_INFO_METHOD_JUMP:
6460 case MONO_PATCH_INFO_METHOD:
6461 printf ("V: %s\n", patch_info->data.method->name);
6469 amd64_patch (ip, (gpointer)target);
6476 get_max_epilog_size (MonoCompile *cfg)
6478 int max_epilog_size = 16;
6480 if (cfg->method->save_lmf)
6481 max_epilog_size += 256;
6483 if (mono_jit_trace_calls != NULL)
6484 max_epilog_size += 50;
6486 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6487 max_epilog_size += 50;
6489 max_epilog_size += (AMD64_NREG * 2);
6491 return max_epilog_size;
6495 * This macro is used for testing whenever the unwinder works correctly at every point
6496 * where an async exception can happen.
6498 /* This will generate a SIGSEGV at the given point in the code */
6499 #define async_exc_point(code) do { \
6500 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6501 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6502 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6503 cfg->arch.async_point_count ++; \
6508 mono_arch_emit_prolog (MonoCompile *cfg)
6510 MonoMethod *method = cfg->method;
6512 MonoMethodSignature *sig;
6514 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6517 MonoInst *lmf_var = cfg->lmf_var;
6518 gboolean args_clobbered = FALSE;
6519 gboolean trace = FALSE;
6520 #ifdef __native_client_codegen__
6521 guint alignment_check;
6524 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
6526 #if defined(__default_codegen__)
6527 code = cfg->native_code = g_malloc (cfg->code_size);
6528 #elif defined(__native_client_codegen__)
6529 /* native_code_alloc is not 32-byte aligned, native_code is. */
6530 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6532 /* Align native_code to next nearest kNaclAlignment byte. */
6533 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6534 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6536 code = cfg->native_code;
6538 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6539 g_assert (alignment_check == 0);
6542 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6545 /* Amount of stack space allocated by register saving code */
6548 /* Offset between RSP and the CFA */
6552 * The prolog consists of the following parts:
6554 * - push rbp, mov rbp, rsp
6555 * - save callee saved regs using pushes
6557 * - save rgctx if needed
6558 * - save lmf if needed
6561 * - save rgctx if needed
6562 * - save lmf if needed
6563 * - save callee saved regs using moves
6568 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6569 // IP saved at CFA - 8
6570 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6571 async_exc_point (code);
6572 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6574 if (!cfg->arch.omit_fp) {
6575 amd64_push_reg (code, AMD64_RBP);
6577 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6578 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6579 async_exc_point (code);
6581 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6583 /* These are handled automatically by the stack marking code */
6584 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6586 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6587 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6588 async_exc_point (code);
6590 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6594 /* The param area is always at offset 0 from sp */
6595 /* This needs to be allocated here, since it has to come after the spill area */
6596 if (cfg->arch.no_pushes && cfg->param_area) {
6597 if (cfg->arch.omit_fp)
6599 g_assert_not_reached ();
6600 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6603 if (cfg->arch.omit_fp) {
6605 * On enter, the stack is misaligned by the pushing of the return
6606 * address. It is either made aligned by the pushing of %rbp, or by
6609 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6610 if ((alloc_size % 16) == 0) {
6612 /* Mark the padding slot as NOREF */
6613 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6616 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6617 if (cfg->stack_offset != alloc_size) {
6618 /* Mark the padding slot as NOREF */
6619 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6621 cfg->arch.sp_fp_offset = alloc_size;
6625 cfg->arch.stack_alloc_size = alloc_size;
6627 /* Allocate stack frame */
6629 /* See mono_emit_stack_alloc */
6630 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6631 guint32 remaining_size = alloc_size;
6632 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6633 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6634 guint32 offset = code - cfg->native_code;
6635 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6636 while (required_code_size >= (cfg->code_size - offset))
6637 cfg->code_size *= 2;
6638 cfg->native_code = mono_realloc_native_code (cfg);
6639 code = cfg->native_code + offset;
6640 cfg->stat_code_reallocs++;
6643 while (remaining_size >= 0x1000) {
6644 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6645 if (cfg->arch.omit_fp) {
6646 cfa_offset += 0x1000;
6647 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6649 async_exc_point (code);
6651 if (cfg->arch.omit_fp)
6652 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6655 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6656 remaining_size -= 0x1000;
6658 if (remaining_size) {
6659 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6660 if (cfg->arch.omit_fp) {
6661 cfa_offset += remaining_size;
6662 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6663 async_exc_point (code);
6666 if (cfg->arch.omit_fp)
6667 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6671 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6672 if (cfg->arch.omit_fp) {
6673 cfa_offset += alloc_size;
6674 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6675 async_exc_point (code);
6680 /* Stack alignment check */
6683 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6684 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6685 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6686 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6687 amd64_breakpoint (code);
6691 if (mini_get_debug_options ()->init_stacks) {
6692 /* Fill the stack frame with a dummy value to force deterministic behavior */
6694 /* Save registers to the red zone */
6695 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6696 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6698 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6699 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6700 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6703 #if defined(__default_codegen__)
6704 amd64_prefix (code, X86_REP_PREFIX);
6706 #elif defined(__native_client_codegen__)
6707 /* NaCl stos pseudo-instruction */
6708 amd64_codegen_pre (code);
6709 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6710 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6711 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6712 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6713 amd64_prefix (code, X86_REP_PREFIX);
6715 amd64_codegen_post (code);
6716 #endif /* __native_client_codegen__ */
6718 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6719 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6723 if (method->save_lmf)
6724 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6726 /* Save callee saved registers */
6727 if (cfg->arch.omit_fp) {
6728 save_area_offset = cfg->arch.reg_save_area_offset;
6729 /* Save caller saved registers after sp is adjusted */
6730 /* The registers are saved at the bottom of the frame */
6731 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6733 /* The registers are saved just below the saved rbp */
6734 save_area_offset = cfg->arch.reg_save_area_offset;
6737 for (i = 0; i < AMD64_NREG; ++i) {
6738 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6739 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6741 if (cfg->arch.omit_fp) {
6742 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6743 /* These are handled automatically by the stack marking code */
6744 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6746 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6750 save_area_offset += 8;
6751 async_exc_point (code);
6755 /* store runtime generic context */
6756 if (cfg->rgctx_var) {
6757 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6758 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6760 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6762 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6763 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6766 /* compute max_length in order to use short forward jumps */
6767 max_epilog_size = get_max_epilog_size (cfg);
6768 if (cfg->opt & MONO_OPT_BRANCH) {
6769 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6773 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6775 /* max alignment for loops */
6776 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6777 max_length += LOOP_ALIGNMENT;
6778 #ifdef __native_client_codegen__
6779 /* max alignment for native client */
6780 max_length += kNaClAlignment;
6783 MONO_BB_FOR_EACH_INS (bb, ins) {
6784 #ifdef __native_client_codegen__
6786 int space_in_block = kNaClAlignment -
6787 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6788 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6789 if (space_in_block < max_len && max_len < kNaClAlignment) {
6790 max_length += space_in_block;
6793 #endif /*__native_client_codegen__*/
6794 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6797 /* Take prolog and epilog instrumentation into account */
6798 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6799 max_length += max_epilog_size;
6801 bb->max_length = max_length;
6805 sig = mono_method_signature (method);
6808 cinfo = cfg->arch.cinfo;
6810 if (sig->ret->type != MONO_TYPE_VOID) {
6811 /* Save volatile arguments to the stack */
6812 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6813 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6816 /* Keep this in sync with emit_load_volatile_arguments */
6817 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6818 ArgInfo *ainfo = cinfo->args + i;
6819 gint32 stack_offset;
6822 ins = cfg->args [i];
6824 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6825 /* Unused arguments */
6828 if (sig->hasthis && (i == 0))
6829 arg_type = &mono_defaults.object_class->byval_arg;
6831 arg_type = sig->params [i - sig->hasthis];
6833 stack_offset = ainfo->offset + ARGS_OFFSET;
6835 if (cfg->globalra) {
6836 /* All the other moves are done by the register allocator */
6837 switch (ainfo->storage) {
6838 case ArgInFloatSSEReg:
6839 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6841 case ArgValuetypeInReg:
6842 for (quad = 0; quad < 2; quad ++) {
6843 switch (ainfo->pair_storage [quad]) {
6845 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6847 case ArgInFloatSSEReg:
6848 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6850 case ArgInDoubleSSEReg:
6851 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6856 g_assert_not_reached ();
6867 /* Save volatile arguments to the stack */
6868 if (ins->opcode != OP_REGVAR) {
6869 switch (ainfo->storage) {
6875 if (stack_offset & 0x1)
6877 else if (stack_offset & 0x2)
6879 else if (stack_offset & 0x4)
6884 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6887 * Save the original location of 'this',
6888 * get_generic_info_from_stack_frame () needs this to properly look up
6889 * the argument value during the handling of async exceptions.
6891 if (ins == cfg->args [0]) {
6892 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6893 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6897 case ArgInFloatSSEReg:
6898 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6900 case ArgInDoubleSSEReg:
6901 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6903 case ArgValuetypeInReg:
6904 for (quad = 0; quad < 2; quad ++) {
6905 switch (ainfo->pair_storage [quad]) {
6907 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6909 case ArgInFloatSSEReg:
6910 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6912 case ArgInDoubleSSEReg:
6913 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6918 g_assert_not_reached ();
6922 case ArgValuetypeAddrInIReg:
6923 if (ainfo->pair_storage [0] == ArgInIReg)
6924 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6930 /* Argument allocated to (non-volatile) register */
6931 switch (ainfo->storage) {
6933 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6936 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6939 g_assert_not_reached ();
6942 if (ins == cfg->args [0]) {
6943 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6944 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6949 if (cfg->method->save_lmf)
6950 args_clobbered = TRUE;
6953 args_clobbered = TRUE;
6954 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6957 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6958 args_clobbered = TRUE;
6961 * Optimize the common case of the first bblock making a call with the same
6962 * arguments as the method. This works because the arguments are still in their
6963 * original argument registers.
6964 * FIXME: Generalize this
6966 if (!args_clobbered) {
6967 MonoBasicBlock *first_bb = cfg->bb_entry;
6970 next = mono_bb_first_ins (first_bb);
6971 if (!next && first_bb->next_bb) {
6972 first_bb = first_bb->next_bb;
6973 next = mono_bb_first_ins (first_bb);
6976 if (first_bb->in_count > 1)
6979 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6980 ArgInfo *ainfo = cinfo->args + i;
6981 gboolean match = FALSE;
6983 ins = cfg->args [i];
6984 if (ins->opcode != OP_REGVAR) {
6985 switch (ainfo->storage) {
6987 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6988 if (next->dreg == ainfo->reg) {
6992 next->opcode = OP_MOVE;
6993 next->sreg1 = ainfo->reg;
6994 /* Only continue if the instruction doesn't change argument regs */
6995 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7005 /* Argument allocated to (non-volatile) register */
7006 switch (ainfo->storage) {
7008 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7020 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7027 if (cfg->gen_seq_points) {
7028 MonoInst *info_var = cfg->arch.seq_point_info_var;
7030 /* Initialize seq_point_info_var */
7031 if (cfg->compile_aot) {
7032 /* Initialize the variable from a GOT slot */
7033 /* Same as OP_AOTCONST */
7034 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7035 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7036 g_assert (info_var->opcode == OP_REGOFFSET);
7037 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7040 /* Initialize ss_trigger_page_var */
7041 ins = cfg->arch.ss_trigger_page_var;
7043 g_assert (ins->opcode == OP_REGOFFSET);
7045 if (cfg->compile_aot) {
7046 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7047 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7049 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7051 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7054 cfg->code_len = code - cfg->native_code;
7056 g_assert (cfg->code_len < cfg->code_size);
7062 mono_arch_emit_epilog (MonoCompile *cfg)
7064 MonoMethod *method = cfg->method;
7067 int max_epilog_size;
7069 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7070 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7072 max_epilog_size = get_max_epilog_size (cfg);
7074 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7075 cfg->code_size *= 2;
7076 cfg->native_code = mono_realloc_native_code (cfg);
7077 cfg->stat_code_reallocs++;
7080 code = cfg->native_code + cfg->code_len;
7082 cfg->has_unwind_info_for_epilog = TRUE;
7084 /* Mark the start of the epilog */
7085 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7087 /* Save the uwind state which is needed by the out-of-line code */
7088 mono_emit_unwind_op_remember_state (cfg, code);
7090 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7091 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7093 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7096 if (method->save_lmf) {
7097 /* check if we need to restore protection of the stack after a stack overflow */
7098 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7100 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7101 /* we load the value in a separate instruction: this mechanism may be
7102 * used later as a safer way to do thread interruption
7104 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7105 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7107 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7108 /* note that the call trampoline will preserve eax/edx */
7109 x86_call_reg (code, X86_ECX);
7110 x86_patch (patch, code);
7112 /* FIXME: maybe save the jit tls in the prolog */
7114 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7115 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7119 /* Restore callee saved regs */
7120 for (i = 0; i < AMD64_NREG; ++i) {
7121 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7122 /* Restore only used_int_regs, not arch.saved_iregs */
7123 if (cfg->used_int_regs & (1 << i)) {
7124 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7125 mono_emit_unwind_op_same_value (cfg, code, i);
7126 async_exc_point (code);
7128 save_area_offset += 8;
7132 /* Load returned vtypes into registers if needed */
7133 cinfo = cfg->arch.cinfo;
7134 if (cinfo->ret.storage == ArgValuetypeInReg) {
7135 ArgInfo *ainfo = &cinfo->ret;
7136 MonoInst *inst = cfg->ret;
7138 for (quad = 0; quad < 2; quad ++) {
7139 switch (ainfo->pair_storage [quad]) {
7141 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7143 case ArgInFloatSSEReg:
7144 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7146 case ArgInDoubleSSEReg:
7147 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7152 g_assert_not_reached ();
7157 if (cfg->arch.omit_fp) {
7158 if (cfg->arch.stack_alloc_size) {
7159 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7163 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7165 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7166 async_exc_point (code);
7169 /* Restore the unwind state to be the same as before the epilog */
7170 mono_emit_unwind_op_restore_state (cfg, code);
7172 cfg->code_len = code - cfg->native_code;
7174 g_assert (cfg->code_len < cfg->code_size);
7178 mono_arch_emit_exceptions (MonoCompile *cfg)
7180 MonoJumpInfo *patch_info;
7183 MonoClass *exc_classes [16];
7184 guint8 *exc_throw_start [16], *exc_throw_end [16];
7185 guint32 code_size = 0;
7187 /* Compute needed space */
7188 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7189 if (patch_info->type == MONO_PATCH_INFO_EXC)
7191 if (patch_info->type == MONO_PATCH_INFO_R8)
7192 code_size += 8 + 15; /* sizeof (double) + alignment */
7193 if (patch_info->type == MONO_PATCH_INFO_R4)
7194 code_size += 4 + 15; /* sizeof (float) + alignment */
7195 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7196 code_size += 8 + 7; /*sizeof (void*) + alignment */
7199 #ifdef __native_client_codegen__
7200 /* Give us extra room on Native Client. This could be */
7201 /* more carefully calculated, but bundle alignment makes */
7202 /* it much trickier, so *2 like other places is good. */
7206 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7207 cfg->code_size *= 2;
7208 cfg->native_code = mono_realloc_native_code (cfg);
7209 cfg->stat_code_reallocs++;
7212 code = cfg->native_code + cfg->code_len;
7214 /* add code to raise exceptions */
7216 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7217 switch (patch_info->type) {
7218 case MONO_PATCH_INFO_EXC: {
7219 MonoClass *exc_class;
7223 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7225 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7226 g_assert (exc_class);
7227 throw_ip = patch_info->ip.i;
7229 //x86_breakpoint (code);
7230 /* Find a throw sequence for the same exception class */
7231 for (i = 0; i < nthrows; ++i)
7232 if (exc_classes [i] == exc_class)
7235 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7236 x86_jump_code (code, exc_throw_start [i]);
7237 patch_info->type = MONO_PATCH_INFO_NONE;
7241 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7245 exc_classes [nthrows] = exc_class;
7246 exc_throw_start [nthrows] = code;
7248 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7250 patch_info->type = MONO_PATCH_INFO_NONE;
7252 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7254 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7259 exc_throw_end [nthrows] = code;
7269 g_assert(code < cfg->native_code + cfg->code_size);
7272 /* Handle relocations with RIP relative addressing */
7273 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7274 gboolean remove = FALSE;
7275 guint8 *orig_code = code;
7277 switch (patch_info->type) {
7278 case MONO_PATCH_INFO_R8:
7279 case MONO_PATCH_INFO_R4: {
7280 guint8 *pos, *patch_pos;
7283 /* The SSE opcodes require a 16 byte alignment */
7284 #if defined(__default_codegen__)
7285 code = (guint8*)ALIGN_TO (code, 16);
7286 #elif defined(__native_client_codegen__)
7288 /* Pad this out with HLT instructions */
7289 /* or we can get garbage bytes emitted */
7290 /* which will fail validation */
7291 guint8 *aligned_code;
7292 /* extra align to make room for */
7293 /* mov/push below */
7294 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7295 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7296 /* The technique of hiding data in an */
7297 /* instruction has a problem here: we */
7298 /* need the data aligned to a 16-byte */
7299 /* boundary but the instruction cannot */
7300 /* cross the bundle boundary. so only */
7301 /* odd multiples of 16 can be used */
7302 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7305 while (code < aligned_code) {
7306 *(code++) = 0xf4; /* hlt */
7311 pos = cfg->native_code + patch_info->ip.i;
7312 if (IS_REX (pos [1])) {
7313 patch_pos = pos + 5;
7314 target_pos = code - pos - 9;
7317 patch_pos = pos + 4;
7318 target_pos = code - pos - 8;
7321 if (patch_info->type == MONO_PATCH_INFO_R8) {
7322 #ifdef __native_client_codegen__
7323 /* Hide 64-bit data in a */
7324 /* "mov imm64, r11" instruction. */
7325 /* write it before the start of */
7327 *(code-2) = 0x49; /* prefix */
7328 *(code-1) = 0xbb; /* mov X, %r11 */
7330 *(double*)code = *(double*)patch_info->data.target;
7331 code += sizeof (double);
7333 #ifdef __native_client_codegen__
7334 /* Hide 32-bit data in a */
7335 /* "push imm32" instruction. */
7336 *(code-1) = 0x68; /* push */
7338 *(float*)code = *(float*)patch_info->data.target;
7339 code += sizeof (float);
7342 *(guint32*)(patch_pos) = target_pos;
7347 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7350 if (cfg->compile_aot)
7353 /*loading is faster against aligned addresses.*/
7354 code = (guint8*)ALIGN_TO (code, 8);
7355 memset (orig_code, 0, code - orig_code);
7357 pos = cfg->native_code + patch_info->ip.i;
7359 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7360 if (IS_REX (pos [1]))
7361 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7363 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7365 *(gpointer*)code = (gpointer)patch_info->data.target;
7366 code += sizeof (gpointer);
7376 if (patch_info == cfg->patch_info)
7377 cfg->patch_info = patch_info->next;
7381 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7383 tmp->next = patch_info->next;
7386 g_assert (code < cfg->native_code + cfg->code_size);
7389 cfg->code_len = code - cfg->native_code;
7391 g_assert (cfg->code_len < cfg->code_size);
7395 #endif /* DISABLE_JIT */
7398 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7401 CallInfo *cinfo = NULL;
7402 MonoMethodSignature *sig;
7404 int i, n, stack_area = 0;
7406 /* Keep this in sync with mono_arch_get_argument_info */
7408 if (enable_arguments) {
7409 /* Allocate a new area on the stack and save arguments there */
7410 sig = mono_method_signature (cfg->method);
7412 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7414 n = sig->param_count + sig->hasthis;
7416 stack_area = ALIGN_TO (n * 8, 16);
7418 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7420 for (i = 0; i < n; ++i) {
7421 inst = cfg->args [i];
7423 if (inst->opcode == OP_REGVAR)
7424 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7426 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7427 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7432 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7433 amd64_set_reg_template (code, AMD64_ARG_REG1);
7434 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7435 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7437 if (enable_arguments)
7438 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7452 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7455 int save_mode = SAVE_NONE;
7456 MonoMethod *method = cfg->method;
7457 MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7460 switch (ret_type->type) {
7461 case MONO_TYPE_VOID:
7462 /* special case string .ctor icall */
7463 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7464 save_mode = SAVE_EAX;
7466 save_mode = SAVE_NONE;
7470 save_mode = SAVE_EAX;
7474 save_mode = SAVE_XMM;
7476 case MONO_TYPE_GENERICINST:
7477 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7478 save_mode = SAVE_EAX;
7482 case MONO_TYPE_VALUETYPE:
7483 save_mode = SAVE_STRUCT;
7486 save_mode = SAVE_EAX;
7490 /* Save the result and copy it into the proper argument register */
7491 switch (save_mode) {
7493 amd64_push_reg (code, AMD64_RAX);
7495 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7496 if (enable_arguments)
7497 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7501 if (enable_arguments)
7502 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7505 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7506 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7508 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7510 * The result is already in the proper argument register so no copying
7517 g_assert_not_reached ();
7520 /* Set %al since this is a varargs call */
7521 if (save_mode == SAVE_XMM)
7522 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7524 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7526 if (preserve_argument_registers) {
7527 for (i = 0; i < PARAM_REGS; ++i)
7528 amd64_push_reg (code, param_regs [i]);
7531 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7532 amd64_set_reg_template (code, AMD64_ARG_REG1);
7533 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7535 if (preserve_argument_registers) {
7536 for (i = PARAM_REGS - 1; i >= 0; --i)
7537 amd64_pop_reg (code, param_regs [i]);
7540 /* Restore result */
7541 switch (save_mode) {
7543 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7544 amd64_pop_reg (code, AMD64_RAX);
7550 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7551 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7552 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7557 g_assert_not_reached ();
7564 mono_arch_flush_icache (guint8 *code, gint size)
7570 mono_arch_flush_register_windows (void)
7575 mono_arch_is_inst_imm (gint64 imm)
7577 return amd64_is_imm32 (imm);
7581 * Determine whenever the trap whose info is in SIGINFO is caused by
7585 mono_arch_is_int_overflow (void *sigctx, void *info)
7592 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7594 rip = (guint8*)ctx.rip;
7596 if (IS_REX (rip [0])) {
7597 reg = amd64_rex_b (rip [0]);
7603 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7605 reg += x86_modrm_rm (rip [1]);
7645 g_assert_not_reached ();
7657 mono_arch_get_patch_offset (guint8 *code)
7663 * mono_breakpoint_clean_code:
7665 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7666 * breakpoints in the original code, they are removed in the copy.
7668 * Returns TRUE if no sw breakpoint was present.
7671 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7674 gboolean can_write = TRUE;
7676 * If method_start is non-NULL we need to perform bound checks, since we access memory
7677 * at code - offset we could go before the start of the method and end up in a different
7678 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7681 if (!method_start || code - offset >= method_start) {
7682 memcpy (buf, code - offset, size);
7684 int diff = code - method_start;
7685 memset (buf, 0, size);
7686 memcpy (buf + offset - diff, method_start, diff + size - offset);
7689 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7690 int idx = mono_breakpoint_info_index [i];
7694 ptr = mono_breakpoint_info [idx].address;
7695 if (ptr >= code && ptr < code + size) {
7696 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7698 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7699 buf [ptr - code] = saved_byte;
7705 #if defined(__native_client_codegen__)
7706 /* For membase calls, we want the base register. for Native Client, */
7707 /* all indirect calls have the following sequence with the given sizes: */
7708 /* mov %eXX,%eXX [2-3] */
7709 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7710 /* and $0xffffffffffffffe0,%r11d [4] */
7711 /* add %r15,%r11 [3] */
7712 /* callq *%r11 [3] */
7715 /* Determine if code points to a NaCl call-through-register sequence, */
7716 /* (i.e., the last 3 instructions listed above) */
7718 is_nacl_call_reg_sequence(guint8* code)
7720 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7721 "\x4d\x03\xdf" /* add */
7722 "\x41\xff\xd3"; /* call */
7723 return memcmp(code, sequence, 10) == 0;
7726 /* Determine if code points to the first opcode of the mov membase component */
7727 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7728 /* (there could be a REX prefix before the opcode but it is ignored) */
7730 is_nacl_indirect_call_membase_sequence(guint8* code)
7732 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7733 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7734 /* and that src reg = dest reg */
7735 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7736 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7738 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7739 /* and has dst of r11 and base of r15 */
7740 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7741 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7743 #endif /* __native_client_codegen__ */
7746 mono_arch_get_this_arg_reg (guint8 *code)
7748 return AMD64_ARG_REG1;
7752 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7754 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7757 #define MAX_ARCH_DELEGATE_PARAMS 10
7760 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7762 guint8 *code, *start;
7766 start = code = mono_global_codeman_reserve (64);
7768 /* Replace the this argument with the target */
7769 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7770 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7771 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7773 g_assert ((code - start) < 64);
7775 start = code = mono_global_codeman_reserve (64);
7777 if (param_count == 0) {
7778 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7780 /* We have to shift the arguments left */
7781 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7782 for (i = 0; i < param_count; ++i) {
7785 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7787 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7789 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7793 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7795 g_assert ((code - start) < 64);
7798 nacl_global_codeman_validate(&start, 64, &code);
7800 mono_debug_add_delegate_trampoline (start, code - start);
7803 *code_len = code - start;
7806 if (mono_jit_map_is_enabled ()) {
7809 buff = (char*)"delegate_invoke_has_target";
7811 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7812 mono_emit_jit_tramp (start, code - start, buff);
7821 * mono_arch_get_delegate_invoke_impls:
7823 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7827 mono_arch_get_delegate_invoke_impls (void)
7835 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7836 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7838 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7839 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7840 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7841 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7842 g_free (tramp_name);
7849 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7851 guint8 *code, *start;
7854 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7857 /* FIXME: Support more cases */
7858 if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7862 static guint8* cached = NULL;
7868 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7870 start = get_delegate_invoke_impl (TRUE, 0, NULL);
7872 mono_memory_barrier ();
7876 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7877 for (i = 0; i < sig->param_count; ++i)
7878 if (!mono_is_regsize_var (sig->params [i]))
7880 if (sig->param_count > 4)
7883 code = cache [sig->param_count];
7887 if (mono_aot_only) {
7888 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7889 start = mono_aot_get_trampoline (name);
7892 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7895 mono_memory_barrier ();
7897 cache [sig->param_count] = start;
7904 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7906 guint8 *code, *start;
7909 start = code = mono_global_codeman_reserve (size);
7911 /* Replace the this argument with the target */
7912 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7913 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7916 /* Load the IMT reg */
7917 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7920 /* Load the vtable */
7921 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7922 amd64_jump_membase (code, AMD64_RAX, offset);
7928 mono_arch_finish_init (void)
7930 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7931 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7936 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7940 #if defined(__default_codegen__)
7941 #define CMP_SIZE (6 + 1)
7942 #define CMP_REG_REG_SIZE (4 + 1)
7943 #define BR_SMALL_SIZE 2
7944 #define BR_LARGE_SIZE 6
7945 #define MOV_REG_IMM_SIZE 10
7946 #define MOV_REG_IMM_32BIT_SIZE 6
7947 #define JUMP_REG_SIZE (2 + 1)
7948 #elif defined(__native_client_codegen__)
7949 /* NaCl N-byte instructions can be padded up to N-1 bytes */
7950 #define CMP_SIZE ((6 + 1) * 2 - 1)
7951 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
7952 #define BR_SMALL_SIZE (2 * 2 - 1)
7953 #define BR_LARGE_SIZE (6 * 2 - 1)
7954 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
7955 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
7956 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
7957 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
7958 /* Jump membase's size is large and unpredictable */
7959 /* in native client, just pad it out a whole bundle. */
7960 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
7964 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7966 int i, distance = 0;
7967 for (i = start; i < target; ++i)
7968 distance += imt_entries [i]->chunk_size;
7973 * LOCKING: called with the domain lock held
7976 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7977 gpointer fail_tramp)
7981 guint8 *code, *start;
7982 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7984 for (i = 0; i < count; ++i) {
7985 MonoIMTCheckItem *item = imt_entries [i];
7986 if (item->is_equals) {
7987 if (item->check_target_idx) {
7988 if (!item->compare_done) {
7989 if (amd64_is_imm32 (item->key))
7990 item->chunk_size += CMP_SIZE;
7992 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7994 if (item->has_target_code) {
7995 item->chunk_size += MOV_REG_IMM_SIZE;
7997 if (vtable_is_32bit)
7998 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8000 item->chunk_size += MOV_REG_IMM_SIZE;
8001 #ifdef __native_client_codegen__
8002 item->chunk_size += JUMP_MEMBASE_SIZE;
8005 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8008 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8009 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8011 if (vtable_is_32bit)
8012 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8014 item->chunk_size += MOV_REG_IMM_SIZE;
8015 item->chunk_size += JUMP_REG_SIZE;
8016 /* with assert below:
8017 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8019 #ifdef __native_client_codegen__
8020 item->chunk_size += JUMP_MEMBASE_SIZE;
8025 if (amd64_is_imm32 (item->key))
8026 item->chunk_size += CMP_SIZE;
8028 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8029 item->chunk_size += BR_LARGE_SIZE;
8030 imt_entries [item->check_target_idx]->compare_done = TRUE;
8032 size += item->chunk_size;
8034 #if defined(__native_client__) && defined(__native_client_codegen__)
8035 /* In Native Client, we don't re-use thunks, allocate from the */
8036 /* normal code manager paths. */
8037 code = mono_domain_code_reserve (domain, size);
8040 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8042 code = mono_domain_code_reserve (domain, size);
8045 for (i = 0; i < count; ++i) {
8046 MonoIMTCheckItem *item = imt_entries [i];
8047 item->code_target = code;
8048 if (item->is_equals) {
8049 gboolean fail_case = !item->check_target_idx && fail_tramp;
8051 if (item->check_target_idx || fail_case) {
8052 if (!item->compare_done || fail_case) {
8053 if (amd64_is_imm32 (item->key))
8054 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8056 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8057 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8060 item->jmp_code = code;
8061 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8062 if (item->has_target_code) {
8063 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8064 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8066 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8067 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8071 amd64_patch (item->jmp_code, code);
8072 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8073 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8074 item->jmp_code = NULL;
8077 /* enable the commented code to assert on wrong method */
8079 if (amd64_is_imm32 (item->key))
8080 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8082 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8083 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8085 item->jmp_code = code;
8086 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8087 /* See the comment below about R10 */
8088 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8089 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8090 amd64_patch (item->jmp_code, code);
8091 amd64_breakpoint (code);
8092 item->jmp_code = NULL;
8094 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8095 needs to be preserved. R10 needs
8096 to be preserved for calls which
8097 require a runtime generic context,
8098 but interface calls don't. */
8099 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8100 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8104 if (amd64_is_imm32 (item->key))
8105 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8107 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8108 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8110 item->jmp_code = code;
8111 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8112 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8114 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8116 g_assert (code - item->code_target <= item->chunk_size);
8118 /* patch the branches to get to the target items */
8119 for (i = 0; i < count; ++i) {
8120 MonoIMTCheckItem *item = imt_entries [i];
8121 if (item->jmp_code) {
8122 if (item->check_target_idx) {
8123 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8129 mono_stats.imt_thunks_size += code - start;
8130 g_assert (code - start <= size);
8132 nacl_domain_code_validate(domain, &start, size, &code);
8138 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8140 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8144 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8146 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8150 mono_arch_get_cie_program (void)
8154 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8155 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8161 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8163 MonoInst *ins = NULL;
8166 if (cmethod->klass == mono_defaults.math_class) {
8167 if (strcmp (cmethod->name, "Sin") == 0) {
8169 } else if (strcmp (cmethod->name, "Cos") == 0) {
8171 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8173 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8178 MONO_INST_NEW (cfg, ins, opcode);
8179 ins->type = STACK_R8;
8180 ins->dreg = mono_alloc_freg (cfg);
8181 ins->sreg1 = args [0]->dreg;
8182 MONO_ADD_INS (cfg->cbb, ins);
8186 if (cfg->opt & MONO_OPT_CMOV) {
8187 if (strcmp (cmethod->name, "Min") == 0) {
8188 if (fsig->params [0]->type == MONO_TYPE_I4)
8190 if (fsig->params [0]->type == MONO_TYPE_U4)
8191 opcode = OP_IMIN_UN;
8192 else if (fsig->params [0]->type == MONO_TYPE_I8)
8194 else if (fsig->params [0]->type == MONO_TYPE_U8)
8195 opcode = OP_LMIN_UN;
8196 } else if (strcmp (cmethod->name, "Max") == 0) {
8197 if (fsig->params [0]->type == MONO_TYPE_I4)
8199 if (fsig->params [0]->type == MONO_TYPE_U4)
8200 opcode = OP_IMAX_UN;
8201 else if (fsig->params [0]->type == MONO_TYPE_I8)
8203 else if (fsig->params [0]->type == MONO_TYPE_U8)
8204 opcode = OP_LMAX_UN;
8209 MONO_INST_NEW (cfg, ins, opcode);
8210 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8211 ins->dreg = mono_alloc_ireg (cfg);
8212 ins->sreg1 = args [0]->dreg;
8213 ins->sreg2 = args [1]->dreg;
8214 MONO_ADD_INS (cfg->cbb, ins);
8218 /* OP_FREM is not IEEE compatible */
8219 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8220 MONO_INST_NEW (cfg, ins, OP_FREM);
8221 ins->inst_i0 = args [0];
8222 ins->inst_i1 = args [1];
8228 * Can't implement CompareExchange methods this way since they have
8236 mono_arch_print_tree (MonoInst *tree, int arity)
8241 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8244 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8247 case AMD64_RCX: return ctx->rcx;
8248 case AMD64_RDX: return ctx->rdx;
8249 case AMD64_RBX: return ctx->rbx;
8250 case AMD64_RBP: return ctx->rbp;
8251 case AMD64_RSP: return ctx->rsp;
8253 return _CTX_REG (ctx, rax, reg);
8258 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8277 _CTX_REG (ctx, rax, reg) = val;
8281 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8283 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8286 gpointer *sp, old_value;
8288 const unsigned char *handler;
8290 /*Decode the first instruction to figure out where did we store the spvar*/
8291 /*Our jit MUST generate the following:
8294 Which is encoded as: REX.W 0x89 mod_rm
8295 mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8296 mod (reg + imm8): 01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8297 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8299 FIXME can we generate frameless methods on this case?
8302 handler = clause->handler_start;
8305 if (*handler != 0x48)
8310 if (*handler != 0x89)
8314 if (*handler == 0x65)
8315 offset = *(signed char*)(handler + 1);
8316 else if (*handler == 0xA5)
8317 offset = *(int*)(handler + 1);
8322 bp = MONO_CONTEXT_GET_BP (ctx);
8323 sp = *(gpointer*)(bp + offset);
8326 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8335 * mono_arch_emit_load_aotconst:
8337 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8338 * TARGET from the mscorlib GOT in full-aot code.
8339 * On AMD64, the result is placed into R11.
8342 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8344 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8345 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8351 * mono_arch_get_trampolines:
8353 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8357 mono_arch_get_trampolines (gboolean aot)
8359 return mono_amd64_get_exception_trampolines (aot);
8362 /* Soft Debug support */
8363 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8366 * mono_arch_set_breakpoint:
8368 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8369 * The location should contain code emitted by OP_SEQ_POINT.
8372 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8375 guint8 *orig_code = code;
8378 guint32 native_offset = ip - (guint8*)ji->code_start;
8379 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8381 g_assert (info->bp_addrs [native_offset] == 0);
8382 info->bp_addrs [native_offset] = bp_trigger_page;
8385 * In production, we will use int3 (has to fix the size in the md
8386 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8389 g_assert (code [0] == 0x90);
8390 if (breakpoint_size == 8) {
8391 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8393 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8394 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8397 g_assert (code - orig_code == breakpoint_size);
8402 * mono_arch_clear_breakpoint:
8404 * Clear the breakpoint at IP.
8407 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8413 guint32 native_offset = ip - (guint8*)ji->code_start;
8414 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8416 g_assert (info->bp_addrs [native_offset] == 0);
8417 info->bp_addrs [native_offset] = info;
8419 for (i = 0; i < breakpoint_size; ++i)
8425 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8428 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8429 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && einfo->ExceptionInformation [1] == bp_trigger_page)
8434 siginfo_t* sinfo = (siginfo_t*) info;
8435 /* Sometimes the address is off by 4 */
8436 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8444 * mono_arch_skip_breakpoint:
8446 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8447 * we resume, the instruction is not executed again.
8450 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8453 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8454 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8456 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8461 * mono_arch_start_single_stepping:
8463 * Start single stepping.
8466 mono_arch_start_single_stepping (void)
8468 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8472 * mono_arch_stop_single_stepping:
8474 * Stop single stepping.
8477 mono_arch_stop_single_stepping (void)
8479 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8483 * mono_arch_is_single_step_event:
8485 * Return whenever the machine state in SIGCTX corresponds to a single
8489 mono_arch_is_single_step_event (void *info, void *sigctx)
8492 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8493 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && einfo->ExceptionInformation [1] == ss_trigger_page)
8498 siginfo_t* sinfo = (siginfo_t*) info;
8499 /* Sometimes the address is off by 4 */
8500 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8508 * mono_arch_skip_single_step:
8510 * Modify CTX so the ip is placed after the single step trigger instruction,
8511 * we resume, the instruction is not executed again.
8514 mono_arch_skip_single_step (MonoContext *ctx)
8516 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8520 * mono_arch_create_seq_point_info:
8522 * Return a pointer to a data structure which is used by the sequence
8523 * point implementation in AOTed code.
8526 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8532 // FIXME: Add a free function
8534 mono_domain_lock (domain);
8535 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8537 mono_domain_unlock (domain);
8540 ji = mono_jit_info_table_find (domain, (char*)code);
8543 // FIXME: Optimize the size
8544 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8546 info->ss_trigger_page = ss_trigger_page;
8547 info->bp_trigger_page = bp_trigger_page;
8548 /* Initialize to a valid address */
8549 for (i = 0; i < ji->code_size; ++i)
8550 info->bp_addrs [i] = info;
8552 mono_domain_lock (domain);
8553 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8555 mono_domain_unlock (domain);
8562 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8564 ext->lmf.previous_lmf = prev_lmf;
8565 /* Mark that this is a MonoLMFExt */
8566 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8567 ext->lmf.rsp = (gssize)ext;
8573 mono_arch_opcode_supported (int opcode)
8576 case OP_ATOMIC_ADD_I4:
8577 case OP_ATOMIC_ADD_I8:
8578 case OP_ATOMIC_EXCHANGE_I4:
8579 case OP_ATOMIC_EXCHANGE_I8:
8580 case OP_ATOMIC_CAS_I4:
8581 case OP_ATOMIC_CAS_I8: