3 * AMD64 backend for the Mono code generator
8 * Paolo Molaro (lupus@ximian.com)
9 * Dietmar Maurer (dietmar@ximian.com)
11 * Zoltan Varga (vargaz@gmail.com)
12 * Johan Lorensson (lateralusx.github@gmail.com)
14 * (C) 2003 Ximian, Inc.
15 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
16 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
17 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
27 #include <mono/metadata/abi-details.h>
28 #include <mono/metadata/appdomain.h>
29 #include <mono/metadata/debug-helpers.h>
30 #include <mono/metadata/threads.h>
31 #include <mono/metadata/profiler-private.h>
32 #include <mono/metadata/mono-debug.h>
33 #include <mono/metadata/gc-internals.h>
34 #include <mono/utils/mono-math.h>
35 #include <mono/utils/mono-mmap.h>
36 #include <mono/utils/mono-memory-model.h>
37 #include <mono/utils/mono-tls.h>
38 #include <mono/utils/mono-hwcap.h>
39 #include <mono/utils/mono-threads.h>
43 #include "mini-amd64.h"
44 #include "cpu-amd64.h"
45 #include "debugger-agent.h"
49 static gboolean optimize_for_xen = TRUE;
51 #define optimize_for_xen 0
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
56 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
58 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
61 /* Under windows, the calling convention is never stdcall */
62 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
64 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
67 /* This mutex protects architecture specific caches */
68 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
69 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
70 static mono_mutex_t mini_arch_mutex;
72 /* The single step trampoline */
73 static gpointer ss_trampoline;
75 /* The breakpoint trampoline */
76 static gpointer bp_trampoline;
78 /* Offset between fp and the first argument in the callee */
79 #define ARGS_OFFSET 16
80 #define GP_SCRATCH_REG AMD64_R11
83 * AMD64 register usage:
84 * - callee saved registers are used for global register allocation
85 * - %r11 is used for materializing 64 bit constants in opcodes
86 * - the rest is used for local allocation
90 * Floating point comparison results:
100 mono_arch_regname (int reg)
103 case AMD64_RAX: return "%rax";
104 case AMD64_RBX: return "%rbx";
105 case AMD64_RCX: return "%rcx";
106 case AMD64_RDX: return "%rdx";
107 case AMD64_RSP: return "%rsp";
108 case AMD64_RBP: return "%rbp";
109 case AMD64_RDI: return "%rdi";
110 case AMD64_RSI: return "%rsi";
111 case AMD64_R8: return "%r8";
112 case AMD64_R9: return "%r9";
113 case AMD64_R10: return "%r10";
114 case AMD64_R11: return "%r11";
115 case AMD64_R12: return "%r12";
116 case AMD64_R13: return "%r13";
117 case AMD64_R14: return "%r14";
118 case AMD64_R15: return "%r15";
123 static const char * packed_xmmregs [] = {
124 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
125 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
128 static const char * single_xmmregs [] = {
129 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
130 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
134 mono_arch_fregname (int reg)
136 if (reg < AMD64_XMM_NREG)
137 return single_xmmregs [reg];
143 mono_arch_xregname (int reg)
145 if (reg < AMD64_XMM_NREG)
146 return packed_xmmregs [reg];
155 return mono_debug_count ();
161 static inline gboolean
162 amd64_is_near_call (guint8 *code)
165 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
168 return code [0] == 0xe8;
171 static inline gboolean
172 amd64_use_imm32 (gint64 val)
174 if (mini_get_debug_options()->single_imm_size)
177 return amd64_is_imm32 (val);
181 amd64_patch (unsigned char* code, gpointer target)
186 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
191 if ((code [0] & 0xf8) == 0xb8) {
192 /* amd64_set_reg_template */
193 *(guint64*)(code + 1) = (guint64)target;
195 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
196 /* mov 0(%rip), %dreg */
197 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
199 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
200 /* call *<OFFSET>(%rip) */
201 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
203 else if (code [0] == 0xe8) {
205 gint64 disp = (guint8*)target - (guint8*)code;
206 g_assert (amd64_is_imm32 (disp));
207 x86_patch (code, (unsigned char*)target);
210 x86_patch (code, (unsigned char*)target);
214 mono_amd64_patch (unsigned char* code, gpointer target)
216 amd64_patch (code, target);
219 #define DEBUG(a) if (cfg->verbose_level > 1) a
222 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
224 ainfo->offset = *stack_size;
226 if (*gr >= PARAM_REGS) {
227 ainfo->storage = ArgOnStack;
228 ainfo->arg_size = sizeof (mgreg_t);
229 /* Since the same stack slot size is used for all arg */
230 /* types, it needs to be big enough to hold them all */
231 (*stack_size) += sizeof(mgreg_t);
234 ainfo->storage = ArgInIReg;
235 ainfo->reg = param_regs [*gr];
241 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
243 ainfo->offset = *stack_size;
245 if (*gr >= FLOAT_PARAM_REGS) {
246 ainfo->storage = ArgOnStack;
247 ainfo->arg_size = sizeof (mgreg_t);
248 /* Since the same stack slot size is used for both float */
249 /* types, it needs to be big enough to hold them both */
250 (*stack_size) += sizeof(mgreg_t);
253 /* A double register */
255 ainfo->storage = ArgInDoubleSSEReg;
257 ainfo->storage = ArgInFloatSSEReg;
263 typedef enum ArgumentClass {
271 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
273 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
276 ptype = mini_get_underlying_type (type);
277 switch (ptype->type) {
286 case MONO_TYPE_OBJECT:
288 case MONO_TYPE_FNPTR:
291 class2 = ARG_CLASS_INTEGER;
296 class2 = ARG_CLASS_INTEGER;
298 class2 = ARG_CLASS_SSE;
302 case MONO_TYPE_TYPEDBYREF:
303 g_assert_not_reached ();
305 case MONO_TYPE_GENERICINST:
306 if (!mono_type_generic_inst_is_valuetype (ptype)) {
307 class2 = ARG_CLASS_INTEGER;
311 case MONO_TYPE_VALUETYPE: {
312 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
315 for (i = 0; i < info->num_fields; ++i) {
317 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
322 g_assert_not_reached ();
326 if (class1 == class2)
328 else if (class1 == ARG_CLASS_NO_CLASS)
330 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
331 class1 = ARG_CLASS_MEMORY;
332 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
333 class1 = ARG_CLASS_INTEGER;
335 class1 = ARG_CLASS_SSE;
346 * collect_field_info_nested:
348 * Collect field info from KLASS recursively into FIELDS.
351 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
353 MonoMarshalType *info;
357 info = mono_marshal_load_type_info (klass);
359 for (i = 0; i < info->num_fields; ++i) {
360 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
361 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
366 f.type = info->fields [i].field->type;
367 f.size = mono_marshal_type_size (info->fields [i].field->type,
368 info->fields [i].mspec,
369 &align, TRUE, unicode);
370 f.offset = offset + info->fields [i].offset;
371 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
372 /* This can happen with .pack directives eg. 'fixed' arrays */
373 if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
374 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
375 g_array_append_val (fields_array, f);
376 while (f.size + f.offset < info->native_size) {
378 g_array_append_val (fields_array, f);
381 f.size = info->native_size - f.offset;
382 g_array_append_val (fields_array, f);
385 g_array_append_val (fields_array, f);
391 MonoClassField *field;
394 while ((field = mono_class_get_fields (klass, &iter))) {
395 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
397 if (MONO_TYPE_ISSTRUCT (field->type)) {
398 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
403 f.type = field->type;
404 f.size = mono_type_size (field->type, &align);
405 f.offset = field->offset - sizeof (MonoObject) + offset;
407 g_array_append_val (fields_array, f);
415 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
416 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
419 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
421 gboolean result = FALSE;
423 assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
424 assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
426 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
427 arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
428 arg_info->pair_size [0] = 0;
429 arg_info->pair_size [1] = 0;
432 if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
433 /* Pass parameter in integer register. */
434 arg_info->pair_storage [0] = ArgInIReg;
435 arg_info->pair_regs [0] = int_regs [*current_int_reg];
436 (*current_int_reg) ++;
438 } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
439 /* Pass parameter in float register. */
440 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
441 arg_info->pair_regs [0] = float_regs [*current_float_reg];
442 (*current_float_reg) ++;
446 if (result == TRUE) {
447 arg_info->pair_size [0] = arg_size;
454 static inline gboolean
455 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
457 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
460 static inline gboolean
461 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
463 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
467 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
468 guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
470 /* Windows x64 value type ABI.
472 * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
474 * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
475 * Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
476 * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
477 * Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
479 * Return values: https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
481 * Integers/Float types smaller than or equal to 8 bytes
482 * Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
483 * Properly sized struct/unions (1,2,4,8)
484 * Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
485 * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
486 * Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
489 assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
493 /* Parameter cases. */
494 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
495 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
497 /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
498 arg_info->storage = ArgValuetypeInReg;
499 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
500 /* No more registers, fallback passing parameter on stack as value. */
501 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
503 /* Passing value directly on stack, so use size of value. */
504 arg_info->storage = ArgOnStack;
505 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
506 arg_info->offset = *stack_size;
507 arg_info->arg_size = arg_size;
508 *stack_size += arg_size;
511 /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
512 arg_info->storage = ArgValuetypeAddrInIReg;
513 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
514 /* No more registers, fallback passing address to parameter on stack. */
515 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
517 /* Passing an address to value on stack, so use size of register as argument size. */
518 arg_info->storage = ArgValuetypeAddrOnStack;
519 arg_size = sizeof (mgreg_t);
520 arg_info->offset = *stack_size;
521 arg_info->arg_size = arg_size;
522 *stack_size += arg_size;
526 /* Return value cases. */
527 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
528 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
530 /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
531 arg_info->storage = ArgValuetypeInReg;
532 allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
534 /* Only RAX/XMM0 should be used to return valuetype. */
535 assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
537 /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
538 arg_info->storage = ArgValuetypeAddrInIReg;
539 allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
541 /* Only RAX should be used to return valuetype address. */
542 assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
544 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
545 arg_info->offset = *stack_size;
546 *stack_size += arg_size;
552 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
555 *arg_class = ARG_CLASS_NO_CLASS;
557 assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
560 /* Calculate argument class type and size of marshalled type. */
561 MonoMarshalType *info = mono_marshal_load_type_info (klass);
562 *arg_size = info->native_size;
564 /* Calculate argument class type and size of managed type. */
565 *arg_size = mono_class_value_size (klass, NULL);
568 /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
569 *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
571 if (*arg_class == ARG_CLASS_MEMORY) {
572 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
573 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
577 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
578 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
579 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
580 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
581 * it must be represented in call and cannot be dropped.
583 if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
584 arg_info->pass_empty_struct = TRUE;
585 *arg_size = SIZEOF_REGISTER;
586 *arg_class = ARG_CLASS_INTEGER;
589 assert (*arg_class != ARG_CLASS_NO_CLASS);
593 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
594 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
596 guint32 arg_size = SIZEOF_REGISTER;
597 MonoClass *klass = NULL;
598 ArgumentClass arg_class;
600 assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
602 klass = mono_class_from_mono_type (type);
603 get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
605 /* Only drop value type if its not an empty struct as input that must be represented in call */
606 if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
607 arg_info->storage = ArgValuetypeInReg;
608 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
610 /* Alocate storage for value type. */
611 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
615 #endif /* TARGET_WIN32 */
618 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
620 guint32 *gr, guint32 *fr, guint32 *stack_size)
623 add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
625 guint32 size, quad, nquads, i, nfields;
626 /* Keep track of the size used in each quad so we can */
627 /* use the right size when copying args/return vars. */
628 guint32 quadsize [2] = {8, 8};
629 ArgumentClass args [2];
630 StructFieldInfo *fields = NULL;
631 GArray *fields_array;
633 gboolean pass_on_stack = FALSE;
636 klass = mono_class_from_mono_type (type);
637 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
639 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
640 /* We pass and return vtypes of size 8 in a register */
641 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
642 pass_on_stack = TRUE;
645 /* If this struct can't be split up naturally into 8-byte */
646 /* chunks (registers), pass it on the stack. */
648 MonoMarshalType *info = mono_marshal_load_type_info (klass);
650 struct_size = info->native_size;
652 struct_size = mono_class_value_size (klass, NULL);
655 * Collect field information recursively to be able to
656 * handle nested structures.
658 fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
659 collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
660 fields = (StructFieldInfo*)fields_array->data;
661 nfields = fields_array->len;
663 for (i = 0; i < nfields; ++i) {
664 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
665 pass_on_stack = TRUE;
671 ainfo->storage = ArgValuetypeInReg;
672 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
677 /* Allways pass in memory */
678 ainfo->offset = *stack_size;
679 *stack_size += ALIGN_TO (size, 8);
680 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
682 ainfo->arg_size = ALIGN_TO (size, 8);
684 g_array_free (fields_array, TRUE);
694 int n = mono_class_value_size (klass, NULL);
696 quadsize [0] = n >= 8 ? 8 : n;
697 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
699 /* Always pass in 1 or 2 integer registers */
700 args [0] = ARG_CLASS_INTEGER;
701 args [1] = ARG_CLASS_INTEGER;
702 /* Only the simplest cases are supported */
703 if (is_return && nquads != 1) {
704 args [0] = ARG_CLASS_MEMORY;
705 args [1] = ARG_CLASS_MEMORY;
709 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
710 * The X87 and SSEUP stuff is left out since there are no such types in
714 ainfo->storage = ArgValuetypeInReg;
715 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
719 if (struct_size > 16) {
720 ainfo->offset = *stack_size;
721 *stack_size += ALIGN_TO (struct_size, 8);
722 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
724 ainfo->arg_size = ALIGN_TO (struct_size, 8);
726 g_array_free (fields_array, TRUE);
730 args [0] = ARG_CLASS_NO_CLASS;
731 args [1] = ARG_CLASS_NO_CLASS;
732 for (quad = 0; quad < nquads; ++quad) {
733 ArgumentClass class1;
736 class1 = ARG_CLASS_MEMORY;
738 class1 = ARG_CLASS_NO_CLASS;
739 for (i = 0; i < nfields; ++i) {
740 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
741 /* Unaligned field */
745 /* Skip fields in other quad */
746 if ((quad == 0) && (fields [i].offset >= 8))
748 if ((quad == 1) && (fields [i].offset < 8))
751 /* How far into this quad this data extends.*/
752 /* (8 is size of quad) */
753 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
755 class1 = merge_argument_class_from_type (fields [i].type, class1);
757 /* Empty structs have a nonzero size, causing this assert to be hit */
759 g_assert (class1 != ARG_CLASS_NO_CLASS);
760 args [quad] = class1;
764 g_array_free (fields_array, TRUE);
766 /* Post merger cleanup */
767 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
768 args [0] = args [1] = ARG_CLASS_MEMORY;
770 /* Allocate registers */
775 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
777 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
780 ainfo->storage = ArgValuetypeInReg;
781 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
782 g_assert (quadsize [0] <= 8);
783 g_assert (quadsize [1] <= 8);
784 ainfo->pair_size [0] = quadsize [0];
785 ainfo->pair_size [1] = quadsize [1];
786 ainfo->nregs = nquads;
787 for (quad = 0; quad < nquads; ++quad) {
788 switch (args [quad]) {
789 case ARG_CLASS_INTEGER:
790 if (*gr >= PARAM_REGS)
791 args [quad] = ARG_CLASS_MEMORY;
793 ainfo->pair_storage [quad] = ArgInIReg;
795 ainfo->pair_regs [quad] = return_regs [*gr];
797 ainfo->pair_regs [quad] = param_regs [*gr];
802 if (*fr >= FLOAT_PARAM_REGS)
803 args [quad] = ARG_CLASS_MEMORY;
805 if (quadsize[quad] <= 4)
806 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
807 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
808 ainfo->pair_regs [quad] = *fr;
812 case ARG_CLASS_MEMORY:
814 case ARG_CLASS_NO_CLASS:
817 g_assert_not_reached ();
821 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
823 /* Revert possible register assignments */
827 ainfo->offset = *stack_size;
829 arg_size = ALIGN_TO (struct_size, 8);
831 arg_size = nquads * sizeof(mgreg_t);
832 *stack_size += arg_size;
833 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
835 ainfo->arg_size = arg_size;
838 #endif /* !TARGET_WIN32 */
844 * Obtain information about a call according to the calling convention.
845 * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
846 * Draft Version 0.23" document for more information.
847 * For AMD64 Windows, see "Overview of x64 Calling Conventions",
848 * https://msdn.microsoft.com/en-us/library/ms235286.aspx
851 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
853 guint32 i, gr, fr, pstart;
855 int n = sig->hasthis + sig->param_count;
856 guint32 stack_size = 0;
858 gboolean is_pinvoke = sig->pinvoke;
861 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
863 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
866 cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
872 /* Reserve space where the callee can save the argument registers */
873 stack_size = 4 * sizeof (mgreg_t);
877 ret_type = mini_get_underlying_type (sig->ret);
878 switch (ret_type->type) {
888 case MONO_TYPE_FNPTR:
889 case MONO_TYPE_OBJECT:
890 cinfo->ret.storage = ArgInIReg;
891 cinfo->ret.reg = AMD64_RAX;
895 cinfo->ret.storage = ArgInIReg;
896 cinfo->ret.reg = AMD64_RAX;
899 cinfo->ret.storage = ArgInFloatSSEReg;
900 cinfo->ret.reg = AMD64_XMM0;
903 cinfo->ret.storage = ArgInDoubleSSEReg;
904 cinfo->ret.reg = AMD64_XMM0;
906 case MONO_TYPE_GENERICINST:
907 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
908 cinfo->ret.storage = ArgInIReg;
909 cinfo->ret.reg = AMD64_RAX;
912 if (mini_is_gsharedvt_type (ret_type)) {
913 cinfo->ret.storage = ArgGsharedvtVariableInReg;
917 case MONO_TYPE_VALUETYPE:
918 case MONO_TYPE_TYPEDBYREF: {
919 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
921 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
922 g_assert (cinfo->ret.storage != ArgInIReg);
927 g_assert (mini_is_gsharedvt_type (ret_type));
928 cinfo->ret.storage = ArgGsharedvtVariableInReg;
933 g_error ("Can't handle as return value 0x%x", ret_type->type);
938 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
939 * the first argument, allowing 'this' to be always passed in the first arg reg.
940 * Also do this if the first argument is a reference type, since virtual calls
941 * are sometimes made using calli without sig->hasthis set, like in the delegate
944 ArgStorage ret_storage = cinfo->ret.storage;
945 if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
947 add_general (&gr, &stack_size, cinfo->args + 0);
949 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
952 add_general (&gr, &stack_size, &cinfo->ret);
953 cinfo->ret.storage = ret_storage;
954 cinfo->vret_arg_index = 1;
958 add_general (&gr, &stack_size, cinfo->args + 0);
960 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
961 add_general (&gr, &stack_size, &cinfo->ret);
962 cinfo->ret.storage = ret_storage;
966 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
968 fr = FLOAT_PARAM_REGS;
970 /* Emit the signature cookie just before the implicit arguments */
971 add_general (&gr, &stack_size, &cinfo->sig_cookie);
974 for (i = pstart; i < sig->param_count; ++i) {
975 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
979 /* The float param registers and other param registers must be the same index on Windows x64.*/
986 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
987 /* We allways pass the sig cookie on the stack for simplicity */
989 * Prevent implicit arguments + the sig cookie from being passed
993 fr = FLOAT_PARAM_REGS;
995 /* Emit the signature cookie just before the implicit arguments */
996 add_general (&gr, &stack_size, &cinfo->sig_cookie);
999 ptype = mini_get_underlying_type (sig->params [i]);
1000 switch (ptype->type) {
1003 add_general (&gr, &stack_size, ainfo);
1007 add_general (&gr, &stack_size, ainfo);
1011 add_general (&gr, &stack_size, ainfo);
1016 case MONO_TYPE_FNPTR:
1017 case MONO_TYPE_OBJECT:
1018 add_general (&gr, &stack_size, ainfo);
1020 case MONO_TYPE_GENERICINST:
1021 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1022 add_general (&gr, &stack_size, ainfo);
1025 if (mini_is_gsharedvt_variable_type (ptype)) {
1026 /* gsharedvt arguments are passed by ref */
1027 add_general (&gr, &stack_size, ainfo);
1028 if (ainfo->storage == ArgInIReg)
1029 ainfo->storage = ArgGSharedVtInReg;
1031 ainfo->storage = ArgGSharedVtOnStack;
1035 case MONO_TYPE_VALUETYPE:
1036 case MONO_TYPE_TYPEDBYREF:
1037 add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1042 add_general (&gr, &stack_size, ainfo);
1045 add_float (&fr, &stack_size, ainfo, FALSE);
1048 add_float (&fr, &stack_size, ainfo, TRUE);
1051 case MONO_TYPE_MVAR:
1052 /* gsharedvt arguments are passed by ref */
1053 g_assert (mini_is_gsharedvt_type (ptype));
1054 add_general (&gr, &stack_size, ainfo);
1055 if (ainfo->storage == ArgInIReg)
1056 ainfo->storage = ArgGSharedVtInReg;
1058 ainfo->storage = ArgGSharedVtOnStack;
1061 g_assert_not_reached ();
1065 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1067 fr = FLOAT_PARAM_REGS;
1069 /* Emit the signature cookie just before the implicit arguments */
1070 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1073 cinfo->stack_usage = stack_size;
1074 cinfo->reg_usage = gr;
1075 cinfo->freg_usage = fr;
1080 * mono_arch_get_argument_info:
1081 * @csig: a method signature
1082 * @param_count: the number of parameters to consider
1083 * @arg_info: an array to store the result infos
1085 * Gathers information on parameters such as size, alignment and
1086 * padding. arg_info should be large enought to hold param_count + 1 entries.
1088 * Returns the size of the argument area on the stack.
1091 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1094 CallInfo *cinfo = get_call_info (NULL, csig);
1095 guint32 args_size = cinfo->stack_usage;
1097 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1098 if (csig->hasthis) {
1099 arg_info [0].offset = 0;
1102 for (k = 0; k < param_count; k++) {
1103 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1105 arg_info [k + 1].size = 0;
1114 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1118 MonoType *callee_ret;
1120 c1 = get_call_info (NULL, caller_sig);
1121 c2 = get_call_info (NULL, callee_sig);
1122 res = c1->stack_usage >= c2->stack_usage;
1123 callee_ret = mini_get_underlying_type (callee_sig->ret);
1124 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1125 /* An address on the callee's stack is passed as the first argument */
1135 * Initialize the cpu to execute managed code.
1138 mono_arch_cpu_init (void)
1143 /* spec compliance requires running with double precision */
1144 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1145 fpcw &= ~X86_FPCW_PRECC_MASK;
1146 fpcw |= X86_FPCW_PREC_DOUBLE;
1147 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1148 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1150 /* TODO: This is crashing on Win64 right now.
1151 * _control87 (_PC_53, MCW_PC);
1157 * Initialize architecture specific code.
1160 mono_arch_init (void)
1162 mono_os_mutex_init_recursive (&mini_arch_mutex);
1164 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1165 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1166 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1167 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1168 mono_aot_register_jit_icall ("mono_amd64_handler_block_trampoline_helper", mono_amd64_handler_block_trampoline_helper);
1170 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1171 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1175 bp_trampoline = mini_get_breakpoint_trampoline ();
1179 * Cleanup architecture specific code.
1182 mono_arch_cleanup (void)
1184 mono_os_mutex_destroy (&mini_arch_mutex);
1188 * This function returns the optimizations supported on this cpu.
1191 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1197 if (mono_hwcap_x86_has_cmov) {
1198 opts |= MONO_OPT_CMOV;
1200 if (mono_hwcap_x86_has_fcmov)
1201 opts |= MONO_OPT_FCMOV;
1203 *exclude_mask |= MONO_OPT_FCMOV;
1205 *exclude_mask |= MONO_OPT_CMOV;
1209 /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1210 /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1211 /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1212 /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1213 /* will now have a reference to an argument that won't be fully decomposed. */
1214 *exclude_mask |= MONO_OPT_SIMD;
1221 * This function test for all SSE functions supported.
1223 * Returns a bitmask corresponding to all supported versions.
1227 mono_arch_cpu_enumerate_simd_versions (void)
1229 guint32 sse_opts = 0;
1231 if (mono_hwcap_x86_has_sse1)
1232 sse_opts |= SIMD_VERSION_SSE1;
1234 if (mono_hwcap_x86_has_sse2)
1235 sse_opts |= SIMD_VERSION_SSE2;
1237 if (mono_hwcap_x86_has_sse3)
1238 sse_opts |= SIMD_VERSION_SSE3;
1240 if (mono_hwcap_x86_has_ssse3)
1241 sse_opts |= SIMD_VERSION_SSSE3;
1243 if (mono_hwcap_x86_has_sse41)
1244 sse_opts |= SIMD_VERSION_SSE41;
1246 if (mono_hwcap_x86_has_sse42)
1247 sse_opts |= SIMD_VERSION_SSE42;
1249 if (mono_hwcap_x86_has_sse4a)
1250 sse_opts |= SIMD_VERSION_SSE4a;
1258 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1263 for (i = 0; i < cfg->num_varinfo; i++) {
1264 MonoInst *ins = cfg->varinfo [i];
1265 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1268 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1271 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1272 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1275 if (mono_is_regsize_var (ins->inst_vtype)) {
1276 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1277 g_assert (i == vmv->idx);
1278 vars = g_list_prepend (vars, vmv);
1282 vars = mono_varlist_sort (cfg, vars, 0);
1288 * mono_arch_compute_omit_fp:
1289 * Determine whether the frame pointer can be eliminated.
1292 mono_arch_compute_omit_fp (MonoCompile *cfg)
1294 MonoMethodSignature *sig;
1295 MonoMethodHeader *header;
1299 if (cfg->arch.omit_fp_computed)
1302 header = cfg->header;
1304 sig = mono_method_signature (cfg->method);
1306 if (!cfg->arch.cinfo)
1307 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1308 cinfo = (CallInfo *)cfg->arch.cinfo;
1311 * FIXME: Remove some of the restrictions.
1313 cfg->arch.omit_fp = TRUE;
1314 cfg->arch.omit_fp_computed = TRUE;
1316 if (cfg->disable_omit_fp)
1317 cfg->arch.omit_fp = FALSE;
1319 if (!debug_omit_fp ())
1320 cfg->arch.omit_fp = FALSE;
1322 if (cfg->method->save_lmf)
1323 cfg->arch.omit_fp = FALSE;
1325 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1326 cfg->arch.omit_fp = FALSE;
1327 if (header->num_clauses)
1328 cfg->arch.omit_fp = FALSE;
1329 if (cfg->param_area)
1330 cfg->arch.omit_fp = FALSE;
1331 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1332 cfg->arch.omit_fp = FALSE;
1333 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1334 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1335 cfg->arch.omit_fp = FALSE;
1336 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1337 ArgInfo *ainfo = &cinfo->args [i];
1339 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1341 * The stack offset can only be determined when the frame
1344 cfg->arch.omit_fp = FALSE;
1349 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1350 MonoInst *ins = cfg->varinfo [i];
1353 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1358 mono_arch_get_global_int_regs (MonoCompile *cfg)
1362 mono_arch_compute_omit_fp (cfg);
1364 if (cfg->arch.omit_fp)
1365 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1367 /* We use the callee saved registers for global allocation */
1368 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1369 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1370 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1371 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1372 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1374 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1375 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1382 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1387 /* All XMM registers */
1388 for (i = 0; i < 16; ++i)
1389 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1395 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1397 static GList *r = NULL;
1402 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1403 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1404 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1405 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1406 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1407 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1409 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1410 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1411 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1412 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1413 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1414 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1415 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1416 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1418 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1425 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1428 static GList *r = NULL;
1433 for (i = 0; i < AMD64_XMM_NREG; ++i)
1434 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1436 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1443 * mono_arch_regalloc_cost:
1445 * Return the cost, in number of memory references, of the action of
1446 * allocating the variable VMV into a register during global register
1450 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1452 MonoInst *ins = cfg->varinfo [vmv->idx];
1454 if (cfg->method->save_lmf)
1455 /* The register is already saved */
1456 /* substract 1 for the invisible store in the prolog */
1457 return (ins->opcode == OP_ARG) ? 0 : 1;
1460 return (ins->opcode == OP_ARG) ? 1 : 2;
1464 * mono_arch_fill_argument_info:
1466 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1470 mono_arch_fill_argument_info (MonoCompile *cfg)
1473 MonoMethodSignature *sig;
1478 sig = mono_method_signature (cfg->method);
1480 cinfo = (CallInfo *)cfg->arch.cinfo;
1481 sig_ret = mini_get_underlying_type (sig->ret);
1484 * Contrary to mono_arch_allocate_vars (), the information should describe
1485 * where the arguments are at the beginning of the method, not where they can be
1486 * accessed during the execution of the method. The later makes no sense for the
1487 * global register allocator, since a variable can be in more than one location.
1489 switch (cinfo->ret.storage) {
1491 case ArgInFloatSSEReg:
1492 case ArgInDoubleSSEReg:
1493 cfg->ret->opcode = OP_REGVAR;
1494 cfg->ret->inst_c0 = cinfo->ret.reg;
1496 case ArgValuetypeInReg:
1497 cfg->ret->opcode = OP_REGOFFSET;
1498 cfg->ret->inst_basereg = -1;
1499 cfg->ret->inst_offset = -1;
1504 g_assert_not_reached ();
1507 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1508 ArgInfo *ainfo = &cinfo->args [i];
1510 ins = cfg->args [i];
1512 switch (ainfo->storage) {
1514 case ArgInFloatSSEReg:
1515 case ArgInDoubleSSEReg:
1516 ins->opcode = OP_REGVAR;
1517 ins->inst_c0 = ainfo->reg;
1520 ins->opcode = OP_REGOFFSET;
1521 ins->inst_basereg = -1;
1522 ins->inst_offset = -1;
1524 case ArgValuetypeInReg:
1526 ins->opcode = OP_NOP;
1529 g_assert_not_reached ();
1535 mono_arch_allocate_vars (MonoCompile *cfg)
1538 MonoMethodSignature *sig;
1541 guint32 locals_stack_size, locals_stack_align;
1545 sig = mono_method_signature (cfg->method);
1547 cinfo = (CallInfo *)cfg->arch.cinfo;
1548 sig_ret = mini_get_underlying_type (sig->ret);
1550 mono_arch_compute_omit_fp (cfg);
1553 * We use the ABI calling conventions for managed code as well.
1554 * Exception: valuetypes are only sometimes passed or returned in registers.
1558 * The stack looks like this:
1559 * <incoming arguments passed on the stack>
1561 * <lmf/caller saved registers>
1564 * <localloc area> -> grows dynamically
1568 if (cfg->arch.omit_fp) {
1569 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1570 cfg->frame_reg = AMD64_RSP;
1573 /* Locals are allocated backwards from %fp */
1574 cfg->frame_reg = AMD64_RBP;
1578 cfg->arch.saved_iregs = cfg->used_int_regs;
1579 if (cfg->method->save_lmf) {
1580 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1581 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1582 cfg->arch.saved_iregs |= iregs_to_save;
1585 if (cfg->arch.omit_fp)
1586 cfg->arch.reg_save_area_offset = offset;
1587 /* Reserve space for callee saved registers */
1588 for (i = 0; i < AMD64_NREG; ++i)
1589 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1590 offset += sizeof(mgreg_t);
1592 if (!cfg->arch.omit_fp)
1593 cfg->arch.reg_save_area_offset = -offset;
1595 if (sig_ret->type != MONO_TYPE_VOID) {
1596 switch (cinfo->ret.storage) {
1598 case ArgInFloatSSEReg:
1599 case ArgInDoubleSSEReg:
1600 cfg->ret->opcode = OP_REGVAR;
1601 cfg->ret->inst_c0 = cinfo->ret.reg;
1602 cfg->ret->dreg = cinfo->ret.reg;
1604 case ArgValuetypeAddrInIReg:
1605 case ArgGsharedvtVariableInReg:
1606 /* The register is volatile */
1607 cfg->vret_addr->opcode = OP_REGOFFSET;
1608 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1609 if (cfg->arch.omit_fp) {
1610 cfg->vret_addr->inst_offset = offset;
1614 cfg->vret_addr->inst_offset = -offset;
1616 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1617 printf ("vret_addr =");
1618 mono_print_ins (cfg->vret_addr);
1621 case ArgValuetypeInReg:
1622 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1623 cfg->ret->opcode = OP_REGOFFSET;
1624 cfg->ret->inst_basereg = cfg->frame_reg;
1625 if (cfg->arch.omit_fp) {
1626 cfg->ret->inst_offset = offset;
1627 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1629 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1630 cfg->ret->inst_offset = - offset;
1634 g_assert_not_reached ();
1638 /* Allocate locals */
1639 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1640 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1641 char *mname = mono_method_full_name (cfg->method, TRUE);
1642 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1647 if (locals_stack_align) {
1648 offset += (locals_stack_align - 1);
1649 offset &= ~(locals_stack_align - 1);
1651 if (cfg->arch.omit_fp) {
1652 cfg->locals_min_stack_offset = offset;
1653 cfg->locals_max_stack_offset = offset + locals_stack_size;
1655 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1656 cfg->locals_max_stack_offset = - offset;
1659 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1660 if (offsets [i] != -1) {
1661 MonoInst *ins = cfg->varinfo [i];
1662 ins->opcode = OP_REGOFFSET;
1663 ins->inst_basereg = cfg->frame_reg;
1664 if (cfg->arch.omit_fp)
1665 ins->inst_offset = (offset + offsets [i]);
1667 ins->inst_offset = - (offset + offsets [i]);
1668 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1671 offset += locals_stack_size;
1673 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1674 g_assert (!cfg->arch.omit_fp);
1675 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1676 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1679 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1680 ins = cfg->args [i];
1681 if (ins->opcode != OP_REGVAR) {
1682 ArgInfo *ainfo = &cinfo->args [i];
1683 gboolean inreg = TRUE;
1685 /* FIXME: Allocate volatile arguments to registers */
1686 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1690 * Under AMD64, all registers used to pass arguments to functions
1691 * are volatile across calls.
1692 * FIXME: Optimize this.
1694 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1697 ins->opcode = OP_REGOFFSET;
1699 switch (ainfo->storage) {
1701 case ArgInFloatSSEReg:
1702 case ArgInDoubleSSEReg:
1703 case ArgGSharedVtInReg:
1705 ins->opcode = OP_REGVAR;
1706 ins->dreg = ainfo->reg;
1710 case ArgGSharedVtOnStack:
1711 g_assert (!cfg->arch.omit_fp);
1712 ins->opcode = OP_REGOFFSET;
1713 ins->inst_basereg = cfg->frame_reg;
1714 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1716 case ArgValuetypeInReg:
1718 case ArgValuetypeAddrInIReg:
1719 case ArgValuetypeAddrOnStack: {
1721 g_assert (!cfg->arch.omit_fp);
1722 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1723 MONO_INST_NEW (cfg, indir, 0);
1725 indir->opcode = OP_REGOFFSET;
1726 if (ainfo->pair_storage [0] == ArgInIReg) {
1727 indir->inst_basereg = cfg->frame_reg;
1728 offset = ALIGN_TO (offset, sizeof (gpointer));
1729 offset += (sizeof (gpointer));
1730 indir->inst_offset = - offset;
1733 indir->inst_basereg = cfg->frame_reg;
1734 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1737 ins->opcode = OP_VTARG_ADDR;
1738 ins->inst_left = indir;
1746 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1747 ins->opcode = OP_REGOFFSET;
1748 ins->inst_basereg = cfg->frame_reg;
1749 /* These arguments are saved to the stack in the prolog */
1750 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1751 if (cfg->arch.omit_fp) {
1752 ins->inst_offset = offset;
1753 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1754 // Arguments are yet supported by the stack map creation code
1755 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1757 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1758 ins->inst_offset = - offset;
1759 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1765 cfg->stack_offset = offset;
1769 mono_arch_create_vars (MonoCompile *cfg)
1771 MonoMethodSignature *sig;
1775 sig = mono_method_signature (cfg->method);
1777 if (!cfg->arch.cinfo)
1778 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1779 cinfo = (CallInfo *)cfg->arch.cinfo;
1781 if (cinfo->ret.storage == ArgValuetypeInReg)
1782 cfg->ret_var_is_local = TRUE;
1784 sig_ret = mini_get_underlying_type (sig->ret);
1785 if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1786 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1787 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1788 printf ("vret_addr = ");
1789 mono_print_ins (cfg->vret_addr);
1793 if (cfg->gen_sdb_seq_points) {
1796 if (cfg->compile_aot) {
1797 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1798 ins->flags |= MONO_INST_VOLATILE;
1799 cfg->arch.seq_point_info_var = ins;
1801 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1802 ins->flags |= MONO_INST_VOLATILE;
1803 cfg->arch.ss_tramp_var = ins;
1805 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1806 ins->flags |= MONO_INST_VOLATILE;
1807 cfg->arch.bp_tramp_var = ins;
1810 if (cfg->method->save_lmf)
1811 cfg->create_lmf_var = TRUE;
1813 if (cfg->method->save_lmf) {
1819 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1825 MONO_INST_NEW (cfg, ins, OP_MOVE);
1826 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1827 ins->sreg1 = tree->dreg;
1828 MONO_ADD_INS (cfg->cbb, ins);
1829 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1831 case ArgInFloatSSEReg:
1832 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1833 ins->dreg = mono_alloc_freg (cfg);
1834 ins->sreg1 = tree->dreg;
1835 MONO_ADD_INS (cfg->cbb, ins);
1837 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1839 case ArgInDoubleSSEReg:
1840 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1841 ins->dreg = mono_alloc_freg (cfg);
1842 ins->sreg1 = tree->dreg;
1843 MONO_ADD_INS (cfg->cbb, ins);
1845 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1849 g_assert_not_reached ();
1854 arg_storage_to_load_membase (ArgStorage storage)
1858 #if defined(__mono_ilp32__)
1859 return OP_LOADI8_MEMBASE;
1861 return OP_LOAD_MEMBASE;
1863 case ArgInDoubleSSEReg:
1864 return OP_LOADR8_MEMBASE;
1865 case ArgInFloatSSEReg:
1866 return OP_LOADR4_MEMBASE;
1868 g_assert_not_reached ();
1875 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1877 MonoMethodSignature *tmp_sig;
1880 if (call->tail_call)
1883 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1886 * mono_ArgIterator_Setup assumes the signature cookie is
1887 * passed first and all the arguments which were before it are
1888 * passed on the stack after the signature. So compensate by
1889 * passing a different signature.
1891 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1892 tmp_sig->param_count -= call->signature->sentinelpos;
1893 tmp_sig->sentinelpos = 0;
1894 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1896 sig_reg = mono_alloc_ireg (cfg);
1897 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1899 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1903 static inline LLVMArgStorage
1904 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1908 return LLVMArgInIReg;
1911 case ArgGSharedVtInReg:
1912 case ArgGSharedVtOnStack:
1913 return LLVMArgGSharedVt;
1915 g_assert_not_reached ();
1921 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1927 LLVMCallInfo *linfo;
1928 MonoType *t, *sig_ret;
1930 n = sig->param_count + sig->hasthis;
1931 sig_ret = mini_get_underlying_type (sig->ret);
1933 cinfo = get_call_info (cfg->mempool, sig);
1935 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1938 * LLVM always uses the native ABI while we use our own ABI, the
1939 * only difference is the handling of vtypes:
1940 * - we only pass/receive them in registers in some cases, and only
1941 * in 1 or 2 integer registers.
1943 switch (cinfo->ret.storage) {
1945 linfo->ret.storage = LLVMArgNone;
1948 case ArgInFloatSSEReg:
1949 case ArgInDoubleSSEReg:
1950 linfo->ret.storage = LLVMArgNormal;
1952 case ArgValuetypeInReg: {
1953 ainfo = &cinfo->ret;
1956 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1957 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1958 cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1959 cfg->disable_llvm = TRUE;
1963 linfo->ret.storage = LLVMArgVtypeInReg;
1964 for (j = 0; j < 2; ++j)
1965 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1968 case ArgValuetypeAddrInIReg:
1969 case ArgGsharedvtVariableInReg:
1970 /* Vtype returned using a hidden argument */
1971 linfo->ret.storage = LLVMArgVtypeRetAddr;
1972 linfo->vret_arg_index = cinfo->vret_arg_index;
1975 g_assert_not_reached ();
1979 for (i = 0; i < n; ++i) {
1980 ainfo = cinfo->args + i;
1982 if (i >= sig->hasthis)
1983 t = sig->params [i - sig->hasthis];
1985 t = &mono_defaults.int_class->byval_arg;
1986 t = mini_type_get_underlying_type (t);
1988 linfo->args [i].storage = LLVMArgNone;
1990 switch (ainfo->storage) {
1992 linfo->args [i].storage = LLVMArgNormal;
1994 case ArgInDoubleSSEReg:
1995 case ArgInFloatSSEReg:
1996 linfo->args [i].storage = LLVMArgNormal;
1999 if (MONO_TYPE_ISSTRUCT (t))
2000 linfo->args [i].storage = LLVMArgVtypeByVal;
2002 linfo->args [i].storage = LLVMArgNormal;
2004 case ArgValuetypeInReg:
2006 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2007 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2008 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2009 cfg->disable_llvm = TRUE;
2013 linfo->args [i].storage = LLVMArgVtypeInReg;
2014 for (j = 0; j < 2; ++j)
2015 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2017 case ArgGSharedVtInReg:
2018 case ArgGSharedVtOnStack:
2019 linfo->args [i].storage = LLVMArgGSharedVt;
2022 cfg->exception_message = g_strdup ("ainfo->storage");
2023 cfg->disable_llvm = TRUE;
2033 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2036 MonoMethodSignature *sig;
2042 sig = call->signature;
2043 n = sig->param_count + sig->hasthis;
2045 cinfo = get_call_info (cfg->mempool, sig);
2049 if (COMPILE_LLVM (cfg)) {
2050 /* We shouldn't be called in the llvm case */
2051 cfg->disable_llvm = TRUE;
2056 * Emit all arguments which are passed on the stack to prevent register
2057 * allocation problems.
2059 for (i = 0; i < n; ++i) {
2061 ainfo = cinfo->args + i;
2063 in = call->args [i];
2065 if (sig->hasthis && i == 0)
2066 t = &mono_defaults.object_class->byval_arg;
2068 t = sig->params [i - sig->hasthis];
2070 t = mini_get_underlying_type (t);
2071 //XXX what about ArgGSharedVtOnStack here?
2072 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2074 if (t->type == MONO_TYPE_R4)
2075 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2076 else if (t->type == MONO_TYPE_R8)
2077 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2079 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2081 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2083 if (cfg->compute_gc_maps) {
2086 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2092 * Emit all parameters passed in registers in non-reverse order for better readability
2093 * and to help the optimization in emit_prolog ().
2095 for (i = 0; i < n; ++i) {
2096 ainfo = cinfo->args + i;
2098 in = call->args [i];
2100 if (ainfo->storage == ArgInIReg)
2101 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2104 for (i = n - 1; i >= 0; --i) {
2107 ainfo = cinfo->args + i;
2109 in = call->args [i];
2111 if (sig->hasthis && i == 0)
2112 t = &mono_defaults.object_class->byval_arg;
2114 t = sig->params [i - sig->hasthis];
2115 t = mini_get_underlying_type (t);
2117 switch (ainfo->storage) {
2121 case ArgInFloatSSEReg:
2122 case ArgInDoubleSSEReg:
2123 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2126 case ArgValuetypeInReg:
2127 case ArgValuetypeAddrInIReg:
2128 case ArgValuetypeAddrOnStack:
2129 case ArgGSharedVtInReg:
2130 case ArgGSharedVtOnStack: {
2131 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2132 /* Already emitted above */
2134 //FIXME what about ArgGSharedVtOnStack ?
2135 if (ainfo->storage == ArgOnStack && call->tail_call) {
2136 MonoInst *call_inst = (MonoInst*)call;
2137 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2138 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2146 size = mono_type_native_stack_size (t, &align);
2149 * Other backends use mono_type_stack_size (), but that
2150 * aligns the size to 8, which is larger than the size of
2151 * the source, leading to reads of invalid memory if the
2152 * source is at the end of address space.
2154 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2157 if (size >= 10000) {
2158 /* Avoid asserts in emit_memcpy () */
2159 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2160 /* Continue normally */
2163 if (size > 0 || ainfo->pass_empty_struct) {
2164 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2165 arg->sreg1 = in->dreg;
2166 arg->klass = mono_class_from_mono_type (t);
2167 arg->backend.size = size;
2168 arg->inst_p0 = call;
2169 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2170 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2172 MONO_ADD_INS (cfg->cbb, arg);
2177 g_assert_not_reached ();
2180 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2181 /* Emit the signature cookie just before the implicit arguments */
2182 emit_sig_cookie (cfg, call, cinfo);
2185 /* Handle the case where there are no implicit arguments */
2186 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2187 emit_sig_cookie (cfg, call, cinfo);
2189 switch (cinfo->ret.storage) {
2190 case ArgValuetypeInReg:
2191 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2193 * Tell the JIT to use a more efficient calling convention: call using
2194 * OP_CALL, compute the result location after the call, and save the
2197 call->vret_in_reg = TRUE;
2199 * Nullify the instruction computing the vret addr to enable
2200 * future optimizations.
2203 NULLIFY_INS (call->vret_var);
2205 if (call->tail_call)
2208 * The valuetype is in RAX:RDX after the call, need to be copied to
2209 * the stack. Push the address here, so the call instruction can
2212 if (!cfg->arch.vret_addr_loc) {
2213 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2214 /* Prevent it from being register allocated or optimized away */
2215 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2218 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2221 case ArgValuetypeAddrInIReg:
2222 case ArgGsharedvtVariableInReg: {
2224 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2225 vtarg->sreg1 = call->vret_var->dreg;
2226 vtarg->dreg = mono_alloc_preg (cfg);
2227 MONO_ADD_INS (cfg->cbb, vtarg);
2229 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2236 if (cfg->method->save_lmf) {
2237 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2238 MONO_ADD_INS (cfg->cbb, arg);
2241 call->stack_usage = cinfo->stack_usage;
2245 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2248 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2249 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2250 int size = ins->backend.size;
2252 switch (ainfo->storage) {
2253 case ArgValuetypeInReg: {
2257 for (part = 0; part < 2; ++part) {
2258 if (ainfo->pair_storage [part] == ArgNone)
2261 if (ainfo->pass_empty_struct) {
2262 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2263 NEW_ICONST (cfg, load, 0);
2266 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2267 load->inst_basereg = src->dreg;
2268 load->inst_offset = part * sizeof(mgreg_t);
2270 switch (ainfo->pair_storage [part]) {
2272 load->dreg = mono_alloc_ireg (cfg);
2274 case ArgInDoubleSSEReg:
2275 case ArgInFloatSSEReg:
2276 load->dreg = mono_alloc_freg (cfg);
2279 g_assert_not_reached ();
2283 MONO_ADD_INS (cfg->cbb, load);
2285 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2289 case ArgValuetypeAddrInIReg:
2290 case ArgValuetypeAddrOnStack: {
2291 MonoInst *vtaddr, *load;
2293 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2295 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2297 MONO_INST_NEW (cfg, load, OP_LDADDR);
2298 cfg->has_indirection = TRUE;
2299 load->inst_p0 = vtaddr;
2300 vtaddr->flags |= MONO_INST_INDIRECT;
2301 load->type = STACK_MP;
2302 load->klass = vtaddr->klass;
2303 load->dreg = mono_alloc_ireg (cfg);
2304 MONO_ADD_INS (cfg->cbb, load);
2305 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2307 if (ainfo->pair_storage [0] == ArgInIReg) {
2308 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2309 arg->dreg = mono_alloc_ireg (cfg);
2310 arg->sreg1 = load->dreg;
2312 MONO_ADD_INS (cfg->cbb, arg);
2313 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2315 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2319 case ArgGSharedVtInReg:
2321 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2323 case ArgGSharedVtOnStack:
2324 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2328 int dreg = mono_alloc_ireg (cfg);
2330 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2331 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2332 } else if (size <= 40) {
2333 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2335 // FIXME: Code growth
2336 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2339 if (cfg->compute_gc_maps) {
2341 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2347 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2349 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2351 if (ret->type == MONO_TYPE_R4) {
2352 if (COMPILE_LLVM (cfg))
2353 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2355 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2357 } else if (ret->type == MONO_TYPE_R8) {
2358 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2362 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2365 #endif /* DISABLE_JIT */
2367 #define EMIT_COND_BRANCH(ins,cond,sign) \
2368 if (ins->inst_true_bb->native_offset) { \
2369 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2371 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2372 if ((cfg->opt & MONO_OPT_BRANCH) && \
2373 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2374 x86_branch8 (code, cond, 0, sign); \
2376 x86_branch32 (code, cond, 0, sign); \
2380 MonoMethodSignature *sig;
2385 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2389 switch (cinfo->ret.storage) {
2392 case ArgInFloatSSEReg:
2393 case ArgInDoubleSSEReg:
2394 case ArgValuetypeAddrInIReg:
2395 case ArgValuetypeInReg:
2401 for (i = 0; i < cinfo->nargs; ++i) {
2402 ArgInfo *ainfo = &cinfo->args [i];
2403 switch (ainfo->storage) {
2405 case ArgInFloatSSEReg:
2406 case ArgInDoubleSSEReg:
2407 case ArgValuetypeInReg:
2410 if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2422 * mono_arch_dyn_call_prepare:
2424 * Return a pointer to an arch-specific structure which contains information
2425 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2426 * supported for SIG.
2427 * This function is equivalent to ffi_prep_cif in libffi.
2430 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2432 ArchDynCallInfo *info;
2435 cinfo = get_call_info (NULL, sig);
2437 if (!dyn_call_supported (sig, cinfo)) {
2442 info = g_new0 (ArchDynCallInfo, 1);
2443 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2445 info->cinfo = cinfo;
2447 return (MonoDynCallInfo*)info;
2451 * mono_arch_dyn_call_free:
2453 * Free a MonoDynCallInfo structure.
2456 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2458 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2460 g_free (ainfo->cinfo);
2464 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2465 #define GREG_TO_PTR(greg) (gpointer)(greg)
2468 * mono_arch_get_start_dyn_call:
2470 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2471 * store the result into BUF.
2472 * ARGS should be an array of pointers pointing to the arguments.
2473 * RET should point to a memory buffer large enought to hold the result of the
2475 * This function should be as fast as possible, any work which does not depend
2476 * on the actual values of the arguments should be done in
2477 * mono_arch_dyn_call_prepare ().
2478 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2482 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2484 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2485 DynCallArgs *p = (DynCallArgs*)buf;
2486 int arg_index, greg, freg, i, pindex;
2487 MonoMethodSignature *sig = dinfo->sig;
2488 int buffer_offset = 0;
2489 static int param_reg_to_index [16];
2490 static gboolean param_reg_to_index_inited;
2492 if (!param_reg_to_index_inited) {
2493 for (i = 0; i < PARAM_REGS; ++i)
2494 param_reg_to_index [param_regs [i]] = i;
2495 mono_memory_barrier ();
2496 param_reg_to_index_inited = 1;
2499 g_assert (buf_len >= sizeof (DynCallArgs));
2509 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2510 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2515 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2516 p->regs [greg ++] = PTR_TO_GREG(ret);
2518 for (; pindex < sig->param_count; pindex++) {
2519 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2520 gpointer *arg = args [arg_index ++];
2521 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2524 if (ainfo->storage == ArgOnStack) {
2525 slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2527 slot = param_reg_to_index [ainfo->reg];
2531 p->regs [slot] = PTR_TO_GREG(*(arg));
2537 case MONO_TYPE_OBJECT:
2541 #if !defined(__mono_ilp32__)
2545 p->regs [slot] = PTR_TO_GREG(*(arg));
2547 #if defined(__mono_ilp32__)
2550 p->regs [slot] = *(guint64*)(arg);
2554 p->regs [slot] = *(guint8*)(arg);
2557 p->regs [slot] = *(gint8*)(arg);
2560 p->regs [slot] = *(gint16*)(arg);
2563 p->regs [slot] = *(guint16*)(arg);
2566 p->regs [slot] = *(gint32*)(arg);
2569 p->regs [slot] = *(guint32*)(arg);
2571 case MONO_TYPE_R4: {
2574 *(float*)&d = *(float*)(arg);
2576 p->fregs [freg ++] = d;
2581 p->fregs [freg ++] = *(double*)(arg);
2583 case MONO_TYPE_GENERICINST:
2584 if (MONO_TYPE_IS_REFERENCE (t)) {
2585 p->regs [slot] = PTR_TO_GREG(*(arg));
2587 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2588 MonoClass *klass = mono_class_from_mono_type (t);
2589 guint8 *nullable_buf;
2592 size = mono_class_value_size (klass, NULL);
2593 nullable_buf = p->buffer + buffer_offset;
2594 buffer_offset += size;
2595 g_assert (buffer_offset <= 256);
2597 /* The argument pointed to by arg is either a boxed vtype or null */
2598 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2600 arg = (gpointer*)nullable_buf;
2606 case MONO_TYPE_VALUETYPE: {
2607 switch (ainfo->storage) {
2608 case ArgValuetypeInReg:
2609 for (i = 0; i < 2; ++i) {
2610 switch (ainfo->pair_storage [i]) {
2614 slot = param_reg_to_index [ainfo->pair_regs [i]];
2615 p->regs [slot] = ((mgreg_t*)(arg))[i];
2617 case ArgInDoubleSSEReg:
2619 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2622 g_assert_not_reached ();
2628 for (i = 0; i < ainfo->arg_size / 8; ++i)
2629 p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2632 g_assert_not_reached ();
2638 g_assert_not_reached ();
2644 * mono_arch_finish_dyn_call:
2646 * Store the result of a dyn call into the return value buffer passed to
2647 * start_dyn_call ().
2648 * This function should be as fast as possible, any work which does not depend
2649 * on the actual values of the arguments should be done in
2650 * mono_arch_dyn_call_prepare ().
2653 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2655 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2656 MonoMethodSignature *sig = dinfo->sig;
2657 DynCallArgs *dargs = (DynCallArgs*)buf;
2658 guint8 *ret = dargs->ret;
2659 mgreg_t res = dargs->res;
2660 MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2663 switch (sig_ret->type) {
2664 case MONO_TYPE_VOID:
2665 *(gpointer*)ret = NULL;
2667 case MONO_TYPE_OBJECT:
2671 *(gpointer*)ret = GREG_TO_PTR(res);
2677 *(guint8*)ret = res;
2680 *(gint16*)ret = res;
2683 *(guint16*)ret = res;
2686 *(gint32*)ret = res;
2689 *(guint32*)ret = res;
2692 *(gint64*)ret = res;
2695 *(guint64*)ret = res;
2698 *(float*)ret = *(float*)&(dargs->fregs [0]);
2701 *(double*)ret = dargs->fregs [0];
2703 case MONO_TYPE_GENERICINST:
2704 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2705 *(gpointer*)ret = GREG_TO_PTR(res);
2710 case MONO_TYPE_VALUETYPE:
2711 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2714 ArgInfo *ainfo = &dinfo->cinfo->ret;
2716 g_assert (ainfo->storage == ArgValuetypeInReg);
2718 for (i = 0; i < 2; ++i) {
2719 switch (ainfo->pair_storage [0]) {
2721 ((mgreg_t*)ret)[i] = res;
2723 case ArgInDoubleSSEReg:
2724 ((double*)ret)[i] = dargs->fregs [i];
2729 g_assert_not_reached ();
2736 g_assert_not_reached ();
2740 /* emit an exception if condition is fail */
2741 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2743 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2744 if (tins == NULL) { \
2745 mono_add_patch_info (cfg, code - cfg->native_code, \
2746 MONO_PATCH_INFO_EXC, exc_name); \
2747 x86_branch32 (code, cond, 0, signed); \
2749 EMIT_COND_BRANCH (tins, cond, signed); \
2753 #define EMIT_FPCOMPARE(code) do { \
2754 amd64_fcompp (code); \
2755 amd64_fnstsw (code); \
2758 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2759 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2760 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2761 amd64_ ##op (code); \
2762 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2763 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2767 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2769 gboolean no_patch = FALSE;
2772 * FIXME: Add support for thunks
2775 gboolean near_call = FALSE;
2778 * Indirect calls are expensive so try to make a near call if possible.
2779 * The caller memory is allocated by the code manager so it is
2780 * guaranteed to be at a 32 bit offset.
2783 if (patch_type != MONO_PATCH_INFO_ABS) {
2784 /* The target is in memory allocated using the code manager */
2787 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2788 if (((MonoMethod*)data)->klass->image->aot_module)
2789 /* The callee might be an AOT method */
2791 if (((MonoMethod*)data)->dynamic)
2792 /* The target is in malloc-ed memory */
2796 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2798 * The call might go directly to a native function without
2801 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2803 gconstpointer target = mono_icall_get_wrapper (mi);
2804 if ((((guint64)target) >> 32) != 0)
2810 MonoJumpInfo *jinfo = NULL;
2812 if (cfg->abs_patches)
2813 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2815 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2816 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2817 if (mi && (((guint64)mi->func) >> 32) == 0)
2822 * This is not really an optimization, but required because the
2823 * generic class init trampolines use R11 to pass the vtable.
2828 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2830 if (info->func == info->wrapper) {
2832 if ((((guint64)info->func) >> 32) == 0)
2836 /* See the comment in mono_codegen () */
2837 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2841 else if ((((guint64)data) >> 32) == 0) {
2848 if (cfg->method->dynamic)
2849 /* These methods are allocated using malloc */
2852 #ifdef MONO_ARCH_NOMAP32BIT
2855 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2856 if (optimize_for_xen)
2859 if (cfg->compile_aot) {
2866 * Align the call displacement to an address divisible by 4 so it does
2867 * not span cache lines. This is required for code patching to work on SMP
2870 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2871 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2872 amd64_padding (code, pad_size);
2874 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2875 amd64_call_code (code, 0);
2878 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2879 amd64_set_reg_template (code, GP_SCRATCH_REG);
2880 amd64_call_reg (code, GP_SCRATCH_REG);
2887 static inline guint8*
2888 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2891 if (win64_adjust_stack)
2892 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2894 code = emit_call_body (cfg, code, patch_type, data);
2896 if (win64_adjust_stack)
2897 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2904 store_membase_imm_to_store_membase_reg (int opcode)
2907 case OP_STORE_MEMBASE_IMM:
2908 return OP_STORE_MEMBASE_REG;
2909 case OP_STOREI4_MEMBASE_IMM:
2910 return OP_STOREI4_MEMBASE_REG;
2911 case OP_STOREI8_MEMBASE_IMM:
2912 return OP_STOREI8_MEMBASE_REG;
2920 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2923 * mono_arch_peephole_pass_1:
2925 * Perform peephole opts which should/can be performed before local regalloc
2928 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2932 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2933 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2935 switch (ins->opcode) {
2939 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2941 * X86_LEA is like ADD, but doesn't have the
2942 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2943 * its operand to 64 bit.
2945 ins->opcode = OP_X86_LEA_MEMBASE;
2946 ins->inst_basereg = ins->sreg1;
2951 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2955 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2956 * the latter has length 2-3 instead of 6 (reverse constant
2957 * propagation). These instruction sequences are very common
2958 * in the initlocals bblock.
2960 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2961 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2962 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2963 ins2->sreg1 = ins->dreg;
2964 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2966 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2969 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2977 case OP_COMPARE_IMM:
2978 case OP_LCOMPARE_IMM:
2979 /* OP_COMPARE_IMM (reg, 0)
2981 * OP_AMD64_TEST_NULL (reg)
2984 ins->opcode = OP_AMD64_TEST_NULL;
2986 case OP_ICOMPARE_IMM:
2988 ins->opcode = OP_X86_TEST_NULL;
2990 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2992 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2993 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2995 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2996 * OP_COMPARE_IMM reg, imm
2998 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3000 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3001 ins->inst_basereg == last_ins->inst_destbasereg &&
3002 ins->inst_offset == last_ins->inst_offset) {
3003 ins->opcode = OP_ICOMPARE_IMM;
3004 ins->sreg1 = last_ins->sreg1;
3006 /* check if we can remove cmp reg,0 with test null */
3008 ins->opcode = OP_X86_TEST_NULL;
3014 mono_peephole_ins (bb, ins);
3019 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3023 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3024 switch (ins->opcode) {
3027 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3028 /* reg = 0 -> XOR (reg, reg) */
3029 /* XOR sets cflags on x86, so we cant do it always */
3030 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3031 ins->opcode = OP_LXOR;
3032 ins->sreg1 = ins->dreg;
3033 ins->sreg2 = ins->dreg;
3041 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3042 * 0 result into 64 bits.
3044 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3045 ins->opcode = OP_IXOR;
3049 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3053 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3054 * the latter has length 2-3 instead of 6 (reverse constant
3055 * propagation). These instruction sequences are very common
3056 * in the initlocals bblock.
3058 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3059 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3060 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3061 ins2->sreg1 = ins->dreg;
3062 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3064 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3067 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3076 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3077 ins->opcode = OP_X86_INC_REG;
3080 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3081 ins->opcode = OP_X86_DEC_REG;
3085 mono_peephole_ins (bb, ins);
3089 #define NEW_INS(cfg,ins,dest,op) do { \
3090 MONO_INST_NEW ((cfg), (dest), (op)); \
3091 (dest)->cil_code = (ins)->cil_code; \
3092 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3096 * mono_arch_lowering_pass:
3098 * Converts complex opcodes into simpler ones so that each IR instruction
3099 * corresponds to one machine instruction.
3102 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3104 MonoInst *ins, *n, *temp;
3107 * FIXME: Need to add more instructions, but the current machine
3108 * description can't model some parts of the composite instructions like
3111 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3112 switch (ins->opcode) {
3116 case OP_IDIV_UN_IMM:
3117 case OP_IREM_UN_IMM:
3120 mono_decompose_op_imm (cfg, bb, ins);
3122 case OP_COMPARE_IMM:
3123 case OP_LCOMPARE_IMM:
3124 if (!amd64_use_imm32 (ins->inst_imm)) {
3125 NEW_INS (cfg, ins, temp, OP_I8CONST);
3126 temp->inst_c0 = ins->inst_imm;
3127 temp->dreg = mono_alloc_ireg (cfg);
3128 ins->opcode = OP_COMPARE;
3129 ins->sreg2 = temp->dreg;
3132 #ifndef __mono_ilp32__
3133 case OP_LOAD_MEMBASE:
3135 case OP_LOADI8_MEMBASE:
3136 /* Don't generate memindex opcodes (to simplify */
3137 /* read sandboxing) */
3138 if (!amd64_use_imm32 (ins->inst_offset)) {
3139 NEW_INS (cfg, ins, temp, OP_I8CONST);
3140 temp->inst_c0 = ins->inst_offset;
3141 temp->dreg = mono_alloc_ireg (cfg);
3142 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3143 ins->inst_indexreg = temp->dreg;
3146 #ifndef __mono_ilp32__
3147 case OP_STORE_MEMBASE_IMM:
3149 case OP_STOREI8_MEMBASE_IMM:
3150 if (!amd64_use_imm32 (ins->inst_imm)) {
3151 NEW_INS (cfg, ins, temp, OP_I8CONST);
3152 temp->inst_c0 = ins->inst_imm;
3153 temp->dreg = mono_alloc_ireg (cfg);
3154 ins->opcode = OP_STOREI8_MEMBASE_REG;
3155 ins->sreg1 = temp->dreg;
3158 #ifdef MONO_ARCH_SIMD_INTRINSICS
3159 case OP_EXPAND_I1: {
3160 int temp_reg1 = mono_alloc_ireg (cfg);
3161 int temp_reg2 = mono_alloc_ireg (cfg);
3162 int original_reg = ins->sreg1;
3164 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3165 temp->sreg1 = original_reg;
3166 temp->dreg = temp_reg1;
3168 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3169 temp->sreg1 = temp_reg1;
3170 temp->dreg = temp_reg2;
3173 NEW_INS (cfg, ins, temp, OP_LOR);
3174 temp->sreg1 = temp->dreg = temp_reg2;
3175 temp->sreg2 = temp_reg1;
3177 ins->opcode = OP_EXPAND_I2;
3178 ins->sreg1 = temp_reg2;
3187 bb->max_vreg = cfg->next_vreg;
3191 branch_cc_table [] = {
3192 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3193 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3194 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3197 /* Maps CMP_... constants to X86_CC_... constants */
3200 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3201 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3205 cc_signed_table [] = {
3206 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3207 FALSE, FALSE, FALSE, FALSE
3210 /*#include "cprop.c"*/
3212 static unsigned char*
3213 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3216 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3218 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3221 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3223 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3227 static unsigned char*
3228 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3230 int sreg = tree->sreg1;
3231 int need_touch = FALSE;
3233 #if defined(TARGET_WIN32)
3235 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3236 if (!tree->flags & MONO_INST_INIT)
3245 * If requested stack size is larger than one page,
3246 * perform stack-touch operation
3249 * Generate stack probe code.
3250 * Under Windows, it is necessary to allocate one page at a time,
3251 * "touching" stack after each successful sub-allocation. This is
3252 * because of the way stack growth is implemented - there is a
3253 * guard page before the lowest stack page that is currently commited.
3254 * Stack normally grows sequentially so OS traps access to the
3255 * guard page and commits more pages when needed.
3257 amd64_test_reg_imm (code, sreg, ~0xFFF);
3258 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3260 br[2] = code; /* loop */
3261 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3262 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3263 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3264 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3265 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3266 amd64_patch (br[3], br[2]);
3267 amd64_test_reg_reg (code, sreg, sreg);
3268 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3269 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3271 br[1] = code; x86_jump8 (code, 0);
3273 amd64_patch (br[0], code);
3274 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3275 amd64_patch (br[1], code);
3276 amd64_patch (br[4], code);
3279 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3281 if (tree->flags & MONO_INST_INIT) {
3283 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3284 amd64_push_reg (code, AMD64_RAX);
3287 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3288 amd64_push_reg (code, AMD64_RCX);
3291 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3292 amd64_push_reg (code, AMD64_RDI);
3296 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3297 if (sreg != AMD64_RCX)
3298 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3299 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3301 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3302 if (cfg->param_area)
3303 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3305 amd64_prefix (code, X86_REP_PREFIX);
3308 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3309 amd64_pop_reg (code, AMD64_RDI);
3310 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3311 amd64_pop_reg (code, AMD64_RCX);
3312 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3313 amd64_pop_reg (code, AMD64_RAX);
3319 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3324 /* Move return value to the target register */
3325 /* FIXME: do this in the local reg allocator */
3326 switch (ins->opcode) {
3329 case OP_CALL_MEMBASE:
3332 case OP_LCALL_MEMBASE:
3333 g_assert (ins->dreg == AMD64_RAX);
3337 case OP_FCALL_MEMBASE: {
3338 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3339 if (rtype->type == MONO_TYPE_R4) {
3340 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3343 if (ins->dreg != AMD64_XMM0)
3344 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3350 case OP_RCALL_MEMBASE:
3351 if (ins->dreg != AMD64_XMM0)
3352 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3356 case OP_VCALL_MEMBASE:
3359 case OP_VCALL2_MEMBASE:
3360 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3361 if (cinfo->ret.storage == ArgValuetypeInReg) {
3362 MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3364 /* Load the destination address */
3365 g_assert (loc->opcode == OP_REGOFFSET);
3366 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3368 for (quad = 0; quad < 2; quad ++) {
3369 switch (cinfo->ret.pair_storage [quad]) {
3371 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3373 case ArgInFloatSSEReg:
3374 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3376 case ArgInDoubleSSEReg:
3377 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3392 #endif /* DISABLE_JIT */
3395 static int tls_gs_offset;
3399 mono_arch_have_fast_tls (void)
3402 static gboolean have_fast_tls = FALSE;
3403 static gboolean inited = FALSE;
3406 if (mini_get_debug_options ()->use_fallback_tls)
3410 return have_fast_tls;
3412 ins = (guint8*)pthread_getspecific;
3415 * We're looking for these two instructions:
3417 * mov %gs:[offset](,%rdi,8),%rax
3420 have_fast_tls = ins [0] == 0x65 &&
3430 tls_gs_offset = ins[5];
3433 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3434 * For that version we're looking for these instructions:
3438 * mov %gs:[offset](,%rdi,8),%rax
3442 if (!have_fast_tls) {
3443 have_fast_tls = ins [0] == 0x55 &&
3458 tls_gs_offset = ins[9];
3462 return have_fast_tls;
3463 #elif defined(TARGET_ANDROID)
3466 if (mini_get_debug_options ()->use_fallback_tls)
3473 mono_amd64_get_tls_gs_offset (void)
3476 return tls_gs_offset;
3478 g_assert_not_reached ();
3484 * \param code buffer to store code to
3485 * \param dreg hard register where to place the result
3486 * \param tls_offset offset info
3487 * \return a pointer to the end of the stored code
3489 * mono_amd64_emit_tls_get emits in \p code the native code that puts in
3490 * the dreg register the item in the thread local storage identified
3494 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3497 if (tls_offset < 64) {
3498 x86_prefix (code, X86_GS_PREFIX);
3499 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3503 g_assert (tls_offset < 0x440);
3504 /* Load TEB->TlsExpansionSlots */
3505 x86_prefix (code, X86_GS_PREFIX);
3506 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3507 amd64_test_reg_reg (code, dreg, dreg);
3509 amd64_branch (code, X86_CC_EQ, code, TRUE);
3510 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3511 amd64_patch (buf [0], code);
3513 #elif defined(TARGET_MACH)
3514 x86_prefix (code, X86_GS_PREFIX);
3515 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3517 if (optimize_for_xen) {
3518 x86_prefix (code, X86_FS_PREFIX);
3519 amd64_mov_reg_mem (code, dreg, 0, 8);
3520 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3522 x86_prefix (code, X86_FS_PREFIX);
3523 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3530 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3533 g_assert_not_reached ();
3534 #elif defined(TARGET_MACH)
3535 x86_prefix (code, X86_GS_PREFIX);
3536 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3538 g_assert (!optimize_for_xen);
3539 x86_prefix (code, X86_FS_PREFIX);
3540 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3548 * Emit code to initialize an LMF structure at LMF_OFFSET.
3551 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3554 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3557 * sp is saved right before calls but we need to save it here too so
3558 * async stack walks would work.
3560 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3562 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3563 if (cfg->arch.omit_fp && cfa_offset != -1)
3564 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3566 /* These can't contain refs */
3567 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3568 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3569 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3570 /* These are handled automatically by the stack marking code */
3571 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3578 #define TEB_LAST_ERROR_OFFSET 0x068
3581 emit_get_last_error (guint8* code, int dreg)
3583 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3584 x86_prefix (code, X86_GS_PREFIX);
3585 amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3593 emit_get_last_error (guint8* code, int dreg)
3595 g_assert_not_reached ();
3600 /* benchmark and set based on cpu */
3601 #define LOOP_ALIGNMENT 8
3602 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3606 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3611 guint8 *code = cfg->native_code + cfg->code_len;
3614 /* Fix max_offset estimate for each successor bb */
3615 if (cfg->opt & MONO_OPT_BRANCH) {
3616 int current_offset = cfg->code_len;
3617 MonoBasicBlock *current_bb;
3618 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3619 current_bb->max_offset = current_offset;
3620 current_offset += current_bb->max_length;
3624 if (cfg->opt & MONO_OPT_LOOP) {
3625 int pad, align = LOOP_ALIGNMENT;
3626 /* set alignment depending on cpu */
3627 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3629 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3630 amd64_padding (code, pad);
3631 cfg->code_len += pad;
3632 bb->native_offset = cfg->code_len;
3636 if (cfg->verbose_level > 2)
3637 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3639 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3640 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3641 g_assert (!cfg->compile_aot);
3643 cov->data [bb->dfn].cil_code = bb->cil_code;
3644 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3645 /* this is not thread save, but good enough */
3646 amd64_inc_membase (code, AMD64_R11, 0);
3649 offset = code - cfg->native_code;
3651 mono_debug_open_block (cfg, bb, offset);
3653 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3654 x86_breakpoint (code);
3656 MONO_BB_FOR_EACH_INS (bb, ins) {
3657 offset = code - cfg->native_code;
3659 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3661 #define EXTRA_CODE_SPACE (16)
3663 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3664 cfg->code_size *= 2;
3665 cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3666 code = cfg->native_code + offset;
3667 cfg->stat_code_reallocs++;
3670 if (cfg->debug_info)
3671 mono_debug_record_line_number (cfg, ins, offset);
3673 switch (ins->opcode) {
3675 amd64_mul_reg (code, ins->sreg2, TRUE);
3678 amd64_mul_reg (code, ins->sreg2, FALSE);
3680 case OP_X86_SETEQ_MEMBASE:
3681 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3683 case OP_STOREI1_MEMBASE_IMM:
3684 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3686 case OP_STOREI2_MEMBASE_IMM:
3687 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3689 case OP_STOREI4_MEMBASE_IMM:
3690 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3692 case OP_STOREI1_MEMBASE_REG:
3693 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3695 case OP_STOREI2_MEMBASE_REG:
3696 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3698 /* In AMD64 NaCl, pointers are 4 bytes, */
3699 /* so STORE_* != STOREI8_*. Likewise below. */
3700 case OP_STORE_MEMBASE_REG:
3701 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3703 case OP_STOREI8_MEMBASE_REG:
3704 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3706 case OP_STOREI4_MEMBASE_REG:
3707 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3709 case OP_STORE_MEMBASE_IMM:
3710 /* In NaCl, this could be a PCONST type, which could */
3711 /* mean a pointer type was copied directly into the */
3712 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3713 /* the value would be 0x00000000FFFFFFFF which is */
3714 /* not proper for an imm32 unless you cast it. */
3715 g_assert (amd64_is_imm32 (ins->inst_imm));
3716 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3718 case OP_STOREI8_MEMBASE_IMM:
3719 g_assert (amd64_is_imm32 (ins->inst_imm));
3720 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3723 #ifdef __mono_ilp32__
3724 /* In ILP32, pointers are 4 bytes, so separate these */
3725 /* cases, use literal 8 below where we really want 8 */
3726 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3727 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3731 // FIXME: Decompose this earlier
3732 if (amd64_use_imm32 (ins->inst_imm))
3733 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3735 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3736 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3740 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3741 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3744 // FIXME: Decompose this earlier
3745 if (amd64_use_imm32 (ins->inst_imm))
3746 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3748 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3749 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3753 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3754 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3757 /* For NaCl, pointers are 4 bytes, so separate these */
3758 /* cases, use literal 8 below where we really want 8 */
3759 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3760 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3762 case OP_LOAD_MEMBASE:
3763 g_assert (amd64_is_imm32 (ins->inst_offset));
3764 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3766 case OP_LOADI8_MEMBASE:
3767 /* Use literal 8 instead of sizeof pointer or */
3768 /* register, we really want 8 for this opcode */
3769 g_assert (amd64_is_imm32 (ins->inst_offset));
3770 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3772 case OP_LOADI4_MEMBASE:
3773 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3775 case OP_LOADU4_MEMBASE:
3776 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3778 case OP_LOADU1_MEMBASE:
3779 /* The cpu zero extends the result into 64 bits */
3780 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3782 case OP_LOADI1_MEMBASE:
3783 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3785 case OP_LOADU2_MEMBASE:
3786 /* The cpu zero extends the result into 64 bits */
3787 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3789 case OP_LOADI2_MEMBASE:
3790 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3792 case OP_AMD64_LOADI8_MEMINDEX:
3793 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3795 case OP_LCONV_TO_I1:
3796 case OP_ICONV_TO_I1:
3798 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3800 case OP_LCONV_TO_I2:
3801 case OP_ICONV_TO_I2:
3803 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3805 case OP_LCONV_TO_U1:
3806 case OP_ICONV_TO_U1:
3807 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3809 case OP_LCONV_TO_U2:
3810 case OP_ICONV_TO_U2:
3811 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3814 /* Clean out the upper word */
3815 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3818 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3822 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3824 case OP_COMPARE_IMM:
3825 #if defined(__mono_ilp32__)
3826 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3827 g_assert (amd64_is_imm32 (ins->inst_imm));
3828 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3831 case OP_LCOMPARE_IMM:
3832 g_assert (amd64_is_imm32 (ins->inst_imm));
3833 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3835 case OP_X86_COMPARE_REG_MEMBASE:
3836 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3838 case OP_X86_TEST_NULL:
3839 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3841 case OP_AMD64_TEST_NULL:
3842 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3845 case OP_X86_ADD_REG_MEMBASE:
3846 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3848 case OP_X86_SUB_REG_MEMBASE:
3849 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3851 case OP_X86_AND_REG_MEMBASE:
3852 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3854 case OP_X86_OR_REG_MEMBASE:
3855 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3857 case OP_X86_XOR_REG_MEMBASE:
3858 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3861 case OP_X86_ADD_MEMBASE_IMM:
3862 /* FIXME: Make a 64 version too */
3863 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3865 case OP_X86_SUB_MEMBASE_IMM:
3866 g_assert (amd64_is_imm32 (ins->inst_imm));
3867 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3869 case OP_X86_AND_MEMBASE_IMM:
3870 g_assert (amd64_is_imm32 (ins->inst_imm));
3871 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3873 case OP_X86_OR_MEMBASE_IMM:
3874 g_assert (amd64_is_imm32 (ins->inst_imm));
3875 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3877 case OP_X86_XOR_MEMBASE_IMM:
3878 g_assert (amd64_is_imm32 (ins->inst_imm));
3879 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3881 case OP_X86_ADD_MEMBASE_REG:
3882 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3884 case OP_X86_SUB_MEMBASE_REG:
3885 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3887 case OP_X86_AND_MEMBASE_REG:
3888 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3890 case OP_X86_OR_MEMBASE_REG:
3891 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3893 case OP_X86_XOR_MEMBASE_REG:
3894 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3896 case OP_X86_INC_MEMBASE:
3897 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3899 case OP_X86_INC_REG:
3900 amd64_inc_reg_size (code, ins->dreg, 4);
3902 case OP_X86_DEC_MEMBASE:
3903 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3905 case OP_X86_DEC_REG:
3906 amd64_dec_reg_size (code, ins->dreg, 4);
3908 case OP_X86_MUL_REG_MEMBASE:
3909 case OP_X86_MUL_MEMBASE_REG:
3910 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3912 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3913 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3915 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3916 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3918 case OP_AMD64_COMPARE_MEMBASE_REG:
3919 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3921 case OP_AMD64_COMPARE_MEMBASE_IMM:
3922 g_assert (amd64_is_imm32 (ins->inst_imm));
3923 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3925 case OP_X86_COMPARE_MEMBASE8_IMM:
3926 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3928 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3929 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3931 case OP_AMD64_COMPARE_REG_MEMBASE:
3932 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3935 case OP_AMD64_ADD_REG_MEMBASE:
3936 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3938 case OP_AMD64_SUB_REG_MEMBASE:
3939 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3941 case OP_AMD64_AND_REG_MEMBASE:
3942 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3944 case OP_AMD64_OR_REG_MEMBASE:
3945 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3947 case OP_AMD64_XOR_REG_MEMBASE:
3948 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3951 case OP_AMD64_ADD_MEMBASE_REG:
3952 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3954 case OP_AMD64_SUB_MEMBASE_REG:
3955 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3957 case OP_AMD64_AND_MEMBASE_REG:
3958 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3960 case OP_AMD64_OR_MEMBASE_REG:
3961 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3963 case OP_AMD64_XOR_MEMBASE_REG:
3964 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3967 case OP_AMD64_ADD_MEMBASE_IMM:
3968 g_assert (amd64_is_imm32 (ins->inst_imm));
3969 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3971 case OP_AMD64_SUB_MEMBASE_IMM:
3972 g_assert (amd64_is_imm32 (ins->inst_imm));
3973 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3975 case OP_AMD64_AND_MEMBASE_IMM:
3976 g_assert (amd64_is_imm32 (ins->inst_imm));
3977 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3979 case OP_AMD64_OR_MEMBASE_IMM:
3980 g_assert (amd64_is_imm32 (ins->inst_imm));
3981 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3983 case OP_AMD64_XOR_MEMBASE_IMM:
3984 g_assert (amd64_is_imm32 (ins->inst_imm));
3985 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3989 amd64_breakpoint (code);
3991 case OP_RELAXED_NOP:
3992 x86_prefix (code, X86_REP_PREFIX);
4000 case OP_DUMMY_STORE:
4001 case OP_DUMMY_ICONST:
4002 case OP_DUMMY_R8CONST:
4003 case OP_NOT_REACHED:
4006 case OP_IL_SEQ_POINT:
4007 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4009 case OP_SEQ_POINT: {
4010 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4011 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4014 /* Load ss_tramp_var */
4015 /* This is equal to &ss_trampoline */
4016 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4017 /* Load the trampoline address */
4018 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4019 /* Call it if it is non-null */
4020 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4022 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4023 amd64_call_reg (code, AMD64_R11);
4024 amd64_patch (label, code);
4028 * This is the address which is saved in seq points,
4030 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4032 if (cfg->compile_aot) {
4033 guint32 offset = code - cfg->native_code;
4035 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4039 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4040 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4041 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4042 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4043 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4045 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4046 /* Call the trampoline */
4047 amd64_call_reg (code, AMD64_R11);
4048 amd64_patch (label, code);
4050 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4054 * Emit a test+branch against a constant, the constant will be overwritten
4055 * by mono_arch_set_breakpoint () to cause the test to fail.
4057 amd64_mov_reg_imm (code, AMD64_R11, 0);
4058 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4060 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4063 g_assert (var->opcode == OP_REGOFFSET);
4064 /* Load bp_tramp_var */
4065 /* This is equal to &bp_trampoline */
4066 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4067 /* Call the trampoline */
4068 amd64_call_membase (code, AMD64_R11, 0);
4069 amd64_patch (label, code);
4072 * Add an additional nop so skipping the bp doesn't cause the ip to point
4073 * to another IL offset.
4081 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4084 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4088 g_assert (amd64_is_imm32 (ins->inst_imm));
4089 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4092 g_assert (amd64_is_imm32 (ins->inst_imm));
4093 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4098 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4101 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4105 g_assert (amd64_is_imm32 (ins->inst_imm));
4106 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4109 g_assert (amd64_is_imm32 (ins->inst_imm));
4110 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4113 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4117 g_assert (amd64_is_imm32 (ins->inst_imm));
4118 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4121 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4126 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4128 switch (ins->inst_imm) {
4132 if (ins->dreg != ins->sreg1)
4133 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4134 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4137 /* LEA r1, [r2 + r2*2] */
4138 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4141 /* LEA r1, [r2 + r2*4] */
4142 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4145 /* LEA r1, [r2 + r2*2] */
4147 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4148 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4151 /* LEA r1, [r2 + r2*8] */
4152 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4155 /* LEA r1, [r2 + r2*4] */
4157 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4158 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4161 /* LEA r1, [r2 + r2*2] */
4163 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4164 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4167 /* LEA r1, [r2 + r2*4] */
4168 /* LEA r1, [r1 + r1*4] */
4169 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4170 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4173 /* LEA r1, [r2 + r2*4] */
4175 /* LEA r1, [r1 + r1*4] */
4176 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4177 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4178 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4181 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4188 /* Regalloc magic makes the div/rem cases the same */
4189 if (ins->sreg2 == AMD64_RDX) {
4190 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4192 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4195 amd64_div_reg (code, ins->sreg2, TRUE);
4200 if (ins->sreg2 == AMD64_RDX) {
4201 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4202 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4203 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4205 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4206 amd64_div_reg (code, ins->sreg2, FALSE);
4211 if (ins->sreg2 == AMD64_RDX) {
4212 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4213 amd64_cdq_size (code, 4);
4214 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4216 amd64_cdq_size (code, 4);
4217 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4222 if (ins->sreg2 == AMD64_RDX) {
4223 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4224 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4225 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4227 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4228 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4232 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4233 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4236 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4240 g_assert (amd64_is_imm32 (ins->inst_imm));
4241 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4244 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4248 g_assert (amd64_is_imm32 (ins->inst_imm));
4249 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4252 g_assert (ins->sreg2 == AMD64_RCX);
4253 amd64_shift_reg (code, X86_SHL, ins->dreg);
4256 g_assert (ins->sreg2 == AMD64_RCX);
4257 amd64_shift_reg (code, X86_SAR, ins->dreg);
4261 g_assert (amd64_is_imm32 (ins->inst_imm));
4262 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4265 g_assert (amd64_is_imm32 (ins->inst_imm));
4266 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4268 case OP_LSHR_UN_IMM:
4269 g_assert (amd64_is_imm32 (ins->inst_imm));
4270 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4273 g_assert (ins->sreg2 == AMD64_RCX);
4274 amd64_shift_reg (code, X86_SHR, ins->dreg);
4278 g_assert (amd64_is_imm32 (ins->inst_imm));
4279 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4284 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4287 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4290 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4293 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4297 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4300 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4303 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4306 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4309 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4312 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4315 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4318 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4321 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4324 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4327 amd64_neg_reg_size (code, ins->sreg1, 4);
4330 amd64_not_reg_size (code, ins->sreg1, 4);
4333 g_assert (ins->sreg2 == AMD64_RCX);
4334 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4337 g_assert (ins->sreg2 == AMD64_RCX);
4338 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4341 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4343 case OP_ISHR_UN_IMM:
4344 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4347 g_assert (ins->sreg2 == AMD64_RCX);
4348 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4351 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4354 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4357 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4358 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4360 case OP_IMUL_OVF_UN:
4361 case OP_LMUL_OVF_UN: {
4362 /* the mul operation and the exception check should most likely be split */
4363 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4364 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4365 /*g_assert (ins->sreg2 == X86_EAX);
4366 g_assert (ins->dreg == X86_EAX);*/
4367 if (ins->sreg2 == X86_EAX) {
4368 non_eax_reg = ins->sreg1;
4369 } else if (ins->sreg1 == X86_EAX) {
4370 non_eax_reg = ins->sreg2;
4372 /* no need to save since we're going to store to it anyway */
4373 if (ins->dreg != X86_EAX) {
4375 amd64_push_reg (code, X86_EAX);
4377 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4378 non_eax_reg = ins->sreg2;
4380 if (ins->dreg == X86_EDX) {
4383 amd64_push_reg (code, X86_EAX);
4387 amd64_push_reg (code, X86_EDX);
4389 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4390 /* save before the check since pop and mov don't change the flags */
4391 if (ins->dreg != X86_EAX)
4392 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4394 amd64_pop_reg (code, X86_EDX);
4396 amd64_pop_reg (code, X86_EAX);
4397 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4401 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4403 case OP_ICOMPARE_IMM:
4404 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4426 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4434 case OP_CMOV_INE_UN:
4435 case OP_CMOV_IGE_UN:
4436 case OP_CMOV_IGT_UN:
4437 case OP_CMOV_ILE_UN:
4438 case OP_CMOV_ILT_UN:
4444 case OP_CMOV_LNE_UN:
4445 case OP_CMOV_LGE_UN:
4446 case OP_CMOV_LGT_UN:
4447 case OP_CMOV_LLE_UN:
4448 case OP_CMOV_LLT_UN:
4449 g_assert (ins->dreg == ins->sreg1);
4450 /* This needs to operate on 64 bit values */
4451 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4455 amd64_not_reg (code, ins->sreg1);
4458 amd64_neg_reg (code, ins->sreg1);
4463 if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4464 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4466 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4469 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4470 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4473 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4474 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4477 if (ins->dreg != ins->sreg1)
4478 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4480 case OP_AMD64_SET_XMMREG_R4: {
4482 if (ins->dreg != ins->sreg1)
4483 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4485 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4489 case OP_AMD64_SET_XMMREG_R8: {
4490 if (ins->dreg != ins->sreg1)
4491 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4495 MonoCallInst *call = (MonoCallInst*)ins;
4496 int i, save_area_offset;
4498 g_assert (!cfg->method->save_lmf);
4500 /* Restore callee saved registers */
4501 save_area_offset = cfg->arch.reg_save_area_offset;
4502 for (i = 0; i < AMD64_NREG; ++i)
4503 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4504 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4505 save_area_offset += 8;
4508 if (cfg->arch.omit_fp) {
4509 if (cfg->arch.stack_alloc_size)
4510 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4512 if (call->stack_usage)
4515 /* Copy arguments on the stack to our argument area */
4516 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4517 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4518 amd64_mov_membase_reg (code, AMD64_RBP, ARGS_OFFSET + i, AMD64_RAX, sizeof(mgreg_t));
4522 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
4523 amd64_pop_reg (code, AMD64_RBP);
4524 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
4530 offset = code - cfg->native_code;
4531 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4532 if (cfg->compile_aot)
4533 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4535 amd64_set_reg_template (code, AMD64_R11);
4536 amd64_jump_reg (code, AMD64_R11);
4537 ins->flags |= MONO_INST_GC_CALLSITE;
4538 ins->backend.pc_offset = code - cfg->native_code;
4542 /* ensure ins->sreg1 is not NULL */
4543 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4546 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4547 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4557 call = (MonoCallInst*)ins;
4559 * The AMD64 ABI forces callers to know about varargs.
4561 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4562 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4563 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4565 * Since the unmanaged calling convention doesn't contain a
4566 * 'vararg' entry, we have to treat every pinvoke call as a
4567 * potential vararg call.
4571 for (i = 0; i < AMD64_XMM_NREG; ++i)
4572 if (call->used_fregs & (1 << i))
4575 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4577 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4580 if (ins->flags & MONO_INST_HAS_METHOD)
4581 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4583 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4584 ins->flags |= MONO_INST_GC_CALLSITE;
4585 ins->backend.pc_offset = code - cfg->native_code;
4586 code = emit_move_return_value (cfg, ins, code);
4593 case OP_VOIDCALL_REG:
4595 call = (MonoCallInst*)ins;
4597 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4598 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4599 ins->sreg1 = AMD64_R11;
4603 * The AMD64 ABI forces callers to know about varargs.
4605 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4606 if (ins->sreg1 == AMD64_RAX) {
4607 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4608 ins->sreg1 = AMD64_R11;
4610 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4611 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4613 * Since the unmanaged calling convention doesn't contain a
4614 * 'vararg' entry, we have to treat every pinvoke call as a
4615 * potential vararg call.
4619 for (i = 0; i < AMD64_XMM_NREG; ++i)
4620 if (call->used_fregs & (1 << i))
4622 if (ins->sreg1 == AMD64_RAX) {
4623 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4624 ins->sreg1 = AMD64_R11;
4627 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4629 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4632 amd64_call_reg (code, ins->sreg1);
4633 ins->flags |= MONO_INST_GC_CALLSITE;
4634 ins->backend.pc_offset = code - cfg->native_code;
4635 code = emit_move_return_value (cfg, ins, code);
4637 case OP_FCALL_MEMBASE:
4638 case OP_RCALL_MEMBASE:
4639 case OP_LCALL_MEMBASE:
4640 case OP_VCALL_MEMBASE:
4641 case OP_VCALL2_MEMBASE:
4642 case OP_VOIDCALL_MEMBASE:
4643 case OP_CALL_MEMBASE:
4644 call = (MonoCallInst*)ins;
4646 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4647 ins->flags |= MONO_INST_GC_CALLSITE;
4648 ins->backend.pc_offset = code - cfg->native_code;
4649 code = emit_move_return_value (cfg, ins, code);
4653 MonoInst *var = cfg->dyn_call_var;
4656 g_assert (var->opcode == OP_REGOFFSET);
4658 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4659 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4661 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4663 /* Save args buffer */
4664 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4666 /* Set fp arg regs */
4667 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4668 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4670 amd64_branch8 (code, X86_CC_Z, -1, 1);
4671 for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4672 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4673 amd64_patch (label, code);
4675 /* Set stack args */
4676 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4677 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4678 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4681 /* Set argument registers */
4682 for (i = 0; i < PARAM_REGS; ++i)
4683 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4686 amd64_call_reg (code, AMD64_R10);
4688 ins->flags |= MONO_INST_GC_CALLSITE;
4689 ins->backend.pc_offset = code - cfg->native_code;
4692 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4693 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4694 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4695 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4698 case OP_AMD64_SAVE_SP_TO_LMF: {
4699 MonoInst *lmf_var = cfg->lmf_var;
4700 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4704 g_assert_not_reached ();
4705 amd64_push_reg (code, ins->sreg1);
4707 case OP_X86_PUSH_IMM:
4708 g_assert_not_reached ();
4709 g_assert (amd64_is_imm32 (ins->inst_imm));
4710 amd64_push_imm (code, ins->inst_imm);
4712 case OP_X86_PUSH_MEMBASE:
4713 g_assert_not_reached ();
4714 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4716 case OP_X86_PUSH_OBJ: {
4717 int size = ALIGN_TO (ins->inst_imm, 8);
4719 g_assert_not_reached ();
4721 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4722 amd64_push_reg (code, AMD64_RDI);
4723 amd64_push_reg (code, AMD64_RSI);
4724 amd64_push_reg (code, AMD64_RCX);
4725 if (ins->inst_offset)
4726 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4728 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4729 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4730 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4732 amd64_prefix (code, X86_REP_PREFIX);
4734 amd64_pop_reg (code, AMD64_RCX);
4735 amd64_pop_reg (code, AMD64_RSI);
4736 amd64_pop_reg (code, AMD64_RDI);
4739 case OP_GENERIC_CLASS_INIT: {
4742 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4744 amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4746 amd64_branch8 (code, X86_CC_NZ, -1, 1);
4748 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4749 ins->flags |= MONO_INST_GC_CALLSITE;
4750 ins->backend.pc_offset = code - cfg->native_code;
4752 x86_patch (jump, code);
4757 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4759 case OP_X86_LEA_MEMBASE:
4760 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4763 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4766 /* keep alignment */
4767 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4768 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4769 code = mono_emit_stack_alloc (cfg, code, ins);
4770 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4771 if (cfg->param_area)
4772 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4774 case OP_LOCALLOC_IMM: {
4775 guint32 size = ins->inst_imm;
4776 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4778 if (ins->flags & MONO_INST_INIT) {
4782 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4783 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4785 for (i = 0; i < size; i += 8)
4786 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4787 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4789 amd64_mov_reg_imm (code, ins->dreg, size);
4790 ins->sreg1 = ins->dreg;
4792 code = mono_emit_stack_alloc (cfg, code, ins);
4793 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4796 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4797 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4799 if (cfg->param_area)
4800 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4804 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4805 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4806 (gpointer)"mono_arch_throw_exception", FALSE);
4807 ins->flags |= MONO_INST_GC_CALLSITE;
4808 ins->backend.pc_offset = code - cfg->native_code;
4812 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4813 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4814 (gpointer)"mono_arch_rethrow_exception", FALSE);
4815 ins->flags |= MONO_INST_GC_CALLSITE;
4816 ins->backend.pc_offset = code - cfg->native_code;
4819 case OP_CALL_HANDLER:
4821 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4822 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4823 amd64_call_imm (code, 0);
4824 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4825 /* Restore stack alignment */
4826 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4828 case OP_START_HANDLER: {
4829 /* Even though we're saving RSP, use sizeof */
4830 /* gpointer because spvar is of type IntPtr */
4831 /* see: mono_create_spvar_for_region */
4832 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4833 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4835 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4836 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4838 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4842 case OP_ENDFINALLY: {
4843 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4844 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4848 case OP_ENDFILTER: {
4849 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4850 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4851 /* The local allocator will put the result into RAX */
4856 if (ins->dreg != AMD64_RAX)
4857 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4860 ins->inst_c0 = code - cfg->native_code;
4863 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4864 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4866 if (ins->inst_target_bb->native_offset) {
4867 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4869 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4870 if ((cfg->opt & MONO_OPT_BRANCH) &&
4871 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4872 x86_jump8 (code, 0);
4874 x86_jump32 (code, 0);
4878 amd64_jump_reg (code, ins->sreg1);
4901 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4902 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4904 case OP_COND_EXC_EQ:
4905 case OP_COND_EXC_NE_UN:
4906 case OP_COND_EXC_LT:
4907 case OP_COND_EXC_LT_UN:
4908 case OP_COND_EXC_GT:
4909 case OP_COND_EXC_GT_UN:
4910 case OP_COND_EXC_GE:
4911 case OP_COND_EXC_GE_UN:
4912 case OP_COND_EXC_LE:
4913 case OP_COND_EXC_LE_UN:
4914 case OP_COND_EXC_IEQ:
4915 case OP_COND_EXC_INE_UN:
4916 case OP_COND_EXC_ILT:
4917 case OP_COND_EXC_ILT_UN:
4918 case OP_COND_EXC_IGT:
4919 case OP_COND_EXC_IGT_UN:
4920 case OP_COND_EXC_IGE:
4921 case OP_COND_EXC_IGE_UN:
4922 case OP_COND_EXC_ILE:
4923 case OP_COND_EXC_ILE_UN:
4924 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4926 case OP_COND_EXC_OV:
4927 case OP_COND_EXC_NO:
4929 case OP_COND_EXC_NC:
4930 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4931 (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4933 case OP_COND_EXC_IOV:
4934 case OP_COND_EXC_INO:
4935 case OP_COND_EXC_IC:
4936 case OP_COND_EXC_INC:
4937 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4938 (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4941 /* floating point opcodes */
4943 double d = *(double *)ins->inst_p0;
4945 if ((d == 0.0) && (mono_signbit (d) == 0)) {
4946 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4949 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4950 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4955 float f = *(float *)ins->inst_p0;
4957 if ((f == 0.0) && (mono_signbit (f) == 0)) {
4959 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4961 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4964 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4965 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4967 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4971 case OP_STORER8_MEMBASE_REG:
4972 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4974 case OP_LOADR8_MEMBASE:
4975 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4977 case OP_STORER4_MEMBASE_REG:
4979 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4981 /* This requires a double->single conversion */
4982 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
4983 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
4986 case OP_LOADR4_MEMBASE:
4988 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4990 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4991 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4994 case OP_ICONV_TO_R4:
4996 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4998 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4999 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5002 case OP_ICONV_TO_R8:
5003 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5005 case OP_LCONV_TO_R4:
5007 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5009 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5010 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5013 case OP_LCONV_TO_R8:
5014 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5016 case OP_FCONV_TO_R4:
5018 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5020 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5021 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5024 case OP_FCONV_TO_I1:
5025 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5027 case OP_FCONV_TO_U1:
5028 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5030 case OP_FCONV_TO_I2:
5031 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5033 case OP_FCONV_TO_U2:
5034 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5036 case OP_FCONV_TO_U4:
5037 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5039 case OP_FCONV_TO_I4:
5041 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5043 case OP_FCONV_TO_I8:
5044 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5047 case OP_RCONV_TO_I1:
5048 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5049 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5051 case OP_RCONV_TO_U1:
5052 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5053 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5055 case OP_RCONV_TO_I2:
5056 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5057 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5059 case OP_RCONV_TO_U2:
5060 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5061 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5063 case OP_RCONV_TO_I4:
5064 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5066 case OP_RCONV_TO_U4:
5067 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5069 case OP_RCONV_TO_I8:
5070 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5072 case OP_RCONV_TO_R8:
5073 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5075 case OP_RCONV_TO_R4:
5076 if (ins->dreg != ins->sreg1)
5077 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5080 case OP_LCONV_TO_R_UN: {
5083 /* Based on gcc code */
5084 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5085 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5088 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5089 br [1] = code; x86_jump8 (code, 0);
5090 amd64_patch (br [0], code);
5093 /* Save to the red zone */
5094 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5095 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5096 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5097 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5098 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5099 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5100 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5101 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5102 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5104 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5105 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5106 amd64_patch (br [1], code);
5109 case OP_LCONV_TO_OVF_U4:
5110 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5111 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5112 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5114 case OP_LCONV_TO_OVF_I4_UN:
5115 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5116 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5117 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5120 if (ins->dreg != ins->sreg1)
5121 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5124 if (ins->dreg != ins->sreg1)
5125 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5127 case OP_MOVE_F_TO_I4:
5129 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5131 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5132 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5135 case OP_MOVE_I4_TO_F:
5136 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5138 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5140 case OP_MOVE_F_TO_I8:
5141 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5143 case OP_MOVE_I8_TO_F:
5144 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5147 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5150 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5153 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5156 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5159 static double r8_0 = -0.0;
5161 g_assert (ins->sreg1 == ins->dreg);
5163 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5164 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5168 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5171 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5174 static guint64 d = 0x7fffffffffffffffUL;
5176 g_assert (ins->sreg1 == ins->dreg);
5178 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5179 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5183 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5187 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5190 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5193 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5196 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5199 static float r4_0 = -0.0;
5201 g_assert (ins->sreg1 == ins->dreg);
5203 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5204 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5205 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5210 g_assert (cfg->opt & MONO_OPT_CMOV);
5211 g_assert (ins->dreg == ins->sreg1);
5212 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5213 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5216 g_assert (cfg->opt & MONO_OPT_CMOV);
5217 g_assert (ins->dreg == ins->sreg1);
5218 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5219 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5222 g_assert (cfg->opt & MONO_OPT_CMOV);
5223 g_assert (ins->dreg == ins->sreg1);
5224 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5225 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5228 g_assert (cfg->opt & MONO_OPT_CMOV);
5229 g_assert (ins->dreg == ins->sreg1);
5230 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5231 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5234 g_assert (cfg->opt & MONO_OPT_CMOV);
5235 g_assert (ins->dreg == ins->sreg1);
5236 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5237 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5240 g_assert (cfg->opt & MONO_OPT_CMOV);
5241 g_assert (ins->dreg == ins->sreg1);
5242 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5243 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5246 g_assert (cfg->opt & MONO_OPT_CMOV);
5247 g_assert (ins->dreg == ins->sreg1);
5248 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5249 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5252 g_assert (cfg->opt & MONO_OPT_CMOV);
5253 g_assert (ins->dreg == ins->sreg1);
5254 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5255 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5261 * The two arguments are swapped because the fbranch instructions
5262 * depend on this for the non-sse case to work.
5264 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5268 * FIXME: Get rid of this.
5269 * The two arguments are swapped because the fbranch instructions
5270 * depend on this for the non-sse case to work.
5272 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5276 /* zeroing the register at the start results in
5277 * shorter and faster code (we can also remove the widening op)
5279 guchar *unordered_check;
5281 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5282 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5283 unordered_check = code;
5284 x86_branch8 (code, X86_CC_P, 0, FALSE);
5286 if (ins->opcode == OP_FCEQ) {
5287 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5288 amd64_patch (unordered_check, code);
5290 guchar *jump_to_end;
5291 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5293 x86_jump8 (code, 0);
5294 amd64_patch (unordered_check, code);
5295 amd64_inc_reg (code, ins->dreg);
5296 amd64_patch (jump_to_end, code);
5302 /* zeroing the register at the start results in
5303 * shorter and faster code (we can also remove the widening op)
5305 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5306 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5307 if (ins->opcode == OP_FCLT_UN) {
5308 guchar *unordered_check = code;
5309 guchar *jump_to_end;
5310 x86_branch8 (code, X86_CC_P, 0, FALSE);
5311 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5313 x86_jump8 (code, 0);
5314 amd64_patch (unordered_check, code);
5315 amd64_inc_reg (code, ins->dreg);
5316 amd64_patch (jump_to_end, code);
5318 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5323 guchar *unordered_check;
5324 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5325 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5326 unordered_check = code;
5327 x86_branch8 (code, X86_CC_P, 0, FALSE);
5328 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5329 amd64_patch (unordered_check, code);
5334 /* zeroing the register at the start results in
5335 * shorter and faster code (we can also remove the widening op)
5337 guchar *unordered_check;
5339 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5340 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5341 if (ins->opcode == OP_FCGT) {
5342 unordered_check = code;
5343 x86_branch8 (code, X86_CC_P, 0, FALSE);
5344 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5345 amd64_patch (unordered_check, code);
5347 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5352 guchar *unordered_check;
5353 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5354 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5355 unordered_check = code;
5356 x86_branch8 (code, X86_CC_P, 0, FALSE);
5357 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5358 amd64_patch (unordered_check, code);
5368 gboolean unordered = FALSE;
5370 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5371 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5373 switch (ins->opcode) {
5375 x86_cond = X86_CC_EQ;
5378 x86_cond = X86_CC_LT;
5381 x86_cond = X86_CC_GT;
5384 x86_cond = X86_CC_GT;
5388 x86_cond = X86_CC_LT;
5392 g_assert_not_reached ();
5397 guchar *unordered_check;
5398 guchar *jump_to_end;
5400 unordered_check = code;
5401 x86_branch8 (code, X86_CC_P, 0, FALSE);
5402 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5404 x86_jump8 (code, 0);
5405 amd64_patch (unordered_check, code);
5406 amd64_inc_reg (code, ins->dreg);
5407 amd64_patch (jump_to_end, code);
5409 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5413 case OP_FCLT_MEMBASE:
5414 case OP_FCGT_MEMBASE:
5415 case OP_FCLT_UN_MEMBASE:
5416 case OP_FCGT_UN_MEMBASE:
5417 case OP_FCEQ_MEMBASE: {
5418 guchar *unordered_check, *jump_to_end;
5421 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5422 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5424 switch (ins->opcode) {
5425 case OP_FCEQ_MEMBASE:
5426 x86_cond = X86_CC_EQ;
5428 case OP_FCLT_MEMBASE:
5429 case OP_FCLT_UN_MEMBASE:
5430 x86_cond = X86_CC_LT;
5432 case OP_FCGT_MEMBASE:
5433 case OP_FCGT_UN_MEMBASE:
5434 x86_cond = X86_CC_GT;
5437 g_assert_not_reached ();
5440 unordered_check = code;
5441 x86_branch8 (code, X86_CC_P, 0, FALSE);
5442 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5444 switch (ins->opcode) {
5445 case OP_FCEQ_MEMBASE:
5446 case OP_FCLT_MEMBASE:
5447 case OP_FCGT_MEMBASE:
5448 amd64_patch (unordered_check, code);
5450 case OP_FCLT_UN_MEMBASE:
5451 case OP_FCGT_UN_MEMBASE:
5453 x86_jump8 (code, 0);
5454 amd64_patch (unordered_check, code);
5455 amd64_inc_reg (code, ins->dreg);
5456 amd64_patch (jump_to_end, code);
5464 guchar *jump = code;
5465 x86_branch8 (code, X86_CC_P, 0, TRUE);
5466 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5467 amd64_patch (jump, code);
5471 /* Branch if C013 != 100 */
5472 /* branch if !ZF or (PF|CF) */
5473 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5474 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5475 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5478 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5481 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5482 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5486 if (ins->opcode == OP_FBGT) {
5489 /* skip branch if C1=1 */
5491 x86_branch8 (code, X86_CC_P, 0, FALSE);
5492 /* branch if (C0 | C3) = 1 */
5493 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5494 amd64_patch (br1, code);
5497 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5501 /* Branch if C013 == 100 or 001 */
5504 /* skip branch if C1=1 */
5506 x86_branch8 (code, X86_CC_P, 0, FALSE);
5507 /* branch if (C0 | C3) = 1 */
5508 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5509 amd64_patch (br1, code);
5513 /* Branch if C013 == 000 */
5514 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5517 /* Branch if C013=000 or 100 */
5520 /* skip branch if C1=1 */
5522 x86_branch8 (code, X86_CC_P, 0, FALSE);
5523 /* branch if C0=0 */
5524 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5525 amd64_patch (br1, code);
5529 /* Branch if C013 != 001 */
5530 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5531 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5534 /* Transfer value to the fp stack */
5535 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5536 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5537 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5539 amd64_push_reg (code, AMD64_RAX);
5541 amd64_fnstsw (code);
5542 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5543 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5544 amd64_pop_reg (code, AMD64_RAX);
5545 amd64_fstp (code, 0);
5546 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5547 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5550 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5554 code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5557 case OP_MEMORY_BARRIER: {
5558 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5562 case OP_ATOMIC_ADD_I4:
5563 case OP_ATOMIC_ADD_I8: {
5564 int dreg = ins->dreg;
5565 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5567 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5570 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5571 amd64_prefix (code, X86_LOCK_PREFIX);
5572 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5573 /* dreg contains the old value, add with sreg2 value */
5574 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5576 if (ins->dreg != dreg)
5577 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5581 case OP_ATOMIC_EXCHANGE_I4:
5582 case OP_ATOMIC_EXCHANGE_I8: {
5583 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5585 /* LOCK prefix is implied. */
5586 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5587 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5588 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5591 case OP_ATOMIC_CAS_I4:
5592 case OP_ATOMIC_CAS_I8: {
5595 if (ins->opcode == OP_ATOMIC_CAS_I8)
5601 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5602 * an explanation of how this works.
5604 g_assert (ins->sreg3 == AMD64_RAX);
5605 g_assert (ins->sreg1 != AMD64_RAX);
5606 g_assert (ins->sreg1 != ins->sreg2);
5608 amd64_prefix (code, X86_LOCK_PREFIX);
5609 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5611 if (ins->dreg != AMD64_RAX)
5612 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5615 case OP_ATOMIC_LOAD_I1: {
5616 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5619 case OP_ATOMIC_LOAD_U1: {
5620 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5623 case OP_ATOMIC_LOAD_I2: {
5624 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5627 case OP_ATOMIC_LOAD_U2: {
5628 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5631 case OP_ATOMIC_LOAD_I4: {
5632 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5635 case OP_ATOMIC_LOAD_U4:
5636 case OP_ATOMIC_LOAD_I8:
5637 case OP_ATOMIC_LOAD_U8: {
5638 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5641 case OP_ATOMIC_LOAD_R4: {
5642 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5643 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5646 case OP_ATOMIC_LOAD_R8: {
5647 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5650 case OP_ATOMIC_STORE_I1:
5651 case OP_ATOMIC_STORE_U1:
5652 case OP_ATOMIC_STORE_I2:
5653 case OP_ATOMIC_STORE_U2:
5654 case OP_ATOMIC_STORE_I4:
5655 case OP_ATOMIC_STORE_U4:
5656 case OP_ATOMIC_STORE_I8:
5657 case OP_ATOMIC_STORE_U8: {
5660 switch (ins->opcode) {
5661 case OP_ATOMIC_STORE_I1:
5662 case OP_ATOMIC_STORE_U1:
5665 case OP_ATOMIC_STORE_I2:
5666 case OP_ATOMIC_STORE_U2:
5669 case OP_ATOMIC_STORE_I4:
5670 case OP_ATOMIC_STORE_U4:
5673 case OP_ATOMIC_STORE_I8:
5674 case OP_ATOMIC_STORE_U8:
5679 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5681 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5685 case OP_ATOMIC_STORE_R4: {
5686 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5687 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5689 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5693 case OP_ATOMIC_STORE_R8: {
5696 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5700 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5704 case OP_CARD_TABLE_WBARRIER: {
5705 int ptr = ins->sreg1;
5706 int value = ins->sreg2;
5708 int nursery_shift, card_table_shift;
5709 gpointer card_table_mask;
5710 size_t nursery_size;
5712 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5713 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5714 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5716 /*If either point to the stack we can simply avoid the WB. This happens due to
5717 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5719 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5723 * We need one register we can clobber, we choose EDX and make sreg1
5724 * fixed EAX to work around limitations in the local register allocator.
5725 * sreg2 might get allocated to EDX, but that is not a problem since
5726 * we use it before clobbering EDX.
5728 g_assert (ins->sreg1 == AMD64_RAX);
5731 * This is the code we produce:
5734 * edx >>= nursery_shift
5735 * cmp edx, (nursery_start >> nursery_shift)
5738 * edx >>= card_table_shift
5744 if (mono_gc_card_table_nursery_check ()) {
5745 if (value != AMD64_RDX)
5746 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5747 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5748 if (shifted_nursery_start >> 31) {
5750 * The value we need to compare against is 64 bits, so we need
5751 * another spare register. We use RBX, which we save and
5754 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5755 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5756 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5757 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5759 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5761 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5763 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5764 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5765 if (card_table_mask)
5766 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5768 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5769 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5771 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5773 if (mono_gc_card_table_nursery_check ())
5774 x86_patch (br, code);
5777 #ifdef MONO_ARCH_SIMD_INTRINSICS
5778 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5780 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5783 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5786 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5789 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5792 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5795 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5798 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5799 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5802 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5805 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5808 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5811 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5814 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5817 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5820 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5823 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5826 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5829 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5832 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5835 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5838 case OP_PSHUFLEW_HIGH:
5839 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5840 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5842 case OP_PSHUFLEW_LOW:
5843 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5844 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5847 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5848 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5851 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5852 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5855 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5856 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5860 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5863 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5866 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5869 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5872 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5875 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5878 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5879 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5882 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5885 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5888 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5891 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5894 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5897 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5900 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5903 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5906 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5909 case OP_EXTRACT_MASK:
5910 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5914 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5917 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5920 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5924 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5927 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5930 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5933 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5937 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5940 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5943 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5946 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5950 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5953 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5956 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5960 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5963 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5966 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5970 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5973 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5977 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5980 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5983 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5987 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5990 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5993 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5997 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6000 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6003 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6006 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6010 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6013 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6016 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6019 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6022 case OP_PSUM_ABS_DIFF:
6023 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6026 case OP_UNPACK_LOWB:
6027 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6029 case OP_UNPACK_LOWW:
6030 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6032 case OP_UNPACK_LOWD:
6033 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6035 case OP_UNPACK_LOWQ:
6036 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6038 case OP_UNPACK_LOWPS:
6039 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6041 case OP_UNPACK_LOWPD:
6042 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6045 case OP_UNPACK_HIGHB:
6046 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6048 case OP_UNPACK_HIGHW:
6049 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6051 case OP_UNPACK_HIGHD:
6052 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6054 case OP_UNPACK_HIGHQ:
6055 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6057 case OP_UNPACK_HIGHPS:
6058 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6060 case OP_UNPACK_HIGHPD:
6061 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6065 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6068 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6071 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6074 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6077 case OP_PADDB_SAT_UN:
6078 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6080 case OP_PSUBB_SAT_UN:
6081 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6083 case OP_PADDW_SAT_UN:
6084 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6086 case OP_PSUBW_SAT_UN:
6087 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6091 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6094 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6097 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6100 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6104 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6107 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6110 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6112 case OP_PMULW_HIGH_UN:
6113 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6116 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6120 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6123 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6127 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6130 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6134 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6137 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6141 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6144 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6148 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6151 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6155 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6158 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6162 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6165 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6168 /*TODO: This is appart of the sse spec but not added
6170 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6173 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6178 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6181 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6184 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6187 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6190 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6193 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6196 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6199 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6202 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6205 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6209 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6212 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6216 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6217 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6219 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6224 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6226 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6227 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6231 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6233 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6234 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6235 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6239 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6241 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6244 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6246 case OP_EXTRACTX_U2:
6247 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6249 case OP_INSERTX_U1_SLOW:
6250 /*sreg1 is the extracted ireg (scratch)
6251 /sreg2 is the to be inserted ireg (scratch)
6252 /dreg is the xreg to receive the value*/
6254 /*clear the bits from the extracted word*/
6255 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6256 /*shift the value to insert if needed*/
6257 if (ins->inst_c0 & 1)
6258 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6259 /*join them together*/
6260 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6261 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6263 case OP_INSERTX_I4_SLOW:
6264 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6265 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6266 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6268 case OP_INSERTX_I8_SLOW:
6269 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6271 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6273 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6276 case OP_INSERTX_R4_SLOW:
6277 switch (ins->inst_c0) {
6280 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6282 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6285 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6287 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6289 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6290 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6293 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6295 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6297 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6298 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6301 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6303 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6305 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6306 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6310 case OP_INSERTX_R8_SLOW:
6312 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6314 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6316 case OP_STOREX_MEMBASE_REG:
6317 case OP_STOREX_MEMBASE:
6318 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6320 case OP_LOADX_MEMBASE:
6321 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6323 case OP_LOADX_ALIGNED_MEMBASE:
6324 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6326 case OP_STOREX_ALIGNED_MEMBASE_REG:
6327 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6329 case OP_STOREX_NTA_MEMBASE_REG:
6330 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6332 case OP_PREFETCH_MEMBASE:
6333 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6337 /*FIXME the peephole pass should have killed this*/
6338 if (ins->dreg != ins->sreg1)
6339 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6342 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6345 amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6347 case OP_ICONV_TO_R4_RAW:
6348 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6350 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6353 case OP_FCONV_TO_R8_X:
6354 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6357 case OP_XCONV_R8_TO_I4:
6358 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6359 switch (ins->backend.source_opcode) {
6360 case OP_FCONV_TO_I1:
6361 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6363 case OP_FCONV_TO_U1:
6364 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6366 case OP_FCONV_TO_I2:
6367 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6369 case OP_FCONV_TO_U2:
6370 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6376 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6377 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6378 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6381 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6382 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6385 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6386 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6390 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6392 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6393 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6395 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6398 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6399 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6402 case OP_LIVERANGE_START: {
6403 if (cfg->verbose_level > 1)
6404 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6405 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6408 case OP_LIVERANGE_END: {
6409 if (cfg->verbose_level > 1)
6410 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6411 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6414 case OP_GC_SAFE_POINT: {
6417 g_assert (mono_threads_is_coop_enabled ());
6419 amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6420 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6421 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6422 amd64_patch (br[0], code);
6426 case OP_GC_LIVENESS_DEF:
6427 case OP_GC_LIVENESS_USE:
6428 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6429 ins->backend.pc_offset = code - cfg->native_code;
6431 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6432 ins->backend.pc_offset = code - cfg->native_code;
6433 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6435 case OP_GET_LAST_ERROR:
6436 emit_get_last_error(code, ins->dreg);
6439 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6440 g_assert_not_reached ();
6443 if ((code - cfg->native_code - offset) > max_len) {
6444 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6445 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6446 g_assert_not_reached ();
6450 cfg->code_len = code - cfg->native_code;
6453 #endif /* DISABLE_JIT */
6456 mono_arch_register_lowlevel_calls (void)
6458 /* The signature doesn't matter */
6459 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6461 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6463 extern void __chkstk (void);
6464 mono_register_jit_icall_full (__chkstk, "mono_chkstk_win64", NULL, TRUE, FALSE, "__chkstk");
6466 extern void ___chkstk_ms (void);
6467 mono_register_jit_icall_full (___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, FALSE, "___chkstk_ms");
6473 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6475 unsigned char *ip = ji->ip.i + code;
6478 * Debug code to help track down problems where the target of a near call is
6481 if (amd64_is_near_call (ip)) {
6482 gint64 disp = (guint8*)target - (guint8*)ip;
6484 if (!amd64_is_imm32 (disp)) {
6485 printf ("TYPE: %d\n", ji->type);
6487 case MONO_PATCH_INFO_INTERNAL_METHOD:
6488 printf ("V: %s\n", ji->data.name);
6490 case MONO_PATCH_INFO_METHOD_JUMP:
6491 case MONO_PATCH_INFO_METHOD:
6492 printf ("V: %s\n", ji->data.method->name);
6500 amd64_patch (ip, (gpointer)target);
6506 get_max_epilog_size (MonoCompile *cfg)
6508 int max_epilog_size = 16;
6510 if (cfg->method->save_lmf)
6511 max_epilog_size += 256;
6513 if (mono_jit_trace_calls != NULL)
6514 max_epilog_size += 50;
6516 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6517 max_epilog_size += 50;
6519 max_epilog_size += (AMD64_NREG * 2);
6521 return max_epilog_size;
6525 * This macro is used for testing whenever the unwinder works correctly at every point
6526 * where an async exception can happen.
6528 /* This will generate a SIGSEGV at the given point in the code */
6529 #define async_exc_point(code) do { \
6530 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6531 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6532 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6533 cfg->arch.async_point_count ++; \
6539 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6541 int cfa_offset = *cfa_offset_input;
6543 /* Allocate windows stack frame using stack probing method */
6546 if (alloc_size >= 0x1000) {
6547 amd64_mov_reg_imm (code, AMD64_RAX, alloc_size);
6548 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_chkstk_win64");
6551 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6552 if (cfg->arch.omit_fp) {
6553 cfa_offset += alloc_size;
6554 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6555 async_exc_point (code);
6558 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6559 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6560 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6561 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6562 // that will retrieve the expected results.
6563 if (cfg->arch.omit_fp)
6564 mono_emit_unwind_op_sp_alloc (cfg, code, alloc_size);
6567 *cfa_offset_input = cfa_offset;
6570 #endif /* TARGET_WIN32 */
6573 mono_arch_emit_prolog (MonoCompile *cfg)
6575 MonoMethod *method = cfg->method;
6577 MonoMethodSignature *sig;
6579 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6582 MonoInst *lmf_var = cfg->lmf_var;
6583 gboolean args_clobbered = FALSE;
6584 gboolean trace = FALSE;
6586 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6588 code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6590 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6593 /* Amount of stack space allocated by register saving code */
6596 /* Offset between RSP and the CFA */
6600 * The prolog consists of the following parts:
6604 * - save callee saved regs using moves
6606 * - save rgctx if needed
6607 * - save lmf if needed
6610 * - save rgctx if needed
6611 * - save lmf if needed
6612 * - save callee saved regs using moves
6617 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6618 // IP saved at CFA - 8
6619 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6620 async_exc_point (code);
6621 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6623 if (!cfg->arch.omit_fp) {
6624 amd64_push_reg (code, AMD64_RBP);
6626 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6627 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6628 async_exc_point (code);
6629 /* These are handled automatically by the stack marking code */
6630 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6632 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6633 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6634 mono_emit_unwind_op_fp_alloc (cfg, code, AMD64_RBP, 0);
6635 async_exc_point (code);
6638 /* The param area is always at offset 0 from sp */
6639 /* This needs to be allocated here, since it has to come after the spill area */
6640 if (cfg->param_area) {
6641 if (cfg->arch.omit_fp)
6643 g_assert_not_reached ();
6644 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6647 if (cfg->arch.omit_fp) {
6649 * On enter, the stack is misaligned by the pushing of the return
6650 * address. It is either made aligned by the pushing of %rbp, or by
6653 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6654 if ((alloc_size % 16) == 0) {
6656 /* Mark the padding slot as NOREF */
6657 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6660 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6661 if (cfg->stack_offset != alloc_size) {
6662 /* Mark the padding slot as NOREF */
6663 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6665 cfg->arch.sp_fp_offset = alloc_size;
6669 cfg->arch.stack_alloc_size = alloc_size;
6671 /* Allocate stack frame */
6673 code = emit_prolog_setup_sp_win64 (cfg, code, alloc_size, &cfa_offset);
6676 /* See mono_emit_stack_alloc */
6677 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6678 guint32 remaining_size = alloc_size;
6679 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6680 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6681 guint32 offset = code - cfg->native_code;
6682 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6683 while (required_code_size >= (cfg->code_size - offset))
6684 cfg->code_size *= 2;
6685 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6686 code = cfg->native_code + offset;
6687 cfg->stat_code_reallocs++;
6690 while (remaining_size >= 0x1000) {
6691 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6692 if (cfg->arch.omit_fp) {
6693 cfa_offset += 0x1000;
6694 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6696 async_exc_point (code);
6698 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6699 remaining_size -= 0x1000;
6701 if (remaining_size) {
6702 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6703 if (cfg->arch.omit_fp) {
6704 cfa_offset += remaining_size;
6705 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6706 async_exc_point (code);
6710 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6711 if (cfg->arch.omit_fp) {
6712 cfa_offset += alloc_size;
6713 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6714 async_exc_point (code);
6720 /* Stack alignment check */
6725 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6726 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6727 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6729 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6730 amd64_breakpoint (code);
6731 amd64_patch (buf, code);
6735 if (mini_get_debug_options ()->init_stacks) {
6736 /* Fill the stack frame with a dummy value to force deterministic behavior */
6738 /* Save registers to the red zone */
6739 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6740 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6742 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6743 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6744 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6747 amd64_prefix (code, X86_REP_PREFIX);
6750 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6751 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6755 if (method->save_lmf)
6756 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6758 /* Save callee saved registers */
6759 if (cfg->arch.omit_fp) {
6760 save_area_offset = cfg->arch.reg_save_area_offset;
6761 /* Save caller saved registers after sp is adjusted */
6762 /* The registers are saved at the bottom of the frame */
6763 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6765 /* The registers are saved just below the saved rbp */
6766 save_area_offset = cfg->arch.reg_save_area_offset;
6769 for (i = 0; i < AMD64_NREG; ++i) {
6770 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6771 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6773 if (cfg->arch.omit_fp) {
6774 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6775 /* These are handled automatically by the stack marking code */
6776 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6778 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6782 save_area_offset += 8;
6783 async_exc_point (code);
6787 /* store runtime generic context */
6788 if (cfg->rgctx_var) {
6789 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6790 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6792 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6794 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6795 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6798 /* compute max_length in order to use short forward jumps */
6799 max_epilog_size = get_max_epilog_size (cfg);
6800 if (cfg->opt & MONO_OPT_BRANCH) {
6801 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6805 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6807 /* max alignment for loops */
6808 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6809 max_length += LOOP_ALIGNMENT;
6811 MONO_BB_FOR_EACH_INS (bb, ins) {
6812 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6815 /* Take prolog and epilog instrumentation into account */
6816 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6817 max_length += max_epilog_size;
6819 bb->max_length = max_length;
6823 sig = mono_method_signature (method);
6826 cinfo = (CallInfo *)cfg->arch.cinfo;
6828 if (sig->ret->type != MONO_TYPE_VOID) {
6829 /* Save volatile arguments to the stack */
6830 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6831 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6834 /* Keep this in sync with emit_load_volatile_arguments */
6835 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6836 ArgInfo *ainfo = cinfo->args + i;
6838 ins = cfg->args [i];
6840 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6841 /* Unused arguments */
6844 /* Save volatile arguments to the stack */
6845 if (ins->opcode != OP_REGVAR) {
6846 switch (ainfo->storage) {
6852 if (stack_offset & 0x1)
6854 else if (stack_offset & 0x2)
6856 else if (stack_offset & 0x4)
6861 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6864 * Save the original location of 'this',
6865 * get_generic_info_from_stack_frame () needs this to properly look up
6866 * the argument value during the handling of async exceptions.
6868 if (ins == cfg->args [0]) {
6869 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6870 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6874 case ArgInFloatSSEReg:
6875 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6877 case ArgInDoubleSSEReg:
6878 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6880 case ArgValuetypeInReg:
6881 for (quad = 0; quad < 2; quad ++) {
6882 switch (ainfo->pair_storage [quad]) {
6884 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6886 case ArgInFloatSSEReg:
6887 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6889 case ArgInDoubleSSEReg:
6890 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6895 g_assert_not_reached ();
6899 case ArgValuetypeAddrInIReg:
6900 if (ainfo->pair_storage [0] == ArgInIReg)
6901 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6903 case ArgValuetypeAddrOnStack:
6905 case ArgGSharedVtInReg:
6906 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6912 /* Argument allocated to (non-volatile) register */
6913 switch (ainfo->storage) {
6915 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6918 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6921 g_assert_not_reached ();
6924 if (ins == cfg->args [0]) {
6925 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6926 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6931 if (cfg->method->save_lmf)
6932 args_clobbered = TRUE;
6935 args_clobbered = TRUE;
6936 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6939 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6940 args_clobbered = TRUE;
6943 * Optimize the common case of the first bblock making a call with the same
6944 * arguments as the method. This works because the arguments are still in their
6945 * original argument registers.
6946 * FIXME: Generalize this
6948 if (!args_clobbered) {
6949 MonoBasicBlock *first_bb = cfg->bb_entry;
6951 int filter = FILTER_IL_SEQ_POINT;
6953 next = mono_bb_first_inst (first_bb, filter);
6954 if (!next && first_bb->next_bb) {
6955 first_bb = first_bb->next_bb;
6956 next = mono_bb_first_inst (first_bb, filter);
6959 if (first_bb->in_count > 1)
6962 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6963 ArgInfo *ainfo = cinfo->args + i;
6964 gboolean match = FALSE;
6966 ins = cfg->args [i];
6967 if (ins->opcode != OP_REGVAR) {
6968 switch (ainfo->storage) {
6970 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6971 if (next->dreg == ainfo->reg) {
6975 next->opcode = OP_MOVE;
6976 next->sreg1 = ainfo->reg;
6977 /* Only continue if the instruction doesn't change argument regs */
6978 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6988 /* Argument allocated to (non-volatile) register */
6989 switch (ainfo->storage) {
6991 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7002 next = mono_inst_next (next, filter);
7003 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7010 if (cfg->gen_sdb_seq_points) {
7011 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7013 /* Initialize seq_point_info_var */
7014 if (cfg->compile_aot) {
7015 /* Initialize the variable from a GOT slot */
7016 /* Same as OP_AOTCONST */
7017 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7018 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7019 g_assert (info_var->opcode == OP_REGOFFSET);
7020 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7023 if (cfg->compile_aot) {
7024 /* Initialize ss_tramp_var */
7025 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7026 g_assert (ins->opcode == OP_REGOFFSET);
7028 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7029 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7030 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7032 /* Initialize ss_tramp_var */
7033 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7034 g_assert (ins->opcode == OP_REGOFFSET);
7036 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7037 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7039 /* Initialize bp_tramp_var */
7040 ins = (MonoInst *)cfg->arch.bp_tramp_var;
7041 g_assert (ins->opcode == OP_REGOFFSET);
7043 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7044 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7048 cfg->code_len = code - cfg->native_code;
7050 g_assert (cfg->code_len < cfg->code_size);
7056 mono_arch_emit_epilog (MonoCompile *cfg)
7058 MonoMethod *method = cfg->method;
7061 int max_epilog_size;
7063 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7064 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7066 max_epilog_size = get_max_epilog_size (cfg);
7068 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7069 cfg->code_size *= 2;
7070 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7071 cfg->stat_code_reallocs++;
7073 code = cfg->native_code + cfg->code_len;
7075 cfg->has_unwind_info_for_epilog = TRUE;
7077 /* Mark the start of the epilog */
7078 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7080 /* Save the uwind state which is needed by the out-of-line code */
7081 mono_emit_unwind_op_remember_state (cfg, code);
7083 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7084 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7086 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7088 if (method->save_lmf) {
7089 /* check if we need to restore protection of the stack after a stack overflow */
7090 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7092 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7093 /* we load the value in a separate instruction: this mechanism may be
7094 * used later as a safer way to do thread interruption
7096 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7097 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7099 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7100 /* note that the call trampoline will preserve eax/edx */
7101 x86_call_reg (code, X86_ECX);
7102 x86_patch (patch, code);
7104 /* FIXME: maybe save the jit tls in the prolog */
7106 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7107 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7111 /* Restore callee saved regs */
7112 for (i = 0; i < AMD64_NREG; ++i) {
7113 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7114 /* Restore only used_int_regs, not arch.saved_iregs */
7115 #if defined(MONO_SUPPORT_TASKLETS)
7118 int restore_reg=(cfg->used_int_regs & (1 << i));
7121 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7122 mono_emit_unwind_op_same_value (cfg, code, i);
7123 async_exc_point (code);
7125 save_area_offset += 8;
7129 /* Load returned vtypes into registers if needed */
7130 cinfo = (CallInfo *)cfg->arch.cinfo;
7131 if (cinfo->ret.storage == ArgValuetypeInReg) {
7132 ArgInfo *ainfo = &cinfo->ret;
7133 MonoInst *inst = cfg->ret;
7135 for (quad = 0; quad < 2; quad ++) {
7136 switch (ainfo->pair_storage [quad]) {
7138 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7140 case ArgInFloatSSEReg:
7141 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7143 case ArgInDoubleSSEReg:
7144 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7149 g_assert_not_reached ();
7154 if (cfg->arch.omit_fp) {
7155 if (cfg->arch.stack_alloc_size) {
7156 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7160 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
7161 amd64_pop_reg (code, AMD64_RBP);
7162 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7165 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7168 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7169 async_exc_point (code);
7172 /* Restore the unwind state to be the same as before the epilog */
7173 mono_emit_unwind_op_restore_state (cfg, code);
7175 cfg->code_len = code - cfg->native_code;
7177 g_assert (cfg->code_len < cfg->code_size);
7181 mono_arch_emit_exceptions (MonoCompile *cfg)
7183 MonoJumpInfo *patch_info;
7186 MonoClass *exc_classes [16];
7187 guint8 *exc_throw_start [16], *exc_throw_end [16];
7188 guint32 code_size = 0;
7190 /* Compute needed space */
7191 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7192 if (patch_info->type == MONO_PATCH_INFO_EXC)
7194 if (patch_info->type == MONO_PATCH_INFO_R8)
7195 code_size += 8 + 15; /* sizeof (double) + alignment */
7196 if (patch_info->type == MONO_PATCH_INFO_R4)
7197 code_size += 4 + 15; /* sizeof (float) + alignment */
7198 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7199 code_size += 8 + 7; /*sizeof (void*) + alignment */
7202 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7203 cfg->code_size *= 2;
7204 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7205 cfg->stat_code_reallocs++;
7208 code = cfg->native_code + cfg->code_len;
7210 /* add code to raise exceptions */
7212 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7213 switch (patch_info->type) {
7214 case MONO_PATCH_INFO_EXC: {
7215 MonoClass *exc_class;
7219 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7221 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7222 throw_ip = patch_info->ip.i;
7224 //x86_breakpoint (code);
7225 /* Find a throw sequence for the same exception class */
7226 for (i = 0; i < nthrows; ++i)
7227 if (exc_classes [i] == exc_class)
7230 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7231 x86_jump_code (code, exc_throw_start [i]);
7232 patch_info->type = MONO_PATCH_INFO_NONE;
7236 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7240 exc_classes [nthrows] = exc_class;
7241 exc_throw_start [nthrows] = code;
7243 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7245 patch_info->type = MONO_PATCH_INFO_NONE;
7247 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7249 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7254 exc_throw_end [nthrows] = code;
7264 g_assert(code < cfg->native_code + cfg->code_size);
7267 /* Handle relocations with RIP relative addressing */
7268 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7269 gboolean remove = FALSE;
7270 guint8 *orig_code = code;
7272 switch (patch_info->type) {
7273 case MONO_PATCH_INFO_R8:
7274 case MONO_PATCH_INFO_R4: {
7275 guint8 *pos, *patch_pos;
7278 /* The SSE opcodes require a 16 byte alignment */
7279 code = (guint8*)ALIGN_TO (code, 16);
7281 pos = cfg->native_code + patch_info->ip.i;
7282 if (IS_REX (pos [1])) {
7283 patch_pos = pos + 5;
7284 target_pos = code - pos - 9;
7287 patch_pos = pos + 4;
7288 target_pos = code - pos - 8;
7291 if (patch_info->type == MONO_PATCH_INFO_R8) {
7292 *(double*)code = *(double*)patch_info->data.target;
7293 code += sizeof (double);
7295 *(float*)code = *(float*)patch_info->data.target;
7296 code += sizeof (float);
7299 *(guint32*)(patch_pos) = target_pos;
7304 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7307 if (cfg->compile_aot)
7310 /*loading is faster against aligned addresses.*/
7311 code = (guint8*)ALIGN_TO (code, 8);
7312 memset (orig_code, 0, code - orig_code);
7314 pos = cfg->native_code + patch_info->ip.i;
7316 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7317 if (IS_REX (pos [1]))
7318 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7320 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7322 *(gpointer*)code = (gpointer)patch_info->data.target;
7323 code += sizeof (gpointer);
7333 if (patch_info == cfg->patch_info)
7334 cfg->patch_info = patch_info->next;
7338 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7340 tmp->next = patch_info->next;
7343 g_assert (code < cfg->native_code + cfg->code_size);
7346 cfg->code_len = code - cfg->native_code;
7348 g_assert (cfg->code_len < cfg->code_size);
7352 #endif /* DISABLE_JIT */
7355 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7357 guchar *code = (guchar *)p;
7358 MonoMethodSignature *sig;
7360 int i, n, stack_area = 0;
7362 /* Keep this in sync with mono_arch_get_argument_info */
7364 if (enable_arguments) {
7365 /* Allocate a new area on the stack and save arguments there */
7366 sig = mono_method_signature (cfg->method);
7368 n = sig->param_count + sig->hasthis;
7370 stack_area = ALIGN_TO (n * 8, 16);
7372 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7374 for (i = 0; i < n; ++i) {
7375 inst = cfg->args [i];
7377 if (inst->opcode == OP_REGVAR)
7378 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7380 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7381 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7386 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7387 amd64_set_reg_template (code, AMD64_ARG_REG1);
7388 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7389 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7391 if (enable_arguments)
7392 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7406 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7408 guchar *code = (guchar *)p;
7409 int save_mode = SAVE_NONE;
7410 MonoMethod *method = cfg->method;
7411 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7414 switch (ret_type->type) {
7415 case MONO_TYPE_VOID:
7416 /* special case string .ctor icall */
7417 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7418 save_mode = SAVE_EAX;
7420 save_mode = SAVE_NONE;
7424 save_mode = SAVE_EAX;
7428 save_mode = SAVE_XMM;
7430 case MONO_TYPE_GENERICINST:
7431 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7432 save_mode = SAVE_EAX;
7436 case MONO_TYPE_VALUETYPE:
7437 save_mode = SAVE_STRUCT;
7440 save_mode = SAVE_EAX;
7444 /* Save the result and copy it into the proper argument register */
7445 switch (save_mode) {
7447 amd64_push_reg (code, AMD64_RAX);
7449 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7450 if (enable_arguments)
7451 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7455 if (enable_arguments)
7456 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7459 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7460 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7462 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7464 * The result is already in the proper argument register so no copying
7471 g_assert_not_reached ();
7474 /* Set %al since this is a varargs call */
7475 if (save_mode == SAVE_XMM)
7476 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7478 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7480 if (preserve_argument_registers) {
7481 for (i = 0; i < PARAM_REGS; ++i)
7482 amd64_push_reg (code, param_regs [i]);
7485 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7486 amd64_set_reg_template (code, AMD64_ARG_REG1);
7487 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7489 if (preserve_argument_registers) {
7490 for (i = PARAM_REGS - 1; i >= 0; --i)
7491 amd64_pop_reg (code, param_regs [i]);
7494 /* Restore result */
7495 switch (save_mode) {
7497 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7498 amd64_pop_reg (code, AMD64_RAX);
7504 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7505 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7506 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7511 g_assert_not_reached ();
7518 mono_arch_flush_icache (guint8 *code, gint size)
7524 mono_arch_flush_register_windows (void)
7529 mono_arch_is_inst_imm (gint64 imm)
7531 return amd64_use_imm32 (imm);
7535 * Determine whenever the trap whose info is in SIGINFO is caused by
7539 mono_arch_is_int_overflow (void *sigctx, void *info)
7546 mono_sigctx_to_monoctx (sigctx, &ctx);
7548 rip = (guint8*)ctx.gregs [AMD64_RIP];
7550 if (IS_REX (rip [0])) {
7551 reg = amd64_rex_b (rip [0]);
7557 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7559 reg += x86_modrm_rm (rip [1]);
7561 value = ctx.gregs [reg];
7571 mono_arch_get_patch_offset (guint8 *code)
7577 * \return TRUE if no sw breakpoint was present.
7579 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
7580 * breakpoints in the original code, they are removed in the copy.
7583 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7586 * If method_start is non-NULL we need to perform bound checks, since we access memory
7587 * at code - offset we could go before the start of the method and end up in a different
7588 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7591 if (!method_start || code - offset >= method_start) {
7592 memcpy (buf, code - offset, size);
7594 int diff = code - method_start;
7595 memset (buf, 0, size);
7596 memcpy (buf + offset - diff, method_start, diff + size - offset);
7602 mono_arch_get_this_arg_reg (guint8 *code)
7604 return AMD64_ARG_REG1;
7608 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7610 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7613 #define MAX_ARCH_DELEGATE_PARAMS 10
7616 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7618 guint8 *code, *start;
7619 GSList *unwind_ops = NULL;
7622 unwind_ops = mono_arch_get_cie_program ();
7625 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7627 /* Replace the this argument with the target */
7628 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7629 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7630 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7632 g_assert ((code - start) < 64);
7633 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7635 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7637 if (param_count == 0) {
7638 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7640 /* We have to shift the arguments left */
7641 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7642 for (i = 0; i < param_count; ++i) {
7645 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7647 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7649 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7653 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7655 g_assert ((code - start) < 64);
7656 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7659 mono_arch_flush_icache (start, code - start);
7662 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7664 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7665 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7669 if (mono_jit_map_is_enabled ()) {
7672 buff = (char*)"delegate_invoke_has_target";
7674 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7675 mono_emit_jit_tramp (start, code - start, buff);
7679 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7684 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7687 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7689 guint8 *code, *start;
7694 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7697 start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7699 unwind_ops = mono_arch_get_cie_program ();
7701 /* Replace the this argument with the target */
7702 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7703 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7706 /* Load the IMT reg */
7707 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7710 /* Load the vtable */
7711 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7712 amd64_jump_membase (code, AMD64_RAX, offset);
7713 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7715 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7716 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7717 g_free (tramp_name);
7723 * mono_arch_get_delegate_invoke_impls:
7725 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7729 mono_arch_get_delegate_invoke_impls (void)
7732 MonoTrampInfo *info;
7735 get_delegate_invoke_impl (&info, TRUE, 0);
7736 res = g_slist_prepend (res, info);
7738 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7739 get_delegate_invoke_impl (&info, FALSE, i);
7740 res = g_slist_prepend (res, info);
7743 for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7744 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7745 res = g_slist_prepend (res, info);
7748 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7749 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7750 res = g_slist_prepend (res, info);
7751 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7752 res = g_slist_prepend (res, info);
7759 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7761 guint8 *code, *start;
7764 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7767 /* FIXME: Support more cases */
7768 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7772 static guint8* cached = NULL;
7777 if (mono_aot_only) {
7778 start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7780 MonoTrampInfo *info;
7781 start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7782 mono_tramp_info_register (info, NULL);
7785 mono_memory_barrier ();
7789 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7790 for (i = 0; i < sig->param_count; ++i)
7791 if (!mono_is_regsize_var (sig->params [i]))
7793 if (sig->param_count > 4)
7796 code = cache [sig->param_count];
7800 if (mono_aot_only) {
7801 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7802 start = (guint8 *)mono_aot_get_trampoline (name);
7805 MonoTrampInfo *info;
7806 start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7807 mono_tramp_info_register (info, NULL);
7810 mono_memory_barrier ();
7812 cache [sig->param_count] = start;
7819 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7821 MonoTrampInfo *info;
7824 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7826 mono_tramp_info_register (info, NULL);
7831 mono_arch_finish_init (void)
7833 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7834 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7839 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7843 #define CMP_SIZE (6 + 1)
7844 #define CMP_REG_REG_SIZE (4 + 1)
7845 #define BR_SMALL_SIZE 2
7846 #define BR_LARGE_SIZE 6
7847 #define MOV_REG_IMM_SIZE 10
7848 #define MOV_REG_IMM_32BIT_SIZE 6
7849 #define JUMP_REG_SIZE (2 + 1)
7852 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7854 int i, distance = 0;
7855 for (i = start; i < target; ++i)
7856 distance += imt_entries [i]->chunk_size;
7861 * LOCKING: called with the domain lock held
7864 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7865 gpointer fail_tramp)
7869 guint8 *code, *start;
7870 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7873 for (i = 0; i < count; ++i) {
7874 MonoIMTCheckItem *item = imt_entries [i];
7875 if (item->is_equals) {
7876 if (item->check_target_idx) {
7877 if (!item->compare_done) {
7878 if (amd64_use_imm32 ((gint64)item->key))
7879 item->chunk_size += CMP_SIZE;
7881 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7883 if (item->has_target_code) {
7884 item->chunk_size += MOV_REG_IMM_SIZE;
7886 if (vtable_is_32bit)
7887 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7889 item->chunk_size += MOV_REG_IMM_SIZE;
7891 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7894 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7895 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7897 if (vtable_is_32bit)
7898 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7900 item->chunk_size += MOV_REG_IMM_SIZE;
7901 item->chunk_size += JUMP_REG_SIZE;
7902 /* with assert below:
7903 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7908 if (amd64_use_imm32 ((gint64)item->key))
7909 item->chunk_size += CMP_SIZE;
7911 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7912 item->chunk_size += BR_LARGE_SIZE;
7913 imt_entries [item->check_target_idx]->compare_done = TRUE;
7915 size += item->chunk_size;
7918 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7920 code = (guint8 *)mono_domain_code_reserve (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7923 unwind_ops = mono_arch_get_cie_program ();
7925 for (i = 0; i < count; ++i) {
7926 MonoIMTCheckItem *item = imt_entries [i];
7927 item->code_target = code;
7928 if (item->is_equals) {
7929 gboolean fail_case = !item->check_target_idx && fail_tramp;
7931 if (item->check_target_idx || fail_case) {
7932 if (!item->compare_done || fail_case) {
7933 if (amd64_use_imm32 ((gint64)item->key))
7934 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7936 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7937 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7940 item->jmp_code = code;
7941 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7942 if (item->has_target_code) {
7943 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7944 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7946 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7947 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7951 amd64_patch (item->jmp_code, code);
7952 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7953 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7954 item->jmp_code = NULL;
7957 /* enable the commented code to assert on wrong method */
7959 if (amd64_is_imm32 (item->key))
7960 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7962 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7963 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7965 item->jmp_code = code;
7966 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7967 /* See the comment below about R10 */
7968 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7969 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7970 amd64_patch (item->jmp_code, code);
7971 amd64_breakpoint (code);
7972 item->jmp_code = NULL;
7974 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7975 needs to be preserved. R10 needs
7976 to be preserved for calls which
7977 require a runtime generic context,
7978 but interface calls don't. */
7979 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7980 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7984 if (amd64_use_imm32 ((gint64)item->key))
7985 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
7987 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
7988 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7990 item->jmp_code = code;
7991 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7992 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7994 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7996 g_assert (code - item->code_target <= item->chunk_size);
7998 /* patch the branches to get to the target items */
7999 for (i = 0; i < count; ++i) {
8000 MonoIMTCheckItem *item = imt_entries [i];
8001 if (item->jmp_code) {
8002 if (item->check_target_idx) {
8003 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8009 mono_stats.imt_trampolines_size += code - start;
8010 g_assert (code - start <= size);
8011 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8013 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8015 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8021 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8023 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8027 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8029 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8033 mono_arch_get_cie_program (void)
8037 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8038 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8046 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8048 MonoInst *ins = NULL;
8051 if (cmethod->klass == mono_defaults.math_class) {
8052 if (strcmp (cmethod->name, "Sin") == 0) {
8054 } else if (strcmp (cmethod->name, "Cos") == 0) {
8056 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8058 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8062 if (opcode && fsig->param_count == 1) {
8063 MONO_INST_NEW (cfg, ins, opcode);
8064 ins->type = STACK_R8;
8065 ins->dreg = mono_alloc_freg (cfg);
8066 ins->sreg1 = args [0]->dreg;
8067 MONO_ADD_INS (cfg->cbb, ins);
8071 if (cfg->opt & MONO_OPT_CMOV) {
8072 if (strcmp (cmethod->name, "Min") == 0) {
8073 if (fsig->params [0]->type == MONO_TYPE_I4)
8075 if (fsig->params [0]->type == MONO_TYPE_U4)
8076 opcode = OP_IMIN_UN;
8077 else if (fsig->params [0]->type == MONO_TYPE_I8)
8079 else if (fsig->params [0]->type == MONO_TYPE_U8)
8080 opcode = OP_LMIN_UN;
8081 } else if (strcmp (cmethod->name, "Max") == 0) {
8082 if (fsig->params [0]->type == MONO_TYPE_I4)
8084 if (fsig->params [0]->type == MONO_TYPE_U4)
8085 opcode = OP_IMAX_UN;
8086 else if (fsig->params [0]->type == MONO_TYPE_I8)
8088 else if (fsig->params [0]->type == MONO_TYPE_U8)
8089 opcode = OP_LMAX_UN;
8093 if (opcode && fsig->param_count == 2) {
8094 MONO_INST_NEW (cfg, ins, opcode);
8095 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8096 ins->dreg = mono_alloc_ireg (cfg);
8097 ins->sreg1 = args [0]->dreg;
8098 ins->sreg2 = args [1]->dreg;
8099 MONO_ADD_INS (cfg->cbb, ins);
8103 /* OP_FREM is not IEEE compatible */
8104 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8105 MONO_INST_NEW (cfg, ins, OP_FREM);
8106 ins->inst_i0 = args [0];
8107 ins->inst_i1 = args [1];
8117 mono_arch_print_tree (MonoInst *tree, int arity)
8123 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8125 return ctx->gregs [reg];
8129 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8131 ctx->gregs [reg] = val;
8135 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8137 gpointer *sp, old_value;
8141 bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8142 sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8145 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8154 * mono_arch_emit_load_aotconst:
8156 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8157 * TARGET from the mscorlib GOT in full-aot code.
8158 * On AMD64, the result is placed into R11.
8161 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8163 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8164 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8170 * mono_arch_get_trampolines:
8172 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8176 mono_arch_get_trampolines (gboolean aot)
8178 return mono_amd64_get_exception_trampolines (aot);
8181 /* Soft Debug support */
8182 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8185 * mono_arch_set_breakpoint:
8187 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8188 * The location should contain code emitted by OP_SEQ_POINT.
8191 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8196 guint32 native_offset = ip - (guint8*)ji->code_start;
8197 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8199 g_assert (info->bp_addrs [native_offset] == 0);
8200 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8202 /* ip points to a mov r11, 0 */
8203 g_assert (code [0] == 0x41);
8204 g_assert (code [1] == 0xbb);
8205 amd64_mov_reg_imm (code, AMD64_R11, 1);
8210 * mono_arch_clear_breakpoint:
8212 * Clear the breakpoint at IP.
8215 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8220 guint32 native_offset = ip - (guint8*)ji->code_start;
8221 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8223 info->bp_addrs [native_offset] = NULL;
8225 amd64_mov_reg_imm (code, AMD64_R11, 0);
8230 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8232 /* We use soft breakpoints on amd64 */
8237 * mono_arch_skip_breakpoint:
8239 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8240 * we resume, the instruction is not executed again.
8243 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8245 g_assert_not_reached ();
8249 * mono_arch_start_single_stepping:
8251 * Start single stepping.
8254 mono_arch_start_single_stepping (void)
8256 ss_trampoline = mini_get_single_step_trampoline ();
8260 * mono_arch_stop_single_stepping:
8262 * Stop single stepping.
8265 mono_arch_stop_single_stepping (void)
8267 ss_trampoline = NULL;
8271 * mono_arch_is_single_step_event:
8273 * Return whenever the machine state in SIGCTX corresponds to a single
8277 mono_arch_is_single_step_event (void *info, void *sigctx)
8279 /* We use soft breakpoints on amd64 */
8284 * mono_arch_skip_single_step:
8286 * Modify CTX so the ip is placed after the single step trigger instruction,
8287 * we resume, the instruction is not executed again.
8290 mono_arch_skip_single_step (MonoContext *ctx)
8292 g_assert_not_reached ();
8296 * mono_arch_create_seq_point_info:
8298 * Return a pointer to a data structure which is used by the sequence
8299 * point implementation in AOTed code.
8302 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8307 // FIXME: Add a free function
8309 mono_domain_lock (domain);
8310 info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8312 mono_domain_unlock (domain);
8315 ji = mono_jit_info_table_find (domain, (char*)code);
8318 // FIXME: Optimize the size
8319 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8321 info->ss_tramp_addr = &ss_trampoline;
8323 mono_domain_lock (domain);
8324 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8326 mono_domain_unlock (domain);
8333 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8335 ext->lmf.previous_lmf = prev_lmf;
8336 /* Mark that this is a MonoLMFExt */
8337 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8338 ext->lmf.rsp = (gssize)ext;
8344 mono_arch_opcode_supported (int opcode)
8347 case OP_ATOMIC_ADD_I4:
8348 case OP_ATOMIC_ADD_I8:
8349 case OP_ATOMIC_EXCHANGE_I4:
8350 case OP_ATOMIC_EXCHANGE_I8:
8351 case OP_ATOMIC_CAS_I4:
8352 case OP_ATOMIC_CAS_I8:
8353 case OP_ATOMIC_LOAD_I1:
8354 case OP_ATOMIC_LOAD_I2:
8355 case OP_ATOMIC_LOAD_I4:
8356 case OP_ATOMIC_LOAD_I8:
8357 case OP_ATOMIC_LOAD_U1:
8358 case OP_ATOMIC_LOAD_U2:
8359 case OP_ATOMIC_LOAD_U4:
8360 case OP_ATOMIC_LOAD_U8:
8361 case OP_ATOMIC_LOAD_R4:
8362 case OP_ATOMIC_LOAD_R8:
8363 case OP_ATOMIC_STORE_I1:
8364 case OP_ATOMIC_STORE_I2:
8365 case OP_ATOMIC_STORE_I4:
8366 case OP_ATOMIC_STORE_I8:
8367 case OP_ATOMIC_STORE_U1:
8368 case OP_ATOMIC_STORE_U2:
8369 case OP_ATOMIC_STORE_U4:
8370 case OP_ATOMIC_STORE_U8:
8371 case OP_ATOMIC_STORE_R4:
8372 case OP_ATOMIC_STORE_R8:
8380 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8382 return get_call_info (mp, sig);